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radeonsi: Update buffer for other planes in si_alloc_resource

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The buffer is shared with all planes, so it needs to be updated
in all other planes. This is already done in si_texture_create_object
when creating the buffer, but it was missing when reallocating
in si_texture_invalidate_storage.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11155
Cc: mesa-stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29216>
This commit is contained in:
David Rosca
2024-05-15 12:59:42 +02:00
committed by Marge Bot
parent ec90da3c76
commit c522848d5a
1 changed files with 9 additions and 0 deletions
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src/gallium/drivers/radeonsi/si_buffer.c
+9
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@@ -176,6 +176,15 @@ bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res)
util_range_set_empty(&res->valid_buffer_range);
res->TC_L2_dirty = false;
if (res->b.b.target != PIPE_BUFFER && !(res->b.b.flags & SI_RESOURCE_AUX_PLANE)) {
/* The buffer is shared with other planes. */
struct si_resource *plane = (struct si_resource *)res->b.b.next;
for (; plane; plane = (struct si_resource *)plane->b.b.next) {
radeon_bo_reference(sscreen->ws, &plane->buf, res->buf);
plane->gpu_address = res->gpu_address;
}
}
/* Print debug information. */
if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
fprintf(stderr, "VM start=0x%" PRIX64 " end=0x%" PRIX64 " | Buffer %" PRIu64 " bytes | Flags: ",