From c522848d5afd598ac16d4dd9fdaf498111ee0d0c Mon Sep 17 00:00:00 2001 From: David Rosca Date: Wed, 15 May 2024 12:59:42 +0200 Subject: [PATCH] radeonsi: Update buffer for other planes in si_alloc_resource MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The buffer is shared with all planes, so it needs to be updated in all other planes. This is already done in si_texture_create_object when creating the buffer, but it was missing when reallocating in si_texture_invalidate_storage. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11155 Cc: mesa-stable Reviewed-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Marek Olšák Part-of: --- src/gallium/drivers/radeonsi/si_buffer.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index 91d5bb97650..c56c32266f4 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -176,6 +176,15 @@ bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res) util_range_set_empty(&res->valid_buffer_range); res->TC_L2_dirty = false; + if (res->b.b.target != PIPE_BUFFER && !(res->b.b.flags & SI_RESOURCE_AUX_PLANE)) { + /* The buffer is shared with other planes. */ + struct si_resource *plane = (struct si_resource *)res->b.b.next; + for (; plane; plane = (struct si_resource *)plane->b.b.next) { + radeon_bo_reference(sscreen->ws, &plane->buf, res->buf); + plane->gpu_address = res->gpu_address; + } + } + /* Print debug information. */ if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) { fprintf(stderr, "VM start=0x%" PRIX64 " end=0x%" PRIX64 " | Buffer %" PRIu64 " bytes | Flags: ",