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iris: Add VF_CACHE_INVALIDATE to IRIS_DOMAIN_OTHER_WRITE flush bits

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Suggested by Francisco Jerez.

Although including VF invalidation in the flush bits is strange, we
believe this is the only way to guarantee that stream output has
finished.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>
This commit is contained in:
Kenneth Graunke
2022-03-07 23:37:58 -08:00
committed by Marge Bot
parent a969ad1ddf
commit b7111f89e8
1 changed files with 4 additions and 1 deletions
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src/gallium/drivers/iris/iris_pipe_control.c
+4 -1
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@@ -196,7 +196,10 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
[IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
[IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH,
[IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_FLUSH_HDC,
[IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
/* OTHER_WRITE includes "VF Cache Invalidate" to make sure that any
* stream output writes are finished. CS stall is added implicitly.
*/
[IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_VF_CACHE_INVALIDATE,
[IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
[IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
[IRIS_DOMAIN_PULL_CONSTANT_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,