From b7111f89e8213315d4d5f66dee2551bac8af46b1 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 7 Mar 2022 23:37:58 -0800 Subject: [PATCH] iris: Add VF_CACHE_INVALIDATE to IRIS_DOMAIN_OTHER_WRITE flush bits Suggested by Francisco Jerez. Although including VF invalidation in the flush bits is strange, we believe this is the only way to guarantee that stream output has finished. Reviewed-by: Francisco Jerez Reviewed-by: Rohan Garg Part-of: --- src/gallium/drivers/iris/iris_pipe_control.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c index 95b1b5bc33b..4050f8641b0 100644 --- a/src/gallium/drivers/iris/iris_pipe_control.c +++ b/src/gallium/drivers/iris/iris_pipe_control.c @@ -196,7 +196,10 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch, [IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH, [IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH, [IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_FLUSH_HDC, - [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE, + /* OTHER_WRITE includes "VF Cache Invalidate" to make sure that any + * stream output writes are finished. CS stall is added implicitly. + */ + [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_VF_CACHE_INVALIDATE, [IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD, [IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD, [IRIS_DOMAIN_PULL_CONSTANT_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,