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brw: Assert that EOT is always SHADER_OPCODE_SEND on pre-Xe3

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We used to have other opcodes as well, but we've since transitioned
entirely to logical send lowering prior to register allocation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34040>
This commit is contained in:
Kenneth Graunke
2025-01-20 02:42:33 -08:00
committed by Marge Bot
parent 90dbbc69bb
commit b0eb90ddb1
1 changed files with 2 additions and 2 deletions
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src/intel/compiler/brw_reg_allocate.cpp
+2 -2
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@@ -630,8 +630,8 @@ brw_reg_alloc::setup_inst_interference(const brw_inst *inst)
* register that works.
*/
if (inst->eot && devinfo->ver < 30) {
const int vgrf = inst->opcode == SHADER_OPCODE_SEND ?
inst->src[2].nr : inst->src[0].nr;
assert(inst->opcode == SHADER_OPCODE_SEND);
const int vgrf = inst->src[2].nr;
const int size = DIV_ROUND_UP(fs->alloc.sizes[vgrf], reg_unit(devinfo));
int reg = BRW_MAX_GRF - size;