From b0eb90ddb1b69f8acdbc81d0669d4d8bf4dbe2e8 Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon, 20 Jan 2025 02:42:33 -0800
Subject: [PATCH] brw: Assert that EOT is always SHADER_OPCODE_SEND on pre-Xe3

We used to have other opcodes as well, but we've since transitioned
entirely to logical send lowering prior to register allocation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34040>
---
 src/intel/compiler/brw_reg_allocate.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp
index bce3c099448..6d73a3d6ee8 100644
--- a/src/intel/compiler/brw_reg_allocate.cpp
+++ b/src/intel/compiler/brw_reg_allocate.cpp
@@ -630,8 +630,8 @@ brw_reg_alloc::setup_inst_interference(const brw_inst *inst)
     * register that works.
     */
    if (inst->eot && devinfo->ver < 30) {
-      const int vgrf = inst->opcode == SHADER_OPCODE_SEND ?
-                       inst->src[2].nr : inst->src[0].nr;
+      assert(inst->opcode == SHADER_OPCODE_SEND);
+      const int vgrf = inst->src[2].nr;
       const int size = DIV_ROUND_UP(fs->alloc.sizes[vgrf], reg_unit(devinfo));
       int reg = BRW_MAX_GRF - size;