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i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.

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This gets rid of two no16() fall-backs and should allow better
scheduling of the generated IR.  There are no uses of usubBorrow() or
uaddCarry() in shader-db so no changes are expected.  However the
"arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow" and
"arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry" piglit
tests go from 40 to 28 instructions.  The reason is that the plain ADD
instruction can easily be CSE'ed with the original addition, and the
b2i negation can easily be propagated into the source modifier of
another instruction, so effectively both operations are performed with
just one instruction.

v2: Rely on carry_to_arith() and borrow_to_arith() to lower these
    (Ilia Mirkin).

Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Francisco Jerez
2015-07-09 21:42:28 +03:00
parent 3ee2daf23d
commit b00cd6e4a0
3 changed files with 12 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+4 -22
View File
@@ -835,29 +835,11 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
break;
case nir_op_uadd_carry: {
if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
case nir_op_uadd_carry:
unreachable("Should have been lowered by carry_to_arith().");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
BRW_REGISTER_TYPE_UD);
bld.ADDC(bld.null_reg_ud(), op[0], op[1]);
bld.MOV(result, fs_reg(acc));
break;
}
case nir_op_usub_borrow: {
if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
BRW_REGISTER_TYPE_UD);
bld.SUBB(bld.null_reg_ud(), op[0], op[1]);
bld.MOV(result, fs_reg(acc));
break;
}
case nir_op_usub_borrow:
unreachable("Should have been lowered by borrow_to_arith().");
case nir_op_umod:
bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
src/mesa/drivers/dri/i965/brw_shader.cpp
+3 -1
View File
@@ -259,7 +259,9 @@ process_glsl_ir(struct brw_context *brw,
EXP_TO_EXP2 |
LOG_TO_LOG2 |
bitfield_insert |
LDEXP_TO_ARITH);
LDEXP_TO_ARITH |
CARRY_TO_ARITH |
BORROW_TO_ARITH);
/* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
* if-statements need to be flattened.
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+5 -12
View File
@@ -1601,20 +1601,13 @@ vec4_visitor::visit(ir_expression *ir)
assert(ir->type->is_integer());
emit_math(SHADER_OPCODE_INT_QUOTIENT, result_dst, op[0], op[1]);
break;
case ir_binop_carry: {
struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
emit(ADDC(dst_null_ud(), op[0], op[1]));
emit(MOV(result_dst, src_reg(acc)));
break;
}
case ir_binop_borrow: {
struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
case ir_binop_carry:
unreachable("Should have been lowered by carry_to_arith().");
case ir_binop_borrow:
unreachable("Should have been lowered by borrow_to_arith().");
emit(SUBB(dst_null_ud(), op[0], op[1]));
emit(MOV(result_dst, src_reg(acc)));
break;
}
case ir_binop_mod:
/* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
assert(ir->type->is_integer());