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r600: split state emit into block specific functions

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We probably want to go finer grained eventually, but
this is a good start.
This commit is contained in:
Alex Deucher
2009-08-20 16:07:07 -04:00
parent a215da5e9c
commit ad36058e21
6 changed files with 379 additions and 320 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/r600/r600_context.c
-16
View File
@@ -247,8 +247,6 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
*/
_mesa_init_driver_functions(&functions);
r700InitChipObject(r600); /* let the eag... */
r700InitStateFuncs(&functions);
r600InitTextureFuncs(&functions);
r700InitShaderFuncs(&functions);
@@ -386,18 +384,4 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
return GL_TRUE;
}
/* Clean our own things only, radeonDestroyContext will do every thing else. */
void
r600DestroyContext (__DRIcontextPrivate * driContextPriv)
{
GET_CURRENT_CONTEXT (ctx);
context_t *context = ctx ? R700_CONTEXT(ctx) : NULL;
if (context)
FREE(context->hw.pStateList);
radeonDestroyContext(driContextPriv);
}
src/mesa/drivers/dri/r600/r600_context.h
+8 -3
View File
@@ -131,15 +131,20 @@ struct r600_context {
#define R700_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx))
#define GL_CONTEXT(context) ((GLcontext *)(context->radeon.glCtx))
extern void r600DestroyContext(__DRIcontextPrivate * driContextPriv);
extern GLboolean r600CreateContext(const __GLcontextModes * glVisual,
__DRIcontextPrivate * driContextPriv,
void *sharedContextPrivate);
#define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw))
extern GLboolean r700InitChipObject(context_t *context);
extern GLboolean r700SendContextStates(context_t *context);
extern GLboolean r700SendSPIState(context_t *context);
extern GLboolean r700SendVGTState(context_t *context);
extern GLboolean r700SendSXState(context_t *context);
extern GLboolean r700SendDBState(context_t *context);
extern GLboolean r700SendCBState(context_t *context);
extern GLboolean r700SendSUState(context_t *context);
extern GLboolean r700SendCLState(context_t *context);
extern GLboolean r700SendSCState(context_t *context);
extern GLboolean r700SendViewportState(context_t *context, int id);
extern GLboolean r700SendRenderTargetState(context_t *context, int id);
extern GLboolean r700SendTextureState(context_t *context);
src/mesa/drivers/dri/r600/r700_chip.c
+336 -280
View File
@@ -40,215 +40,6 @@
#include "radeon_mipmap_tree.h"
#define LINK_STATES(reg) \
do \
{ \
pStateListWork->puiValue = (unsigned int*)&(r700->reg); \
pStateListWork->unOffset = mm##reg - ASIC_CONTEXT_BASE_INDEX; \
pStateListWork->pNext = pStateListWork + 1; \
pStateListWork++; \
}while(0)
GLboolean r700InitChipObject(context_t *context)
{
ContextState * pStateListWork;
R700_CHIP_CONTEXT *r700 = &context->hw;
/* init state list */
r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int));
pStateListWork = r700->pStateList;
// SC
LINK_STATES(PA_SC_SCREEN_SCISSOR_TL);
LINK_STATES(PA_SC_SCREEN_SCISSOR_BR);
LINK_STATES(PA_SC_WINDOW_OFFSET);
LINK_STATES(PA_SC_WINDOW_SCISSOR_TL);
LINK_STATES(PA_SC_WINDOW_SCISSOR_BR);
LINK_STATES(PA_SC_CLIPRECT_RULE);
LINK_STATES(PA_SC_CLIPRECT_0_TL);
LINK_STATES(PA_SC_CLIPRECT_0_BR);
LINK_STATES(PA_SC_CLIPRECT_1_TL);
LINK_STATES(PA_SC_CLIPRECT_1_BR);
LINK_STATES(PA_SC_CLIPRECT_2_TL);
LINK_STATES(PA_SC_CLIPRECT_2_BR);
LINK_STATES(PA_SC_CLIPRECT_3_TL);
LINK_STATES(PA_SC_CLIPRECT_3_BR);
LINK_STATES(PA_SC_EDGERULE);
LINK_STATES(PA_SC_GENERIC_SCISSOR_TL);
LINK_STATES(PA_SC_GENERIC_SCISSOR_BR);
LINK_STATES(PA_SC_LINE_STIPPLE);
LINK_STATES(PA_SC_MPASS_PS_CNTL);
LINK_STATES(PA_SC_MODE_CNTL);
LINK_STATES(PA_SC_LINE_CNTL);
LINK_STATES(PA_SC_AA_CONFIG);
LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX);
LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX);
LINK_STATES(PA_SC_AA_MASK);
// SU
LINK_STATES(PA_SU_POINT_SIZE);
LINK_STATES(PA_SU_POINT_MINMAX);
LINK_STATES(PA_SU_LINE_CNTL);
LINK_STATES(PA_SU_SC_MODE_CNTL);
LINK_STATES(PA_SU_VTX_CNTL);
LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL);
LINK_STATES(PA_SU_POLY_OFFSET_CLAMP);
LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE);
LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET);
LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE);
LINK_STATES(PA_SU_POLY_OFFSET_BACK_OFFSET);
// CL
LINK_STATES(PA_CL_CLIP_CNTL);
LINK_STATES(PA_CL_VTE_CNTL);
LINK_STATES(PA_CL_VS_OUT_CNTL);
LINK_STATES(PA_CL_NANINF_CNTL);
LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ);
LINK_STATES(PA_CL_GB_VERT_DISC_ADJ);
LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ);
LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ);
// CB
LINK_STATES(CB_CLEAR_RED_R6XX);
LINK_STATES(CB_CLEAR_GREEN_R6XX);
LINK_STATES(CB_CLEAR_BLUE_R6XX);
LINK_STATES(CB_CLEAR_ALPHA_R6XX);
LINK_STATES(CB_TARGET_MASK);
LINK_STATES(CB_SHADER_MASK);
LINK_STATES(CB_BLEND_RED);
LINK_STATES(CB_BLEND_GREEN);
LINK_STATES(CB_BLEND_BLUE);
LINK_STATES(CB_BLEND_ALPHA);
LINK_STATES(CB_FOG_RED_R6XX);
LINK_STATES(CB_FOG_GREEN_R6XX);
LINK_STATES(CB_FOG_BLUE_R6XX);
LINK_STATES(CB_SHADER_CONTROL);
LINK_STATES(CB_COLOR_CONTROL);
LINK_STATES(CB_CLRCMP_CONTROL);
LINK_STATES(CB_CLRCMP_SRC);
LINK_STATES(CB_CLRCMP_DST);
LINK_STATES(CB_CLRCMP_MSK);
LINK_STATES(CB_BLEND_CONTROL);
//DB
LINK_STATES(DB_HTILE_DATA_BASE);
LINK_STATES(DB_STENCIL_CLEAR);
LINK_STATES(DB_DEPTH_CLEAR);
LINK_STATES(DB_STENCILREFMASK);
LINK_STATES(DB_STENCILREFMASK_BF);
LINK_STATES(DB_DEPTH_CONTROL);
LINK_STATES(DB_SHADER_CONTROL);
LINK_STATES(DB_RENDER_CONTROL);
LINK_STATES(DB_RENDER_OVERRIDE);
LINK_STATES(DB_HTILE_SURFACE);
LINK_STATES(DB_ALPHA_TO_MASK);
// SX
LINK_STATES(SX_MISC);
LINK_STATES(SX_ALPHA_TEST_CONTROL);
LINK_STATES(SX_ALPHA_REF);
// VGT
LINK_STATES(VGT_MAX_VTX_INDX);
LINK_STATES(VGT_MIN_VTX_INDX);
LINK_STATES(VGT_INDX_OFFSET);
LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX);
LINK_STATES(VGT_OUTPUT_PATH_CNTL);
LINK_STATES(VGT_HOS_CNTL);
LINK_STATES(VGT_HOS_MAX_TESS_LEVEL);
LINK_STATES(VGT_HOS_MIN_TESS_LEVEL);
LINK_STATES(VGT_HOS_REUSE_DEPTH);
LINK_STATES(VGT_GROUP_PRIM_TYPE);
LINK_STATES(VGT_GROUP_FIRST_DECR);
LINK_STATES(VGT_GROUP_DECR);
LINK_STATES(VGT_GROUP_VECT_0_CNTL);
LINK_STATES(VGT_GROUP_VECT_1_CNTL);
LINK_STATES(VGT_GROUP_VECT_0_FMT_CNTL);
LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL);
LINK_STATES(VGT_GS_MODE);
LINK_STATES(VGT_PRIMITIVEID_EN);
LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN);
LINK_STATES(VGT_INSTANCE_STEP_RATE_0);
LINK_STATES(VGT_INSTANCE_STEP_RATE_1);
LINK_STATES(VGT_STRMOUT_EN);
LINK_STATES(VGT_REUSE_OFF);
LINK_STATES(VGT_VTX_CNT_EN);
LINK_STATES(VGT_STRMOUT_BUFFER_EN);
LINK_STATES(SQ_VTX_SEMANTIC_0);
LINK_STATES(SQ_VTX_SEMANTIC_1);
LINK_STATES(SQ_VTX_SEMANTIC_2);
LINK_STATES(SQ_VTX_SEMANTIC_3);
LINK_STATES(SQ_VTX_SEMANTIC_4);
LINK_STATES(SQ_VTX_SEMANTIC_5);
LINK_STATES(SQ_VTX_SEMANTIC_6);
LINK_STATES(SQ_VTX_SEMANTIC_7);
LINK_STATES(SQ_VTX_SEMANTIC_8);
LINK_STATES(SQ_VTX_SEMANTIC_9);
LINK_STATES(SQ_VTX_SEMANTIC_10);
LINK_STATES(SQ_VTX_SEMANTIC_11);
LINK_STATES(SQ_VTX_SEMANTIC_12);
LINK_STATES(SQ_VTX_SEMANTIC_13);
LINK_STATES(SQ_VTX_SEMANTIC_14);
LINK_STATES(SQ_VTX_SEMANTIC_15);
LINK_STATES(SQ_VTX_SEMANTIC_16);
LINK_STATES(SQ_VTX_SEMANTIC_17);
LINK_STATES(SQ_VTX_SEMANTIC_18);
LINK_STATES(SQ_VTX_SEMANTIC_19);
LINK_STATES(SQ_VTX_SEMANTIC_20);
LINK_STATES(SQ_VTX_SEMANTIC_21);
LINK_STATES(SQ_VTX_SEMANTIC_22);
LINK_STATES(SQ_VTX_SEMANTIC_23);
LINK_STATES(SQ_VTX_SEMANTIC_24);
LINK_STATES(SQ_VTX_SEMANTIC_25);
LINK_STATES(SQ_VTX_SEMANTIC_26);
LINK_STATES(SQ_VTX_SEMANTIC_27);
LINK_STATES(SQ_VTX_SEMANTIC_28);
LINK_STATES(SQ_VTX_SEMANTIC_29);
LINK_STATES(SQ_VTX_SEMANTIC_30);
LINK_STATES(SQ_VTX_SEMANTIC_31);
// SPI
LINK_STATES(SPI_VS_OUT_ID_0);
LINK_STATES(SPI_VS_OUT_ID_1);
LINK_STATES(SPI_VS_OUT_ID_2);
LINK_STATES(SPI_VS_OUT_ID_3);
LINK_STATES(SPI_VS_OUT_ID_4);
LINK_STATES(SPI_VS_OUT_ID_5);
LINK_STATES(SPI_VS_OUT_ID_6);
LINK_STATES(SPI_VS_OUT_ID_7);
LINK_STATES(SPI_VS_OUT_ID_8);
LINK_STATES(SPI_VS_OUT_ID_9);
LINK_STATES(SPI_VS_OUT_CONFIG);
LINK_STATES(SPI_THREAD_GROUPING);
LINK_STATES(SPI_PS_IN_CONTROL_0);
LINK_STATES(SPI_PS_IN_CONTROL_1);
LINK_STATES(SPI_INTERP_CONTROL_0);
LINK_STATES(SPI_INPUT_Z);
LINK_STATES(SPI_FOG_CNTL);
LINK_STATES(SPI_FOG_FUNC_SCALE);
LINK_STATES(SPI_FOG_FUNC_BIAS);
// SQ
LINK_STATES(SQ_ESGS_RING_ITEMSIZE);
LINK_STATES(SQ_GSVS_RING_ITEMSIZE);
LINK_STATES(SQ_ESTMP_RING_ITEMSIZE);
LINK_STATES(SQ_GSTMP_RING_ITEMSIZE);
LINK_STATES(SQ_VSTMP_RING_ITEMSIZE);
LINK_STATES(SQ_PSTMP_RING_ITEMSIZE);
LINK_STATES(SQ_FBUF_RING_ITEMSIZE);
LINK_STATES(SQ_REDUC_RING_ITEMSIZE);
//LINK_STATES(SQ_GS_VERT_ITEMSIZE);
pStateListWork->puiValue = (unsigned int*)&(r700->SQ_GS_VERT_ITEMSIZE);
pStateListWork->unOffset = mmSQ_GS_VERT_ITEMSIZE - ASIC_CONTEXT_BASE_INDEX;
pStateListWork->pNext = NULL; /* END OF STATE LIST */
return GL_TRUE;
}
GLboolean r700SendTextureState(context_t *context)
{
unsigned int i;
@@ -429,74 +220,6 @@ int r700SetupStreams(GLcontext * ctx)
return R600_FALLBACK_NONE;
}
GLboolean r700SendContextStates(context_t *context)
{
BATCH_LOCALS(&context->radeon);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
ContextState * pState = r700->pStateList;
ContextState * pInit;
unsigned int toSend;
unsigned int ui;
while(NULL != pState)
{
toSend = 1;
pInit = pState;
while(NULL != pState->pNext)
{
if ((pState->pNext->unOffset - pState->unOffset) > 1)
{
break;
}
else
{
pState = pState->pNext;
toSend++;
}
}
pState = pState->pNext;
BEGIN_BATCH_NO_AUTOSTATE(toSend + 2);
R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend);
for(ui=0; ui<toSend; ui++)
{
R600_OUT_BATCH(*(pInit->puiValue));
pInit = pInit->pNext;
};
END_BATCH();
};
/* todo:
* - split this into a separate function?
* - only emit the ones we use
*/
BEGIN_BATCH_NO_AUTOSTATE(2 + R700_MAX_SHADER_EXPORTS);
R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
END_BATCH();
if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
if (r700->render_target[ui].enabled) {
BEGIN_BATCH_NO_AUTOSTATE(3);
R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
END_BATCH();
}
}
}
COMMIT_BATCH();
return GL_TRUE;
}
GLboolean r700SendDepthTargetState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
@@ -733,7 +456,7 @@ GLboolean r700SendSQConfig(context_t *context)
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(8);
BEGIN_BATCH_NO_AUTOSTATE(34);
R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
@@ -741,14 +464,23 @@ GLboolean r700SendSQConfig(context_t *context)
R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(15);
R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
END_BATCH();
COMMIT_BATCH();
@@ -778,3 +510,327 @@ GLboolean r700SendUCPState(context_t *context)
return GL_TRUE;
}
GLboolean r700SendSPIState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
unsigned int ui;
BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
END_BATCH();
COMMIT_BATCH();
return GL_TRUE;
}
GLboolean r700SendVGTState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(41);
R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
END_BATCH();
COMMIT_BATCH();
return GL_TRUE;
}
GLboolean r700SendSXState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(9);
R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
END_BATCH();
COMMIT_BATCH();
return GL_TRUE;
}
GLboolean r700SendDBState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(27);
R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All);
R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
END_BATCH();
COMMIT_BATCH();
return GL_TRUE;
}
GLboolean r700SendCBState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
unsigned int ui;
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
BEGIN_BATCH_NO_AUTOSTATE(14);
R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
/* R600 does not have per-MRT blend */
R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
END_BATCH();
}
BEGIN_BATCH_NO_AUTOSTATE(22);
R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
END_BATCH();
if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
if (r700->render_target[ui].enabled) {
BEGIN_BATCH_NO_AUTOSTATE(3);
R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
END_BATCH();
}
}
}
COMMIT_BATCH();
return GL_TRUE;
}
GLboolean r700SendSUState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(19);
R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
END_BATCH();
COMMIT_BATCH();
return GL_TRUE;
}
GLboolean r700SendCLState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(18);
R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
END_BATCH();
COMMIT_BATCH();
return GL_TRUE;
}
// XXX need to split this up
GLboolean r700SendSCState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(47);
R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 13);
R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
R600_OUT_BATCH(r700->PA_SC_EDGERULE.u32All);
R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
END_BATCH();
COMMIT_BATCH();
return GL_TRUE;
}
src/mesa/drivers/dri/r600/r700_chip.h
+26 -19
View File
@@ -188,6 +188,7 @@ typedef struct _RENDER_TARGET_STATE_STRUCT
union UINT_FLOAT CB_COLOR0_MASK; /* 0xA040 */
union UINT_FLOAT CB_BLEND0_CONTROL; /* 0xA1E0 */
GLboolean enabled;
GLboolean dirty;
} RENDER_TARGET_STATE_STRUCT;
typedef struct _VIEWPORT_STATE_STRUCT
@@ -203,6 +204,7 @@ typedef struct _VIEWPORT_STATE_STRUCT
union UINT_FLOAT PA_CL_VPORT_ZSCALE; /* 0xA113 */
union UINT_FLOAT PA_CL_VPORT_ZOFFSET; /* 0xA114 */
GLboolean enabled;
GLboolean dirty;
} VIEWPORT_STATE_STRUCT;
typedef struct _UCP_STATE_STRUCT
@@ -212,6 +214,7 @@ typedef struct _UCP_STATE_STRUCT
union UINT_FLOAT PA_CL_UCP_0_Z;
union UINT_FLOAT PA_CL_UCP_0_W;
GLboolean enabled;
GLboolean dirty;
} UCP_STATE_STRUCT;
typedef struct _PS_STATE_STRUCT
@@ -220,6 +223,7 @@ typedef struct _PS_STATE_STRUCT
union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */
union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */
union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */
GLboolean dirty;
} PS_STATE_STRUCT;
typedef struct _VS_STATE_STRUCT
@@ -227,6 +231,7 @@ typedef struct _VS_STATE_STRUCT
union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */
union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */
union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */
GLboolean dirty;
} VS_STATE_STRUCT;
typedef struct _GS_STATE_STRUCT
@@ -234,6 +239,7 @@ typedef struct _GS_STATE_STRUCT
union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */
union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */
union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */
GLboolean dirty;
} GS_STATE_STRUCT;
typedef struct _ES_STATE_STRUCT
@@ -241,6 +247,7 @@ typedef struct _ES_STATE_STRUCT
union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */
union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */
union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */
GLboolean dirty;
} ES_STATE_STRUCT;
typedef struct _FS_STATE_STRUCT
@@ -248,6 +255,7 @@ typedef struct _FS_STATE_STRUCT
union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */
union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */
union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */
GLboolean dirty;
} FS_STATE_STRUCT;
typedef struct _SQ_CONFIG_STRUCT
@@ -260,22 +268,8 @@ typedef struct _SQ_CONFIG_STRUCT
union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2 ; /* 0x2305 */
} SQ_CONFIG_STRUCT;
typedef struct ContextState
{
unsigned int * puiValue;
unsigned int unOffset;
struct ContextState * pNext;
} ContextState;
typedef struct _R700_CHIP_CONTEXT
{
// misc
union UINT_FLOAT TA_CNTL_AUX ; /* 0x2542 */
union UINT_FLOAT VC_ENHANCE ; /* 0x25C5 */
union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; /* 0x2363 */
union UINT_FLOAT DB_DEBUG ; /* 0x260C */
union UINT_FLOAT DB_WATERMARKS ; /* 0x260E */
// DB
union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */
union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */
@@ -292,6 +286,7 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */
union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */
union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */
GLboolean db_dirty;
// SC
union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */
@@ -311,6 +306,8 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */
union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */
union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */
GLboolean scissor_dirty;
union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */
union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */
union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */
@@ -319,6 +316,7 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */
union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */
GLboolean sc_dirty;
// CL
union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */
@@ -329,6 +327,7 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */
union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */
union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */
GLboolean cl_dirty;
// SU
union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */
@@ -342,6 +341,7 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */
union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */
union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */
GLboolean su_dirty;
VIEWPORT_STATE_STRUCT viewport[R700_MAX_VIEWPORTS];
UCP_STATE_STRUCT ucp[R700_MAX_UCP];
@@ -367,12 +367,14 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */
union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */
union UINT_FLOAT CB_BLEND_CONTROL ; /* 0xABD0 */
GLboolean cb_dirty;
RENDER_TARGET_STATE_STRUCT render_target[R700_MAX_RENDER_TARGETS];
// SX
union UINT_FLOAT SX_MISC ; /* 0xA0D4 */
union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */
union UINT_FLOAT SX_ALPHA_REF ; /* 0xA10E */
GLboolean sx_dirty;
// VGT
union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */
@@ -400,6 +402,7 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */
union UINT_FLOAT VGT_VTX_CNT_EN ; /* 0xA2AE */
union UINT_FLOAT VGT_STRMOUT_BUFFER_EN ; /* 0xA2C8 */
GLboolean vgt_dirty;
// SPI
union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */
@@ -454,8 +457,8 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT SQ_VTX_SEMANTIC_29 ; /* 0xA0FD */
union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */
union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */
union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
GLboolean spi_dirty;
// shaders
PS_STATE_STRUCT ps;
@@ -466,7 +469,12 @@ typedef struct _R700_CHIP_CONTEXT
// SQ CONFIG
SQ_CONFIG_STRUCT sq_config;
// misc
union UINT_FLOAT TA_CNTL_AUX ; /* 0x2542 */
union UINT_FLOAT VC_ENHANCE ; /* 0x25C5 */
union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; /* 0x2363 */
union UINT_FLOAT DB_DEBUG ; /* 0x260C */
union UINT_FLOAT DB_WATERMARKS ; /* 0x260E */
// SQ
union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */
union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */
@@ -477,8 +485,7 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */
union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */
ContextState* pStateList;
GLboolean sq_dirty;
radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS];
src/mesa/drivers/dri/r600/r700_render.c
+8 -1
View File
@@ -345,7 +345,14 @@ void r700EmitState(GLcontext * ctx)
r700SendSQConfig(context);
r700SendUCPState(context);
r700SendContextStates(context);
r700SendSCState(context);
r700SendSUState(context);
r700SendCLState(context);
r700SendCBState(context);
r700SendDBState(context);
r700SendSXState(context);
r700SendVGTState(context);
r700SendSPIState(context);
r700SendViewportState(context, 0);
r700SendRenderTargetState(context, 0);
r700SendDepthTargetState(context);
src/mesa/drivers/dri/radeon/radeon_screen.c
+1 -1
View File
@@ -1797,7 +1797,7 @@ const struct __DriverAPIRec driDriverAPI = {
.DestroyContext = r200DestroyContext,
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
.CreateContext = r600CreateContext,
.DestroyContext = r600DestroyContext,
.DestroyContext = radeonDestroyContext,
#else
.CreateContext = radeonCreateContext,
.DestroyContext = radeonDestroyContext,