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amd,radv,radeonsi: move GFX12 push SH REGS helpers to common code

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38000>
This commit is contained in:
Samuel Pitoiset
2025-10-22 16:16:53 +02:00
committed by Marge Bot
parent bddd7919d3
commit a31d3c764c
3 changed files with 29 additions and 29 deletions
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24
src/amd/common/ac_cmdbuf.h
View File

@@ -199,6 +199,30 @@ struct ac_buffered_sh_regs {
#define ac_gfx12_end_context_regs() __ac_gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS)
/* GFX12 generic packet building helpers for buffered registers. */
#define __ac_gfx12_push_reg(buf_regs, reg, value, base_offset) \
do { \
unsigned __i = buf_regs.num++; \
assert(__i < ARRAY_SIZE(buf_regs.gfx12.regs)); \
buf_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \
buf_regs.gfx12.regs[__i].reg_value = value; \
} while (0)
#define ac_gfx12_push_sh_reg(buf_regs, reg, value) \
__ac_gfx12_push_reg(buf_regs, reg, value, SI_SH_REG_OFFSET)
#define ac_gfx12_push_32bit_pointer(buf_regs, sh_offset, va, info) \
do { \
assert((va) == 0 || ((va) >> 32) == (info)->address32_hi); \
ac_gfx12_push_sh_reg(buf_regs, sh_offset, va); \
} while (0)
#define ac_gfx12_push_64bit_pointer(buf_regs, sh_offset, va) \
do { \
ac_gfx12_push_sh_reg(buf_regs, sh_offset, va); \
ac_gfx12_push_sh_reg(buf_regs, sh_offset + 4, va >> 32); \
} while (0)
struct ac_preamble_state {
uint64_t border_color_va;

22
src/amd/vulkan/radv_cs.h
View File

@@ -236,15 +236,6 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
} \
} while (0)
/* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */
#define __gfx12_push_reg(reg, value, base_offset) \
do { \
unsigned __i = __rcs->buffered_sh_regs.num++; \
assert(__i < ARRAY_SIZE(__rcs->buffered_sh_regs.gfx12.regs)); \
__rcs->buffered_sh_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \
__rcs->buffered_sh_regs.gfx12.regs[__i].reg_value = value; \
} while (0)
/* GFX12 packet building helpers for PAIRS packets. */
#define gfx12_begin_context_regs() ac_gfx12_begin_context_regs()
@@ -258,19 +249,12 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
#define gfx12_end_context_regs() ac_gfx12_end_context_regs()
/* GFX12 packet building helpers for buffered registers. */
#define gfx12_push_sh_reg(reg, value) __gfx12_push_reg(reg, value, SI_SH_REG_OFFSET)
#define gfx12_push_sh_reg(reg, value) ac_gfx12_push_sh_reg(__rcs->buffered_sh_regs, reg, value)
#define gfx12_push_32bit_pointer(sh_offset, va, info) \
do { \
assert((va) == 0 || ((va) >> 32) == (info)->address32_hi); \
gfx12_push_sh_reg(sh_offset, va); \
} while (0)
ac_gfx12_push_32bit_pointer(__rcs->buffered_sh_regs, sh_offset, va, info)
#define gfx12_push_64bit_pointer(sh_offset, va) \
do { \
gfx12_push_sh_reg(sh_offset, va); \
gfx12_push_sh_reg(sh_offset + 4, va >> 32); \
} while (0)
#define gfx12_push_64bit_pointer(sh_offset, va) ac_gfx12_push_64bit_pointer(__rcs->buffered_sh_regs, sh_offset, va)
ALWAYS_INLINE static void
radv_gfx12_emit_buffered_regs(struct radv_device *device, struct radv_cmd_stream *cs)

12
src/gallium/drivers/radeonsi/si_build_pm4.h
View File

@@ -420,14 +420,6 @@
} \
} while (0)
/* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */
#define gfx12_push_reg(reg, value, base_offset, type) do { \
unsigned __i = sctx->buffered_##type##_regs.num++; \
assert(__i < ARRAY_SIZE(sctx->buffered_##type##_regs.gfx12.regs)); \
sctx->buffered_##type##_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \
sctx->buffered_##type##_regs.gfx12.regs[__i].reg_value = value; \
} while (0)
#define gfx12_opt_push_reg(reg, reg_enum, value, type) do { \
unsigned __value = value; \
unsigned __reg_enum = reg_enum; \
@@ -457,10 +449,10 @@
/* GFX12 packet building helpers for buffered registers. */
#define gfx12_push_gfx_sh_reg(reg, value) \
gfx12_push_reg(reg, value, SI_SH_REG_OFFSET, gfx_sh)
ac_gfx12_push_sh_reg(sctx->buffered_gfx_sh_regs, reg, value)
#define gfx12_push_compute_sh_reg(reg, value) \
gfx12_push_reg(reg, value, SI_SH_REG_OFFSET, compute_sh)
ac_gfx12_push_sh_reg(sctx->buffered_compute_sh_regs, reg, value)
#define gfx12_opt_push_gfx_sh_reg(reg, reg_enum, value) \
gfx12_opt_push_reg(reg, reg_enum, value, gfx_sh)