From a31d3c764cd63897ab47031ab1634d62a979dfb9 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 22 Oct 2025 16:16:53 +0200 Subject: [PATCH] amd,radv,radeonsi: move GFX12 push SH REGS helpers to common code Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_cmdbuf.h | 24 +++++++++++++++++++++ src/amd/vulkan/radv_cs.h | 22 +++---------------- src/gallium/drivers/radeonsi/si_build_pm4.h | 12 ++--------- 3 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index 35eb7254837..2fd5b4ff1de 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -199,6 +199,30 @@ struct ac_buffered_sh_regs { #define ac_gfx12_end_context_regs() __ac_gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS) +/* GFX12 generic packet building helpers for buffered registers. */ +#define __ac_gfx12_push_reg(buf_regs, reg, value, base_offset) \ + do { \ + unsigned __i = buf_regs.num++; \ + assert(__i < ARRAY_SIZE(buf_regs.gfx12.regs)); \ + buf_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \ + buf_regs.gfx12.regs[__i].reg_value = value; \ + } while (0) + +#define ac_gfx12_push_sh_reg(buf_regs, reg, value) \ + __ac_gfx12_push_reg(buf_regs, reg, value, SI_SH_REG_OFFSET) + +#define ac_gfx12_push_32bit_pointer(buf_regs, sh_offset, va, info) \ + do { \ + assert((va) == 0 || ((va) >> 32) == (info)->address32_hi); \ + ac_gfx12_push_sh_reg(buf_regs, sh_offset, va); \ + } while (0) + +#define ac_gfx12_push_64bit_pointer(buf_regs, sh_offset, va) \ + do { \ + ac_gfx12_push_sh_reg(buf_regs, sh_offset, va); \ + ac_gfx12_push_sh_reg(buf_regs, sh_offset + 4, va >> 32); \ + } while (0) + struct ac_preamble_state { uint64_t border_color_va; diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 447359065cb..e6d093d69d1 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -236,15 +236,6 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need } \ } while (0) -/* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */ -#define __gfx12_push_reg(reg, value, base_offset) \ - do { \ - unsigned __i = __rcs->buffered_sh_regs.num++; \ - assert(__i < ARRAY_SIZE(__rcs->buffered_sh_regs.gfx12.regs)); \ - __rcs->buffered_sh_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \ - __rcs->buffered_sh_regs.gfx12.regs[__i].reg_value = value; \ - } while (0) - /* GFX12 packet building helpers for PAIRS packets. */ #define gfx12_begin_context_regs() ac_gfx12_begin_context_regs() @@ -258,19 +249,12 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need #define gfx12_end_context_regs() ac_gfx12_end_context_regs() /* GFX12 packet building helpers for buffered registers. */ -#define gfx12_push_sh_reg(reg, value) __gfx12_push_reg(reg, value, SI_SH_REG_OFFSET) +#define gfx12_push_sh_reg(reg, value) ac_gfx12_push_sh_reg(__rcs->buffered_sh_regs, reg, value) #define gfx12_push_32bit_pointer(sh_offset, va, info) \ - do { \ - assert((va) == 0 || ((va) >> 32) == (info)->address32_hi); \ - gfx12_push_sh_reg(sh_offset, va); \ - } while (0) + ac_gfx12_push_32bit_pointer(__rcs->buffered_sh_regs, sh_offset, va, info) -#define gfx12_push_64bit_pointer(sh_offset, va) \ - do { \ - gfx12_push_sh_reg(sh_offset, va); \ - gfx12_push_sh_reg(sh_offset + 4, va >> 32); \ - } while (0) +#define gfx12_push_64bit_pointer(sh_offset, va) ac_gfx12_push_64bit_pointer(__rcs->buffered_sh_regs, sh_offset, va) ALWAYS_INLINE static void radv_gfx12_emit_buffered_regs(struct radv_device *device, struct radv_cmd_stream *cs) diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index b37d1449dd9..6ea9b9fb55c 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -420,14 +420,6 @@ } \ } while (0) -/* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */ -#define gfx12_push_reg(reg, value, base_offset, type) do { \ - unsigned __i = sctx->buffered_##type##_regs.num++; \ - assert(__i < ARRAY_SIZE(sctx->buffered_##type##_regs.gfx12.regs)); \ - sctx->buffered_##type##_regs.gfx12.regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \ - sctx->buffered_##type##_regs.gfx12.regs[__i].reg_value = value; \ -} while (0) - #define gfx12_opt_push_reg(reg, reg_enum, value, type) do { \ unsigned __value = value; \ unsigned __reg_enum = reg_enum; \ @@ -457,10 +449,10 @@ /* GFX12 packet building helpers for buffered registers. */ #define gfx12_push_gfx_sh_reg(reg, value) \ - gfx12_push_reg(reg, value, SI_SH_REG_OFFSET, gfx_sh) + ac_gfx12_push_sh_reg(sctx->buffered_gfx_sh_regs, reg, value) #define gfx12_push_compute_sh_reg(reg, value) \ - gfx12_push_reg(reg, value, SI_SH_REG_OFFSET, compute_sh) + ac_gfx12_push_sh_reg(sctx->buffered_compute_sh_regs, reg, value) #define gfx12_opt_push_gfx_sh_reg(reg, reg_enum, value) \ gfx12_opt_push_reg(reg, reg_enum, value, gfx_sh)