ir3: Drop old comment about ldg vectorization limitation.

We've looked at it again, and concluded that there's just no way that LDG
crossing a boundary could be OK in the components-are-read case but bad in
the components-are-not-read case, and this must have been papering over
something else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38704>

src/freedreno/ir3/ir3_nir_lower_tess.c

@@ -569,11 +569,6 @@ lower_tess_ctrl_block(nir_block *block, nir_builder *b, struct state *state)
 
          nir_def *address, *offset;
 
-         /* note if vectorization of the tess level loads ever happens:
-          * "ldg" across 16-byte boundaries can behave incorrectly if results
-          * are never used. most likely some issue with (sy) not properly
-          * syncing with values coming from a second memory transaction.
-          */
          gl_varying_slot location = nir_intrinsic_io_semantics(intr).location;
          if (is_tess_levels(location)) {
             assert(intr->def.num_components == 1);
@@ -759,11 +754,6 @@ lower_tess_eval_block(nir_block *block, nir_builder *b, struct state *state)
 
          nir_def *address, *offset;
 
-         /* note if vectorization of the tess level loads ever happens:
-          * "ldg" across 16-byte boundaries can behave incorrectly if results
-          * are never used. most likely some issue with (sy) not properly
-          * syncing with values coming from a second memory transaction.
-          */
          gl_varying_slot location = nir_intrinsic_io_semantics(intr).location;
          if (is_tess_levels(location)) {
             assert(intr->def.num_components == 1);