From 9e145f33cb080e326e0dbded2ab8c6b97473a6cb Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Wed, 3 Dec 2025 14:27:12 -0800 Subject: [PATCH] ir3: Drop old comment about ldg vectorization limitation. We've looked at it again, and concluded that there's just no way that LDG crossing a boundary could be OK in the components-are-read case but bad in the components-are-not-read case, and this must have been papering over something else. Part-of: --- src/freedreno/ir3/ir3_nir_lower_tess.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/freedreno/ir3/ir3_nir_lower_tess.c b/src/freedreno/ir3/ir3_nir_lower_tess.c index c7e7165cc62..5e3c706079d 100644 --- a/src/freedreno/ir3/ir3_nir_lower_tess.c +++ b/src/freedreno/ir3/ir3_nir_lower_tess.c @@ -569,11 +569,6 @@ lower_tess_ctrl_block(nir_block *block, nir_builder *b, struct state *state) nir_def *address, *offset; - /* note if vectorization of the tess level loads ever happens: - * "ldg" across 16-byte boundaries can behave incorrectly if results - * are never used. most likely some issue with (sy) not properly - * syncing with values coming from a second memory transaction. - */ gl_varying_slot location = nir_intrinsic_io_semantics(intr).location; if (is_tess_levels(location)) { assert(intr->def.num_components == 1); @@ -759,11 +754,6 @@ lower_tess_eval_block(nir_block *block, nir_builder *b, struct state *state) nir_def *address, *offset; - /* note if vectorization of the tess level loads ever happens: - * "ldg" across 16-byte boundaries can behave incorrectly if results - * are never used. most likely some issue with (sy) not properly - * syncing with values coming from a second memory transaction. - */ gl_varying_slot location = nir_intrinsic_io_semantics(intr).location; if (is_tess_levels(location)) { assert(intr->def.num_components == 1);