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r600c: add OQ support for evergreen

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This commit is contained in:
Alex Deucher
2010-09-10 13:26:10 -04:00
parent 7ffc5d7c2e
commit 9cced19125
3 changed files with 55 additions and 16 deletions
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src/mesa/drivers/dri/r600/evergreen_chip.c
+43 -4
View File
@@ -60,7 +60,46 @@ do { \
insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
} while (0)
/*
static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = radeon->query.current;
int count;
if (!query || query->emitted_begin)
count = 0;
else
count = atom->cmd_size;
radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
return count;
}
static void evergreenSendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = radeon->query.current;
BATCH_LOCALS(radeon);
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
/* clear the buffer */
radeon_bo_map(query->bo, GL_FALSE);
memset(query->bo->ptr, 0, 8 * 2 * sizeof(uint64_t)); /* 8 DBs, 2 qwords each */
radeon_bo_unmap(query->bo);
radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
query->bo,
0, RADEON_GEM_DOMAIN_GTT);
BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
R600_OUT_BATCH(0x00000000);
R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
END_BATCH();
query->emitted_begin = GL_TRUE;
}
static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
{
radeon->query.queryobj.cmd_size = (SZ);
@@ -69,11 +108,11 @@ static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
radeon->query.queryobj.idx = 0;
radeon->query.queryobj.check = check_queryobj;
radeon->query.queryobj.dirty = GL_FALSE;
radeon->query.queryobj.emit = r700SendQueryBegin;
radeon->query.queryobj.emit = evergreenSendQueryBegin;
radeon->hw.max_state_size += (SZ);
insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
}
*/
static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
{
@@ -1511,7 +1550,7 @@ void evergreenInitAtoms(context_t *context)
EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
EVERGREEN_ALLOC_STATE(timestamp, always, 3, evergreenSendTIMESTAMP);
//evergreen_init_query_stateobj(&context->radeon, 6 * 2);
evergreen_init_query_stateobj(&context->radeon, 6 * 2);
context->radeon.hw.is_dirty = GL_TRUE;
context->radeon.hw.all_dirty = GL_TRUE;
src/mesa/drivers/dri/r600/evergreen_context.c
+11 -11
View File
@@ -36,6 +36,7 @@
#include "evergreen_context.h"
#include "evergreen_state.h"
#include "evergreen_blit.h"
#include "r600_cmdbuf.h"
static void evergreen_get_lock(radeonContextPtr rmesa)
{
@@ -70,20 +71,19 @@ static void evergreen_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
static void evergreen_emit_query_finish(radeonContextPtr radeon)
{
//TODO apr.01
//context_t *context = (context_t*) radeon;
//BATCH_LOCALS(&context->radeon);
context_t *context = (context_t*) radeon;
BATCH_LOCALS(&context->radeon);
struct radeon_query_object *query = radeon->query.current;
//BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
//R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
//R600_OUT_BATCH(ZPASS_DONE);
//R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
//R600_OUT_BATCH(0x00000000);
//R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
//END_BATCH();
//assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
R600_OUT_BATCH(0x00000000);
R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
END_BATCH();
assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
query->emitted_begin = GL_FALSE;
}
src/mesa/drivers/dri/radeon/radeon_queryobj.c
+1 -1
View File
@@ -56,7 +56,7 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q)
* hw writes zpass end counts to qwords 1, 3, 5, 7.
* then we substract. MSB is the valid bit.
*/
for (i = 0; i < 16; i += 4) {
for (i = 0; i < 32; i += 4) {
uint64_t start = (uint64_t)LE32_TO_CPU(result[i]) |
(uint64_t)LE32_TO_CPU(result[i + 1]) << 32;
uint64_t end = (uint64_t)LE32_TO_CPU(result[i + 2]) |