r600c: oq updates
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@@ -105,6 +105,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define R600_IT_ME_INITIALIZE 0x00004400
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#define R600_IT_COND_WRITE 0x00004500
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#define R600_IT_EVENT_WRITE 0x00004600
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# define R600_EVENT_TYPE(x) ((x) << 0)
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# define R600_EVENT_INDEX(x) ((x) << 8)
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#define R600_IT_EVENT_WRITE_EOP 0x00004700
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#define R600_IT_ONE_REG_WRITE 0x00005700
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#define R600_IT_SET_CONFIG_REG 0x00006800
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@@ -228,7 +228,7 @@ static void r600_emit_query_finish(radeonContextPtr radeon)
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BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
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R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
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R600_OUT_BATCH(ZPASS_DONE);
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R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
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R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
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R600_OUT_BATCH(0x00000000);
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R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
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@@ -1416,7 +1416,7 @@ static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
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BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
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R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
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R600_OUT_BATCH(ZPASS_DONE);
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R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
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R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
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R600_OUT_BATCH(0x00000000);
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R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
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