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intel/compiler: Pack LOD/bias and array index on TG4 messages

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Bspec: 56996

Programming note:
When doing cube arrays on gather4_l and gather4_b with SIMD16 or
SIMD32 the AI parameters is combined with the LOD/bias parameter on
the 9 LSBs.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>
This commit is contained in:
Sagar Ghuge
2024-02-09 10:27:59 -08:00
committed by Marge Bot
parent b34b2bdff3
commit 9b37b3ba73
1 changed files with 1 additions and 0 deletions
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src/intel/compiler/intel_nir_lower_texture.c
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@@ -109,6 +109,7 @@ intel_nir_lower_texture_instr(nir_builder *b, nir_instr *instr, void *cb_data)
switch (tex->op) {
case nir_texop_txl:
case nir_texop_txb:
case nir_texop_tg4:
if (tex->is_array &&
tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
opts->combined_lod_and_array_index) {