From 9b37b3ba730500877ef33fdf05f74e94ba43b890 Mon Sep 17 00:00:00 2001
From: Sagar Ghuge <sagar.ghuge@intel.com>
Date: Fri, 9 Feb 2024 10:27:59 -0800
Subject: [PATCH] intel/compiler: Pack LOD/bias and array index on TG4 messages

Bspec: 56996

Programming note:
When doing cube arrays on gather4_l and gather4_b with SIMD16 or
SIMD32 the AI parameters is combined with the LOD/bias parameter on
the 9 LSBs.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>
---
 src/intel/compiler/intel_nir_lower_texture.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/intel_nir_lower_texture.c b/src/intel/compiler/intel_nir_lower_texture.c
index 3286ef0454f..9b3a79052ee 100644
--- a/src/intel/compiler/intel_nir_lower_texture.c
+++ b/src/intel/compiler/intel_nir_lower_texture.c
@@ -109,6 +109,7 @@ intel_nir_lower_texture_instr(nir_builder *b, nir_instr *instr, void *cb_data)
    switch (tex->op) {
    case nir_texop_txl:
    case nir_texop_txb:
+   case nir_texop_tg4:
       if (tex->is_array &&
           tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
           opts->combined_lod_and_array_index) {