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radv: add missing L2 invalidate cache flush for non-coherent images

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Images aren't always coherent with L2 and AMD generations have
different rules, see radv_image_is_l2_coherent() for the full picture.

This fixes a rendering issue on GFX9 because depth/stencil images
aren't coherent, but this also affects color images.

This also fixes a cache coherency issue with an ongoing extension.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12274
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36815>
This commit is contained in:
Samuel Pitoiset
2025-08-18 14:15:53 +02:00
committed by Marge Bot
parent 0bfa01e466
commit 99b287bde5
1 changed files with 4 additions and 0 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+4
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@@ -6439,12 +6439,16 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2
if (src_flags & VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT) {
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
if (!image_is_coherent)
flush_bits |= RADV_CMD_FLAG_INV_L2;
if (has_CB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
if (src_flags & VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT) {
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
if (!image_is_coherent)
flush_bits |= RADV_CMD_FLAG_INV_L2;
if (has_DB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
}