From 99b287bde583906280e721569ddfa46c71060314 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 18 Aug 2025 14:15:53 +0200 Subject: [PATCH] radv: add missing L2 invalidate cache flush for non-coherent images Images aren't always coherent with L2 and AMD generations have different rules, see radv_image_is_l2_coherent() for the full picture. This fixes a rendering issue on GFX9 because depth/stencil images aren't coherent, but this also affects color images. This also fixes a cache coherency issue with an ongoing extension. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12274 Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index ae370fcdc7f..662c7e3c899 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6439,12 +6439,16 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 if (src_flags & VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT) { flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; + if (!image_is_coherent) + flush_bits |= RADV_CMD_FLAG_INV_L2; if (has_CB_meta) flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; } if (src_flags & VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT) { flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB; + if (!image_is_coherent) + flush_bits |= RADV_CMD_FLAG_INV_L2; if (has_DB_meta) flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; }