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freedreno/a750: Fix typo in recent magic regs change

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Caused GPU hangs.

Fixes: a84069cff4 ("freedreno/registers: De-open-code some offsets")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37079>
This commit is contained in:
Danylo Piliaiev
2025-08-29 12:31:28 +02:00
committed by Marge Bot
parent 371df8bdce
commit 97b4b1879d
2 changed files with 1 additions and 2 deletions
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src/freedreno/common/freedreno_devices.py
+1 -1
View File
@@ -1351,7 +1351,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_VPC_UNKNOWN_930A, 0],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9EB6, 0],
[A6XXRegs.REG_A7XX_VPC_FLATSHADE_MODE_CNTL, 1],
[A6XXRegs.REG_A7XX_SP_PS_OUTPUT_CONST_CNTL, 0],
[A6XXRegs.REG_A7XX_SP_PS_OUTPUT_CONST_MASK, 0],
src/freedreno/registers/adreno/a6xx.xml
-1
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@@ -2261,7 +2261,6 @@ by a particular renderpass/blit.
<reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/>
<reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/>
<reg32 offset="0x9eb6" name="PC_UNKNOWN_9EB6" variants="A7XX"/>
<reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/>