From 97b4b1879d30ba55200b6f3e8fcb17aa6248318f Mon Sep 17 00:00:00 2001
From: Danylo Piliaiev <dpiliaiev@igalia.com>
Date: Fri, 29 Aug 2025 12:31:28 +0200
Subject: [PATCH] freedreno/a750: Fix typo in recent magic regs change

Caused GPU hangs.

Fixes: a84069cff42 ("freedreno/registers: De-open-code some offsets")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37079>
---
 src/freedreno/common/freedreno_devices.py | 2 +-
 src/freedreno/registers/adreno/a6xx.xml   | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index 6362cba2031..b47d8457d01 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -1351,7 +1351,7 @@ add_gpus([
             [A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34,   0x00000000],
 
             [A6XXRegs.REG_A7XX_VPC_UNKNOWN_930A, 0],
-            [A6XXRegs.REG_A7XX_PC_UNKNOWN_9EB6, 0],
+            [A6XXRegs.REG_A7XX_VPC_FLATSHADE_MODE_CNTL, 1],
 
             [A6XXRegs.REG_A7XX_SP_PS_OUTPUT_CONST_CNTL, 0],
             [A6XXRegs.REG_A7XX_SP_PS_OUTPUT_CONST_MASK, 0],
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 2cdb0e2da11..98b8e490380 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2261,7 +2261,6 @@ by a particular renderpass/blit.
 	<reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/>
 
 	<reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/>
-	<reg32 offset="0x9eb6" name="PC_UNKNOWN_9EB6" variants="A7XX"/>
 
 	<reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/>