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intel/brw: Record that SHADER_OPCODE_SCRATCH_HEADER uses g0

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The generator code for emitting legacy scratch headers was implicitly
using g0 as a source.  But the IR wasn't indicating any usage of g0,
which means the liveness isn't properly tracked at the IR level.

It works because we reserve g0 as permanently live for the whole
program.  In order to stop doing that, we need to record it properly.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30319>
This commit is contained in:
Kenneth Graunke
2024-07-22 00:22:20 -07:00
parent 545f20419f
commit 9200fb966c
4 changed files with 14 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_fs.h
+2 -1
View File
@@ -505,7 +505,8 @@ private:
struct brw_reg dst, struct brw_reg src);
void generate_ddy(const fs_inst *inst,
struct brw_reg dst, struct brw_reg src);
void generate_scratch_header(fs_inst *inst, struct brw_reg dst);
void generate_scratch_header(fs_inst *inst,
struct brw_reg dst, struct brw_reg src);
void generate_halt(fs_inst *inst);
src/intel/compiler/brw_fs_generator.cpp
+8 -6
View File
@@ -701,10 +701,14 @@ fs_generator::generate_halt(fs_inst *)
* information required by either set of opcodes.
*/
void
fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
fs_generator::generate_scratch_header(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src)
{
assert(inst->exec_size == 8 && inst->force_writemask_all);
assert(dst.file == BRW_GENERAL_REGISTER_FILE);
assert(src.file == BRW_GENERAL_REGISTER_FILE);
assert(src.type == BRW_TYPE_UD);
dst.type = BRW_TYPE_UD;
@@ -716,8 +720,7 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
/* Copy the per-thread scratch space size from g0.3[3:0] */
brw_set_default_exec_size(p, BRW_EXECUTE_1);
insn = brw_AND(p, suboffset(dst, 3),
retype(brw_vec1_grf(0, 3), BRW_TYPE_UD),
insn = brw_AND(p, suboffset(dst, 3), component(src, 3),
brw_imm_ud(INTEL_MASK(3, 0)));
if (devinfo->ver < 12) {
brw_inst_set_no_dd_clear(p->devinfo, insn, true);
@@ -725,8 +728,7 @@ fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
}
/* Copy the scratch base address from g0.5[31:10] */
insn = brw_AND(p, suboffset(dst, 5),
retype(brw_vec1_grf(0, 5), BRW_TYPE_UD),
insn = brw_AND(p, suboffset(dst, 5), component(src, 5),
brw_imm_ud(INTEL_MASK(31, 10)));
if (devinfo->ver < 12)
brw_inst_set_no_dd_check(p->devinfo, insn, true);
@@ -1159,7 +1161,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
break;
case SHADER_OPCODE_SCRATCH_HEADER:
generate_scratch_header(inst, dst);
generate_scratch_header(inst, dst, src[0]);
break;
case SHADER_OPCODE_MOV_INDIRECT:
src/intel/compiler/brw_fs_reg_allocate.cpp
+2 -1
View File
@@ -622,7 +622,8 @@ fs_reg_alloc::build_legacy_scratch_header(const fs_builder &bld,
brw_reg header = retype(alloc_spill_reg(1, ip), BRW_TYPE_UD);
ra_add_node_interference(g, first_vgrf_node + header.nr, first_payload_node);
fs_inst *inst = ubld8.emit(SHADER_OPCODE_SCRATCH_HEADER, header);
fs_inst *inst =
ubld8.emit(SHADER_OPCODE_SCRATCH_HEADER, header, brw_ud8_grf(0, 0));
_mesa_set_add(spill_insts, inst);
/* Write the scratch offset */
src/intel/compiler/brw_lower_logical_sends.cpp
+2 -2
View File
@@ -1461,7 +1461,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
assert(!is_surface_access);
fs_builder ubld = bld.exec_all().group(8, 0);
header = ubld.vgrf(BRW_TYPE_UD);
ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header);
ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header, brw_ud8_grf(0, 0));
}
const unsigned header_sz = header.file != BAD_FILE ? 1 : 0;
@@ -1947,7 +1947,7 @@ lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst)
brw_reg header = ubld.vgrf(BRW_TYPE_UD);
if (is_stateless)
ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header);
ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header, brw_ud8_grf(0, 0));
else
ubld.MOV(header, brw_imm_d(0));