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agx,freedreno,intel,lima,panfrost,svga,virgl,zink: fix supports_indirect_inputs

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The GLSL compiler always lowers inputs to temps for VS and GS, so exclude
them from driver support because the GLSL compiler will no longer do that
unconditionally. Thus, indirect VS and GS inputs are completely untested
and broken in a lot of drivers.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35945>
This commit is contained in:
Marek Olšák
2025-07-05 01:40:10 -04:00
committed by Marge Bot
parent a86f32a1ae
commit 8def3f865d
11 changed files with 28 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/asahi/compiler/agx_compile.h
+3 -1
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@@ -378,7 +378,9 @@ static const nir_shader_compiler_options agx_nir_options = {
.lower_int64_options =
(nir_lower_int64_options) ~(nir_lower_iadd64 | nir_lower_imul_2x32_64),
.lower_doubles_options = (nir_lower_doubles_options)(~0),
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
BITFIELD_BIT(MESA_SHADER_FRAGMENT),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.lower_fquantize2f16 = true,
.compact_arrays = true,
src/freedreno/ir3/ir3_compiler.c
+3 -1
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@@ -372,7 +372,9 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
if (compiler->gen >= 5 && !(ir3_shader_debug & IR3_DBG_NOFP16))
compiler->nir_options.support_16bit_alu = true;
compiler->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
compiler->nir_options.support_indirect_inputs =
BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | BITFIELD_BIT(MESA_SHADER_FRAGMENT);
compiler->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
if (!options->disable_cache)
src/gallium/drivers/lima/lima_program.c
+1 -2
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@@ -64,7 +64,6 @@ static const nir_shader_compiler_options vs_nir_options = {
.force_indirect_unrolling_sampler = true,
.max_unroll_iterations = 32,
.no_integers = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.max_varying_expression_cost = 2,
};
@@ -87,7 +86,7 @@ static const nir_shader_compiler_options fs_nir_options = {
.force_indirect_unrolling_sampler = true,
.max_unroll_iterations = 32,
.no_integers = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_FRAGMENT),
.max_varying_expression_cost = 2,
};
src/gallium/drivers/svga/svga_screen.c
+3 -1
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@@ -149,7 +149,9 @@ get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
.lower_doubles_options = nir_lower_dfloor | nir_lower_dsign | nir_lower_dceil | nir_lower_dtrunc | nir_lower_dround_even, \
.lower_fmod = true, \
.lower_fpow = true, \
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \
.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | \
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | \
BITFIELD_BIT(MESA_SHADER_FRAGMENT), \
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES)
static const nir_shader_compiler_options svga_vgpu9_fragment_compiler_options = {
src/gallium/drivers/virgl/virgl_screen.c
-4
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@@ -1090,11 +1090,7 @@ virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *c
if (screen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR) {
screen->compiler_options.support_indirect_inputs |= BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
BITFIELD_BIT(MESA_SHADER_GEOMETRY) |
BITFIELD_BIT(MESA_SHADER_FRAGMENT);
if (!(screen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES))
screen->compiler_options.support_indirect_inputs |= BITFIELD_BIT(MESA_SHADER_VERTEX);
}
slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
src/gallium/drivers/zink/zink_compiler.c
+3 -3
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@@ -1310,8 +1310,6 @@ zink_screen_init_compiler(struct zink_screen *screen)
.has_isub = true,
.lower_mul_2x32_64 = true,
.support_16bit_alu = true, /* not quite what it sounds like */
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(MESA_SHADER_COMPUTE),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(MESA_SHADER_COMPUTE),
.max_unroll_iterations = 0,
};
@@ -1359,7 +1357,9 @@ zink_screen_init_compiler(struct zink_screen *screen)
nir_lower_bitfield_reverse64 | nir_lower_bitfield_extract64;
}
screen->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
screen->nir_options.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
BITFIELD_BIT(MESA_SHADER_FRAGMENT);
screen->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
}
src/intel/compiler/brw_compiler.c
+3 -1
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@@ -83,7 +83,9 @@ const struct nir_shader_compiler_options brw_scalar_nir_options = {
.vectorize_tess_levels = true,
.vertex_id_zero_based = true,
.scalarize_ddx = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_inputs = BITFIELD_BIT(PIPE_SHADER_TESS_CTRL) |
BITFIELD_BIT(PIPE_SHADER_TESS_EVAL) |
BITFIELD_BIT(PIPE_SHADER_FRAGMENT),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.per_view_unique_driver_locations = true,
.compact_view_index = true,
src/intel/compiler/elk/elk_compiler.c
+3 -1
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@@ -124,7 +124,9 @@ elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_options->lower_doubles_options = fp64_options;
nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
nir_options->support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
nir_options->support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
BITFIELD_BIT(MESA_SHADER_FRAGMENT),
nir_options->support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
nir_options->force_indirect_unrolling |=
src/intel/compiler/elk/elk_nir_options.c
+3 -1
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@@ -32,7 +32,9 @@
.lower_base_vertex = true, \
.support_16bit_alu = true, \
.lower_uniforms_to_ubo = true, \
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \
.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | \
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | \
BITFIELD_BIT(MESA_SHADER_FRAGMENT), \
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES)
#define COMMON_SCALAR_OPTIONS \
src/panfrost/compiler/bifrost_compile.h
+3 -1
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@@ -147,7 +147,9 @@ void bifrost_compile_shader_nir(nir_shader *nir,
(nir_var_shader_in | nir_var_shader_out | nir_var_function_temp), \
.force_indirect_unrolling_sampler = true, \
.scalarize_ddx = true, \
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \
.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | \
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | \
BITFIELD_BIT(MESA_SHADER_FRAGMENT), \
.lower_hadd = arch >= 11, \
.discard_is_demote = true, \
.has_udot_4x8 = arch >= 9, \
src/panfrost/midgard/midgard_compile.h
+3 -1
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@@ -105,7 +105,9 @@ static const nir_shader_compiler_options midgard_nir_options = {
.force_indirect_unrolling =
(nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
.force_indirect_unrolling_sampler = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
BITFIELD_BIT(MESA_SHADER_FRAGMENT),
};
#endif