diff --git a/src/asahi/compiler/agx_compile.h b/src/asahi/compiler/agx_compile.h index d6c3eeea1ba..103eb78f81f 100644 --- a/src/asahi/compiler/agx_compile.h +++ b/src/asahi/compiler/agx_compile.h @@ -378,7 +378,9 @@ static const nir_shader_compiler_options agx_nir_options = { .lower_int64_options = (nir_lower_int64_options) ~(nir_lower_iadd64 | nir_lower_imul_2x32_64), .lower_doubles_options = (nir_lower_doubles_options)(~0), - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), + .support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | + BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | + BITFIELD_BIT(MESA_SHADER_FRAGMENT), .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), .lower_fquantize2f16 = true, .compact_arrays = true, diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c index 8b09f199ce9..689c94d5ab3 100644 --- a/src/freedreno/ir3/ir3_compiler.c +++ b/src/freedreno/ir3/ir3_compiler.c @@ -372,7 +372,9 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id, if (compiler->gen >= 5 && !(ir3_shader_debug & IR3_DBG_NOFP16)) compiler->nir_options.support_16bit_alu = true; - compiler->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES); + compiler->nir_options.support_indirect_inputs = + BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | + BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | BITFIELD_BIT(MESA_SHADER_FRAGMENT); compiler->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES); if (!options->disable_cache) diff --git a/src/gallium/drivers/lima/lima_program.c b/src/gallium/drivers/lima/lima_program.c index f9fb395a02e..6705277dc2b 100644 --- a/src/gallium/drivers/lima/lima_program.c +++ b/src/gallium/drivers/lima/lima_program.c @@ -64,7 +64,6 @@ static const nir_shader_compiler_options vs_nir_options = { .force_indirect_unrolling_sampler = true, .max_unroll_iterations = 32, .no_integers = true, - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), .max_varying_expression_cost = 2, }; @@ -87,7 +86,7 @@ static const nir_shader_compiler_options fs_nir_options = { .force_indirect_unrolling_sampler = true, .max_unroll_iterations = 32, .no_integers = true, - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), + .support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_FRAGMENT), .max_varying_expression_cost = 2, }; diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index 99c1e82b3dd..d7a3e4a02cf 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -149,7 +149,9 @@ get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap, .lower_doubles_options = nir_lower_dfloor | nir_lower_dsign | nir_lower_dceil | nir_lower_dtrunc | nir_lower_dround_even, \ .lower_fmod = true, \ .lower_fpow = true, \ - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \ + .support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | \ + BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | \ + BITFIELD_BIT(MESA_SHADER_FRAGMENT), \ .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES) static const nir_shader_compiler_options svga_vgpu9_fragment_compiler_options = { diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index 342aa4887ca..c6f6814a42a 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -1090,11 +1090,7 @@ virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *c if (screen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR) { screen->compiler_options.support_indirect_inputs |= BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | - BITFIELD_BIT(MESA_SHADER_GEOMETRY) | BITFIELD_BIT(MESA_SHADER_FRAGMENT); - - if (!(screen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES)) - screen->compiler_options.support_indirect_inputs |= BITFIELD_BIT(MESA_SHADER_VERTEX); } slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16); diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index f1fb82e805b..7afcaf2eb47 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -1310,8 +1310,6 @@ zink_screen_init_compiler(struct zink_screen *screen) .has_isub = true, .lower_mul_2x32_64 = true, .support_16bit_alu = true, /* not quite what it sounds like */ - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(MESA_SHADER_COMPUTE), - .support_indirect_outputs = (uint8_t)BITFIELD_MASK(MESA_SHADER_COMPUTE), .max_unroll_iterations = 0, }; @@ -1359,7 +1357,9 @@ zink_screen_init_compiler(struct zink_screen *screen) nir_lower_bitfield_reverse64 | nir_lower_bitfield_extract64; } - screen->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES); + screen->nir_options.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | + BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | + BITFIELD_BIT(MESA_SHADER_FRAGMENT); screen->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES); } diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index ed579ed0d5c..0a5afe83c2b 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -83,7 +83,9 @@ const struct nir_shader_compiler_options brw_scalar_nir_options = { .vectorize_tess_levels = true, .vertex_id_zero_based = true, .scalarize_ddx = true, - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), + .support_indirect_inputs = BITFIELD_BIT(PIPE_SHADER_TESS_CTRL) | + BITFIELD_BIT(PIPE_SHADER_TESS_EVAL) | + BITFIELD_BIT(PIPE_SHADER_FRAGMENT), .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), .per_view_unique_driver_locations = true, .compact_view_index = true, diff --git a/src/intel/compiler/elk/elk_compiler.c b/src/intel/compiler/elk/elk_compiler.c index d0a39dde4e5..b3c103e5b71 100644 --- a/src/intel/compiler/elk/elk_compiler.c +++ b/src/intel/compiler/elk/elk_compiler.c @@ -124,7 +124,9 @@ elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) nir_options->lower_doubles_options = fp64_options; nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT; - nir_options->support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), + nir_options->support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | + BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | + BITFIELD_BIT(MESA_SHADER_FRAGMENT), nir_options->support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), nir_options->force_indirect_unrolling |= diff --git a/src/intel/compiler/elk/elk_nir_options.c b/src/intel/compiler/elk/elk_nir_options.c index 81c0362804b..70ab15b5d83 100644 --- a/src/intel/compiler/elk/elk_nir_options.c +++ b/src/intel/compiler/elk/elk_nir_options.c @@ -32,7 +32,9 @@ .lower_base_vertex = true, \ .support_16bit_alu = true, \ .lower_uniforms_to_ubo = true, \ - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \ + .support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | \ + BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | \ + BITFIELD_BIT(MESA_SHADER_FRAGMENT), \ .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES) #define COMMON_SCALAR_OPTIONS \ diff --git a/src/panfrost/compiler/bifrost_compile.h b/src/panfrost/compiler/bifrost_compile.h index 0c7297cb10c..b2db6cc7f2b 100644 --- a/src/panfrost/compiler/bifrost_compile.h +++ b/src/panfrost/compiler/bifrost_compile.h @@ -147,7 +147,9 @@ void bifrost_compile_shader_nir(nir_shader *nir, (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp), \ .force_indirect_unrolling_sampler = true, \ .scalarize_ddx = true, \ - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \ + .support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | \ + BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | \ + BITFIELD_BIT(MESA_SHADER_FRAGMENT), \ .lower_hadd = arch >= 11, \ .discard_is_demote = true, \ .has_udot_4x8 = arch >= 9, \ diff --git a/src/panfrost/midgard/midgard_compile.h b/src/panfrost/midgard/midgard_compile.h index 55b39b8dc55..f28d2cd72d7 100644 --- a/src/panfrost/midgard/midgard_compile.h +++ b/src/panfrost/midgard/midgard_compile.h @@ -105,7 +105,9 @@ static const nir_shader_compiler_options midgard_nir_options = { .force_indirect_unrolling = (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp), .force_indirect_unrolling_sampler = true, - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), + .support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | + BITFIELD_BIT(MESA_SHADER_TESS_EVAL) | + BITFIELD_BIT(MESA_SHADER_FRAGMENT), }; #endif