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radeonsi: reindent code in si_state_binning.c

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21641>
This commit is contained in:
Marek Olšák
2023-02-25 16:56:25 -05:00
committed by Marge Bot
parent 3a26d2b1a7
commit 8a564f72e5
1 changed files with 32 additions and 28 deletions
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src/gallium/drivers/radeonsi/si_state_binning.c
+32 -28
View File
@@ -418,23 +418,25 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
if (bin_size.y >= 32)
bin_size_extend.y = util_logbase2(bin_size.y) - 5;
radeon_opt_set_context_reg(
sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FPOVS_PER_BATCH(63) |
S_028C44_OPTIMAL_BIN_SELECTION(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(1));
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
S_028C44_BIN_SIZE_X(bin_size.x == 16) |
S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FPOVS_PER_BATCH(63) |
S_028C44_OPTIMAL_BIN_SELECTION(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(1));
} else {
radeon_opt_set_context_reg(
sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2));
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2));
}
radeon_end_update_context_roll(sctx);
}
@@ -507,17 +509,19 @@ void si_emit_dpbb_state(struct si_context *sctx)
bin_size_extend.y = util_logbase2(bin_size.y) - 5;
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(
sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) | S_028C44_BIN_SIZE_X(bin_size.x == 16) |
S_028C44_BIN_SIZE_Y(bin_size.y == 16) | S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
S_028C44_CONTEXT_STATES_PER_BIN(sscreen->pbb_context_states_per_bin - 1) |
S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) |
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2));
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
S_028C44_BIN_SIZE_X(bin_size.x == 16) |
S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
S_028C44_CONTEXT_STATES_PER_BIN(sscreen->pbb_context_states_per_bin - 1) |
S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) |
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
S_028C44_OPTIMAL_BIN_SELECTION(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2));
radeon_end_update_context_roll(sctx);
}