diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 48c2343f8ba..77cc4b26028 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -418,23 +418,25 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
       if (bin_size.y >= 32)
          bin_size_extend.y = util_logbase2(bin_size.y) - 5;
 
-      radeon_opt_set_context_reg(
-         sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
-         S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
-            S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
-            S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
-            S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | S_028C44_DISABLE_START_OF_PRIM(1) |
-            S_028C44_FPOVS_PER_BATCH(63) |
-            S_028C44_OPTIMAL_BIN_SELECTION(1) |
-            S_028C44_FLUSH_ON_BINNING_TRANSITION(1));
+      radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
+                                 SI_TRACKED_PA_SC_BINNER_CNTL_0,
+                                 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
+                                 S_028C44_BIN_SIZE_X(bin_size.x == 16) |
+                                 S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
+                                 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
+                                 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
+                                 S_028C44_DISABLE_START_OF_PRIM(1) |
+                                 S_028C44_FPOVS_PER_BATCH(63) |
+                                 S_028C44_OPTIMAL_BIN_SELECTION(1) |
+                                 S_028C44_FLUSH_ON_BINNING_TRANSITION(1));
    } else {
-      radeon_opt_set_context_reg(
-         sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
-         S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
-            S_028C44_DISABLE_START_OF_PRIM(1) |
-            S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
-                                                 sctx->family == CHIP_VEGA20 ||
-                                                 sctx->family >= CHIP_RAVEN2));
+      radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
+                                 SI_TRACKED_PA_SC_BINNER_CNTL_0,
+                                 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
+                                 S_028C44_DISABLE_START_OF_PRIM(1) |
+                                 S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
+                                                                      sctx->family == CHIP_VEGA20 ||
+                                                                      sctx->family >= CHIP_RAVEN2));
    }
    radeon_end_update_context_roll(sctx);
 }
@@ -507,17 +509,19 @@ void si_emit_dpbb_state(struct si_context *sctx)
       bin_size_extend.y = util_logbase2(bin_size.y) - 5;
 
    radeon_begin(&sctx->gfx_cs);
-   radeon_opt_set_context_reg(
-      sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
-      S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) | S_028C44_BIN_SIZE_X(bin_size.x == 16) |
-         S_028C44_BIN_SIZE_Y(bin_size.y == 16) | S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
-         S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
-         S_028C44_CONTEXT_STATES_PER_BIN(sscreen->pbb_context_states_per_bin - 1) |
-         S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) |
-         S_028C44_DISABLE_START_OF_PRIM(1) |
-         S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1) |
-         S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
-                                              sctx->family == CHIP_VEGA20 ||
-                                              sctx->family >= CHIP_RAVEN2));
+   radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
+                              S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
+                              S_028C44_BIN_SIZE_X(bin_size.x == 16) |
+                              S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
+                              S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
+                              S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
+                              S_028C44_CONTEXT_STATES_PER_BIN(sscreen->pbb_context_states_per_bin - 1) |
+                              S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) |
+                              S_028C44_DISABLE_START_OF_PRIM(1) |
+                              S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
+                              S_028C44_OPTIMAL_BIN_SELECTION(1) |
+                              S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
+                                                                   sctx->family == CHIP_VEGA20 ||
+                                                                   sctx->family >= CHIP_RAVEN2));
    radeon_end_update_context_roll(sctx);
 }