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i965/gen6_surface_state.c: Remove (gen < 6) code path

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Since this code was branched from brw_wm_surface_state.c, it had
support for gen < 6. We can now remove this.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen
2014-07-30 11:20:48 -07:00
parent 1f8e0fbd38
commit 89b1f5d6ac
1 changed files with 0 additions and 22 deletions
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src/mesa/drivers/dri/i965/gen6_surface_state.c
-22
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@@ -114,28 +114,6 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
(tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
(mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
if (brw->gen < 6) {
/* _NEW_COLOR */
if (!ctx->Color.ColorLogicOpEnabled &&
(ctx->Color.BlendEnabled & (1 << unit)))
surf[0] |= BRW_SURFACE_BLEND_ENABLED;
if (!ctx->Color.ColorMask[unit][0])
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
if (!ctx->Color.ColorMask[unit][1])
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
if (!ctx->Color.ColorMask[unit][2])
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
/* As mentioned above, disable writes to the alpha component when the
* renderbuffer is XRGB.
*/
if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
!ctx->Color.ColorMask[unit][3]) {
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
}
}
drm_intel_bo_emit_reloc(brw->batch.bo,
brw->wm.base.surf_offset[surf_index] + 4,
mt->bo,