AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

etnaviv: stop touching code steering bits while updating uniforms

Browse Source 
Bit 0 of the SH_CONTROL register does not control uniform cache
flushes so stop touching this bit when updating the uniforms.
While it is harmless to change the bit at this time in the emit
sequence, it's confusing and not needed.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36114>
This commit is contained in:
Lucas Stach
2025-07-14 00:50:34 +02:00
committed by Marge Bot
parent b093fa9dcf
commit 845e7c4426
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/etnaviv/etnaviv_emit.c
+4 -4
View File
@@ -723,12 +723,12 @@ etna_emit_state(struct etna_context *ctx)
}
if (do_uniform_flush)
etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE);
etna_set_state(stream, VIVS_SH_CONTROL, 0x0);
etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
if (do_uniform_flush)
etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE | VIVS_SH_CONTROL_PS_UNIFORM);
etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_UNIFORM);
etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
@@ -741,14 +741,14 @@ etna_emit_state(struct etna_context *ctx)
} else {
/* ideally this cache would only be flushed if there are VS uniform changes */
if (do_uniform_flush)
etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE);
etna_set_state(stream, VIVS_SH_CONTROL, 0x0);
if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
/* ideally this cache would only be flushed if there are PS uniform changes */
if (do_uniform_flush)
etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE | VIVS_SH_CONTROL_PS_UNIFORM);
etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_UNIFORM);
if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);