ir3: Make instruction IP 32 bits

a6xx supports shaders with more than 64k dwords, or at least the shader
size register has increased in size, and the matching name is gone so
there's no reason to be clever here. This doesn't fix anything at the
moment.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12487>

src/freedreno/ir3/ir3.h

@@ -384,7 +384,7 @@ struct ir3_instruction {
    };
 
    /* For assigning jump offsets, we need instruction's position: */
-   uint16_t ip;
+   uint32_t ip;
 
    /* used for per-pass extra instruction data.
     *