From 82c3dc220e39995b466694c2784252044d2e12c8 Mon Sep 17 00:00:00 2001
From: Connor Abbott <cwabbott0@gmail.com>
Date: Fri, 20 Aug 2021 16:30:30 +0200
Subject: [PATCH] ir3: Make instruction IP 32 bits

a6xx supports shaders with more than 64k dwords, or at least the shader
size register has increased in size, and the matching name is gone so
there's no reason to be clever here. This doesn't fix anything at the
moment.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12487>
---
 src/freedreno/ir3/ir3.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index 759be5f21ff..9d8f09b3bb5 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -384,7 +384,7 @@ struct ir3_instruction {
    };
 
    /* For assigning jump offsets, we need instruction's position: */
-   uint16_t ip;
+   uint32_t ip;
 
    /* used for per-pass extra instruction data.
     *