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radeonsi: call si_upload_graphics_shader_descriptors before the big conditional

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6786>
This commit is contained in:
Marek Olšák
2020-09-19 04:05:22 -04:00
committed by Marge Bot
parent 0051f2cb2a
commit 816a867bbd
1 changed files with 2 additions and 7 deletions
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src/gallium/drivers/radeonsi/si_state_draw.c
+2 -7
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@@ -1939,7 +1939,8 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
* this must be called after si_need_cs_space, because we must let
* need_cs_space flush before we add buffers to the buffer list.
*/
if (!si_upload_vertex_buffer_descriptors(sctx))
if (!si_upload_vertex_buffer_descriptors(sctx) ||
!si_upload_graphics_shader_descriptors(sctx))
goto return_cleanup;
/* Vega10/Raven scissor bug workaround. When any context register is
@@ -1968,9 +1969,6 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
if (!si_upload_graphics_shader_descriptors(sctx))
goto return_cleanup;
/* Emit all states except possibly render condition. */
si_emit_all_states(sctx, info, prim, instance_count, primitive_restart, masked_atoms);
sctx->emit_cache_flush(sctx);
@@ -2005,9 +2003,6 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
cik_emit_prefetch_L2(sctx, true);
if (!si_upload_graphics_shader_descriptors(sctx))
goto return_cleanup;
si_emit_all_states(sctx, info, prim, instance_count, primitive_restart, masked_atoms);
if (sctx->screen->info.has_gfx9_scissor_bug &&