From 816a867bbd071d8b119023d6769164cdca218faf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 19 Sep 2020 04:05:22 -0400 Subject: [PATCH] radeonsi: call si_upload_graphics_shader_descriptors before the big conditional Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_state_draw.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 20abe1dc6bb..f6a9c95be43 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1939,7 +1939,8 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i * this must be called after si_need_cs_space, because we must let * need_cs_space flush before we add buffers to the buffer list. */ - if (!si_upload_vertex_buffer_descriptors(sctx)) + if (!si_upload_vertex_buffer_descriptors(sctx) || + !si_upload_graphics_shader_descriptors(sctx)) goto return_cleanup; /* Vega10/Raven scissor bug workaround. When any context register is @@ -1968,9 +1969,6 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND)) masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond); - if (!si_upload_graphics_shader_descriptors(sctx)) - goto return_cleanup; - /* Emit all states except possibly render condition. */ si_emit_all_states(sctx, info, prim, instance_count, primitive_restart, masked_atoms); sctx->emit_cache_flush(sctx); @@ -2005,9 +2003,6 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask) cik_emit_prefetch_L2(sctx, true); - if (!si_upload_graphics_shader_descriptors(sctx)) - goto return_cleanup; - si_emit_all_states(sctx, info, prim, instance_count, primitive_restart, masked_atoms); if (sctx->screen->info.has_gfx9_scissor_bug &&