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radv: Reserve space in si_cs_emit_cache_flush.

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Fixes: 4c6f83006d ("radv: Synchronization for task shaders.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22392>
This commit is contained in:
Bas Nieuwenhuizen
2022-12-05 02:11:51 +01:00
committed by Marge Bot
parent 1de978b873
commit 771c0f0e65
5 changed files with 19 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_cmd_buffer.c
+6 -8
View File
@@ -611,8 +611,9 @@ radv_ace_internal_cache_flush(struct radv_cmd_buffer *cmd_buffer)
const uint32_t flush_bits = cmd_buffer->ace_internal.flush_bits;
enum rgp_flush_bits sqtt_flush_bits = 0;
si_cs_emit_cache_flush(ace_cs, cmd_buffer->device->physical_device->rad_info.gfx_level, NULL, 0,
true, flush_bits, &sqtt_flush_bits, 0);
si_cs_emit_cache_flush(cmd_buffer->device->ws, ace_cs,
cmd_buffer->device->physical_device->rad_info.gfx_level, NULL, 0, true,
flush_bits, &sqtt_flush_bits, 0);
cmd_buffer->ace_internal.flush_bits = 0;
}
@@ -740,20 +741,17 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flu
enum rgp_flush_bits sqtt_flush_bits = 0;
assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
ASSERTED const unsigned cdw_max = radeon_check_space(device->ws, cmd_buffer->cs, 4);
/* Force wait for graphics or compute engines to be idle. */
si_cs_emit_cache_flush(cmd_buffer->cs, device->physical_device->rad_info.gfx_level,
si_cs_emit_cache_flush(device->ws, cmd_buffer->cs,
device->physical_device->rad_info.gfx_level,
&cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va,
radv_cmd_buffer_uses_mec(cmd_buffer), flags, &sqtt_flush_bits,
cmd_buffer->gfx9_eop_bug_va);
assert(cmd_buffer->cs->cdw <= cdw_max);
if (cmd_buffer->state.graphics_pipeline && (flags & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) &&
radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) {
/* Force wait for compute engines to be idle on the internal cmdbuf. */
si_cs_emit_cache_flush(cmd_buffer->ace_internal.cs,
si_cs_emit_cache_flush(device->ws, cmd_buffer->ace_internal.cs,
device->physical_device->rad_info.gfx_level, NULL, 0, true,
RADV_CMD_FLAG_CS_PARTIAL_FLUSH, &sqtt_flush_bits, 0);
}
src/amd/vulkan/radv_private.h
+3 -3
View File
@@ -1885,9 +1885,9 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx
void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref,
uint32_t mask);
void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level,
uint32_t *fence_ptr, uint64_t va, bool is_mec,
enum radv_cmd_flush_bits flush_bits,
void si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va,
bool is_mec, enum radv_cmd_flush_bits flush_bits,
enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va);
void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visible,
src/amd/vulkan/radv_queue.c
+2 -1
View File
@@ -1127,7 +1127,8 @@ radv_update_preamble_cs(struct radv_queue_state *queue, struct radv_device *devi
flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
}
si_cs_emit_cache_flush(cs, gfx_level, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, 0);
si_cs_emit_cache_flush(ws, cs, gfx_level, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits,
0);
}
result = ws->cs_finalize(cs);
src/amd/vulkan/radv_sqtt.c
+1 -1
View File
@@ -78,7 +78,7 @@ radv_emit_wait_for_idle(struct radv_device *device, struct radeon_cmdbuf *cs, in
{
enum rgp_flush_bits sqtt_flush_bits = 0;
si_cs_emit_cache_flush(
cs, device->physical_device->rad_info.gfx_level, NULL, 0,
device->ws, cs, device->physical_device->rad_info.gfx_level, NULL, 0,
family == AMD_IP_COMPUTE && device->physical_device->rad_info.gfx_level >= GFX7,
(family == RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
src/amd/vulkan/si_cmd_buffer.c
+7 -5
View File
@@ -1324,14 +1324,17 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level
}
void
si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt,
uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits,
si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va,
bool is_mec, enum radv_cmd_flush_bits flush_bits,
enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va)
{
unsigned cp_coher_cntl = 0;
uint32_t flush_cb_db =
flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB);
radeon_check_space(ws, cs, 128);
if (gfx_level >= GFX10) {
/* GFX10 cache flush handling is quite different. */
gfx10_cs_emit_cache_flush(cs, gfx_level, flush_cnt, flush_va, is_mec, flush_bits,
@@ -1536,9 +1539,8 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
return;
}
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
si_cs_emit_cache_flush(cmd_buffer->device->ws, cmd_buffer->cs,
cmd_buffer->device->physical_device->rad_info.gfx_level,
&cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va,
radv_cmd_buffer_uses_mec(cmd_buffer), cmd_buffer->state.flush_bits,
&cmd_buffer->state.sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va);