From 771c0f0e658d78d603083e535135c1cd954717db Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Mon, 5 Dec 2022 02:11:51 +0100 Subject: [PATCH] radv: Reserve space in si_cs_emit_cache_flush. Fixes: 4c6f83006d4 ("radv: Synchronization for task shaders.") Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 14 ++++++-------- src/amd/vulkan/radv_private.h | 6 +++--- src/amd/vulkan/radv_queue.c | 3 ++- src/amd/vulkan/radv_sqtt.c | 2 +- src/amd/vulkan/si_cmd_buffer.c | 12 +++++++----- 5 files changed, 19 insertions(+), 18 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 4c6282cd3c7..c1e9fb457ae 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -611,8 +611,9 @@ radv_ace_internal_cache_flush(struct radv_cmd_buffer *cmd_buffer) const uint32_t flush_bits = cmd_buffer->ace_internal.flush_bits; enum rgp_flush_bits sqtt_flush_bits = 0; - si_cs_emit_cache_flush(ace_cs, cmd_buffer->device->physical_device->rad_info.gfx_level, NULL, 0, - true, flush_bits, &sqtt_flush_bits, 0); + si_cs_emit_cache_flush(cmd_buffer->device->ws, ace_cs, + cmd_buffer->device->physical_device->rad_info.gfx_level, NULL, 0, true, + flush_bits, &sqtt_flush_bits, 0); cmd_buffer->ace_internal.flush_bits = 0; } @@ -740,20 +741,17 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flu enum rgp_flush_bits sqtt_flush_bits = 0; assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH)); - ASSERTED const unsigned cdw_max = radeon_check_space(device->ws, cmd_buffer->cs, 4); - /* Force wait for graphics or compute engines to be idle. */ - si_cs_emit_cache_flush(cmd_buffer->cs, device->physical_device->rad_info.gfx_level, + si_cs_emit_cache_flush(device->ws, cmd_buffer->cs, + device->physical_device->rad_info.gfx_level, &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer), flags, &sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); - assert(cmd_buffer->cs->cdw <= cdw_max); - if (cmd_buffer->state.graphics_pipeline && (flags & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) && radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) { /* Force wait for compute engines to be idle on the internal cmdbuf. */ - si_cs_emit_cache_flush(cmd_buffer->ace_internal.cs, + si_cs_emit_cache_flush(device->ws, cmd_buffer->ace_internal.cs, device->physical_device->rad_info.gfx_level, NULL, 0, true, RADV_CMD_FLAG_CS_PARTIAL_FLUSH, &sqtt_flush_bits, 0); } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 095b8270000..12de11d288d 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1885,9 +1885,9 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask); -void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, - uint32_t *fence_ptr, uint64_t va, bool is_mec, - enum radv_cmd_flush_bits flush_bits, +void si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, + enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, + bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va); void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer); void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visible, diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 147e5a20fcd..0823e545a19 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -1127,7 +1127,8 @@ radv_update_preamble_cs(struct radv_queue_state *queue, struct radv_device *devi flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH; } - si_cs_emit_cache_flush(cs, gfx_level, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, 0); + si_cs_emit_cache_flush(ws, cs, gfx_level, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, + 0); } result = ws->cs_finalize(cs); diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index 8c9b67ad656..c4adb9b38e4 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -78,7 +78,7 @@ radv_emit_wait_for_idle(struct radv_device *device, struct radeon_cmdbuf *cs, in { enum rgp_flush_bits sqtt_flush_bits = 0; si_cs_emit_cache_flush( - cs, device->physical_device->rad_info.gfx_level, NULL, 0, + device->ws, cs, device->physical_device->rad_info.gfx_level, NULL, 0, family == AMD_IP_COMPUTE && device->physical_device->rad_info.gfx_level >= GFX7, (family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index a68a35127f5..dede9a862b1 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -1324,14 +1324,17 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level } void -si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, - uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, +si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, + enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, + bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) { unsigned cp_coher_cntl = 0; uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB); + radeon_check_space(ws, cs, 128); + if (gfx_level >= GFX10) { /* GFX10 cache flush handling is quite different. */ gfx10_cs_emit_cache_flush(cs, gfx_level, flush_cnt, flush_va, is_mec, flush_bits, @@ -1536,9 +1539,8 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) return; } - radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128); - - si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level, + si_cs_emit_cache_flush(cmd_buffer->device->ws, cmd_buffer->cs, + cmd_buffer->device->physical_device->rad_info.gfx_level, &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer), cmd_buffer->state.flush_bits, &cmd_buffer->state.sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va);