AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

tu: Workaround bionic _SC_LEVEL1_DCACHE_LINESIZE

Browse Source 
Bionic just returns a hard-coded 0, which isn't helpful.  But
fortunately on aarch64 it is easy enough just to read the value
ourselves.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24829>
This commit is contained in:
Rob Clark
2023-08-21 13:35:57 -07:00
committed by Marge Bot
parent 08fc4603dd
commit 75789e9429
3 changed files with 16 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/vulkan/tu_knl.cc
+16
View File
@@ -221,6 +221,22 @@ tu_physical_device_try_create(struct vk_instance *vk_instance,
assert(device);
#ifdef _SC_LEVEL1_DCACHE_LINESIZE
if (DETECT_ARCH_AARCH64 || DETECT_ARCH_X86 || DETECT_ARCH_X86_64) {
long l1_dcache;
#if defined(ANDROID) && DETECT_ARCH_AARCH64
/* Bionic does not implement _SC_LEVEL1_DCACHE_LINESIZE properly: */
uint64_t ctr_el0;
asm("mrs\t%x0, ctr_el0" : "=r"(ctr_el0));
l1_dcache = 4 << ((ctr_el0 >> 16) & 0xf);
#else
l1_dcache = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
#endif
device->has_cached_non_coherent_memory = l1_dcache > 0;
device->level1_dcache_size = l1_dcache;
}
#endif
if (instance->vk.enabled_extensions.KHR_display) {
master_fd = open(primary_path, O_RDWR | O_CLOEXEC);
}
src/freedreno/vulkan/tu_knl_drm_msm.cc
-7
View File
@@ -1098,13 +1098,6 @@ tu_knl_drm_msm_load(struct tu_instance *instance,
device->has_cached_coherent_memory =
(device->msm_minor_version >= 8) &&
tu_drm_is_memory_type_supported(fd, MSM_BO_CACHED_COHERENT);
#ifdef _SC_LEVEL1_DCACHE_LINESIZE
if (DETECT_ARCH_AARCH64 || DETECT_ARCH_X86 || DETECT_ARCH_X86_64) {
long l1_dcache = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
device->has_cached_non_coherent_memory = l1_dcache > 0;
device->level1_dcache_size = l1_dcache;
}
#endif
device->submitqueue_priority_count = tu_drm_get_priorities(device);
src/freedreno/vulkan/tu_knl_drm_virtio.cc
-7
View File
@@ -1579,13 +1579,6 @@ tu_knl_drm_virtio_load(struct tu_instance *instance,
device->gmem_size = debug_get_num_option("TU_GMEM", device->gmem_size);
device->has_cached_coherent_memory = caps.u.msm.has_cached_coherent;
#ifdef _SC_LEVEL1_DCACHE_LINESIZE
if (DETECT_ARCH_AARCH64 || DETECT_ARCH_X86 || DETECT_ARCH_X86_64) {
long l1_dcache = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
device->has_cached_non_coherent_memory = l1_dcache > 0;
device->level1_dcache_size = l1_dcache;
}
#endif
device->submitqueue_priority_count = caps.u.msm.priorities;