brw: use transpose unspill messages when possible

This simplifies the unspill messages quite a bit.

A/B testing on DG2 :

BlackOps3 : +0.96%
TotalWarPharaoh: +0.31%

DG2 shader changes :

  Assassin's Creed Valhalla:
  Totals from 19 (0.89% of 2131) affected shaders:
  Instrs: 70542 -> 64369 (-8.75%)
  Cycle count: 18810945 -> 18560169 (-1.33%); split: -1.40%, +0.06%

  Black Ops 3:
  Totals from 55 (3.41% of 1612) affected shaders:
  Instrs: 389549 -> 350646 (-9.99%)
  Cycle count: 344168275 -> 340652311 (-1.02%); split: -1.17%, +0.15%

  Control:
  Totals from 1 (0.11% of 878) affected shaders:
  Instrs: 3409 -> 3212 (-5.78%)
  Cycle count: 255991 -> 250411 (-2.18%)

  Cyberpunk 2077:
  Totals from 1 (0.08% of 1264) affected shaders:
  Instrs: 2363 -> 2337 (-1.10%)
  Cycle count: 69283 -> 69186 (-0.14%)

  Fallout 4:
  Totals from 1 (0.06% of 1601) affected shaders:
  Instrs: 27946 -> 20056 (-28.23%)
  Cycle count: 2391398 -> 2153658 (-9.94%)

  Fortnite:
  Totals from 273 (3.65% of 7470) affected shaders:
  Instrs: 634377 -> 601519 (-5.18%)
  Cycle count: 31870433 -> 31624089 (-0.77%); split: -0.78%, +0.01%

  Hogwarts Legacy:
  Totals from 50 (3.02% of 1656) affected shaders:
  Instrs: 110455 -> 103339 (-6.44%)
  Cycle count: 6613728 -> 6530832 (-1.25%); split: -1.28%, +0.03%

  Metro Exodus:
  Totals from 70 (0.16% of 43076) affected shaders:
  Instrs: 253847 -> 245321 (-3.36%)
  Cycle count: 13269473 -> 13209131 (-0.45%)
  Spill count: 1111 -> 1108 (-0.27%)
  Fill count: 2868 -> 2865 (-0.10%)

  Red Dead Redemption 2:
  Totals from 139 (2.38% of 5847) affected shaders:
  Instrs: 496551 -> 450180 (-9.34%)
  Cycle count: 43233944 -> 40947386 (-5.29%); split: -5.33%, +0.04%
  Spill count: 6322 -> 6326 (+0.06%)
  Fill count: 15558 -> 15568 (+0.06%)

  Rise Of The Tomb Raider:
  Totals from 1 (0.56% of 178) affected shaders:
  Instrs: 1682 -> 1437 (-14.57%)
  Cycle count: 603670 -> 586766 (-2.80%)

  Spiderman Remastered:
  Totals from 820 (11.77% of 6965) affected shaders:
  Instrs: 4622877 -> 3984893 (-13.80%)
  Cycle count: 235094963186 -> 234483925430 (-0.26%); split: -0.42%, +0.16%
  Spill count: 73414 -> 73581 (+0.23%); split: -0.02%, +0.25%
  Fill count: 215090 -> 215627 (+0.25%); split: -0.02%, +0.27%
  Scratch Memory Size: 3520512 -> 3528704 (+0.23%); split: -0.12%, +0.35%

Some of stats show spilling changes which is telling of how our spill
code is not adequate. Some of the spilled values are probably being
respilled which shouldn't be the case.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32110>

src/intel/compiler/brw_fs_builder.h

@@ -813,6 +813,10 @@ namespace brw {
       fs_inst *WHILE()    { return emit(BRW_OPCODE_WHILE); }
       fs_inst *CONTINUE() { return emit(BRW_OPCODE_CONTINUE); }
 
+      bool has_writemask_all() const {
+         return force_writemask_all;
+      }
+
    private:
       /**
        * Workaround for negation of UD registers.  See comment in

src/intel/compiler/brw_fs_reg_allocate.cpp

@@ -773,7 +773,7 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld,
          /* LSC is limited to SIMD16 load/store but we can load more using
           * transpose messages.
           */
-         const bool use_transpose = bld.dispatch_width() > 16;
+         const bool use_transpose = bld.dispatch_width() > 16 || bld.has_writemask_all();
          const fs_builder ubld = use_transpose ? bld.exec_all().group(1, 0) : bld;
          brw_reg offset;
          if (use_transpose) {