diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h
index 038cb0bab14..807b566531b 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -813,6 +813,10 @@ namespace brw {
       fs_inst *WHILE()    { return emit(BRW_OPCODE_WHILE); }
       fs_inst *CONTINUE() { return emit(BRW_OPCODE_CONTINUE); }
 
+      bool has_writemask_all() const {
+         return force_writemask_all;
+      }
+
    private:
       /**
        * Workaround for negation of UD registers.  See comment in
diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp
index 979367ade01..9e1d1a6e5b2 100644
--- a/src/intel/compiler/brw_fs_reg_allocate.cpp
+++ b/src/intel/compiler/brw_fs_reg_allocate.cpp
@@ -773,7 +773,7 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld,
          /* LSC is limited to SIMD16 load/store but we can load more using
           * transpose messages.
           */
-         const bool use_transpose = bld.dispatch_width() > 16;
+         const bool use_transpose = bld.dispatch_width() > 16 || bld.has_writemask_all();
          const fs_builder ubld = use_transpose ? bld.exec_all().group(1, 0) : bld;
          brw_reg offset;
          if (use_transpose) {