pan/va: Add unit tests for ADD_IMM optimizations
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
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Alyssa Rosenzweig
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676d9c9441
@@ -160,10 +160,11 @@ if with_tests
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'test/test-pack-formats.cpp',
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'test/test-packing.cpp',
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'test/test-scheduler-predicates.cpp',
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'valhall/test/test-add-imm.cpp',
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),
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c_args : [c_msvc_compat_args, no_override_init_args],
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gnu_symbol_visibility : 'hidden',
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include_directories : [inc_include, inc_src, inc_mesa],
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include_directories : [inc_include, inc_src, inc_mesa, inc_valhall],
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dependencies: [idep_gtest, idep_nir, idep_bi_opcodes_h, idep_bi_builder_h],
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link_with : [libpanfrost_bifrost],
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),
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@@ -0,0 +1,137 @@
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/*
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* Copyright (C) 2021 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "va_compiler.h"
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#include "bi_test.h"
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#include "bi_builder.h"
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#include "util/u_cpu_detect.h"
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#include <gtest/gtest.h>
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static inline void
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add_imm(bi_context *ctx)
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{
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bi_foreach_instr_global(ctx, I) {
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va_fuse_add_imm(I);
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}
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}
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#define CASE(instr, expected) INSTRUCTION_CASE(instr, expected, add_imm)
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#define NEGCASE(instr) CASE(instr, instr)
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class AddImm : public testing::Test {
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protected:
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AddImm() {
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mem_ctx = ralloc_context(NULL);
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/* For bi_imm_f16 */
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util_cpu_detect();
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}
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~AddImm() {
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ralloc_free(mem_ctx);
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}
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void *mem_ctx;
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};
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TEST_F(AddImm, Basic) {
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CASE(bi_mov_i32_to(b, bi_register(63), bi_imm_u32(0xABAD1DEA)),
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bi_iadd_imm_i32_to(b, bi_register(63), bi_zero(), 0xABAD1DEA));
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CASE(bi_fadd_f32_to(b, bi_register(1), bi_register(2), bi_imm_f32(42.0), BI_ROUND_NONE),
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bi_fadd_imm_f32_to(b, bi_register(1), bi_register(2), fui(42.0)));
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CASE(bi_fadd_f32_to(b, bi_register(1), bi_discard(bi_register(2)), bi_imm_f32(42.0), BI_ROUND_NONE),
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bi_fadd_imm_f32_to(b, bi_register(1), bi_discard(bi_register(2)), fui(42.0)));
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CASE(bi_fadd_f32_to(b, bi_register(1), bi_discard(bi_register(2)), bi_neg(bi_imm_f32(42.0)), BI_ROUND_NONE),
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bi_fadd_imm_f32_to(b, bi_register(1), bi_discard(bi_register(2)), fui(-42.0)));
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}
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TEST_F(AddImm, Commutativty) {
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CASE(bi_fadd_f32_to(b, bi_register(1), bi_imm_f32(42.0), bi_register(2), BI_ROUND_NONE),
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bi_fadd_imm_f32_to(b, bi_register(1), bi_register(2), fui(42.0)));
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}
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TEST_F(AddImm, NoModifiers) {
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NEGCASE(bi_fadd_f32_to(b, bi_register(1), bi_register(2), bi_imm_f32(42.0),
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BI_ROUND_RTP));
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NEGCASE(bi_fadd_f32_to(b, bi_register(1), bi_abs(bi_register(2)), bi_imm_f32(42.0),
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BI_ROUND_NONE));
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NEGCASE(bi_fadd_f32_to(b, bi_register(1), bi_neg(bi_register(2)), bi_imm_f32(42.0),
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BI_ROUND_NONE));
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NEGCASE(bi_fadd_f32_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_f32(42.0),
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BI_ROUND_NONE));
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}
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TEST_F(AddImm, NoClamp) {
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NEGCASE({
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bi_instr *I = bi_fadd_f32_to(b, bi_register(1), bi_register(2),
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bi_imm_f32(42.0), BI_ROUND_NONE);
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I->clamp = BI_CLAMP_CLAMP_M1_1;
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});
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}
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TEST_F(AddImm, OtherTypes) {
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CASE(bi_fadd_v2f16_to(b, bi_register(1), bi_register(2), bi_imm_f16(42.0), BI_ROUND_NONE),
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bi_fadd_imm_v2f16_to(b, bi_register(1), bi_register(2), 0x51405140));
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CASE(bi_iadd_u32_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false),
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bi_iadd_imm_i32_to(b, bi_register(1), bi_register(2), 0xDEADBEEF));
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CASE(bi_iadd_v2u16_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false),
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bi_iadd_imm_v2i16_to(b, bi_register(1), bi_register(2), 0xDEADBEEF));
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CASE(bi_iadd_v4u8_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false),
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bi_iadd_imm_v4i8_to(b, bi_register(1), bi_register(2), 0xDEADBEEF));
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CASE(bi_iadd_s32_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false),
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bi_iadd_imm_i32_to(b, bi_register(1), bi_register(2), 0xDEADBEEF));
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CASE(bi_iadd_v2s16_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false),
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bi_iadd_imm_v2i16_to(b, bi_register(1), bi_register(2), 0xDEADBEEF));
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CASE(bi_iadd_v4s8_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false),
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bi_iadd_imm_v4i8_to(b, bi_register(1), bi_register(2), 0xDEADBEEF));
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NEGCASE(bi_fadd_v2f16_to(b, bi_register(1), bi_register(2), bi_imm_f16(42.0), BI_ROUND_RTZ));
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NEGCASE(bi_iadd_u32_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_u32(0xDEADBEEF), false));
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NEGCASE(bi_iadd_v2u16_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_u32(0xDEADBEEF), false));
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NEGCASE(bi_iadd_u32_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), true));
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NEGCASE(bi_iadd_s32_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_u32(0xDEADBEEF), false));
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NEGCASE(bi_iadd_v2s16_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_u32(0xDEADBEEF), false));
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NEGCASE(bi_iadd_s32_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), true));
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}
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TEST_F(AddImm, Int8) {
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bi_index idx = bi_register(2);
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idx.swizzle = BI_SWIZZLE_B0000;
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NEGCASE(bi_iadd_v4u8_to(b, bi_register(1), idx, bi_imm_u32(0xDEADBEEF), false));
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NEGCASE(bi_iadd_v4s8_to(b, bi_register(1), idx, bi_imm_u32(0xDEADBEEF), false));
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}
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