From 676d9c94412b4d753f8f8949759a6a67f43f5345 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 22 Jul 2021 11:59:09 -0400 Subject: [PATCH] pan/va: Add unit tests for ADD_IMM optimizations Signed-off-by: Alyssa Rosenzweig Part-of: --- src/panfrost/bifrost/meson.build | 3 +- .../bifrost/valhall/test/test-add-imm.cpp | 137 ++++++++++++++++++ 2 files changed, 139 insertions(+), 1 deletion(-) create mode 100644 src/panfrost/bifrost/valhall/test/test-add-imm.cpp diff --git a/src/panfrost/bifrost/meson.build b/src/panfrost/bifrost/meson.build index 3191d24ec65..914bd53f407 100644 --- a/src/panfrost/bifrost/meson.build +++ b/src/panfrost/bifrost/meson.build @@ -160,10 +160,11 @@ if with_tests 'test/test-pack-formats.cpp', 'test/test-packing.cpp', 'test/test-scheduler-predicates.cpp', + 'valhall/test/test-add-imm.cpp', ), c_args : [c_msvc_compat_args, no_override_init_args], gnu_symbol_visibility : 'hidden', - include_directories : [inc_include, inc_src, inc_mesa], + include_directories : [inc_include, inc_src, inc_mesa, inc_valhall], dependencies: [idep_gtest, idep_nir, idep_bi_opcodes_h, idep_bi_builder_h], link_with : [libpanfrost_bifrost], ), diff --git a/src/panfrost/bifrost/valhall/test/test-add-imm.cpp b/src/panfrost/bifrost/valhall/test/test-add-imm.cpp new file mode 100644 index 00000000000..7004bbbd564 --- /dev/null +++ b/src/panfrost/bifrost/valhall/test/test-add-imm.cpp @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2021 Collabora, Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "va_compiler.h" +#include "bi_test.h" +#include "bi_builder.h" +#include "util/u_cpu_detect.h" + +#include + +static inline void +add_imm(bi_context *ctx) +{ + bi_foreach_instr_global(ctx, I) { + va_fuse_add_imm(I); + } +} + +#define CASE(instr, expected) INSTRUCTION_CASE(instr, expected, add_imm) +#define NEGCASE(instr) CASE(instr, instr) + +class AddImm : public testing::Test { +protected: + AddImm() { + mem_ctx = ralloc_context(NULL); + + /* For bi_imm_f16 */ + util_cpu_detect(); + } + + ~AddImm() { + ralloc_free(mem_ctx); + } + + void *mem_ctx; +}; + + +TEST_F(AddImm, Basic) { + CASE(bi_mov_i32_to(b, bi_register(63), bi_imm_u32(0xABAD1DEA)), + bi_iadd_imm_i32_to(b, bi_register(63), bi_zero(), 0xABAD1DEA)); + + CASE(bi_fadd_f32_to(b, bi_register(1), bi_register(2), bi_imm_f32(42.0), BI_ROUND_NONE), + bi_fadd_imm_f32_to(b, bi_register(1), bi_register(2), fui(42.0))); + + CASE(bi_fadd_f32_to(b, bi_register(1), bi_discard(bi_register(2)), bi_imm_f32(42.0), BI_ROUND_NONE), + bi_fadd_imm_f32_to(b, bi_register(1), bi_discard(bi_register(2)), fui(42.0))); + + CASE(bi_fadd_f32_to(b, bi_register(1), bi_discard(bi_register(2)), bi_neg(bi_imm_f32(42.0)), BI_ROUND_NONE), + bi_fadd_imm_f32_to(b, bi_register(1), bi_discard(bi_register(2)), fui(-42.0))); +} + +TEST_F(AddImm, Commutativty) { + CASE(bi_fadd_f32_to(b, bi_register(1), bi_imm_f32(42.0), bi_register(2), BI_ROUND_NONE), + bi_fadd_imm_f32_to(b, bi_register(1), bi_register(2), fui(42.0))); +} + +TEST_F(AddImm, NoModifiers) { + NEGCASE(bi_fadd_f32_to(b, bi_register(1), bi_register(2), bi_imm_f32(42.0), + BI_ROUND_RTP)); + + NEGCASE(bi_fadd_f32_to(b, bi_register(1), bi_abs(bi_register(2)), bi_imm_f32(42.0), + BI_ROUND_NONE)); + + NEGCASE(bi_fadd_f32_to(b, bi_register(1), bi_neg(bi_register(2)), bi_imm_f32(42.0), + BI_ROUND_NONE)); + + NEGCASE(bi_fadd_f32_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_f32(42.0), + BI_ROUND_NONE)); +} + +TEST_F(AddImm, NoClamp) { + NEGCASE({ + bi_instr *I = bi_fadd_f32_to(b, bi_register(1), bi_register(2), + bi_imm_f32(42.0), BI_ROUND_NONE); + I->clamp = BI_CLAMP_CLAMP_M1_1; + }); +} + +TEST_F(AddImm, OtherTypes) { + CASE(bi_fadd_v2f16_to(b, bi_register(1), bi_register(2), bi_imm_f16(42.0), BI_ROUND_NONE), + bi_fadd_imm_v2f16_to(b, bi_register(1), bi_register(2), 0x51405140)); + + CASE(bi_iadd_u32_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false), + bi_iadd_imm_i32_to(b, bi_register(1), bi_register(2), 0xDEADBEEF)); + + CASE(bi_iadd_v2u16_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false), + bi_iadd_imm_v2i16_to(b, bi_register(1), bi_register(2), 0xDEADBEEF)); + + CASE(bi_iadd_v4u8_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false), + bi_iadd_imm_v4i8_to(b, bi_register(1), bi_register(2), 0xDEADBEEF)); + + CASE(bi_iadd_s32_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false), + bi_iadd_imm_i32_to(b, bi_register(1), bi_register(2), 0xDEADBEEF)); + + CASE(bi_iadd_v2s16_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false), + bi_iadd_imm_v2i16_to(b, bi_register(1), bi_register(2), 0xDEADBEEF)); + + CASE(bi_iadd_v4s8_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), false), + bi_iadd_imm_v4i8_to(b, bi_register(1), bi_register(2), 0xDEADBEEF)); + + NEGCASE(bi_fadd_v2f16_to(b, bi_register(1), bi_register(2), bi_imm_f16(42.0), BI_ROUND_RTZ)); + NEGCASE(bi_iadd_u32_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_u32(0xDEADBEEF), false)); + NEGCASE(bi_iadd_v2u16_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_u32(0xDEADBEEF), false)); + NEGCASE(bi_iadd_u32_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), true)); + NEGCASE(bi_iadd_s32_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_u32(0xDEADBEEF), false)); + NEGCASE(bi_iadd_v2s16_to(b, bi_register(1), bi_swz_16(bi_register(2), false, false), bi_imm_u32(0xDEADBEEF), false)); + + NEGCASE(bi_iadd_s32_to(b, bi_register(1), bi_register(2), bi_imm_u32(0xDEADBEEF), true)); +} + +TEST_F(AddImm, Int8) { + bi_index idx = bi_register(2); + idx.swizzle = BI_SWIZZLE_B0000; + NEGCASE(bi_iadd_v4u8_to(b, bi_register(1), idx, bi_imm_u32(0xDEADBEEF), false)); + NEGCASE(bi_iadd_v4s8_to(b, bi_register(1), idx, bi_imm_u32(0xDEADBEEF), false)); +}