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intel/elk: Rename symbols

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Either replace the BRW prefix with ELK or add an extra ELK prefix.  Used
the following sed script to perform the renames in this patch:

```
    # Simple prefix changes.
    s/\<BRW_/ELK_/g
    s/\<brw_/elk_/g
    s/nir_to_brw/nir_to_elk/g
    s/\<as_brw_reg\>/as_elk_reg/g
    s/\<_brw_/_elk_/g

    # Add prefix to various symbols.
    #
    # Initially I've considered using C++ namespaces here, but in various
    # cases the structs or functions had to be also visible from C code.
    # So added explicit prefix instead.
    s/\<backend_instruction/elk_\0/g
    s/\<backend_reg/elk_\0/g
    s/\<backend_shader/elk_\0/g
    s/\<bblock_t\>/elk_\0/g
    s/\<bblock_link\>/elk_\0/g
    s/\<cfg_t\>/elk_\0/g
    s/\<fs_visitor\>/elk_\0/g
    s/\<fs_reg\>/elk_\0/g
    s/\<fs_instruction_scheduler\>/elk_\0/g
    s/\<vec4_instruction_scheduler\>/elk_\0/g
    s/\<instruction_scheduler\>/elk_\0/g
    s/\<schedule_node\>/elk_\0/g
    s/\<schedule_node_child\>/elk_\0/g
    s/\<\([a-z]*_\)\?thread_payload\>/elk_\1thread_payload/g
    s/\<fs_generator\>/elk_\0/g
    s/\<fs_inst\>/elk_\0/g
    s/\<fs_reg_alloc\>/elk_\0/g
    s/\<disasm_info\>/elk_\0/g
    s/\<gfx._math\>/elk_\0/g
    s/\<gfx7_block_read_scratch\>/elk_\0/g
    s/\<gfx6_IF\>/elk_\0/g
    s/\<gfx9_fb_READ\>/elk_\0/g
    s/\<gfx6_resolve_implied_move\>/elk_\0/g

    # Opcodes.
    s/\<opcode op\>/elk_\0/g
    s/\<opcode mov_op\>/elk_\0/g
    s/\<opcode opcode\>/elk_\0/g
    s/enum opcode\>/enum elk_opcode/g
    s/static opcode\>/static elk_opcode/g
    s/\<opcode elk_op/elk_opcode elk_op/g
    s/struct opcode_desc/struct elk_opcode_desc/g
    s/NUM_BRW_OPCODES/NUM_ELK_OPCODES/g
    s/\<.._OPCODE_/ELK_\0/g
    s/\<T.._OPCODE_/ELK_\0/g
    s/\<VEC4_OPCODE_/ELK_\0/g
    s/\<VEC4_...\?_OPCODE_/ELK_\0/g
    s/\<SHADER_OPCODE_/ELK_\0/g

    # Remaining specific cases.
    s/\<wm_prog_data_barycentric_modes\>/elk_\0/g
    s/\<encode_slm_size\>/elk_\0/g
    s/\<intel_calculate_slm_size\>/elk_\0/g
    s/\<gfx6_gather_sampler_wa\>/elk_\0/g
    s/\<is_3src\>/elk_\0/g
    s/\<WA_/ELK_\0/g
    s/\<conditional_modifier\>/elk_\0/g
    s/\<pred_ctrl_align16\>/elk_\0/g
    s/\<shuffle_from_32bit_read\>/elk_\0/g
    s/\<shuffle_src_to_dst\>/elk_\0/g
    s/\<setup_imm_..\?\>/elk_\0/g

    s/\<opt_predicated_break\>/elk_\0/g
    s/\<has_bank_conflict\>/elk_\0/g
    s/\<dead_control_flow_eliminate\>/elk_\0/g

    s/\<disasm_new_inst_group\>/elk_\0/g
    s/\<disasm_initialize\>/elk_\0/g
    s/\<dump_assembly\>/elk_\0/g
    s/\<disasm_insert_error\>/elk_\0/g
    s/\<disasm_annotate\>/elk_\0/g

    s/\<enum lsc_opcode\>/enum elk_lsc_opcode/g
    s/\<lsc_opcode_/elk_lsc_opcode_/g
    s/\<lsc_aop_[a-z_]\+\>/elk_\0/g

    s/\<type_size_vec4\>/elk_\0/g
    s/\<type_size_dvec4\>/elk_\0/g
    s/\<type_size_xvec4\>/elk_\0/g
    s/\<type_size_[a-z4]\+_bytes\>/elk_\0/g

    s/\<gfx12_systolic_depth\>/elk_\0/g
```

Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
This commit is contained in:
Caio Oliveira
2024-01-19 18:46:03 -08:00
committed by Marge Bot
parent f677485ad4
commit 6648e0ebd3
123 changed files with 20566 additions and 20567 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/elk/elk_asm.h
+1 -1
View File
@@ -44,7 +44,7 @@ int yyparse(void);
int yylex(void);
char *lex_text(void);
extern struct brw_codegen *p;
extern struct elk_codegen *p;
extern int errors;
extern char *input_filename;
src/intel/compiler/elk/elk_asm_tool.c
+41 -41
View File
@@ -34,7 +34,7 @@ enum opt_output_type {
};
extern FILE *yyin;
struct brw_codegen *p;
struct elk_codegen *p;
static enum opt_output_type output_type = OPT_OUTPUT_BIN;
char *input_filename = NULL;
int errors;
@@ -61,7 +61,7 @@ print_help(const char *progname, FILE *file)
}
static uint32_t
get_dword(const brw_inst *inst, int idx)
get_dword(const elk_inst *inst, int idx)
{
uint32_t dword;
memcpy(&dword, (char *)inst + 4 * idx, sizeof(dword));
@@ -69,7 +69,7 @@ get_dword(const brw_inst *inst, int idx)
}
static void
print_instruction(FILE *output, bool compact, const brw_inst *instruction)
print_instruction(FILE *output, bool compact, const elk_inst *instruction)
{
int byte_limit;
@@ -133,34 +133,34 @@ i965_postprocess_labels()
struct target_label *tlabel;
struct instr_label *ilabel, *s;
const unsigned to_bytes_scale = brw_jump_scale(p->devinfo);
const unsigned to_bytes_scale = elk_jump_scale(p->devinfo);
LIST_FOR_EACH_ENTRY(tlabel, &target_labels, link) {
LIST_FOR_EACH_ENTRY_SAFE(ilabel, s, &instr_labels, link) {
if (!strcmp(tlabel->name, ilabel->name)) {
brw_inst *inst = store + ilabel->offset;
elk_inst *inst = store + ilabel->offset;
int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(brw_inst);
int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(elk_inst);
relative_offset *= to_bytes_scale;
unsigned opcode = brw_inst_opcode(p->isa, inst);
unsigned opcode = elk_inst_opcode(p->isa, inst);
if (ilabel->type == INSTR_LABEL_JIP) {
switch (opcode) {
case BRW_OPCODE_IF:
case BRW_OPCODE_ELSE:
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_WHILE:
case ELK_OPCODE_IF:
case ELK_OPCODE_ELSE:
case ELK_OPCODE_ENDIF:
case ELK_OPCODE_WHILE:
if (p->devinfo->ver >= 7) {
brw_inst_set_jip(p->devinfo, inst, relative_offset);
elk_inst_set_jip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->ver == 6) {
brw_inst_set_gfx6_jump_count(p->devinfo, inst, relative_offset);
elk_inst_set_gfx6_jump_count(p->devinfo, inst, relative_offset);
}
break;
case BRW_OPCODE_BREAK:
case BRW_OPCODE_HALT:
case BRW_OPCODE_CONTINUE:
brw_inst_set_jip(p->devinfo, inst, relative_offset);
case ELK_OPCODE_BREAK:
case ELK_OPCODE_HALT:
case ELK_OPCODE_CONTINUE:
elk_inst_set_jip(p->devinfo, inst, relative_offset);
break;
default:
fprintf(stderr, "Unknown opcode %d with JIP label\n", opcode);
@@ -168,24 +168,24 @@ i965_postprocess_labels()
}
} else {
switch (opcode) {
case BRW_OPCODE_IF:
case BRW_OPCODE_ELSE:
case ELK_OPCODE_IF:
case ELK_OPCODE_ELSE:
if (p->devinfo->ver > 7) {
brw_inst_set_uip(p->devinfo, inst, relative_offset);
elk_inst_set_uip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->ver == 7) {
brw_inst_set_uip(p->devinfo, inst, relative_offset);
elk_inst_set_uip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->ver == 6) {
// Nothing
}
break;
case BRW_OPCODE_WHILE:
case BRW_OPCODE_ENDIF:
case ELK_OPCODE_WHILE:
case ELK_OPCODE_ENDIF:
fprintf(stderr, "WHILE/ENDIF cannot have UIP offset\n");
return false;
case BRW_OPCODE_BREAK:
case BRW_OPCODE_CONTINUE:
case BRW_OPCODE_HALT:
brw_inst_set_uip(p->devinfo, inst, relative_offset);
case ELK_OPCODE_BREAK:
case ELK_OPCODE_CONTINUE:
case ELK_OPCODE_HALT:
elk_inst_set_uip(p->devinfo, inst, relative_offset);
break;
default:
fprintf(stderr, "Unknown opcode %d with UIP label\n", opcode);
@@ -215,7 +215,7 @@ int main(int argc, char **argv)
uint64_t pci_id = 0;
int offset = 0, err;
int start_offset = 0;
struct disasm_info *disasm_info;
struct elk_disasm_info *elk_disasm_info;
struct intel_device_info *devinfo = NULL;
int result = EXIT_FAILURE;
list_inithead(&instr_labels);
@@ -310,11 +310,11 @@ int main(int argc, char **argv)
goto end;
}
struct brw_isa_info isa;
brw_init_isa_info(&isa, devinfo);
struct elk_isa_info isa;
elk_init_isa_info(&isa, devinfo);
p = rzalloc(NULL, struct brw_codegen);
brw_init_codegen(&isa, p, p);
p = rzalloc(NULL, struct elk_codegen);
elk_init_codegen(&isa, p, p);
p->automatic_exec_sizes = false;
err = yyparse();
@@ -326,28 +326,28 @@ int main(int argc, char **argv)
store = p->store;
disasm_info = disasm_initialize(p->isa, NULL);
if (!disasm_info) {
fprintf(stderr, "Unable to initialize disasm_info struct instance\n");
elk_disasm_info = elk_disasm_initialize(p->isa, NULL);
if (!elk_disasm_info) {
fprintf(stderr, "Unable to initialize elk_disasm_info struct instance\n");
goto end;
}
if (output_type == OPT_OUTPUT_C_LITERAL)
fprintf(output, "{\n");
brw_validate_instructions(p->isa, p->store, 0,
p->next_insn_offset, disasm_info);
elk_validate_instructions(p->isa, p->store, 0,
p->next_insn_offset, elk_disasm_info);
const int nr_insn = (p->next_insn_offset - start_offset) / 16;
if (compact)
brw_compact_instructions(p, start_offset, disasm_info);
elk_compact_instructions(p, start_offset, elk_disasm_info);
for (int i = 0; i < nr_insn; i++) {
const brw_inst *insn = store + offset;
const elk_inst *insn = store + offset;
bool compacted = false;
if (compact && brw_inst_cmpt_control(p->devinfo, insn)) {
if (compact && elk_inst_cmpt_control(p->devinfo, insn)) {
offset += 8;
compacted = true;
} else {
@@ -357,7 +357,7 @@ int main(int argc, char **argv)
print_instruction(output, compacted, insn);
}
ralloc_free(disasm_info);
ralloc_free(elk_disasm_info);
if (output_type == OPT_OUTPUT_C_LITERAL)
fprintf(output, "}");
src/intel/compiler/elk/elk_cfg.cpp
+96 -96
View File
@@ -37,25 +37,25 @@
using namespace elk;
static bblock_t *
static elk_bblock_t *
pop_stack(exec_list *list)
{
bblock_link *link = (bblock_link *)list->get_tail();
bblock_t *block = link->block;
elk_bblock_link *link = (elk_bblock_link *)list->get_tail();
elk_bblock_t *block = link->block;
link->link.remove();
return block;
}
static exec_node *
link(void *mem_ctx, bblock_t *block, enum bblock_link_kind kind)
link(void *mem_ctx, elk_bblock_t *block, enum bblock_link_kind kind)
{
bblock_link *l = new(mem_ctx) bblock_link(block, kind);
elk_bblock_link *l = new(mem_ctx) elk_bblock_link(block, kind);
return &l->link;
}
void
push_stack(exec_list *list, void *mem_ctx, bblock_t *block)
push_stack(exec_list *list, void *mem_ctx, elk_bblock_t *block)
{
/* The kind of the link is immaterial, but we need to provide one since
* this is (ab)using the edge data structure in order to implement a stack.
@@ -63,7 +63,7 @@ push_stack(exec_list *list, void *mem_ctx, bblock_t *block)
list->push_tail(link(mem_ctx, block, bblock_link_logical));
}
bblock_t::bblock_t(cfg_t *cfg) :
elk_bblock_t::elk_bblock_t(elk_cfg_t *cfg) :
cfg(cfg), start_ip(0), end_ip(0), end_ip_delta(0), num(0)
{
instructions.make_empty();
@@ -72,7 +72,7 @@ bblock_t::bblock_t(cfg_t *cfg) :
}
void
bblock_t::add_successor(void *mem_ctx, bblock_t *successor,
elk_bblock_t::add_successor(void *mem_ctx, elk_bblock_t *successor,
enum bblock_link_kind kind)
{
successor->parents.push_tail(::link(mem_ctx, this, kind));
@@ -80,10 +80,10 @@ bblock_t::add_successor(void *mem_ctx, bblock_t *successor,
}
bool
bblock_t::is_predecessor_of(const bblock_t *block,
elk_bblock_t::is_predecessor_of(const elk_bblock_t *block,
enum bblock_link_kind kind) const
{
foreach_list_typed_safe (bblock_link, parent, link, &block->parents) {
foreach_list_typed_safe (elk_bblock_link, parent, link, &block->parents) {
if (parent->block == this && parent->kind <= kind) {
return true;
}
@@ -93,10 +93,10 @@ bblock_t::is_predecessor_of(const bblock_t *block,
}
bool
bblock_t::is_successor_of(const bblock_t *block,
elk_bblock_t::is_successor_of(const elk_bblock_t *block,
enum bblock_link_kind kind) const
{
foreach_list_typed_safe (bblock_link, child, link, &block->children) {
foreach_list_typed_safe (elk_bblock_link, child, link, &block->children) {
if (child->block == this && child->kind <= kind) {
return true;
}
@@ -106,31 +106,31 @@ bblock_t::is_successor_of(const bblock_t *block,
}
static bool
ends_block(const backend_instruction *inst)
ends_block(const elk_backend_instruction *inst)
{
enum opcode op = inst->opcode;
enum elk_opcode op = inst->opcode;
return op == BRW_OPCODE_IF ||
op == BRW_OPCODE_ELSE ||
op == BRW_OPCODE_CONTINUE ||
op == BRW_OPCODE_BREAK ||
op == BRW_OPCODE_DO ||
op == BRW_OPCODE_WHILE;
return op == ELK_OPCODE_IF ||
op == ELK_OPCODE_ELSE ||
op == ELK_OPCODE_CONTINUE ||
op == ELK_OPCODE_BREAK ||
op == ELK_OPCODE_DO ||
op == ELK_OPCODE_WHILE;
}
static bool
starts_block(const backend_instruction *inst)
starts_block(const elk_backend_instruction *inst)
{
enum opcode op = inst->opcode;
enum elk_opcode op = inst->opcode;
return op == BRW_OPCODE_DO ||
op == BRW_OPCODE_ENDIF;
return op == ELK_OPCODE_DO ||
op == ELK_OPCODE_ENDIF;
}
bool
bblock_t::can_combine_with(const bblock_t *that) const
elk_bblock_t::can_combine_with(const elk_bblock_t *that) const
{
if ((const bblock_t *)this->link.next != that)
if ((const elk_bblock_t *)this->link.next != that)
return false;
if (ends_block(this->end()) ||
@@ -141,10 +141,10 @@ bblock_t::can_combine_with(const bblock_t *that) const
}
void
bblock_t::combine_with(bblock_t *that)
elk_bblock_t::combine_with(elk_bblock_t *that)
{
assert(this->can_combine_with(that));
foreach_list_typed (bblock_link, link, link, &that->parents) {
foreach_list_typed (elk_bblock_link, link, link, &that->parents) {
assert(link->block == this);
}
@@ -155,12 +155,12 @@ bblock_t::combine_with(bblock_t *that)
}
void
bblock_t::dump(FILE *file) const
elk_bblock_t::dump(FILE *file) const
{
const backend_shader *s = this->cfg->s;
const elk_backend_shader *s = this->cfg->s;
int ip = this->start_ip;
foreach_inst_in_block(backend_instruction, inst, this) {
foreach_inst_in_block(elk_backend_instruction, inst, this) {
fprintf(file, "%5d: ", ip);
s->dump_instruction(inst, file);
ip++;
@@ -168,16 +168,16 @@ bblock_t::dump(FILE *file) const
}
void
bblock_t::unlink_list(exec_list *list)
elk_bblock_t::unlink_list(exec_list *list)
{
assert(list == &parents || list == &children);
const bool remove_parent = list == &children;
foreach_list_typed_safe(bblock_link, link, link, list) {
foreach_list_typed_safe(elk_bblock_link, link, link, list) {
/* Also break the links from the other block back to this block. */
exec_list *sub_list = remove_parent ? &link->block->parents : &link->block->children;
foreach_list_typed_safe(bblock_link, sub_link, link, sub_list) {
foreach_list_typed_safe(elk_bblock_link, sub_link, link, sub_list) {
if (sub_link->block == this) {
sub_link->link.remove();
ralloc_free(sub_link);
@@ -189,7 +189,7 @@ bblock_t::unlink_list(exec_list *list)
}
}
cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
elk_cfg_t::elk_cfg_t(const elk_backend_shader *s, exec_list *instructions) :
s(s)
{
mem_ctx = ralloc_context(NULL);
@@ -197,27 +197,27 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
blocks = NULL;
num_blocks = 0;
bblock_t *cur = NULL;
elk_bblock_t *cur = NULL;
int ip = 0;
bblock_t *entry = new_block();
bblock_t *cur_if = NULL; /**< BB ending with IF. */
bblock_t *cur_else = NULL; /**< BB ending with ELSE. */
bblock_t *cur_do = NULL; /**< BB starting with DO. */
bblock_t *cur_while = NULL; /**< BB immediately following WHILE. */
elk_bblock_t *entry = new_block();
elk_bblock_t *cur_if = NULL; /**< BB ending with IF. */
elk_bblock_t *cur_else = NULL; /**< BB ending with ELSE. */
elk_bblock_t *cur_do = NULL; /**< BB starting with DO. */
elk_bblock_t *cur_while = NULL; /**< BB immediately following WHILE. */
exec_list if_stack, else_stack, do_stack, while_stack;
bblock_t *next;
elk_bblock_t *next;
set_next_block(&cur, entry, ip);
foreach_in_list_safe(backend_instruction, inst, instructions) {
foreach_in_list_safe(elk_backend_instruction, inst, instructions) {
/* set_next_block wants the post-incremented ip */
ip++;
inst->exec_node::remove();
switch (inst->opcode) {
case BRW_OPCODE_IF:
case ELK_OPCODE_IF:
cur->instructions.push_tail(inst);
/* Push our information onto a stack so we can recover from
@@ -238,7 +238,7 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
set_next_block(&cur, next, ip);
break;
case BRW_OPCODE_ELSE:
case ELK_OPCODE_ELSE:
cur->instructions.push_tail(inst);
cur_else = cur;
@@ -251,8 +251,8 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
set_next_block(&cur, next, ip);
break;
case BRW_OPCODE_ENDIF: {
bblock_t *cur_endif;
case ELK_OPCODE_ENDIF: {
elk_bblock_t *cur_endif;
if (cur->instructions.is_empty()) {
/* New block was just created; use it. */
@@ -274,15 +274,15 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
cur_if->add_successor(mem_ctx, cur_endif, bblock_link_logical);
}
assert(cur_if->end()->opcode == BRW_OPCODE_IF);
assert(!cur_else || cur_else->end()->opcode == BRW_OPCODE_ELSE);
assert(cur_if->end()->opcode == ELK_OPCODE_IF);
assert(!cur_else || cur_else->end()->opcode == ELK_OPCODE_ELSE);
/* Pop the stack so we're in the previous if/else/endif */
cur_if = pop_stack(&if_stack);
cur_else = pop_stack(&else_stack);
break;
}
case BRW_OPCODE_DO:
case ELK_OPCODE_DO:
/* Push our information onto a stack so we can recover from
* nested loops.
*/
@@ -339,7 +339,7 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
set_next_block(&cur, next, ip);
break;
case BRW_OPCODE_CONTINUE:
case ELK_OPCODE_CONTINUE:
cur->instructions.push_tail(inst);
/* A conditional CONTINUE may start a region of divergent control
@@ -367,7 +367,7 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
set_next_block(&cur, next, ip);
break;
case BRW_OPCODE_BREAK:
case ELK_OPCODE_BREAK:
cur->instructions.push_tail(inst);
/* A conditional BREAK instruction may start a region of divergent
@@ -393,7 +393,7 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
set_next_block(&cur, next, ip);
break;
case BRW_OPCODE_WHILE:
case ELK_OPCODE_WHILE:
cur->instructions.push_tail(inst);
assert(cur_do != NULL && cur_while != NULL);
@@ -431,16 +431,16 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
make_block_array();
}
cfg_t::~cfg_t()
elk_cfg_t::~elk_cfg_t()
{
ralloc_free(mem_ctx);
}
void
cfg_t::remove_block(bblock_t *block)
elk_cfg_t::remove_block(elk_bblock_t *block)
{
foreach_list_typed_safe (bblock_link, predecessor, link, &block->parents) {
/* cfg_t::validate checks that predecessor and successor lists are well
foreach_list_typed_safe (elk_bblock_link, predecessor, link, &block->parents) {
/* elk_cfg_t::validate checks that predecessor and successor lists are well
* formed, so it is known that the loop here would find exactly one
* block. Set old_link_kind to silence "variable used but not set"
* warnings.
@@ -448,7 +448,7 @@ cfg_t::remove_block(bblock_t *block)
bblock_link_kind old_link_kind = bblock_link_logical;
/* Remove block from all of its predecessors' successor lists. */
foreach_list_typed_safe (bblock_link, successor, link,
foreach_list_typed_safe (elk_bblock_link, successor, link,
&predecessor->block->children) {
if (block == successor->block) {
old_link_kind = successor->kind;
@@ -459,11 +459,11 @@ cfg_t::remove_block(bblock_t *block)
}
/* Add removed-block's successors to its predecessors' successor lists. */
foreach_list_typed (bblock_link, successor, link, &block->children) {
foreach_list_typed (elk_bblock_link, successor, link, &block->children) {
bool need_to_link = true;
bblock_link_kind new_link_kind = MAX2(old_link_kind, successor->kind);
foreach_list_typed_safe (bblock_link, child, link, &predecessor->block->children) {
foreach_list_typed_safe (elk_bblock_link, child, link, &predecessor->block->children) {
/* There is already a link between the two blocks. If the links
* are the same kind or the link is logical, do nothing. If the
* existing link is physical and the proposed new link is logical,
@@ -487,8 +487,8 @@ cfg_t::remove_block(bblock_t *block)
}
}
foreach_list_typed_safe (bblock_link, successor, link, &block->children) {
/* cfg_t::validate checks that predecessor and successor lists are well
foreach_list_typed_safe (elk_bblock_link, successor, link, &block->children) {
/* elk_cfg_t::validate checks that predecessor and successor lists are well
* formed, so it is known that the loop here would find exactly one
* block. Set old_link_kind to silence "variable used but not set"
* warnings.
@@ -496,7 +496,7 @@ cfg_t::remove_block(bblock_t *block)
bblock_link_kind old_link_kind = bblock_link_logical;
/* Remove block from all of its childrens' parents lists. */
foreach_list_typed_safe (bblock_link, predecessor, link,
foreach_list_typed_safe (elk_bblock_link, predecessor, link,
&successor->block->parents) {
if (block == predecessor->block) {
old_link_kind = predecessor->kind;
@@ -506,11 +506,11 @@ cfg_t::remove_block(bblock_t *block)
}
/* Add removed-block's predecessors to its successors' predecessor lists. */
foreach_list_typed (bblock_link, predecessor, link, &block->parents) {
foreach_list_typed (elk_bblock_link, predecessor, link, &block->parents) {
bool need_to_link = true;
bblock_link_kind new_link_kind = MAX2(old_link_kind, predecessor->kind);
foreach_list_typed_safe (bblock_link, parent, link, &successor->block->parents) {
foreach_list_typed_safe (elk_bblock_link, parent, link, &successor->block->parents) {
/* There is already a link between the two blocks. If the links
* are the same kind or the link is logical, do nothing. If the
* existing link is physical and the proposed new link is logical,
@@ -545,16 +545,16 @@ cfg_t::remove_block(bblock_t *block)
this->num_blocks--;
}
bblock_t *
cfg_t::new_block()
elk_bblock_t *
elk_cfg_t::new_block()
{
bblock_t *block = new(mem_ctx) bblock_t(this);
elk_bblock_t *block = new(mem_ctx) elk_bblock_t(this);
return block;
}
void
cfg_t::set_next_block(bblock_t **cur, bblock_t *block, int ip)
elk_cfg_t::set_next_block(elk_bblock_t **cur, elk_bblock_t *block, int ip)
{
if (*cur) {
(*cur)->end_ip = ip - 1;
@@ -567,9 +567,9 @@ cfg_t::set_next_block(bblock_t **cur, bblock_t *block, int ip)
}
void
cfg_t::make_block_array()
elk_cfg_t::make_block_array()
{
blocks = ralloc_array(mem_ctx, bblock_t *, num_blocks);
blocks = ralloc_array(mem_ctx, elk_bblock_t *, num_blocks);
int i = 0;
foreach_block (block, this) {
@@ -602,7 +602,7 @@ void
sort_links(util_dynarray *scratch, exec_list *list)
{
util_dynarray_clear(scratch);
foreach_list_typed(bblock_link, link, link, list) {
foreach_list_typed(elk_bblock_link, link, link, list) {
link_desc l;
l.kind = link->kind == bblock_link_logical ? '-' : '~';
l.num = link->block->num;
@@ -615,7 +615,7 @@ sort_links(util_dynarray *scratch, exec_list *list)
} /* namespace */
void
cfg_t::dump(FILE *file)
elk_cfg_t::dump(FILE *file)
{
const idom_tree *idom = (s ? &s->idom_analysis.require() : NULL);
@@ -658,9 +658,9 @@ cfg_t::dump(FILE *file)
* (less than 1000 nodes) that this algorithm is significantly faster than
* others like Lengauer-Tarjan.
*/
idom_tree::idom_tree(const backend_shader *s) :
idom_tree::idom_tree(const elk_backend_shader *s) :
num_parents(s->cfg->num_blocks),
parents(new bblock_t *[num_parents]())
parents(new elk_bblock_t *[num_parents]())
{
bool changed;
@@ -673,8 +673,8 @@ idom_tree::idom_tree(const backend_shader *s) :
if (block->num == 0)
continue;
bblock_t *new_idom = NULL;
foreach_list_typed(bblock_link, parent_link, link, &block->parents) {
elk_bblock_t *new_idom = NULL;
foreach_list_typed(elk_bblock_link, parent_link, link, &block->parents) {
if (parent(parent_link->block)) {
new_idom = (new_idom ? intersect(new_idom, parent_link->block) :
parent_link->block);
@@ -694,8 +694,8 @@ idom_tree::~idom_tree()
delete[] parents;
}
bblock_t *
idom_tree::intersect(bblock_t *b1, bblock_t *b2) const
elk_bblock_t *
idom_tree::intersect(elk_bblock_t *b1, elk_bblock_t *b2) const
{
/* Note, the comparisons here are the opposite of what the paper says
* because we index blocks from beginning -> end (i.e. reverse post-order)
@@ -721,13 +721,13 @@ idom_tree::dump() const
}
void
cfg_t::dump_cfg()
elk_cfg_t::dump_cfg()
{
printf("digraph CFG {\n");
for (int b = 0; b < num_blocks; b++) {
bblock_t *block = this->blocks[b];
elk_bblock_t *block = this->blocks[b];
foreach_list_typed_safe (bblock_link, child, link, &block->children) {
foreach_list_typed_safe (elk_bblock_link, child, link, &block->children) {
printf("\t%d -> %d\n", b, child->block->num);
}
}
@@ -745,17 +745,17 @@ cfg_t::dump_cfg()
#ifndef NDEBUG
void
cfg_t::validate(const char *stage_abbrev)
elk_cfg_t::validate(const char *stage_abbrev)
{
foreach_block(block, this) {
foreach_list_typed(bblock_link, successor, link, &block->children) {
foreach_list_typed(elk_bblock_link, successor, link, &block->children) {
/* Each successor of a block must have one predecessor link back to
* the block.
*/
bool successor_links_back_to_predecessor = false;
bblock_t *succ_block = successor->block;
elk_bblock_t *succ_block = successor->block;
foreach_list_typed(bblock_link, predecessor, link, &succ_block->parents) {
foreach_list_typed(elk_bblock_link, predecessor, link, &succ_block->parents) {
if (predecessor->block == block) {
cfgv_assert(!successor_links_back_to_predecessor);
cfgv_assert(successor->kind == predecessor->kind);
@@ -768,20 +768,20 @@ cfg_t::validate(const char *stage_abbrev)
/* Each successor block must appear only once in the list of
* successors.
*/
foreach_list_typed_from(bblock_link, later_successor, link,
foreach_list_typed_from(elk_bblock_link, later_successor, link,
&block->children, successor->link.next) {
cfgv_assert(successor->block != later_successor->block);
}
}
foreach_list_typed(bblock_link, predecessor, link, &block->parents) {
foreach_list_typed(elk_bblock_link, predecessor, link, &block->parents) {
/* Each predecessor of a block must have one successor link back to
* the block.
*/
bool predecessor_links_back_to_successor = false;
bblock_t *pred_block = predecessor->block;
elk_bblock_t *pred_block = predecessor->block;
foreach_list_typed(bblock_link, successor, link, &pred_block->children) {
foreach_list_typed(elk_bblock_link, successor, link, &pred_block->children) {
if (successor->block == block) {
cfgv_assert(!predecessor_links_back_to_successor);
cfgv_assert(successor->kind == predecessor->kind);
@@ -794,14 +794,14 @@ cfg_t::validate(const char *stage_abbrev)
/* Each precessor block must appear only once in the list of
* precessors.
*/
foreach_list_typed_from(bblock_link, later_precessor, link,
foreach_list_typed_from(elk_bblock_link, later_precessor, link,
&block->parents, predecessor->link.next) {
cfgv_assert(predecessor->block != later_precessor->block);
}
}
backend_instruction *first_inst = block->start();
if (first_inst->opcode == BRW_OPCODE_DO) {
elk_backend_instruction *first_inst = block->start();
if (first_inst->opcode == ELK_OPCODE_DO) {
/* DO instructions both begin and end a block, so the DO instruction
* must be the only instruction in the block.
*/
@@ -812,10 +812,10 @@ cfg_t::validate(const char *stage_abbrev)
* instruction. The other is a logical link to the block starting the
* body of the loop.
*/
bblock_t *physical_block = nullptr;
bblock_t *logical_block = nullptr;
elk_bblock_t *physical_block = nullptr;
elk_bblock_t *logical_block = nullptr;
foreach_list_typed(bblock_link, child, link, &block->children) {
foreach_list_typed(elk_bblock_link, child, link, &block->children) {
if (child->kind == bblock_link_physical) {
cfgv_assert(physical_block == nullptr);
physical_block = child->block;
src/intel/compiler/elk/elk_cfg.h
+140 -140
View File
@@ -33,7 +33,7 @@
#include "elk_ir_analysis.h"
#endif
struct bblock_t;
struct elk_bblock_t;
/**
* CFG edge types.
@@ -53,18 +53,18 @@ enum bblock_link_kind {
bblock_link_physical
};
struct bblock_link {
struct elk_bblock_link {
#ifdef __cplusplus
DECLARE_RALLOC_CXX_OPERATORS(bblock_link)
DECLARE_RALLOC_CXX_OPERATORS(elk_bblock_link)
bblock_link(bblock_t *block, enum bblock_link_kind kind)
elk_bblock_link(elk_bblock_t *block, enum bblock_link_kind kind)
: block(block), kind(kind)
{
}
#endif
struct exec_node link;
struct bblock_t *block;
struct elk_bblock_t *block;
/* Type of this CFG edge. Because bblock_link_logical also implies
* bblock_link_physical, the proper way to test for membership of edge 'l'
@@ -73,40 +73,40 @@ struct bblock_link {
enum bblock_link_kind kind;
};
struct backend_shader;
struct cfg_t;
struct elk_backend_shader;
struct elk_cfg_t;
struct bblock_t {
struct elk_bblock_t {
#ifdef __cplusplus
DECLARE_RALLOC_CXX_OPERATORS(bblock_t)
DECLARE_RALLOC_CXX_OPERATORS(elk_bblock_t)
explicit bblock_t(cfg_t *cfg);
explicit elk_bblock_t(elk_cfg_t *cfg);
void add_successor(void *mem_ctx, bblock_t *successor,
void add_successor(void *mem_ctx, elk_bblock_t *successor,
enum bblock_link_kind kind);
bool is_predecessor_of(const bblock_t *block,
bool is_predecessor_of(const elk_bblock_t *block,
enum bblock_link_kind kind) const;
bool is_successor_of(const bblock_t *block,
bool is_successor_of(const elk_bblock_t *block,
enum bblock_link_kind kind) const;
bool can_combine_with(const bblock_t *that) const;
void combine_with(bblock_t *that);
bool can_combine_with(const elk_bblock_t *that) const;
void combine_with(elk_bblock_t *that);
void dump(FILE *file = stderr) const;
backend_instruction *start();
const backend_instruction *start() const;
backend_instruction *end();
const backend_instruction *end() const;
elk_backend_instruction *start();
const elk_backend_instruction *start() const;
elk_backend_instruction *end();
const elk_backend_instruction *end() const;
bblock_t *next();
const bblock_t *next() const;
bblock_t *prev();
const bblock_t *prev() const;
elk_bblock_t *next();
const elk_bblock_t *next() const;
elk_bblock_t *prev();
const elk_bblock_t *prev() const;
bool starts_with_control_flow() const;
bool ends_with_control_flow() const;
backend_instruction *first_non_control_flow_inst();
backend_instruction *last_non_control_flow_inst();
elk_backend_instruction *first_non_control_flow_inst();
elk_backend_instruction *last_non_control_flow_inst();
private:
/**
@@ -127,7 +127,7 @@ public:
#endif
struct exec_node link;
struct cfg_t *cfg;
struct elk_cfg_t *cfg;
int start_ip;
int end_ip;
@@ -143,200 +143,200 @@ public:
int num;
};
static inline struct backend_instruction *
bblock_start(struct bblock_t *block)
static inline struct elk_backend_instruction *
bblock_start(struct elk_bblock_t *block)
{
return (struct backend_instruction *)exec_list_get_head(&block->instructions);
return (struct elk_backend_instruction *)exec_list_get_head(&block->instructions);
}
static inline const struct backend_instruction *
bblock_start_const(const struct bblock_t *block)
static inline const struct elk_backend_instruction *
bblock_start_const(const struct elk_bblock_t *block)
{
return (const struct backend_instruction *)exec_list_get_head_const(&block->instructions);
return (const struct elk_backend_instruction *)exec_list_get_head_const(&block->instructions);
}
static inline struct backend_instruction *
bblock_end(struct bblock_t *block)
static inline struct elk_backend_instruction *
bblock_end(struct elk_bblock_t *block)
{
return (struct backend_instruction *)exec_list_get_tail(&block->instructions);
return (struct elk_backend_instruction *)exec_list_get_tail(&block->instructions);
}
static inline const struct backend_instruction *
bblock_end_const(const struct bblock_t *block)
static inline const struct elk_backend_instruction *
bblock_end_const(const struct elk_bblock_t *block)
{
return (const struct backend_instruction *)exec_list_get_tail_const(&block->instructions);
return (const struct elk_backend_instruction *)exec_list_get_tail_const(&block->instructions);
}
static inline struct bblock_t *
bblock_next(struct bblock_t *block)
static inline struct elk_bblock_t *
bblock_next(struct elk_bblock_t *block)
{
if (exec_node_is_tail_sentinel(block->link.next))
return NULL;
return (struct bblock_t *)block->link.next;
return (struct elk_bblock_t *)block->link.next;
}
static inline const struct bblock_t *
bblock_next_const(const struct bblock_t *block)
static inline const struct elk_bblock_t *
bblock_next_const(const struct elk_bblock_t *block)
{
if (exec_node_is_tail_sentinel(block->link.next))
return NULL;
return (const struct bblock_t *)block->link.next;
return (const struct elk_bblock_t *)block->link.next;
}
static inline struct bblock_t *
bblock_prev(struct bblock_t *block)
static inline struct elk_bblock_t *
bblock_prev(struct elk_bblock_t *block)
{
if (exec_node_is_head_sentinel(block->link.prev))
return NULL;
return (struct bblock_t *)block->link.prev;
return (struct elk_bblock_t *)block->link.prev;
}
static inline const struct bblock_t *
bblock_prev_const(const struct bblock_t *block)
static inline const struct elk_bblock_t *
bblock_prev_const(const struct elk_bblock_t *block)
{
if (exec_node_is_head_sentinel(block->link.prev))
return NULL;
return (const struct bblock_t *)block->link.prev;
return (const struct elk_bblock_t *)block->link.prev;
}
static inline bool
bblock_starts_with_control_flow(const struct bblock_t *block)
bblock_starts_with_control_flow(const struct elk_bblock_t *block)
{
enum opcode op = bblock_start_const(block)->opcode;
return op == BRW_OPCODE_DO || op == BRW_OPCODE_ENDIF;
enum elk_opcode op = bblock_start_const(block)->opcode;
return op == ELK_OPCODE_DO || op == ELK_OPCODE_ENDIF;
}
static inline bool
bblock_ends_with_control_flow(const struct bblock_t *block)
bblock_ends_with_control_flow(const struct elk_bblock_t *block)
{
enum opcode op = bblock_end_const(block)->opcode;
return op == BRW_OPCODE_IF ||
op == BRW_OPCODE_ELSE ||
op == BRW_OPCODE_WHILE ||
op == BRW_OPCODE_BREAK ||
op == BRW_OPCODE_CONTINUE;
enum elk_opcode op = bblock_end_const(block)->opcode;
return op == ELK_OPCODE_IF ||
op == ELK_OPCODE_ELSE ||
op == ELK_OPCODE_WHILE ||
op == ELK_OPCODE_BREAK ||
op == ELK_OPCODE_CONTINUE;
}
static inline struct backend_instruction *
bblock_first_non_control_flow_inst(struct bblock_t *block)
static inline struct elk_backend_instruction *
bblock_first_non_control_flow_inst(struct elk_bblock_t *block)
{
struct backend_instruction *inst = bblock_start(block);
struct elk_backend_instruction *inst = bblock_start(block);
if (bblock_starts_with_control_flow(block))
#ifdef __cplusplus
inst = (struct backend_instruction *)inst->next;
inst = (struct elk_backend_instruction *)inst->next;
#else
inst = (struct backend_instruction *)inst->link.next;
inst = (struct elk_backend_instruction *)inst->link.next;
#endif
return inst;
}
static inline struct backend_instruction *
bblock_last_non_control_flow_inst(struct bblock_t *block)
static inline struct elk_backend_instruction *
bblock_last_non_control_flow_inst(struct elk_bblock_t *block)
{
struct backend_instruction *inst = bblock_end(block);
struct elk_backend_instruction *inst = bblock_end(block);
if (bblock_ends_with_control_flow(block))
#ifdef __cplusplus
inst = (struct backend_instruction *)inst->prev;
inst = (struct elk_backend_instruction *)inst->prev;
#else
inst = (struct backend_instruction *)inst->link.prev;
inst = (struct elk_backend_instruction *)inst->link.prev;
#endif
return inst;
}
#ifdef __cplusplus
inline backend_instruction *
bblock_t::start()
inline elk_backend_instruction *
elk_bblock_t::start()
{
return bblock_start(this);
}
inline const backend_instruction *
bblock_t::start() const
inline const elk_backend_instruction *
elk_bblock_t::start() const
{
return bblock_start_const(this);
}
inline backend_instruction *
bblock_t::end()
inline elk_backend_instruction *
elk_bblock_t::end()
{
return bblock_end(this);
}
inline const backend_instruction *
bblock_t::end() const
inline const elk_backend_instruction *
elk_bblock_t::end() const
{
return bblock_end_const(this);
}
inline bblock_t *
bblock_t::next()
inline elk_bblock_t *
elk_bblock_t::next()
{
return bblock_next(this);
}
inline const bblock_t *
bblock_t::next() const
inline const elk_bblock_t *
elk_bblock_t::next() const
{
return bblock_next_const(this);
}
inline bblock_t *
bblock_t::prev()
inline elk_bblock_t *
elk_bblock_t::prev()
{
return bblock_prev(this);
}
inline const bblock_t *
bblock_t::prev() const
inline const elk_bblock_t *
elk_bblock_t::prev() const
{
return bblock_prev_const(this);
}
inline bool
bblock_t::starts_with_control_flow() const
elk_bblock_t::starts_with_control_flow() const
{
return bblock_starts_with_control_flow(this);
}
inline bool
bblock_t::ends_with_control_flow() const
elk_bblock_t::ends_with_control_flow() const
{
return bblock_ends_with_control_flow(this);
}
inline backend_instruction *
bblock_t::first_non_control_flow_inst()
inline elk_backend_instruction *
elk_bblock_t::first_non_control_flow_inst()
{
return bblock_first_non_control_flow_inst(this);
}
inline backend_instruction *
bblock_t::last_non_control_flow_inst()
inline elk_backend_instruction *
elk_bblock_t::last_non_control_flow_inst()
{
return bblock_last_non_control_flow_inst(this);
}
#endif
struct cfg_t {
struct elk_cfg_t {
#ifdef __cplusplus
DECLARE_RALLOC_CXX_OPERATORS(cfg_t)
DECLARE_RALLOC_CXX_OPERATORS(elk_cfg_t)
cfg_t(const backend_shader *s, exec_list *instructions);
~cfg_t();
elk_cfg_t(const elk_backend_shader *s, exec_list *instructions);
~elk_cfg_t();
void remove_block(bblock_t *block);
void remove_block(elk_bblock_t *block);
bblock_t *first_block();
const bblock_t *first_block() const;
bblock_t *last_block();
const bblock_t *last_block() const;
elk_bblock_t *first_block();
const elk_bblock_t *first_block() const;
elk_bblock_t *last_block();
const elk_bblock_t *last_block() const;
bblock_t *new_block();
void set_next_block(bblock_t **cur, bblock_t *block, int ip);
elk_bblock_t *new_block();
void set_next_block(elk_bblock_t **cur, elk_bblock_t *block, int ip);
void make_block_array();
void dump(FILE *file = stderr);
@@ -349,65 +349,65 @@ struct cfg_t {
#endif
/**
* Propagate bblock_t::end_ip_delta data through the CFG.
* Propagate elk_bblock_t::end_ip_delta data through the CFG.
*/
inline void adjust_block_ips();
#endif
const struct backend_shader *s;
const struct elk_backend_shader *s;
void *mem_ctx;
/** Ordered list (by ip) of basic blocks */
struct exec_list block_list;
struct bblock_t **blocks;
struct elk_bblock_t **blocks;
int num_blocks;
};
static inline struct bblock_t *
cfg_first_block(struct cfg_t *cfg)
static inline struct elk_bblock_t *
cfg_first_block(struct elk_cfg_t *cfg)
{
return (struct bblock_t *)exec_list_get_head(&cfg->block_list);
return (struct elk_bblock_t *)exec_list_get_head(&cfg->block_list);
}
static inline const struct bblock_t *
cfg_first_block_const(const struct cfg_t *cfg)
static inline const struct elk_bblock_t *
cfg_first_block_const(const struct elk_cfg_t *cfg)
{
return (const struct bblock_t *)exec_list_get_head_const(&cfg->block_list);
return (const struct elk_bblock_t *)exec_list_get_head_const(&cfg->block_list);
}
static inline struct bblock_t *
cfg_last_block(struct cfg_t *cfg)
static inline struct elk_bblock_t *
cfg_last_block(struct elk_cfg_t *cfg)
{
return (struct bblock_t *)exec_list_get_tail(&cfg->block_list);
return (struct elk_bblock_t *)exec_list_get_tail(&cfg->block_list);
}
static inline const struct bblock_t *
cfg_last_block_const(const struct cfg_t *cfg)
static inline const struct elk_bblock_t *
cfg_last_block_const(const struct elk_cfg_t *cfg)
{
return (const struct bblock_t *)exec_list_get_tail_const(&cfg->block_list);
return (const struct elk_bblock_t *)exec_list_get_tail_const(&cfg->block_list);
}
#ifdef __cplusplus
inline bblock_t *
cfg_t::first_block()
inline elk_bblock_t *
elk_cfg_t::first_block()
{
return cfg_first_block(this);
}
const inline bblock_t *
cfg_t::first_block() const
const inline elk_bblock_t *
elk_cfg_t::first_block() const
{
return cfg_first_block_const(this);
}
inline bblock_t *
cfg_t::last_block()
inline elk_bblock_t *
elk_cfg_t::last_block()
{
return cfg_last_block(this);
}
const inline bblock_t *
cfg_t::last_block() const
const inline elk_bblock_t *
elk_cfg_t::last_block() const
{
return cfg_last_block_const(this);
}
@@ -428,16 +428,16 @@ cfg_t::last_block() const
foreach_inst_in_block_safe (__type, __inst, __block)
#define foreach_block(__block, __cfg) \
foreach_list_typed (bblock_t, __block, link, &(__cfg)->block_list)
foreach_list_typed (elk_bblock_t, __block, link, &(__cfg)->block_list)
#define foreach_block_reverse(__block, __cfg) \
foreach_list_typed_reverse (bblock_t, __block, link, &(__cfg)->block_list)
foreach_list_typed_reverse (elk_bblock_t, __block, link, &(__cfg)->block_list)
#define foreach_block_safe(__block, __cfg) \
foreach_list_typed_safe (bblock_t, __block, link, &(__cfg)->block_list)
foreach_list_typed_safe (elk_bblock_t, __block, link, &(__cfg)->block_list)
#define foreach_block_reverse_safe(__block, __cfg) \
foreach_list_typed_reverse_safe (bblock_t, __block, link, &(__cfg)->block_list)
foreach_list_typed_reverse_safe (elk_bblock_t, __block, link, &(__cfg)->block_list)
#define foreach_inst_in_block(__type, __inst, __block) \
foreach_in_list(__type, __inst, &(__block)->instructions)
@@ -467,7 +467,7 @@ cfg_t::last_block() const
#ifdef __cplusplus
inline void
cfg_t::adjust_block_ips()
elk_cfg_t::adjust_block_ips()
{
int delta = 0;
@@ -486,11 +486,11 @@ namespace elk {
* Immediate dominator tree analysis of a shader.
*/
struct idom_tree {
idom_tree(const backend_shader *s);
idom_tree(const elk_backend_shader *s);
~idom_tree();
bool
validate(const backend_shader *) const
validate(const elk_backend_shader *) const
{
/* FINISHME */
return true;
@@ -502,29 +502,29 @@ namespace elk {
return DEPENDENCY_BLOCKS;
}
const bblock_t *
parent(const bblock_t *b) const
const elk_bblock_t *
parent(const elk_bblock_t *b) const
{
assert(unsigned(b->num) < num_parents);
return parents[b->num];
}
bblock_t *
parent(bblock_t *b) const
elk_bblock_t *
parent(elk_bblock_t *b) const
{
assert(unsigned(b->num) < num_parents);
return parents[b->num];
}
bblock_t *
intersect(bblock_t *b1, bblock_t *b2) const;
elk_bblock_t *
intersect(elk_bblock_t *b1, elk_bblock_t *b2) const;
void
dump() const;
private:
unsigned num_parents;
bblock_t **parents;
elk_bblock_t **parents;
};
}
#endif
src/intel/compiler/elk/elk_clip.h
+55 -55
View File
@@ -43,37 +43,37 @@
#define PRIM_MASK (0x1f)
struct brw_clip_compile {
struct brw_codegen func;
struct brw_clip_prog_key key;
struct brw_clip_prog_data prog_data;
struct elk_clip_compile {
struct elk_codegen func;
struct elk_clip_prog_key key;
struct elk_clip_prog_data prog_data;
struct {
struct brw_reg R0;
struct brw_reg vertex[MAX_VERTS];
struct elk_reg R0;
struct elk_reg vertex[MAX_VERTS];
struct brw_reg t;
struct brw_reg t0, t1;
struct brw_reg dp0, dp1;
struct elk_reg t;
struct elk_reg t0, t1;
struct elk_reg dp0, dp1;
struct brw_reg dpPrev;
struct brw_reg dp;
struct brw_reg loopcount;
struct brw_reg nr_verts;
struct brw_reg planemask;
struct elk_reg dpPrev;
struct elk_reg dp;
struct elk_reg loopcount;
struct elk_reg nr_verts;
struct elk_reg planemask;
struct brw_reg inlist;
struct brw_reg outlist;
struct brw_reg freelist;
struct elk_reg inlist;
struct elk_reg outlist;
struct elk_reg freelist;
struct brw_reg dir;
struct brw_reg tmp0, tmp1;
struct brw_reg offset;
struct elk_reg dir;
struct elk_reg tmp0, tmp1;
struct elk_reg offset;
struct brw_reg fixed_planes;
struct brw_reg plane_equation;
struct elk_reg fixed_planes;
struct elk_reg plane_equation;
struct brw_reg ff_sync;
struct elk_reg ff_sync;
/* Bitmask indicating which coordinate attribute should be used for
* comparison to each clipping plane. A 0 indicates that VARYING_SLOT_POS
@@ -82,10 +82,10 @@ struct brw_clip_compile {
* VARYING_SLOT_CLIP_VERTEX should be used (if available) since it's a user-
* defined clipping plane.
*/
struct brw_reg vertex_src_mask;
struct elk_reg vertex_src_mask;
/* Offset into the vertex of the current plane's clipdistance value */
struct brw_reg clipdistance_offset;
struct elk_reg clipdistance_offset;
} reg;
/* Number of registers storing VUE data */
@@ -102,7 +102,7 @@ struct brw_clip_compile {
/**
* True if the given varying is one of the outputs of the vertex shader.
*/
static inline bool brw_clip_have_varying(struct brw_clip_compile *c,
static inline bool elk_clip_have_varying(struct elk_clip_compile *c,
GLuint varying)
{
return (c->key.attrs & BITFIELD64_BIT(varying)) ? 1 : 0;
@@ -111,53 +111,53 @@ static inline bool brw_clip_have_varying(struct brw_clip_compile *c,
/* Points are only culled, so no need for a clip routine, however it
* works out easier to have a dummy one.
*/
void brw_emit_unfilled_clip( struct brw_clip_compile *c );
void brw_emit_tri_clip( struct brw_clip_compile *c );
void brw_emit_line_clip( struct brw_clip_compile *c );
void brw_emit_point_clip( struct brw_clip_compile *c );
void elk_emit_unfilled_clip( struct elk_clip_compile *c );
void elk_emit_tri_clip( struct elk_clip_compile *c );
void elk_emit_line_clip( struct elk_clip_compile *c );
void elk_emit_point_clip( struct elk_clip_compile *c );
/* brw_clip_tri.c, for use by the unfilled clip routine:
/* elk_clip_tri.c, for use by the unfilled clip routine:
*/
void brw_clip_tri_init_vertices( struct brw_clip_compile *c );
void brw_clip_tri_flat_shade( struct brw_clip_compile *c );
void brw_clip_tri( struct brw_clip_compile *c );
void brw_clip_tri_emit_polygon( struct brw_clip_compile *c );
void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
void elk_clip_tri_init_vertices( struct elk_clip_compile *c );
void elk_clip_tri_flat_shade( struct elk_clip_compile *c );
void elk_clip_tri( struct elk_clip_compile *c );
void elk_clip_tri_emit_polygon( struct elk_clip_compile *c );
void elk_clip_tri_alloc_regs( struct elk_clip_compile *c,
GLuint nr_verts );
/* Utils:
*/
void brw_clip_interp_vertex( struct brw_clip_compile *c,
struct brw_indirect dest_ptr,
struct brw_indirect v0_ptr, /* from */
struct brw_indirect v1_ptr, /* to */
struct brw_reg t0,
void elk_clip_interp_vertex( struct elk_clip_compile *c,
struct elk_indirect dest_ptr,
struct elk_indirect v0_ptr, /* from */
struct elk_indirect v1_ptr, /* to */
struct elk_reg t0,
bool force_edgeflag );
void brw_clip_init_planes( struct brw_clip_compile *c );
void elk_clip_init_planes( struct elk_clip_compile *c );
void brw_clip_emit_vue(struct brw_clip_compile *c,
struct brw_indirect vert,
enum brw_urb_write_flags flags,
void elk_clip_emit_vue(struct elk_clip_compile *c,
struct elk_indirect vert,
enum elk_urb_write_flags flags,
GLuint header);
void brw_clip_kill_thread(struct brw_clip_compile *c);
void elk_clip_kill_thread(struct elk_clip_compile *c);
struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c );
struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c );
struct elk_reg elk_clip_plane_stride( struct elk_clip_compile *c );
struct elk_reg elk_clip_plane0_address( struct elk_clip_compile *c );
void brw_clip_copy_flatshaded_attributes( struct brw_clip_compile *c,
void elk_clip_copy_flatshaded_attributes( struct elk_clip_compile *c,
GLuint to, GLuint from );
void brw_clip_init_clipmask( struct brw_clip_compile *c );
void elk_clip_init_clipmask( struct elk_clip_compile *c );
struct brw_reg get_tmp( struct brw_clip_compile *c );
struct elk_reg get_tmp( struct elk_clip_compile *c );
void brw_clip_project_position(struct brw_clip_compile *c,
struct brw_reg pos );
void brw_clip_ff_sync(struct brw_clip_compile *c);
void brw_clip_init_ff_sync(struct brw_clip_compile *c);
void elk_clip_project_position(struct elk_clip_compile *c,
struct elk_reg pos );
void elk_clip_ff_sync(struct elk_clip_compile *c);
void elk_clip_init_ff_sync(struct elk_clip_compile *c);
#endif
src/intel/compiler/elk/elk_clip_line.c
+107 -107
View File
@@ -32,17 +32,17 @@
#include "elk_clip.h"
#include "elk_prim.h"
static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
static void elk_clip_line_alloc_regs( struct elk_clip_compile *c )
{
const struct intel_device_info *devinfo = c->func.devinfo;
GLuint i = 0,j;
/* Register usage is static, precompute here:
*/
c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
c->reg.R0 = retype(elk_vec8_grf(i, 0), ELK_REGISTER_TYPE_UD); i++;
if (c->key.nr_userclip) {
c->reg.fixed_planes = brw_vec4_grf(i, 0);
c->reg.fixed_planes = elk_vec4_grf(i, 0);
i += (6 + c->key.nr_userclip + 1) / 2;
c->prog_data.curb_read_length = (6 + c->key.nr_userclip + 1) / 2;
@@ -54,32 +54,32 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
/* Payload vertices plus space for more generated vertices:
*/
for (j = 0; j < 4; j++) {
c->reg.vertex[j] = brw_vec4_grf(i, 0);
c->reg.vertex[j] = elk_vec4_grf(i, 0);
i += c->nr_regs;
}
c->reg.t = brw_vec1_grf(i, 0);
c->reg.t0 = brw_vec1_grf(i, 1);
c->reg.t1 = brw_vec1_grf(i, 2);
c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD);
c->reg.plane_equation = brw_vec4_grf(i, 4);
c->reg.t = elk_vec1_grf(i, 0);
c->reg.t0 = elk_vec1_grf(i, 1);
c->reg.t1 = elk_vec1_grf(i, 2);
c->reg.planemask = retype(elk_vec1_grf(i, 3), ELK_REGISTER_TYPE_UD);
c->reg.plane_equation = elk_vec4_grf(i, 4);
i++;
c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */
c->reg.dp1 = brw_vec1_grf(i, 4);
c->reg.dp0 = elk_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */
c->reg.dp1 = elk_vec1_grf(i, 4);
i++;
if (!c->key.nr_userclip) {
c->reg.fixed_planes = brw_vec8_grf(i, 0);
c->reg.fixed_planes = elk_vec8_grf(i, 0);
i++;
}
c->reg.vertex_src_mask = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W);
c->reg.vertex_src_mask = retype(elk_vec1_grf(i, 0), ELK_REGISTER_TYPE_UD);
c->reg.clipdistance_offset = retype(elk_vec1_grf(i, 1), ELK_REGISTER_TYPE_W);
i++;
if (devinfo->ver == 5) {
c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
c->reg.ff_sync = retype(elk_vec1_grf(i, 0), ELK_REGISTER_TYPE_UD);
i++;
}
@@ -115,111 +115,111 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
* interp( ctx, newvtx1, vtx1, vtx0, t1 );
*
*/
static void clip_and_emit_line( struct brw_clip_compile *c )
static void clip_and_emit_line( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_indirect vtx0 = brw_indirect(0, 0);
struct brw_indirect vtx1 = brw_indirect(1, 0);
struct brw_indirect newvtx0 = brw_indirect(2, 0);
struct brw_indirect newvtx1 = brw_indirect(3, 0);
struct brw_indirect plane_ptr = brw_indirect(4, 0);
struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD);
GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
struct elk_codegen *p = &c->func;
struct elk_indirect vtx0 = elk_indirect(0, 0);
struct elk_indirect vtx1 = elk_indirect(1, 0);
struct elk_indirect newvtx0 = elk_indirect(2, 0);
struct elk_indirect newvtx1 = elk_indirect(3, 0);
struct elk_indirect plane_ptr = elk_indirect(4, 0);
struct elk_reg v1_null_ud = retype(vec1(elk_null_reg()), ELK_REGISTER_TYPE_UD);
GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
GLint clipdist0_offset = c->key.nr_userclip
? brw_varying_to_offset(&c->vue_map, VARYING_SLOT_CLIP_DIST0)
? elk_varying_to_offset(&c->vue_map, VARYING_SLOT_CLIP_DIST0)
: 0;
brw_MOV(p, get_addr_reg(vtx0), brw_address(c->reg.vertex[0]));
brw_MOV(p, get_addr_reg(vtx1), brw_address(c->reg.vertex[1]));
brw_MOV(p, get_addr_reg(newvtx0), brw_address(c->reg.vertex[2]));
brw_MOV(p, get_addr_reg(newvtx1), brw_address(c->reg.vertex[3]));
brw_MOV(p, get_addr_reg(plane_ptr), brw_clip_plane0_address(c));
elk_MOV(p, get_addr_reg(vtx0), elk_address(c->reg.vertex[0]));
elk_MOV(p, get_addr_reg(vtx1), elk_address(c->reg.vertex[1]));
elk_MOV(p, get_addr_reg(newvtx0), elk_address(c->reg.vertex[2]));
elk_MOV(p, get_addr_reg(newvtx1), elk_address(c->reg.vertex[3]));
elk_MOV(p, get_addr_reg(plane_ptr), elk_clip_plane0_address(c));
/* Note: init t0, t1 together:
*/
brw_MOV(p, vec2(c->reg.t0), brw_imm_f(0));
elk_MOV(p, vec2(c->reg.t0), elk_imm_f(0));
brw_clip_init_planes(c);
brw_clip_init_clipmask(c);
elk_clip_init_planes(c);
elk_clip_init_clipmask(c);
/* -ve rhw workaround */
if (p->devinfo->has_negative_rhw_bug) {
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_AND(p, elk_null_reg(), get_element_ud(c->reg.R0, 2),
elk_imm_ud(1<<20));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud(0x3f));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
}
/* Set the initial vertex source mask: The first 6 planes are the bounds
* of the view volume; the next 8 planes are the user clipping planes.
*/
brw_MOV(p, c->reg.vertex_src_mask, brw_imm_ud(0x3fc0));
elk_MOV(p, c->reg.vertex_src_mask, elk_imm_ud(0x3fc0));
/* Set the initial clipdistance offset to be 6 floats before gl_ClipDistance[0].
* We'll increment 6 times before we start hitting actual user clipping. */
brw_MOV(p, c->reg.clipdistance_offset, brw_imm_d(clipdist0_offset - 6*sizeof(float)));
elk_MOV(p, c->reg.clipdistance_offset, elk_imm_d(clipdist0_offset - 6*sizeof(float)));
brw_DO(p, BRW_EXECUTE_1);
elk_DO(p, ELK_EXECUTE_1);
{
/* if (planemask & 1)
*/
brw_AND(p, v1_null_ud, c->reg.planemask, brw_imm_ud(1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
elk_AND(p, v1_null_ud, c->reg.planemask, elk_imm_ud(1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
brw_AND(p, v1_null_ud, c->reg.vertex_src_mask, brw_imm_ud(1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
elk_AND(p, v1_null_ud, c->reg.vertex_src_mask, elk_imm_ud(1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_IF(p, ELK_EXECUTE_1);
{
/* user clip distance: just fetch the correct float from each vertex */
struct brw_indirect temp_ptr = brw_indirect(7, 0);
brw_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx0), c->reg.clipdistance_offset);
brw_MOV(p, c->reg.dp0, deref_1f(temp_ptr, 0));
brw_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx1), c->reg.clipdistance_offset);
brw_MOV(p, c->reg.dp1, deref_1f(temp_ptr, 0));
struct elk_indirect temp_ptr = elk_indirect(7, 0);
elk_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx0), c->reg.clipdistance_offset);
elk_MOV(p, c->reg.dp0, deref_1f(temp_ptr, 0));
elk_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx1), c->reg.clipdistance_offset);
elk_MOV(p, c->reg.dp1, deref_1f(temp_ptr, 0));
}
brw_ELSE(p);
elk_ELSE(p);
{
/* fixed plane: fetch the hpos, dp4 against the plane. */
if (c->key.nr_userclip)
brw_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0));
elk_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0));
else
brw_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0));
elk_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0));
brw_DP4(p, vec4(c->reg.dp0), deref_4f(vtx0, hpos_offset), c->reg.plane_equation);
brw_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1, hpos_offset), c->reg.plane_equation);
elk_DP4(p, vec4(c->reg.dp0), deref_4f(vtx0, hpos_offset), c->reg.plane_equation);
elk_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1, hpos_offset), c->reg.plane_equation);
}
brw_ENDIF(p);
elk_ENDIF(p);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, vec1(c->reg.dp1), brw_imm_f(0.0f));
elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_L, vec1(c->reg.dp1), elk_imm_f(0.0f));
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
/*
* Both can be negative on GM965/G965 due to RHW workaround
* if so, this object should be rejected.
*/
if (p->devinfo->has_negative_rhw_bug) {
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0));
brw_IF(p, BRW_EXECUTE_1);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_LE, c->reg.dp0, elk_imm_f(0.0));
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_kill_thread(c);
elk_clip_kill_thread(c);
}
brw_ENDIF(p);
elk_ENDIF(p);
}
brw_ADD(p, c->reg.t, c->reg.dp1, negate(c->reg.dp0));
brw_math_invert(p, c->reg.t, c->reg.t);
brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp1);
elk_ADD(p, c->reg.t, c->reg.dp1, negate(c->reg.dp0));
elk_math_invert(p, c->reg.t, c->reg.t);
elk_MUL(p, c->reg.t, c->reg.t, c->reg.dp1);
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t1 );
brw_MOV(p, c->reg.t1, c->reg.t);
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
BRW_PREDICATE_NORMAL);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_G, c->reg.t, c->reg.t1 );
elk_MOV(p, c->reg.t1, c->reg.t);
elk_inst_set_pred_control(p->devinfo, elk_last_inst,
ELK_PREDICATE_NORMAL);
}
brw_ELSE(p);
elk_ELSE(p);
{
/* Coming back in. We know that both cannot be negative
* because the line would have been culled in that case.
@@ -228,75 +228,75 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
/* If both are positive, do nothing */
/* Only on GM965/G965 */
if (p->devinfo->has_negative_rhw_bug) {
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
brw_IF(p, BRW_EXECUTE_1);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_L, c->reg.dp0, elk_imm_f(0.0));
elk_IF(p, ELK_EXECUTE_1);
}
{
brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
brw_math_invert(p, c->reg.t, c->reg.t);
brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
elk_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
elk_math_invert(p, c->reg.t, c->reg.t);
elk_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
brw_MOV(p, c->reg.t0, c->reg.t);
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
BRW_PREDICATE_NORMAL);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_G, c->reg.t, c->reg.t0 );
elk_MOV(p, c->reg.t0, c->reg.t);
elk_inst_set_pred_control(p->devinfo, elk_last_inst,
ELK_PREDICATE_NORMAL);
}
if (p->devinfo->has_negative_rhw_bug) {
brw_ENDIF(p);
elk_ENDIF(p);
}
}
brw_ENDIF(p);
elk_ENDIF(p);
}
brw_ENDIF(p);
elk_ENDIF(p);
/* plane_ptr++;
*/
brw_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), brw_clip_plane_stride(c));
elk_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), elk_clip_plane_stride(c));
/* while (planemask>>=1) != 0
*/
brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, brw_imm_ud(1));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, brw_imm_w(sizeof(float)));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_SHR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud(1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, elk_imm_ud(1));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
elk_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, elk_imm_w(sizeof(float)));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
}
brw_WHILE(p);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_WHILE(p);
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
brw_ADD(p, c->reg.t, c->reg.t0, c->reg.t1);
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.t, brw_imm_f(1.0));
brw_IF(p, BRW_EXECUTE_1);
elk_ADD(p, c->reg.t, c->reg.t0, c->reg.t1);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_L, c->reg.t, elk_imm_f(1.0));
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, false);
brw_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, false);
elk_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, false);
elk_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, false);
brw_clip_emit_vue(c, newvtx0, BRW_URB_WRITE_ALLOCATE_COMPLETE,
elk_clip_emit_vue(c, newvtx0, ELK_URB_WRITE_ALLOCATE_COMPLETE,
(_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_START);
brw_clip_emit_vue(c, newvtx1, BRW_URB_WRITE_EOT_COMPLETE,
elk_clip_emit_vue(c, newvtx1, ELK_URB_WRITE_EOT_COMPLETE,
(_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_END);
}
brw_ENDIF(p);
brw_clip_kill_thread(c);
elk_ENDIF(p);
elk_clip_kill_thread(c);
}
void brw_emit_line_clip( struct brw_clip_compile *c )
void elk_emit_line_clip( struct elk_clip_compile *c )
{
brw_clip_line_alloc_regs(c);
brw_clip_init_ff_sync(c);
elk_clip_line_alloc_regs(c);
elk_clip_init_ff_sync(c);
if (c->key.contains_flat_varying) {
if (c->key.pv_first)
brw_clip_copy_flatshaded_attributes(c, 1, 0);
elk_clip_copy_flatshaded_attributes(c, 1, 0);
else
brw_clip_copy_flatshaded_attributes(c, 0, 1);
elk_clip_copy_flatshaded_attributes(c, 0, 1);
}
clip_and_emit_line(c);
src/intel/compiler/elk/elk_clip_point.c
+4 -4
View File
@@ -34,12 +34,12 @@
/* Point clipping, nothing to do?
*/
void brw_emit_point_clip( struct brw_clip_compile *c )
void elk_emit_point_clip( struct elk_clip_compile *c )
{
/* Send an empty message to kill the thread:
*/
brw_clip_tri_alloc_regs(c, 0);
brw_clip_init_ff_sync(c);
elk_clip_tri_alloc_regs(c, 0);
elk_clip_init_ff_sync(c);
brw_clip_kill_thread(c);
elk_clip_kill_thread(c);
}
src/intel/compiler/elk/elk_clip_tri.c
+303 -303
View File
@@ -32,13 +32,13 @@
#include "elk_clip.h"
#include "elk_prim.h"
static void release_tmps( struct brw_clip_compile *c )
static void release_tmps( struct elk_clip_compile *c )
{
c->last_tmp = c->first_tmp;
}
void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
void elk_clip_tri_alloc_regs( struct elk_clip_compile *c,
GLuint nr_verts )
{
const struct intel_device_info *devinfo = c->func.devinfo;
@@ -46,10 +46,10 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
/* Register usage is static, precompute here:
*/
c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
c->reg.R0 = retype(elk_vec8_grf(i, 0), ELK_REGISTER_TYPE_UD); i++;
if (c->key.nr_userclip) {
c->reg.fixed_planes = brw_vec4_grf(i, 0);
c->reg.fixed_planes = elk_vec4_grf(i, 0);
i += (6 + c->key.nr_userclip + 1) / 2;
c->prog_data.curb_read_length = (6 + c->key.nr_userclip + 1) / 2;
@@ -61,7 +61,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
/* Payload vertices plus space for more generated vertices:
*/
for (j = 0; j < nr_verts; j++) {
c->reg.vertex[j] = brw_vec4_grf(i, 0);
c->reg.vertex[j] = elk_vec4_grf(i, 0);
i += c->nr_regs;
}
@@ -70,52 +70,52 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
* used. Fill the second half with zero.
*/
for (j = 0; j < 3; j++) {
GLuint delta = brw_vue_slot_to_offset(c->vue_map.num_slots);
GLuint delta = elk_vue_slot_to_offset(c->vue_map.num_slots);
brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));
elk_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), elk_imm_f(0));
}
}
c->reg.t = brw_vec1_grf(i, 0);
c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D);
c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD);
c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD);
c->reg.plane_equation = brw_vec4_grf(i, 4);
c->reg.t = elk_vec1_grf(i, 0);
c->reg.loopcount = retype(elk_vec1_grf(i, 1), ELK_REGISTER_TYPE_D);
c->reg.nr_verts = retype(elk_vec1_grf(i, 2), ELK_REGISTER_TYPE_UD);
c->reg.planemask = retype(elk_vec1_grf(i, 3), ELK_REGISTER_TYPE_UD);
c->reg.plane_equation = elk_vec4_grf(i, 4);
i++;
c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */
c->reg.dp = brw_vec1_grf(i, 4);
c->reg.dpPrev = elk_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */
c->reg.dp = elk_vec1_grf(i, 4);
i++;
c->reg.inlist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0);
c->reg.inlist = elk_uw16_reg(ELK_GENERAL_REGISTER_FILE, i, 0);
i++;
c->reg.outlist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0);
c->reg.outlist = elk_uw16_reg(ELK_GENERAL_REGISTER_FILE, i, 0);
i++;
c->reg.freelist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0);
c->reg.freelist = elk_uw16_reg(ELK_GENERAL_REGISTER_FILE, i, 0);
i++;
if (!c->key.nr_userclip) {
c->reg.fixed_planes = brw_vec8_grf(i, 0);
c->reg.fixed_planes = elk_vec8_grf(i, 0);
i++;
}
if (c->key.do_unfilled) {
c->reg.dir = brw_vec4_grf(i, 0);
c->reg.offset = brw_vec4_grf(i, 4);
c->reg.dir = elk_vec4_grf(i, 0);
c->reg.offset = elk_vec4_grf(i, 4);
i++;
c->reg.tmp0 = brw_vec4_grf(i, 0);
c->reg.tmp1 = brw_vec4_grf(i, 4);
c->reg.tmp0 = elk_vec4_grf(i, 0);
c->reg.tmp1 = elk_vec4_grf(i, 4);
i++;
}
c->reg.vertex_src_mask = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W);
c->reg.vertex_src_mask = retype(elk_vec1_grf(i, 0), ELK_REGISTER_TYPE_UD);
c->reg.clipdistance_offset = retype(elk_vec1_grf(i, 1), ELK_REGISTER_TYPE_W);
i++;
if (devinfo->ver == 5) {
c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
c->reg.ff_sync = retype(elk_vec1_grf(i, 0), ELK_REGISTER_TYPE_UD);
i++;
}
@@ -128,89 +128,89 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
void brw_clip_tri_init_vertices( struct brw_clip_compile *c )
void elk_clip_tri_init_vertices( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */
struct elk_codegen *p = &c->func;
struct elk_reg tmp0 = c->reg.loopcount; /* handy temporary */
/* Initial list of indices for incoming vertices:
*/
brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
brw_CMP(p,
vec1(brw_null_reg()),
BRW_CONDITIONAL_EQ,
elk_AND(p, tmp0, get_element_ud(c->reg.R0, 2), elk_imm_ud(PRIM_MASK));
elk_CMP(p,
vec1(elk_null_reg()),
ELK_CONDITIONAL_EQ,
tmp0,
brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
elk_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
/* XXX: Is there an easier way to do this? Need to reverse every
* second tristrip element: Can ignore sometimes?
*/
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
brw_MOV(p, get_element(c->reg.inlist, 0), brw_address(c->reg.vertex[1]) );
brw_MOV(p, get_element(c->reg.inlist, 1), brw_address(c->reg.vertex[0]) );
elk_MOV(p, get_element(c->reg.inlist, 0), elk_address(c->reg.vertex[1]) );
elk_MOV(p, get_element(c->reg.inlist, 1), elk_address(c->reg.vertex[0]) );
if (c->need_direction)
brw_MOV(p, c->reg.dir, brw_imm_f(-1));
elk_MOV(p, c->reg.dir, elk_imm_f(-1));
}
brw_ELSE(p);
elk_ELSE(p);
{
brw_MOV(p, get_element(c->reg.inlist, 0), brw_address(c->reg.vertex[0]) );
brw_MOV(p, get_element(c->reg.inlist, 1), brw_address(c->reg.vertex[1]) );
elk_MOV(p, get_element(c->reg.inlist, 0), elk_address(c->reg.vertex[0]) );
elk_MOV(p, get_element(c->reg.inlist, 1), elk_address(c->reg.vertex[1]) );
if (c->need_direction)
brw_MOV(p, c->reg.dir, brw_imm_f(1));
elk_MOV(p, c->reg.dir, elk_imm_f(1));
}
brw_ENDIF(p);
elk_ENDIF(p);
brw_MOV(p, get_element(c->reg.inlist, 2), brw_address(c->reg.vertex[2]) );
brw_MOV(p, brw_vec8_grf(c->reg.outlist.nr, 0), brw_imm_f(0));
brw_MOV(p, c->reg.nr_verts, brw_imm_ud(3));
elk_MOV(p, get_element(c->reg.inlist, 2), elk_address(c->reg.vertex[2]) );
elk_MOV(p, elk_vec8_grf(c->reg.outlist.nr, 0), elk_imm_f(0));
elk_MOV(p, c->reg.nr_verts, elk_imm_ud(3));
}
void brw_clip_tri_flat_shade( struct brw_clip_compile *c )
void elk_clip_tri_flat_shade( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */
struct elk_codegen *p = &c->func;
struct elk_reg tmp0 = c->reg.loopcount; /* handy temporary */
brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
brw_CMP(p,
vec1(brw_null_reg()),
BRW_CONDITIONAL_EQ,
elk_AND(p, tmp0, get_element_ud(c->reg.R0, 2), elk_imm_ud(PRIM_MASK));
elk_CMP(p,
vec1(elk_null_reg()),
ELK_CONDITIONAL_EQ,
tmp0,
brw_imm_ud(_3DPRIM_POLYGON));
elk_imm_ud(_3DPRIM_POLYGON));
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_copy_flatshaded_attributes(c, 1, 0);
brw_clip_copy_flatshaded_attributes(c, 2, 0);
elk_clip_copy_flatshaded_attributes(c, 1, 0);
elk_clip_copy_flatshaded_attributes(c, 2, 0);
}
brw_ELSE(p);
elk_ELSE(p);
{
if (c->key.pv_first) {
brw_CMP(p,
vec1(brw_null_reg()),
BRW_CONDITIONAL_EQ,
elk_CMP(p,
vec1(elk_null_reg()),
ELK_CONDITIONAL_EQ,
tmp0,
brw_imm_ud(_3DPRIM_TRIFAN));
brw_IF(p, BRW_EXECUTE_1);
elk_imm_ud(_3DPRIM_TRIFAN));
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_copy_flatshaded_attributes(c, 0, 1);
brw_clip_copy_flatshaded_attributes(c, 2, 1);
elk_clip_copy_flatshaded_attributes(c, 0, 1);
elk_clip_copy_flatshaded_attributes(c, 2, 1);
}
brw_ELSE(p);
elk_ELSE(p);
{
brw_clip_copy_flatshaded_attributes(c, 1, 0);
brw_clip_copy_flatshaded_attributes(c, 2, 0);
elk_clip_copy_flatshaded_attributes(c, 1, 0);
elk_clip_copy_flatshaded_attributes(c, 2, 0);
}
brw_ENDIF(p);
elk_ENDIF(p);
}
else {
brw_clip_copy_flatshaded_attributes(c, 0, 2);
brw_clip_copy_flatshaded_attributes(c, 1, 2);
elk_clip_copy_flatshaded_attributes(c, 0, 2);
elk_clip_copy_flatshaded_attributes(c, 1, 2);
}
}
brw_ENDIF(p);
elk_ENDIF(p);
}
@@ -222,438 +222,438 @@ void brw_clip_tri_flat_shade( struct brw_clip_compile *c )
* - If using a user clip plane, the distance is directly available in the vertex.
*/
static inline void
load_clip_distance(struct brw_clip_compile *c, struct brw_indirect vtx,
struct brw_reg dst, GLuint hpos_offset, int cond)
load_clip_distance(struct elk_clip_compile *c, struct elk_indirect vtx,
struct elk_reg dst, GLuint hpos_offset, int cond)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
dst = vec4(dst);
brw_AND(p, vec1(brw_null_reg()), c->reg.vertex_src_mask, brw_imm_ud(1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
elk_AND(p, vec1(elk_null_reg()), c->reg.vertex_src_mask, elk_imm_ud(1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_IF(p, ELK_EXECUTE_1);
{
struct brw_indirect temp_ptr = brw_indirect(7, 0);
brw_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx), c->reg.clipdistance_offset);
brw_MOV(p, vec1(dst), deref_1f(temp_ptr, 0));
struct elk_indirect temp_ptr = elk_indirect(7, 0);
elk_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx), c->reg.clipdistance_offset);
elk_MOV(p, vec1(dst), deref_1f(temp_ptr, 0));
}
brw_ELSE(p);
elk_ELSE(p);
{
brw_MOV(p, dst, deref_4f(vtx, hpos_offset));
brw_DP4(p, dst, dst, c->reg.plane_equation);
elk_MOV(p, dst, deref_4f(vtx, hpos_offset));
elk_DP4(p, dst, dst, c->reg.plane_equation);
}
brw_ENDIF(p);
elk_ENDIF(p);
brw_CMP(p, brw_null_reg(), cond, vec1(dst), brw_imm_f(0.0f));
elk_CMP(p, elk_null_reg(), cond, vec1(dst), elk_imm_f(0.0f));
}
/* Use mesa's clipping algorithms, translated to GFX4 assembly.
*/
void brw_clip_tri( struct brw_clip_compile *c )
void elk_clip_tri( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_indirect vtx = brw_indirect(0, 0);
struct brw_indirect vtxPrev = brw_indirect(1, 0);
struct brw_indirect vtxOut = brw_indirect(2, 0);
struct brw_indirect plane_ptr = brw_indirect(3, 0);
struct brw_indirect inlist_ptr = brw_indirect(4, 0);
struct brw_indirect outlist_ptr = brw_indirect(5, 0);
struct brw_indirect freelist_ptr = brw_indirect(6, 0);
GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
struct elk_codegen *p = &c->func;
struct elk_indirect vtx = elk_indirect(0, 0);
struct elk_indirect vtxPrev = elk_indirect(1, 0);
struct elk_indirect vtxOut = elk_indirect(2, 0);
struct elk_indirect plane_ptr = elk_indirect(3, 0);
struct elk_indirect inlist_ptr = elk_indirect(4, 0);
struct elk_indirect outlist_ptr = elk_indirect(5, 0);
struct elk_indirect freelist_ptr = elk_indirect(6, 0);
GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
GLint clipdist0_offset = c->key.nr_userclip
? brw_varying_to_offset(&c->vue_map, VARYING_SLOT_CLIP_DIST0)
? elk_varying_to_offset(&c->vue_map, VARYING_SLOT_CLIP_DIST0)
: 0;
brw_MOV(p, get_addr_reg(vtxPrev), brw_address(c->reg.vertex[2]) );
brw_MOV(p, get_addr_reg(plane_ptr), brw_clip_plane0_address(c));
brw_MOV(p, get_addr_reg(inlist_ptr), brw_address(c->reg.inlist));
brw_MOV(p, get_addr_reg(outlist_ptr), brw_address(c->reg.outlist));
elk_MOV(p, get_addr_reg(vtxPrev), elk_address(c->reg.vertex[2]) );
elk_MOV(p, get_addr_reg(plane_ptr), elk_clip_plane0_address(c));
elk_MOV(p, get_addr_reg(inlist_ptr), elk_address(c->reg.inlist));
elk_MOV(p, get_addr_reg(outlist_ptr), elk_address(c->reg.outlist));
brw_MOV(p, get_addr_reg(freelist_ptr), brw_address(c->reg.vertex[3]) );
elk_MOV(p, get_addr_reg(freelist_ptr), elk_address(c->reg.vertex[3]) );
/* Set the initial vertex source mask: The first 6 planes are the bounds
* of the view volume; the next 8 planes are the user clipping planes.
*/
brw_MOV(p, c->reg.vertex_src_mask, brw_imm_ud(0x3fc0));
elk_MOV(p, c->reg.vertex_src_mask, elk_imm_ud(0x3fc0));
/* Set the initial clipdistance offset to be 6 floats before gl_ClipDistance[0].
* We'll increment 6 times before we start hitting actual user clipping. */
brw_MOV(p, c->reg.clipdistance_offset, brw_imm_d(clipdist0_offset - 6*sizeof(float)));
elk_MOV(p, c->reg.clipdistance_offset, elk_imm_d(clipdist0_offset - 6*sizeof(float)));
brw_DO(p, BRW_EXECUTE_1);
elk_DO(p, ELK_EXECUTE_1);
{
/* if (planemask & 1)
*/
brw_AND(p, vec1(brw_null_reg()), c->reg.planemask, brw_imm_ud(1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
elk_AND(p, vec1(elk_null_reg()), c->reg.planemask, elk_imm_ud(1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
/* vtxOut = freelist_ptr++
*/
brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(freelist_ptr) );
brw_ADD(p, get_addr_reg(freelist_ptr), get_addr_reg(freelist_ptr), brw_imm_uw(c->nr_regs * REG_SIZE));
elk_MOV(p, get_addr_reg(vtxOut), get_addr_reg(freelist_ptr) );
elk_ADD(p, get_addr_reg(freelist_ptr), get_addr_reg(freelist_ptr), elk_imm_uw(c->nr_regs * REG_SIZE));
if (c->key.nr_userclip)
brw_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0));
elk_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0));
else
brw_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0));
elk_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0));
brw_MOV(p, c->reg.loopcount, c->reg.nr_verts);
brw_MOV(p, c->reg.nr_verts, brw_imm_ud(0));
elk_MOV(p, c->reg.loopcount, c->reg.nr_verts);
elk_MOV(p, c->reg.nr_verts, elk_imm_ud(0));
brw_DO(p, BRW_EXECUTE_1);
elk_DO(p, ELK_EXECUTE_1);
{
/* vtx = *input_ptr;
*/
brw_MOV(p, get_addr_reg(vtx), deref_1uw(inlist_ptr, 0));
elk_MOV(p, get_addr_reg(vtx), deref_1uw(inlist_ptr, 0));
load_clip_distance(c, vtxPrev, c->reg.dpPrev, hpos_offset, BRW_CONDITIONAL_L);
load_clip_distance(c, vtxPrev, c->reg.dpPrev, hpos_offset, ELK_CONDITIONAL_L);
/* (prev < 0.0f) */
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
load_clip_distance(c, vtx, c->reg.dp, hpos_offset, BRW_CONDITIONAL_GE);
load_clip_distance(c, vtx, c->reg.dp, hpos_offset, ELK_CONDITIONAL_GE);
/* IS_POSITIVE(next)
*/
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
/* Coming back in.
*/
brw_ADD(p, c->reg.t, c->reg.dpPrev, negate(c->reg.dp));
brw_math_invert(p, c->reg.t, c->reg.t);
brw_MUL(p, c->reg.t, c->reg.t, c->reg.dpPrev);
elk_ADD(p, c->reg.t, c->reg.dpPrev, negate(c->reg.dp));
elk_math_invert(p, c->reg.t, c->reg.t);
elk_MUL(p, c->reg.t, c->reg.t, c->reg.dpPrev);
/* If (vtxOut == 0) vtxOut = vtxPrev
*/
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, get_addr_reg(vtxOut), brw_imm_uw(0) );
brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtxPrev));
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
BRW_PREDICATE_NORMAL);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_EQ, get_addr_reg(vtxOut), elk_imm_uw(0) );
elk_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtxPrev));
elk_inst_set_pred_control(p->devinfo, elk_last_inst,
ELK_PREDICATE_NORMAL);
brw_clip_interp_vertex(c, vtxOut, vtxPrev, vtx, c->reg.t, false);
elk_clip_interp_vertex(c, vtxOut, vtxPrev, vtx, c->reg.t, false);
/* *outlist_ptr++ = vtxOut;
* nr_verts++;
* vtxOut = 0;
*/
brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut));
brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short)));
brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1));
brw_MOV(p, get_addr_reg(vtxOut), brw_imm_uw(0) );
elk_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut));
elk_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), elk_imm_uw(sizeof(short)));
elk_ADD(p, c->reg.nr_verts, c->reg.nr_verts, elk_imm_ud(1));
elk_MOV(p, get_addr_reg(vtxOut), elk_imm_uw(0) );
}
brw_ENDIF(p);
elk_ENDIF(p);
}
brw_ELSE(p);
elk_ELSE(p);
{
/* *outlist_ptr++ = vtxPrev;
* nr_verts++;
*/
brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxPrev));
brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short)));
brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1));
elk_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxPrev));
elk_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), elk_imm_uw(sizeof(short)));
elk_ADD(p, c->reg.nr_verts, c->reg.nr_verts, elk_imm_ud(1));
load_clip_distance(c, vtx, c->reg.dp, hpos_offset, BRW_CONDITIONAL_L);
load_clip_distance(c, vtx, c->reg.dp, hpos_offset, ELK_CONDITIONAL_L);
/* (next < 0.0f)
*/
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
/* Going out of bounds. Avoid division by zero as we
* know dp != dpPrev from DIFFERENT_SIGNS, above.
*/
brw_ADD(p, c->reg.t, c->reg.dp, negate(c->reg.dpPrev));
brw_math_invert(p, c->reg.t, c->reg.t);
brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp);
elk_ADD(p, c->reg.t, c->reg.dp, negate(c->reg.dpPrev));
elk_math_invert(p, c->reg.t, c->reg.t);
elk_MUL(p, c->reg.t, c->reg.t, c->reg.dp);
/* If (vtxOut == 0) vtxOut = vtx
*/
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, get_addr_reg(vtxOut), brw_imm_uw(0) );
brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtx));
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
BRW_PREDICATE_NORMAL);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_EQ, get_addr_reg(vtxOut), elk_imm_uw(0) );
elk_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtx));
elk_inst_set_pred_control(p->devinfo, elk_last_inst,
ELK_PREDICATE_NORMAL);
brw_clip_interp_vertex(c, vtxOut, vtx, vtxPrev, c->reg.t, true);
elk_clip_interp_vertex(c, vtxOut, vtx, vtxPrev, c->reg.t, true);
/* *outlist_ptr++ = vtxOut;
* nr_verts++;
* vtxOut = 0;
*/
brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut));
brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short)));
brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1));
brw_MOV(p, get_addr_reg(vtxOut), brw_imm_uw(0) );
elk_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut));
elk_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), elk_imm_uw(sizeof(short)));
elk_ADD(p, c->reg.nr_verts, c->reg.nr_verts, elk_imm_ud(1));
elk_MOV(p, get_addr_reg(vtxOut), elk_imm_uw(0) );
}
brw_ENDIF(p);
elk_ENDIF(p);
}
brw_ENDIF(p);
elk_ENDIF(p);
/* vtxPrev = vtx;
* inlist_ptr++;
*/
brw_MOV(p, get_addr_reg(vtxPrev), get_addr_reg(vtx));
brw_ADD(p, get_addr_reg(inlist_ptr), get_addr_reg(inlist_ptr), brw_imm_uw(sizeof(short)));
elk_MOV(p, get_addr_reg(vtxPrev), get_addr_reg(vtx));
elk_ADD(p, get_addr_reg(inlist_ptr), get_addr_reg(inlist_ptr), elk_imm_uw(sizeof(short)));
/* while (--loopcount != 0)
*/
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
}
brw_WHILE(p);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_WHILE(p);
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
/* vtxPrev = *(outlist_ptr-1) OR: outlist[nr_verts-1]
* inlist = outlist
* inlist_ptr = &inlist[0]
* outlist_ptr = &outlist[0]
*/
brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_w(-2));
brw_MOV(p, get_addr_reg(vtxPrev), deref_1uw(outlist_ptr, 0));
brw_MOV(p, brw_vec8_grf(c->reg.inlist.nr, 0), brw_vec8_grf(c->reg.outlist.nr, 0));
brw_MOV(p, get_addr_reg(inlist_ptr), brw_address(c->reg.inlist));
brw_MOV(p, get_addr_reg(outlist_ptr), brw_address(c->reg.outlist));
elk_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), elk_imm_w(-2));
elk_MOV(p, get_addr_reg(vtxPrev), deref_1uw(outlist_ptr, 0));
elk_MOV(p, elk_vec8_grf(c->reg.inlist.nr, 0), elk_vec8_grf(c->reg.outlist.nr, 0));
elk_MOV(p, get_addr_reg(inlist_ptr), elk_address(c->reg.inlist));
elk_MOV(p, get_addr_reg(outlist_ptr), elk_address(c->reg.outlist));
}
brw_ENDIF(p);
elk_ENDIF(p);
/* plane_ptr++;
*/
brw_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), brw_clip_plane_stride(c));
elk_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), elk_clip_plane_stride(c));
/* nr_verts >= 3
*/
brw_CMP(p,
vec1(brw_null_reg()),
BRW_CONDITIONAL_GE,
elk_CMP(p,
vec1(elk_null_reg()),
ELK_CONDITIONAL_GE,
c->reg.nr_verts,
brw_imm_ud(3));
brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
elk_imm_ud(3));
elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL);
/* && (planemask>>=1) != 0
*/
brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, brw_imm_ud(1));
brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, brw_imm_w(sizeof(float)));
elk_SHR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud(1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, elk_imm_ud(1));
elk_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, elk_imm_w(sizeof(float)));
}
brw_WHILE(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_WHILE(p);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
}
void brw_clip_tri_emit_polygon(struct brw_clip_compile *c)
void elk_clip_tri_emit_polygon(struct elk_clip_compile *c)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
/* for (loopcount = nr_verts-2; loopcount > 0; loopcount--)
*/
brw_ADD(p,
elk_ADD(p,
c->reg.loopcount,
c->reg.nr_verts,
brw_imm_d(-2));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_G);
elk_imm_d(-2));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_G);
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
struct brw_indirect v0 = brw_indirect(0, 0);
struct brw_indirect vptr = brw_indirect(1, 0);
struct elk_indirect v0 = elk_indirect(0, 0);
struct elk_indirect vptr = elk_indirect(1, 0);
brw_MOV(p, get_addr_reg(vptr), brw_address(c->reg.inlist));
brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0));
elk_MOV(p, get_addr_reg(vptr), elk_address(c->reg.inlist));
elk_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0));
brw_clip_emit_vue(c, v0, BRW_URB_WRITE_ALLOCATE_COMPLETE,
elk_clip_emit_vue(c, v0, ELK_URB_WRITE_ALLOCATE_COMPLETE,
((_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_START));
brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2));
brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0));
elk_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), elk_imm_uw(2));
elk_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0));
brw_DO(p, BRW_EXECUTE_1);
elk_DO(p, ELK_EXECUTE_1);
{
brw_clip_emit_vue(c, v0, BRW_URB_WRITE_ALLOCATE_COMPLETE,
elk_clip_emit_vue(c, v0, ELK_URB_WRITE_ALLOCATE_COMPLETE,
(_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT));
brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2));
brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0));
elk_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), elk_imm_uw(2));
elk_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0));
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
}
brw_WHILE(p);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_WHILE(p);
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
brw_clip_emit_vue(c, v0, BRW_URB_WRITE_EOT_COMPLETE,
elk_clip_emit_vue(c, v0, ELK_URB_WRITE_EOT_COMPLETE,
((_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_END));
}
brw_ENDIF(p);
elk_ENDIF(p);
}
static void do_clip_tri( struct brw_clip_compile *c )
static void do_clip_tri( struct elk_clip_compile *c )
{
brw_clip_init_planes(c);
elk_clip_init_planes(c);
brw_clip_tri(c);
elk_clip_tri(c);
}
static void maybe_do_clip_tri( struct brw_clip_compile *c )
static void maybe_do_clip_tri( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, c->reg.planemask, brw_imm_ud(0));
brw_IF(p, BRW_EXECUTE_1);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_NZ, c->reg.planemask, elk_imm_ud(0));
elk_IF(p, ELK_EXECUTE_1);
{
do_clip_tri(c);
}
brw_ENDIF(p);
elk_ENDIF(p);
}
static void brw_clip_test( struct brw_clip_compile *c )
static void elk_clip_test( struct elk_clip_compile *c )
{
struct brw_reg t = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
struct brw_reg t1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
struct brw_reg t2 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
struct brw_reg t3 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
struct elk_reg t = retype(get_tmp(c), ELK_REGISTER_TYPE_UD);
struct elk_reg t1 = retype(get_tmp(c), ELK_REGISTER_TYPE_UD);
struct elk_reg t2 = retype(get_tmp(c), ELK_REGISTER_TYPE_UD);
struct elk_reg t3 = retype(get_tmp(c), ELK_REGISTER_TYPE_UD);
struct brw_reg v0 = get_tmp(c);
struct brw_reg v1 = get_tmp(c);
struct brw_reg v2 = get_tmp(c);
struct elk_reg v0 = get_tmp(c);
struct elk_reg v1 = get_tmp(c);
struct elk_reg v2 = get_tmp(c);
struct brw_indirect vt0 = brw_indirect(0, 0);
struct brw_indirect vt1 = brw_indirect(1, 0);
struct brw_indirect vt2 = brw_indirect(2, 0);
struct elk_indirect vt0 = elk_indirect(0, 0);
struct elk_indirect vt1 = elk_indirect(1, 0);
struct elk_indirect vt2 = elk_indirect(2, 0);
struct brw_codegen *p = &c->func;
struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */
struct elk_codegen *p = &c->func;
struct elk_reg tmp0 = c->reg.loopcount; /* handy temporary */
GLuint hpos_offset = brw_varying_to_offset(&c->vue_map,
GLuint hpos_offset = elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_POS);
brw_MOV(p, get_addr_reg(vt0), brw_address(c->reg.vertex[0]));
brw_MOV(p, get_addr_reg(vt1), brw_address(c->reg.vertex[1]));
brw_MOV(p, get_addr_reg(vt2), brw_address(c->reg.vertex[2]));
brw_MOV(p, v0, deref_4f(vt0, hpos_offset));
brw_MOV(p, v1, deref_4f(vt1, hpos_offset));
brw_MOV(p, v2, deref_4f(vt2, hpos_offset));
brw_AND(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(~0x3f));
elk_MOV(p, get_addr_reg(vt0), elk_address(c->reg.vertex[0]));
elk_MOV(p, get_addr_reg(vt1), elk_address(c->reg.vertex[1]));
elk_MOV(p, get_addr_reg(vt2), elk_address(c->reg.vertex[2]));
elk_MOV(p, v0, deref_4f(vt0, hpos_offset));
elk_MOV(p, v1, deref_4f(vt1, hpos_offset));
elk_MOV(p, v2, deref_4f(vt2, hpos_offset));
elk_AND(p, c->reg.planemask, c->reg.planemask, elk_imm_ud(~0x3f));
/* test nearz, xmin, ymin plane */
/* clip.xyz < -clip.w */
brw_CMP(p, t1, BRW_CONDITIONAL_L, v0, negate(get_element(v0, 3)));
brw_CMP(p, t2, BRW_CONDITIONAL_L, v1, negate(get_element(v1, 3)));
brw_CMP(p, t3, BRW_CONDITIONAL_L, v2, negate(get_element(v2, 3)));
elk_CMP(p, t1, ELK_CONDITIONAL_L, v0, negate(get_element(v0, 3)));
elk_CMP(p, t2, ELK_CONDITIONAL_L, v1, negate(get_element(v1, 3)));
elk_CMP(p, t3, ELK_CONDITIONAL_L, v2, negate(get_element(v2, 3)));
/* All vertices are outside of a plane, rejected */
brw_AND(p, t, t1, t2);
brw_AND(p, t, t, t3);
brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1));
brw_OR(p, tmp0, tmp0, get_element(t, 2));
brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
elk_AND(p, t, t1, t2);
elk_AND(p, t, t, t3);
elk_OR(p, tmp0, get_element(t, 0), get_element(t, 1));
elk_OR(p, tmp0, tmp0, get_element(t, 2));
elk_AND(p, elk_null_reg(), tmp0, elk_imm_ud(0x1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_kill_thread(c);
elk_clip_kill_thread(c);
}
brw_ENDIF(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_ENDIF(p);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
/* some vertices are inside a plane, some are outside,need to clip */
brw_XOR(p, t, t1, t2);
brw_XOR(p, t1, t2, t3);
brw_OR(p, t, t, t1);
brw_AND(p, t, t, brw_imm_ud(0x1));
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 0), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<5)));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 1), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<3)));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 2), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<1)));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_XOR(p, t, t1, t2);
elk_XOR(p, t1, t2, t3);
elk_OR(p, t, t, t1);
elk_AND(p, t, t, elk_imm_ud(0x1));
elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ,
get_element(t, 0), elk_imm_ud(0));
elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<5)));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ,
get_element(t, 1), elk_imm_ud(0));
elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<3)));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ,
get_element(t, 2), elk_imm_ud(0));
elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<1)));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
/* test farz, xmax, ymax plane */
/* clip.xyz > clip.w */
brw_CMP(p, t1, BRW_CONDITIONAL_G, v0, get_element(v0, 3));
brw_CMP(p, t2, BRW_CONDITIONAL_G, v1, get_element(v1, 3));
brw_CMP(p, t3, BRW_CONDITIONAL_G, v2, get_element(v2, 3));
elk_CMP(p, t1, ELK_CONDITIONAL_G, v0, get_element(v0, 3));
elk_CMP(p, t2, ELK_CONDITIONAL_G, v1, get_element(v1, 3));
elk_CMP(p, t3, ELK_CONDITIONAL_G, v2, get_element(v2, 3));
/* All vertices are outside of a plane, rejected */
brw_AND(p, t, t1, t2);
brw_AND(p, t, t, t3);
brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1));
brw_OR(p, tmp0, tmp0, get_element(t, 2));
brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
elk_AND(p, t, t1, t2);
elk_AND(p, t, t, t3);
elk_OR(p, tmp0, get_element(t, 0), get_element(t, 1));
elk_OR(p, tmp0, tmp0, get_element(t, 2));
elk_AND(p, elk_null_reg(), tmp0, elk_imm_ud(0x1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_kill_thread(c);
elk_clip_kill_thread(c);
}
brw_ENDIF(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_ENDIF(p);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
/* some vertices are inside a plane, some are outside,need to clip */
brw_XOR(p, t, t1, t2);
brw_XOR(p, t1, t2, t3);
brw_OR(p, t, t, t1);
brw_AND(p, t, t, brw_imm_ud(0x1));
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 0), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<4)));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 1), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<2)));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
get_element(t, 2), brw_imm_ud(0));
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<0)));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_XOR(p, t, t1, t2);
elk_XOR(p, t1, t2, t3);
elk_OR(p, t, t, t1);
elk_AND(p, t, t, elk_imm_ud(0x1));
elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ,
get_element(t, 0), elk_imm_ud(0));
elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<4)));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ,
get_element(t, 1), elk_imm_ud(0));
elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<2)));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ,
get_element(t, 2), elk_imm_ud(0));
elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<0)));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
release_tmps(c);
}
void brw_emit_tri_clip( struct brw_clip_compile *c )
void elk_emit_tri_clip( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
brw_clip_tri_init_vertices(c);
brw_clip_init_clipmask(c);
brw_clip_init_ff_sync(c);
struct elk_codegen *p = &c->func;
elk_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
elk_clip_tri_init_vertices(c);
elk_clip_init_clipmask(c);
elk_clip_init_ff_sync(c);
/* if -ve rhw workaround bit is set,
do cliptest */
if (p->devinfo->has_negative_rhw_bug) {
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
elk_AND(p, elk_null_reg(), get_element_ud(c->reg.R0, 2),
elk_imm_ud(1<<20));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_test(c);
elk_clip_test(c);
}
brw_ENDIF(p);
elk_ENDIF(p);
}
/* Can't push into do_clip_tri because with polygon (or quad)
* flatshading, need to apply the flatshade here because we don't
* respect the PV when converting to trifan for emit:
*/
if (c->key.contains_flat_varying)
brw_clip_tri_flat_shade(c);
elk_clip_tri_flat_shade(c);
if ((c->key.clip_mode == BRW_CLIP_MODE_NORMAL) ||
(c->key.clip_mode == BRW_CLIP_MODE_KERNEL_CLIP))
if ((c->key.clip_mode == ELK_CLIP_MODE_NORMAL) ||
(c->key.clip_mode == ELK_CLIP_MODE_KERNEL_CLIP))
do_clip_tri(c);
else
maybe_do_clip_tri(c);
brw_clip_tri_emit_polygon(c);
elk_clip_tri_emit_polygon(c);
/* Send an empty message to kill the thread:
*/
brw_clip_kill_thread(c);
elk_clip_kill_thread(c);
}
src/intel/compiler/elk/elk_clip_unfilled.c
+215 -215
View File
@@ -37,20 +37,20 @@
* required:
BZZZT!
*/
static void compute_tri_direction( struct brw_clip_compile *c )
static void compute_tri_direction( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_reg e = c->reg.tmp0;
struct brw_reg f = c->reg.tmp1;
GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
struct brw_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset);
struct brw_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset);
struct brw_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset);
struct elk_codegen *p = &c->func;
struct elk_reg e = c->reg.tmp0;
struct elk_reg f = c->reg.tmp1;
GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
struct elk_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset);
struct elk_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset);
struct elk_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset);
struct brw_reg v0n = get_tmp(c);
struct brw_reg v1n = get_tmp(c);
struct brw_reg v2n = get_tmp(c);
struct elk_reg v0n = get_tmp(c);
struct elk_reg v1n = get_tmp(c);
struct elk_reg v2n = get_tmp(c);
/* Convert to NDC.
* NOTE: We can't modify the original vertex coordinates,
@@ -60,71 +60,71 @@ static void compute_tri_direction( struct brw_clip_compile *c )
* TBD-KC
* Try to optimize unnecessary MOV's.
*/
brw_MOV(p, v0n, v0);
brw_MOV(p, v1n, v1);
brw_MOV(p, v2n, v2);
elk_MOV(p, v0n, v0);
elk_MOV(p, v1n, v1);
elk_MOV(p, v2n, v2);
brw_clip_project_position(c, v0n);
brw_clip_project_position(c, v1n);
brw_clip_project_position(c, v2n);
elk_clip_project_position(c, v0n);
elk_clip_project_position(c, v1n);
elk_clip_project_position(c, v2n);
/* Calculate the vectors of two edges of the triangle:
*/
brw_ADD(p, e, v0n, negate(v2n));
brw_ADD(p, f, v1n, negate(v2n));
elk_ADD(p, e, v0n, negate(v2n));
elk_ADD(p, f, v1n, negate(v2n));
/* Take their crossproduct:
*/
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MUL(p, vec4(brw_null_reg()), brw_swizzle(e, BRW_SWIZZLE_YZXW),
brw_swizzle(f, BRW_SWIZZLE_ZXYW));
brw_MAC(p, vec4(e), negate(brw_swizzle(e, BRW_SWIZZLE_ZXYW)),
brw_swizzle(f, BRW_SWIZZLE_YZXW));
brw_set_default_access_mode(p, BRW_ALIGN_1);
elk_set_default_access_mode(p, ELK_ALIGN_16);
elk_MUL(p, vec4(elk_null_reg()), elk_swizzle(e, ELK_SWIZZLE_YZXW),
elk_swizzle(f, ELK_SWIZZLE_ZXYW));
elk_MAC(p, vec4(e), negate(elk_swizzle(e, ELK_SWIZZLE_ZXYW)),
elk_swizzle(f, ELK_SWIZZLE_YZXW));
elk_set_default_access_mode(p, ELK_ALIGN_1);
brw_MUL(p, c->reg.dir, c->reg.dir, vec4(e));
elk_MUL(p, c->reg.dir, c->reg.dir, vec4(e));
}
static void cull_direction( struct brw_clip_compile *c )
static void cull_direction( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint conditional;
assert (!(c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL &&
c->key.fill_cw == BRW_CLIP_FILL_MODE_CULL));
assert (!(c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL &&
c->key.fill_cw == ELK_CLIP_FILL_MODE_CULL));
if (c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL)
conditional = BRW_CONDITIONAL_GE;
if (c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL)
conditional = ELK_CONDITIONAL_GE;
else
conditional = BRW_CONDITIONAL_L;
conditional = ELK_CONDITIONAL_L;
brw_CMP(p,
vec1(brw_null_reg()),
elk_CMP(p,
vec1(elk_null_reg()),
conditional,
get_element(c->reg.dir, 2),
brw_imm_f(0));
elk_imm_f(0));
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_kill_thread(c);
elk_clip_kill_thread(c);
}
brw_ENDIF(p);
elk_ENDIF(p);
}
static void copy_bfc( struct brw_clip_compile *c )
static void copy_bfc( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint conditional;
/* Do we have any colors to copy?
*/
if (!(brw_clip_have_varying(c, VARYING_SLOT_COL0) &&
brw_clip_have_varying(c, VARYING_SLOT_BFC0)) &&
!(brw_clip_have_varying(c, VARYING_SLOT_COL1) &&
brw_clip_have_varying(c, VARYING_SLOT_BFC1)))
if (!(elk_clip_have_varying(c, VARYING_SLOT_COL0) &&
elk_clip_have_varying(c, VARYING_SLOT_BFC0)) &&
!(elk_clip_have_varying(c, VARYING_SLOT_COL1) &&
elk_clip_have_varying(c, VARYING_SLOT_BFC1)))
return;
/* In some weird degenerate cases we can end up testing the
@@ -132,43 +132,43 @@ static void copy_bfc( struct brw_clip_compile *c )
* well, that's what you get for setting weird GL state.
*/
if (c->key.copy_bfc_ccw)
conditional = BRW_CONDITIONAL_GE;
conditional = ELK_CONDITIONAL_GE;
else
conditional = BRW_CONDITIONAL_L;
conditional = ELK_CONDITIONAL_L;
brw_CMP(p,
vec1(brw_null_reg()),
elk_CMP(p,
vec1(elk_null_reg()),
conditional,
get_element(c->reg.dir, 2),
brw_imm_f(0));
elk_imm_f(0));
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
GLuint i;
for (i = 0; i < 3; i++) {
if (brw_clip_have_varying(c, VARYING_SLOT_COL0) &&
brw_clip_have_varying(c, VARYING_SLOT_BFC0))
brw_MOV(p,
if (elk_clip_have_varying(c, VARYING_SLOT_COL0) &&
elk_clip_have_varying(c, VARYING_SLOT_BFC0))
elk_MOV(p,
byte_offset(c->reg.vertex[i],
brw_varying_to_offset(&c->vue_map,
elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_COL0)),
byte_offset(c->reg.vertex[i],
brw_varying_to_offset(&c->vue_map,
elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_BFC0)));
if (brw_clip_have_varying(c, VARYING_SLOT_COL1) &&
brw_clip_have_varying(c, VARYING_SLOT_BFC1))
brw_MOV(p,
if (elk_clip_have_varying(c, VARYING_SLOT_COL1) &&
elk_clip_have_varying(c, VARYING_SLOT_BFC1))
elk_MOV(p,
byte_offset(c->reg.vertex[i],
brw_varying_to_offset(&c->vue_map,
elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_COL1)),
byte_offset(c->reg.vertex[i],
brw_varying_to_offset(&c->vue_map,
elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_BFC1)));
}
}
brw_ENDIF(p);
elk_ENDIF(p);
}
@@ -188,86 +188,86 @@ static void copy_bfc( struct brw_clip_compile *c )
}
offset *= MRD;
*/
static void compute_offset( struct brw_clip_compile *c )
static void compute_offset( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_reg off = c->reg.offset;
struct brw_reg dir = c->reg.dir;
struct elk_codegen *p = &c->func;
struct elk_reg off = c->reg.offset;
struct elk_reg dir = c->reg.dir;
brw_math_invert(p, get_element(off, 2), get_element(dir, 2));
brw_MUL(p, vec2(off), vec2(dir), get_element(off, 2));
elk_math_invert(p, get_element(off, 2), get_element(dir, 2));
elk_MUL(p, vec2(off), vec2(dir), get_element(off, 2));
brw_CMP(p,
vec1(brw_null_reg()),
BRW_CONDITIONAL_GE,
brw_abs(get_element(off, 0)),
brw_abs(get_element(off, 1)));
elk_CMP(p,
vec1(elk_null_reg()),
ELK_CONDITIONAL_GE,
elk_abs(get_element(off, 0)),
elk_abs(get_element(off, 1)));
brw_SEL(p, vec1(off),
brw_abs(get_element(off, 0)), brw_abs(get_element(off, 1)));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_SEL(p, vec1(off),
elk_abs(get_element(off, 0)), elk_abs(get_element(off, 1)));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
brw_MUL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_factor));
brw_ADD(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_units));
elk_MUL(p, vec1(off), vec1(off), elk_imm_f(c->key.offset_factor));
elk_ADD(p, vec1(off), vec1(off), elk_imm_f(c->key.offset_units));
if (c->key.offset_clamp && isfinite(c->key.offset_clamp)) {
brw_CMP(p,
vec1(brw_null_reg()),
c->key.offset_clamp < 0 ? BRW_CONDITIONAL_GE : BRW_CONDITIONAL_L,
elk_CMP(p,
vec1(elk_null_reg()),
c->key.offset_clamp < 0 ? ELK_CONDITIONAL_GE : ELK_CONDITIONAL_L,
vec1(off),
brw_imm_f(c->key.offset_clamp));
brw_SEL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_clamp));
elk_imm_f(c->key.offset_clamp));
elk_SEL(p, vec1(off), vec1(off), elk_imm_f(c->key.offset_clamp));
}
}
static void merge_edgeflags( struct brw_clip_compile *c )
static void merge_edgeflags( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_reg tmp0 = get_element_ud(c->reg.tmp0, 0);
struct elk_codegen *p = &c->func;
struct elk_reg tmp0 = get_element_ud(c->reg.tmp0, 0);
brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
brw_CMP(p,
vec1(brw_null_reg()),
BRW_CONDITIONAL_EQ,
elk_AND(p, tmp0, get_element_ud(c->reg.R0, 2), elk_imm_ud(PRIM_MASK));
elk_CMP(p,
vec1(elk_null_reg()),
ELK_CONDITIONAL_EQ,
tmp0,
brw_imm_ud(_3DPRIM_POLYGON));
elk_imm_ud(_3DPRIM_POLYGON));
/* Get away with using reg.vertex because we know that this is not
* a _3DPRIM_TRISTRIP_REVERSE:
*/
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_EQ);
brw_MOV(p, byte_offset(c->reg.vertex[0],
brw_varying_to_offset(&c->vue_map,
elk_AND(p, vec1(elk_null_reg()), get_element_ud(c->reg.R0, 2), elk_imm_ud(1<<8));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_EQ);
elk_MOV(p, byte_offset(c->reg.vertex[0],
elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_EDGE)),
brw_imm_f(0));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_imm_f(0));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_EQ);
brw_MOV(p, byte_offset(c->reg.vertex[2],
brw_varying_to_offset(&c->vue_map,
elk_AND(p, vec1(elk_null_reg()), get_element_ud(c->reg.R0, 2), elk_imm_ud(1<<9));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_EQ);
elk_MOV(p, byte_offset(c->reg.vertex[2],
elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_EDGE)),
brw_imm_f(0));
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_imm_f(0));
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
}
brw_ENDIF(p);
elk_ENDIF(p);
}
static void apply_one_offset( struct brw_clip_compile *c,
struct brw_indirect vert )
static void apply_one_offset( struct elk_clip_compile *c,
struct elk_indirect vert )
{
struct brw_codegen *p = &c->func;
GLuint ndc_offset = brw_varying_to_offset(&c->vue_map,
BRW_VARYING_SLOT_NDC);
struct brw_reg z = deref_1f(vert, ndc_offset +
2 * type_sz(BRW_REGISTER_TYPE_F));
struct elk_codegen *p = &c->func;
GLuint ndc_offset = elk_varying_to_offset(&c->vue_map,
ELK_VARYING_SLOT_NDC);
struct elk_reg z = deref_1f(vert, ndc_offset +
2 * type_sz(ELK_REGISTER_TYPE_F));
brw_ADD(p, z, z, vec1(c->reg.offset));
elk_ADD(p, z, z, vec1(c->reg.offset));
}
@@ -275,115 +275,115 @@ static void apply_one_offset( struct brw_clip_compile *c,
/***********************************************************************
* Output clipped polygon as an unfilled primitive:
*/
static void emit_lines(struct brw_clip_compile *c,
static void emit_lines(struct elk_clip_compile *c,
bool do_offset)
{
struct brw_codegen *p = &c->func;
struct brw_indirect v0 = brw_indirect(0, 0);
struct brw_indirect v1 = brw_indirect(1, 0);
struct brw_indirect v0ptr = brw_indirect(2, 0);
struct brw_indirect v1ptr = brw_indirect(3, 0);
struct elk_codegen *p = &c->func;
struct elk_indirect v0 = elk_indirect(0, 0);
struct elk_indirect v1 = elk_indirect(1, 0);
struct elk_indirect v0ptr = elk_indirect(2, 0);
struct elk_indirect v1ptr = elk_indirect(3, 0);
/* Need a separate loop for offset:
*/
if (do_offset) {
brw_MOV(p, c->reg.loopcount, c->reg.nr_verts);
brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist));
elk_MOV(p, c->reg.loopcount, c->reg.nr_verts);
elk_MOV(p, get_addr_reg(v0ptr), elk_address(c->reg.inlist));
brw_DO(p, BRW_EXECUTE_1);
elk_DO(p, ELK_EXECUTE_1);
{
brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2));
elk_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
elk_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), elk_imm_uw(2));
apply_one_offset(c, v0);
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_G);
elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_G);
}
brw_WHILE(p);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_WHILE(p);
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
}
/* v1ptr = &inlist[nr_verts]
* *v1ptr = v0
*/
brw_MOV(p, c->reg.loopcount, c->reg.nr_verts);
brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist));
brw_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v0ptr), retype(c->reg.nr_verts, BRW_REGISTER_TYPE_UW));
brw_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v1ptr), retype(c->reg.nr_verts, BRW_REGISTER_TYPE_UW));
brw_MOV(p, deref_1uw(v1ptr, 0), deref_1uw(v0ptr, 0));
elk_MOV(p, c->reg.loopcount, c->reg.nr_verts);
elk_MOV(p, get_addr_reg(v0ptr), elk_address(c->reg.inlist));
elk_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v0ptr), retype(c->reg.nr_verts, ELK_REGISTER_TYPE_UW));
elk_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v1ptr), retype(c->reg.nr_verts, ELK_REGISTER_TYPE_UW));
elk_MOV(p, deref_1uw(v1ptr, 0), deref_1uw(v0ptr, 0));
brw_DO(p, BRW_EXECUTE_1);
elk_DO(p, ELK_EXECUTE_1);
{
brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
brw_MOV(p, get_addr_reg(v1), deref_1uw(v0ptr, 2));
brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2));
elk_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
elk_MOV(p, get_addr_reg(v1), deref_1uw(v0ptr, 2));
elk_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), elk_imm_uw(2));
/* draw edge if edgeflag != 0 */
brw_CMP(p,
vec1(brw_null_reg()), BRW_CONDITIONAL_NZ,
deref_1f(v0, brw_varying_to_offset(&c->vue_map,
elk_CMP(p,
vec1(elk_null_reg()), ELK_CONDITIONAL_NZ,
deref_1f(v0, elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_EDGE)),
brw_imm_f(0));
brw_IF(p, BRW_EXECUTE_1);
elk_imm_f(0));
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_emit_vue(c, v0, BRW_URB_WRITE_ALLOCATE_COMPLETE,
elk_clip_emit_vue(c, v0, ELK_URB_WRITE_ALLOCATE_COMPLETE,
(_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_START);
brw_clip_emit_vue(c, v1, BRW_URB_WRITE_ALLOCATE_COMPLETE,
elk_clip_emit_vue(c, v1, ELK_URB_WRITE_ALLOCATE_COMPLETE,
(_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_END);
}
brw_ENDIF(p);
elk_ENDIF(p);
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
}
brw_WHILE(p);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_WHILE(p);
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
}
static void emit_points(struct brw_clip_compile *c,
static void emit_points(struct elk_clip_compile *c,
bool do_offset )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
struct brw_indirect v0 = brw_indirect(0, 0);
struct brw_indirect v0ptr = brw_indirect(2, 0);
struct elk_indirect v0 = elk_indirect(0, 0);
struct elk_indirect v0ptr = elk_indirect(2, 0);
brw_MOV(p, c->reg.loopcount, c->reg.nr_verts);
brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist));
elk_MOV(p, c->reg.loopcount, c->reg.nr_verts);
elk_MOV(p, get_addr_reg(v0ptr), elk_address(c->reg.inlist));
brw_DO(p, BRW_EXECUTE_1);
elk_DO(p, ELK_EXECUTE_1);
{
brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2));
elk_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
elk_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), elk_imm_uw(2));
/* draw if edgeflag != 0
*/
brw_CMP(p,
vec1(brw_null_reg()), BRW_CONDITIONAL_NZ,
deref_1f(v0, brw_varying_to_offset(&c->vue_map,
elk_CMP(p,
vec1(elk_null_reg()), ELK_CONDITIONAL_NZ,
deref_1f(v0, elk_varying_to_offset(&c->vue_map,
VARYING_SLOT_EDGE)),
brw_imm_f(0));
brw_IF(p, BRW_EXECUTE_1);
elk_imm_f(0));
elk_IF(p, ELK_EXECUTE_1);
{
if (do_offset)
apply_one_offset(c, v0);
brw_clip_emit_vue(c, v0, BRW_URB_WRITE_ALLOCATE_COMPLETE,
elk_clip_emit_vue(c, v0, ELK_URB_WRITE_ALLOCATE_COMPLETE,
(_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
}
brw_ENDIF(p);
elk_ENDIF(p);
brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
}
brw_WHILE(p);
brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL);
elk_WHILE(p);
elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL);
}
@@ -392,60 +392,60 @@ static void emit_points(struct brw_clip_compile *c,
static void emit_primitives( struct brw_clip_compile *c,
static void emit_primitives( struct elk_clip_compile *c,
GLuint mode,
bool do_offset )
{
switch (mode) {
case BRW_CLIP_FILL_MODE_FILL:
brw_clip_tri_emit_polygon(c);
case ELK_CLIP_FILL_MODE_FILL:
elk_clip_tri_emit_polygon(c);
break;
case BRW_CLIP_FILL_MODE_LINE:
case ELK_CLIP_FILL_MODE_LINE:
emit_lines(c, do_offset);
break;
case BRW_CLIP_FILL_MODE_POINT:
case ELK_CLIP_FILL_MODE_POINT:
emit_points(c, do_offset);
break;
case BRW_CLIP_FILL_MODE_CULL:
case ELK_CLIP_FILL_MODE_CULL:
unreachable("not reached");
}
}
static void emit_unfilled_primitives( struct brw_clip_compile *c )
static void emit_unfilled_primitives( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
/* Direction culling has already been done.
*/
if (c->key.fill_ccw != c->key.fill_cw &&
c->key.fill_ccw != BRW_CLIP_FILL_MODE_CULL &&
c->key.fill_cw != BRW_CLIP_FILL_MODE_CULL)
c->key.fill_ccw != ELK_CLIP_FILL_MODE_CULL &&
c->key.fill_cw != ELK_CLIP_FILL_MODE_CULL)
{
brw_CMP(p,
vec1(brw_null_reg()),
BRW_CONDITIONAL_GE,
elk_CMP(p,
vec1(elk_null_reg()),
ELK_CONDITIONAL_GE,
get_element(c->reg.dir, 2),
brw_imm_f(0));
elk_imm_f(0));
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
{
emit_primitives(c, c->key.fill_ccw, c->key.offset_ccw);
}
brw_ELSE(p);
elk_ELSE(p);
{
emit_primitives(c, c->key.fill_cw, c->key.offset_cw);
}
brw_ENDIF(p);
elk_ENDIF(p);
}
else if (c->key.fill_cw != BRW_CLIP_FILL_MODE_CULL) {
else if (c->key.fill_cw != ELK_CLIP_FILL_MODE_CULL) {
emit_primitives(c, c->key.fill_cw, c->key.offset_cw);
}
else if (c->key.fill_ccw != BRW_CLIP_FILL_MODE_CULL) {
else if (c->key.fill_ccw != ELK_CLIP_FILL_MODE_CULL) {
emit_primitives(c, c->key.fill_ccw, c->key.offset_ccw);
}
}
@@ -453,39 +453,39 @@ static void emit_unfilled_primitives( struct brw_clip_compile *c )
static void check_nr_verts( struct brw_clip_compile *c )
static void check_nr_verts( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.nr_verts, brw_imm_d(3));
brw_IF(p, BRW_EXECUTE_1);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_L, c->reg.nr_verts, elk_imm_d(3));
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_kill_thread(c);
elk_clip_kill_thread(c);
}
brw_ENDIF(p);
elk_ENDIF(p);
}
void brw_emit_unfilled_clip( struct brw_clip_compile *c )
void elk_emit_unfilled_clip( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
c->need_direction = ((c->key.offset_ccw || c->key.offset_cw) ||
(c->key.fill_ccw != c->key.fill_cw) ||
c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL ||
c->key.fill_cw == BRW_CLIP_FILL_MODE_CULL ||
c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL ||
c->key.fill_cw == ELK_CLIP_FILL_MODE_CULL ||
c->key.copy_bfc_cw ||
c->key.copy_bfc_ccw);
brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
brw_clip_tri_init_vertices(c);
brw_clip_init_ff_sync(c);
elk_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
elk_clip_tri_init_vertices(c);
elk_clip_init_ff_sync(c);
assert(brw_clip_have_varying(c, VARYING_SLOT_EDGE));
assert(elk_clip_have_varying(c, VARYING_SLOT_EDGE));
if (c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL &&
c->key.fill_cw == BRW_CLIP_FILL_MODE_CULL) {
brw_clip_kill_thread(c);
if (c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL &&
c->key.fill_cw == ELK_CLIP_FILL_MODE_CULL) {
elk_clip_kill_thread(c);
return;
}
@@ -496,8 +496,8 @@ void brw_emit_unfilled_clip( struct brw_clip_compile *c )
if (c->need_direction)
compute_tri_direction(c);
if (c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL ||
c->key.fill_cw == BRW_CLIP_FILL_MODE_CULL)
if (c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL ||
c->key.fill_cw == ELK_CLIP_FILL_MODE_CULL)
cull_direction(c);
if (c->key.offset_ccw ||
@@ -511,18 +511,18 @@ void brw_emit_unfilled_clip( struct brw_clip_compile *c )
/* Need to do this whether we clip or not:
*/
if (c->key.contains_flat_varying)
brw_clip_tri_flat_shade(c);
elk_clip_tri_flat_shade(c);
brw_clip_init_clipmask(c);
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, c->reg.planemask, brw_imm_ud(0));
brw_IF(p, BRW_EXECUTE_1);
elk_clip_init_clipmask(c);
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_NZ, c->reg.planemask, elk_imm_ud(0));
elk_IF(p, ELK_EXECUTE_1);
{
brw_clip_init_planes(c);
brw_clip_tri(c);
elk_clip_init_planes(c);
elk_clip_tri(c);
check_nr_verts(c);
}
brw_ENDIF(p);
elk_ENDIF(p);
emit_unfilled_primitives(c);
brw_clip_kill_thread(c);
elk_clip_kill_thread(c);
}
src/intel/compiler/elk/elk_clip_util.c
+140 -140
View File
@@ -32,9 +32,9 @@
#include "elk_clip.h"
struct brw_reg get_tmp( struct brw_clip_compile *c )
struct elk_reg get_tmp( struct elk_clip_compile *c )
{
struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0);
struct elk_reg tmp = elk_vec4_grf(c->last_tmp, 0);
if (++c->last_tmp > c->prog_data.total_grf)
c->prog_data.total_grf = c->last_tmp;
@@ -42,30 +42,30 @@ struct brw_reg get_tmp( struct brw_clip_compile *c )
return tmp;
}
static void release_tmp( struct brw_clip_compile *c, struct brw_reg tmp )
static void release_tmp( struct elk_clip_compile *c, struct elk_reg tmp )
{
if (tmp.nr == c->last_tmp-1)
c->last_tmp--;
}
static struct brw_reg make_plane_ud(GLuint x, GLuint y, GLuint z, GLuint w)
static struct elk_reg make_plane_ud(GLuint x, GLuint y, GLuint z, GLuint w)
{
return brw_imm_ud((w<<24) | (z<<16) | (y<<8) | x);
return elk_imm_ud((w<<24) | (z<<16) | (y<<8) | x);
}
void brw_clip_init_planes( struct brw_clip_compile *c )
void elk_clip_init_planes( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
if (!c->key.nr_userclip) {
brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1));
brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1));
brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1));
brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1));
brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1));
elk_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
elk_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1));
elk_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1));
elk_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1));
elk_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1));
elk_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1));
}
}
@@ -75,38 +75,38 @@ void brw_clip_init_planes( struct brw_clip_compile *c )
/* Project 'pos' to screen space (or back again), overwrite with results:
*/
void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos )
void elk_clip_project_position(struct elk_clip_compile *c, struct elk_reg pos )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
/* calc rhw
*/
brw_math_invert(p, get_element(pos, W), get_element(pos, W));
elk_math_invert(p, get_element(pos, W), get_element(pos, W));
/* value.xyz *= value.rhw
*/
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos,
brw_swizzle(pos, BRW_SWIZZLE_WWWW));
brw_set_default_access_mode(p, BRW_ALIGN_1);
elk_set_default_access_mode(p, ELK_ALIGN_16);
elk_MUL(p, elk_writemask(pos, WRITEMASK_XYZ), pos,
elk_swizzle(pos, ELK_SWIZZLE_WWWW));
elk_set_default_access_mode(p, ELK_ALIGN_1);
}
static void brw_clip_project_vertex( struct brw_clip_compile *c,
struct brw_indirect vert_addr )
static void elk_clip_project_vertex( struct elk_clip_compile *c,
struct elk_indirect vert_addr )
{
struct brw_codegen *p = &c->func;
struct brw_reg tmp = get_tmp(c);
GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
GLuint ndc_offset = brw_varying_to_offset(&c->vue_map,
BRW_VARYING_SLOT_NDC);
struct elk_codegen *p = &c->func;
struct elk_reg tmp = get_tmp(c);
GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
GLuint ndc_offset = elk_varying_to_offset(&c->vue_map,
ELK_VARYING_SLOT_NDC);
/* Fixup position. Extract from the original vertex and re-project
* to screen space:
*/
brw_MOV(p, tmp, deref_4f(vert_addr, hpos_offset));
brw_clip_project_position(c, tmp);
brw_MOV(p, deref_4f(vert_addr, ndc_offset), tmp);
elk_MOV(p, tmp, deref_4f(vert_addr, hpos_offset));
elk_clip_project_position(c, tmp);
elk_MOV(p, deref_4f(vert_addr, ndc_offset), tmp);
release_tmp(c, tmp);
}
@@ -119,15 +119,15 @@ static void brw_clip_project_vertex( struct brw_clip_compile *c,
*
* Beware that dest_ptr can be equal to v0_ptr!
*/
void brw_clip_interp_vertex( struct brw_clip_compile *c,
struct brw_indirect dest_ptr,
struct brw_indirect v0_ptr, /* from */
struct brw_indirect v1_ptr, /* to */
struct brw_reg t0,
void elk_clip_interp_vertex( struct elk_clip_compile *c,
struct elk_indirect dest_ptr,
struct elk_indirect v0_ptr, /* from */
struct elk_indirect v1_ptr, /* to */
struct elk_reg t0,
bool force_edgeflag)
{
struct brw_codegen *p = &c->func;
struct brw_reg t_nopersp, v0_ndc_copy;
struct elk_codegen *p = &c->func;
struct elk_reg t_nopersp, v0_ndc_copy;
GLuint slot;
/* Just copy the vertex header:
@@ -136,7 +136,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
* After CLIP stage, only first 256 bits of the VUE are read
* back on Ironlake, so needn't change it
*/
brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1);
elk_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1);
/* First handle the 3D and NDC interpolation, in case we
@@ -146,10 +146,10 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
/* Take a copy of the v0 NDC coordinates, in case dest == v0. */
if (c->key.contains_noperspective_varying) {
GLuint offset = brw_varying_to_offset(&c->vue_map,
BRW_VARYING_SLOT_NDC);
GLuint offset = elk_varying_to_offset(&c->vue_map,
ELK_VARYING_SLOT_NDC);
v0_ndc_copy = get_tmp(c);
brw_MOV(p, v0_ndc_copy, deref_4f(v0_ptr, offset));
elk_MOV(p, v0_ndc_copy, deref_4f(v0_ptr, offset));
}
/* Compute the new 3D position
@@ -157,37 +157,37 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
* dest_hpos = v0_hpos * (1 - t0) + v1_hpos * t0
*/
{
GLuint delta = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
struct brw_reg tmp = get_tmp(c);
brw_MUL(p, vec4(brw_null_reg()), deref_4f(v1_ptr, delta), t0);
brw_MAC(p, tmp, negate(deref_4f(v0_ptr, delta)), t0);
brw_ADD(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta), tmp);
GLuint delta = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
struct elk_reg tmp = get_tmp(c);
elk_MUL(p, vec4(elk_null_reg()), deref_4f(v1_ptr, delta), t0);
elk_MAC(p, tmp, negate(deref_4f(v0_ptr, delta)), t0);
elk_ADD(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta), tmp);
release_tmp(c, tmp);
}
/* Recreate the projected (NDC) coordinate in the new vertex header */
brw_clip_project_vertex(c, dest_ptr);
elk_clip_project_vertex(c, dest_ptr);
/* If we have noperspective attributes,
* we need to compute the screen-space t
*/
if (c->key.contains_noperspective_varying) {
GLuint delta = brw_varying_to_offset(&c->vue_map,
BRW_VARYING_SLOT_NDC);
struct brw_reg tmp = get_tmp(c);
GLuint delta = elk_varying_to_offset(&c->vue_map,
ELK_VARYING_SLOT_NDC);
struct elk_reg tmp = get_tmp(c);
t_nopersp = get_tmp(c);
/* t_nopersp = vec4(v1.xy, dest.xy) */
brw_MOV(p, t_nopersp, deref_4f(v1_ptr, delta));
brw_MOV(p, tmp, deref_4f(dest_ptr, delta));
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MOV(p,
brw_writemask(t_nopersp, WRITEMASK_ZW),
brw_swizzle(tmp, BRW_SWIZZLE_XYXY));
elk_MOV(p, t_nopersp, deref_4f(v1_ptr, delta));
elk_MOV(p, tmp, deref_4f(dest_ptr, delta));
elk_set_default_access_mode(p, ELK_ALIGN_16);
elk_MOV(p,
elk_writemask(t_nopersp, WRITEMASK_ZW),
elk_swizzle(tmp, ELK_SWIZZLE_XYXY));
/* t_nopersp = vec4(v1.xy, dest.xy) - v0.xyxy */
brw_ADD(p, t_nopersp, t_nopersp,
negate(brw_swizzle(v0_ndc_copy, BRW_SWIZZLE_XYXY)));
elk_ADD(p, t_nopersp, t_nopersp,
negate(elk_swizzle(v0_ndc_copy, ELK_SWIZZLE_XYXY)));
/* Add the absolute values of the X and Y deltas so that if
* the points aren't in the same place on the screen we get
@@ -199,32 +199,32 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
* t_nopersp = vec2(|v1.x -v0.x| + |v1.y -v0.y|,
* |dest.x-v0.x| + |dest.y-v0.y|)
*/
brw_ADD(p,
brw_writemask(t_nopersp, WRITEMASK_XY),
brw_abs(brw_swizzle(t_nopersp, BRW_SWIZZLE_XZXZ)),
brw_abs(brw_swizzle(t_nopersp, BRW_SWIZZLE_YWYW)));
brw_set_default_access_mode(p, BRW_ALIGN_1);
elk_ADD(p,
elk_writemask(t_nopersp, WRITEMASK_XY),
elk_abs(elk_swizzle(t_nopersp, ELK_SWIZZLE_XZXZ)),
elk_abs(elk_swizzle(t_nopersp, ELK_SWIZZLE_YWYW)));
elk_set_default_access_mode(p, ELK_ALIGN_1);
/* If the points are in the same place, just substitute a
* value to avoid divide-by-zero
*/
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ,
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_EQ,
vec1(t_nopersp),
brw_imm_f(0));
brw_IF(p, BRW_EXECUTE_1);
brw_MOV(p, t_nopersp, brw_imm_vf4(brw_float_to_vf(1.0),
brw_float_to_vf(0.0),
brw_float_to_vf(0.0),
brw_float_to_vf(0.0)));
brw_ENDIF(p);
elk_imm_f(0));
elk_IF(p, ELK_EXECUTE_1);
elk_MOV(p, t_nopersp, elk_imm_vf4(elk_float_to_vf(1.0),
elk_float_to_vf(0.0),
elk_float_to_vf(0.0),
elk_float_to_vf(0.0)));
elk_ENDIF(p);
/* Now compute t_nopersp = t_nopersp.y/t_nopersp.x and broadcast it. */
brw_math_invert(p, get_element(t_nopersp, 0), get_element(t_nopersp, 0));
brw_MUL(p, vec1(t_nopersp), vec1(t_nopersp),
elk_math_invert(p, get_element(t_nopersp, 0), get_element(t_nopersp, 0));
elk_MUL(p, vec1(t_nopersp), vec1(t_nopersp),
vec1(suboffset(t_nopersp, 1)));
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MOV(p, t_nopersp, brw_swizzle(t_nopersp, BRW_SWIZZLE_XXXX));
brw_set_default_access_mode(p, BRW_ALIGN_1);
elk_set_default_access_mode(p, ELK_ALIGN_16);
elk_MOV(p, t_nopersp, elk_swizzle(t_nopersp, ELK_SWIZZLE_XXXX));
elk_set_default_access_mode(p, ELK_ALIGN_1);
release_tmp(c, tmp);
release_tmp(c, v0_ndc_copy);
@@ -235,18 +235,18 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
*/
for (slot = 0; slot < c->vue_map.num_slots; slot++) {
int varying = c->vue_map.slot_to_varying[slot];
GLuint delta = brw_vue_slot_to_offset(slot);
GLuint delta = elk_vue_slot_to_offset(slot);
/* HPOS, NDC already handled above */
if (varying == VARYING_SLOT_POS || varying == BRW_VARYING_SLOT_NDC)
if (varying == VARYING_SLOT_POS || varying == ELK_VARYING_SLOT_NDC)
continue;
if (varying == VARYING_SLOT_EDGE) {
if (force_edgeflag)
brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1));
elk_MOV(p, deref_4f(dest_ptr, delta), elk_imm_f(1));
else
brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta));
elk_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta));
} else if (varying == VARYING_SLOT_PSIZ) {
/* PSIZ doesn't need interpolation because it isn't used by the
* fragment shader.
@@ -263,21 +263,21 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
GLuint interp = c->key.interp_mode[slot];
if (interp != INTERP_MODE_FLAT) {
struct brw_reg tmp = get_tmp(c);
struct brw_reg t =
struct elk_reg tmp = get_tmp(c);
struct elk_reg t =
interp == INTERP_MODE_NOPERSPECTIVE ? t_nopersp : t0;
brw_MUL(p,
vec4(brw_null_reg()),
elk_MUL(p,
vec4(elk_null_reg()),
deref_4f(v1_ptr, delta),
t);
brw_MAC(p,
elk_MAC(p,
tmp,
negate(deref_4f(v0_ptr, delta)),
t);
brw_ADD(p,
elk_ADD(p,
deref_4f(dest_ptr, delta),
deref_4f(v0_ptr, delta),
tmp);
@@ -285,7 +285,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
release_tmp(c, tmp);
}
else {
brw_MOV(p,
elk_MOV(p,
deref_4f(dest_ptr, delta),
deref_4f(v0_ptr, delta));
}
@@ -293,94 +293,94 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
}
if (c->vue_map.num_slots % 2) {
GLuint delta = brw_vue_slot_to_offset(c->vue_map.num_slots);
GLuint delta = elk_vue_slot_to_offset(c->vue_map.num_slots);
brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));
elk_MOV(p, deref_4f(dest_ptr, delta), elk_imm_f(0));
}
if (c->key.contains_noperspective_varying)
release_tmp(c, t_nopersp);
}
void brw_clip_emit_vue(struct brw_clip_compile *c,
struct brw_indirect vert,
enum brw_urb_write_flags flags,
void elk_clip_emit_vue(struct elk_clip_compile *c,
struct elk_indirect vert,
enum elk_urb_write_flags flags,
GLuint header)
{
struct brw_codegen *p = &c->func;
bool allocate = flags & BRW_URB_WRITE_ALLOCATE;
struct elk_codegen *p = &c->func;
bool allocate = flags & ELK_URB_WRITE_ALLOCATE;
brw_clip_ff_sync(c);
elk_clip_ff_sync(c);
/* Any URB entry that is allocated must subsequently be used or discarded,
* so it doesn't make sense to mark EOT and ALLOCATE at the same time.
*/
assert(!(allocate && (flags & BRW_URB_WRITE_EOT)));
assert(!(allocate && (flags & ELK_URB_WRITE_EOT)));
/* Copy the vertex from vertn into m1..mN+1:
*/
brw_copy_from_indirect(p, brw_message_reg(1), vert, c->nr_regs);
elk_copy_from_indirect(p, elk_message_reg(1), vert, c->nr_regs);
/* Overwrite PrimType and PrimStart in the message header, for
* each vertex in turn:
*/
brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
elk_MOV(p, get_element_ud(c->reg.R0, 2), elk_imm_ud(header));
/* Send each vertex as a separate write to the urb. This
* is different to the concept in brw_sf_emit.c, where
* is different to the concept in elk_sf_emit.c, where
* subsequent writes are used to build up a single urb
* entry. Each of these writes instantiates a separate
* urb entry - (I think... what about 'allocate'?)
*/
brw_urb_WRITE(p,
allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
elk_urb_WRITE(p,
allocate ? c->reg.R0 : retype(elk_null_reg(), ELK_REGISTER_TYPE_UD),
0,
c->reg.R0,
flags,
c->nr_regs + 1, /* msg length */
allocate ? 1 : 0, /* response_length */
0, /* urb offset */
BRW_URB_SWIZZLE_NONE);
ELK_URB_SWIZZLE_NONE);
}
void brw_clip_kill_thread(struct brw_clip_compile *c)
void elk_clip_kill_thread(struct elk_clip_compile *c)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
brw_clip_ff_sync(c);
elk_clip_ff_sync(c);
/* Send an empty message to kill the thread and release any
* allocated urb entry:
*/
brw_urb_WRITE(p,
retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
elk_urb_WRITE(p,
retype(elk_null_reg(), ELK_REGISTER_TYPE_UD),
0,
c->reg.R0,
BRW_URB_WRITE_UNUSED | BRW_URB_WRITE_EOT_COMPLETE,
ELK_URB_WRITE_UNUSED | ELK_URB_WRITE_EOT_COMPLETE,
1, /* msg len */
0, /* response len */
0,
BRW_URB_SWIZZLE_NONE);
ELK_URB_SWIZZLE_NONE);
}
struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c )
struct elk_reg elk_clip_plane0_address( struct elk_clip_compile *c )
{
return brw_address(c->reg.fixed_planes);
return elk_address(c->reg.fixed_planes);
}
struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c )
struct elk_reg elk_clip_plane_stride( struct elk_clip_compile *c )
{
if (c->key.nr_userclip) {
return brw_imm_uw(16);
return elk_imm_uw(16);
}
else {
return brw_imm_uw(4);
return elk_imm_uw(4);
}
}
@@ -388,60 +388,60 @@ struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c )
/* Distribute flatshaded attributes from provoking vertex prior to
* clipping.
*/
void brw_clip_copy_flatshaded_attributes( struct brw_clip_compile *c,
void elk_clip_copy_flatshaded_attributes( struct elk_clip_compile *c,
GLuint to, GLuint from )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
for (int i = 0; i < c->vue_map.num_slots; i++) {
if (c->key.interp_mode[i] == INTERP_MODE_FLAT) {
brw_MOV(p,
byte_offset(c->reg.vertex[to], brw_vue_slot_to_offset(i)),
byte_offset(c->reg.vertex[from], brw_vue_slot_to_offset(i)));
elk_MOV(p,
byte_offset(c->reg.vertex[to], elk_vue_slot_to_offset(i)),
byte_offset(c->reg.vertex[from], elk_vue_slot_to_offset(i)));
}
}
}
void brw_clip_init_clipmask( struct brw_clip_compile *c )
void elk_clip_init_clipmask( struct elk_clip_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
struct elk_codegen *p = &c->func;
struct elk_reg incoming = get_element_ud(c->reg.R0, 2);
/* Shift so that lowest outcode bit is rightmost:
*/
brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26));
elk_SHR(p, c->reg.planemask, incoming, elk_imm_ud(26));
if (c->key.nr_userclip) {
struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD);
struct elk_reg tmp = retype(vec1(get_tmp(c)), ELK_REGISTER_TYPE_UD);
/* Rearrange userclip outcodes so that they come directly after
* the fixed plane bits.
*/
if (p->devinfo->ver == 5 || p->devinfo->verx10 == 45)
brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14));
elk_AND(p, tmp, incoming, elk_imm_ud(0xff<<14));
else
brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
elk_AND(p, tmp, incoming, elk_imm_ud(0x3f<<14));
brw_SHR(p, tmp, tmp, brw_imm_ud(8));
brw_OR(p, c->reg.planemask, c->reg.planemask, tmp);
elk_SHR(p, tmp, tmp, elk_imm_ud(8));
elk_OR(p, c->reg.planemask, c->reg.planemask, tmp);
release_tmp(c, tmp);
}
}
void brw_clip_ff_sync(struct brw_clip_compile *c)
void elk_clip_ff_sync(struct elk_clip_compile *c)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
if (p->devinfo->ver == 5) {
brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
brw_IF(p, BRW_EXECUTE_1);
elk_AND(p, elk_null_reg(), c->reg.ff_sync, elk_imm_ud(0x1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_Z);
elk_IF(p, ELK_EXECUTE_1);
{
brw_OR(p, c->reg.ff_sync, c->reg.ff_sync, brw_imm_ud(0x1));
brw_ff_sync(p,
elk_OR(p, c->reg.ff_sync, c->reg.ff_sync, elk_imm_ud(0x1));
elk_ff_sync(p,
c->reg.R0,
0,
c->reg.R0,
@@ -449,16 +449,16 @@ void brw_clip_ff_sync(struct brw_clip_compile *c)
1, /* response length */
0 /* eot */);
}
brw_ENDIF(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_ENDIF(p);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
}
}
void brw_clip_init_ff_sync(struct brw_clip_compile *c)
void elk_clip_init_ff_sync(struct elk_clip_compile *c)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
if (p->devinfo->ver == 5) {
brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0));
elk_MOV(p, c->reg.ff_sync, elk_imm_ud(0));
}
}
src/intel/compiler/elk/elk_compile_clip.c
+13 -13
View File
@@ -27,19 +27,19 @@
#include "dev/intel_debug.h"
const unsigned *
brw_compile_clip(const struct brw_compiler *compiler,
elk_compile_clip(const struct elk_compiler *compiler,
void *mem_ctx,
const struct brw_clip_prog_key *key,
struct brw_clip_prog_data *prog_data,
const struct elk_clip_prog_key *key,
struct elk_clip_prog_data *prog_data,
struct intel_vue_map *vue_map,
unsigned *final_assembly_size)
{
struct brw_clip_compile c;
struct elk_clip_compile c;
memset(&c, 0, sizeof(c));
/* Begin the compilation:
*/
brw_init_codegen(&compiler->isa, &c.func, mem_ctx);
elk_init_codegen(&compiler->isa, &c.func, mem_ctx);
c.func.single_program_flow = 1;
@@ -58,7 +58,7 @@ brw_compile_clip(const struct brw_compiler *compiler,
/* For some reason the thread is spawned with only 4 channels
* unmasked.
*/
brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE);
elk_set_default_mask_control(&c.func, ELK_MASK_DISABLE);
/* Would ideally have the option of producing a program which could
* do all three:
@@ -66,29 +66,29 @@ brw_compile_clip(const struct brw_compiler *compiler,
switch (key->primitive) {
case MESA_PRIM_TRIANGLES:
if (key->do_unfilled)
brw_emit_unfilled_clip( &c );
elk_emit_unfilled_clip( &c );
else
brw_emit_tri_clip( &c );
elk_emit_tri_clip( &c );
break;
case MESA_PRIM_LINES:
brw_emit_line_clip( &c );
elk_emit_line_clip( &c );
break;
case MESA_PRIM_POINTS:
brw_emit_point_clip( &c );
elk_emit_point_clip( &c );
break;
default:
unreachable("not reached");
}
brw_compact_instructions(&c.func, 0, NULL);
elk_compact_instructions(&c.func, 0, NULL);
*prog_data = c.prog_data;
const unsigned *program = brw_get_program(&c.func, final_assembly_size);
const unsigned *program = elk_get_program(&c.func, final_assembly_size);
if (INTEL_DEBUG(DEBUG_CLIP)) {
fprintf(stderr, "clip:\n");
brw_disassemble_with_labels(&compiler->isa,
elk_disassemble_with_labels(&compiler->isa,
program, 0, *final_assembly_size, stderr);
fprintf(stderr, "\n");
}
src/intel/compiler/elk/elk_compile_ff_gs.c
+174 -174
View File
@@ -38,30 +38,30 @@
#define MAX_GS_VERTS (4)
struct brw_ff_gs_compile {
struct brw_codegen func;
struct brw_ff_gs_prog_key key;
struct brw_ff_gs_prog_data *prog_data;
struct elk_ff_gs_compile {
struct elk_codegen func;
struct elk_ff_gs_prog_key key;
struct elk_ff_gs_prog_data *prog_data;
struct {
struct brw_reg R0;
struct elk_reg R0;
/**
* Register holding streamed vertex buffer pointers -- see the Sandy
* Bridge PRM, volume 2 part 1, section 4.4.2 (GS Thread Payload
* [DevSNB]). These pointers are delivered in GRF 1.
*/
struct brw_reg SVBI;
struct elk_reg SVBI;
struct brw_reg vertex[MAX_GS_VERTS];
struct brw_reg header;
struct brw_reg temp;
struct elk_reg vertex[MAX_GS_VERTS];
struct elk_reg header;
struct elk_reg temp;
/**
* Register holding destination indices for streamed buffer writes.
* Only used for SOL programs.
*/
struct brw_reg destination_indices;
struct elk_reg destination_indices;
} reg;
/* Number of registers used to store vertex data */
@@ -80,7 +80,7 @@ struct brw_ff_gs_compile {
*
* - The thread will need to use the destination_indices register.
*/
static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c,
static void elk_ff_gs_alloc_regs(struct elk_ff_gs_compile *c,
GLuint nr_verts,
bool sol_program)
{
@@ -88,25 +88,25 @@ static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c,
/* Register usage is static, precompute here:
*/
c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
c->reg.R0 = retype(elk_vec8_grf(i, 0), ELK_REGISTER_TYPE_UD); i++;
/* Streamed vertex buffer indices */
if (sol_program)
c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
c->reg.SVBI = retype(elk_vec8_grf(i++, 0), ELK_REGISTER_TYPE_UD);
/* Payload vertices plus space for more generated vertices:
*/
for (j = 0; j < nr_verts; j++) {
c->reg.vertex[j] = brw_vec4_grf(i, 0);
c->reg.vertex[j] = elk_vec4_grf(i, 0);
i += c->nr_regs;
}
c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
c->reg.header = retype(elk_vec8_grf(i++, 0), ELK_REGISTER_TYPE_UD);
c->reg.temp = retype(elk_vec8_grf(i++, 0), ELK_REGISTER_TYPE_UD);
if (sol_program) {
c->reg.destination_indices =
retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD);
retype(elk_vec4_grf(i++, 0), ELK_REGISTER_TYPE_UD);
}
c->prog_data->urb_read_length = c->nr_regs;
@@ -128,10 +128,10 @@ static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c,
* This function sets up the above data by copying by copying the contents of
* R0 to the header register.
*/
static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c)
static void elk_ff_gs_initialize_header(struct elk_ff_gs_compile *c)
{
struct brw_codegen *p = &c->func;
brw_MOV(p, c->reg.header, c->reg.R0);
struct elk_codegen *p = &c->func;
elk_MOV(p, c->reg.header, c->reg.R0);
}
/**
@@ -141,11 +141,11 @@ static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c)
* PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
* need to be able to update on a per-vertex basis.
*/
static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c,
static void elk_ff_gs_overwrite_header_dw2(struct elk_ff_gs_compile *c,
unsigned dw2)
{
struct brw_codegen *p = &c->func;
brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
struct elk_codegen *p = &c->func;
elk_MOV(p, get_element_ud(c->reg.header, 2), elk_imm_ud(dw2));
}
/**
@@ -156,13 +156,13 @@ static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c,
* DWORD 2. So this function extracts the primitive type field, bitshifts it
* appropriately, and stores it in c->reg.header.
*/
static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c)
static void elk_ff_gs_overwrite_header_dw2_from_r0(struct elk_ff_gs_compile *c)
{
struct brw_codegen *p = &c->func;
brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
brw_imm_ud(0x1f));
brw_SHL(p, get_element_ud(c->reg.header, 2),
get_element_ud(c->reg.header, 2), brw_imm_ud(2));
struct elk_codegen *p = &c->func;
elk_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
elk_imm_ud(0x1f));
elk_SHL(p, get_element_ud(c->reg.header, 2),
get_element_ud(c->reg.header, 2), elk_imm_ud(2));
}
/**
@@ -171,12 +171,12 @@ static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c)
* This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
* for each vertex.
*/
static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c,
static void elk_ff_gs_offset_header_dw2(struct elk_ff_gs_compile *c,
int offset)
{
struct brw_codegen *p = &c->func;
brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
brw_imm_d(offset));
struct elk_codegen *p = &c->func;
elk_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
elk_imm_d(offset));
}
@@ -192,11 +192,11 @@ static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c,
* will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
* message.
*/
static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c,
struct brw_reg vert,
static void elk_ff_gs_emit_vue(struct elk_ff_gs_compile *c,
struct elk_reg vert,
bool last)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
int write_offset = 0;
bool complete = false;
@@ -208,36 +208,36 @@ static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c,
/* Copy the vertex from vertn into m1..mN+1:
*/
brw_copy8(p, brw_message_reg(1), offset(vert, write_offset), write_len);
elk_copy8(p, elk_message_reg(1), offset(vert, write_offset), write_len);
/* Send the vertex data to the URB. If this is the last write for this
* vertex, then we mark it as complete, and either end the thread or
* allocate another vertex URB entry (depending whether this is the last
* vertex).
*/
enum brw_urb_write_flags flags;
enum elk_urb_write_flags flags;
if (!complete)
flags = BRW_URB_WRITE_NO_FLAGS;
flags = ELK_URB_WRITE_NO_FLAGS;
else if (last)
flags = BRW_URB_WRITE_EOT_COMPLETE;
flags = ELK_URB_WRITE_EOT_COMPLETE;
else
flags = BRW_URB_WRITE_ALLOCATE_COMPLETE;
brw_urb_WRITE(p,
(flags & BRW_URB_WRITE_ALLOCATE) ? c->reg.temp
: retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
flags = ELK_URB_WRITE_ALLOCATE_COMPLETE;
elk_urb_WRITE(p,
(flags & ELK_URB_WRITE_ALLOCATE) ? c->reg.temp
: retype(elk_null_reg(), ELK_REGISTER_TYPE_UD),
0,
c->reg.header,
flags,
write_len + 1, /* msg length */
(flags & BRW_URB_WRITE_ALLOCATE) ? 1
(flags & ELK_URB_WRITE_ALLOCATE) ? 1
: 0, /* response length */
write_offset, /* urb offset */
BRW_URB_SWIZZLE_NONE);
ELK_URB_SWIZZLE_NONE);
write_offset += write_len;
} while (!complete);
if (!last) {
brw_MOV(p, get_element_ud(c->reg.header, 0),
elk_MOV(p, get_element_ud(c->reg.header, 0),
get_element_ud(c->reg.temp, 0));
}
}
@@ -252,112 +252,112 @@ static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c,
* the allocated URB entry (which will be needed by the URB_WRITE meesage that
* follows).
*/
static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile *c, int num_prim)
static void elk_ff_gs_ff_sync(struct elk_ff_gs_compile *c, int num_prim)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
brw_ff_sync(p,
elk_MOV(p, get_element_ud(c->reg.header, 1), elk_imm_ud(num_prim));
elk_ff_sync(p,
c->reg.temp,
0,
c->reg.header,
1, /* allocate */
1, /* response length */
0 /* eot */);
brw_MOV(p, get_element_ud(c->reg.header, 0),
elk_MOV(p, get_element_ud(c->reg.header, 0),
get_element_ud(c->reg.temp, 0));
}
static void
brw_ff_gs_quads(struct brw_ff_gs_compile *c,
const struct brw_ff_gs_prog_key *key)
elk_ff_gs_quads(struct elk_ff_gs_compile *c,
const struct elk_ff_gs_prog_key *key)
{
brw_ff_gs_alloc_regs(c, 4, false);
brw_ff_gs_initialize_header(c);
elk_ff_gs_alloc_regs(c, 4, false);
elk_ff_gs_initialize_header(c);
/* Use polygons for correct edgeflag behaviour. Note that vertex 3
* is the PV for quads, but vertex 0 for polygons:
*/
if (c->func.devinfo->ver == 5)
brw_ff_gs_ff_sync(c, 1);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_ff_sync(c, 1);
elk_ff_gs_overwrite_header_dw2(
c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_START));
if (key->pv_first) {
brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
elk_ff_gs_overwrite_header_dw2(
c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
elk_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
elk_ff_gs_overwrite_header_dw2(
c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_END));
brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
elk_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
}
else {
brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
elk_ff_gs_overwrite_header_dw2(
c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
elk_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
elk_ff_gs_overwrite_header_dw2(
c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_END));
brw_ff_gs_emit_vue(c, c->reg.vertex[2], 1);
elk_ff_gs_emit_vue(c, c->reg.vertex[2], 1);
}
}
static void
brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c,
const struct brw_ff_gs_prog_key *key)
elk_ff_gs_quad_strip(struct elk_ff_gs_compile *c,
const struct elk_ff_gs_prog_key *key)
{
brw_ff_gs_alloc_regs(c, 4, false);
brw_ff_gs_initialize_header(c);
elk_ff_gs_alloc_regs(c, 4, false);
elk_ff_gs_initialize_header(c);
if (c->func.devinfo->ver == 5)
brw_ff_gs_ff_sync(c, 1);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_ff_sync(c, 1);
elk_ff_gs_overwrite_header_dw2(
c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_START));
if (key->pv_first) {
brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
elk_ff_gs_overwrite_header_dw2(
c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
elk_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
elk_ff_gs_overwrite_header_dw2(
c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_END));
brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
elk_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
}
else {
brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
elk_ff_gs_overwrite_header_dw2(
c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
elk_ff_gs_overwrite_header_dw2(
c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_END));
brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
elk_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
}
}
static void brw_ff_gs_lines(struct brw_ff_gs_compile *c)
static void elk_ff_gs_lines(struct elk_ff_gs_compile *c)
{
brw_ff_gs_alloc_regs(c, 2, false);
brw_ff_gs_initialize_header(c);
elk_ff_gs_alloc_regs(c, 2, false);
elk_ff_gs_initialize_header(c);
if (c->func.devinfo->ver == 5)
brw_ff_gs_ff_sync(c, 1);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_ff_sync(c, 1);
elk_ff_gs_overwrite_header_dw2(
c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_START));
brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
brw_ff_gs_overwrite_header_dw2(
elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
elk_ff_gs_overwrite_header_dw2(
c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
| URB_WRITE_PRIM_END));
brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
elk_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
}
/**
@@ -365,20 +365,20 @@ static void brw_ff_gs_lines(struct brw_ff_gs_compile *c)
* (transform feedback).
*/
static void
gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *key,
gfx6_sol_program(struct elk_ff_gs_compile *c, const struct elk_ff_gs_prog_key *key,
unsigned num_verts, bool check_edge_flags)
{
struct brw_codegen *p = &c->func;
brw_inst *inst;
struct elk_codegen *p = &c->func;
elk_inst *inst;
c->prog_data->svbi_postincrement_value = num_verts;
brw_ff_gs_alloc_regs(c, num_verts, true);
brw_ff_gs_initialize_header(c);
elk_ff_gs_alloc_regs(c, num_verts, true);
elk_ff_gs_initialize_header(c);
if (key->num_transform_feedback_bindings > 0) {
unsigned vertex, binding;
struct brw_reg destination_indices_uw =
vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
struct elk_reg destination_indices_uw =
vec8(retype(c->reg.destination_indices, ELK_REGISTER_TYPE_UW));
/* Note: since we use the binding table to keep track of buffer offsets
* and stride, the GS doesn't need to keep track of a separate pointer
@@ -388,12 +388,12 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k
*
* Make sure that the buffers have enough room for all the vertices.
*/
brw_ADD(p, get_element_ud(c->reg.temp, 0),
get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
elk_ADD(p, get_element_ud(c->reg.temp, 0),
get_element_ud(c->reg.SVBI, 0), elk_imm_ud(num_verts));
elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_LE,
get_element_ud(c->reg.temp, 0),
get_element_ud(c->reg.SVBI, 4));
brw_IF(p, BRW_EXECUTE_1);
elk_IF(p, ELK_EXECUTE_1);
/* Compute the destination indices to write to. Usually we use SVBI[0]
* + (0, 1, 2). However, for odd-numbered triangles in tristrips, the
@@ -404,7 +404,7 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k
* vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
* the last provoking vertex convention.
*
* Note: since brw_imm_v can only be used in instructions in
* Note: since elk_imm_v can only be used in instructions in
* packed-word execution mode, and SVBI is a double-word, we need to
* first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
* or (1, 0, 2)) to the destination_indices register, and then add SVBI
@@ -413,42 +413,42 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k
* destination_indices, we need to intersperse zeros to fill the upper
* halves of each double-word.
*/
brw_MOV(p, destination_indices_uw,
brw_imm_v(0x00020100)); /* (0, 1, 2) */
elk_MOV(p, destination_indices_uw,
elk_imm_v(0x00020100)); /* (0, 1, 2) */
if (num_verts == 3) {
/* Get primitive type into temp register. */
brw_AND(p, get_element_ud(c->reg.temp, 0),
get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
elk_AND(p, get_element_ud(c->reg.temp, 0),
get_element_ud(c->reg.R0, 2), elk_imm_ud(0x1f));
/* Test if primitive type is TRISTRIP_REVERSE. We need to do this as
* an 8-wide comparison so that the conditional MOV that follows
* moves all 8 words correctly.
*/
brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
elk_CMP(p, vec8(elk_null_reg()), ELK_CONDITIONAL_EQ,
get_element_ud(c->reg.temp, 0),
brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
elk_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
/* If so, then overwrite destination_indices_uw with the appropriate
* reordering.
*/
inst = brw_MOV(p, destination_indices_uw,
brw_imm_v(key->pv_first ? 0x00010200 /* (0, 2, 1) */
inst = elk_MOV(p, destination_indices_uw,
elk_imm_v(key->pv_first ? 0x00010200 /* (0, 2, 1) */
: 0x00020001)); /* (1, 0, 2) */
brw_inst_set_pred_control(p->devinfo, inst, BRW_PREDICATE_NORMAL);
elk_inst_set_pred_control(p->devinfo, inst, ELK_PREDICATE_NORMAL);
}
assert(c->reg.destination_indices.width == BRW_EXECUTE_4);
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_4);
brw_ADD(p, c->reg.destination_indices,
assert(c->reg.destination_indices.width == ELK_EXECUTE_4);
elk_push_insn_state(p);
elk_set_default_exec_size(p, ELK_EXECUTE_4);
elk_ADD(p, c->reg.destination_indices,
c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
brw_pop_insn_state(p);
elk_pop_insn_state(p);
/* For each vertex, generate code to output each varying using the
* appropriate binding table entry.
*/
for (vertex = 0; vertex < num_verts; ++vertex) {
/* Set up the correct destination index for this vertex */
brw_MOV(p, get_element_ud(c->reg.header, 5),
elk_MOV(p, get_element_ud(c->reg.header, 5),
get_element_ud(c->reg.destination_indices, vertex));
for (binding = 0; binding < key->num_transform_feedback_bindings;
@@ -465,36 +465,36 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k
bool final_write =
binding == key->num_transform_feedback_bindings - 1 &&
vertex == num_verts - 1;
struct brw_reg vertex_slot = c->reg.vertex[vertex];
struct elk_reg vertex_slot = c->reg.vertex[vertex];
vertex_slot.nr += slot / 2;
vertex_slot.subnr = (slot % 2) * 16;
/* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
vertex_slot.swizzle = varying == VARYING_SLOT_PSIZ
? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_4);
? ELK_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
elk_set_default_access_mode(p, ELK_ALIGN_16);
elk_push_insn_state(p);
elk_set_default_exec_size(p, ELK_EXECUTE_4);
brw_MOV(p, stride(c->reg.header, 4, 4, 1),
retype(vertex_slot, BRW_REGISTER_TYPE_UD));
brw_pop_insn_state(p);
elk_MOV(p, stride(c->reg.header, 4, 4, 1),
retype(vertex_slot, ELK_REGISTER_TYPE_UD));
elk_pop_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_svb_write(p,
final_write ? c->reg.temp : brw_null_reg(), /* dest */
elk_set_default_access_mode(p, ELK_ALIGN_1);
elk_svb_write(p,
final_write ? c->reg.temp : elk_null_reg(), /* dest */
1, /* msg_reg_nr */
c->reg.header, /* src0 */
BRW_GFX6_SOL_BINDING_START + binding, /* binding_table_index */
ELK_GFX6_SOL_BINDING_START + binding, /* binding_table_index */
final_write); /* send_commit_msg */
}
}
brw_ENDIF(p);
elk_ENDIF(p);
/* Now, reinitialize the header register from R0 to restore the parts of
* the register that we overwrote while streaming out transform feedback
* data.
*/
brw_ff_gs_initialize_header(c);
elk_ff_gs_initialize_header(c);
/* Finally, wait for the write commit to occur so that we can proceed to
* other things safely.
@@ -506,68 +506,68 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k
* register. Thus, a simple “mov” instruction using the register as a
* source is sufficient to wait for the write commit to occur.
*/
brw_MOV(p, c->reg.temp, c->reg.temp);
elk_MOV(p, c->reg.temp, c->reg.temp);
}
brw_ff_gs_ff_sync(c, 1);
elk_ff_gs_ff_sync(c, 1);
brw_ff_gs_overwrite_header_dw2_from_r0(c);
elk_ff_gs_overwrite_header_dw2_from_r0(c);
switch (num_verts) {
case 1:
brw_ff_gs_offset_header_dw2(c,
elk_ff_gs_offset_header_dw2(c,
URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
brw_ff_gs_emit_vue(c, c->reg.vertex[0], true);
elk_ff_gs_emit_vue(c, c->reg.vertex[0], true);
break;
case 2:
brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
brw_ff_gs_offset_header_dw2(c,
elk_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
elk_ff_gs_emit_vue(c, c->reg.vertex[0], false);
elk_ff_gs_offset_header_dw2(c,
URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
brw_ff_gs_emit_vue(c, c->reg.vertex[1], true);
elk_ff_gs_emit_vue(c, c->reg.vertex[1], true);
break;
case 3:
if (check_edge_flags) {
/* Only emit vertices 0 and 1 if this is the first triangle of the
* polygon. Otherwise they are redundant.
*/
brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
elk_AND(p, retype(elk_null_reg(), ELK_REGISTER_TYPE_UD),
get_element_ud(c->reg.R0, 2),
brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
elk_imm_ud(ELK_GS_EDGE_INDICATOR_0));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_IF(p, ELK_EXECUTE_1);
}
brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
brw_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
brw_ff_gs_emit_vue(c, c->reg.vertex[1], false);
elk_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
elk_ff_gs_emit_vue(c, c->reg.vertex[0], false);
elk_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
elk_ff_gs_emit_vue(c, c->reg.vertex[1], false);
if (check_edge_flags) {
brw_ENDIF(p);
elk_ENDIF(p);
/* Only emit vertex 2 in PRIM_END mode if this is the last triangle
* of the polygon. Otherwise leave the primitive incomplete because
* there are more polygon vertices coming.
*/
brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
elk_AND(p, retype(elk_null_reg(), ELK_REGISTER_TYPE_UD),
get_element_ud(c->reg.R0, 2),
brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
elk_imm_ud(ELK_GS_EDGE_INDICATOR_1));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL);
}
brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_ff_gs_emit_vue(c, c->reg.vertex[2], true);
elk_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
elk_ff_gs_emit_vue(c, c->reg.vertex[2], true);
break;
}
}
const unsigned *
brw_compile_ff_gs_prog(struct brw_compiler *compiler,
elk_compile_ff_gs_prog(struct elk_compiler *compiler,
void *mem_ctx,
const struct brw_ff_gs_prog_key *key,
struct brw_ff_gs_prog_data *prog_data,
const struct elk_ff_gs_prog_key *key,
struct elk_ff_gs_prog_data *prog_data,
struct intel_vue_map *vue_map,
unsigned *final_assembly_size)
{
struct brw_ff_gs_compile c;
struct elk_ff_gs_compile c;
const GLuint *program;
memset(&c, 0, sizeof(c));
@@ -581,14 +581,14 @@ brw_compile_ff_gs_prog(struct brw_compiler *compiler,
/* Begin the compilation:
*/
brw_init_codegen(&compiler->isa, &c.func, mem_ctx);
elk_init_codegen(&compiler->isa, &c.func, mem_ctx);
c.func.single_program_flow = 1;
/* For some reason the thread is spawned with only 4 channels
* unmasked.
*/
brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE);
elk_set_default_mask_control(&c.func, ELK_MASK_DISABLE);
if (compiler->devinfo->ver >= 6) {
unsigned num_verts;
@@ -631,28 +631,28 @@ brw_compile_ff_gs_prog(struct brw_compiler *compiler,
*/
switch (key->primitive) {
case _3DPRIM_QUADLIST:
brw_ff_gs_quads( &c, key );
elk_ff_gs_quads( &c, key );
break;
case _3DPRIM_QUADSTRIP:
brw_ff_gs_quad_strip( &c, key );
elk_ff_gs_quad_strip( &c, key );
break;
case _3DPRIM_LINELOOP:
brw_ff_gs_lines( &c );
elk_ff_gs_lines( &c );
break;
default:
return NULL;
}
}
brw_compact_instructions(&c.func, 0, NULL);
elk_compact_instructions(&c.func, 0, NULL);
/* get the program
*/
program = brw_get_program(&c.func, final_assembly_size);
program = elk_get_program(&c.func, final_assembly_size);
if (INTEL_DEBUG(DEBUG_GS)) {
fprintf(stderr, "gs:\n");
brw_disassemble_with_labels(&compiler->isa, c.func.store,
elk_disassemble_with_labels(&compiler->isa, c.func.store,
0, *final_assembly_size, stderr);
fprintf(stderr, "\n");
}
src/intel/compiler/elk/elk_compile_sf.c
+227 -227
View File
@@ -28,37 +28,37 @@
#include "dev/intel_debug.h"
struct brw_sf_compile {
struct brw_codegen func;
struct brw_sf_prog_key key;
struct brw_sf_prog_data prog_data;
struct elk_sf_compile {
struct elk_codegen func;
struct elk_sf_prog_key key;
struct elk_sf_prog_data prog_data;
struct brw_reg pv;
struct brw_reg det;
struct brw_reg dx0;
struct brw_reg dx2;
struct brw_reg dy0;
struct brw_reg dy2;
struct elk_reg pv;
struct elk_reg det;
struct elk_reg dx0;
struct elk_reg dx2;
struct elk_reg dy0;
struct elk_reg dy2;
/* z and 1/w passed in separately:
*/
struct brw_reg z[3];
struct brw_reg inv_w[3];
struct elk_reg z[3];
struct elk_reg inv_w[3];
/* The vertices:
*/
struct brw_reg vert[3];
struct elk_reg vert[3];
/* Temporaries, allocated after last vertex reg.
*/
struct brw_reg inv_det;
struct brw_reg a1_sub_a0;
struct brw_reg a2_sub_a0;
struct brw_reg tmp;
struct elk_reg inv_det;
struct elk_reg a1_sub_a0;
struct elk_reg a2_sub_a0;
struct elk_reg tmp;
struct brw_reg m1Cx;
struct brw_reg m2Cy;
struct brw_reg m3C0;
struct elk_reg m1Cx;
struct elk_reg m2Cy;
struct elk_reg m3C0;
GLuint nr_verts;
GLuint nr_attr_regs;
@@ -74,7 +74,7 @@ struct brw_sf_compile {
/**
* Determine the vue slot corresponding to the given half of the given register.
*/
static inline int vert_reg_to_vue_slot(struct brw_sf_compile *c, GLuint reg,
static inline int vert_reg_to_vue_slot(struct elk_sf_compile *c, GLuint reg,
int half)
{
return (reg + c->urb_entry_read_offset) * 2 + half;
@@ -85,7 +85,7 @@ static inline int vert_reg_to_vue_slot(struct brw_sf_compile *c, GLuint reg,
* register. half=0 means the first half of a register, half=1 means the
* second half.
*/
static inline int vert_reg_to_varying(struct brw_sf_compile *c, GLuint reg,
static inline int vert_reg_to_varying(struct elk_sf_compile *c, GLuint reg,
int half)
{
int vue_slot = vert_reg_to_vue_slot(c, reg, half);
@@ -95,21 +95,21 @@ static inline int vert_reg_to_varying(struct brw_sf_compile *c, GLuint reg,
/**
* Determine the register corresponding to the given vue slot
*/
static struct brw_reg get_vue_slot(struct brw_sf_compile *c,
struct brw_reg vert,
static struct elk_reg get_vue_slot(struct elk_sf_compile *c,
struct elk_reg vert,
int vue_slot)
{
GLuint off = vue_slot / 2 - c->urb_entry_read_offset;
GLuint sub = vue_slot % 2;
return brw_vec4_grf(vert.nr + off, sub * 4);
return elk_vec4_grf(vert.nr + off, sub * 4);
}
/**
* Determine the register corresponding to the given varying.
*/
static struct brw_reg get_varying(struct brw_sf_compile *c,
struct brw_reg vert,
static struct elk_reg get_varying(struct elk_sf_compile *c,
struct elk_reg vert,
GLuint varying)
{
int vue_slot = c->vue_map.varying_to_slot[varying];
@@ -118,7 +118,7 @@ static struct brw_reg get_varying(struct brw_sf_compile *c,
}
static bool
have_attr(struct brw_sf_compile *c, GLuint attr)
have_attr(struct elk_sf_compile *c, GLuint attr)
{
return (c->key.attrs & BITFIELD64_BIT(attr)) ? 1 : 0;
}
@@ -126,30 +126,30 @@ have_attr(struct brw_sf_compile *c, GLuint attr)
/***********************************************************************
* Twoside lighting
*/
static void copy_bfc( struct brw_sf_compile *c,
struct brw_reg vert )
static void copy_bfc( struct elk_sf_compile *c,
struct elk_reg vert )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint i;
for (i = 0; i < 2; i++) {
if (have_attr(c, VARYING_SLOT_COL0+i) &&
have_attr(c, VARYING_SLOT_BFC0+i))
brw_MOV(p,
elk_MOV(p,
get_varying(c, vert, VARYING_SLOT_COL0+i),
get_varying(c, vert, VARYING_SLOT_BFC0+i));
}
}
static void do_twoside_color( struct brw_sf_compile *c )
static void do_twoside_color( struct elk_sf_compile *c )
{
struct brw_codegen *p = &c->func;
GLuint backface_conditional = c->key.frontface_ccw ? BRW_CONDITIONAL_G : BRW_CONDITIONAL_L;
struct elk_codegen *p = &c->func;
GLuint backface_conditional = c->key.frontface_ccw ? ELK_CONDITIONAL_G : ELK_CONDITIONAL_L;
/* Already done in clip program:
*/
if (c->key.primitive == BRW_SF_PRIM_UNFILLED_TRIS)
if (c->key.primitive == ELK_SF_PRIM_UNFILLED_TRIS)
return;
/* If the vertex shader provides backface color, do the selection. The VS
@@ -160,13 +160,13 @@ static void do_twoside_color( struct brw_sf_compile *c )
!(have_attr(c, VARYING_SLOT_COL1) && have_attr(c, VARYING_SLOT_BFC1)))
return;
/* Need to use BRW_EXECUTE_4 and also do an 4-wide compare in order
/* Need to use ELK_EXECUTE_4 and also do an 4-wide compare in order
* to get all channels active inside the IF. In the clipping code
* we run with NoMask, so it's not an option and we can use
* BRW_EXECUTE_1 for all comparisons.
* ELK_EXECUTE_1 for all comparisons.
*/
brw_CMP(p, vec4(brw_null_reg()), backface_conditional, c->det, brw_imm_f(0));
brw_IF(p, BRW_EXECUTE_4);
elk_CMP(p, vec4(elk_null_reg()), backface_conditional, c->det, elk_imm_f(0));
elk_IF(p, ELK_EXECUTE_4);
{
switch (c->nr_verts) {
case 3: copy_bfc(c, c->vert[2]); FALLTHROUGH;
@@ -174,7 +174,7 @@ static void do_twoside_color( struct brw_sf_compile *c )
case 1: copy_bfc(c, c->vert[0]);
}
}
brw_ENDIF(p);
elk_ENDIF(p);
}
@@ -183,23 +183,23 @@ static void do_twoside_color( struct brw_sf_compile *c )
* Flat shading
*/
static void copy_flatshaded_attributes(struct brw_sf_compile *c,
struct brw_reg dst,
struct brw_reg src)
static void copy_flatshaded_attributes(struct elk_sf_compile *c,
struct elk_reg dst,
struct elk_reg src)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
int i;
for (i = 0; i < c->vue_map.num_slots; i++) {
if (c->key.interp_mode[i] == INTERP_MODE_FLAT) {
brw_MOV(p,
elk_MOV(p,
get_vue_slot(c, dst, i),
get_vue_slot(c, src, i));
}
}
}
static int count_flatshaded_attributes(struct brw_sf_compile *c)
static int count_flatshaded_attributes(struct elk_sf_compile *c)
{
int i;
int count = 0;
@@ -217,15 +217,15 @@ static int count_flatshaded_attributes(struct brw_sf_compile *c)
* vertices are ordered according to y-coordinate before reaching this
* point, so the PV could be anywhere.
*/
static void do_flatshade_triangle( struct brw_sf_compile *c )
static void do_flatshade_triangle( struct elk_sf_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint nr;
GLuint jmpi = 1;
/* Already done in clip program:
*/
if (c->key.primitive == BRW_SF_PRIM_UNFILLED_TRIS)
if (c->key.primitive == ELK_SF_PRIM_UNFILLED_TRIS)
return;
if (p->devinfo->ver == 5)
@@ -233,31 +233,31 @@ static void do_flatshade_triangle( struct brw_sf_compile *c )
nr = count_flatshaded_attributes(c);
brw_MUL(p, c->pv, c->pv, brw_imm_d(jmpi*(nr*2+1)));
brw_JMPI(p, c->pv, BRW_PREDICATE_NONE);
elk_MUL(p, c->pv, c->pv, elk_imm_d(jmpi*(nr*2+1)));
elk_JMPI(p, c->pv, ELK_PREDICATE_NONE);
copy_flatshaded_attributes(c, c->vert[1], c->vert[0]);
copy_flatshaded_attributes(c, c->vert[2], c->vert[0]);
brw_JMPI(p, brw_imm_d(jmpi*(nr*4+1)), BRW_PREDICATE_NONE);
elk_JMPI(p, elk_imm_d(jmpi*(nr*4+1)), ELK_PREDICATE_NONE);
copy_flatshaded_attributes(c, c->vert[0], c->vert[1]);
copy_flatshaded_attributes(c, c->vert[2], c->vert[1]);
brw_JMPI(p, brw_imm_d(jmpi*nr*2), BRW_PREDICATE_NONE);
elk_JMPI(p, elk_imm_d(jmpi*nr*2), ELK_PREDICATE_NONE);
copy_flatshaded_attributes(c, c->vert[0], c->vert[2]);
copy_flatshaded_attributes(c, c->vert[1], c->vert[2]);
}
static void do_flatshade_line( struct brw_sf_compile *c )
static void do_flatshade_line( struct elk_sf_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint nr;
GLuint jmpi = 1;
/* Already done in clip program:
*/
if (c->key.primitive == BRW_SF_PRIM_UNFILLED_TRIS)
if (c->key.primitive == ELK_SF_PRIM_UNFILLED_TRIS)
return;
if (p->devinfo->ver == 5)
@@ -265,11 +265,11 @@ static void do_flatshade_line( struct brw_sf_compile *c )
nr = count_flatshaded_attributes(c);
brw_MUL(p, c->pv, c->pv, brw_imm_d(jmpi*(nr+1)));
brw_JMPI(p, c->pv, BRW_PREDICATE_NONE);
elk_MUL(p, c->pv, c->pv, elk_imm_d(jmpi*(nr+1)));
elk_JMPI(p, c->pv, ELK_PREDICATE_NONE);
copy_flatshaded_attributes(c, c->vert[1], c->vert[0]);
brw_JMPI(p, brw_imm_ud(jmpi*nr), BRW_PREDICATE_NONE);
elk_JMPI(p, elk_imm_ud(jmpi*nr), ELK_PREDICATE_NONE);
copy_flatshaded_attributes(c, c->vert[0], c->vert[1]);
}
@@ -279,42 +279,42 @@ static void do_flatshade_line( struct brw_sf_compile *c )
*/
static void alloc_regs( struct brw_sf_compile *c )
static void alloc_regs( struct elk_sf_compile *c )
{
GLuint reg, i;
/* Values computed by fixed function unit:
*/
c->pv = retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_D);
c->det = brw_vec1_grf(1, 2);
c->dx0 = brw_vec1_grf(1, 3);
c->dx2 = brw_vec1_grf(1, 4);
c->dy0 = brw_vec1_grf(1, 5);
c->dy2 = brw_vec1_grf(1, 6);
c->pv = retype(elk_vec1_grf(1, 1), ELK_REGISTER_TYPE_D);
c->det = elk_vec1_grf(1, 2);
c->dx0 = elk_vec1_grf(1, 3);
c->dx2 = elk_vec1_grf(1, 4);
c->dy0 = elk_vec1_grf(1, 5);
c->dy2 = elk_vec1_grf(1, 6);
/* z and 1/w passed in separately:
*/
c->z[0] = brw_vec1_grf(2, 0);
c->inv_w[0] = brw_vec1_grf(2, 1);
c->z[1] = brw_vec1_grf(2, 2);
c->inv_w[1] = brw_vec1_grf(2, 3);
c->z[2] = brw_vec1_grf(2, 4);
c->inv_w[2] = brw_vec1_grf(2, 5);
c->z[0] = elk_vec1_grf(2, 0);
c->inv_w[0] = elk_vec1_grf(2, 1);
c->z[1] = elk_vec1_grf(2, 2);
c->inv_w[1] = elk_vec1_grf(2, 3);
c->z[2] = elk_vec1_grf(2, 4);
c->inv_w[2] = elk_vec1_grf(2, 5);
/* The vertices:
*/
reg = 3;
for (i = 0; i < c->nr_verts; i++) {
c->vert[i] = brw_vec8_grf(reg, 0);
c->vert[i] = elk_vec8_grf(reg, 0);
reg += c->nr_attr_regs;
}
/* Temporaries, allocated after last vertex reg.
*/
c->inv_det = brw_vec1_grf(reg, 0); reg++;
c->a1_sub_a0 = brw_vec8_grf(reg, 0); reg++;
c->a2_sub_a0 = brw_vec8_grf(reg, 0); reg++;
c->tmp = brw_vec8_grf(reg, 0); reg++;
c->inv_det = elk_vec1_grf(reg, 0); reg++;
c->a1_sub_a0 = elk_vec8_grf(reg, 0); reg++;
c->a2_sub_a0 = elk_vec8_grf(reg, 0); reg++;
c->tmp = elk_vec8_grf(reg, 0); reg++;
/* Note grf allocation:
*/
@@ -324,41 +324,41 @@ static void alloc_regs( struct brw_sf_compile *c )
/* Outputs of this program - interpolation coefficients for
* rasterization:
*/
c->m1Cx = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 1, 0);
c->m2Cy = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 2, 0);
c->m3C0 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 3, 0);
c->m1Cx = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 1, 0);
c->m2Cy = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 2, 0);
c->m3C0 = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 3, 0);
}
static void copy_z_inv_w( struct brw_sf_compile *c )
static void copy_z_inv_w( struct elk_sf_compile *c )
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint i;
/* Copy both scalars with a single MOV:
*/
for (i = 0; i < c->nr_verts; i++)
brw_MOV(p, vec2(suboffset(c->vert[i], 2)), vec2(c->z[i]));
elk_MOV(p, vec2(suboffset(c->vert[i], 2)), vec2(c->z[i]));
}
static void invert_det( struct brw_sf_compile *c)
static void invert_det( struct elk_sf_compile *c)
{
/* Looks like we invert all 8 elements just to get 1/det in
* position 2 !?!
*/
gfx4_math(&c->func,
elk_gfx4_math(&c->func,
c->inv_det,
BRW_MATH_FUNCTION_INV,
ELK_MATH_FUNCTION_INV,
0,
c->det,
BRW_MATH_PRECISION_FULL);
ELK_MATH_PRECISION_FULL);
}
static bool
calculate_masks(struct brw_sf_compile *c,
calculate_masks(struct elk_sf_compile *c,
GLuint reg,
GLushort *pc,
GLushort *pc_persp,
@@ -380,7 +380,7 @@ calculate_masks(struct brw_sf_compile *c,
/* Maybe only process one attribute on the final round:
*/
if (vert_reg_to_varying(c, reg, 1) != BRW_VARYING_SLOT_COUNT) {
if (vert_reg_to_varying(c, reg, 1) != ELK_VARYING_SLOT_COUNT) {
*pc |= 0xf0;
interp = c->key.interp_mode[vert_reg_to_vue_slot(c, reg, 1)];
@@ -398,7 +398,7 @@ calculate_masks(struct brw_sf_compile *c,
* (containing 2 attrs) to do point sprite coordinate replacement on.
*/
static uint16_t
calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg)
calculate_point_sprite_mask(struct elk_sf_compile *c, GLuint reg)
{
int varying1, varying2;
uint16_t pc = 0;
@@ -408,7 +408,7 @@ calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg)
if (c->key.point_sprite_coord_replace & (1 << (varying1 - VARYING_SLOT_TEX0)))
pc |= 0x0f;
}
if (varying1 == BRW_VARYING_SLOT_PNTC)
if (varying1 == ELK_VARYING_SLOT_PNTC)
pc |= 0x0f;
varying2 = vert_reg_to_varying(c, reg, 1);
@@ -417,32 +417,32 @@ calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg)
VARYING_SLOT_TEX0)))
pc |= 0xf0;
}
if (varying2 == BRW_VARYING_SLOT_PNTC)
if (varying2 == ELK_VARYING_SLOT_PNTC)
pc |= 0xf0;
return pc;
}
static void
set_predicate_control_flag_value(struct brw_codegen *p,
struct brw_sf_compile *c,
set_predicate_control_flag_value(struct elk_codegen *p,
struct elk_sf_compile *c,
unsigned value)
{
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
if (value != 0xff) {
if (value != c->flag_value) {
brw_MOV(p, brw_flag_reg(0, 0), brw_imm_uw(value));
elk_MOV(p, elk_flag_reg(0, 0), elk_imm_uw(value));
c->flag_value = value;
}
brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL);
}
}
static void brw_emit_tri_setup(struct brw_sf_compile *c, bool allocate)
static void elk_emit_tri_setup(struct elk_sf_compile *c, bool allocate)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint i;
c->flag_value = 0xff;
@@ -465,18 +465,18 @@ static void brw_emit_tri_setup(struct brw_sf_compile *c, bool allocate)
{
/* Pair of incoming attributes:
*/
struct brw_reg a0 = offset(c->vert[0], i);
struct brw_reg a1 = offset(c->vert[1], i);
struct brw_reg a2 = offset(c->vert[2], i);
struct elk_reg a0 = offset(c->vert[0], i);
struct elk_reg a1 = offset(c->vert[1], i);
struct elk_reg a2 = offset(c->vert[2], i);
GLushort pc, pc_persp, pc_linear;
bool last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
if (pc_persp)
{
set_predicate_control_flag_value(p, c, pc_persp);
brw_MUL(p, a0, a0, c->inv_w[0]);
brw_MUL(p, a1, a1, c->inv_w[1]);
brw_MUL(p, a2, a2, c->inv_w[2]);
elk_MUL(p, a0, a0, c->inv_w[0]);
elk_MUL(p, a1, a1, c->inv_w[1]);
elk_MUL(p, a2, a2, c->inv_w[2]);
}
@@ -486,52 +486,52 @@ static void brw_emit_tri_setup(struct brw_sf_compile *c, bool allocate)
{
set_predicate_control_flag_value(p, c, pc_linear);
brw_ADD(p, c->a1_sub_a0, a1, negate(a0));
brw_ADD(p, c->a2_sub_a0, a2, negate(a0));
elk_ADD(p, c->a1_sub_a0, a1, negate(a0));
elk_ADD(p, c->a2_sub_a0, a2, negate(a0));
/* calculate dA/dx
*/
brw_MUL(p, brw_null_reg(), c->a1_sub_a0, c->dy2);
brw_MAC(p, c->tmp, c->a2_sub_a0, negate(c->dy0));
brw_MUL(p, c->m1Cx, c->tmp, c->inv_det);
elk_MUL(p, elk_null_reg(), c->a1_sub_a0, c->dy2);
elk_MAC(p, c->tmp, c->a2_sub_a0, negate(c->dy0));
elk_MUL(p, c->m1Cx, c->tmp, c->inv_det);
/* calculate dA/dy
*/
brw_MUL(p, brw_null_reg(), c->a2_sub_a0, c->dx0);
brw_MAC(p, c->tmp, c->a1_sub_a0, negate(c->dx2));
brw_MUL(p, c->m2Cy, c->tmp, c->inv_det);
elk_MUL(p, elk_null_reg(), c->a2_sub_a0, c->dx0);
elk_MAC(p, c->tmp, c->a1_sub_a0, negate(c->dx2));
elk_MUL(p, c->m2Cy, c->tmp, c->inv_det);
}
{
set_predicate_control_flag_value(p, c, pc);
/* start point for interpolation
*/
brw_MOV(p, c->m3C0, a0);
elk_MOV(p, c->m3C0, a0);
/* Copy m0..m3 to URB. m0 is implicitly copied from r0 in
* the send instruction:
*/
brw_urb_WRITE(p,
brw_null_reg(),
elk_urb_WRITE(p,
elk_null_reg(),
0,
brw_vec8_grf(0, 0), /* r0, will be copied to m0 */
last ? BRW_URB_WRITE_EOT_COMPLETE
: BRW_URB_WRITE_NO_FLAGS,
elk_vec8_grf(0, 0), /* r0, will be copied to m0 */
last ? ELK_URB_WRITE_EOT_COMPLETE
: ELK_URB_WRITE_NO_FLAGS,
4, /* msg len */
0, /* response len */
i*4, /* offset */
BRW_URB_SWIZZLE_TRANSPOSE); /* XXX: Swizzle control "SF to windower" */
ELK_URB_SWIZZLE_TRANSPOSE); /* XXX: Swizzle control "SF to windower" */
}
}
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
}
static void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate)
static void elk_emit_line_setup(struct elk_sf_compile *c, bool allocate)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint i;
c->flag_value = 0xff;
@@ -550,16 +550,16 @@ static void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate)
{
/* Pair of incoming attributes:
*/
struct brw_reg a0 = offset(c->vert[0], i);
struct brw_reg a1 = offset(c->vert[1], i);
struct elk_reg a0 = offset(c->vert[0], i);
struct elk_reg a1 = offset(c->vert[1], i);
GLushort pc, pc_persp, pc_linear;
bool last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
if (pc_persp)
{
set_predicate_control_flag_value(p, c, pc_persp);
brw_MUL(p, a0, a0, c->inv_w[0]);
brw_MUL(p, a1, a1, c->inv_w[1]);
elk_MUL(p, a0, a0, c->inv_w[0]);
elk_MUL(p, a1, a1, c->inv_w[1]);
}
/* Calculate coefficients for position, color:
@@ -567,13 +567,13 @@ static void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate)
if (pc_linear) {
set_predicate_control_flag_value(p, c, pc_linear);
brw_ADD(p, c->a1_sub_a0, a1, negate(a0));
elk_ADD(p, c->a1_sub_a0, a1, negate(a0));
brw_MUL(p, c->tmp, c->a1_sub_a0, c->dx0);
brw_MUL(p, c->m1Cx, c->tmp, c->inv_det);
elk_MUL(p, c->tmp, c->a1_sub_a0, c->dx0);
elk_MUL(p, c->m1Cx, c->tmp, c->inv_det);
brw_MUL(p, c->tmp, c->a1_sub_a0, c->dy0);
brw_MUL(p, c->m2Cy, c->tmp, c->inv_det);
elk_MUL(p, c->tmp, c->a1_sub_a0, c->dy0);
elk_MUL(p, c->m2Cy, c->tmp, c->inv_det);
}
{
@@ -581,29 +581,29 @@ static void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate)
/* start point for interpolation
*/
brw_MOV(p, c->m3C0, a0);
elk_MOV(p, c->m3C0, a0);
/* Copy m0..m3 to URB.
*/
brw_urb_WRITE(p,
brw_null_reg(),
elk_urb_WRITE(p,
elk_null_reg(),
0,
brw_vec8_grf(0, 0),
last ? BRW_URB_WRITE_EOT_COMPLETE
: BRW_URB_WRITE_NO_FLAGS,
elk_vec8_grf(0, 0),
last ? ELK_URB_WRITE_EOT_COMPLETE
: ELK_URB_WRITE_NO_FLAGS,
4, /* msg len */
0, /* response len */
i*4, /* urb destination offset */
BRW_URB_SWIZZLE_TRANSPOSE);
ELK_URB_SWIZZLE_TRANSPOSE);
}
}
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
}
static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
static void elk_emit_point_sprite_setup(struct elk_sf_compile *c, bool allocate)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint i;
c->flag_value = 0xff;
@@ -615,7 +615,7 @@ static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
copy_z_inv_w(c);
for (i = 0; i < c->nr_setup_regs; i++)
{
struct brw_reg a0 = offset(c->vert[0], i);
struct elk_reg a0 = offset(c->vert[0], i);
GLushort pc, pc_persp, pc_linear, pc_coord_replace;
bool last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
@@ -624,7 +624,7 @@ static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
if (pc_persp) {
set_predicate_control_flag_value(p, c, pc_persp);
brw_MUL(p, a0, a0, c->inv_w[0]);
elk_MUL(p, a0, a0, c->inv_w[0]);
}
/* Point sprite coordinate replacement: A texcoord with this
@@ -635,67 +635,67 @@ static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
if (pc_coord_replace) {
set_predicate_control_flag_value(p, c, pc_coord_replace);
/* Calculate 1.0/PointWidth */
gfx4_math(&c->func,
elk_gfx4_math(&c->func,
c->tmp,
BRW_MATH_FUNCTION_INV,
ELK_MATH_FUNCTION_INV,
0,
c->dx0,
BRW_MATH_PRECISION_FULL);
ELK_MATH_PRECISION_FULL);
brw_set_default_access_mode(p, BRW_ALIGN_16);
elk_set_default_access_mode(p, ELK_ALIGN_16);
/* dA/dx, dA/dy */
brw_MOV(p, c->m1Cx, brw_imm_f(0.0));
brw_MOV(p, c->m2Cy, brw_imm_f(0.0));
brw_MOV(p, brw_writemask(c->m1Cx, WRITEMASK_X), c->tmp);
elk_MOV(p, c->m1Cx, elk_imm_f(0.0));
elk_MOV(p, c->m2Cy, elk_imm_f(0.0));
elk_MOV(p, elk_writemask(c->m1Cx, WRITEMASK_X), c->tmp);
if (c->key.sprite_origin_lower_left) {
brw_MOV(p, brw_writemask(c->m2Cy, WRITEMASK_Y), negate(c->tmp));
elk_MOV(p, elk_writemask(c->m2Cy, WRITEMASK_Y), negate(c->tmp));
} else {
brw_MOV(p, brw_writemask(c->m2Cy, WRITEMASK_Y), c->tmp);
elk_MOV(p, elk_writemask(c->m2Cy, WRITEMASK_Y), c->tmp);
}
/* attribute constant offset */
brw_MOV(p, c->m3C0, brw_imm_f(0.0));
elk_MOV(p, c->m3C0, elk_imm_f(0.0));
if (c->key.sprite_origin_lower_left) {
brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_YW), brw_imm_f(1.0));
elk_MOV(p, elk_writemask(c->m3C0, WRITEMASK_YW), elk_imm_f(1.0));
} else {
brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_W), brw_imm_f(1.0));
elk_MOV(p, elk_writemask(c->m3C0, WRITEMASK_W), elk_imm_f(1.0));
}
brw_set_default_access_mode(p, BRW_ALIGN_1);
elk_set_default_access_mode(p, ELK_ALIGN_1);
}
if (pc & ~pc_coord_replace) {
set_predicate_control_flag_value(p, c, pc & ~pc_coord_replace);
brw_MOV(p, c->m1Cx, brw_imm_ud(0));
brw_MOV(p, c->m2Cy, brw_imm_ud(0));
brw_MOV(p, c->m3C0, a0); /* constant value */
elk_MOV(p, c->m1Cx, elk_imm_ud(0));
elk_MOV(p, c->m2Cy, elk_imm_ud(0));
elk_MOV(p, c->m3C0, a0); /* constant value */
}
set_predicate_control_flag_value(p, c, pc);
/* Copy m0..m3 to URB. */
brw_urb_WRITE(p,
brw_null_reg(),
elk_urb_WRITE(p,
elk_null_reg(),
0,
brw_vec8_grf(0, 0),
last ? BRW_URB_WRITE_EOT_COMPLETE
: BRW_URB_WRITE_NO_FLAGS,
elk_vec8_grf(0, 0),
last ? ELK_URB_WRITE_EOT_COMPLETE
: ELK_URB_WRITE_NO_FLAGS,
4, /* msg len */
0, /* response len */
i*4, /* urb destination offset */
BRW_URB_SWIZZLE_TRANSPOSE);
ELK_URB_SWIZZLE_TRANSPOSE);
}
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
}
/* Points setup - several simplifications as all attributes are
* constant across the face of the point (point sprites excluded!)
*/
static void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate)
static void elk_emit_point_setup(struct elk_sf_compile *c, bool allocate)
{
struct brw_codegen *p = &c->func;
struct elk_codegen *p = &c->func;
GLuint i;
c->flag_value = 0xff;
@@ -706,12 +706,12 @@ static void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate)
copy_z_inv_w(c);
brw_MOV(p, c->m1Cx, brw_imm_ud(0)); /* zero - move out of loop */
brw_MOV(p, c->m2Cy, brw_imm_ud(0)); /* zero - move out of loop */
elk_MOV(p, c->m1Cx, elk_imm_ud(0)); /* zero - move out of loop */
elk_MOV(p, c->m2Cy, elk_imm_ud(0)); /* zero - move out of loop */
for (i = 0; i < c->nr_setup_regs; i++)
{
struct brw_reg a0 = offset(c->vert[0], i);
struct elk_reg a0 = offset(c->vert[0], i);
GLushort pc, pc_persp, pc_linear;
bool last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
@@ -721,7 +721,7 @@ static void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate)
* fragment shader will be expecting it:
*/
set_predicate_control_flag_value(p, c, pc_persp);
brw_MUL(p, a0, a0, c->inv_w[0]);
elk_MUL(p, a0, a0, c->inv_w[0]);
}
@@ -732,89 +732,89 @@ static void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate)
{
set_predicate_control_flag_value(p, c, pc);
brw_MOV(p, c->m3C0, a0); /* constant value */
elk_MOV(p, c->m3C0, a0); /* constant value */
/* Copy m0..m3 to URB.
*/
brw_urb_WRITE(p,
brw_null_reg(),
elk_urb_WRITE(p,
elk_null_reg(),
0,
brw_vec8_grf(0, 0),
last ? BRW_URB_WRITE_EOT_COMPLETE
: BRW_URB_WRITE_NO_FLAGS,
elk_vec8_grf(0, 0),
last ? ELK_URB_WRITE_EOT_COMPLETE
: ELK_URB_WRITE_NO_FLAGS,
4, /* msg len */
0, /* response len */
i*4, /* urb destination offset */
BRW_URB_SWIZZLE_TRANSPOSE);
ELK_URB_SWIZZLE_TRANSPOSE);
}
}
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
}
static void brw_emit_anyprim_setup( struct brw_sf_compile *c )
static void elk_emit_anyprim_setup( struct elk_sf_compile *c )
{
struct brw_codegen *p = &c->func;
struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0);
struct brw_reg payload_attr = get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0);
struct brw_reg primmask;
struct elk_codegen *p = &c->func;
struct elk_reg payload_prim = elk_uw1_reg(ELK_GENERAL_REGISTER_FILE, 1, 0);
struct elk_reg payload_attr = get_element_ud(elk_vec1_reg(ELK_GENERAL_REGISTER_FILE, 1, 0), 0);
struct elk_reg primmask;
int jmp;
struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
struct elk_reg v1_null_ud = vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD));
c->nr_verts = 3;
alloc_regs(c);
primmask = retype(get_element(c->tmp, 0), BRW_REGISTER_TYPE_UD);
primmask = retype(get_element(c->tmp, 0), ELK_REGISTER_TYPE_UD);
brw_MOV(p, primmask, brw_imm_ud(1));
brw_SHL(p, primmask, primmask, payload_prim);
elk_MOV(p, primmask, elk_imm_ud(1));
elk_SHL(p, primmask, primmask, payload_prim);
brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_TRILIST) |
elk_AND(p, v1_null_ud, primmask, elk_imm_ud((1<<_3DPRIM_TRILIST) |
(1<<_3DPRIM_TRISTRIP) |
(1<<_3DPRIM_TRIFAN) |
(1<<_3DPRIM_TRISTRIP_REVERSE) |
(1<<_3DPRIM_POLYGON) |
(1<<_3DPRIM_RECTLIST) |
(1<<_3DPRIM_TRIFAN_NOSTIPPLE)));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store;
brw_emit_tri_setup(c, false);
brw_land_fwd_jump(p, jmp);
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_Z);
jmp = elk_JMPI(p, elk_imm_d(0), ELK_PREDICATE_NORMAL) - p->store;
elk_emit_tri_setup(c, false);
elk_land_fwd_jump(p, jmp);
brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_LINELIST) |
elk_AND(p, v1_null_ud, primmask, elk_imm_ud((1<<_3DPRIM_LINELIST) |
(1<<_3DPRIM_LINESTRIP) |
(1<<_3DPRIM_LINELOOP) |
(1<<_3DPRIM_LINESTRIP_CONT) |
(1<<_3DPRIM_LINESTRIP_BF) |
(1<<_3DPRIM_LINESTRIP_CONT_BF)));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store;
brw_emit_line_setup(c, false);
brw_land_fwd_jump(p, jmp);
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_Z);
jmp = elk_JMPI(p, elk_imm_d(0), ELK_PREDICATE_NORMAL) - p->store;
elk_emit_line_setup(c, false);
elk_land_fwd_jump(p, jmp);
brw_AND(p, v1_null_ud, payload_attr, brw_imm_ud(1<<BRW_SPRITE_POINT_ENABLE));
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store;
brw_emit_point_sprite_setup(c, false);
brw_land_fwd_jump(p, jmp);
elk_AND(p, v1_null_ud, payload_attr, elk_imm_ud(1<<ELK_SPRITE_POINT_ENABLE));
elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_Z);
jmp = elk_JMPI(p, elk_imm_d(0), ELK_PREDICATE_NORMAL) - p->store;
elk_emit_point_sprite_setup(c, false);
elk_land_fwd_jump(p, jmp);
brw_emit_point_setup( c, false );
elk_emit_point_setup( c, false );
}
const unsigned *
brw_compile_sf(const struct brw_compiler *compiler,
elk_compile_sf(const struct elk_compiler *compiler,
void *mem_ctx,
const struct brw_sf_prog_key *key,
struct brw_sf_prog_data *prog_data,
const struct elk_sf_prog_key *key,
struct elk_sf_prog_data *prog_data,
struct intel_vue_map *vue_map,
unsigned *final_assembly_size)
{
struct brw_sf_compile c;
struct elk_sf_compile c;
memset(&c, 0, sizeof(c));
/* Begin the compilation:
*/
brw_init_codegen(&compiler->isa, &c.func, mem_ctx);
elk_init_codegen(&compiler->isa, &c.func, mem_ctx);
c.key = *key;
c.vue_map = *vue_map;
@@ -825,10 +825,10 @@ brw_compile_sf(const struct brw_compiler *compiler,
* it manually to let SF shader generate the needed interpolation
* coefficient for FS shader.
*/
c.vue_map.varying_to_slot[BRW_VARYING_SLOT_PNTC] = c.vue_map.num_slots;
c.vue_map.slot_to_varying[c.vue_map.num_slots++] = BRW_VARYING_SLOT_PNTC;
c.vue_map.varying_to_slot[ELK_VARYING_SLOT_PNTC] = c.vue_map.num_slots;
c.vue_map.slot_to_varying[c.vue_map.num_slots++] = ELK_VARYING_SLOT_PNTC;
}
c.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
c.urb_entry_read_offset = ELK_SF_URB_ENTRY_READ_OFFSET;
c.nr_attr_regs = (c.vue_map.num_slots + 1)/2 - c.urb_entry_read_offset;
c.nr_setup_regs = c.nr_attr_regs;
@@ -838,24 +838,24 @@ brw_compile_sf(const struct brw_compiler *compiler,
/* Which primitive? Or all three?
*/
switch (key->primitive) {
case BRW_SF_PRIM_TRIANGLES:
case ELK_SF_PRIM_TRIANGLES:
c.nr_verts = 3;
brw_emit_tri_setup( &c, true );
elk_emit_tri_setup( &c, true );
break;
case BRW_SF_PRIM_LINES:
case ELK_SF_PRIM_LINES:
c.nr_verts = 2;
brw_emit_line_setup( &c, true );
elk_emit_line_setup( &c, true );
break;
case BRW_SF_PRIM_POINTS:
case ELK_SF_PRIM_POINTS:
c.nr_verts = 1;
if (key->do_point_sprite)
brw_emit_point_sprite_setup( &c, true );
elk_emit_point_sprite_setup( &c, true );
else
brw_emit_point_setup( &c, true );
elk_emit_point_setup( &c, true );
break;
case BRW_SF_PRIM_UNFILLED_TRIS:
case ELK_SF_PRIM_UNFILLED_TRIS:
c.nr_verts = 3;
brw_emit_anyprim_setup( &c );
elk_emit_anyprim_setup( &c );
break;
default:
unreachable("not reached");
@@ -864,15 +864,15 @@ brw_compile_sf(const struct brw_compiler *compiler,
/* FINISHME: SF programs use calculated jumps (i.e., JMPI with a register
* source). Compacting would be difficult.
*/
/* brw_compact_instructions(&c.func, 0, 0, NULL); */
/* elk_compact_instructions(&c.func, 0, 0, NULL); */
*prog_data = c.prog_data;
const unsigned *program = brw_get_program(&c.func, final_assembly_size);
const unsigned *program = elk_get_program(&c.func, final_assembly_size);
if (INTEL_DEBUG(DEBUG_SF)) {
fprintf(stderr, "sf:\n");
brw_disassemble_with_labels(&compiler->isa,
elk_disassemble_with_labels(&compiler->isa,
program, 0, *final_assembly_size, stderr);
fprintf(stderr, "\n");
}
src/intel/compiler/elk/elk_compiler.c
+32 -32
View File
@@ -77,12 +77,12 @@
nir_divergence_single_patch_per_tes_subgroup | \
nir_divergence_shader_record_ptr_uniform)
const struct nir_shader_compiler_options brw_scalar_nir_options = {
const struct nir_shader_compiler_options elk_scalar_nir_options = {
COMMON_OPTIONS,
COMMON_SCALAR_OPTIONS,
};
const struct nir_shader_compiler_options brw_vector_nir_options = {
const struct nir_shader_compiler_options elk_vector_nir_options = {
COMMON_OPTIONS,
/* In the vec4 backend, our dpN instruction replicates its result to all the
@@ -102,20 +102,20 @@ const struct nir_shader_compiler_options brw_vector_nir_options = {
.max_unroll_iterations = 32,
};
struct brw_compiler *
brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
struct elk_compiler *
elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
{
assert(devinfo->ver <= 8);
struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
struct elk_compiler *compiler = rzalloc(mem_ctx, struct elk_compiler);
compiler->devinfo = devinfo;
brw_init_isa_info(&compiler->isa, devinfo);
elk_init_isa_info(&compiler->isa, devinfo);
brw_fs_alloc_reg_sets(compiler);
elk_fs_alloc_reg_sets(compiler);
if (devinfo->ver < 8)
brw_vec4_alloc_reg_set(compiler);
elk_vec4_alloc_reg_set(compiler);
compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
@@ -175,10 +175,10 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
rzalloc(compiler, struct nir_shader_compiler_options);
bool is_scalar = compiler->scalar_stage[i];
if (is_scalar) {
*nir_options = brw_scalar_nir_options;
*nir_options = elk_scalar_nir_options;
int64_options |= nir_lower_usub_sat64;
} else {
*nir_options = brw_vector_nir_options;
*nir_options = elk_vector_nir_options;
}
/* Prior to Gfx6, there are no three source operations, and Gfx11 loses
@@ -214,7 +214,7 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
nir_options->force_indirect_unrolling |=
brw_nir_no_indirect_mask(compiler, i);
elk_nir_no_indirect_mask(compiler, i);
nir_options->force_indirect_unrolling_sampler = devinfo->ver < 7;
if (compiler->use_tcs_multi_patch) {
@@ -240,7 +240,7 @@ insert_u64_bit(uint64_t *val, bool add)
}
uint64_t
brw_get_compiler_config_value(const struct brw_compiler *compiler)
elk_get_compiler_config_value(const struct elk_compiler *compiler)
{
uint64_t config = 0;
unsigned bits = 0;
@@ -271,40 +271,40 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler)
}
unsigned
brw_prog_data_size(gl_shader_stage stage)
elk_prog_data_size(gl_shader_stage stage)
{
static const size_t stage_sizes[] = {
[MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data),
[MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_data),
[MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_data),
[MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data),
[MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data),
[MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data),
[MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_data),
[MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_data),
[MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_data),
[MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_data),
[MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_data),
[MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_data),
};
assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
return stage_sizes[stage];
}
unsigned
brw_prog_key_size(gl_shader_stage stage)
elk_prog_key_size(gl_shader_stage stage)
{
static const size_t stage_sizes[] = {
[MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key),
[MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_key),
[MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_key),
[MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key),
[MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key),
[MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key),
[MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_key),
[MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_key),
[MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_key),
[MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_key),
[MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_key),
[MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_key),
};
assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
return stage_sizes[stage];
}
void
brw_write_shader_relocs(const struct brw_isa_info *isa,
elk_write_shader_relocs(const struct elk_isa_info *isa,
void *program,
const struct brw_stage_prog_data *prog_data,
struct brw_shader_reloc_value *values,
const struct elk_stage_prog_data *prog_data,
struct elk_shader_reloc_value *values,
unsigned num_values)
{
for (unsigned i = 0; i < prog_data->num_relocs; i++) {
@@ -314,11 +314,11 @@ brw_write_shader_relocs(const struct brw_isa_info *isa,
if (prog_data->relocs[i].id == values[j].id) {
uint32_t value = values[j].value + prog_data->relocs[i].delta;
switch (prog_data->relocs[i].type) {
case BRW_SHADER_RELOC_TYPE_U32:
case ELK_SHADER_RELOC_TYPE_U32:
*(uint32_t *)dst = value;
break;
case BRW_SHADER_RELOC_TYPE_MOV_IMM:
brw_update_reloc_imm(isa, dst, value);
case ELK_SHADER_RELOC_TYPE_MOV_IMM:
elk_update_reloc_imm(isa, dst, value);
break;
default:
unreachable("Invalid relocation type");
src/intel/compiler/elk/elk_compiler.h
+382 -382
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_dead_control_flow.cpp
+20 -20
View File
@@ -38,37 +38,37 @@ using namespace elk;
* - then in if/else/endif
*/
bool
dead_control_flow_eliminate(backend_shader *s)
elk_dead_control_flow_eliminate(elk_backend_shader *s)
{
bool progress = false;
foreach_block_safe (block, s->cfg) {
bblock_t *prev_block = block->prev();
elk_bblock_t *prev_block = block->prev();
if (!prev_block)
continue;
backend_instruction *const inst = block->start();
backend_instruction *const prev_inst = prev_block->end();
elk_backend_instruction *const inst = block->start();
elk_backend_instruction *const prev_inst = prev_block->end();
/* ENDIF instructions, by definition, can only be found at the start of
* basic blocks.
*/
if (inst->opcode == BRW_OPCODE_ENDIF &&
prev_inst->opcode == BRW_OPCODE_ELSE) {
bblock_t *const else_block = prev_block;
backend_instruction *const else_inst = prev_inst;
if (inst->opcode == ELK_OPCODE_ENDIF &&
prev_inst->opcode == ELK_OPCODE_ELSE) {
elk_bblock_t *const else_block = prev_block;
elk_backend_instruction *const else_inst = prev_inst;
else_inst->remove(else_block);
progress = true;
} else if (inst->opcode == BRW_OPCODE_ENDIF &&
prev_inst->opcode == BRW_OPCODE_IF) {
bblock_t *const endif_block = block;
bblock_t *const if_block = prev_block;
backend_instruction *const endif_inst = inst;
backend_instruction *const if_inst = prev_inst;
} else if (inst->opcode == ELK_OPCODE_ENDIF &&
prev_inst->opcode == ELK_OPCODE_IF) {
elk_bblock_t *const endif_block = block;
elk_bblock_t *const if_block = prev_block;
elk_backend_instruction *const endif_inst = inst;
elk_backend_instruction *const if_inst = prev_inst;
bblock_t *earlier_block = NULL, *later_block = NULL;
elk_bblock_t *earlier_block = NULL, *later_block = NULL;
if (if_block->start_ip == if_block->end_ip) {
earlier_block = if_block->prev();
@@ -98,11 +98,11 @@ dead_control_flow_eliminate(backend_shader *s)
}
progress = true;
} else if (inst->opcode == BRW_OPCODE_ELSE &&
prev_inst->opcode == BRW_OPCODE_IF) {
bblock_t *const else_block = block;
backend_instruction *const if_inst = prev_inst;
backend_instruction *const else_inst = inst;
} else if (inst->opcode == ELK_OPCODE_ELSE &&
prev_inst->opcode == ELK_OPCODE_IF) {
elk_bblock_t *const else_block = block;
elk_backend_instruction *const if_inst = prev_inst;
elk_backend_instruction *const else_inst = inst;
/* Since the else-branch is becoming the new then-branch, the
* condition has to be inverted.
src/intel/compiler/elk/elk_dead_control_flow.h
+1 -1
View File
@@ -26,6 +26,6 @@
#include "elk_shader.h"
bool dead_control_flow_eliminate(backend_shader *s);
bool elk_dead_control_flow_eliminate(elk_backend_shader *s);
#endif /* ELK_DEAD_CONTROL_FLOW_H */
src/intel/compiler/elk/elk_debug_recompile.c
+51 -51
View File
@@ -29,22 +29,22 @@
#include "elk_compiler.h"
static bool
key_debug(const struct brw_compiler *c, void *log,
key_debug(const struct elk_compiler *c, void *log,
const char *name, int a, int b)
{
if (a != b) {
brw_shader_perf_log(c, log, " %s %d->%d\n", name, a, b);
elk_shader_perf_log(c, log, " %s %d->%d\n", name, a, b);
return true;
}
return false;
}
static bool
key_debug_float(const struct brw_compiler *c, void *log,
key_debug_float(const struct elk_compiler *c, void *log,
const char *name, float a, float b)
{
if (a != b) {
brw_shader_perf_log(c, log, " %s %f->%f\n", name, a, b);
elk_shader_perf_log(c, log, " %s %f->%f\n", name, a, b);
return true;
}
return false;
@@ -56,15 +56,15 @@ key_debug_float(const struct brw_compiler *c, void *log,
key_debug_float(c, log, name, old_key->field, key->field)
static bool
debug_sampler_recompile(const struct brw_compiler *c, void *log,
const struct brw_sampler_prog_key_data *old_key,
const struct brw_sampler_prog_key_data *key)
debug_sampler_recompile(const struct elk_compiler *c, void *log,
const struct elk_sampler_prog_key_data *old_key,
const struct elk_sampler_prog_key_data *key)
{
bool found = false;
found |= check("gather channel quirk", gather_channel_quirk_mask);
for (unsigned i = 0; i < BRW_MAX_SAMPLERS; i++) {
for (unsigned i = 0; i < ELK_MAX_SAMPLERS; i++) {
found |= check("EXT_texture_swizzle or DEPTH_TEXTURE_MODE", swizzles[i]);
found |= check("textureGather workarounds", gfx6_gather_wa[i]);
}
@@ -77,17 +77,17 @@ debug_sampler_recompile(const struct brw_compiler *c, void *log,
}
static bool
debug_base_recompile(const struct brw_compiler *c, void *log,
const struct brw_base_prog_key *old_key,
const struct brw_base_prog_key *key)
debug_base_recompile(const struct elk_compiler *c, void *log,
const struct elk_base_prog_key *old_key,
const struct elk_base_prog_key *key)
{
return debug_sampler_recompile(c, log, &old_key->tex, &key->tex);
}
static void
debug_vs_recompile(const struct brw_compiler *c, void *log,
const struct brw_vs_prog_key *old_key,
const struct brw_vs_prog_key *key)
debug_vs_recompile(const struct elk_compiler *c, void *log,
const struct elk_vs_prog_key *old_key,
const struct elk_vs_prog_key *key)
{
bool found = debug_base_recompile(c, log, &old_key->base, &key->base);
@@ -101,14 +101,14 @@ debug_vs_recompile(const struct brw_compiler *c, void *log,
found |= check("vertex color clamping", clamp_vertex_color);
if (!found) {
brw_shader_perf_log(c, log, " something else\n");
elk_shader_perf_log(c, log, " something else\n");
}
}
static void
debug_tcs_recompile(const struct brw_compiler *c, void *log,
const struct brw_tcs_prog_key *old_key,
const struct brw_tcs_prog_key *key)
debug_tcs_recompile(const struct elk_compiler *c, void *log,
const struct elk_tcs_prog_key *old_key,
const struct elk_tcs_prog_key *key)
{
bool found = debug_base_recompile(c, log, &old_key->base, &key->base);
@@ -119,14 +119,14 @@ debug_tcs_recompile(const struct brw_compiler *c, void *log,
found |= check("quads and equal_spacing workaround", quads_workaround);
if (!found) {
brw_shader_perf_log(c, log, " something else\n");
elk_shader_perf_log(c, log, " something else\n");
}
}
static void
debug_tes_recompile(const struct brw_compiler *c, void *log,
const struct brw_tes_prog_key *old_key,
const struct brw_tes_prog_key *key)
debug_tes_recompile(const struct elk_compiler *c, void *log,
const struct elk_tes_prog_key *old_key,
const struct elk_tes_prog_key *key)
{
bool found = debug_base_recompile(c, log, &old_key->base, &key->base);
@@ -134,26 +134,26 @@ debug_tes_recompile(const struct brw_compiler *c, void *log,
found |= check("patch inputs read", patch_inputs_read);
if (!found) {
brw_shader_perf_log(c, log, " something else\n");
elk_shader_perf_log(c, log, " something else\n");
}
}
static void
debug_gs_recompile(const struct brw_compiler *c, void *log,
const struct brw_gs_prog_key *old_key,
const struct brw_gs_prog_key *key)
debug_gs_recompile(const struct elk_compiler *c, void *log,
const struct elk_gs_prog_key *old_key,
const struct elk_gs_prog_key *key)
{
bool found = debug_base_recompile(c, log, &old_key->base, &key->base);
if (!found) {
brw_shader_perf_log(c, log, " something else\n");
elk_shader_perf_log(c, log, " something else\n");
}
}
static void
debug_fs_recompile(const struct brw_compiler *c, void *log,
const struct brw_wm_prog_key *old_key,
const struct brw_wm_prog_key *key)
debug_fs_recompile(const struct elk_compiler *c, void *log,
const struct elk_wm_prog_key *old_key,
const struct elk_wm_prog_key *key)
{
bool found = false;
@@ -180,57 +180,57 @@ debug_fs_recompile(const struct brw_compiler *c, void *log,
found |= debug_base_recompile(c, log, &old_key->base, &key->base);
if (!found) {
brw_shader_perf_log(c, log, " something else\n");
elk_shader_perf_log(c, log, " something else\n");
}
}
static void
debug_cs_recompile(const struct brw_compiler *c, void *log,
const struct brw_cs_prog_key *old_key,
const struct brw_cs_prog_key *key)
debug_cs_recompile(const struct elk_compiler *c, void *log,
const struct elk_cs_prog_key *old_key,
const struct elk_cs_prog_key *key)
{
bool found = debug_base_recompile(c, log, &old_key->base, &key->base);
if (!found) {
brw_shader_perf_log(c, log, " something else\n");
elk_shader_perf_log(c, log, " something else\n");
}
}
void
brw_debug_key_recompile(const struct brw_compiler *c, void *log,
elk_debug_key_recompile(const struct elk_compiler *c, void *log,
gl_shader_stage stage,
const struct brw_base_prog_key *old_key,
const struct brw_base_prog_key *key)
const struct elk_base_prog_key *old_key,
const struct elk_base_prog_key *key)
{
if (!old_key) {
brw_shader_perf_log(c, log, " No previous compile found...\n");
elk_shader_perf_log(c, log, " No previous compile found...\n");
return;
}
switch (stage) {
case MESA_SHADER_VERTEX:
debug_vs_recompile(c, log, (const struct brw_vs_prog_key *)old_key,
(const struct brw_vs_prog_key *)key);
debug_vs_recompile(c, log, (const struct elk_vs_prog_key *)old_key,
(const struct elk_vs_prog_key *)key);
break;
case MESA_SHADER_TESS_CTRL:
debug_tcs_recompile(c, log, (const struct brw_tcs_prog_key *)old_key,
(const struct brw_tcs_prog_key *)key);
debug_tcs_recompile(c, log, (const struct elk_tcs_prog_key *)old_key,
(const struct elk_tcs_prog_key *)key);
break;
case MESA_SHADER_TESS_EVAL:
debug_tes_recompile(c, log, (const struct brw_tes_prog_key *)old_key,
(const struct brw_tes_prog_key *)key);
debug_tes_recompile(c, log, (const struct elk_tes_prog_key *)old_key,
(const struct elk_tes_prog_key *)key);
break;
case MESA_SHADER_GEOMETRY:
debug_gs_recompile(c, log, (const struct brw_gs_prog_key *)old_key,
(const struct brw_gs_prog_key *)key);
debug_gs_recompile(c, log, (const struct elk_gs_prog_key *)old_key,
(const struct elk_gs_prog_key *)key);
break;
case MESA_SHADER_FRAGMENT:
debug_fs_recompile(c, log, (const struct brw_wm_prog_key *)old_key,
(const struct brw_wm_prog_key *)key);
debug_fs_recompile(c, log, (const struct elk_wm_prog_key *)old_key,
(const struct elk_wm_prog_key *)key);
break;
case MESA_SHADER_COMPUTE:
debug_cs_recompile(c, log, (const struct brw_cs_prog_key *)old_key,
(const struct brw_cs_prog_key *)key);
debug_cs_recompile(c, log, (const struct elk_cs_prog_key *)old_key,
(const struct elk_cs_prog_key *)key);
break;
default:
break;
src/intel/compiler/elk/elk_disasm.c
+734 -734
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_disasm.h
+13 -13
View File
@@ -13,26 +13,26 @@
extern "C" {
#endif
struct brw_isa_info;
struct brw_inst;
struct elk_isa_info;
struct elk_inst;
const struct brw_label *brw_find_label(const struct brw_label *root, int offset);
void brw_create_label(struct brw_label **labels, int offset, void *mem_ctx);
int brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
const struct brw_inst *inst, bool is_compacted,
int offset, const struct brw_label *root_label);
const struct elk_label *elk_find_label(const struct elk_label *root, int offset);
void elk_create_label(struct elk_label **labels, int offset, void *mem_ctx);
int elk_disassemble_inst(FILE *file, const struct elk_isa_info *isa,
const struct elk_inst *inst, bool is_compacted,
int offset, const struct elk_label *root_label);
const struct
brw_label *brw_label_assembly(const struct brw_isa_info *isa,
elk_label *elk_label_assembly(const struct elk_isa_info *isa,
const void *assembly, int start, int end,
void *mem_ctx);
void brw_disassemble_with_labels(const struct brw_isa_info *isa,
void elk_disassemble_with_labels(const struct elk_isa_info *isa,
const void *assembly, int start, int end, FILE *out);
void brw_disassemble(const struct brw_isa_info *isa,
void elk_disassemble(const struct elk_isa_info *isa,
const void *assembly, int start, int end,
const struct brw_label *root_label, FILE *out);
int brw_disassemble_find_end(const struct brw_isa_info *isa,
const struct elk_label *root_label, FILE *out);
int elk_disassemble_find_end(const struct elk_isa_info *isa,
const void *assembly, int start);
void brw_disassemble_with_errors(const struct brw_isa_info *isa,
void elk_disassemble_with_errors(const struct elk_isa_info *isa,
const void *assembly, int start, FILE *out);
#ifdef __cplusplus
src/intel/compiler/elk/elk_disasm_info.c
+21 -21
View File
@@ -32,16 +32,16 @@ __attribute__((weak)) void nir_print_instr(UNUSED const nir_instr *instr,
UNUSED FILE *fp) {}
void
dump_assembly(void *assembly, int start_offset, int end_offset,
struct disasm_info *disasm, const unsigned *block_latency)
elk_dump_assembly(void *assembly, int start_offset, int end_offset,
struct elk_disasm_info *disasm, const unsigned *block_latency)
{
const struct brw_isa_info *isa = disasm->isa;
const struct elk_isa_info *isa = disasm->isa;
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
void *mem_ctx = ralloc_context(NULL);
const struct brw_label *root_label =
brw_label_assembly(isa, assembly, start_offset, end_offset, mem_ctx);
const struct elk_label *root_label =
elk_label_assembly(isa, assembly, start_offset, end_offset, mem_ctx);
foreach_list_typed(struct inst_group, group, link, &disasm->group_list) {
struct exec_node *next_node = exec_node_get_next(&group->link);
@@ -56,9 +56,9 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
if (group->block_start) {
fprintf(stderr, " START B%d", group->block_start->num);
foreach_list_typed(struct bblock_link, predecessor_link, link,
foreach_list_typed(struct elk_bblock_link, predecessor_link, link,
&group->block_start->parents) {
struct bblock_t *predecessor_block = predecessor_link->block;
struct elk_bblock_t *predecessor_block = predecessor_link->block;
fprintf(stderr, " <-B%d", predecessor_block->num);
}
if (block_latency)
@@ -82,7 +82,7 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
fprintf(stderr, " %s\n", last_annotation_string);
}
brw_disassemble(isa, assembly, start_offset, end_offset,
elk_disassemble(isa, assembly, start_offset, end_offset,
root_label, stderr);
if (group->error) {
@@ -91,9 +91,9 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
if (group->block_end) {
fprintf(stderr, " END B%d", group->block_end->num);
foreach_list_typed(struct bblock_link, successor_link, link,
foreach_list_typed(struct elk_bblock_link, successor_link, link,
&group->block_end->children) {
struct bblock_t *successor_block = successor_link->block;
struct elk_bblock_t *successor_block = successor_link->block;
fprintf(stderr, " ->B%d", successor_block->num);
}
fprintf(stderr, "\n");
@@ -104,11 +104,11 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
ralloc_free(mem_ctx);
}
struct disasm_info *
disasm_initialize(const struct brw_isa_info *isa,
const struct cfg_t *cfg)
struct elk_disasm_info *
elk_disasm_initialize(const struct elk_isa_info *isa,
const struct elk_cfg_t *cfg)
{
struct disasm_info *disasm = ralloc(NULL, struct disasm_info);
struct elk_disasm_info *disasm = ralloc(NULL, struct elk_disasm_info);
exec_list_make_empty(&disasm->group_list);
disasm->isa = isa;
disasm->cfg = cfg;
@@ -118,7 +118,7 @@ disasm_initialize(const struct brw_isa_info *isa,
}
struct inst_group *
disasm_new_inst_group(struct disasm_info *disasm, unsigned next_inst_offset)
elk_disasm_new_inst_group(struct elk_disasm_info *disasm, unsigned next_inst_offset)
{
struct inst_group *tail = rzalloc(disasm, struct inst_group);
tail->offset = next_inst_offset;
@@ -127,15 +127,15 @@ disasm_new_inst_group(struct disasm_info *disasm, unsigned next_inst_offset)
}
void
disasm_annotate(struct disasm_info *disasm,
struct backend_instruction *inst, unsigned offset)
elk_disasm_annotate(struct elk_disasm_info *disasm,
struct elk_backend_instruction *inst, unsigned offset)
{
const struct intel_device_info *devinfo = disasm->isa->devinfo;
const struct cfg_t *cfg = disasm->cfg;
const struct elk_cfg_t *cfg = disasm->cfg;
struct inst_group *group;
if (!disasm->use_tail) {
group = disasm_new_inst_group(disasm, offset);
group = elk_disasm_new_inst_group(disasm, offset);
} else {
disasm->use_tail = false;
group = exec_node_data(struct inst_group,
@@ -159,7 +159,7 @@ disasm_annotate(struct disasm_info *disasm,
* There's also only complication from emitting an annotation without
* a corresponding hardware instruction to disassemble.
*/
if (devinfo->ver >= 6 && inst->opcode == BRW_OPCODE_DO) {
if (devinfo->ver >= 6 && inst->opcode == ELK_OPCODE_DO) {
disasm->use_tail = true;
}
@@ -170,7 +170,7 @@ disasm_annotate(struct disasm_info *disasm,
}
void
disasm_insert_error(struct disasm_info *disasm, unsigned offset,
elk_disasm_insert_error(struct elk_disasm_info *disasm, unsigned offset,
unsigned inst_size, const char *error)
{
foreach_list_typed(struct inst_group, cur, link, &disasm->group_list) {
src/intel/compiler/elk/elk_disasm_info.h
+16 -16
View File
@@ -30,8 +30,8 @@
extern "C" {
#endif
struct cfg_t;
struct backend_instruction;
struct elk_cfg_t;
struct elk_backend_instruction;
struct intel_device_info;
struct inst_group {
@@ -45,19 +45,19 @@ struct inst_group {
/* Pointers to the basic block in the CFG if the instruction group starts
* or ends a basic block.
*/
struct bblock_t *block_start;
struct bblock_t *block_end;
struct elk_bblock_t *block_start;
struct elk_bblock_t *block_end;
/* Annotation for the generated IR. One of the two can be set. */
const void *ir;
const char *annotation;
};
struct disasm_info {
struct elk_disasm_info {
struct exec_list group_list;
const struct brw_isa_info *isa;
const struct cfg_t *cfg;
const struct elk_isa_info *isa;
const struct elk_cfg_t *cfg;
/** Block index in the cfg. */
int cur_block;
@@ -65,22 +65,22 @@ struct disasm_info {
};
void
dump_assembly(void *assembly, int start_offset, int end_offset,
struct disasm_info *disasm, const unsigned *block_latency);
elk_dump_assembly(void *assembly, int start_offset, int end_offset,
struct elk_disasm_info *disasm, const unsigned *block_latency);
struct disasm_info *
disasm_initialize(const struct brw_isa_info *isa,
const struct cfg_t *cfg);
struct elk_disasm_info *
elk_disasm_initialize(const struct elk_isa_info *isa,
const struct elk_cfg_t *cfg);
struct inst_group *
disasm_new_inst_group(struct disasm_info *disasm, unsigned offset);
elk_disasm_new_inst_group(struct elk_disasm_info *disasm, unsigned offset);
void
disasm_annotate(struct disasm_info *disasm,
struct backend_instruction *inst, unsigned offset);
elk_disasm_annotate(struct elk_disasm_info *disasm,
struct elk_backend_instruction *inst, unsigned offset);
void
disasm_insert_error(struct disasm_info *disasm, unsigned offset,
elk_disasm_insert_error(struct elk_disasm_info *disasm, unsigned offset,
unsigned inst_size, const char *error);
#ifdef __cplusplus
src/intel/compiler/elk/elk_disasm_tool.c
+3 -3
View File
@@ -209,8 +209,8 @@ int main(int argc, char *argv[])
exit(EXIT_FAILURE);
}
struct brw_isa_info isa;
brw_init_isa_info(&isa, &devinfo);
struct elk_isa_info isa;
elk_init_isa_info(&isa, &devinfo);
if (input_type == OPT_INPUT_BINARY)
assembly = i965_disasm_read_binary(fp, &end);
@@ -227,7 +227,7 @@ int main(int argc, char *argv[])
}
/* Disassemble i965 instructions from buffer assembly */
brw_disassemble_with_labels(&isa, assembly, start, end, stdout);
elk_disassemble_with_labels(&isa, assembly, start, end, stdout);
result = EXIT_SUCCESS;
src/intel/compiler/elk/elk_eu.c
+268 -268
View File
@@ -43,22 +43,22 @@
#include "util/ralloc.h"
/* Returns a conditional modifier that negates the condition. */
enum brw_conditional_mod
brw_negate_cmod(enum brw_conditional_mod cmod)
enum elk_conditional_mod
elk_negate_cmod(enum elk_conditional_mod cmod)
{
switch (cmod) {
case BRW_CONDITIONAL_Z:
return BRW_CONDITIONAL_NZ;
case BRW_CONDITIONAL_NZ:
return BRW_CONDITIONAL_Z;
case BRW_CONDITIONAL_G:
return BRW_CONDITIONAL_LE;
case BRW_CONDITIONAL_GE:
return BRW_CONDITIONAL_L;
case BRW_CONDITIONAL_L:
return BRW_CONDITIONAL_GE;
case BRW_CONDITIONAL_LE:
return BRW_CONDITIONAL_G;
case ELK_CONDITIONAL_Z:
return ELK_CONDITIONAL_NZ;
case ELK_CONDITIONAL_NZ:
return ELK_CONDITIONAL_Z;
case ELK_CONDITIONAL_G:
return ELK_CONDITIONAL_LE;
case ELK_CONDITIONAL_GE:
return ELK_CONDITIONAL_L;
case ELK_CONDITIONAL_L:
return ELK_CONDITIONAL_GE;
case ELK_CONDITIONAL_LE:
return ELK_CONDITIONAL_G;
default:
unreachable("Can't negate this cmod");
}
@@ -67,23 +67,23 @@ brw_negate_cmod(enum brw_conditional_mod cmod)
/* Returns the corresponding conditional mod for swapping src0 and
* src1 in e.g. CMP.
*/
enum brw_conditional_mod
brw_swap_cmod(enum brw_conditional_mod cmod)
enum elk_conditional_mod
elk_swap_cmod(enum elk_conditional_mod cmod)
{
switch (cmod) {
case BRW_CONDITIONAL_Z:
case BRW_CONDITIONAL_NZ:
case ELK_CONDITIONAL_Z:
case ELK_CONDITIONAL_NZ:
return cmod;
case BRW_CONDITIONAL_G:
return BRW_CONDITIONAL_L;
case BRW_CONDITIONAL_GE:
return BRW_CONDITIONAL_LE;
case BRW_CONDITIONAL_L:
return BRW_CONDITIONAL_G;
case BRW_CONDITIONAL_LE:
return BRW_CONDITIONAL_GE;
case ELK_CONDITIONAL_G:
return ELK_CONDITIONAL_L;
case ELK_CONDITIONAL_GE:
return ELK_CONDITIONAL_LE;
case ELK_CONDITIONAL_L:
return ELK_CONDITIONAL_G;
case ELK_CONDITIONAL_LE:
return ELK_CONDITIONAL_GE;
default:
return BRW_CONDITIONAL_NONE;
return ELK_CONDITIONAL_NONE;
}
}
@@ -94,12 +94,12 @@ brw_swap_cmod(enum brw_conditional_mod cmod)
* scalar register types return zero.
*/
static unsigned
imm_shift(enum brw_reg_type type, unsigned i)
imm_shift(enum elk_reg_type type, unsigned i)
{
assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
assert(type != ELK_REGISTER_TYPE_UV && type != ELK_REGISTER_TYPE_V &&
"Not implemented.");
if (type == BRW_REGISTER_TYPE_VF)
if (type == ELK_REGISTER_TYPE_VF)
return 8 * (i & 3);
else
return 0;
@@ -110,7 +110,7 @@ imm_shift(enum brw_reg_type type, unsigned i)
* permutation specified as \p swz.
*/
uint32_t
brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
elk_swizzle_immediate(enum elk_reg_type type, uint32_t x, unsigned swz)
{
if (imm_shift(type, 1)) {
const unsigned n = 32 / imm_shift(type, 1);
@@ -120,7 +120,7 @@ brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
/* Shift the specified component all the way to the right and left to
* discard any undesired L/MSBs, then shift it right into component i.
*/
y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3))
y |= x >> imm_shift(type, (i & ~3) + ELK_GET_SWZ(swz, i & 3))
<< imm_shift(type, ~0u)
>> imm_shift(type, ~0u - i);
}
@@ -132,72 +132,72 @@ brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
}
unsigned
brw_get_default_exec_size(struct brw_codegen *p)
elk_get_default_exec_size(struct elk_codegen *p)
{
return p->current->exec_size;
}
unsigned
brw_get_default_group(struct brw_codegen *p)
elk_get_default_group(struct elk_codegen *p)
{
return p->current->group;
}
unsigned
brw_get_default_access_mode(struct brw_codegen *p)
elk_get_default_access_mode(struct elk_codegen *p)
{
return p->current->access_mode;
}
struct tgl_swsb
brw_get_default_swsb(struct brw_codegen *p)
elk_get_default_swsb(struct elk_codegen *p)
{
return p->current->swsb;
}
void
brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
elk_set_default_exec_size(struct elk_codegen *p, unsigned value)
{
p->current->exec_size = value;
}
void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc)
void elk_set_default_predicate_control(struct elk_codegen *p, enum elk_predicate pc)
{
p->current->predicate = pc;
}
void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
void elk_set_default_predicate_inverse(struct elk_codegen *p, bool predicate_inverse)
{
p->current->pred_inv = predicate_inverse;
}
void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
void elk_set_default_flag_reg(struct elk_codegen *p, int reg, int subreg)
{
assert(subreg < 2);
p->current->flag_subreg = reg * 2 + subreg;
}
void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
void elk_set_default_access_mode( struct elk_codegen *p, unsigned access_mode )
{
p->current->access_mode = access_mode;
}
void
brw_set_default_compression_control(struct brw_codegen *p,
enum brw_compression compression_control)
elk_set_default_compression_control(struct elk_codegen *p,
enum elk_compression compression_control)
{
switch (compression_control) {
case BRW_COMPRESSION_NONE:
case ELK_COMPRESSION_NONE:
/* This is the "use the first set of bits of dmask/vmask/arf
* according to execsize" option.
*/
p->current->group = 0;
break;
case BRW_COMPRESSION_2NDHALF:
case ELK_COMPRESSION_2NDHALF:
/* For SIMD8, this is "use the second set of 8 bits." */
p->current->group = 8;
break;
case BRW_COMPRESSION_COMPRESSED:
case ELK_COMPRESSION_COMPRESSED:
/* For SIMD16 instruction compression, use the first set of 16 bits
* since we don't do SIMD32 dispatch.
*/
@@ -209,7 +209,7 @@ brw_set_default_compression_control(struct brw_codegen *p,
if (p->devinfo->ver <= 6) {
p->current->compressed =
(compression_control == BRW_COMPRESSION_COMPRESSED);
(compression_control == ELK_COMPRESSION_COMPRESSED);
}
}
@@ -218,8 +218,8 @@ brw_set_default_compression_control(struct brw_codegen *p,
* the currently selected channel enable group untouched.
*/
void
brw_inst_set_compression(const struct intel_device_info *devinfo,
brw_inst *inst, bool on)
elk_inst_set_compression(const struct intel_device_info *devinfo,
elk_inst *inst, bool on)
{
if (devinfo->ver >= 6) {
/* No-op, the EU will figure out for us whether the instruction needs to
@@ -232,15 +232,15 @@ brw_inst_set_compression(const struct intel_device_info *devinfo,
* channel group inadvertently.
*/
if (on)
brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED);
else if (brw_inst_qtr_control(devinfo, inst)
== BRW_COMPRESSION_COMPRESSED)
brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_COMPRESSED);
else if (elk_inst_qtr_control(devinfo, inst)
== ELK_COMPRESSION_COMPRESSED)
elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_NONE);
}
}
void
brw_set_default_compression(struct brw_codegen *p, bool on)
elk_set_default_compression(struct elk_codegen *p, bool on)
{
p->current->compressed = on;
}
@@ -250,21 +250,21 @@ brw_set_default_compression(struct brw_codegen *p, bool on)
* [group, group + exec_size) to the instruction passed as argument.
*/
void
brw_inst_set_group(const struct intel_device_info *devinfo,
brw_inst *inst, unsigned group)
elk_inst_set_group(const struct intel_device_info *devinfo,
elk_inst *inst, unsigned group)
{
if (devinfo->ver >= 20) {
assert(group % 8 == 0 && group < 32);
brw_inst_set_qtr_control(devinfo, inst, group / 8);
elk_inst_set_qtr_control(devinfo, inst, group / 8);
} else if (devinfo->ver >= 7) {
assert(group % 4 == 0 && group < 32);
brw_inst_set_qtr_control(devinfo, inst, group / 8);
brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
elk_inst_set_qtr_control(devinfo, inst, group / 8);
elk_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
} else if (devinfo->ver == 6) {
assert(group % 8 == 0 && group < 32);
brw_inst_set_qtr_control(devinfo, inst, group / 8);
elk_inst_set_qtr_control(devinfo, inst, group / 8);
} else {
assert(group % 8 == 0 && group < 16);
@@ -274,46 +274,46 @@ brw_inst_set_group(const struct intel_device_info *devinfo,
* enable inadvertently.
*/
if (group == 8)
brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF);
else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF)
brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_2NDHALF);
else if (elk_inst_qtr_control(devinfo, inst) == ELK_COMPRESSION_2NDHALF)
elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_NONE);
}
}
void
brw_set_default_group(struct brw_codegen *p, unsigned group)
elk_set_default_group(struct elk_codegen *p, unsigned group)
{
p->current->group = group;
}
void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
void elk_set_default_mask_control( struct elk_codegen *p, unsigned value )
{
p->current->mask_control = value;
}
void brw_set_default_saturate( struct brw_codegen *p, bool enable )
void elk_set_default_saturate( struct elk_codegen *p, bool enable )
{
p->current->saturate = enable;
}
void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
void elk_set_default_acc_write_control(struct elk_codegen *p, unsigned value)
{
p->current->acc_wr_control = value;
}
void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value)
void elk_set_default_swsb(struct elk_codegen *p, struct tgl_swsb value)
{
p->current->swsb = value;
}
void brw_push_insn_state( struct brw_codegen *p )
void elk_push_insn_state( struct elk_codegen *p )
{
assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
assert(p->current != &p->stack[ELK_EU_MAX_INSN_STACK-1]);
*(p->current + 1) = *p->current;
p->current++;
}
void brw_pop_insn_state( struct brw_codegen *p )
void elk_pop_insn_state( struct elk_codegen *p )
{
assert(p->current != p->stack);
p->current--;
@@ -323,8 +323,8 @@ void brw_pop_insn_state( struct brw_codegen *p )
/***********************************************************************
*/
void
brw_init_codegen(const struct brw_isa_info *isa,
struct brw_codegen *p, void *mem_ctx)
elk_init_codegen(const struct elk_isa_info *isa,
struct elk_codegen *p, void *mem_ctx)
{
memset(p, 0, sizeof(*p));
@@ -333,11 +333,11 @@ brw_init_codegen(const struct brw_isa_info *isa,
p->automatic_exec_sizes = true;
/*
* Set the initial instruction store array size to 1024, if found that
* isn't enough, then it will double the store size at brw_next_insn()
* isn't enough, then it will double the store size at elk_next_insn()
* until out of memory.
*/
p->store_size = 1024;
p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
p->store = rzalloc_array(mem_ctx, elk_inst, p->store_size);
p->nr_insn = 0;
p->current = p->stack;
memset(p->current, 0, sizeof(p->current[0]));
@@ -346,10 +346,10 @@ brw_init_codegen(const struct brw_isa_info *isa,
/* Some defaults?
*/
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
brw_set_default_saturate(p, 0);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
elk_set_default_exec_size(p, ELK_EXECUTE_8);
elk_set_default_mask_control(p, ELK_MASK_ENABLE); /* what does this do? */
elk_set_default_saturate(p, 0);
elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
/* Set up control flow stack */
p->if_stack_depth = 0;
@@ -363,15 +363,15 @@ brw_init_codegen(const struct brw_isa_info *isa,
}
const unsigned *brw_get_program( struct brw_codegen *p,
const unsigned *elk_get_program( struct elk_codegen *p,
unsigned *sz )
{
*sz = p->next_insn_offset;
return (const unsigned *)p->store;
}
const struct brw_shader_reloc *
brw_get_shader_relocs(struct brw_codegen *p, unsigned *num_relocs)
const struct elk_shader_reloc *
elk_get_shader_relocs(struct elk_codegen *p, unsigned *num_relocs)
{
*num_relocs = p->num_relocs;
return p->relocs;
@@ -379,12 +379,12 @@ brw_get_shader_relocs(struct brw_codegen *p, unsigned *num_relocs)
DEBUG_GET_ONCE_OPTION(shader_bin_dump_path, "INTEL_SHADER_BIN_DUMP_PATH", NULL);
bool brw_should_dump_shader_bin(void)
bool elk_should_dump_shader_bin(void)
{
return debug_get_option_shader_bin_dump_path() != NULL;
}
void brw_dump_shader_bin(void *assembly, int start_offset, int end_offset,
void elk_dump_shader_bin(void *assembly, int start_offset, int end_offset,
const char *identifier)
{
char *name = ralloc_asprintf(NULL, "%s/%s.bin",
@@ -421,7 +421,7 @@ void brw_dump_shader_bin(void *assembly, int start_offset, int end_offset,
close(fd);
}
bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
bool elk_try_override_assembly(struct elk_codegen *p, int start_offset,
const char *identifier)
{
const char *read_path = getenv("INTEL_SHADER_ASM_READ_PATH");
@@ -444,12 +444,12 @@ bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
return false;
}
p->nr_insn -= (p->next_insn_offset - start_offset) / sizeof(brw_inst);
p->nr_insn += sb.st_size / sizeof(brw_inst);
p->nr_insn -= (p->next_insn_offset - start_offset) / sizeof(elk_inst);
p->nr_insn += sb.st_size / sizeof(elk_inst);
p->next_insn_offset = start_offset + sb.st_size;
p->store_size = (start_offset + sb.st_size) / sizeof(brw_inst);
p->store = (brw_inst *)reralloc_size(p->mem_ctx, p->store, p->next_insn_offset);
p->store_size = (start_offset + sb.st_size) / sizeof(elk_inst);
p->store = (elk_inst *)reralloc_size(p->mem_ctx, p->store, p->next_insn_offset);
assert(p->store);
ssize_t ret = read(fd, (char *)p->store + start_offset, sb.st_size);
@@ -459,7 +459,7 @@ bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
}
ASSERTED bool valid =
brw_validate_instructions(p->isa, p->store,
elk_validate_instructions(p->isa, p->store,
start_offset, p->next_insn_offset,
NULL);
assert(valid);
@@ -467,10 +467,10 @@ bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
return true;
}
const struct brw_label *
brw_find_label(const struct brw_label *root, int offset)
const struct elk_label *
elk_find_label(const struct elk_label *root, int offset)
{
const struct brw_label *curr = root;
const struct elk_label *curr = root;
if (curr != NULL)
{
@@ -486,11 +486,11 @@ brw_find_label(const struct brw_label *root, int offset)
}
void
brw_create_label(struct brw_label **labels, int offset, void *mem_ctx)
elk_create_label(struct elk_label **labels, int offset, void *mem_ctx)
{
if (*labels != NULL) {
struct brw_label *curr = *labels;
struct brw_label *prev;
struct elk_label *curr = *labels;
struct elk_label *prev;
do {
prev = curr;
@@ -501,13 +501,13 @@ brw_create_label(struct brw_label **labels, int offset, void *mem_ctx)
curr = curr->next;
} while (curr != NULL);
curr = ralloc(mem_ctx, struct brw_label);
curr = ralloc(mem_ctx, struct elk_label);
curr->offset = offset;
curr->number = prev->number + 1;
curr->next = NULL;
prev->next = curr;
} else {
struct brw_label *root = ralloc(mem_ctx, struct brw_label);
struct elk_label *root = ralloc(mem_ctx, struct elk_label);
root->number = 0;
root->offset = offset;
root->next = NULL;
@@ -515,49 +515,49 @@ brw_create_label(struct brw_label **labels, int offset, void *mem_ctx)
}
}
const struct brw_label *
brw_label_assembly(const struct brw_isa_info *isa,
const struct elk_label *
elk_label_assembly(const struct elk_isa_info *isa,
const void *assembly, int start, int end, void *mem_ctx)
{
const struct intel_device_info *const devinfo = isa->devinfo;
struct brw_label *root_label = NULL;
struct elk_label *root_label = NULL;
int to_bytes_scale = sizeof(brw_inst) / brw_jump_scale(devinfo);
int to_bytes_scale = sizeof(elk_inst) / elk_jump_scale(devinfo);
for (int offset = start; offset < end;) {
const brw_inst *inst = (const brw_inst *) ((const char *) assembly + offset);
brw_inst uncompacted;
const elk_inst *inst = (const elk_inst *) ((const char *) assembly + offset);
elk_inst uncompacted;
bool is_compact = brw_inst_cmpt_control(devinfo, inst);
bool is_compact = elk_inst_cmpt_control(devinfo, inst);
if (is_compact) {
brw_compact_inst *compacted = (brw_compact_inst *)inst;
brw_uncompact_instruction(isa, &uncompacted, compacted);
elk_compact_inst *compacted = (elk_compact_inst *)inst;
elk_uncompact_instruction(isa, &uncompacted, compacted);
inst = &uncompacted;
}
if (brw_has_uip(devinfo, brw_inst_opcode(isa, inst))) {
if (elk_has_uip(devinfo, elk_inst_opcode(isa, inst))) {
/* Instructions that have UIP also have JIP. */
brw_create_label(&root_label,
offset + brw_inst_uip(devinfo, inst) * to_bytes_scale, mem_ctx);
brw_create_label(&root_label,
offset + brw_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx);
} else if (brw_has_jip(devinfo, brw_inst_opcode(isa, inst))) {
elk_create_label(&root_label,
offset + elk_inst_uip(devinfo, inst) * to_bytes_scale, mem_ctx);
elk_create_label(&root_label,
offset + elk_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx);
} else if (elk_has_jip(devinfo, elk_inst_opcode(isa, inst))) {
int jip;
if (devinfo->ver >= 7) {
jip = brw_inst_jip(devinfo, inst);
jip = elk_inst_jip(devinfo, inst);
} else {
jip = brw_inst_gfx6_jump_count(devinfo, inst);
jip = elk_inst_gfx6_jump_count(devinfo, inst);
}
brw_create_label(&root_label, offset + jip * to_bytes_scale, mem_ctx);
elk_create_label(&root_label, offset + jip * to_bytes_scale, mem_ctx);
}
if (is_compact) {
offset += sizeof(brw_compact_inst);
offset += sizeof(elk_compact_inst);
} else {
offset += sizeof(brw_inst);
offset += sizeof(elk_inst);
}
}
@@ -565,44 +565,44 @@ brw_label_assembly(const struct brw_isa_info *isa,
}
void
brw_disassemble_with_labels(const struct brw_isa_info *isa,
elk_disassemble_with_labels(const struct elk_isa_info *isa,
const void *assembly, int start, int end, FILE *out)
{
void *mem_ctx = ralloc_context(NULL);
const struct brw_label *root_label =
brw_label_assembly(isa, assembly, start, end, mem_ctx);
const struct elk_label *root_label =
elk_label_assembly(isa, assembly, start, end, mem_ctx);
brw_disassemble(isa, assembly, start, end, root_label, out);
elk_disassemble(isa, assembly, start, end, root_label, out);
ralloc_free(mem_ctx);
}
void
brw_disassemble(const struct brw_isa_info *isa,
elk_disassemble(const struct elk_isa_info *isa,
const void *assembly, int start, int end,
const struct brw_label *root_label, FILE *out)
const struct elk_label *root_label, FILE *out)
{
const struct intel_device_info *devinfo = isa->devinfo;
bool dump_hex = INTEL_DEBUG(DEBUG_HEX);
for (int offset = start; offset < end;) {
const brw_inst *insn = (const brw_inst *)((char *)assembly + offset);
brw_inst uncompacted;
const elk_inst *insn = (const elk_inst *)((char *)assembly + offset);
elk_inst uncompacted;
if (root_label != NULL) {
const struct brw_label *label = brw_find_label(root_label, offset);
const struct elk_label *label = elk_find_label(root_label, offset);
if (label != NULL) {
fprintf(out, "\nLABEL%d:\n", label->number);
}
}
bool compacted = brw_inst_cmpt_control(devinfo, insn);
bool compacted = elk_inst_cmpt_control(devinfo, insn);
if (0)
fprintf(out, "0x%08x: ", offset);
if (compacted) {
brw_compact_inst *compacted = (brw_compact_inst *)insn;
elk_compact_inst *compacted = (elk_compact_inst *)insn;
if (dump_hex) {
unsigned char * insn_ptr = ((unsigned char *)&insn[0]);
const unsigned int blank_spaces = 24;
@@ -619,7 +619,7 @@ brw_disassemble(const struct brw_isa_info *isa,
fprintf(out, "%*c", blank_spaces, ' ');
}
brw_uncompact_instruction(isa, &uncompacted, compacted);
elk_uncompact_instruction(isa, &uncompacted, compacted);
insn = &uncompacted;
} else {
if (dump_hex) {
@@ -634,130 +634,130 @@ brw_disassemble(const struct brw_isa_info *isa,
}
}
brw_disassemble_inst(out, isa, insn, compacted, offset, root_label);
elk_disassemble_inst(out, isa, insn, compacted, offset, root_label);
if (compacted) {
offset += sizeof(brw_compact_inst);
offset += sizeof(elk_compact_inst);
} else {
offset += sizeof(brw_inst);
offset += sizeof(elk_inst);
}
}
}
static const struct opcode_desc opcode_descs[] = {
static const struct elk_opcode_desc opcode_descs[] = {
/* IR, HW, name, nsrc, ndst, gfx_vers */
{ BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GFX_ALL },
{ BRW_OPCODE_SYNC, 1, "sync", 1, 0, GFX_GE(GFX12) },
{ BRW_OPCODE_MOV, 1, "mov", 1, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_MOV, 97, "mov", 1, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SEL, 2, "sel", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SEL, 98, "sel", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_MOVI, 3, "movi", 2, 1, GFX_GE(GFX45) & GFX_LT(GFX12) },
{ BRW_OPCODE_MOVI, 99, "movi", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_NOT, 4, "not", 1, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_NOT, 100, "not", 1, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_AND, 5, "and", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_AND, 101, "and", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_OR, 6, "or", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_OR, 102, "or", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_XOR, 7, "xor", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_XOR, 103, "xor", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SHR, 8, "shr", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SHR, 104, "shr", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SHL, 9, "shl", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SHL, 105, "shl", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_DIM, 10, "dim", 1, 1, GFX75 },
{ BRW_OPCODE_SMOV, 10, "smov", 0, 0, GFX_GE(GFX8) & GFX_LT(GFX12) },
{ BRW_OPCODE_SMOV, 106, "smov", 0, 0, GFX_GE(GFX12) },
{ BRW_OPCODE_ASR, 12, "asr", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_ASR, 108, "asr", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_ROR, 14, "ror", 2, 1, GFX11 },
{ BRW_OPCODE_ROR, 110, "ror", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_ROL, 15, "rol", 2, 1, GFX11 },
{ BRW_OPCODE_ROL, 111, "rol", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_CMP, 16, "cmp", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_CMP, 112, "cmp", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_CMPN, 17, "cmpn", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_CMPN, 113, "cmpn", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_CSEL, 18, "csel", 3, 1, GFX_GE(GFX8) & GFX_LT(GFX12) },
{ BRW_OPCODE_CSEL, 114, "csel", 3, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 },
{ BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 },
{ BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFREV, 119, "bfrev", 1, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFE, 120, "bfe", 3, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFI1, 121, "bfi1", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFI2, 122, "bfi2", 3, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_JMPI, 32, "jmpi", 0, 0, GFX_ALL },
{ BRW_OPCODE_BRD, 33, "brd", 0, 0, GFX_GE(GFX7) },
{ BRW_OPCODE_IF, 34, "if", 0, 0, GFX_ALL },
{ BRW_OPCODE_IFF, 35, "iff", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_BRC, 35, "brc", 0, 0, GFX_GE(GFX7) },
{ BRW_OPCODE_ELSE, 36, "else", 0, 0, GFX_ALL },
{ BRW_OPCODE_ENDIF, 37, "endif", 0, 0, GFX_ALL },
{ BRW_OPCODE_DO, 38, "do", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_CASE, 38, "case", 0, 0, GFX6 },
{ BRW_OPCODE_WHILE, 39, "while", 0, 0, GFX_ALL },
{ BRW_OPCODE_BREAK, 40, "break", 0, 0, GFX_ALL },
{ BRW_OPCODE_CONTINUE, 41, "cont", 0, 0, GFX_ALL },
{ BRW_OPCODE_HALT, 42, "halt", 0, 0, GFX_ALL },
{ BRW_OPCODE_CALLA, 43, "calla", 0, 0, GFX_GE(GFX75) },
{ BRW_OPCODE_MSAVE, 44, "msave", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_CALL, 44, "call", 0, 0, GFX_GE(GFX6) },
{ BRW_OPCODE_MREST, 45, "mrest", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_RET, 45, "ret", 0, 0, GFX_GE(GFX6) },
{ BRW_OPCODE_PUSH, 46, "push", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_FORK, 46, "fork", 0, 0, GFX6 },
{ BRW_OPCODE_GOTO, 46, "goto", 0, 0, GFX_GE(GFX8) },
{ BRW_OPCODE_POP, 47, "pop", 2, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_WAIT, 48, "wait", 0, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SEND, 49, "send", 1, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SENDC, 50, "sendc", 1, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SEND, 49, "send", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SENDC, 50, "sendc", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SENDS, 51, "sends", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) },
{ BRW_OPCODE_SENDSC, 52, "sendsc", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) },
{ BRW_OPCODE_MATH, 56, "math", 2, 1, GFX_GE(GFX6) },
{ BRW_OPCODE_ADD, 64, "add", 2, 1, GFX_ALL },
{ BRW_OPCODE_MUL, 65, "mul", 2, 1, GFX_ALL },
{ BRW_OPCODE_AVG, 66, "avg", 2, 1, GFX_ALL },
{ BRW_OPCODE_FRC, 67, "frc", 1, 1, GFX_ALL },
{ BRW_OPCODE_RNDU, 68, "rndu", 1, 1, GFX_ALL },
{ BRW_OPCODE_RNDD, 69, "rndd", 1, 1, GFX_ALL },
{ BRW_OPCODE_RNDE, 70, "rnde", 1, 1, GFX_ALL },
{ BRW_OPCODE_RNDZ, 71, "rndz", 1, 1, GFX_ALL },
{ BRW_OPCODE_MAC, 72, "mac", 2, 1, GFX_ALL },
{ BRW_OPCODE_MACH, 73, "mach", 2, 1, GFX_ALL },
{ BRW_OPCODE_LZD, 74, "lzd", 1, 1, GFX_ALL },
{ BRW_OPCODE_FBH, 75, "fbh", 1, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_FBL, 76, "fbl", 1, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_CBIT, 77, "cbit", 1, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_ADDC, 78, "addc", 2, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_SUBB, 79, "subb", 2, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_SAD2, 80, "sad2", 2, 1, GFX_ALL },
{ BRW_OPCODE_SADA2, 81, "sada2", 2, 1, GFX_ALL },
{ BRW_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) },
{ BRW_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_DP3, 86, "dp3", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_DP2, 87, "dp2", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_DP4A, 88, "dp4a", 3, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_LINE, 89, "line", 2, 1, GFX_LE(GFX10) },
{ BRW_OPCODE_DPAS, 89, "dpas", 3, 1, GFX_GE(GFX125) },
{ BRW_OPCODE_PLN, 90, "pln", 2, 1, GFX_GE(GFX45) & GFX_LE(GFX10) },
{ BRW_OPCODE_MAD, 91, "mad", 3, 1, GFX_GE(GFX6) },
{ BRW_OPCODE_LRP, 92, "lrp", 3, 1, GFX_GE(GFX6) & GFX_LE(GFX10) },
{ BRW_OPCODE_MADM, 93, "madm", 3, 1, GFX_GE(GFX8) },
{ BRW_OPCODE_NENOP, 125, "nenop", 0, 0, GFX45 },
{ BRW_OPCODE_NOP, 126, "nop", 0, 0, GFX_LT(GFX12) },
{ BRW_OPCODE_NOP, 96, "nop", 0, 0, GFX_GE(GFX12) }
{ ELK_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GFX_ALL },
{ ELK_OPCODE_SYNC, 1, "sync", 1, 0, GFX_GE(GFX12) },
{ ELK_OPCODE_MOV, 1, "mov", 1, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_MOV, 97, "mov", 1, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_SEL, 2, "sel", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_SEL, 98, "sel", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_MOVI, 3, "movi", 2, 1, GFX_GE(GFX45) & GFX_LT(GFX12) },
{ ELK_OPCODE_MOVI, 99, "movi", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_NOT, 4, "not", 1, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_NOT, 100, "not", 1, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_AND, 5, "and", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_AND, 101, "and", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_OR, 6, "or", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_OR, 102, "or", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_XOR, 7, "xor", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_XOR, 103, "xor", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_SHR, 8, "shr", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_SHR, 104, "shr", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_SHL, 9, "shl", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_SHL, 105, "shl", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_DIM, 10, "dim", 1, 1, GFX75 },
{ ELK_OPCODE_SMOV, 10, "smov", 0, 0, GFX_GE(GFX8) & GFX_LT(GFX12) },
{ ELK_OPCODE_SMOV, 106, "smov", 0, 0, GFX_GE(GFX12) },
{ ELK_OPCODE_ASR, 12, "asr", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_ASR, 108, "asr", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_ROR, 14, "ror", 2, 1, GFX11 },
{ ELK_OPCODE_ROR, 110, "ror", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_ROL, 15, "rol", 2, 1, GFX11 },
{ ELK_OPCODE_ROL, 111, "rol", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_CMP, 16, "cmp", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_CMP, 112, "cmp", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_CMPN, 17, "cmpn", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_CMPN, 113, "cmpn", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_CSEL, 18, "csel", 3, 1, GFX_GE(GFX8) & GFX_LT(GFX12) },
{ ELK_OPCODE_CSEL, 114, "csel", 3, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 },
{ ELK_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 },
{ ELK_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ ELK_OPCODE_BFREV, 119, "bfrev", 1, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ ELK_OPCODE_BFE, 120, "bfe", 3, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_BFI1, 25, "bfi1", 2, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ ELK_OPCODE_BFI1, 121, "bfi1", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_BFI2, 26, "bfi2", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ ELK_OPCODE_BFI2, 122, "bfi2", 3, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_JMPI, 32, "jmpi", 0, 0, GFX_ALL },
{ ELK_OPCODE_BRD, 33, "brd", 0, 0, GFX_GE(GFX7) },
{ ELK_OPCODE_IF, 34, "if", 0, 0, GFX_ALL },
{ ELK_OPCODE_IFF, 35, "iff", 0, 0, GFX_LE(GFX5) },
{ ELK_OPCODE_BRC, 35, "brc", 0, 0, GFX_GE(GFX7) },
{ ELK_OPCODE_ELSE, 36, "else", 0, 0, GFX_ALL },
{ ELK_OPCODE_ENDIF, 37, "endif", 0, 0, GFX_ALL },
{ ELK_OPCODE_DO, 38, "do", 0, 0, GFX_LE(GFX5) },
{ ELK_OPCODE_CASE, 38, "case", 0, 0, GFX6 },
{ ELK_OPCODE_WHILE, 39, "while", 0, 0, GFX_ALL },
{ ELK_OPCODE_BREAK, 40, "break", 0, 0, GFX_ALL },
{ ELK_OPCODE_CONTINUE, 41, "cont", 0, 0, GFX_ALL },
{ ELK_OPCODE_HALT, 42, "halt", 0, 0, GFX_ALL },
{ ELK_OPCODE_CALLA, 43, "calla", 0, 0, GFX_GE(GFX75) },
{ ELK_OPCODE_MSAVE, 44, "msave", 0, 0, GFX_LE(GFX5) },
{ ELK_OPCODE_CALL, 44, "call", 0, 0, GFX_GE(GFX6) },
{ ELK_OPCODE_MREST, 45, "mrest", 0, 0, GFX_LE(GFX5) },
{ ELK_OPCODE_RET, 45, "ret", 0, 0, GFX_GE(GFX6) },
{ ELK_OPCODE_PUSH, 46, "push", 0, 0, GFX_LE(GFX5) },
{ ELK_OPCODE_FORK, 46, "fork", 0, 0, GFX6 },
{ ELK_OPCODE_GOTO, 46, "goto", 0, 0, GFX_GE(GFX8) },
{ ELK_OPCODE_POP, 47, "pop", 2, 0, GFX_LE(GFX5) },
{ ELK_OPCODE_WAIT, 48, "wait", 0, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_SEND, 49, "send", 1, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_SENDC, 50, "sendc", 1, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_SEND, 49, "send", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_SENDC, 50, "sendc", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_SENDS, 51, "sends", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) },
{ ELK_OPCODE_SENDSC, 52, "sendsc", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) },
{ ELK_OPCODE_MATH, 56, "math", 2, 1, GFX_GE(GFX6) },
{ ELK_OPCODE_ADD, 64, "add", 2, 1, GFX_ALL },
{ ELK_OPCODE_MUL, 65, "mul", 2, 1, GFX_ALL },
{ ELK_OPCODE_AVG, 66, "avg", 2, 1, GFX_ALL },
{ ELK_OPCODE_FRC, 67, "frc", 1, 1, GFX_ALL },
{ ELK_OPCODE_RNDU, 68, "rndu", 1, 1, GFX_ALL },
{ ELK_OPCODE_RNDD, 69, "rndd", 1, 1, GFX_ALL },
{ ELK_OPCODE_RNDE, 70, "rnde", 1, 1, GFX_ALL },
{ ELK_OPCODE_RNDZ, 71, "rndz", 1, 1, GFX_ALL },
{ ELK_OPCODE_MAC, 72, "mac", 2, 1, GFX_ALL },
{ ELK_OPCODE_MACH, 73, "mach", 2, 1, GFX_ALL },
{ ELK_OPCODE_LZD, 74, "lzd", 1, 1, GFX_ALL },
{ ELK_OPCODE_FBH, 75, "fbh", 1, 1, GFX_GE(GFX7) },
{ ELK_OPCODE_FBL, 76, "fbl", 1, 1, GFX_GE(GFX7) },
{ ELK_OPCODE_CBIT, 77, "cbit", 1, 1, GFX_GE(GFX7) },
{ ELK_OPCODE_ADDC, 78, "addc", 2, 1, GFX_GE(GFX7) },
{ ELK_OPCODE_SUBB, 79, "subb", 2, 1, GFX_GE(GFX7) },
{ ELK_OPCODE_SAD2, 80, "sad2", 2, 1, GFX_ALL },
{ ELK_OPCODE_SADA2, 81, "sada2", 2, 1, GFX_ALL },
{ ELK_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) },
{ ELK_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) },
{ ELK_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) },
{ ELK_OPCODE_DP3, 86, "dp3", 2, 1, GFX_LT(GFX11) },
{ ELK_OPCODE_DP2, 87, "dp2", 2, 1, GFX_LT(GFX11) },
{ ELK_OPCODE_DP4A, 88, "dp4a", 3, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_LINE, 89, "line", 2, 1, GFX_LE(GFX10) },
{ ELK_OPCODE_DPAS, 89, "dpas", 3, 1, GFX_GE(GFX125) },
{ ELK_OPCODE_PLN, 90, "pln", 2, 1, GFX_GE(GFX45) & GFX_LE(GFX10) },
{ ELK_OPCODE_MAD, 91, "mad", 3, 1, GFX_GE(GFX6) },
{ ELK_OPCODE_LRP, 92, "lrp", 3, 1, GFX_GE(GFX6) & GFX_LE(GFX10) },
{ ELK_OPCODE_MADM, 93, "madm", 3, 1, GFX_GE(GFX8) },
{ ELK_OPCODE_NENOP, 125, "nenop", 0, 0, GFX45 },
{ ELK_OPCODE_NOP, 126, "nop", 0, 0, GFX_LT(GFX12) },
{ ELK_OPCODE_NOP, 96, "nop", 0, 0, GFX_GE(GFX12) }
};
void
brw_init_isa_info(struct brw_isa_info *isa,
elk_init_isa_info(struct elk_isa_info *isa,
const struct intel_device_info *devinfo)
{
isa->devinfo = devinfo;
@@ -783,8 +783,8 @@ brw_init_isa_info(struct brw_isa_info *isa,
* Return the matching opcode_desc for the specified IR opcode and hardware
* generation, or NULL if the opcode is not supported by the device.
*/
const struct opcode_desc *
brw_opcode_desc(const struct brw_isa_info *isa, enum opcode op)
const struct elk_opcode_desc *
elk_opcode_desc(const struct elk_isa_info *isa, enum elk_opcode op)
{
return op < ARRAY_SIZE(isa->ir_to_descs) ? isa->ir_to_descs[op] : NULL;
}
@@ -793,26 +793,26 @@ brw_opcode_desc(const struct brw_isa_info *isa, enum opcode op)
* Return the matching opcode_desc for the specified HW opcode and hardware
* generation, or NULL if the opcode is not supported by the device.
*/
const struct opcode_desc *
brw_opcode_desc_from_hw(const struct brw_isa_info *isa, unsigned hw)
const struct elk_opcode_desc *
elk_opcode_desc_from_hw(const struct elk_isa_info *isa, unsigned hw)
{
return hw < ARRAY_SIZE(isa->hw_to_descs) ? isa->hw_to_descs[hw] : NULL;
}
unsigned
brw_num_sources_from_inst(const struct brw_isa_info *isa,
const brw_inst *inst)
elk_num_sources_from_inst(const struct elk_isa_info *isa,
const elk_inst *inst)
{
const struct intel_device_info *devinfo = isa->devinfo;
const struct opcode_desc *desc =
brw_opcode_desc(isa, brw_inst_opcode(isa, inst));
const struct elk_opcode_desc *desc =
elk_opcode_desc(isa, elk_inst_opcode(isa, inst));
unsigned math_function;
if (brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) {
math_function = brw_inst_math_function(devinfo, inst);
if (elk_inst_opcode(isa, inst) == ELK_OPCODE_MATH) {
math_function = elk_inst_math_function(devinfo, inst);
} else if (devinfo->ver < 6 &&
brw_inst_opcode(isa, inst) == BRW_OPCODE_SEND) {
if (brw_inst_sfid(devinfo, inst) == BRW_SFID_MATH) {
elk_inst_opcode(isa, inst) == ELK_OPCODE_SEND) {
if (elk_inst_sfid(devinfo, inst) == ELK_SFID_MATH) {
/* src1 must be a descriptor (including the information to determine
* that the SEND is doing an extended math operation), but src0 can
* actually be null since it serves as the source of the implicit GRF
@@ -833,22 +833,22 @@ brw_num_sources_from_inst(const struct brw_isa_info *isa,
}
switch (math_function) {
case BRW_MATH_FUNCTION_INV:
case BRW_MATH_FUNCTION_LOG:
case BRW_MATH_FUNCTION_EXP:
case BRW_MATH_FUNCTION_SQRT:
case BRW_MATH_FUNCTION_RSQ:
case BRW_MATH_FUNCTION_SIN:
case BRW_MATH_FUNCTION_COS:
case BRW_MATH_FUNCTION_SINCOS:
case ELK_MATH_FUNCTION_INV:
case ELK_MATH_FUNCTION_LOG:
case ELK_MATH_FUNCTION_EXP:
case ELK_MATH_FUNCTION_SQRT:
case ELK_MATH_FUNCTION_RSQ:
case ELK_MATH_FUNCTION_SIN:
case ELK_MATH_FUNCTION_COS:
case ELK_MATH_FUNCTION_SINCOS:
case GFX8_MATH_FUNCTION_INVM:
case GFX8_MATH_FUNCTION_RSQRTM:
return 1;
case BRW_MATH_FUNCTION_FDIV:
case BRW_MATH_FUNCTION_POW:
case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT:
case BRW_MATH_FUNCTION_INT_DIV_REMAINDER:
case ELK_MATH_FUNCTION_FDIV:
case ELK_MATH_FUNCTION_POW:
case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT:
case ELK_MATH_FUNCTION_INT_DIV_REMAINDER:
return 2;
default:
unreachable("not reached");
src/intel/compiler/elk/elk_eu.h
+357 -357
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_eu_compact.c
+588 -588
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_eu_defines.h
+572 -572
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_eu_emit.c
+1522 -1522
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_eu_util.c
+25 -25
View File
@@ -34,23 +34,23 @@
#include "elk_eu.h"
void brw_math_invert( struct brw_codegen *p,
struct brw_reg dst,
struct brw_reg src)
void elk_math_invert( struct elk_codegen *p,
struct elk_reg dst,
struct elk_reg src)
{
gfx4_math(p,
elk_gfx4_math(p,
dst,
BRW_MATH_FUNCTION_INV,
ELK_MATH_FUNCTION_INV,
0,
src,
BRW_MATH_PRECISION_FULL);
ELK_MATH_PRECISION_FULL);
}
void brw_copy4(struct brw_codegen *p,
struct brw_reg dst,
struct brw_reg src,
void elk_copy4(struct elk_codegen *p,
struct elk_reg dst,
struct elk_reg src,
unsigned count)
{
unsigned i;
@@ -61,15 +61,15 @@ void brw_copy4(struct brw_codegen *p,
for (i = 0; i < count; i++)
{
unsigned delta = i*32;
brw_MOV(p, byte_offset(dst, delta), byte_offset(src, delta));
brw_MOV(p, byte_offset(dst, delta+16), byte_offset(src, delta+16));
elk_MOV(p, byte_offset(dst, delta), byte_offset(src, delta));
elk_MOV(p, byte_offset(dst, delta+16), byte_offset(src, delta+16));
}
}
void brw_copy8(struct brw_codegen *p,
struct brw_reg dst,
struct brw_reg src,
void elk_copy8(struct elk_codegen *p,
struct elk_reg dst,
struct elk_reg src,
unsigned count)
{
unsigned i;
@@ -80,14 +80,14 @@ void brw_copy8(struct brw_codegen *p,
for (i = 0; i < count; i++)
{
unsigned delta = i*32;
brw_MOV(p, byte_offset(dst, delta), byte_offset(src, delta));
elk_MOV(p, byte_offset(dst, delta), byte_offset(src, delta));
}
}
void brw_copy_indirect_to_indirect(struct brw_codegen *p,
struct brw_indirect dst_ptr,
struct brw_indirect src_ptr,
void elk_copy_indirect_to_indirect(struct elk_codegen *p,
struct elk_indirect dst_ptr,
struct elk_indirect src_ptr,
unsigned count)
{
unsigned i;
@@ -95,15 +95,15 @@ void brw_copy_indirect_to_indirect(struct brw_codegen *p,
for (i = 0; i < count; i++)
{
unsigned delta = i*32;
brw_MOV(p, deref_4f(dst_ptr, delta), deref_4f(src_ptr, delta));
brw_MOV(p, deref_4f(dst_ptr, delta+16), deref_4f(src_ptr, delta+16));
elk_MOV(p, deref_4f(dst_ptr, delta), deref_4f(src_ptr, delta));
elk_MOV(p, deref_4f(dst_ptr, delta+16), deref_4f(src_ptr, delta+16));
}
}
void brw_copy_from_indirect(struct brw_codegen *p,
struct brw_reg dst,
struct brw_indirect ptr,
void elk_copy_from_indirect(struct elk_codegen *p,
struct elk_reg dst,
struct elk_indirect ptr,
unsigned count)
{
unsigned i;
@@ -113,7 +113,7 @@ void brw_copy_from_indirect(struct brw_codegen *p,
for (i = 0; i < count; i++)
{
unsigned delta = i*32;
brw_MOV(p, byte_offset(dst, delta), deref_4f(ptr, delta));
brw_MOV(p, byte_offset(dst, delta+16), deref_4f(ptr, delta+16));
elk_MOV(p, byte_offset(dst, delta), deref_4f(ptr, delta));
elk_MOV(p, byte_offset(dst, delta+16), deref_4f(ptr, delta+16));
}
}
src/intel/compiler/elk/elk_eu_validate.c
+649 -649
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_fs.cpp
+1249 -1249
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_fs.h
+199 -199
View File
@@ -34,12 +34,12 @@
#include "elk_ir_performance.h"
#include "compiler/nir/nir.h"
struct bblock_t;
struct elk_bblock_t;
namespace {
struct acp_entry;
}
class fs_visitor;
class elk_fs_visitor;
namespace elk {
/**
@@ -47,7 +47,7 @@ namespace elk {
* are live at any point of the program in GRF units.
*/
struct register_pressure {
register_pressure(const fs_visitor *v);
register_pressure(const elk_fs_visitor *v);
~register_pressure();
analysis_dependency_class
@@ -59,7 +59,7 @@ namespace elk {
}
bool
validate(const fs_visitor *) const
validate(const elk_fs_visitor *) const
{
/* FINISHME */
return true;
@@ -69,7 +69,7 @@ namespace elk {
};
}
struct brw_gs_compile;
struct elk_gs_compile;
namespace elk {
class fs_builder;
@@ -84,50 +84,50 @@ struct shader_stats {
};
/** Register numbers for thread payload fields. */
struct thread_payload {
struct elk_elk_thread_payload {
/** The number of thread payload registers the hardware will supply. */
uint8_t num_regs;
virtual ~thread_payload() = default;
virtual ~elk_elk_thread_payload() = default;
protected:
thread_payload() : num_regs() {}
elk_elk_thread_payload() : num_regs() {}
};
struct vs_thread_payload : public thread_payload {
vs_thread_payload(const fs_visitor &v);
struct elk_vs_thread_payload : public elk_elk_thread_payload {
elk_vs_thread_payload(const elk_fs_visitor &v);
fs_reg urb_handles;
elk_fs_reg urb_handles;
};
struct tcs_thread_payload : public thread_payload {
tcs_thread_payload(const fs_visitor &v);
struct elk_tcs_thread_payload : public elk_elk_thread_payload {
elk_tcs_thread_payload(const elk_fs_visitor &v);
fs_reg patch_urb_output;
fs_reg primitive_id;
fs_reg icp_handle_start;
elk_fs_reg patch_urb_output;
elk_fs_reg primitive_id;
elk_fs_reg icp_handle_start;
};
struct tes_thread_payload : public thread_payload {
tes_thread_payload(const fs_visitor &v);
struct elk_tes_thread_payload : public elk_elk_thread_payload {
elk_tes_thread_payload(const elk_fs_visitor &v);
fs_reg patch_urb_input;
fs_reg primitive_id;
fs_reg coords[3];
fs_reg urb_output;
elk_fs_reg patch_urb_input;
elk_fs_reg primitive_id;
elk_fs_reg coords[3];
elk_fs_reg urb_output;
};
struct gs_thread_payload : public thread_payload {
gs_thread_payload(fs_visitor &v);
struct elk_gs_thread_payload : public elk_elk_thread_payload {
elk_gs_thread_payload(elk_fs_visitor &v);
fs_reg urb_handles;
fs_reg primitive_id;
fs_reg instance_id;
fs_reg icp_handle_start;
elk_fs_reg urb_handles;
elk_fs_reg primitive_id;
elk_fs_reg instance_id;
elk_fs_reg icp_handle_start;
};
struct fs_thread_payload : public thread_payload {
fs_thread_payload(const fs_visitor &v,
struct elk_fs_thread_payload : public elk_elk_thread_payload {
elk_fs_thread_payload(const elk_fs_visitor &v,
bool &source_depth_to_render_target,
bool &runtime_check_aads_emit);
@@ -139,65 +139,65 @@ struct fs_thread_payload : public thread_payload {
uint8_t sample_pos_reg[2];
uint8_t sample_mask_in_reg[2];
uint8_t depth_w_coef_reg;
uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
uint8_t barycentric_coord_reg[ELK_BARYCENTRIC_MODE_COUNT][2];
};
struct cs_thread_payload : public thread_payload {
cs_thread_payload(const fs_visitor &v);
struct elk_cs_thread_payload : public elk_elk_thread_payload {
elk_cs_thread_payload(const elk_fs_visitor &v);
void load_subgroup_id(const elk::fs_builder &bld, fs_reg &dest) const;
void load_subgroup_id(const elk::fs_builder &bld, elk_fs_reg &dest) const;
fs_reg local_invocation_id[3];
elk_fs_reg local_invocation_id[3];
protected:
fs_reg subgroup_id_;
elk_fs_reg subgroup_id_;
};
class fs_instruction_scheduler;
class elk_fs_instruction_scheduler;
/**
* The fragment shader front-end.
*
* Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
*/
class fs_visitor : public backend_shader
class elk_fs_visitor : public elk_backend_shader
{
public:
fs_visitor(const struct brw_compiler *compiler,
const struct brw_compile_params *params,
const brw_base_prog_key *key,
struct brw_stage_prog_data *prog_data,
elk_fs_visitor(const struct elk_compiler *compiler,
const struct elk_compile_params *params,
const elk_base_prog_key *key,
struct elk_stage_prog_data *prog_data,
const nir_shader *shader,
unsigned dispatch_width,
bool needs_register_pressure,
bool debug_enabled);
fs_visitor(const struct brw_compiler *compiler,
const struct brw_compile_params *params,
const brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data,
elk_fs_visitor(const struct elk_compiler *compiler,
const struct elk_compile_params *params,
const elk_wm_prog_key *key,
struct elk_wm_prog_data *prog_data,
const nir_shader *shader,
unsigned dispatch_width,
unsigned num_polygons,
bool needs_register_pressure,
bool debug_enabled);
fs_visitor(const struct brw_compiler *compiler,
const struct brw_compile_params *params,
struct brw_gs_compile *gs_compile,
struct brw_gs_prog_data *prog_data,
elk_fs_visitor(const struct elk_compiler *compiler,
const struct elk_compile_params *params,
struct elk_gs_compile *gs_compile,
struct elk_gs_prog_data *prog_data,
const nir_shader *shader,
bool needs_register_pressure,
bool debug_enabled);
void init();
~fs_visitor();
~elk_fs_visitor();
fs_reg vgrf(const glsl_type *const type);
void import_uniforms(fs_visitor *v);
elk_fs_reg vgrf(const glsl_type *const type);
void import_uniforms(elk_fs_visitor *v);
void VARYING_PULL_CONSTANT_LOAD(const elk::fs_builder &bld,
const fs_reg &dst,
const fs_reg &surface,
const fs_reg &surface_handle,
const fs_reg &varying_offset,
const elk_fs_reg &dst,
const elk_fs_reg &surface,
const elk_fs_reg &surface_handle,
const elk_fs_reg &varying_offset,
uint32_t const_offset,
uint8_t alignment,
unsigned components);
@@ -219,7 +219,7 @@ public:
bool fixup_nomask_control_flow();
void assign_curb_setup();
void assign_urb_setup();
void convert_attr_sources_to_hw_regs(fs_inst *inst);
void convert_attr_sources_to_hw_regs(elk_fs_inst *inst);
void assign_vs_urb_setup();
void assign_tcs_urb_setup();
void assign_tes_urb_setup();
@@ -231,7 +231,7 @@ public:
bool split_virtual_grfs();
bool compact_virtual_grfs();
void assign_constant_locations();
bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
bool get_pull_locs(const elk_fs_reg &src, unsigned *out_surf_index,
unsigned *out_pull_index);
bool lower_constant_loads();
virtual void invalidate_analysis(elk::analysis_dependency_class c);
@@ -245,7 +245,7 @@ public:
bool opt_algebraic();
bool opt_redundant_halt();
bool opt_cse();
bool opt_cse_local(const elk::fs_live_variables &live, bblock_t *block, int &ip);
bool opt_cse_local(const elk::fs_live_variables &live, elk_bblock_t *block, int &ip);
bool opt_copy_propagation();
bool opt_bank_conflicts();
@@ -257,16 +257,16 @@ public:
bool remove_duplicate_mrf_writes();
bool remove_extra_rounding_modes();
fs_instruction_scheduler *prepare_scheduler(void *mem_ctx);
void schedule_instructions_pre_ra(fs_instruction_scheduler *sched,
elk_fs_instruction_scheduler *prepare_scheduler(void *mem_ctx);
void schedule_instructions_pre_ra(elk_fs_instruction_scheduler *sched,
instruction_scheduler_mode mode);
void schedule_instructions_post_ra();
void insert_gfx4_send_dependency_workarounds();
void insert_gfx4_pre_send_dependency_workarounds(bblock_t *block,
fs_inst *inst);
void insert_gfx4_post_send_dependency_workarounds(bblock_t *block,
fs_inst *inst);
void insert_gfx4_pre_send_dependency_workarounds(elk_bblock_t *block,
elk_fs_inst *inst);
void insert_gfx4_post_send_dependency_workarounds(elk_bblock_t *block,
elk_fs_inst *inst);
void vfail(const char *msg, va_list args);
void fail(const char *msg, ...);
void limit_dispatch_width(unsigned n, const char *msg);
@@ -296,37 +296,37 @@ public:
void set_tcs_invocation_id();
void emit_alpha_test();
fs_inst *emit_single_fb_write(const elk::fs_builder &bld,
fs_reg color1, fs_reg color2,
fs_reg src0_alpha, unsigned components);
elk_fs_inst *emit_single_fb_write(const elk::fs_builder &bld,
elk_fs_reg color1, elk_fs_reg color2,
elk_fs_reg src0_alpha, unsigned components);
void do_emit_fb_writes(int nr_color_regions, bool replicate_alpha);
void emit_fb_writes();
void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
void emit_gs_control_data_bits(const fs_reg &vertex_count);
void emit_urb_writes(const elk_fs_reg &gs_vertex_count = elk_fs_reg());
void emit_gs_control_data_bits(const elk_fs_reg &vertex_count);
void emit_gs_thread_end();
bool mark_last_urb_write_with_eot();
void emit_tcs_thread_end();
void emit_urb_fence();
void emit_cs_terminate();
fs_reg interp_reg(const elk::fs_builder &bld, unsigned location,
elk_fs_reg interp_reg(const elk::fs_builder &bld, unsigned location,
unsigned channel, unsigned comp);
fs_reg per_primitive_reg(const elk::fs_builder &bld,
elk_fs_reg per_primitive_reg(const elk::fs_builder &bld,
int location, unsigned comp);
virtual void dump_instruction_to_file(const backend_instruction *inst, FILE *file) const;
virtual void dump_instruction_to_file(const elk_backend_instruction *inst, FILE *file) const;
virtual void dump_instructions_to_file(FILE *file) const;
const brw_base_prog_key *const key;
const struct brw_sampler_prog_key_data *key_tex;
const elk_base_prog_key *const key;
const struct elk_sampler_prog_key_data *key_tex;
struct brw_gs_compile *gs_compile;
struct elk_gs_compile *gs_compile;
struct brw_stage_prog_data *prog_data;
struct elk_stage_prog_data *prog_data;
brw_analysis<elk::fs_live_variables, backend_shader> live_analysis;
brw_analysis<elk::register_pressure, fs_visitor> regpressure_analysis;
brw_analysis<elk::performance, fs_visitor> performance_analysis;
elk_analysis<elk::fs_live_variables, elk_backend_shader> live_analysis;
elk_analysis<elk::register_pressure, elk_fs_visitor> regpressure_analysis;
elk_analysis<elk::performance, elk_fs_visitor> performance_analysis;
/** Number of uniform variable components visited. */
unsigned uniforms;
@@ -340,66 +340,66 @@ public:
*/
int *push_constant_loc;
fs_reg frag_depth;
fs_reg frag_stencil;
fs_reg sample_mask;
fs_reg outputs[VARYING_SLOT_MAX];
fs_reg dual_src_output;
elk_fs_reg frag_depth;
elk_fs_reg frag_stencil;
elk_fs_reg sample_mask;
elk_fs_reg outputs[VARYING_SLOT_MAX];
elk_fs_reg dual_src_output;
int first_non_payload_grf;
/** Either BRW_MAX_GRF or GFX7_MRF_HACK_START */
/** Either ELK_MAX_GRF or GFX7_MRF_HACK_START */
unsigned max_grf;
bool failed;
char *fail_msg;
thread_payload *payload_;
elk_elk_thread_payload *payload_;
thread_payload &payload() {
elk_elk_thread_payload &payload() {
return *this->payload_;
}
vs_thread_payload &vs_payload() {
elk_vs_thread_payload &vs_payload() {
assert(stage == MESA_SHADER_VERTEX);
return *static_cast<vs_thread_payload *>(this->payload_);
return *static_cast<elk_vs_thread_payload *>(this->payload_);
}
tcs_thread_payload &tcs_payload() {
elk_tcs_thread_payload &tcs_payload() {
assert(stage == MESA_SHADER_TESS_CTRL);
return *static_cast<tcs_thread_payload *>(this->payload_);
return *static_cast<elk_tcs_thread_payload *>(this->payload_);
}
tes_thread_payload &tes_payload() {
elk_tes_thread_payload &tes_payload() {
assert(stage == MESA_SHADER_TESS_EVAL);
return *static_cast<tes_thread_payload *>(this->payload_);
return *static_cast<elk_tes_thread_payload *>(this->payload_);
}
gs_thread_payload &gs_payload() {
elk_gs_thread_payload &gs_payload() {
assert(stage == MESA_SHADER_GEOMETRY);
return *static_cast<gs_thread_payload *>(this->payload_);
return *static_cast<elk_gs_thread_payload *>(this->payload_);
}
fs_thread_payload &fs_payload() {
elk_fs_thread_payload &fs_payload() {
assert(stage == MESA_SHADER_FRAGMENT);
return *static_cast<fs_thread_payload *>(this->payload_);
return *static_cast<elk_fs_thread_payload *>(this->payload_);
};
cs_thread_payload &cs_payload() {
elk_cs_thread_payload &cs_payload() {
assert(gl_shader_stage_uses_workgroup(stage));
return *static_cast<cs_thread_payload *>(this->payload_);
return *static_cast<elk_cs_thread_payload *>(this->payload_);
}
bool source_depth_to_render_target;
bool runtime_check_aads_emit;
fs_reg pixel_x;
fs_reg pixel_y;
fs_reg pixel_z;
fs_reg wpos_w;
fs_reg pixel_w;
fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
fs_reg final_gs_vertex_count;
fs_reg control_data_bits;
fs_reg invocation_id;
elk_fs_reg pixel_x;
elk_fs_reg pixel_y;
elk_fs_reg pixel_z;
elk_fs_reg wpos_w;
elk_fs_reg pixel_w;
elk_fs_reg delta_xy[ELK_BARYCENTRIC_MODE_COUNT];
elk_fs_reg final_gs_vertex_count;
elk_fs_reg control_data_bits;
elk_fs_reg invocation_id;
unsigned grf_used;
bool spilled_any_registers;
@@ -414,9 +414,9 @@ public:
struct shader_stats shader_stats;
void lower_mul_dword_inst(fs_inst *inst, bblock_t *block);
void lower_mul_qword_inst(fs_inst *inst, bblock_t *block);
void lower_mulh_inst(fs_inst *inst, bblock_t *block);
void lower_mul_dword_inst(elk_fs_inst *inst, elk_bblock_t *block);
void lower_mul_qword_inst(elk_fs_inst *inst, elk_bblock_t *block);
void lower_mulh_inst(elk_fs_inst *inst, elk_bblock_t *block);
unsigned workgroup_size() const;
@@ -432,7 +432,7 @@ public:
* limits the dispatch width to SIMD16 for fragment shaders that use discard.
*/
static inline unsigned
sample_mask_flag_subreg(const fs_visitor &s)
sample_mask_flag_subreg(const elk_fs_visitor &s)
{
assert(s.stage == MESA_SHADER_FRAGMENT);
return s.devinfo->ver >= 7 ? 2 : 1;
@@ -443,91 +443,91 @@ sample_mask_flag_subreg(const fs_visitor &s)
*
* Translates FS IR to actual i965 assembly code.
*/
class fs_generator
class elk_fs_generator
{
public:
fs_generator(const struct brw_compiler *compiler,
const struct brw_compile_params *params,
struct brw_stage_prog_data *prog_data,
elk_fs_generator(const struct elk_compiler *compiler,
const struct elk_compile_params *params,
struct elk_stage_prog_data *prog_data,
bool runtime_check_aads_emit,
gl_shader_stage stage);
~fs_generator();
~elk_fs_generator();
void enable_debug(const char *shader_name);
int generate_code(const cfg_t *cfg, int dispatch_width,
int generate_code(const elk_cfg_t *cfg, int dispatch_width,
struct shader_stats shader_stats,
const elk::performance &perf,
struct brw_compile_stats *stats,
struct elk_compile_stats *stats,
unsigned max_polygons = 0);
void add_const_data(void *data, unsigned size);
const unsigned *get_assembly();
private:
void fire_fb_write(fs_inst *inst,
struct brw_reg payload,
struct brw_reg implied_header,
void fire_fb_write(elk_fs_inst *inst,
struct elk_reg payload,
struct elk_reg implied_header,
GLuint nr);
void generate_send(fs_inst *inst,
struct brw_reg dst,
struct brw_reg desc,
struct brw_reg ex_desc,
struct brw_reg payload,
struct brw_reg payload2);
void generate_fb_write(fs_inst *inst, struct brw_reg payload);
void generate_fb_read(fs_inst *inst, struct brw_reg dst,
struct brw_reg payload);
void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
void generate_barrier(fs_inst *inst, struct brw_reg src);
bool generate_linterp(fs_inst *inst, struct brw_reg dst,
struct brw_reg *src);
void generate_tex(fs_inst *inst, struct brw_reg dst,
struct brw_reg surface_index,
struct brw_reg sampler_index);
void generate_ddx(const fs_inst *inst,
struct brw_reg dst, struct brw_reg src);
void generate_ddy(const fs_inst *inst,
struct brw_reg dst, struct brw_reg src);
void generate_scratch_write(fs_inst *inst, struct brw_reg src);
void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
void generate_scratch_read_gfx7(fs_inst *inst, struct brw_reg dst);
void generate_scratch_header(fs_inst *inst, struct brw_reg dst);
void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset);
void generate_varying_pull_constant_load_gfx4(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index);
void generate_send(elk_fs_inst *inst,
struct elk_reg dst,
struct elk_reg desc,
struct elk_reg ex_desc,
struct elk_reg payload,
struct elk_reg payload2);
void generate_fb_write(elk_fs_inst *inst, struct elk_reg payload);
void generate_fb_read(elk_fs_inst *inst, struct elk_reg dst,
struct elk_reg payload);
void generate_cs_terminate(elk_fs_inst *inst, struct elk_reg payload);
void generate_barrier(elk_fs_inst *inst, struct elk_reg src);
bool generate_linterp(elk_fs_inst *inst, struct elk_reg dst,
struct elk_reg *src);
void generate_tex(elk_fs_inst *inst, struct elk_reg dst,
struct elk_reg surface_index,
struct elk_reg sampler_index);
void generate_ddx(const elk_fs_inst *inst,
struct elk_reg dst, struct elk_reg src);
void generate_ddy(const elk_fs_inst *inst,
struct elk_reg dst, struct elk_reg src);
void generate_scratch_write(elk_fs_inst *inst, struct elk_reg src);
void generate_scratch_read(elk_fs_inst *inst, struct elk_reg dst);
void generate_scratch_read_gfx7(elk_fs_inst *inst, struct elk_reg dst);
void generate_scratch_header(elk_fs_inst *inst, struct elk_reg dst);
void generate_uniform_pull_constant_load(elk_fs_inst *inst, struct elk_reg dst,
struct elk_reg index,
struct elk_reg offset);
void generate_varying_pull_constant_load_gfx4(elk_fs_inst *inst,
struct elk_reg dst,
struct elk_reg index);
void generate_set_sample_id(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1);
void generate_set_sample_id(elk_fs_inst *inst,
struct elk_reg dst,
struct elk_reg src0,
struct elk_reg src1);
void generate_halt(fs_inst *inst);
void generate_halt(elk_fs_inst *inst);
void generate_mov_indirect(fs_inst *inst,
struct brw_reg dst,
struct brw_reg reg,
struct brw_reg indirect_byte_offset);
void generate_mov_indirect(elk_fs_inst *inst,
struct elk_reg dst,
struct elk_reg reg,
struct elk_reg indirect_byte_offset);
void generate_shuffle(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src,
struct brw_reg idx);
void generate_shuffle(elk_fs_inst *inst,
struct elk_reg dst,
struct elk_reg src,
struct elk_reg idx);
void generate_quad_swizzle(const fs_inst *inst,
struct brw_reg dst, struct brw_reg src,
void generate_quad_swizzle(const elk_fs_inst *inst,
struct elk_reg dst, struct elk_reg src,
unsigned swiz);
bool patch_halt_jumps();
const struct brw_compiler *compiler;
const struct brw_compile_params *params;
const struct elk_compiler *compiler;
const struct elk_compile_params *params;
const struct intel_device_info *devinfo;
struct brw_codegen *p;
struct brw_stage_prog_data * const prog_data;
struct elk_codegen *p;
struct elk_stage_prog_data * const prog_data;
unsigned dispatch_width; /**< 8, 16 or 32 */
@@ -540,62 +540,62 @@ private:
};
namespace elk {
fs_reg
elk_fs_reg
fetch_payload_reg(const elk::fs_builder &bld, uint8_t regs[2],
brw_reg_type type = BRW_REGISTER_TYPE_F,
elk_reg_type type = ELK_REGISTER_TYPE_F,
unsigned n = 1);
fs_reg
elk_fs_reg
fetch_barycentric_reg(const elk::fs_builder &bld, uint8_t regs[2]);
inline fs_reg
dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data)
inline elk_fs_reg
dynamic_msaa_flags(const struct elk_wm_prog_data *wm_prog_data)
{
return fs_reg(UNIFORM, wm_prog_data->msaa_flags_param,
BRW_REGISTER_TYPE_UD);
return elk_fs_reg(UNIFORM, wm_prog_data->msaa_flags_param,
ELK_REGISTER_TYPE_UD);
}
void
check_dynamic_msaa_flag(const fs_builder &bld,
const struct brw_wm_prog_data *wm_prog_data,
const struct elk_wm_prog_data *wm_prog_data,
enum intel_msaa_flags flag);
bool
lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
lower_src_modifiers(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst, unsigned i);
}
void shuffle_from_32bit_read(const elk::fs_builder &bld,
const fs_reg &dst,
const fs_reg &src,
void elk_shuffle_from_32bit_read(const elk::fs_builder &bld,
const elk_fs_reg &dst,
const elk_fs_reg &src,
uint32_t first_component,
uint32_t components);
fs_reg setup_imm_df(const elk::fs_builder &bld,
elk_fs_reg elk_setup_imm_df(const elk::fs_builder &bld,
double v);
fs_reg setup_imm_b(const elk::fs_builder &bld,
elk_fs_reg elk_setup_imm_b(const elk::fs_builder &bld,
int8_t v);
fs_reg setup_imm_ub(const elk::fs_builder &bld,
elk_fs_reg elk_setup_imm_ub(const elk::fs_builder &bld,
uint8_t v);
enum brw_barycentric_mode brw_barycentric_mode(nir_intrinsic_instr *intr);
enum elk_barycentric_mode elk_barycentric_mode(nir_intrinsic_instr *intr);
uint32_t brw_fb_write_msg_control(const fs_inst *inst,
const struct brw_wm_prog_data *prog_data);
uint32_t elk_fb_write_msg_control(const elk_fs_inst *inst,
const struct elk_wm_prog_data *prog_data);
void brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data);
void elk_compute_urb_setup_index(struct elk_wm_prog_data *wm_prog_data);
bool brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width);
bool elk_nir_lower_simd(nir_shader *nir, unsigned dispatch_width);
fs_reg brw_sample_mask_reg(const elk::fs_builder &bld);
void brw_emit_predicate_on_sample_mask(const elk::fs_builder &bld, fs_inst *inst);
elk_fs_reg elk_sample_mask_reg(const elk::fs_builder &bld);
void elk_emit_predicate_on_sample_mask(const elk::fs_builder &bld, elk_fs_inst *inst);
int brw_get_subgroup_id_param_index(const intel_device_info *devinfo,
const brw_stage_prog_data *prog_data);
int elk_get_subgroup_id_param_index(const intel_device_info *devinfo,
const elk_stage_prog_data *prog_data);
bool brw_lower_dpas(fs_visitor &v);
bool elk_lower_dpas(elk_fs_visitor &v);
void nir_to_brw(fs_visitor *s);
void nir_to_elk(elk_fs_visitor *s);
#endif /* ELK_FS_H */
src/intel/compiler/elk/elk_fs_bank_conflicts.cpp
+20 -20
View File
@@ -480,7 +480,7 @@ namespace {
* possibly incur bank conflicts.
*/
bool
is_grf(const fs_reg &r)
is_grf(const elk_fs_reg &r)
{
return r.file == VGRF || r.file == FIXED_GRF;
}
@@ -492,7 +492,7 @@ namespace {
* allocation or whether it was part of a VGRF allocation.
*/
unsigned
reg_of(const fs_reg &r)
reg_of(const elk_fs_reg &r)
{
assert(is_grf(r));
if (r.file == VGRF)
@@ -507,11 +507,11 @@ namespace {
* the program.
*/
partitioning
shader_reg_partitioning(const fs_visitor *v)
shader_reg_partitioning(const elk_fs_visitor *v)
{
partitioning p(BRW_MAX_GRF);
partitioning p(ELK_MAX_GRF);
foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) {
if (is_grf(inst->dst))
p.require_contiguous(reg_of(inst->dst), regs_written(inst));
@@ -529,7 +529,7 @@ namespace {
* original location to avoid violating hardware or software assumptions.
*/
bool *
shader_reg_constraints(const fs_visitor *v, const partitioning &p)
shader_reg_constraints(const elk_fs_visitor *v, const partitioning &p)
{
bool *constrained = new bool[p.num_atoms()]();
@@ -552,7 +552,7 @@ namespace {
if (v->devinfo->ver >= 8)
constrained[p.atom_of_reg(127)] = true;
foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) {
/* Assume that anything referenced via fixed GRFs is baked into the
* hardware's fixed-function logic and may be unsafe to move around.
* Also take into account the source GRF restrictions of EOT
@@ -572,7 +572,7 @@ namespace {
* barycentrics allow the PLN instruction to be used.
*/
if (v->devinfo->has_pln && v->devinfo->ver <= 6 &&
inst->opcode == FS_OPCODE_LINTERP)
inst->opcode == ELK_FS_OPCODE_LINTERP)
constrained[p.atom_of_reg(reg_of(inst->src[0]))] = true;
/* The location of the Gfx7 MRF hack registers is hard-coded in the
@@ -598,7 +598,7 @@ namespace {
*/
bool
is_conflict_optimized_out(const intel_device_info *devinfo,
const fs_inst *inst)
const elk_fs_inst *inst)
{
return devinfo->ver >= 9 &&
((is_grf(inst->src[0]) && (reg_of(inst->src[0]) == reg_of(inst->src[1]) ||
@@ -627,7 +627,7 @@ namespace {
* helpful than not optimizing at all.
*/
weight_vector_type *
shader_conflict_weight_matrix(const fs_visitor *v, const partitioning &p)
shader_conflict_weight_matrix(const elk_fs_visitor *v, const partitioning &p)
{
weight_vector_type *conflicts = new weight_vector_type[p.num_atoms()];
for (unsigned r = 0; r < p.num_atoms(); r++)
@@ -638,14 +638,14 @@ namespace {
*/
unsigned block_scale = 1;
foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
if (inst->opcode == BRW_OPCODE_DO) {
foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) {
if (inst->opcode == ELK_OPCODE_DO) {
block_scale *= 10;
} else if (inst->opcode == BRW_OPCODE_WHILE) {
} else if (inst->opcode == ELK_OPCODE_WHILE) {
block_scale /= 10;
} else if (inst->is_3src(v->compiler) &&
} else if (inst->elk_is_3src(v->compiler) &&
is_grf(inst->src[1]) && is_grf(inst->src[2])) {
const unsigned r = p.atom_of_reg(reg_of(inst->src[1]));
const unsigned s = p.atom_of_reg(reg_of(inst->src[2]));
@@ -892,8 +892,8 @@ namespace {
* Apply the GRF atom permutation given by \p map to register \p r and
* return the result.
*/
fs_reg
transform(const partitioning &p, const permutation &map, fs_reg r)
elk_fs_reg
transform(const partitioning &p, const permutation &map, elk_fs_reg r)
{
if (r.file == VGRF) {
const unsigned reg = reg_of(r);
@@ -907,7 +907,7 @@ namespace {
}
bool
fs_visitor::opt_bank_conflicts()
elk_fs_visitor::opt_bank_conflicts()
{
assert(grf_used || !"Must be called after register allocation");
@@ -927,7 +927,7 @@ fs_visitor::opt_bank_conflicts()
optimize_reg_permutation(p, constrained, conflicts,
identity_reg_permutation(p));
foreach_block_and_inst(block, fs_inst, inst, cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, cfg) {
inst->dst = transform(p, map, inst->dst);
for (int i = 0; i < inst->sources; i++)
@@ -946,9 +946,9 @@ fs_visitor::opt_bank_conflicts()
* we don't know which bank each VGRF is going to end up aligned to.
*/
bool
has_bank_conflict(const struct brw_isa_info *isa, const fs_inst *inst)
elk_has_bank_conflict(const struct elk_isa_info *isa, const elk_fs_inst *inst)
{
return is_3src(isa, inst->opcode) &&
return elk_is_3src(isa, inst->opcode) &&
is_grf(inst->src[1]) && is_grf(inst->src[2]) &&
bank_of(reg_of(inst->src[1])) == bank_of(reg_of(inst->src[2])) &&
!is_conflict_optimized_out(isa->devinfo, inst);
src/intel/compiler/elk/elk_fs_builder.h
+106 -106
View File
@@ -42,19 +42,19 @@ namespace elk {
class fs_builder {
public:
/** Type used in this IR to represent a source of an instruction. */
typedef fs_reg src_reg;
typedef elk_fs_reg src_reg;
/** Type used in this IR to represent the destination of an instruction. */
typedef fs_reg dst_reg;
typedef elk_fs_reg dst_reg;
/** Type used in this IR to represent an instruction. */
typedef fs_inst instruction;
typedef elk_fs_inst instruction;
/**
* Construct an fs_builder that inserts instructions into \p shader.
* \p dispatch_width gives the native execution width of the program.
*/
fs_builder(fs_visitor *shader,
fs_builder(elk_fs_visitor *shader,
unsigned dispatch_width) :
shader(shader), block(NULL), cursor(NULL),
_dispatch_width(dispatch_width),
@@ -64,7 +64,7 @@ namespace elk {
{
}
explicit fs_builder(fs_visitor *s) : fs_builder(s, s->dispatch_width) {}
explicit fs_builder(elk_fs_visitor *s) : fs_builder(s, s->dispatch_width) {}
/**
* Construct an fs_builder that inserts instructions into \p shader
@@ -72,7 +72,7 @@ namespace elk {
* execution controls and debug annotation are initialized from the
* instruction passed as argument.
*/
fs_builder(fs_visitor *shader, bblock_t *block, fs_inst *inst) :
fs_builder(elk_fs_visitor *shader, elk_bblock_t *block, elk_fs_inst *inst) :
shader(shader), block(block), cursor(inst),
_dispatch_width(inst->exec_size),
_group(inst->group),
@@ -88,7 +88,7 @@ namespace elk {
* from this.
*/
fs_builder
at(bblock_t *block, exec_node *cursor) const
at(elk_bblock_t *block, exec_node *cursor) const
{
fs_builder bld = *this;
bld.block = block;
@@ -200,7 +200,7 @@ namespace elk {
* component in this IR).
*/
dst_reg
vgrf(enum brw_reg_type type, unsigned n = 1) const
vgrf(enum elk_reg_type type, unsigned n = 1) const
{
const unsigned unit = reg_unit(shader->devinfo);
assert(dispatch_width() <= 32);
@@ -220,13 +220,13 @@ namespace elk {
dst_reg
null_reg_f() const
{
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_F));
}
dst_reg
null_reg_df() const
{
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF));
return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_DF));
}
/**
@@ -235,7 +235,7 @@ namespace elk {
dst_reg
null_reg_d() const
{
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_D));
}
/**
@@ -244,7 +244,7 @@ namespace elk {
dst_reg
null_reg_ud() const
{
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD));
}
/**
@@ -260,7 +260,7 @@ namespace elk {
* Create and insert a nullary control instruction into the program.
*/
instruction *
emit(enum opcode opcode) const
emit(enum elk_opcode opcode) const
{
return emit(instruction(opcode, dispatch_width()));
}
@@ -269,7 +269,7 @@ namespace elk {
* Create and insert a nullary instruction into the program.
*/
instruction *
emit(enum opcode opcode, const dst_reg &dst) const
emit(enum elk_opcode opcode, const dst_reg &dst) const
{
return emit(instruction(opcode, dispatch_width(), dst));
}
@@ -278,16 +278,16 @@ namespace elk {
* Create and insert a unary instruction into the program.
*/
instruction *
emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const
emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0) const
{
switch (opcode) {
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_SQRT:
case SHADER_OPCODE_EXP2:
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
case ELK_SHADER_OPCODE_RCP:
case ELK_SHADER_OPCODE_RSQ:
case ELK_SHADER_OPCODE_SQRT:
case ELK_SHADER_OPCODE_EXP2:
case ELK_SHADER_OPCODE_LOG2:
case ELK_SHADER_OPCODE_SIN:
case ELK_SHADER_OPCODE_COS:
return emit(instruction(opcode, dispatch_width(), dst,
fix_math_operand(src0)));
@@ -300,13 +300,13 @@ namespace elk {
* Create and insert a binary instruction into the program.
*/
instruction *
emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0,
const src_reg &src1) const
{
switch (opcode) {
case SHADER_OPCODE_POW:
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
case ELK_SHADER_OPCODE_POW:
case ELK_SHADER_OPCODE_INT_QUOTIENT:
case ELK_SHADER_OPCODE_INT_REMAINDER:
return emit(instruction(opcode, dispatch_width(), dst,
fix_math_operand(src0),
fix_math_operand(src1)));
@@ -322,14 +322,14 @@ namespace elk {
* Create and insert a ternary instruction into the program.
*/
instruction *
emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0,
const src_reg &src1, const src_reg &src2) const
{
switch (opcode) {
case BRW_OPCODE_BFE:
case BRW_OPCODE_BFI2:
case BRW_OPCODE_MAD:
case BRW_OPCODE_LRP:
case ELK_OPCODE_BFE:
case ELK_OPCODE_BFI2:
case ELK_OPCODE_MAD:
case ELK_OPCODE_LRP:
return emit(instruction(opcode, dispatch_width(), dst,
fix_3src_operand(src0),
fix_3src_operand(src1),
@@ -346,7 +346,7 @@ namespace elk {
* into the program.
*/
instruction *
emit(enum opcode opcode, const dst_reg &dst, const src_reg srcs[],
emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg srcs[],
unsigned n) const
{
/* Use the emit() methods for specific operand counts to ensure that
@@ -392,9 +392,9 @@ namespace elk {
*/
instruction *
emit_minmax(const dst_reg &dst, const src_reg &src0,
const src_reg &src1, brw_conditional_mod mod) const
const src_reg &src1, elk_conditional_mod mod) const
{
assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L);
assert(mod == ELK_CONDITIONAL_GE || mod == ELK_CONDITIONAL_L);
/* In some cases we can't have bytes as operand for src1, so use the
* same type for both operand.
@@ -417,11 +417,11 @@ namespace elk {
* should go back to scalar destinations here.
*/
const fs_builder ubld = exec_all();
const dst_reg chan_index = vgrf(BRW_REGISTER_TYPE_UD);
const dst_reg chan_index = vgrf(ELK_REGISTER_TYPE_UD);
const dst_reg dst = vgrf(src.type);
ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0));
ubld.emit(ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
ubld.emit(ELK_SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0));
return src_reg(component(dst, 0));
}
@@ -442,7 +442,7 @@ namespace elk {
}
void
emit_scan_step(enum opcode opcode, brw_conditional_mod mod,
emit_scan_step(enum elk_opcode opcode, elk_conditional_mod mod,
const dst_reg &tmp,
unsigned left_offset, unsigned left_stride,
unsigned right_offset, unsigned right_stride) const
@@ -450,31 +450,31 @@ namespace elk {
dst_reg left, right;
left = horiz_stride(horiz_offset(tmp, left_offset), left_stride);
right = horiz_stride(horiz_offset(tmp, right_offset), right_stride);
if ((tmp.type == BRW_REGISTER_TYPE_Q ||
tmp.type == BRW_REGISTER_TYPE_UQ) &&
if ((tmp.type == ELK_REGISTER_TYPE_Q ||
tmp.type == ELK_REGISTER_TYPE_UQ) &&
!shader->devinfo->has_64bit_int) {
switch (opcode) {
case BRW_OPCODE_MUL:
case ELK_OPCODE_MUL:
/* This will get lowered by integer MUL lowering */
set_condmod(mod, emit(opcode, right, left, right));
break;
case BRW_OPCODE_SEL: {
case ELK_OPCODE_SEL: {
/* In order for the comparisons to work out right, we need our
* comparisons to be strict.
*/
assert(mod == BRW_CONDITIONAL_L || mod == BRW_CONDITIONAL_GE);
if (mod == BRW_CONDITIONAL_GE)
mod = BRW_CONDITIONAL_G;
assert(mod == ELK_CONDITIONAL_L || mod == ELK_CONDITIONAL_GE);
if (mod == ELK_CONDITIONAL_GE)
mod = ELK_CONDITIONAL_G;
/* We treat the bottom 32 bits as unsigned regardless of
* whether or not the integer as a whole is signed.
*/
dst_reg right_low = subscript(right, BRW_REGISTER_TYPE_UD, 0);
dst_reg left_low = subscript(left, BRW_REGISTER_TYPE_UD, 0);
dst_reg right_low = subscript(right, ELK_REGISTER_TYPE_UD, 0);
dst_reg left_low = subscript(left, ELK_REGISTER_TYPE_UD, 0);
/* The upper bits get the same sign as the 64-bit type */
brw_reg_type type32 = brw_reg_type_from_bit_size(32, tmp.type);
elk_reg_type type32 = elk_reg_type_from_bit_size(32, tmp.type);
dst_reg right_high = subscript(right, type32, 1);
dst_reg left_high = subscript(left, type32, 1);
@@ -482,20 +482,20 @@ namespace elk {
*
* l_hi < r_hi || (l_hi == r_hi && l_low < r_low)
*/
CMP(null_reg_ud(), retype(left_low, BRW_REGISTER_TYPE_UD),
retype(right_low, BRW_REGISTER_TYPE_UD), mod);
set_predicate(BRW_PREDICATE_NORMAL,
CMP(null_reg_ud(), retype(left_low, ELK_REGISTER_TYPE_UD),
retype(right_low, ELK_REGISTER_TYPE_UD), mod);
set_predicate(ELK_PREDICATE_NORMAL,
CMP(null_reg_ud(), left_high, right_high,
BRW_CONDITIONAL_EQ));
set_predicate_inv(BRW_PREDICATE_NORMAL, true,
ELK_CONDITIONAL_EQ));
set_predicate_inv(ELK_PREDICATE_NORMAL, true,
CMP(null_reg_ud(), left_high, right_high, mod));
/* We could use selects here or we could use predicated MOVs
* because the destination and second source (if it were a SEL)
* are the same.
*/
set_predicate(BRW_PREDICATE_NORMAL, MOV(right_low, left_low));
set_predicate(BRW_PREDICATE_NORMAL, MOV(right_high, left_high));
set_predicate(ELK_PREDICATE_NORMAL, MOV(right_low, left_low));
set_predicate(ELK_PREDICATE_NORMAL, MOV(right_high, left_high));
break;
}
@@ -508,8 +508,8 @@ namespace elk {
}
void
emit_scan(enum opcode opcode, const dst_reg &tmp,
unsigned cluster_size, brw_conditional_mod mod) const
emit_scan(enum elk_opcode opcode, const dst_reg &tmp,
unsigned cluster_size, elk_conditional_mod mod) const
{
assert(dispatch_width() >= 8);
@@ -574,8 +574,8 @@ namespace elk {
emit_undef_for_dst(const instruction *old_inst) const
{
assert(old_inst->dst.file == VGRF);
instruction *inst = emit(SHADER_OPCODE_UNDEF,
retype(old_inst->dst, BRW_REGISTER_TYPE_UD));
instruction *inst = emit(ELK_SHADER_OPCODE_UNDEF,
retype(old_inst->dst, ELK_REGISTER_TYPE_UD));
inst->size_written = old_inst->size_written;
return inst;
@@ -589,21 +589,21 @@ namespace elk {
instruction * \
op(const dst_reg &dst, const src_reg &src0) const \
{ \
return emit(BRW_OPCODE_##op, dst, src0); \
return emit(ELK_OPCODE_##op, dst, src0); \
}
#define ALU2(op) \
instruction * \
op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \
{ \
return emit(BRW_OPCODE_##op, dst, src0, src1); \
return emit(ELK_OPCODE_##op, dst, src0, src1); \
}
#define ALU2_ACC(op) \
instruction * \
op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \
{ \
instruction *inst = emit(BRW_OPCODE_##op, dst, src0, src1); \
instruction *inst = emit(ELK_OPCODE_##op, dst, src0, src1); \
inst->writes_accumulator = true; \
return inst; \
}
@@ -613,7 +613,7 @@ namespace elk {
op(const dst_reg &dst, const src_reg &src0, const src_reg &src1, \
const src_reg &src2) const \
{ \
return emit(BRW_OPCODE_##op, dst, src0, src1, src2); \
return emit(ELK_OPCODE_##op, dst, src0, src1, src2); \
}
ALU2(ADD)
@@ -668,30 +668,30 @@ namespace elk {
instruction *
F32TO16(const dst_reg &dst, const src_reg &src) const
{
assert(dst.type == BRW_REGISTER_TYPE_HF);
assert(src.type == BRW_REGISTER_TYPE_F);
assert(dst.type == ELK_REGISTER_TYPE_HF);
assert(src.type == ELK_REGISTER_TYPE_F);
if (shader->devinfo->ver >= 8) {
return MOV(dst, src);
} else {
assert(shader->devinfo->ver == 7);
return emit(BRW_OPCODE_F32TO16,
retype(dst, BRW_REGISTER_TYPE_W), src);
return emit(ELK_OPCODE_F32TO16,
retype(dst, ELK_REGISTER_TYPE_W), src);
}
}
instruction *
F16TO32(const dst_reg &dst, const src_reg &src) const
{
assert(dst.type == BRW_REGISTER_TYPE_F);
assert(src.type == BRW_REGISTER_TYPE_HF);
assert(dst.type == ELK_REGISTER_TYPE_F);
assert(src.type == ELK_REGISTER_TYPE_HF);
if (shader->devinfo->ver >= 8) {
return MOV(dst, src);
} else {
assert(shader->devinfo->ver == 7);
return emit(BRW_OPCODE_F16TO32,
dst, retype(src, BRW_REGISTER_TYPE_W));
return emit(ELK_OPCODE_F16TO32,
dst, retype(src, ELK_REGISTER_TYPE_W));
}
}
/** @} */
@@ -703,7 +703,7 @@ namespace elk {
*/
instruction *
CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1,
brw_conditional_mod condition) const
elk_conditional_mod condition) const
{
/* Take the instruction:
*
@@ -718,7 +718,7 @@ namespace elk {
* instruction.
*/
return set_condmod(condition,
emit(BRW_OPCODE_CMP, retype(dst, src0.type),
emit(ELK_OPCODE_CMP, retype(dst, src0.type),
fix_unsigned_negate(src0),
fix_unsigned_negate(src1)));
}
@@ -728,7 +728,7 @@ namespace elk {
*/
instruction *
CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1,
brw_conditional_mod condition) const
elk_conditional_mod condition) const
{
/* Take the instruction:
*
@@ -743,7 +743,7 @@ namespace elk {
* instruction.
*/
return set_condmod(condition,
emit(BRW_OPCODE_CMPN, retype(dst, src0.type),
emit(ELK_OPCODE_CMPN, retype(dst, src0.type),
fix_unsigned_negate(src0),
fix_unsigned_negate(src1)));
}
@@ -752,9 +752,9 @@ namespace elk {
* Gfx4 predicated IF.
*/
instruction *
IF(brw_predicate predicate) const
IF(elk_predicate predicate) const
{
return set_predicate(predicate, emit(BRW_OPCODE_IF));
return set_predicate(predicate, emit(ELK_OPCODE_IF));
}
/**
@@ -762,19 +762,19 @@ namespace elk {
*/
instruction *
CSEL(const dst_reg &dst, const src_reg &src0, const src_reg &src1,
const src_reg &src2, brw_conditional_mod condition) const
const src_reg &src2, elk_conditional_mod condition) const
{
/* CSEL only operates on floats, so we can't do integer </<=/>=/>
* comparisons. Zero/non-zero (== and !=) comparisons almost work.
* 0x80000000 fails because it is -0.0, and -0.0 == 0.0.
*/
assert(src2.type == BRW_REGISTER_TYPE_F);
assert(src2.type == ELK_REGISTER_TYPE_F);
return set_condmod(condition,
emit(BRW_OPCODE_CSEL,
retype(dst, BRW_REGISTER_TYPE_F),
retype(src0, BRW_REGISTER_TYPE_F),
retype(src1, BRW_REGISTER_TYPE_F),
emit(ELK_OPCODE_CSEL,
retype(dst, ELK_REGISTER_TYPE_F),
retype(src0, ELK_REGISTER_TYPE_F),
retype(src1, ELK_REGISTER_TYPE_F),
src2));
}
@@ -789,7 +789,7 @@ namespace elk {
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
* we need to reorder the operands.
*/
return emit(BRW_OPCODE_LRP, dst, a, y, x);
return emit(ELK_OPCODE_LRP, dst, a, y, x);
} else {
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
@@ -798,7 +798,7 @@ namespace elk {
const dst_reg x_times_one_minus_a = vgrf(dst.type);
MUL(y_times_a, y, a);
ADD(one_minus_a, negate(a), brw_imm_f(1.0f));
ADD(one_minus_a, negate(a), elk_imm_f(1.0f));
MUL(x_times_one_minus_a, x, src_reg(one_minus_a));
return ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a));
}
@@ -811,7 +811,7 @@ namespace elk {
LOAD_PAYLOAD(const dst_reg &dst, const src_reg *src,
unsigned sources, unsigned header_size) const
{
instruction *inst = emit(SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources);
instruction *inst = emit(ELK_SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources);
inst->header_size = header_size;
inst->size_written = header_size * REG_SIZE;
for (unsigned i = header_size; i < sources; i++) {
@@ -827,8 +827,8 @@ namespace elk {
{
assert(dst.file == VGRF);
assert(dst.offset % REG_SIZE == 0);
instruction *inst = emit(SHADER_OPCODE_UNDEF,
retype(dst, BRW_REGISTER_TYPE_UD));
instruction *inst = emit(ELK_SHADER_OPCODE_UNDEF,
retype(dst, ELK_REGISTER_TYPE_UD));
inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE - dst.offset;
return inst;
@@ -842,11 +842,11 @@ namespace elk {
assert(sdepth == 8);
assert(rcount == 1 || rcount == 2 || rcount == 4 || rcount == 8);
instruction *inst = emit(BRW_OPCODE_DPAS, dst, src0, src1, src2);
instruction *inst = emit(ELK_OPCODE_DPAS, dst, src0, src1, src2);
inst->sdepth = sdepth;
inst->rcount = rcount;
if (dst.type == BRW_REGISTER_TYPE_HF) {
if (dst.type == ELK_REGISTER_TYPE_HF) {
inst->size_written = rcount * REG_SIZE / 2;
} else {
inst->size_written = rcount * REG_SIZE;
@@ -855,26 +855,26 @@ namespace elk {
return inst;
}
fs_visitor *shader;
elk_fs_visitor *shader;
fs_inst *BREAK() { return emit(BRW_OPCODE_BREAK); }
fs_inst *DO() { return emit(BRW_OPCODE_DO); }
fs_inst *ENDIF() { return emit(BRW_OPCODE_ENDIF); }
fs_inst *NOP() { return emit(BRW_OPCODE_NOP); }
fs_inst *WHILE() { return emit(BRW_OPCODE_WHILE); }
fs_inst *CONTINUE() { return emit(BRW_OPCODE_CONTINUE); }
elk_fs_inst *BREAK() { return emit(ELK_OPCODE_BREAK); }
elk_fs_inst *DO() { return emit(ELK_OPCODE_DO); }
elk_fs_inst *ENDIF() { return emit(ELK_OPCODE_ENDIF); }
elk_fs_inst *NOP() { return emit(ELK_OPCODE_NOP); }
elk_fs_inst *WHILE() { return emit(ELK_OPCODE_WHILE); }
elk_fs_inst *CONTINUE() { return emit(ELK_OPCODE_CONTINUE); }
private:
/**
* Workaround for negation of UD registers. See comment in
* fs_generator::generate_code() for more details.
* elk_fs_generator::generate_code() for more details.
*/
src_reg
fix_unsigned_negate(const src_reg &src) const
{
if (src.type == BRW_REGISTER_TYPE_UD &&
if (src.type == ELK_REGISTER_TYPE_UD &&
src.negate) {
dst_reg temp = vgrf(BRW_REGISTER_TYPE_UD);
dst_reg temp = vgrf(ELK_REGISTER_TYPE_UD);
MOV(temp, src);
return src_reg(temp);
} else {
@@ -892,9 +892,9 @@ namespace elk {
switch (src.file) {
case FIXED_GRF:
/* FINISHME: Could handle scalar region, other stride=1 regions */
if (src.vstride != BRW_VERTICAL_STRIDE_8 ||
src.width != BRW_WIDTH_8 ||
src.hstride != BRW_HORIZONTAL_STRIDE_1)
if (src.vstride != ELK_VERTICAL_STRIDE_8 ||
src.width != ELK_WIDTH_8 ||
src.hstride != ELK_HORIZONTAL_STRIDE_1)
break;
FALLTHROUGH;
case ATTR:
@@ -941,7 +941,7 @@ namespace elk {
}
}
bblock_t *block;
elk_bblock_t *block;
exec_node *cursor;
unsigned _dispatch_width;
@@ -956,8 +956,8 @@ namespace elk {
};
}
static inline fs_reg
offset(const fs_reg &reg, const elk::fs_builder &bld, unsigned delta)
static inline elk_fs_reg
offset(const elk_fs_reg &reg, const elk::fs_builder &bld, unsigned delta)
{
return offset(reg, bld.dispatch_width(), delta);
}
src/intel/compiler/elk/elk_fs_cmod_propagation.cpp
+66 -66
View File
@@ -51,14 +51,14 @@
using namespace elk;
static bool
cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block,
fs_inst *inst)
cmod_propagate_cmp_to_add(const intel_device_info *devinfo, elk_bblock_t *block,
elk_fs_inst *inst)
{
bool read_flag = false;
const unsigned flags_written = inst->flags_written(devinfo);
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
if (scan_inst->opcode == BRW_OPCODE_ADD &&
foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) {
if (scan_inst->opcode == ELK_OPCODE_ADD &&
!scan_inst->is_partial_write() &&
scan_inst->exec_size == inst->exec_size) {
bool negate;
@@ -119,20 +119,20 @@ cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block,
* (sat(x) > 0) == (x > 0) --- false
* (sat(x) <= 0) == (x <= 0) --- true
*/
const enum brw_conditional_mod cond =
negate ? brw_swap_cmod(inst->conditional_mod)
const enum elk_conditional_mod cond =
negate ? elk_swap_cmod(inst->conditional_mod)
: inst->conditional_mod;
if (scan_inst->saturate &&
(brw_reg_type_is_floating_point(scan_inst->dst.type) ||
brw_reg_type_is_unsigned_integer(scan_inst->dst.type)) &&
(cond != BRW_CONDITIONAL_G &&
cond != BRW_CONDITIONAL_LE))
(elk_reg_type_is_floating_point(scan_inst->dst.type) ||
elk_reg_type_is_unsigned_integer(scan_inst->dst.type)) &&
(cond != ELK_CONDITIONAL_G &&
cond != ELK_CONDITIONAL_LE))
goto not_match;
/* Otherwise, try propagating the conditional. */
if (scan_inst->can_do_cmod() &&
((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
((!read_flag && scan_inst->conditional_mod == ELK_CONDITIONAL_NONE) ||
scan_inst->conditional_mod == cond)) {
scan_inst->conditional_mod = cond;
scan_inst->flag_subreg = inst->flag_subreg;
@@ -167,21 +167,21 @@ cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block,
* or.z.f0(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD
*/
static bool
cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block,
fs_inst *inst)
cmod_propagate_not(const intel_device_info *devinfo, elk_bblock_t *block,
elk_fs_inst *inst)
{
const enum brw_conditional_mod cond = brw_negate_cmod(inst->conditional_mod);
const enum elk_conditional_mod cond = elk_negate_cmod(inst->conditional_mod);
bool read_flag = false;
const unsigned flags_written = inst->flags_written(devinfo);
if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ)
if (cond != ELK_CONDITIONAL_Z && cond != ELK_CONDITIONAL_NZ)
return false;
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) {
if (regions_overlap(scan_inst->dst, scan_inst->size_written,
inst->src[0], inst->size_read(0))) {
if (scan_inst->opcode != BRW_OPCODE_OR &&
scan_inst->opcode != BRW_OPCODE_AND)
if (scan_inst->opcode != ELK_OPCODE_OR &&
scan_inst->opcode != ELK_OPCODE_AND)
break;
if (scan_inst->is_partial_write() ||
@@ -201,7 +201,7 @@ cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block,
break;
if (scan_inst->can_do_cmod() &&
((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
((!read_flag && scan_inst->conditional_mod == ELK_CONDITIONAL_NONE) ||
scan_inst->conditional_mod == cond)) {
scan_inst->conditional_mod = cond;
scan_inst->flag_subreg = inst->flag_subreg;
@@ -222,19 +222,19 @@ cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block,
}
static bool
opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
opt_cmod_propagation_local(const intel_device_info *devinfo, elk_bblock_t *block)
{
bool progress = false;
UNUSED int ip = block->end_ip + 1;
foreach_inst_in_block_reverse_safe(fs_inst, inst, block) {
foreach_inst_in_block_reverse_safe(elk_fs_inst, inst, block) {
ip--;
if ((inst->opcode != BRW_OPCODE_AND &&
inst->opcode != BRW_OPCODE_CMP &&
inst->opcode != BRW_OPCODE_MOV &&
inst->opcode != BRW_OPCODE_NOT) ||
inst->predicate != BRW_PREDICATE_NONE ||
if ((inst->opcode != ELK_OPCODE_AND &&
inst->opcode != ELK_OPCODE_CMP &&
inst->opcode != ELK_OPCODE_MOV &&
inst->opcode != ELK_OPCODE_NOT) ||
inst->predicate != ELK_PREDICATE_NONE ||
!inst->dst.is_null() ||
(inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
inst->src[0].file != UNIFORM))
@@ -244,19 +244,19 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
* with a value other than zero.
*/
if (inst->src[0].abs &&
(inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero()))
(inst->opcode != ELK_OPCODE_CMP || inst->src[1].is_zero()))
continue;
/* Only an AND.NZ can be propagated. Many AND.Z instructions are
* generated (for ir_unop_not in fs_visitor::emit_bool_to_cond_code).
* generated (for ir_unop_not in elk_fs_visitor::emit_bool_to_cond_code).
* Propagating those would require inverting the condition on the CMP.
* This changes both the flag value and the register destination of the
* CMP. That result may be used elsewhere, so we can't change its value
* on a whim.
*/
if (inst->opcode == BRW_OPCODE_AND &&
if (inst->opcode == ELK_OPCODE_AND &&
!(inst->src[1].is_one() &&
inst->conditional_mod == BRW_CONDITIONAL_NZ &&
inst->conditional_mod == ELK_CONDITIONAL_NZ &&
!inst->src[0].negate))
continue;
@@ -269,22 +269,22 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
* int(0x80000000) - 4 overflows and results in 0x7ffffffc. that's not
* less than zero, so the flags get set differently than for (a < b).
*/
if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) {
if (brw_reg_type_is_floating_point(inst->src[0].type) &&
if (inst->opcode == ELK_OPCODE_CMP && !inst->src[1].is_zero()) {
if (elk_reg_type_is_floating_point(inst->src[0].type) &&
cmod_propagate_cmp_to_add(devinfo, block, inst))
progress = true;
continue;
}
if (inst->opcode == BRW_OPCODE_NOT) {
if (inst->opcode == ELK_OPCODE_NOT) {
progress = cmod_propagate_not(devinfo, block, inst) || progress;
continue;
}
bool read_flag = false;
const unsigned flags_written = inst->flags_written(devinfo);
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) {
if (regions_overlap(scan_inst->dst, scan_inst->size_written,
inst->src[0], inst->size_read(0))) {
/* If the scan instruction writes a different flag register than
@@ -308,9 +308,9 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
break;
/* CMP's result is the same regardless of dest type. */
if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
scan_inst->opcode == BRW_OPCODE_CMP &&
brw_reg_type_is_integer(inst->dst.type)) {
if (inst->conditional_mod == ELK_CONDITIONAL_NZ &&
scan_inst->opcode == ELK_OPCODE_CMP &&
elk_reg_type_is_integer(inst->dst.type)) {
inst->remove(block, true);
progress = true;
break;
@@ -319,11 +319,11 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
/* If the AND wasn't handled by the previous case, it isn't safe
* to remove it.
*/
if (inst->opcode == BRW_OPCODE_AND)
if (inst->opcode == ELK_OPCODE_AND)
break;
if (inst->opcode == BRW_OPCODE_MOV) {
if (brw_reg_type_is_floating_point(scan_inst->dst.type)) {
if (inst->opcode == ELK_OPCODE_MOV) {
if (elk_reg_type_is_floating_point(scan_inst->dst.type)) {
/* If the destination type of scan_inst is floating-point,
* then:
*
@@ -338,7 +338,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
if (scan_inst->dst.type != inst->src[0].type)
break;
if (!brw_reg_type_is_floating_point(inst->dst.type))
if (!elk_reg_type_is_floating_point(inst->dst.type))
break;
if (type_sz(scan_inst->dst.type) > type_sz(inst->dst.type))
@@ -359,18 +359,18 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
* (of any size) or integer with a size at least as large
* as the destination of inst and the same signedness.
*/
if (!brw_reg_type_is_integer(inst->src[0].type) ||
if (!elk_reg_type_is_integer(inst->src[0].type) ||
type_sz(scan_inst->dst.type) != type_sz(inst->src[0].type))
break;
if (brw_reg_type_is_integer(inst->dst.type)) {
if (elk_reg_type_is_integer(inst->dst.type)) {
if (type_sz(inst->dst.type) < type_sz(scan_inst->dst.type))
break;
if (inst->conditional_mod != BRW_CONDITIONAL_Z &&
inst->conditional_mod != BRW_CONDITIONAL_NZ &&
brw_reg_type_is_unsigned_integer(inst->dst.type) !=
brw_reg_type_is_unsigned_integer(scan_inst->dst.type))
if (inst->conditional_mod != ELK_CONDITIONAL_Z &&
inst->conditional_mod != ELK_CONDITIONAL_NZ &&
elk_reg_type_is_unsigned_integer(inst->dst.type) !=
elk_reg_type_is_unsigned_integer(scan_inst->dst.type))
break;
}
}
@@ -379,8 +379,8 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
* different.
*/
if (scan_inst->dst.type != inst->src[0].type &&
inst->conditional_mod != BRW_CONDITIONAL_Z &&
inst->conditional_mod != BRW_CONDITIONAL_NZ)
inst->conditional_mod != ELK_CONDITIONAL_Z &&
inst->conditional_mod != ELK_CONDITIONAL_NZ)
break;
/* Comparisons operate differently for ints and floats */
@@ -391,8 +391,8 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
if (type_sz(scan_inst->dst.type) != type_sz(inst->dst.type))
break;
if (brw_reg_type_is_floating_point(scan_inst->dst.type) !=
brw_reg_type_is_floating_point(inst->dst.type))
if (elk_reg_type_is_floating_point(scan_inst->dst.type) !=
elk_reg_type_is_floating_point(inst->dst.type))
break;
}
}
@@ -440,12 +440,12 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
*/
if (!inst->src[0].negate &&
scan_inst->flags_written(devinfo)) {
if (scan_inst->opcode == BRW_OPCODE_CMP) {
if ((inst->conditional_mod == BRW_CONDITIONAL_NZ) ||
(inst->conditional_mod == BRW_CONDITIONAL_G &&
inst->src[0].type == BRW_REGISTER_TYPE_UD) ||
(inst->conditional_mod == BRW_CONDITIONAL_L &&
inst->src[0].type == BRW_REGISTER_TYPE_D)) {
if (scan_inst->opcode == ELK_OPCODE_CMP) {
if ((inst->conditional_mod == ELK_CONDITIONAL_NZ) ||
(inst->conditional_mod == ELK_CONDITIONAL_G &&
inst->src[0].type == ELK_REGISTER_TYPE_UD) ||
(inst->conditional_mod == ELK_CONDITIONAL_L &&
inst->src[0].type == ELK_REGISTER_TYPE_D)) {
inst->remove(block, true);
progress = true;
break;
@@ -456,7 +456,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
* destination. On all other platforms sel.cond will not
* write the flags, so execution will not get to this point.
*/
if (scan_inst->opcode == BRW_OPCODE_SEL) {
if (scan_inst->opcode == ELK_OPCODE_SEL) {
assert(devinfo->ver <= 5);
} else {
inst->remove(block, true);
@@ -481,8 +481,8 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
* different results because they are evaluated based on different
* inputs.
*/
if (scan_inst->opcode == BRW_OPCODE_CMP ||
scan_inst->opcode == BRW_OPCODE_CMPN)
if (scan_inst->opcode == ELK_OPCODE_CMP ||
scan_inst->opcode == ELK_OPCODE_CMPN)
break;
/* From the Sky Lake PRM, Vol 2a, "Multiply":
@@ -498,12 +498,12 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
*
* We just disallow cmod propagation on all integer multiplies.
*/
if (!brw_reg_type_is_floating_point(scan_inst->dst.type) &&
scan_inst->opcode == BRW_OPCODE_MUL)
if (!elk_reg_type_is_floating_point(scan_inst->dst.type) &&
scan_inst->opcode == ELK_OPCODE_MUL)
break;
enum brw_conditional_mod cond =
inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod)
enum elk_conditional_mod cond =
inst->src[0].negate ? elk_swap_cmod(inst->conditional_mod)
: inst->conditional_mod;
/* From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags":
@@ -525,7 +525,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
/* Otherwise, try propagating the conditional. */
if (scan_inst->can_do_cmod() &&
((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
((!read_flag && scan_inst->conditional_mod == ELK_CONDITIONAL_NONE) ||
scan_inst->conditional_mod == cond)) {
scan_inst->conditional_mod = cond;
scan_inst->flag_subreg = inst->flag_subreg;
@@ -550,7 +550,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
}
bool
fs_visitor::opt_cmod_propagation()
elk_fs_visitor::opt_cmod_propagation()
{
bool progress = false;
src/intel/compiler/elk/elk_fs_combine_constants.cpp
+126 -126
View File
@@ -62,7 +62,7 @@ struct value {
/**
* Which source of instr is this value?
*
* \note This field is not actually used by \c brw_combine_constants, but
* \note This field is not actually used by \c elk_combine_constants, but
* it is generally very useful to callers.
*/
uint8_t src;
@@ -107,10 +107,10 @@ struct value {
/**
* \name UtilCombineConstantsPrivate
* Private data used only by brw_combine_constants
* Private data used only by elk_combine_constants
*
* Any data stored in these fields will be overwritten by the call to
* \c brw_combine_constants. No assumptions should be made about the
* \c elk_combine_constants. No assumptions should be made about the
* state of these fields after that function returns.
*/
/**@{*/
@@ -156,7 +156,7 @@ struct combine_constants_value {
};
struct combine_constants_user {
/** Index into the array of values passed to brw_combine_constants. */
/** Index into the array of values passed to elk_combine_constants. */
unsigned index;
/**
@@ -757,7 +757,7 @@ combine_constants_greedy(struct value *candidates, unsigned num_candidates)
}
static combine_constants_result *
brw_combine_constants(struct value *candidates, unsigned num_candidates)
elk_combine_constants(struct value *candidates, unsigned num_candidates)
{
preprocess_candidates(candidates, num_candidates);
@@ -768,12 +768,12 @@ brw_combine_constants(struct value *candidates, unsigned num_candidates)
* replaced with a GRF source.
*/
static bool
could_coissue(const struct intel_device_info *devinfo, const fs_inst *inst)
could_coissue(const struct intel_device_info *devinfo, const elk_fs_inst *inst)
{
assert(inst->opcode == BRW_OPCODE_MOV ||
inst->opcode == BRW_OPCODE_CMP ||
inst->opcode == BRW_OPCODE_ADD ||
inst->opcode == BRW_OPCODE_MUL);
assert(inst->opcode == ELK_OPCODE_MOV ||
inst->opcode == ELK_OPCODE_CMP ||
inst->opcode == ELK_OPCODE_ADD ||
inst->opcode == ELK_OPCODE_MUL);
if (devinfo->ver != 7)
return false;
@@ -784,19 +784,19 @@ could_coissue(const struct intel_device_info *devinfo, const fs_inst *inst)
* (based on the source types), so we take the conservative choice of
* only promoting when both destination and source are float.
*/
return inst->dst.type == BRW_REGISTER_TYPE_F &&
inst->src[0].type == BRW_REGISTER_TYPE_F;
return inst->dst.type == ELK_REGISTER_TYPE_F &&
inst->src[0].type == ELK_REGISTER_TYPE_F;
}
/**
* Box for storing fs_inst and some other necessary data
* Box for storing elk_fs_inst and some other necessary data
*
* \sa box_instruction
*/
struct fs_inst_box {
fs_inst *inst;
elk_fs_inst *inst;
unsigned ip;
bblock_t *block;
elk_bblock_t *block;
bool must_promote;
};
@@ -804,18 +804,18 @@ struct fs_inst_box {
struct reg_link {
DECLARE_RALLOC_CXX_OPERATORS(reg_link)
reg_link(fs_inst *inst, unsigned src, bool negate, enum interpreted_type type)
reg_link(elk_fs_inst *inst, unsigned src, bool negate, enum interpreted_type type)
: inst(inst), src(src), negate(negate), type(type) {}
struct exec_node link;
fs_inst *inst;
elk_fs_inst *inst;
uint8_t src;
bool negate;
enum interpreted_type type;
};
static struct exec_node *
link(void *mem_ctx, fs_inst *inst, unsigned src, bool negate,
link(void *mem_ctx, elk_fs_inst *inst, unsigned src, bool negate,
enum interpreted_type type)
{
reg_link *l = new(mem_ctx) reg_link(inst, src, negate, type);
@@ -827,13 +827,13 @@ link(void *mem_ctx, fs_inst *inst, unsigned src, bool negate,
*/
struct imm {
/** The common ancestor of all blocks using this immediate value. */
bblock_t *block;
elk_bblock_t *block;
/**
* The instruction generating the immediate value, if all uses are contained
* within a single basic block. Otherwise, NULL.
*/
fs_inst *inst;
elk_fs_inst *inst;
/**
* A list of fs_regs that refer to this immediate. If we promote it, we'll
@@ -908,8 +908,8 @@ new_value(struct table *table, void *mem_ctx)
* \returns the index into the dynamic array of boxes for the instruction.
*/
static unsigned
box_instruction(struct table *table, void *mem_ctx, fs_inst *inst,
unsigned ip, bblock_t *block, bool must_promote)
box_instruction(struct table *table, void *mem_ctx, elk_fs_inst *inst,
unsigned ip, elk_bblock_t *block, bool must_promote)
{
/* It is common for box_instruction to be called consecutively for each
* source of an instruction. As a result, the most common case for finding
@@ -967,16 +967,16 @@ compare(const void *_a, const void *_b)
return a->first_use_ip - b->first_use_ip;
}
static struct brw_reg
static struct elk_reg
build_imm_reg_for_copy(struct imm *imm)
{
switch (imm->size) {
case 8:
return brw_imm_d(imm->d64);
return elk_imm_d(imm->d64);
case 4:
return brw_imm_d(imm->d);
return elk_imm_d(imm->d);
case 2:
return brw_imm_w(imm->w);
return elk_imm_w(imm->w);
default:
unreachable("not implemented");
}
@@ -1030,22 +1030,22 @@ representable_as_uw(unsigned ud, uint16_t *uw)
}
static bool
supports_src_as_imm(const struct intel_device_info *devinfo, const fs_inst *inst)
supports_src_as_imm(const struct intel_device_info *devinfo, const elk_fs_inst *inst)
{
if (devinfo->ver < 12)
return false;
switch (inst->opcode) {
case BRW_OPCODE_ADD3:
case ELK_OPCODE_ADD3:
/* ADD3 only exists on Gfx12.5+. */
return true;
case BRW_OPCODE_MAD:
case ELK_OPCODE_MAD:
/* Integer types can always mix sizes. Floating point types can mix
* sizes on Gfx12. On Gfx12.5, floating point sources must all be HF or
* all be F.
*/
return devinfo->verx10 < 125 || inst->src[0].type != BRW_REGISTER_TYPE_F;
return devinfo->verx10 < 125 || inst->src[0].type != ELK_REGISTER_TYPE_F;
default:
return false;
@@ -1053,7 +1053,7 @@ supports_src_as_imm(const struct intel_device_info *devinfo, const fs_inst *inst
}
static bool
can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
can_promote_src_as_imm(const struct intel_device_info *devinfo, elk_fs_inst *inst,
unsigned src_idx)
{
bool can_promote = false;
@@ -1073,33 +1073,33 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
* since HF/F mixed mode has been removed from the hardware.
*/
switch (inst->src[src_idx].type) {
case BRW_REGISTER_TYPE_F: {
case ELK_REGISTER_TYPE_F: {
uint16_t hf;
if (representable_as_hf(inst->src[src_idx].f, &hf)) {
inst->src[src_idx] = retype(brw_imm_uw(hf), BRW_REGISTER_TYPE_HF);
inst->src[src_idx] = retype(elk_imm_uw(hf), ELK_REGISTER_TYPE_HF);
can_promote = true;
}
break;
}
case BRW_REGISTER_TYPE_D: {
case ELK_REGISTER_TYPE_D: {
int16_t w;
if (representable_as_w(inst->src[src_idx].d, &w)) {
inst->src[src_idx] = brw_imm_w(w);
inst->src[src_idx] = elk_imm_w(w);
can_promote = true;
}
break;
}
case BRW_REGISTER_TYPE_UD: {
case ELK_REGISTER_TYPE_UD: {
uint16_t uw;
if (representable_as_uw(inst->src[src_idx].ud, &uw)) {
inst->src[src_idx] = brw_imm_uw(uw);
inst->src[src_idx] = elk_imm_uw(uw);
can_promote = true;
}
break;
}
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_HF:
case ELK_REGISTER_TYPE_W:
case ELK_REGISTER_TYPE_UW:
case ELK_REGISTER_TYPE_HF:
can_promote = true;
break;
default:
@@ -1110,11 +1110,11 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
}
static void
add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip,
add_candidate_immediate(struct table *table, elk_fs_inst *inst, unsigned ip,
unsigned i,
bool must_promote,
bool allow_one_constant,
bblock_t *block,
elk_bblock_t *block,
const struct intel_device_info *devinfo,
void *const_ctx)
{
@@ -1134,32 +1134,32 @@ add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip,
* allow negations on a right shift if the source type is already signed.
*/
v->no_negations = !inst->can_do_source_mods(devinfo) ||
((inst->opcode == BRW_OPCODE_SHR ||
inst->opcode == BRW_OPCODE_ASR) &&
brw_reg_type_is_unsigned_integer(inst->src[i].type));
((inst->opcode == ELK_OPCODE_SHR ||
inst->opcode == ELK_OPCODE_ASR) &&
elk_reg_type_is_unsigned_integer(inst->src[i].type));
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
case ELK_REGISTER_TYPE_DF:
case ELK_REGISTER_TYPE_NF:
case ELK_REGISTER_TYPE_F:
case ELK_REGISTER_TYPE_HF:
v->type = float_only;
break;
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_W:
case ELK_REGISTER_TYPE_UQ:
case ELK_REGISTER_TYPE_Q:
case ELK_REGISTER_TYPE_UD:
case ELK_REGISTER_TYPE_D:
case ELK_REGISTER_TYPE_UW:
case ELK_REGISTER_TYPE_W:
v->type = integer_only;
break;
case BRW_REGISTER_TYPE_VF:
case BRW_REGISTER_TYPE_UV:
case BRW_REGISTER_TYPE_V:
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case ELK_REGISTER_TYPE_VF:
case ELK_REGISTER_TYPE_UV:
case ELK_REGISTER_TYPE_V:
case ELK_REGISTER_TYPE_UB:
case ELK_REGISTER_TYPE_B:
default:
unreachable("not reached");
}
@@ -1168,8 +1168,8 @@ add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip,
* that has no conditional modifier, no source modifiers, and no saturate
* modifer.
*/
if (inst->opcode == BRW_OPCODE_SEL &&
inst->conditional_mod == BRW_CONDITIONAL_NONE &&
if (inst->opcode == ELK_OPCODE_SEL &&
inst->conditional_mod == ELK_CONDITIONAL_NONE &&
!inst->src[0].negate && !inst->src[0].abs &&
!inst->src[1].negate && !inst->src[1].abs &&
!inst->saturate) {
@@ -1190,7 +1190,7 @@ struct register_allocation {
uint16_t avail;
};
static fs_reg
static elk_fs_reg
allocate_slots(struct register_allocation *regs, unsigned num_regs,
unsigned bytes, unsigned align_bytes,
elk::simple_allocator &alloc)
@@ -1212,7 +1212,7 @@ allocate_slots(struct register_allocation *regs, unsigned num_regs,
regs[i].avail &= ~(mask << j);
fs_reg reg(VGRF, regs[i].nr);
elk_fs_reg reg(VGRF, regs[i].nr);
reg.offset = j * 2;
return reg;
@@ -1246,7 +1246,7 @@ deallocate_slots(struct register_allocation *regs, unsigned num_regs,
}
static void
parcel_out_registers(struct imm *imm, unsigned len, const bblock_t *cur_block,
parcel_out_registers(struct imm *imm, unsigned len, const elk_bblock_t *cur_block,
struct register_allocation *regs, unsigned num_regs,
elk::simple_allocator &alloc, unsigned ver)
{
@@ -1283,7 +1283,7 @@ parcel_out_registers(struct imm *imm, unsigned len, const bblock_t *cur_block,
*/
const unsigned width = ver == 8 && imm[i].is_half_float ? 2 : 1;
const fs_reg reg = allocate_slots(regs, num_regs,
const elk_fs_reg reg = allocate_slots(regs, num_regs,
imm[i].size * width,
get_alignment_for_imm(&imm[i]),
alloc);
@@ -1305,7 +1305,7 @@ parcel_out_registers(struct imm *imm, unsigned len, const bblock_t *cur_block,
}
bool
fs_visitor::opt_combine_constants()
elk_fs_visitor::opt_combine_constants()
{
void *const_ctx = ralloc_context(NULL);
@@ -1332,15 +1332,15 @@ fs_visitor::opt_combine_constants()
* constant is used by coissueable instructions or instructions that cannot
* take immediate arguments.
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, cfg) {
ip++;
switch (inst->opcode) {
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
case SHADER_OPCODE_POW:
case ELK_SHADER_OPCODE_INT_QUOTIENT:
case ELK_SHADER_OPCODE_INT_REMAINDER:
case ELK_SHADER_OPCODE_POW:
if (inst->src[0].file == IMM) {
assert(inst->opcode != SHADER_OPCODE_POW);
assert(inst->opcode != ELK_SHADER_OPCODE_POW);
add_candidate_immediate(&table, inst, ip, 0, true, false, block,
devinfo, const_ctx);
@@ -1353,8 +1353,8 @@ fs_visitor::opt_combine_constants()
break;
case BRW_OPCODE_ADD3:
case BRW_OPCODE_MAD: {
case ELK_OPCODE_ADD3:
case ELK_OPCODE_MAD: {
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].file != IMM)
continue;
@@ -1369,9 +1369,9 @@ fs_visitor::opt_combine_constants()
break;
}
case BRW_OPCODE_BFE:
case BRW_OPCODE_BFI2:
case BRW_OPCODE_LRP:
case ELK_OPCODE_BFE:
case ELK_OPCODE_BFI2:
case ELK_OPCODE_LRP:
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].file != IMM)
continue;
@@ -1382,16 +1382,16 @@ fs_visitor::opt_combine_constants()
break;
case BRW_OPCODE_SEL:
case ELK_OPCODE_SEL:
if (inst->src[0].file == IMM) {
/* It is possible to have src0 be immediate but src1 not be
* immediate for the non-commutative conditional modifiers (e.g.,
* G).
*/
if (inst->conditional_mod == BRW_CONDITIONAL_NONE ||
if (inst->conditional_mod == ELK_CONDITIONAL_NONE ||
/* Only GE and L are commutative. */
inst->conditional_mod == BRW_CONDITIONAL_GE ||
inst->conditional_mod == BRW_CONDITIONAL_L) {
inst->conditional_mod == ELK_CONDITIONAL_GE ||
inst->conditional_mod == ELK_CONDITIONAL_L) {
assert(inst->src[1].file == IMM);
add_candidate_immediate(&table, inst, ip, 0, true, true, block,
@@ -1405,28 +1405,28 @@ fs_visitor::opt_combine_constants()
}
break;
case BRW_OPCODE_ASR:
case BRW_OPCODE_BFI1:
case BRW_OPCODE_ROL:
case BRW_OPCODE_ROR:
case BRW_OPCODE_SHL:
case BRW_OPCODE_SHR:
case ELK_OPCODE_ASR:
case ELK_OPCODE_BFI1:
case ELK_OPCODE_ROL:
case ELK_OPCODE_ROR:
case ELK_OPCODE_SHL:
case ELK_OPCODE_SHR:
if (inst->src[0].file == IMM) {
add_candidate_immediate(&table, inst, ip, 0, true, false, block,
devinfo, const_ctx);
}
break;
case BRW_OPCODE_MOV:
case ELK_OPCODE_MOV:
if (could_coissue(devinfo, inst) && inst->src[0].file == IMM) {
add_candidate_immediate(&table, inst, ip, 0, false, false, block,
devinfo, const_ctx);
}
break;
case BRW_OPCODE_CMP:
case BRW_OPCODE_ADD:
case BRW_OPCODE_MUL:
case ELK_OPCODE_CMP:
case ELK_OPCODE_ADD:
case ELK_OPCODE_MUL:
assert(inst->src[0].file != IMM);
if (could_coissue(devinfo, inst) && inst->src[1].file == IMM) {
@@ -1446,7 +1446,7 @@ fs_visitor::opt_combine_constants()
}
combine_constants_result *result =
brw_combine_constants(table.values, table.num_values);
elk_combine_constants(table.values, table.num_values);
table.imm = ralloc_array(const_ctx, struct imm, result->num_values_to_emit);
table.len = 0;
@@ -1499,7 +1499,7 @@ fs_visitor::opt_combine_constants()
imm->last_use_ip = ib->ip;
imm->used_in_single_block = true;
} else {
bblock_t *intersection = idom.intersect(ib->block,
elk_bblock_t *intersection = idom.intersect(ib->block,
imm->block);
if (ib->block != imm->block)
@@ -1531,7 +1531,7 @@ fs_visitor::opt_combine_constants()
imm->block = intersection;
}
if (ib->inst->src[src].type == BRW_REGISTER_TYPE_HF)
if (ib->inst->src[src].type == ELK_REGISTER_TYPE_HF)
imm->is_half_float = true;
}
@@ -1567,7 +1567,7 @@ fs_visitor::opt_combine_constants()
free(regs);
} else {
fs_reg reg(VGRF, alloc.allocate(1));
elk_fs_reg reg(VGRF, alloc.allocate(1));
reg.stride = 0;
for (int i = 0; i < table.len; i++) {
@@ -1602,17 +1602,17 @@ fs_visitor::opt_combine_constants()
* or after the last non-control flow instruction of the common ancestor.
*/
exec_node *n;
bblock_t *insert_block;
elk_bblock_t *insert_block;
if (imm->inst != nullptr) {
n = imm->inst;
insert_block = imm->block;
} else {
if (imm->block->start()->opcode == BRW_OPCODE_DO) {
if (imm->block->start()->opcode == ELK_OPCODE_DO) {
/* DO blocks are weird. They can contain only the single DO
* instruction. As a result, MOV instructions cannot be added to
* the DO block.
*/
bblock_t *next_block = imm->block->next();
elk_bblock_t *next_block = imm->block->next();
if (next_block->starts_with_control_flow()) {
/* This is the difficult case. This occurs for code like
*
@@ -1663,7 +1663,7 @@ fs_visitor::opt_combine_constants()
const uint32_t width = devinfo->ver == 8 && imm->is_half_float ? 2 : 1;
const fs_builder ibld = fs_builder(this, width).at(insert_block, n).exec_all();
fs_reg reg(VGRF, imm->nr);
elk_fs_reg reg(VGRF, imm->nr);
reg.offset = imm->subreg_offset;
reg.stride = 0;
@@ -1673,7 +1673,7 @@ fs_visitor::opt_combine_constants()
*/
assert(reg.offset == ALIGN(reg.offset, get_alignment_for_imm(imm)));
struct brw_reg imm_reg = build_imm_reg_for_copy(imm);
struct elk_reg imm_reg = build_imm_reg_for_copy(imm);
/* Ensure we have enough space in the register to copy the immediate */
assert(reg.offset + type_sz(imm_reg.type) * width <= REG_SIZE);
@@ -1685,70 +1685,70 @@ fs_visitor::opt_combine_constants()
/* Rewrite the immediate sources to refer to the new GRFs. */
for (int i = 0; i < table.len; i++) {
foreach_list_typed(reg_link, link, link, table.imm[i].uses) {
fs_reg *reg = &link->inst->src[link->src];
elk_fs_reg *reg = &link->inst->src[link->src];
if (link->inst->opcode == BRW_OPCODE_SEL) {
if (link->inst->opcode == ELK_OPCODE_SEL) {
if (link->type == either_type) {
/* Do not change the register type. */
} else if (link->type == integer_only) {
reg->type = brw_int_type(type_sz(reg->type), true);
reg->type = elk_int_type(type_sz(reg->type), true);
} else {
assert(link->type == float_only);
switch (type_sz(reg->type)) {
case 2:
reg->type = BRW_REGISTER_TYPE_HF;
reg->type = ELK_REGISTER_TYPE_HF;
break;
case 4:
reg->type = BRW_REGISTER_TYPE_F;
reg->type = ELK_REGISTER_TYPE_F;
break;
case 8:
reg->type = BRW_REGISTER_TYPE_DF;
reg->type = ELK_REGISTER_TYPE_DF;
break;
default:
unreachable("Bad type size");
}
}
} else if ((link->inst->opcode == BRW_OPCODE_SHL ||
link->inst->opcode == BRW_OPCODE_ASR) &&
} else if ((link->inst->opcode == ELK_OPCODE_SHL ||
link->inst->opcode == ELK_OPCODE_ASR) &&
link->negate) {
reg->type = brw_int_type(type_sz(reg->type), true);
reg->type = elk_int_type(type_sz(reg->type), true);
}
#ifdef DEBUG
switch (reg->type) {
case BRW_REGISTER_TYPE_DF:
case ELK_REGISTER_TYPE_DF:
assert((isnan(reg->df) && isnan(table.imm[i].df)) ||
(fabs(reg->df) == fabs(table.imm[i].df)));
break;
case BRW_REGISTER_TYPE_F:
case ELK_REGISTER_TYPE_F:
assert((isnan(reg->f) && isnan(table.imm[i].f)) ||
(fabsf(reg->f) == fabsf(table.imm[i].f)));
break;
case BRW_REGISTER_TYPE_HF:
case ELK_REGISTER_TYPE_HF:
assert((isnan(_mesa_half_to_float(reg->d & 0xffffu)) &&
isnan(_mesa_half_to_float(table.imm[i].w))) ||
(fabsf(_mesa_half_to_float(reg->d & 0xffffu)) ==
fabsf(_mesa_half_to_float(table.imm[i].w))));
break;
case BRW_REGISTER_TYPE_Q:
case ELK_REGISTER_TYPE_Q:
assert(abs(reg->d64) == abs(table.imm[i].d64));
break;
case BRW_REGISTER_TYPE_UQ:
case ELK_REGISTER_TYPE_UQ:
assert(!link->negate);
assert(reg->d64 == table.imm[i].d64);
break;
case BRW_REGISTER_TYPE_D:
case ELK_REGISTER_TYPE_D:
assert(abs(reg->d) == abs(table.imm[i].d));
break;
case BRW_REGISTER_TYPE_UD:
case ELK_REGISTER_TYPE_UD:
assert(!link->negate);
assert(reg->d == table.imm[i].d);
break;
case BRW_REGISTER_TYPE_W:
case ELK_REGISTER_TYPE_W:
assert(abs((int16_t) (reg->d & 0xffff)) == table.imm[i].w);
break;
case BRW_REGISTER_TYPE_UW:
case ELK_REGISTER_TYPE_UW:
assert(!link->negate);
assert((reg->ud & 0xffffu) == (uint16_t) table.imm[i].w);
break;
@@ -1773,9 +1773,9 @@ fs_visitor::opt_combine_constants()
* so the other source (and destination) must be changed to match.
*/
for (unsigned i = 0; i < table.num_boxes; i++) {
fs_inst *inst = table.boxes[i].inst;
elk_fs_inst *inst = table.boxes[i].inst;
if (inst->opcode != BRW_OPCODE_SEL)
if (inst->opcode != ELK_OPCODE_SEL)
continue;
/* If both sources have negation, the types had better be the same! */
@@ -1799,18 +1799,18 @@ fs_visitor::opt_combine_constants()
continue;
assert(inst->src[1].file != IMM);
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE ||
inst->conditional_mod == BRW_CONDITIONAL_GE ||
inst->conditional_mod == BRW_CONDITIONAL_L);
assert(inst->conditional_mod == ELK_CONDITIONAL_NONE ||
inst->conditional_mod == ELK_CONDITIONAL_GE ||
inst->conditional_mod == ELK_CONDITIONAL_L);
fs_reg temp = inst->src[0];
elk_fs_reg temp = inst->src[0];
inst->src[0] = inst->src[1];
inst->src[1] = temp;
/* If this was predicated, flipping operands means we also need to flip
* the predicate.
*/
if (inst->conditional_mod == BRW_CONDITIONAL_NONE)
if (inst->conditional_mod == ELK_CONDITIONAL_NONE)
inst->predicate_inverse = !inst->predicate_inverse;
}
@@ -1835,7 +1835,7 @@ fs_visitor::opt_combine_constants()
if (rebuild_cfg) {
/* When the CFG is initially built, the instructions are removed from
* the list of instructions stored in fs_visitor -- the same exec_node
* the list of instructions stored in elk_fs_visitor -- the same exec_node
* is used for membership in that list and in a block list. So we need
* to pull them back before rebuilding the CFG.
*/
src/intel/compiler/elk/elk_fs_copy_propagation.cpp
+130 -130
View File
@@ -46,12 +46,12 @@ namespace { /* avoid conflict with opt_copy_propagation_elements */
struct acp_entry {
struct rb_node by_dst;
struct rb_node by_src;
fs_reg dst;
fs_reg src;
elk_fs_reg dst;
elk_fs_reg src;
unsigned global_idx;
unsigned size_written;
unsigned size_read;
enum opcode opcode;
enum elk_opcode opcode;
bool is_partial_write;
bool force_writemask_all;
};
@@ -265,7 +265,7 @@ struct block_data {
class fs_copy_prop_dataflow
{
public:
fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg,
fs_copy_prop_dataflow(linear_ctx *lin_ctx, elk_cfg_t *cfg,
const fs_live_variables &live,
struct acp *out_acp);
@@ -274,7 +274,7 @@ public:
void dump_block_data() const UNUSED;
cfg_t *cfg;
elk_cfg_t *cfg;
const fs_live_variables &live;
acp_entry **acp;
@@ -285,7 +285,7 @@ public:
};
} /* anonymous namespace */
fs_copy_prop_dataflow::fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg,
fs_copy_prop_dataflow::fs_copy_prop_dataflow(linear_ctx *lin_ctx, elk_cfg_t *cfg,
const fs_live_variables &live,
struct acp *out_acp)
: cfg(cfg), live(live)
@@ -338,7 +338,7 @@ fs_copy_prop_dataflow::fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg,
* Like reg_offset, but register must be VGRF or FIXED_GRF.
*/
static inline unsigned
grf_reg_offset(const fs_reg &r)
grf_reg_offset(const elk_fs_reg &r)
{
return (r.file == VGRF ? 0 : r.nr) * REG_SIZE +
r.offset +
@@ -349,7 +349,7 @@ grf_reg_offset(const fs_reg &r)
* Like regions_overlap, but register must be VGRF or FIXED_GRF.
*/
static inline bool
grf_regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
grf_regions_overlap(const elk_fs_reg &r, unsigned dr, const elk_fs_reg &s, unsigned ds)
{
return reg_space(r) == reg_space(s) &&
!(grf_reg_offset(r) + dr <= grf_reg_offset(s) ||
@@ -374,7 +374,7 @@ fs_copy_prop_dataflow::setup_initial_values()
acp_table.add(acp[i]);
foreach_block (block, cfg) {
foreach_inst_in_block(fs_inst, inst, block) {
foreach_inst_in_block(elk_fs_inst, inst, block) {
if (inst->dst.file != VGRF &&
inst->dst.file != FIXED_GRF)
continue;
@@ -463,8 +463,8 @@ fs_copy_prop_dataflow::run()
* parent blocks, it's live coming in to this block.
*/
bd[block->num].livein[i] = ~0u;
foreach_list_typed(bblock_link, parent_link, link, &block->parents) {
bblock_t *parent = parent_link->block;
foreach_list_typed(elk_bblock_link, parent_link, link, &block->parents) {
elk_bblock_t *parent = parent_link->block;
/* Consider ACP entries with a known-undefined destination to
* be available from the parent. This is valid because we're
* free to set the undefined variable equal to the source of
@@ -521,8 +521,8 @@ fs_copy_prop_dataflow::run()
* inconsistent execution masking, the start of this block
* is reachable by such an overwrite as well.
*/
foreach_list_typed(bblock_link, parent_link, link, &block->parents) {
bblock_t *parent = parent_link->block;
foreach_list_typed(elk_bblock_link, parent_link, link, &block->parents) {
elk_bblock_t *parent = parent_link->block;
bd[block->num].exec_mismatch[i] |= (bd[parent->num].exec_mismatch[i] &
bd[parent->num].reachin[i]);
}
@@ -546,8 +546,8 @@ fs_copy_prop_dataflow::dump_block_data() const
foreach_block (block, cfg) {
fprintf(stderr, "Block %d [%d, %d] (parents ", block->num,
block->start_ip, block->end_ip);
foreach_list_typed(bblock_link, link, link, &block->parents) {
bblock_t *parent = link->block;
foreach_list_typed(elk_bblock_link, link, link, &block->parents) {
elk_bblock_t *parent = link->block;
fprintf(stderr, "%d ", parent->num);
}
fprintf(stderr, "):\n");
@@ -568,18 +568,18 @@ fs_copy_prop_dataflow::dump_block_data() const
}
static bool
is_logic_op(enum opcode opcode)
is_logic_op(enum elk_opcode opcode)
{
return (opcode == BRW_OPCODE_AND ||
opcode == BRW_OPCODE_OR ||
opcode == BRW_OPCODE_XOR ||
opcode == BRW_OPCODE_NOT);
return (opcode == ELK_OPCODE_AND ||
opcode == ELK_OPCODE_OR ||
opcode == ELK_OPCODE_XOR ||
opcode == ELK_OPCODE_NOT);
}
static bool
can_take_stride(fs_inst *inst, brw_reg_type dst_type,
can_take_stride(elk_fs_inst *inst, elk_reg_type dst_type,
unsigned arg, unsigned stride,
const struct brw_compiler *compiler)
const struct elk_compiler *compiler)
{
const struct intel_device_info *devinfo = compiler->devinfo;
@@ -606,7 +606,7 @@ can_take_stride(fs_inst *inst, brw_reg_type dst_type,
* This is applicable to 32b datatypes and 16b datatype. 64b datatypes
* cannot use the replicate control.
*/
if (inst->is_3src(compiler)) {
if (inst->elk_is_3src(compiler)) {
if (type_sz(inst->src[arg].type) > 4)
return stride == 1;
else
@@ -643,14 +643,14 @@ can_take_stride(fs_inst *inst, brw_reg_type dst_type,
}
static bool
instruction_requires_packed_data(fs_inst *inst)
instruction_requires_packed_data(elk_fs_inst *inst)
{
switch (inst->opcode) {
case FS_OPCODE_DDX_FINE:
case FS_OPCODE_DDX_COARSE:
case FS_OPCODE_DDY_FINE:
case FS_OPCODE_DDY_COARSE:
case SHADER_OPCODE_QUAD_SWIZZLE:
case ELK_FS_OPCODE_DDX_FINE:
case ELK_FS_OPCODE_DDX_COARSE:
case ELK_FS_OPCODE_DDY_FINE:
case ELK_FS_OPCODE_DDY_COARSE:
case ELK_SHADER_OPCODE_QUAD_SWIZZLE:
return true;
default:
return false;
@@ -658,7 +658,7 @@ instruction_requires_packed_data(fs_inst *inst)
}
static bool
try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
try_copy_propagate(const elk_compiler *compiler, elk_fs_inst *inst,
acp_entry *entry, int arg,
const elk::simple_allocator &alloc,
uint8_t max_polygons)
@@ -685,7 +685,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
* optimization loop. Avoid this by detecting LOAD_PAYLOAD copies from CSE
* temporaries which should match is_coalescing_payload().
*/
if (entry->opcode == SHADER_OPCODE_LOAD_PAYLOAD &&
if (entry->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD &&
(is_coalescing_payload(alloc, inst) || is_multi_copy_payload(inst)))
return false;
@@ -714,7 +714,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
* We need to pin both split SEND sources in g112-g126/127, so only
* allow this if the registers aren't too large.
*/
if (inst->opcode == SHADER_OPCODE_SEND && entry->src.file == VGRF) {
if (inst->opcode == ELK_SHADER_OPCODE_SEND && entry->src.file == VGRF) {
int other_src = arg == 2 ? 3 : 2;
unsigned other_size = inst->src[other_src].file == VGRF ?
alloc.sizes[inst->src[other_src].nr] :
@@ -731,15 +731,15 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
*/
if (devinfo->has_pln && devinfo->ver <= 6 &&
entry->src.file == FIXED_GRF && (entry->src.nr & 1) &&
inst->opcode == FS_OPCODE_LINTERP && arg == 0)
inst->opcode == ELK_FS_OPCODE_LINTERP && arg == 0)
return false;
/* we can't generally copy-propagate UD negations because we
* can end up accessing the resulting values as signed integers
* instead. See also resolve_ud_negate() and comment in
* fs_generator::generate_code.
* elk_fs_generator::generate_code.
*/
if (entry->src.type == BRW_REGISTER_TYPE_UD &&
if (entry->src.type == ELK_REGISTER_TYPE_UD &&
entry->src.negate)
return false;
@@ -757,7 +757,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
}
if (has_source_modifiers &&
inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE)
inst->opcode == ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE)
return false;
/* Some instructions implemented in the generator backend, such as
@@ -769,7 +769,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
if (instruction_requires_packed_data(inst) && entry_stride != 1)
return false;
const brw_reg_type dst_type = (has_source_modifiers &&
const elk_reg_type dst_type = (has_source_modifiers &&
entry->dst.type != inst->src[arg].type) ?
entry->dst.type : inst->dst.type;
@@ -810,7 +810,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
if (entry->src.file == ATTR && max_polygons > 1 &&
(has_dst_aligned_region_restriction(devinfo, inst, dst_type) ||
instruction_requires_packed_data(inst) ||
(inst->is_3src(compiler) && arg == 2) ||
(inst->elk_is_3src(compiler) && arg == 2) ||
entry->dst.type != inst->src[arg].type))
return false;
@@ -833,7 +833,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
*/
if ((type_sz(entry->dst.type) < type_sz(inst->src[arg].type) ||
entry->is_partial_write) &&
inst->opcode != BRW_OPCODE_MOV) {
inst->opcode != ELK_OPCODE_MOV) {
return false;
}
@@ -900,7 +900,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
inst->src[arg].stride = 1;
/* Hopefully no Align16 around here... */
assert(entry->src.swizzle == BRW_SWIZZLE_XYZW);
assert(entry->src.swizzle == ELK_SWIZZLE_XYZW);
inst->src[arg].swizzle = entry->src.swizzle;
} else {
inst->src[arg].stride *= entry->src.stride;
@@ -909,7 +909,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
/* Compute the first component of the copy that the instruction is
* reading, and the base byte offset within that component.
*/
assert((entry->dst.offset % REG_SIZE == 0 || inst->opcode == BRW_OPCODE_MOV) &&
assert((entry->dst.offset % REG_SIZE == 0 || inst->opcode == ELK_OPCODE_MOV) &&
entry->dst.stride == 1);
const unsigned component = rel_offset / type_sz(entry->dst.type);
const unsigned suboffset = rel_offset % type_sz(entry->dst.type);
@@ -943,7 +943,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
static bool
try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
try_constant_propagate(const elk_compiler *compiler, elk_fs_inst *inst,
acp_entry *entry, int arg)
{
const struct intel_device_info *devinfo = compiler->devinfo;
@@ -973,7 +973,7 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
if (type_sz(inst->src[arg].type) > type_sz(entry->dst.type))
return false;
fs_reg val = entry->src;
elk_fs_reg val = entry->src;
/* If the size of the use type is smaller than the size of the entry,
* clamp the value to the range of the use type. This enables constant
@@ -1003,27 +1003,27 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
if (inst->src[arg].abs) {
if ((devinfo->ver >= 8 && is_logic_op(inst->opcode)) ||
!brw_abs_immediate(val.type, &val.as_brw_reg())) {
!elk_abs_immediate(val.type, &val.as_elk_reg())) {
return false;
}
}
if (inst->src[arg].negate) {
if ((devinfo->ver >= 8 && is_logic_op(inst->opcode)) ||
!brw_negate_immediate(val.type, &val.as_brw_reg())) {
!elk_negate_immediate(val.type, &val.as_elk_reg())) {
return false;
}
}
switch (inst->opcode) {
case BRW_OPCODE_MOV:
case SHADER_OPCODE_LOAD_PAYLOAD:
case FS_OPCODE_PACK:
case ELK_OPCODE_MOV:
case ELK_SHADER_OPCODE_LOAD_PAYLOAD:
case ELK_FS_OPCODE_PACK:
inst->src[arg] = val;
progress = true;
break;
case SHADER_OPCODE_POW:
case ELK_SHADER_OPCODE_POW:
/* Allow constant propagation into src1 (except on Gen 6 which
* doesn't support scalar source math), and let constant combining
* promote the constant on Gen < 8.
@@ -1037,19 +1037,19 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
}
break;
case BRW_OPCODE_SUBB:
case ELK_OPCODE_SUBB:
if (arg == 1) {
inst->src[arg] = val;
progress = true;
}
break;
case BRW_OPCODE_MACH:
case BRW_OPCODE_MUL:
case SHADER_OPCODE_MULH:
case BRW_OPCODE_ADD:
case BRW_OPCODE_XOR:
case BRW_OPCODE_ADDC:
case ELK_OPCODE_MACH:
case ELK_OPCODE_MUL:
case ELK_SHADER_OPCODE_MULH:
case ELK_OPCODE_ADD:
case ELK_OPCODE_XOR:
case ELK_OPCODE_ADDC:
if (arg == 1) {
inst->src[arg] = val;
progress = true;
@@ -1076,7 +1076,7 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
* When multiplying a DW and any lower precision integer, the
* DW operand must on src0.
*/
if (inst->opcode == BRW_OPCODE_MUL &&
if (inst->opcode == ELK_OPCODE_MUL &&
type_sz(inst->src[1].type) < 4 &&
type_sz(val.type) == 4)
break;
@@ -1092,11 +1092,11 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
* Integer MUL with a non-accumulator destination will be lowered
* by lower_integer_multiplication(), so don't restrict it.
*/
if (((inst->opcode == BRW_OPCODE_MUL &&
if (((inst->opcode == ELK_OPCODE_MUL &&
inst->dst.is_accumulator()) ||
inst->opcode == BRW_OPCODE_MACH) &&
(inst->src[1].type == BRW_REGISTER_TYPE_D ||
inst->src[1].type == BRW_REGISTER_TYPE_UD))
inst->opcode == ELK_OPCODE_MACH) &&
(inst->src[1].type == ELK_REGISTER_TYPE_D ||
inst->src[1].type == ELK_REGISTER_TYPE_UD))
break;
inst->src[0] = inst->src[1];
inst->src[1] = val;
@@ -1104,16 +1104,16 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
}
break;
case BRW_OPCODE_ADD3:
case ELK_OPCODE_ADD3:
/* add3 can have a single imm16 source. Proceed if the source type is
* already W or UW or the value can be coerced to one of those types.
*/
if (val.type == BRW_REGISTER_TYPE_W || val.type == BRW_REGISTER_TYPE_UW)
if (val.type == ELK_REGISTER_TYPE_W || val.type == ELK_REGISTER_TYPE_UW)
; /* Nothing to do. */
else if (val.ud <= 0xffff)
val = brw_imm_uw(val.ud);
val = elk_imm_uw(val.ud);
else if (val.d >= -0x8000 && val.d <= 0x7fff)
val = brw_imm_w(val.d);
val = elk_imm_w(val.d);
else
break;
@@ -1128,16 +1128,16 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
break;
case BRW_OPCODE_CMP:
case BRW_OPCODE_IF:
case ELK_OPCODE_CMP:
case ELK_OPCODE_IF:
if (arg == 1) {
inst->src[arg] = val;
progress = true;
} else if (arg == 0 && inst->src[1].file != IMM) {
enum brw_conditional_mod new_cmod;
enum elk_conditional_mod new_cmod;
new_cmod = brw_swap_cmod(inst->conditional_mod);
if (new_cmod != BRW_CONDITIONAL_NONE) {
new_cmod = elk_swap_cmod(inst->conditional_mod);
if (new_cmod != ELK_CONDITIONAL_NONE) {
/* Fit this constant in by swapping the operands and
* flipping the test
*/
@@ -1149,23 +1149,23 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
}
break;
case BRW_OPCODE_SEL:
case ELK_OPCODE_SEL:
if (arg == 1) {
inst->src[arg] = val;
progress = true;
} else if (arg == 0) {
if (inst->src[1].file != IMM &&
(inst->conditional_mod == BRW_CONDITIONAL_NONE ||
(inst->conditional_mod == ELK_CONDITIONAL_NONE ||
/* Only GE and L are commutative. */
inst->conditional_mod == BRW_CONDITIONAL_GE ||
inst->conditional_mod == BRW_CONDITIONAL_L)) {
inst->conditional_mod == ELK_CONDITIONAL_GE ||
inst->conditional_mod == ELK_CONDITIONAL_L)) {
inst->src[0] = inst->src[1];
inst->src[1] = val;
/* If this was predicated, flipping operands means
* we also need to flip the predicate.
*/
if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
if (inst->conditional_mod == ELK_CONDITIONAL_NONE) {
inst->predicate_inverse =
!inst->predicate_inverse;
}
@@ -1177,8 +1177,8 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
}
break;
case FS_OPCODE_FB_WRITE_LOGICAL:
/* The stencil and omask sources of FS_OPCODE_FB_WRITE_LOGICAL are
case ELK_FS_OPCODE_FB_WRITE_LOGICAL:
/* The stencil and omask sources of ELK_FS_OPCODE_FB_WRITE_LOGICAL are
* bit-cast using a strided region so they cannot be immediates.
*/
if (arg != FB_WRITE_LOGICAL_SRC_SRC_STENCIL &&
@@ -1188,8 +1188,8 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
}
break;
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
case ELK_SHADER_OPCODE_INT_QUOTIENT:
case ELK_SHADER_OPCODE_INT_REMAINDER:
/* Allow constant propagation into either source (except on Gen 6
* which doesn't support scalar source math). Constant combining
* promote the src1 constant on Gen < 8, and it will promote the src0
@@ -1199,46 +1199,46 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
break;
FALLTHROUGH;
case BRW_OPCODE_AND:
case BRW_OPCODE_ASR:
case BRW_OPCODE_BFE:
case BRW_OPCODE_BFI1:
case BRW_OPCODE_BFI2:
case BRW_OPCODE_ROL:
case BRW_OPCODE_ROR:
case BRW_OPCODE_SHL:
case BRW_OPCODE_SHR:
case BRW_OPCODE_OR:
case SHADER_OPCODE_TEX_LOGICAL:
case SHADER_OPCODE_TXD_LOGICAL:
case SHADER_OPCODE_TXF_LOGICAL:
case SHADER_OPCODE_TXL_LOGICAL:
case SHADER_OPCODE_TXS_LOGICAL:
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case SHADER_OPCODE_BROADCAST:
case BRW_OPCODE_MAD:
case BRW_OPCODE_LRP:
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
case SHADER_OPCODE_SHUFFLE:
case ELK_OPCODE_AND:
case ELK_OPCODE_ASR:
case ELK_OPCODE_BFE:
case ELK_OPCODE_BFI1:
case ELK_OPCODE_BFI2:
case ELK_OPCODE_ROL:
case ELK_OPCODE_ROR:
case ELK_OPCODE_SHL:
case ELK_OPCODE_SHR:
case ELK_OPCODE_OR:
case ELK_SHADER_OPCODE_TEX_LOGICAL:
case ELK_SHADER_OPCODE_TXD_LOGICAL:
case ELK_SHADER_OPCODE_TXF_LOGICAL:
case ELK_SHADER_OPCODE_TXL_LOGICAL:
case ELK_SHADER_OPCODE_TXS_LOGICAL:
case ELK_FS_OPCODE_TXB_LOGICAL:
case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL:
case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL:
case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL:
case ELK_SHADER_OPCODE_LOD_LOGICAL:
case ELK_SHADER_OPCODE_TG4_LOGICAL:
case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL:
case ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL:
case ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case ELK_SHADER_OPCODE_BROADCAST:
case ELK_OPCODE_MAD:
case ELK_OPCODE_LRP:
case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT:
case ELK_SHADER_OPCODE_SHUFFLE:
inst->src[arg] = val;
progress = true;
break;
@@ -1251,9 +1251,9 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
}
static bool
can_propagate_from(fs_inst *inst)
can_propagate_from(elk_fs_inst *inst)
{
return (inst->opcode == BRW_OPCODE_MOV &&
return (inst->opcode == ELK_OPCODE_MOV &&
inst->dst.file == VGRF &&
((inst->src[0].file == VGRF &&
!grf_regions_overlap(inst->dst, inst->size_written,
@@ -1274,14 +1274,14 @@ can_propagate_from(fs_inst *inst)
* list.
*/
static bool
opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx,
bblock_t *block, struct acp &acp,
opt_copy_propagation_local(const elk_compiler *compiler, linear_ctx *lin_ctx,
elk_bblock_t *block, struct acp &acp,
const elk::simple_allocator &alloc,
uint8_t max_polygons)
{
bool progress = false;
foreach_inst_in_block(fs_inst, inst, block) {
foreach_inst_in_block(elk_fs_inst, inst, block) {
/* Try propagating into this instruction. */
bool instruction_progress = false;
for (int i = inst->sources - 1; i >= 0; i--) {
@@ -1310,7 +1310,7 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx,
progress = true;
/* ADD3 can only have the immediate as src0. */
if (inst->opcode == BRW_OPCODE_ADD3) {
if (inst->opcode == ELK_OPCODE_ADD3) {
if (inst->src[2].file == IMM) {
const auto src0 = inst->src[0];
inst->src[0] = inst->src[2];
@@ -1366,7 +1366,7 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx,
entry->is_partial_write = inst->is_partial_write();
entry->force_writemask_all = inst->force_writemask_all;
acp.add(entry);
} else if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD &&
} else if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD &&
inst->dst.file == VGRF) {
int offset = 0;
for (int i = 0; i < inst->sources; i++) {
@@ -1376,9 +1376,9 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx,
if (inst->src[i].file == VGRF ||
(inst->src[i].file == FIXED_GRF &&
inst->src[i].is_contiguous())) {
const brw_reg_type t = i < inst->header_size ?
BRW_REGISTER_TYPE_UD : inst->src[i].type;
fs_reg dst = byte_offset(retype(inst->dst, t), offset);
const elk_reg_type t = i < inst->header_size ?
ELK_REGISTER_TYPE_UD : inst->src[i].type;
elk_fs_reg dst = byte_offset(retype(inst->dst, t), offset);
if (!dst.equals(inst->src[i])) {
acp_entry *entry = linear_zalloc(lin_ctx, acp_entry);
entry->dst = dst;
@@ -1399,7 +1399,7 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx,
}
bool
fs_visitor::opt_copy_propagation()
elk_fs_visitor::opt_copy_propagation()
{
bool progress = false;
void *copy_prop_ctx = ralloc_context(NULL);
src/intel/compiler/elk/elk_fs_cse.cpp
+83 -83
View File
@@ -38,76 +38,76 @@ using namespace elk;
namespace {
struct aeb_entry : public exec_node {
/** The instruction that generates the expression value. */
fs_inst *generator;
elk_fs_inst *generator;
/** The temporary where the value is stored. */
fs_reg tmp;
elk_fs_reg tmp;
};
}
static bool
is_expression(const fs_visitor *v, const fs_inst *const inst)
is_expression(const elk_fs_visitor *v, const elk_fs_inst *const inst)
{
switch (inst->opcode) {
case BRW_OPCODE_MOV:
case BRW_OPCODE_SEL:
case BRW_OPCODE_NOT:
case BRW_OPCODE_AND:
case BRW_OPCODE_OR:
case BRW_OPCODE_XOR:
case BRW_OPCODE_SHR:
case BRW_OPCODE_SHL:
case BRW_OPCODE_ASR:
case BRW_OPCODE_CMP:
case BRW_OPCODE_CMPN:
case BRW_OPCODE_ADD:
case BRW_OPCODE_MUL:
case SHADER_OPCODE_MULH:
case BRW_OPCODE_FRC:
case BRW_OPCODE_RNDU:
case BRW_OPCODE_RNDD:
case BRW_OPCODE_RNDE:
case BRW_OPCODE_RNDZ:
case BRW_OPCODE_LINE:
case BRW_OPCODE_PLN:
case BRW_OPCODE_MAD:
case BRW_OPCODE_LRP:
case FS_OPCODE_FB_READ_LOGICAL:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
case FS_OPCODE_LINTERP:
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL:
case FS_OPCODE_LOAD_LIVE_CHANNELS:
case SHADER_OPCODE_BROADCAST:
case SHADER_OPCODE_MOV_INDIRECT:
case SHADER_OPCODE_TEX_LOGICAL:
case SHADER_OPCODE_TXD_LOGICAL:
case SHADER_OPCODE_TXF_LOGICAL:
case SHADER_OPCODE_TXL_LOGICAL:
case SHADER_OPCODE_TXS_LOGICAL:
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
case FS_OPCODE_PACK:
case ELK_OPCODE_MOV:
case ELK_OPCODE_SEL:
case ELK_OPCODE_NOT:
case ELK_OPCODE_AND:
case ELK_OPCODE_OR:
case ELK_OPCODE_XOR:
case ELK_OPCODE_SHR:
case ELK_OPCODE_SHL:
case ELK_OPCODE_ASR:
case ELK_OPCODE_CMP:
case ELK_OPCODE_CMPN:
case ELK_OPCODE_ADD:
case ELK_OPCODE_MUL:
case ELK_SHADER_OPCODE_MULH:
case ELK_OPCODE_FRC:
case ELK_OPCODE_RNDU:
case ELK_OPCODE_RNDD:
case ELK_OPCODE_RNDE:
case ELK_OPCODE_RNDZ:
case ELK_OPCODE_LINE:
case ELK_OPCODE_PLN:
case ELK_OPCODE_MAD:
case ELK_OPCODE_LRP:
case ELK_FS_OPCODE_FB_READ_LOGICAL:
case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
case ELK_FS_OPCODE_LINTERP:
case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL:
case ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL:
case ELK_FS_OPCODE_LOAD_LIVE_CHANNELS:
case ELK_SHADER_OPCODE_BROADCAST:
case ELK_SHADER_OPCODE_MOV_INDIRECT:
case ELK_SHADER_OPCODE_TEX_LOGICAL:
case ELK_SHADER_OPCODE_TXD_LOGICAL:
case ELK_SHADER_OPCODE_TXF_LOGICAL:
case ELK_SHADER_OPCODE_TXL_LOGICAL:
case ELK_SHADER_OPCODE_TXS_LOGICAL:
case ELK_FS_OPCODE_TXB_LOGICAL:
case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL:
case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL:
case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL:
case ELK_SHADER_OPCODE_LOD_LOGICAL:
case ELK_SHADER_OPCODE_TG4_LOGICAL:
case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL:
case ELK_FS_OPCODE_PACK:
return true;
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_SQRT:
case SHADER_OPCODE_EXP2:
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_POW:
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
case ELK_SHADER_OPCODE_RCP:
case ELK_SHADER_OPCODE_RSQ:
case ELK_SHADER_OPCODE_SQRT:
case ELK_SHADER_OPCODE_EXP2:
case ELK_SHADER_OPCODE_LOG2:
case ELK_SHADER_OPCODE_POW:
case ELK_SHADER_OPCODE_INT_QUOTIENT:
case ELK_SHADER_OPCODE_INT_REMAINDER:
case ELK_SHADER_OPCODE_SIN:
case ELK_SHADER_OPCODE_COS:
return inst->mlen < 2;
case SHADER_OPCODE_LOAD_PAYLOAD:
case ELK_SHADER_OPCODE_LOAD_PAYLOAD:
return !is_coalescing_payload(v->alloc, inst);
default:
return inst->is_send_from_grf() && !inst->has_side_effects() &&
@@ -116,16 +116,16 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
}
static bool
operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
operands_match(const elk_fs_inst *a, const elk_fs_inst *b, bool *negate)
{
fs_reg *xs = a->src;
fs_reg *ys = b->src;
elk_fs_reg *xs = a->src;
elk_fs_reg *ys = b->src;
if (a->opcode == BRW_OPCODE_MAD) {
if (a->opcode == ELK_OPCODE_MAD) {
return xs[0].equals(ys[0]) &&
((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
(xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
} else if (a->opcode == BRW_OPCODE_MUL && a->dst.type == BRW_REGISTER_TYPE_F) {
} else if (a->opcode == ELK_OPCODE_MUL && a->dst.type == ELK_REGISTER_TYPE_F) {
bool xs0_negate = xs[0].negate;
bool xs1_negate = xs[1].file == IMM ? xs[1].f < 0.0f
: xs[1].negate;
@@ -172,7 +172,7 @@ operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
}
static bool
instructions_match(fs_inst *a, fs_inst *b, bool *negate)
instructions_match(elk_fs_inst *a, elk_fs_inst *b, bool *negate)
{
return a->opcode == b->opcode &&
a->force_writemask_all == b->force_writemask_all &&
@@ -203,16 +203,16 @@ instructions_match(fs_inst *a, fs_inst *b, bool *negate)
}
static void
create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate)
create_copy_instr(const fs_builder &bld, elk_fs_inst *inst, elk_fs_reg src, bool negate)
{
unsigned written = regs_written(inst);
unsigned dst_width =
DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE);
fs_inst *copy;
elk_fs_inst *copy;
if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD) {
assert(src.file == VGRF);
fs_reg *payload = ralloc_array(bld.shader->mem_ctx, fs_reg,
elk_fs_reg *payload = ralloc_array(bld.shader->mem_ctx, elk_fs_reg,
inst->sources);
for (int i = 0; i < inst->header_size; i++) {
payload[i] = src;
@@ -229,7 +229,7 @@ create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate)
assert(src.file == VGRF);
assert(written % dst_width == 0);
const int sources = written / dst_width;
fs_reg *payload = ralloc_array(bld.shader->mem_ctx, fs_reg, sources);
elk_fs_reg *payload = ralloc_array(bld.shader->mem_ctx, elk_fs_reg, sources);
for (int i = 0; i < sources; i++) {
payload[i] = src;
src = offset(src, bld, 1);
@@ -245,14 +245,14 @@ create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate)
}
bool
fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &ip)
elk_fs_visitor::opt_cse_local(const fs_live_variables &live, elk_bblock_t *block, int &ip)
{
bool progress = false;
exec_list aeb;
void *cse_ctx = ralloc_context(NULL);
foreach_inst_in_block(fs_inst, inst, block) {
foreach_inst_in_block(elk_fs_inst, inst, block) {
/* Skip some cases. */
if (is_expression(this, inst) && !inst->is_partial_write() &&
((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) ||
@@ -272,10 +272,10 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i
}
if (!found) {
if (inst->opcode != BRW_OPCODE_MOV ||
(inst->opcode == BRW_OPCODE_MOV &&
if (inst->opcode != ELK_OPCODE_MOV ||
(inst->opcode == ELK_OPCODE_MOV &&
inst->src[0].file == IMM &&
inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
inst->src[0].type == ELK_REGISTER_TYPE_VF)) {
/* Our first sighting of this expression. Create an entry. */
aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
entry->tmp = reg_undef;
@@ -292,7 +292,7 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i
.at(block, entry->generator->next);
int written = regs_written(entry->generator);
entry->tmp = fs_reg(VGRF, alloc.allocate(written),
entry->tmp = elk_fs_reg(VGRF, alloc.allocate(written),
entry->generator->dst.type);
create_copy_instr(ibld, entry->generator, entry->tmp, false);
@@ -313,7 +313,7 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i
* will get the instruction in the basic block after the one we've
* removed.
*/
fs_inst *prev = (fs_inst *)inst->prev;
elk_fs_inst *prev = (elk_fs_inst *)inst->prev;
inst->remove(block);
inst = prev;
@@ -324,10 +324,10 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i
* to make sure that they behave as a CSE barrier, since we lack global
* dataflow information. This is particularly likely to cause problems
* with instructions dependent on the current execution mask like
* SHADER_OPCODE_FIND_LIVE_CHANNEL.
* ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL.
*/
if (inst->opcode == BRW_OPCODE_HALT ||
inst->opcode == SHADER_OPCODE_HALT_TARGET)
if (inst->opcode == ELK_OPCODE_HALT ||
inst->opcode == ELK_SHADER_OPCODE_HALT_TARGET)
aeb.make_empty();
foreach_in_list_safe(aeb_entry, entry, &aeb) {
@@ -346,7 +346,7 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i
}
for (int i = 0; i < entry->generator->sources; i++) {
fs_reg *src_reg = &entry->generator->src[i];
elk_fs_reg *src_reg = &entry->generator->src[i];
/* Kill all AEB entries that use the destination we just
* overwrote.
@@ -379,7 +379,7 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i
}
bool
fs_visitor::opt_cse()
elk_fs_visitor::opt_cse()
{
const fs_live_variables &live = live_analysis.require();
bool progress = false;
src/intel/compiler/elk/elk_fs_dead_code_eliminate.cpp
+10 -10
View File
@@ -40,7 +40,7 @@ using namespace elk;
* Is it safe to eliminate the instruction?
*/
static bool
can_eliminate(const intel_device_info *devinfo, const fs_inst *inst,
can_eliminate(const intel_device_info *devinfo, const elk_fs_inst *inst,
BITSET_WORD *flag_live)
{
return !inst->is_control_flow() &&
@@ -53,12 +53,12 @@ can_eliminate(const intel_device_info *devinfo, const fs_inst *inst,
* Is it safe to omit the write, making the destination ARF null?
*/
static bool
can_omit_write(const fs_inst *inst)
can_omit_write(const elk_fs_inst *inst)
{
switch (inst->opcode) {
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
return true;
default:
/* We can eliminate the destination write for ordinary instructions,
@@ -73,7 +73,7 @@ can_omit_write(const fs_inst *inst)
}
bool
fs_visitor::dead_code_eliminate()
elk_fs_visitor::dead_code_eliminate()
{
bool progress = false;
@@ -88,7 +88,7 @@ fs_visitor::dead_code_eliminate()
memcpy(flag_live, live_vars.block_data[block->num].flag_liveout,
sizeof(BITSET_WORD));
foreach_inst_in_block_reverse_safe(fs_inst, inst, block) {
foreach_inst_in_block_reverse_safe(elk_fs_inst, inst, block) {
if (inst->dst.file == VGRF) {
const unsigned var = live_vars.var_from_reg(inst->dst);
bool result_live = false;
@@ -98,14 +98,14 @@ fs_visitor::dead_code_eliminate()
if (!result_live &&
(can_omit_write(inst) || can_eliminate(devinfo, inst, flag_live))) {
inst->dst = fs_reg(spread(retype(brw_null_reg(), inst->dst.type),
inst->dst = elk_fs_reg(spread(retype(elk_null_reg(), inst->dst.type),
inst->dst.stride));
progress = true;
}
}
if (inst->dst.is_null() && can_eliminate(devinfo, inst, flag_live)) {
inst->opcode = BRW_OPCODE_NOP;
inst->opcode = ELK_OPCODE_NOP;
progress = true;
}
@@ -121,7 +121,7 @@ fs_visitor::dead_code_eliminate()
if (!inst->predicate && inst->exec_size >= 8)
flag_live[0] &= ~inst->flags_written(devinfo);
if (inst->opcode == BRW_OPCODE_NOP) {
if (inst->opcode == ELK_OPCODE_NOP) {
inst->remove(block, true);
continue;
}
src/intel/compiler/elk/elk_fs_generator.cpp
+775 -776
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_fs_live_variables.cpp
+12 -12
View File
@@ -54,7 +54,7 @@ using namespace elk;
void
fs_live_variables::setup_one_read(struct block_data *bd,
int ip, const fs_reg &reg)
int ip, const elk_fs_reg &reg)
{
int var = var_from_reg(reg);
assert(var < num_vars);
@@ -71,8 +71,8 @@ fs_live_variables::setup_one_read(struct block_data *bd,
}
void
fs_live_variables::setup_one_write(struct block_data *bd, fs_inst *inst,
int ip, const fs_reg &reg)
fs_live_variables::setup_one_write(struct block_data *bd, elk_fs_inst *inst,
int ip, const elk_fs_reg &reg)
{
int var = var_from_reg(reg);
assert(var < num_vars);
@@ -112,10 +112,10 @@ fs_live_variables::setup_def_use()
struct block_data *bd = &block_data[block->num];
foreach_inst_in_block(fs_inst, inst, block) {
foreach_inst_in_block(elk_fs_inst, inst, block) {
/* Set use[] for this instruction */
for (unsigned int i = 0; i < inst->sources; i++) {
fs_reg reg = inst->src[i];
elk_fs_reg reg = inst->src[i];
if (reg.file != VGRF)
continue;
@@ -130,7 +130,7 @@ fs_live_variables::setup_def_use()
/* Set def[] for this instruction */
if (inst->dst.file == VGRF) {
fs_reg reg = inst->dst;
elk_fs_reg reg = inst->dst;
for (unsigned j = 0; j < regs_written(inst); j++) {
setup_one_write(bd, inst, ip, reg);
reg.offset += REG_SIZE;
@@ -165,7 +165,7 @@ fs_live_variables::compute_live_variables()
foreach_block (block, cfg) {
const struct block_data *bd = &block_data[block->num];
foreach_list_typed(bblock_link, child_link, link, &block->children) {
foreach_list_typed(elk_bblock_link, child_link, link, &block->children) {
struct block_data *child_bd = &block_data[child_link->block->num];
for (int i = 0; i < bitset_words; i++) {
@@ -185,7 +185,7 @@ fs_live_variables::compute_live_variables()
struct block_data *bd = &block_data[block->num];
/* Update liveout */
foreach_list_typed(bblock_link, child_link, link, &block->children) {
foreach_list_typed(elk_bblock_link, child_link, link, &block->children) {
struct block_data *child_bd = &block_data[child_link->block->num];
for (int i = 0; i < bitset_words; i++) {
@@ -246,7 +246,7 @@ fs_live_variables::compute_start_end()
}
}
fs_live_variables::fs_live_variables(const backend_shader *s)
fs_live_variables::fs_live_variables(const elk_backend_shader *s)
: devinfo(s->devinfo), cfg(s->cfg)
{
mem_ctx = ralloc_context(NULL);
@@ -317,7 +317,7 @@ fs_live_variables::~fs_live_variables()
static bool
check_register_live_range(const fs_live_variables *live, int ip,
const fs_reg &reg, unsigned n)
const elk_fs_reg &reg, unsigned n)
{
const unsigned var = live->var_from_reg(reg);
@@ -334,11 +334,11 @@ check_register_live_range(const fs_live_variables *live, int ip,
}
bool
fs_live_variables::validate(const backend_shader *s) const
fs_live_variables::validate(const elk_backend_shader *s) const
{
int ip = 0;
foreach_block_and_inst(block, fs_inst, inst, s->cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, s->cfg) {
for (unsigned i = 0; i < inst->sources; i++) {
if (inst->src[i].file == VGRF &&
!check_register_live_range(this, ip,
src/intel/compiler/elk/elk_fs_live_variables.h
+9 -9
View File
@@ -32,8 +32,8 @@
#include "elk_ir_fs.h"
#include "util/bitset.h"
struct cfg_t;
struct backend_shader;
struct elk_cfg_t;
struct elk_backend_shader;
namespace elk {
@@ -77,10 +77,10 @@ public:
BITSET_WORD flag_liveout[1];
};
fs_live_variables(const backend_shader *s);
fs_live_variables(const elk_backend_shader *s);
~fs_live_variables();
bool validate(const backend_shader *s) const;
bool validate(const elk_backend_shader *s) const;
analysis_dependency_class
dependency_class() const
@@ -92,7 +92,7 @@ public:
bool vars_interfere(int a, int b) const;
bool vgrfs_interfere(int a, int b) const;
int var_from_reg(const fs_reg &reg) const
int var_from_reg(const elk_fs_reg &reg) const
{
return var_from_vgrf[reg.nr] + reg.offset / REG_SIZE;
}
@@ -132,14 +132,14 @@ public:
protected:
void setup_def_use();
void setup_one_read(struct block_data *bd, int ip, const fs_reg &reg);
void setup_one_write(struct block_data *bd, fs_inst *inst, int ip,
const fs_reg &reg);
void setup_one_read(struct block_data *bd, int ip, const elk_fs_reg &reg);
void setup_one_write(struct block_data *bd, elk_fs_inst *inst, int ip,
const elk_fs_reg &reg);
void compute_live_variables();
void compute_start_end();
const struct intel_device_info *devinfo;
const cfg_t *cfg;
const elk_cfg_t *cfg;
void *mem_ctx;
};
src/intel/compiler/elk/elk_fs_lower_pack.cpp
+15 -15
View File
@@ -29,18 +29,18 @@
using namespace elk;
bool
fs_visitor::lower_pack()
elk_fs_visitor::lower_pack()
{
bool progress = false;
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
if (inst->opcode != FS_OPCODE_PACK &&
inst->opcode != FS_OPCODE_PACK_HALF_2x16_SPLIT)
foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) {
if (inst->opcode != ELK_FS_OPCODE_PACK &&
inst->opcode != ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT)
continue;
assert(inst->dst.file == VGRF);
assert(inst->saturate == false);
fs_reg dst = inst->dst;
elk_fs_reg dst = inst->dst;
const fs_builder ibld(this, block, inst);
/* The lowering generates 2 instructions for what was previously 1. This
@@ -52,27 +52,27 @@ fs_visitor::lower_pack()
ibld.emit_undef_for_dst(inst);
switch (inst->opcode) {
case FS_OPCODE_PACK:
case ELK_FS_OPCODE_PACK:
for (unsigned i = 0; i < inst->sources; i++)
ibld.MOV(subscript(dst, inst->src[i].type, i), inst->src[i]);
break;
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
assert(dst.type == BRW_REGISTER_TYPE_UD);
case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT:
assert(dst.type == ELK_REGISTER_TYPE_UD);
for (unsigned i = 0; i < inst->sources; i++) {
if (inst->src[i].file == IMM) {
const uint32_t half = _mesa_float_to_half(inst->src[i].f);
ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_UW, i),
brw_imm_uw(half));
ibld.MOV(subscript(dst, ELK_REGISTER_TYPE_UW, i),
elk_imm_uw(half));
} else if (i == 1 && devinfo->ver < 9) {
/* Pre-Skylake requires DWord aligned destinations */
fs_reg tmp = ibld.vgrf(BRW_REGISTER_TYPE_UD);
ibld.F32TO16(subscript(tmp, BRW_REGISTER_TYPE_HF, 0),
elk_fs_reg tmp = ibld.vgrf(ELK_REGISTER_TYPE_UD);
ibld.F32TO16(subscript(tmp, ELK_REGISTER_TYPE_HF, 0),
inst->src[i]);
ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_UW, 1),
subscript(tmp, BRW_REGISTER_TYPE_UW, 0));
ibld.MOV(subscript(dst, ELK_REGISTER_TYPE_UW, 1),
subscript(tmp, ELK_REGISTER_TYPE_UW, 0));
} else {
ibld.F32TO16(subscript(dst, BRW_REGISTER_TYPE_HF, i),
ibld.F32TO16(subscript(dst, ELK_REGISTER_TYPE_HF, i),
inst->src[i]);
}
}
src/intel/compiler/elk/elk_fs_lower_regioning.cpp
+77 -77
View File
@@ -36,10 +36,10 @@ namespace {
* using raw move."
*/
bool
is_byte_raw_mov(const fs_inst *inst)
is_byte_raw_mov(const elk_fs_inst *inst)
{
return type_sz(inst->dst.type) == 1 &&
inst->opcode == BRW_OPCODE_MOV &&
inst->opcode == ELK_OPCODE_MOV &&
inst->src[0].type == inst->dst.type &&
!inst->saturate &&
!inst->src[0].negate &&
@@ -51,7 +51,7 @@ namespace {
* that requires it to have some particular alignment.
*/
unsigned
required_dst_byte_stride(const fs_inst *inst)
required_dst_byte_stride(const elk_fs_inst *inst)
{
if (inst->dst.is_accumulator()) {
/* If the destination is an accumulator, insist that we leave the
@@ -107,7 +107,7 @@ namespace {
* the sources.
*/
unsigned
required_dst_byte_offset(const intel_device_info *devinfo, const fs_inst *inst)
required_dst_byte_offset(const intel_device_info *devinfo, const elk_fs_inst *inst)
{
for (unsigned i = 0; i < inst->sources; i++) {
if (!is_uniform(inst->src[i]) && !inst->is_control_source(i))
@@ -123,15 +123,15 @@ namespace {
* Return the closest legal execution type for an instruction on
* the specified platform.
*/
brw_reg_type
required_exec_type(const intel_device_info *devinfo, const fs_inst *inst)
elk_reg_type
required_exec_type(const intel_device_info *devinfo, const elk_fs_inst *inst)
{
const brw_reg_type t = get_exec_type(inst);
const bool has_64bit = brw_reg_type_is_floating_point(t) ?
const elk_reg_type t = get_exec_type(inst);
const bool has_64bit = elk_reg_type_is_floating_point(t) ?
devinfo->has_64bit_float : devinfo->has_64bit_int;
switch (inst->opcode) {
case SHADER_OPCODE_SHUFFLE:
case ELK_SHADER_OPCODE_SHUFFLE:
/* IVB has an issue (which we found empirically) where it reads
* two address register components per channel for indirectly
* addressed 64-bit sources.
@@ -148,26 +148,26 @@ namespace {
if ((!devinfo->has_64bit_int ||
devinfo->platform == INTEL_PLATFORM_CHV ||
intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4)
return BRW_REGISTER_TYPE_UD;
return ELK_REGISTER_TYPE_UD;
else if (has_dst_aligned_region_restriction(devinfo, inst))
return brw_int_type(type_sz(t), false);
return elk_int_type(type_sz(t), false);
else
return t;
case SHADER_OPCODE_SEL_EXEC:
case ELK_SHADER_OPCODE_SEL_EXEC:
if ((!has_64bit || devinfo->has_64bit_float_via_math_pipe) &&
type_sz(t) > 4)
return BRW_REGISTER_TYPE_UD;
return ELK_REGISTER_TYPE_UD;
else
return t;
case SHADER_OPCODE_QUAD_SWIZZLE:
case ELK_SHADER_OPCODE_QUAD_SWIZZLE:
if (has_dst_aligned_region_restriction(devinfo, inst))
return brw_int_type(type_sz(t), false);
return elk_int_type(type_sz(t), false);
else
return t;
case SHADER_OPCODE_CLUSTER_BROADCAST:
case ELK_SHADER_OPCODE_CLUSTER_BROADCAST:
/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
*
* "When source or destination datatype is 64b or operation is
@@ -186,19 +186,19 @@ namespace {
if ((!has_64bit || devinfo->verx10 >= 125 ||
devinfo->platform == INTEL_PLATFORM_CHV ||
intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4)
return BRW_REGISTER_TYPE_UD;
return ELK_REGISTER_TYPE_UD;
else
return brw_int_type(type_sz(t), false);
return elk_int_type(type_sz(t), false);
case SHADER_OPCODE_BROADCAST:
case SHADER_OPCODE_MOV_INDIRECT:
case ELK_SHADER_OPCODE_BROADCAST:
case ELK_SHADER_OPCODE_MOV_INDIRECT:
if (((devinfo->verx10 == 70 ||
devinfo->platform == INTEL_PLATFORM_CHV ||
intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) ||
(devinfo->verx10 >= 125 &&
brw_reg_type_is_floating_point(inst->src[0].type)))
return brw_int_type(type_sz(t), false);
elk_reg_type_is_floating_point(inst->src[0].type)))
return elk_int_type(type_sz(t), false);
else
return t;
@@ -213,7 +213,7 @@ namespace {
* single one-dimensional stride.
*/
unsigned
byte_stride(const fs_reg &reg)
byte_stride(const elk_fs_reg &reg)
{
switch (reg.file) {
case BAD_FILE:
@@ -250,11 +250,11 @@ namespace {
* specified for the i-th source region.
*/
bool
has_invalid_src_region(const intel_device_info *devinfo, const fs_inst *inst,
has_invalid_src_region(const intel_device_info *devinfo, const elk_fs_inst *inst,
unsigned i)
{
if (is_send(inst) || inst->is_math() || inst->is_control_source(i) ||
inst->opcode == BRW_OPCODE_DPAS) {
inst->opcode == ELK_OPCODE_DPAS) {
return false;
}
@@ -269,8 +269,8 @@ namespace {
* register. The problem doesn't occur if the stride of the source is 0.
*/
if (devinfo->ver == 8 &&
inst->opcode == BRW_OPCODE_MAD &&
inst->src[i].type == BRW_REGISTER_TYPE_HF &&
inst->opcode == ELK_OPCODE_MAD &&
inst->src[i].type == ELK_REGISTER_TYPE_HF &&
reg_offset(inst->src[i]) % REG_SIZE > 0 &&
inst->src[i].stride != 0) {
return true;
@@ -291,12 +291,12 @@ namespace {
*/
bool
has_invalid_dst_region(const intel_device_info *devinfo,
const fs_inst *inst)
const elk_fs_inst *inst)
{
if (is_send(inst) || inst->is_math()) {
return false;
} else {
const brw_reg_type exec_type = get_exec_type(inst);
const elk_reg_type exec_type = get_exec_type(inst);
const unsigned dst_byte_offset = reg_offset(inst->dst) % (reg_unit(devinfo) * REG_SIZE);
const bool is_narrowing_conversion = !is_byte_raw_mov(inst) &&
type_sz(inst->dst.type) < type_sz(exec_type);
@@ -316,18 +316,18 @@ namespace {
* source or destination modifiers into separate MOV instructions.
*/
unsigned
has_invalid_exec_type(const intel_device_info *devinfo, const fs_inst *inst)
has_invalid_exec_type(const intel_device_info *devinfo, const elk_fs_inst *inst)
{
if (required_exec_type(devinfo, inst) != get_exec_type(inst)) {
switch (inst->opcode) {
case SHADER_OPCODE_SHUFFLE:
case SHADER_OPCODE_QUAD_SWIZZLE:
case SHADER_OPCODE_CLUSTER_BROADCAST:
case SHADER_OPCODE_BROADCAST:
case SHADER_OPCODE_MOV_INDIRECT:
case ELK_SHADER_OPCODE_SHUFFLE:
case ELK_SHADER_OPCODE_QUAD_SWIZZLE:
case ELK_SHADER_OPCODE_CLUSTER_BROADCAST:
case ELK_SHADER_OPCODE_BROADCAST:
case ELK_SHADER_OPCODE_MOV_INDIRECT:
return 0x1;
case SHADER_OPCODE_SEL_EXEC:
case ELK_SHADER_OPCODE_SEL_EXEC:
return 0x3;
default:
@@ -344,7 +344,7 @@ namespace {
*/
bool
has_invalid_src_modifiers(const intel_device_info *devinfo,
const fs_inst *inst, unsigned i)
const elk_fs_inst *inst, unsigned i)
{
return (!inst->can_do_source_mods(devinfo) &&
(inst->src[i].negate || inst->src[i].abs)) ||
@@ -358,12 +358,12 @@ namespace {
* specified for the destination.
*/
bool
has_invalid_conversion(const intel_device_info *devinfo, const fs_inst *inst)
has_invalid_conversion(const intel_device_info *devinfo, const elk_fs_inst *inst)
{
switch (inst->opcode) {
case BRW_OPCODE_MOV:
case ELK_OPCODE_MOV:
return false;
case BRW_OPCODE_SEL:
case ELK_OPCODE_SEL:
return inst->dst.type != get_exec_type(inst);
default:
/* FIXME: We assume the opcodes not explicitly mentioned before just
@@ -379,7 +379,7 @@ namespace {
* Return whether the instruction has unsupported destination modifiers.
*/
bool
has_invalid_dst_modifiers(const intel_device_info *devinfo, const fs_inst *inst)
has_invalid_dst_modifiers(const intel_device_info *devinfo, const elk_fs_inst *inst)
{
return (has_invalid_exec_type(devinfo, inst) &&
(inst->saturate || inst->conditional_mod)) ||
@@ -392,16 +392,16 @@ namespace {
* the comparison result.
*/
bool
has_inconsistent_cmod(const fs_inst *inst)
has_inconsistent_cmod(const elk_fs_inst *inst)
{
return inst->opcode == BRW_OPCODE_SEL ||
inst->opcode == BRW_OPCODE_CSEL ||
inst->opcode == BRW_OPCODE_IF ||
inst->opcode == BRW_OPCODE_WHILE;
return inst->opcode == ELK_OPCODE_SEL ||
inst->opcode == ELK_OPCODE_CSEL ||
inst->opcode == ELK_OPCODE_IF ||
inst->opcode == ELK_OPCODE_WHILE;
}
bool
lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst);
lower_instruction(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst);
}
namespace elk {
@@ -412,17 +412,17 @@ namespace elk {
* MOV instruction prior to the original instruction.
*/
bool
lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i)
lower_src_modifiers(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst, unsigned i)
{
assert(inst->components_read(i) == 1);
assert(v->devinfo->has_integer_dword_mul ||
inst->opcode != BRW_OPCODE_MUL ||
brw_reg_type_is_floating_point(get_exec_type(inst)) ||
inst->opcode != ELK_OPCODE_MUL ||
elk_reg_type_is_floating_point(get_exec_type(inst)) ||
MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4 ||
type_sz(inst->src[i].type) == get_exec_type_size(inst));
const fs_builder ibld(v, block, inst);
const fs_reg tmp = ibld.vgrf(get_exec_type(inst));
const elk_fs_reg tmp = ibld.vgrf(get_exec_type(inst));
lower_instruction(v, block, ibld.MOV(tmp, inst->src[i]));
inst->src[i] = tmp;
@@ -440,10 +440,10 @@ namespace {
* instruction.
*/
bool
lower_dst_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst)
lower_dst_modifiers(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst)
{
const fs_builder ibld(v, block, inst);
const brw_reg_type type = get_exec_type(inst);
const elk_reg_type type = get_exec_type(inst);
/* Not strictly necessary, but if possible use a temporary with the same
* channel alignment as the current destination in order to avoid
* violating the restrictions enforced later on by lower_src_region()
@@ -453,16 +453,16 @@ namespace {
const unsigned stride =
type_sz(inst->dst.type) * inst->dst.stride <= type_sz(type) ? 1 :
type_sz(inst->dst.type) * inst->dst.stride / type_sz(type);
fs_reg tmp = ibld.vgrf(type, stride);
elk_fs_reg tmp = ibld.vgrf(type, stride);
ibld.UNDEF(tmp);
tmp = horiz_stride(tmp, stride);
/* Emit a MOV taking care of all the destination modifiers. */
fs_inst *mov = ibld.at(block, inst->next).MOV(inst->dst, tmp);
elk_fs_inst *mov = ibld.at(block, inst->next).MOV(inst->dst, tmp);
mov->saturate = inst->saturate;
if (!has_inconsistent_cmod(inst))
mov->conditional_mod = inst->conditional_mod;
if (inst->opcode != BRW_OPCODE_SEL) {
if (inst->opcode != ELK_OPCODE_SEL) {
mov->predicate = inst->predicate;
mov->predicate_inverse = inst->predicate_inverse;
}
@@ -477,7 +477,7 @@ namespace {
inst->size_written = inst->dst.component_size(inst->exec_size);
inst->saturate = false;
if (!has_inconsistent_cmod(inst))
inst->conditional_mod = BRW_CONDITIONAL_NONE;
inst->conditional_mod = ELK_CONDITIONAL_NONE;
assert(!inst->flags_written(v->devinfo) || !mov->predicate);
return true;
@@ -489,24 +489,24 @@ namespace {
* copies into a temporary with the same channel layout as the destination.
*/
bool
lower_src_region(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i)
lower_src_region(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst, unsigned i)
{
assert(inst->components_read(i) == 1);
const fs_builder ibld(v, block, inst);
const unsigned stride = type_sz(inst->dst.type) * inst->dst.stride /
type_sz(inst->src[i].type);
assert(stride > 0);
fs_reg tmp = ibld.vgrf(inst->src[i].type, stride);
elk_fs_reg tmp = ibld.vgrf(inst->src[i].type, stride);
ibld.UNDEF(tmp);
tmp = horiz_stride(tmp, stride);
/* Emit a series of 32-bit integer copies with any source modifiers
* cleaned up (because their semantics are dependent on the type).
*/
const brw_reg_type raw_type = brw_int_type(MIN2(type_sz(tmp.type), 4),
const elk_reg_type raw_type = elk_int_type(MIN2(type_sz(tmp.type), 4),
false);
const unsigned n = type_sz(tmp.type) / type_sz(raw_type);
fs_reg raw_src = inst->src[i];
elk_fs_reg raw_src = inst->src[i];
raw_src.negate = false;
raw_src.abs = false;
@@ -516,7 +516,7 @@ namespace {
/* Point the original instruction at the temporary, making sure to keep
* any source modifiers in the instruction.
*/
fs_reg lower_src = tmp;
elk_fs_reg lower_src = tmp;
lower_src.negate = inst->src[i].negate;
lower_src.abs = inst->src[i].abs;
inst->src[i] = lower_src;
@@ -531,32 +531,32 @@ namespace {
* sources.
*/
bool
lower_dst_region(fs_visitor *v, bblock_t *block, fs_inst *inst)
lower_dst_region(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst)
{
/* We cannot replace the result of an integer multiply which writes the
* accumulator because MUL+MACH pairs act on the accumulator as a 66-bit
* value whereas the MOV will act on only 32 or 33 bits of the
* accumulator.
*/
assert(inst->opcode != BRW_OPCODE_MUL || !inst->dst.is_accumulator() ||
brw_reg_type_is_floating_point(inst->dst.type));
assert(inst->opcode != ELK_OPCODE_MUL || !inst->dst.is_accumulator() ||
elk_reg_type_is_floating_point(inst->dst.type));
const fs_builder ibld(v, block, inst);
const unsigned stride = required_dst_byte_stride(inst) /
type_sz(inst->dst.type);
assert(stride > 0);
fs_reg tmp = ibld.vgrf(inst->dst.type, stride);
elk_fs_reg tmp = ibld.vgrf(inst->dst.type, stride);
ibld.UNDEF(tmp);
tmp = horiz_stride(tmp, stride);
/* Emit a series of 32-bit integer copies from the temporary into the
* original destination.
*/
const brw_reg_type raw_type = brw_int_type(MIN2(type_sz(tmp.type), 4),
const elk_reg_type raw_type = elk_int_type(MIN2(type_sz(tmp.type), 4),
false);
const unsigned n = type_sz(tmp.type) / type_sz(raw_type);
if (inst->predicate && inst->opcode != BRW_OPCODE_SEL) {
if (inst->predicate && inst->opcode != ELK_OPCODE_SEL) {
/* Note that in general we cannot simply predicate the copies on the
* same flag register as the original instruction, since it may have
* been overwritten by the instruction itself. Instead initialize
@@ -589,20 +589,20 @@ namespace {
* where the execution type of an instruction is unsupported.
*/
bool
lower_exec_type(fs_visitor *v, bblock_t *block, fs_inst *inst)
lower_exec_type(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst)
{
assert(inst->dst.type == get_exec_type(inst));
const unsigned mask = has_invalid_exec_type(v->devinfo, inst);
const brw_reg_type raw_type = required_exec_type(v->devinfo, inst);
const elk_reg_type raw_type = required_exec_type(v->devinfo, inst);
const unsigned n = get_exec_type_size(inst) / type_sz(raw_type);
const fs_builder ibld(v, block, inst);
fs_reg tmp = ibld.vgrf(inst->dst.type, inst->dst.stride);
elk_fs_reg tmp = ibld.vgrf(inst->dst.type, inst->dst.stride);
ibld.UNDEF(tmp);
tmp = horiz_stride(tmp, inst->dst.stride);
for (unsigned j = 0; j < n; j++) {
fs_inst sub_inst = *inst;
elk_fs_inst sub_inst = *inst;
for (unsigned i = 0; i < inst->sources; i++) {
if (mask & (1u << i)) {
@@ -617,9 +617,9 @@ namespace {
assert(!sub_inst.flags_written(v->devinfo) && !sub_inst.saturate);
ibld.emit(sub_inst);
fs_inst *mov = ibld.MOV(subscript(inst->dst, raw_type, j),
elk_fs_inst *mov = ibld.MOV(subscript(inst->dst, raw_type, j),
subscript(tmp, raw_type, j));
if (inst->opcode != BRW_OPCODE_SEL) {
if (inst->opcode != ELK_OPCODE_SEL) {
mov->predicate = inst->predicate;
mov->predicate_inverse = inst->predicate_inverse;
}
@@ -636,7 +636,7 @@ namespace {
* instruction.
*/
bool
lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst)
lower_instruction(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst)
{
const intel_device_info *devinfo = v->devinfo;
bool progress = false;
@@ -663,11 +663,11 @@ namespace {
}
bool
fs_visitor::lower_regioning()
elk_fs_visitor::lower_regioning()
{
bool progress = false;
foreach_block_and_inst_safe(block, fs_inst, inst, cfg)
foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg)
progress |= lower_instruction(this, block, inst);
if (progress)
src/intel/compiler/elk/elk_fs_nir.cpp
+1535 -1535
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_fs_reg_allocate.cpp
+135 -135
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@@ -38,7 +38,7 @@ using namespace elk;
static void
assign_reg(const struct intel_device_info *devinfo,
unsigned *reg_hw_locations, fs_reg *reg)
unsigned *reg_hw_locations, elk_fs_reg *reg)
{
if (reg->file == VGRF) {
reg->nr = reg_unit(devinfo) * reg_hw_locations[reg->nr] + reg->offset / REG_SIZE;
@@ -47,7 +47,7 @@ assign_reg(const struct intel_device_info *devinfo,
}
void
fs_visitor::assign_regs_trivial()
elk_fs_visitor::assign_regs_trivial()
{
unsigned hw_reg_mapping[this->alloc.count + 1];
unsigned i;
@@ -62,7 +62,7 @@ fs_visitor::assign_regs_trivial()
}
this->grf_used = hw_reg_mapping[this->alloc.count];
foreach_block_and_inst(block, fs_inst, inst, cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, cfg) {
assign_reg(devinfo, hw_reg_mapping, &inst->dst);
for (i = 0; i < inst->sources; i++) {
assign_reg(devinfo, hw_reg_mapping, &inst->src[i]);
@@ -88,10 +88,10 @@ aligned_bary_size(unsigned dispatch_width)
}
static void
brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
elk_alloc_reg_set(struct elk_compiler *compiler, int dispatch_width)
{
const struct intel_device_info *devinfo = compiler->devinfo;
int base_reg_count = BRW_MAX_GRF;
int base_reg_count = ELK_MAX_GRF;
const int index = util_logbase2(dispatch_width / 8);
if (dispatch_width > 8 && devinfo->ver >= 7) {
@@ -123,7 +123,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
for (unsigned i = 0; i < REG_CLASS_COUNT; i++)
class_sizes[i] = i + 1;
struct ra_regs *regs = ra_alloc_reg_set(compiler, BRW_MAX_GRF, false);
struct ra_regs *regs = ra_alloc_reg_set(compiler, ELK_MAX_GRF, false);
if (devinfo->ver >= 6)
ra_set_allocate_round_robin(regs);
struct ra_class **classes = ralloc_array(compiler, struct ra_class *,
@@ -178,17 +178,17 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
}
void
brw_fs_alloc_reg_sets(struct brw_compiler *compiler)
elk_fs_alloc_reg_sets(struct elk_compiler *compiler)
{
brw_alloc_reg_set(compiler, 8);
brw_alloc_reg_set(compiler, 16);
brw_alloc_reg_set(compiler, 32);
elk_alloc_reg_set(compiler, 8);
elk_alloc_reg_set(compiler, 16);
elk_alloc_reg_set(compiler, 32);
}
static int
count_to_loop_end(const bblock_t *block)
count_to_loop_end(const elk_bblock_t *block)
{
if (block->end()->opcode == BRW_OPCODE_WHILE)
if (block->end()->opcode == ELK_OPCODE_WHILE)
return block->end_ip;
int depth = 1;
@@ -198,9 +198,9 @@ count_to_loop_end(const bblock_t *block)
for (block = block->next();
depth > 0;
block = block->next()) {
if (block->start()->opcode == BRW_OPCODE_DO)
if (block->start()->opcode == ELK_OPCODE_DO)
depth++;
if (block->end()->opcode == BRW_OPCODE_WHILE) {
if (block->end()->opcode == ELK_OPCODE_WHILE) {
depth--;
if (depth == 0)
return block->end_ip;
@@ -209,7 +209,7 @@ count_to_loop_end(const bblock_t *block)
unreachable("not reached");
}
void fs_visitor::calculate_payload_ranges(unsigned payload_node_count,
void elk_fs_visitor::calculate_payload_ranges(unsigned payload_node_count,
int *payload_last_use_ip) const
{
int loop_depth = 0;
@@ -219,9 +219,9 @@ void fs_visitor::calculate_payload_ranges(unsigned payload_node_count,
payload_last_use_ip[i] = -1;
int ip = 0;
foreach_block_and_inst(block, fs_inst, inst, cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, cfg) {
switch (inst->opcode) {
case BRW_OPCODE_DO:
case ELK_OPCODE_DO:
loop_depth++;
/* Since payload regs are deffed only at the start of the shader
@@ -232,7 +232,7 @@ void fs_visitor::calculate_payload_ranges(unsigned payload_node_count,
if (loop_depth == 1)
loop_end_ip = count_to_loop_end(block);
break;
case BRW_OPCODE_WHILE:
case ELK_OPCODE_WHILE:
loop_depth--;
break;
default:
@@ -280,7 +280,7 @@ void fs_visitor::calculate_payload_ranges(unsigned payload_node_count,
/* Special case instructions which have extra implied registers used. */
switch (inst->opcode) {
case CS_OPCODE_CS_TERMINATE:
case ELK_CS_OPCODE_CS_TERMINATE:
payload_last_use_ip[0] = use_ip;
break;
@@ -302,9 +302,9 @@ void fs_visitor::calculate_payload_ranges(unsigned payload_node_count,
}
}
class fs_reg_alloc {
class elk_fs_reg_alloc {
public:
fs_reg_alloc(fs_visitor *fs):
elk_fs_reg_alloc(elk_fs_visitor *fs):
fs(fs), devinfo(fs->devinfo), compiler(fs->compiler),
live(fs->live_analysis.require()), g(NULL),
have_spill_costs(false)
@@ -345,7 +345,7 @@ public:
spill_node_count = 0;
}
~fs_reg_alloc()
~elk_fs_reg_alloc()
{
ralloc_free(mem_ctx);
}
@@ -355,31 +355,31 @@ public:
private:
void setup_live_interference(unsigned node,
int node_start_ip, int node_end_ip);
void setup_inst_interference(const fs_inst *inst);
void setup_inst_interference(const elk_fs_inst *inst);
void build_interference_graph(bool allow_spilling);
void discard_interference_graph();
fs_reg build_lane_offsets(const fs_builder &bld,
elk_fs_reg build_lane_offsets(const fs_builder &bld,
uint32_t spill_offset, int ip);
fs_reg build_single_offset(const fs_builder &bld,
elk_fs_reg build_single_offset(const fs_builder &bld,
uint32_t spill_offset, int ip);
void emit_unspill(const fs_builder &bld, struct shader_stats *stats,
fs_reg dst, uint32_t spill_offset, unsigned count, int ip);
elk_fs_reg dst, uint32_t spill_offset, unsigned count, int ip);
void emit_spill(const fs_builder &bld, struct shader_stats *stats,
fs_reg src, uint32_t spill_offset, unsigned count, int ip);
elk_fs_reg src, uint32_t spill_offset, unsigned count, int ip);
void set_spill_costs();
int choose_spill_reg();
fs_reg alloc_scratch_header();
fs_reg alloc_spill_reg(unsigned size, int ip);
elk_fs_reg alloc_scratch_header();
elk_fs_reg alloc_spill_reg(unsigned size, int ip);
void spill_reg(unsigned spill_reg);
void *mem_ctx;
fs_visitor *fs;
elk_fs_visitor *fs;
const intel_device_info *devinfo;
const brw_compiler *compiler;
const elk_compiler *compiler;
const fs_live_variables &live;
int live_instr_count;
@@ -407,7 +407,7 @@ private:
int spill_vgrf_ip_alloc;
int spill_node_count;
fs_reg scratch_header;
elk_fs_reg scratch_header;
};
/**
@@ -419,18 +419,18 @@ private:
* contents.
*/
static void
get_used_mrfs(const fs_visitor *v, bool *mrf_used)
get_used_mrfs(const elk_fs_visitor *v, bool *mrf_used)
{
int reg_width = v->dispatch_width / 8;
memset(mrf_used, 0, BRW_MAX_MRF(v->devinfo->ver) * sizeof(bool));
memset(mrf_used, 0, ELK_MAX_MRF(v->devinfo->ver) * sizeof(bool));
foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) {
if (inst->dst.file == MRF) {
int reg = inst->dst.nr & ~BRW_MRF_COMPR4;
int reg = inst->dst.nr & ~ELK_MRF_COMPR4;
mrf_used[reg] = true;
if (reg_width == 2) {
if (inst->dst.nr & BRW_MRF_COMPR4) {
if (inst->dst.nr & ELK_MRF_COMPR4) {
mrf_used[reg + 4] = true;
} else {
mrf_used[reg + 1] = true;
@@ -463,7 +463,7 @@ namespace {
* into multiple (force_writemask_all) scratch messages.
*/
unsigned
spill_max_size(const backend_shader *s)
spill_max_size(const elk_backend_shader *s)
{
/* LSC is limited to SIMD16 sends */
if (s->devinfo->has_lsc)
@@ -475,26 +475,26 @@ namespace {
* scratch write header).
*/
/* FINISHME - The shader's dispatch width probably belongs in
* backend_shader (or some nonexistent fs_shader class?)
* elk_backend_shader (or some nonexistent fs_shader class?)
* rather than in the visitor class.
*/
return static_cast<const fs_visitor *>(s)->dispatch_width / 8;
return static_cast<const elk_fs_visitor *>(s)->dispatch_width / 8;
}
/**
* First MRF register available for spilling.
*/
unsigned
spill_base_mrf(const backend_shader *s)
spill_base_mrf(const elk_backend_shader *s)
{
/* We don't use the MRF hack on Gfx9+ */
assert(s->devinfo->ver < 9);
return BRW_MAX_MRF(s->devinfo->ver) - spill_max_size(s) - 1;
return ELK_MAX_MRF(s->devinfo->ver) - spill_max_size(s) - 1;
}
}
void
fs_reg_alloc::setup_live_interference(unsigned node,
elk_fs_reg_alloc::setup_live_interference(unsigned node,
int node_start_ip, int node_end_ip)
{
/* Mark any virtual grf that is live between the start of the program and
@@ -516,7 +516,7 @@ fs_reg_alloc::setup_live_interference(unsigned node,
* MRF registers.
*/
if (first_mrf_hack_node >= 0) {
for (int i = spill_base_mrf(fs); i < BRW_MAX_MRF(devinfo->ver); i++)
for (int i = spill_base_mrf(fs); i < ELK_MAX_MRF(devinfo->ver); i++)
ra_add_node_interference(g, node, first_mrf_hack_node + i);
}
@@ -538,7 +538,7 @@ fs_reg_alloc::setup_live_interference(unsigned node,
}
void
fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
elk_fs_reg_alloc::setup_inst_interference(const elk_fs_inst *inst)
{
/* Certain instructions can't safely use the same register for their
* sources and destination. Add interference.
@@ -597,8 +597,8 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
* message as source. So as we will have an overlap for sure, we create
* an interference between destination and grf127.
*/
if ((inst->opcode == SHADER_OPCODE_GFX7_SCRATCH_READ ||
inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_READ) &&
if ((inst->opcode == ELK_SHADER_OPCODE_GFX7_SCRATCH_READ ||
inst->opcode == ELK_SHADER_OPCODE_GFX4_SCRATCH_READ) &&
inst->dst.file == VGRF)
ra_add_node_interference(g, first_vgrf_node + inst->dst.nr,
grf127_send_hack_node);
@@ -616,7 +616,7 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
* interference here.
*/
if (devinfo->ver >= 9) {
if (inst->opcode == SHADER_OPCODE_SEND && inst->ex_mlen > 0 &&
if (inst->opcode == ELK_SHADER_OPCODE_SEND && inst->ex_mlen > 0 &&
inst->src[2].file == VGRF && inst->src[3].file == VGRF &&
inst->src[2].nr != inst->src[3].nr)
ra_add_node_interference(g, first_vgrf_node + inst->src[2].nr,
@@ -633,17 +633,17 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
* register that works.
*/
if (inst->eot) {
const int vgrf = inst->opcode == SHADER_OPCODE_SEND ?
const int vgrf = inst->opcode == ELK_SHADER_OPCODE_SEND ?
inst->src[2].nr : inst->src[0].nr;
const int size = DIV_ROUND_UP(fs->alloc.sizes[vgrf], reg_unit(devinfo));
int reg = BRW_MAX_GRF - size;
int reg = ELK_MAX_GRF - size;
if (first_mrf_hack_node >= 0) {
/* If something happened to spill, we want to push the EOT send
* register early enough in the register file that we don't
* conflict with any used MRF hack registers.
*/
reg -= BRW_MAX_MRF(devinfo->ver) - spill_base_mrf(fs);
reg -= ELK_MAX_MRF(devinfo->ver) - spill_base_mrf(fs);
} else if (grf127_send_hack_node >= 0) {
/* Avoid r127 which might be unusable if the node was previously
* written by a SIMD8 SEND message with source/destination overlap.
@@ -662,7 +662,7 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
}
void
fs_reg_alloc::build_interference_graph(bool allow_spilling)
elk_fs_reg_alloc::build_interference_graph(bool allow_spilling)
{
/* Compute the RA node layout */
node_count = 0;
@@ -670,7 +670,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
node_count += payload_node_count;
if (devinfo->ver >= 7 && devinfo->ver < 9 && allow_spilling) {
first_mrf_hack_node = node_count;
node_count += BRW_MAX_GRF - GFX7_MRF_HACK_START;
node_count += ELK_MAX_GRF - GFX7_MRF_HACK_START;
} else {
first_mrf_hack_node = -1;
}
@@ -708,7 +708,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
* The alternative would be to have per-physical-register classes,
* which would just be silly.
*/
for (int i = 0; i < BRW_MAX_MRF(devinfo->ver); i++) {
for (int i = 0; i < ELK_MAX_MRF(devinfo->ver); i++) {
ra_set_node_reg(g, first_mrf_hack_node + i,
GFX7_MRF_HACK_START + i);
}
@@ -733,8 +733,8 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
* special register class aligned_bary_class to handle this case.
*/
if (compiler->fs_reg_sets[rsi].aligned_bary_class) {
foreach_block_and_inst(block, fs_inst, inst, fs->cfg) {
if (inst->opcode == FS_OPCODE_LINTERP && inst->src[0].file == VGRF &&
foreach_block_and_inst(block, elk_fs_inst, inst, fs->cfg) {
if (inst->opcode == ELK_FS_OPCODE_LINTERP && inst->src[0].file == VGRF &&
fs->alloc.sizes[inst->src[0].nr] ==
aligned_bary_size(fs->dispatch_width)) {
ra_set_node_class(g, first_vgrf_node + inst->src[0].nr,
@@ -752,29 +752,29 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
/* Add interference based on the instructions in which a register is used.
*/
foreach_block_and_inst(block, fs_inst, inst, fs->cfg)
foreach_block_and_inst(block, elk_fs_inst, inst, fs->cfg)
setup_inst_interference(inst);
}
void
fs_reg_alloc::discard_interference_graph()
elk_fs_reg_alloc::discard_interference_graph()
{
ralloc_free(g);
g = NULL;
have_spill_costs = false;
}
fs_reg
fs_reg_alloc::build_single_offset(const fs_builder &bld, uint32_t spill_offset, int ip)
elk_fs_reg
elk_fs_reg_alloc::build_single_offset(const fs_builder &bld, uint32_t spill_offset, int ip)
{
fs_reg offset = retype(alloc_spill_reg(1, ip), BRW_REGISTER_TYPE_UD);
fs_inst *inst = bld.MOV(offset, brw_imm_ud(spill_offset));
elk_fs_reg offset = retype(alloc_spill_reg(1, ip), ELK_REGISTER_TYPE_UD);
elk_fs_inst *inst = bld.MOV(offset, elk_imm_ud(spill_offset));
_mesa_set_add(spill_insts, inst);
return offset;
}
fs_reg
fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, int ip)
elk_fs_reg
elk_fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, int ip)
{
/* LSC messages are limited to SIMD16 */
assert(bld.dispatch_width() <= 16);
@@ -782,14 +782,14 @@ fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, i
const fs_builder ubld = bld.exec_all();
const unsigned reg_count = ubld.dispatch_width() / 8;
fs_reg offset = retype(alloc_spill_reg(reg_count, ip), BRW_REGISTER_TYPE_UD);
fs_inst *inst;
elk_fs_reg offset = retype(alloc_spill_reg(reg_count, ip), ELK_REGISTER_TYPE_UD);
elk_fs_inst *inst;
/* Build an offset per lane in SIMD8 */
inst = ubld.group(8, 0).MOV(retype(offset, BRW_REGISTER_TYPE_UW),
brw_imm_uv(0x76543210));
inst = ubld.group(8, 0).MOV(retype(offset, ELK_REGISTER_TYPE_UW),
elk_imm_uv(0x76543210));
_mesa_set_add(spill_insts, inst);
inst = ubld.group(8, 0).MOV(offset, retype(offset, BRW_REGISTER_TYPE_UW));
inst = ubld.group(8, 0).MOV(offset, retype(offset, ELK_REGISTER_TYPE_UW));
_mesa_set_add(spill_insts, inst);
/* Build offsets in the upper 8 lanes of SIMD16 */
@@ -797,25 +797,25 @@ fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, i
inst = ubld.group(8, 0).ADD(
byte_offset(offset, REG_SIZE),
byte_offset(offset, 0),
brw_imm_ud(8));
elk_imm_ud(8));
_mesa_set_add(spill_insts, inst);
}
/* Make the offset a dword */
inst = ubld.SHL(offset, offset, brw_imm_ud(2));
inst = ubld.SHL(offset, offset, elk_imm_ud(2));
_mesa_set_add(spill_insts, inst);
/* Add the base offset */
inst = ubld.ADD(offset, offset, brw_imm_ud(spill_offset));
inst = ubld.ADD(offset, offset, elk_imm_ud(spill_offset));
_mesa_set_add(spill_insts, inst);
return offset;
}
void
fs_reg_alloc::emit_unspill(const fs_builder &bld,
elk_fs_reg_alloc::emit_unspill(const fs_builder &bld,
struct shader_stats *stats,
fs_reg dst,
elk_fs_reg dst,
uint32_t spill_offset, unsigned count, int ip)
{
const intel_device_info *devinfo = bld.shader->devinfo;
@@ -826,14 +826,14 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld,
for (unsigned i = 0; i < count / reg_size; i++) {
++stats->fill_count;
fs_inst *unspill_inst;
elk_fs_inst *unspill_inst;
if (devinfo->verx10 >= 125) {
/* LSC is limited to SIMD16 load/store but we can load more using
* transpose messages.
*/
const bool use_transpose = bld.dispatch_width() > 16;
const fs_builder ubld = use_transpose ? bld.exec_all().group(1, 0) : bld;
fs_reg offset;
elk_fs_reg offset;
if (use_transpose) {
offset = build_single_offset(ubld, spill_offset, ip);
} else {
@@ -844,14 +844,14 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld,
* register. That way we don't need to burn an additional register
* for register allocation spill/fill.
*/
fs_reg srcs[] = {
brw_imm_ud(0), /* desc */
brw_imm_ud(0), /* ex_desc */
elk_fs_reg srcs[] = {
elk_imm_ud(0), /* desc */
elk_imm_ud(0), /* ex_desc */
offset, /* payload */
fs_reg(), /* payload2 */
elk_fs_reg(), /* payload2 */
};
unspill_inst = ubld.emit(SHADER_OPCODE_SEND, dst,
unspill_inst = ubld.emit(ELK_SHADER_OPCODE_SEND, dst,
srcs, ARRAY_SIZE(srcs));
unspill_inst->sfid = GFX12_SFID_UGM;
unspill_inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD,
@@ -874,18 +874,18 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld,
unspill_inst->send_is_volatile = true;
unspill_inst->send_ex_desc_scratch = true;
} else if (devinfo->ver >= 9) {
fs_reg header = this->scratch_header;
elk_fs_reg header = this->scratch_header;
fs_builder ubld = bld.exec_all().group(1, 0);
assert(spill_offset % 16 == 0);
unspill_inst = ubld.MOV(component(header, 2),
brw_imm_ud(spill_offset / 16));
elk_imm_ud(spill_offset / 16));
_mesa_set_add(spill_insts, unspill_inst);
const unsigned bti = GFX8_BTI_STATELESS_NON_COHERENT;
const fs_reg ex_desc = brw_imm_ud(0);
const elk_fs_reg ex_desc = elk_imm_ud(0);
fs_reg srcs[] = { brw_imm_ud(0), ex_desc, header };
unspill_inst = bld.emit(SHADER_OPCODE_SEND, dst,
elk_fs_reg srcs[] = { elk_imm_ud(0), ex_desc, header };
unspill_inst = bld.emit(ELK_SHADER_OPCODE_SEND, dst,
srcs, ARRAY_SIZE(srcs));
unspill_inst->mlen = 1;
unspill_inst->header_size = 1;
@@ -894,9 +894,9 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld,
unspill_inst->send_is_volatile = true;
unspill_inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
unspill_inst->desc =
brw_dp_desc(devinfo, bti,
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8));
elk_dp_desc(devinfo, bti,
ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ,
ELK_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8));
} else if (devinfo->ver >= 7 && spill_offset < (1 << 12) * REG_SIZE) {
/* The Gfx7 descriptor-based offset is 12 bits of HWORD units.
* Because the Gfx7-style scratch block read is hardwired to BTI 255,
@@ -905,10 +905,10 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld,
* the address as part of the message header, so we're better off
* using plain old oword block reads.
*/
unspill_inst = bld.emit(SHADER_OPCODE_GFX7_SCRATCH_READ, dst);
unspill_inst = bld.emit(ELK_SHADER_OPCODE_GFX7_SCRATCH_READ, dst);
unspill_inst->offset = spill_offset;
} else {
unspill_inst = bld.emit(SHADER_OPCODE_GFX4_SCRATCH_READ, dst);
unspill_inst = bld.emit(ELK_SHADER_OPCODE_GFX4_SCRATCH_READ, dst);
unspill_inst->offset = spill_offset;
unspill_inst->base_mrf = spill_base_mrf(bld.shader);
unspill_inst->mlen = 1; /* header contains offset */
@@ -921,9 +921,9 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld,
}
void
fs_reg_alloc::emit_spill(const fs_builder &bld,
elk_fs_reg_alloc::emit_spill(const fs_builder &bld,
struct shader_stats *stats,
fs_reg src,
elk_fs_reg src,
uint32_t spill_offset, unsigned count, int ip)
{
const intel_device_info *devinfo = bld.shader->devinfo;
@@ -934,21 +934,21 @@ fs_reg_alloc::emit_spill(const fs_builder &bld,
for (unsigned i = 0; i < count / reg_size; i++) {
++stats->spill_count;
fs_inst *spill_inst;
elk_fs_inst *spill_inst;
if (devinfo->verx10 >= 125) {
fs_reg offset = build_lane_offsets(bld, spill_offset, ip);
elk_fs_reg offset = build_lane_offsets(bld, spill_offset, ip);
/* We leave the extended descriptor empty and flag the instruction
* relocate the extended descriptor. That way the surface offset is
* directly put into the instruction and we don't need to use a
* register to hold it.
*/
fs_reg srcs[] = {
brw_imm_ud(0), /* desc */
brw_imm_ud(0), /* ex_desc */
elk_fs_reg srcs[] = {
elk_imm_ud(0), /* desc */
elk_imm_ud(0), /* ex_desc */
offset, /* payload */
src, /* payload2 */
};
spill_inst = bld.emit(SHADER_OPCODE_SEND, bld.null_reg_f(),
spill_inst = bld.emit(ELK_SHADER_OPCODE_SEND, bld.null_reg_f(),
srcs, ARRAY_SIZE(srcs));
spill_inst->sfid = GFX12_SFID_UGM;
spill_inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE,
@@ -969,18 +969,18 @@ fs_reg_alloc::emit_spill(const fs_builder &bld,
spill_inst->send_is_volatile = false;
spill_inst->send_ex_desc_scratch = true;
} else if (devinfo->ver >= 9) {
fs_reg header = this->scratch_header;
elk_fs_reg header = this->scratch_header;
fs_builder ubld = bld.exec_all().group(1, 0);
assert(spill_offset % 16 == 0);
spill_inst = ubld.MOV(component(header, 2),
brw_imm_ud(spill_offset / 16));
elk_imm_ud(spill_offset / 16));
_mesa_set_add(spill_insts, spill_inst);
const unsigned bti = GFX8_BTI_STATELESS_NON_COHERENT;
const fs_reg ex_desc = brw_imm_ud(0);
const elk_fs_reg ex_desc = elk_imm_ud(0);
fs_reg srcs[] = { brw_imm_ud(0), ex_desc, header, src };
spill_inst = bld.emit(SHADER_OPCODE_SEND, bld.null_reg_f(),
elk_fs_reg srcs[] = { elk_imm_ud(0), ex_desc, header, src };
spill_inst = bld.emit(ELK_SHADER_OPCODE_SEND, bld.null_reg_f(),
srcs, ARRAY_SIZE(srcs));
spill_inst->mlen = 1;
spill_inst->ex_mlen = reg_size;
@@ -990,11 +990,11 @@ fs_reg_alloc::emit_spill(const fs_builder &bld,
spill_inst->send_is_volatile = false;
spill_inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE;
spill_inst->desc =
brw_dp_desc(devinfo, bti,
elk_dp_desc(devinfo, bti,
GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE,
BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8));
ELK_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8));
} else {
spill_inst = bld.emit(SHADER_OPCODE_GFX4_SCRATCH_WRITE,
spill_inst = bld.emit(ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE,
bld.null_reg_f(), src);
spill_inst->offset = spill_offset;
spill_inst->mlen = 1 + reg_size; /* header, value */
@@ -1008,7 +1008,7 @@ fs_reg_alloc::emit_spill(const fs_builder &bld,
}
void
fs_reg_alloc::set_spill_costs()
elk_fs_reg_alloc::set_spill_costs()
{
float block_scale = 1.0;
float spill_costs[fs->alloc.count];
@@ -1023,7 +1023,7 @@ fs_reg_alloc::set_spill_costs()
* spill/unspill we'll have to do, and guess that the insides of
* loops run 10 times.
*/
foreach_block_and_inst(block, fs_inst, inst, fs->cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, fs->cfg) {
for (unsigned int i = 0; i < inst->sources; i++) {
if (inst->src[i].file == VGRF)
spill_costs[inst->src[i].nr] += regs_read(inst, i) * block_scale;
@@ -1044,20 +1044,20 @@ fs_reg_alloc::set_spill_costs()
switch (inst->opcode) {
case BRW_OPCODE_DO:
case ELK_OPCODE_DO:
block_scale *= 10;
break;
case BRW_OPCODE_WHILE:
case ELK_OPCODE_WHILE:
block_scale /= 10;
break;
case BRW_OPCODE_IF:
case BRW_OPCODE_IFF:
case ELK_OPCODE_IF:
case ELK_OPCODE_IFF:
block_scale *= 0.5;
break;
case BRW_OPCODE_ENDIF:
case ELK_OPCODE_ENDIF:
block_scale /= 0.5;
break;
@@ -1095,7 +1095,7 @@ fs_reg_alloc::set_spill_costs()
}
int
fs_reg_alloc::choose_spill_reg()
elk_fs_reg_alloc::choose_spill_reg()
{
if (!have_spill_costs)
set_spill_costs();
@@ -1108,8 +1108,8 @@ fs_reg_alloc::choose_spill_reg()
return node - first_vgrf_node;
}
fs_reg
fs_reg_alloc::alloc_scratch_header()
elk_fs_reg
elk_fs_reg_alloc::alloc_scratch_header()
{
int vgrf = fs->alloc.allocate(1);
assert(first_vgrf_node + vgrf == scratch_header_node);
@@ -1118,11 +1118,11 @@ fs_reg_alloc::alloc_scratch_header()
setup_live_interference(scratch_header_node, 0, INT_MAX);
return fs_reg(VGRF, vgrf, BRW_REGISTER_TYPE_UD);
return elk_fs_reg(VGRF, vgrf, ELK_REGISTER_TYPE_UD);
}
fs_reg
fs_reg_alloc::alloc_spill_reg(unsigned size, int ip)
elk_fs_reg
elk_fs_reg_alloc::alloc_spill_reg(unsigned size, int ip)
{
int vgrf = fs->alloc.allocate(ALIGN(size, reg_unit(devinfo)));
int class_idx = DIV_ROUND_UP(size, reg_unit(devinfo)) - 1;
@@ -1151,11 +1151,11 @@ fs_reg_alloc::alloc_spill_reg(unsigned size, int ip)
}
spill_vgrf_ip[spill_node_count++] = ip;
return fs_reg(VGRF, vgrf);
return elk_fs_reg(VGRF, vgrf);
}
void
fs_reg_alloc::spill_reg(unsigned spill_reg)
elk_fs_reg_alloc::spill_reg(unsigned spill_reg)
{
int size = fs->alloc.sizes[spill_reg];
unsigned int spill_offset = fs->last_scratch;
@@ -1176,14 +1176,14 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
fs_builder ubld = fs_builder(fs, 8).exec_all().at(
fs->cfg->first_block(), fs->cfg->first_block()->start());
fs_inst *inst = ubld.emit(SHADER_OPCODE_SCRATCH_HEADER,
elk_fs_inst *inst = ubld.emit(ELK_SHADER_OPCODE_SCRATCH_HEADER,
this->scratch_header);
_mesa_set_add(spill_insts, inst);
} else {
bool mrf_used[BRW_MAX_MRF(devinfo->ver)];
bool mrf_used[ELK_MAX_MRF(devinfo->ver)];
get_used_mrfs(fs, mrf_used);
for (int i = spill_base_mrf(fs); i < BRW_MAX_MRF(devinfo->ver); i++) {
for (int i = spill_base_mrf(fs); i < ELK_MAX_MRF(devinfo->ver); i++) {
if (mrf_used[i]) {
fs->fail("Register spilling not supported with m%d used", i);
return;
@@ -1208,7 +1208,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
* could just spill/unspill the GRF being accessed.
*/
int ip = 0;
foreach_block_and_inst (block, fs_inst, inst, fs->cfg) {
foreach_block_and_inst (block, elk_fs_inst, inst, fs->cfg) {
const fs_builder ibld = fs_builder(fs, block, inst);
exec_node *before = inst->prev;
exec_node *after = inst->next;
@@ -1219,7 +1219,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
int count = regs_read(inst, i);
int subset_spill_offset = spill_offset +
ROUND_DOWN_TO(inst->src[i].offset, REG_SIZE);
fs_reg unspill_dst = alloc_spill_reg(count, ip);
elk_fs_reg unspill_dst = alloc_spill_reg(count, ip);
inst->src[i].nr = unspill_dst.nr;
inst->src[i].offset %= REG_SIZE;
@@ -1245,10 +1245,10 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
if (inst->dst.file == VGRF &&
inst->dst.nr == spill_reg &&
inst->opcode != SHADER_OPCODE_UNDEF) {
inst->opcode != ELK_SHADER_OPCODE_UNDEF) {
int subset_spill_offset = spill_offset +
ROUND_DOWN_TO(inst->dst.offset, REG_SIZE);
fs_reg spill_src = alloc_spill_reg(regs_written(inst), ip);
elk_fs_reg spill_src = alloc_spill_reg(regs_written(inst), ip);
inst->dst.nr = spill_src.nr;
inst->dst.offset %= REG_SIZE;
@@ -1301,8 +1301,8 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
subset_spill_offset, regs_written(inst), ip);
}
for (fs_inst *inst = (fs_inst *)before->next;
inst != after; inst = (fs_inst *)inst->next)
for (elk_fs_inst *inst = (elk_fs_inst *)before->next;
inst != after; inst = (elk_fs_inst *)inst->next)
setup_inst_interference(inst);
/* We don't advance the ip for scratch read/write instructions
@@ -1319,7 +1319,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
}
bool
fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all)
elk_fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all)
{
build_interference_graph(fs->spilled_any_registers || spill_all);
@@ -1387,7 +1387,7 @@ fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all)
reg_unit(devinfo)));
}
foreach_block_and_inst(block, fs_inst, inst, fs->cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, fs->cfg) {
assign_reg(devinfo, hw_reg_mapping, &inst->dst);
for (int i = 0; i < inst->sources; i++) {
assign_reg(devinfo, hw_reg_mapping, &inst->src[i]);
@@ -1400,9 +1400,9 @@ fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all)
}
bool
fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
elk_fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
{
fs_reg_alloc alloc(this);
elk_fs_reg_alloc alloc(this);
bool success = alloc.assign_regs(allow_spilling, spill_all);
if (!success && allow_spilling) {
fail("no register to spill:\n");
src/intel/compiler/elk/elk_fs_register_coalesce.cpp
+23 -23
View File
@@ -47,10 +47,10 @@
using namespace elk;
static bool
is_nop_mov(const fs_inst *inst)
is_nop_mov(const elk_fs_inst *inst)
{
if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
fs_reg dst = inst->dst;
if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD) {
elk_fs_reg dst = inst->dst;
for (int i = 0; i < inst->sources; i++) {
if (!dst.equals(inst->src[i])) {
return false;
@@ -60,7 +60,7 @@ is_nop_mov(const fs_inst *inst)
type_sz(inst->src[i].type));
}
return true;
} else if (inst->opcode == BRW_OPCODE_MOV) {
} else if (inst->opcode == ELK_OPCODE_MOV) {
return inst->dst.equals(inst->src[0]);
}
@@ -68,10 +68,10 @@ is_nop_mov(const fs_inst *inst)
}
static bool
is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
is_coalesce_candidate(const elk_fs_visitor *v, const elk_fs_inst *inst)
{
if ((inst->opcode != BRW_OPCODE_MOV &&
inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
if ((inst->opcode != ELK_OPCODE_MOV &&
inst->opcode != ELK_SHADER_OPCODE_LOAD_PAYLOAD) ||
inst->is_partial_write() ||
inst->saturate ||
inst->src[0].file != VGRF ||
@@ -87,7 +87,7 @@ is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
v->alloc.sizes[inst->dst.nr])
return false;
if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD) {
if (!is_coalescing_payload(v->alloc, inst)) {
return false;
}
@@ -97,8 +97,8 @@ is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
}
static bool
can_coalesce_vars(const fs_live_variables &live, const cfg_t *cfg,
const bblock_t *block, const fs_inst *inst,
can_coalesce_vars(const fs_live_variables &live, const elk_cfg_t *cfg,
const elk_bblock_t *block, const elk_fs_inst *inst,
int dst_var, int src_var)
{
if (!live.vars_interfere(src_var, dst_var))
@@ -128,7 +128,7 @@ can_coalesce_vars(const fs_live_variables &live, const cfg_t *cfg,
bool seen_src_write = false;
bool seen_copy = false;
foreach_inst_in_block(fs_inst, scan_inst, scan_block) {
foreach_inst_in_block(elk_fs_inst, scan_inst, scan_block) {
scan_ip++;
/* Ignore anything before the intersection of the live ranges */
@@ -189,7 +189,7 @@ can_coalesce_vars(const fs_live_variables &live, const cfg_t *cfg,
}
bool
fs_visitor::register_coalesce()
elk_fs_visitor::register_coalesce()
{
bool progress = false;
fs_live_variables &live = live_analysis.require();
@@ -197,16 +197,16 @@ fs_visitor::register_coalesce()
int channels_remaining = 0;
unsigned src_reg = ~0u, dst_reg = ~0u;
int *dst_reg_offset = new int[MAX_VGRF_SIZE(devinfo)];
fs_inst **mov = new fs_inst *[MAX_VGRF_SIZE(devinfo)];
elk_fs_inst **mov = new elk_fs_inst *[MAX_VGRF_SIZE(devinfo)];
int *dst_var = new int[MAX_VGRF_SIZE(devinfo)];
int *src_var = new int[MAX_VGRF_SIZE(devinfo)];
foreach_block_and_inst(block, fs_inst, inst, cfg) {
foreach_block_and_inst(block, elk_fs_inst, inst, cfg) {
if (!is_coalesce_candidate(this, inst))
continue;
if (is_nop_mov(inst)) {
inst->opcode = BRW_OPCODE_NOP;
inst->opcode = ELK_OPCODE_NOP;
progress = true;
continue;
}
@@ -226,7 +226,7 @@ fs_visitor::register_coalesce()
if (dst_reg != inst->dst.nr)
continue;
if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD) {
for (int i = 0; i < src_size; i++) {
dst_reg_offset[i] = i;
}
@@ -281,8 +281,8 @@ fs_visitor::register_coalesce()
if (!mov[i])
continue;
if (mov[i]->conditional_mod == BRW_CONDITIONAL_NONE) {
mov[i]->opcode = BRW_OPCODE_NOP;
if (mov[i]->conditional_mod == ELK_CONDITIONAL_NONE) {
mov[i]->opcode = ELK_OPCODE_NOP;
mov[i]->dst = reg_undef;
for (int j = 0; j < mov[i]->sources; j++) {
mov[i]->src[j] = reg_undef;
@@ -294,14 +294,14 @@ fs_visitor::register_coalesce()
* that writes the register. If not, this keeps things correct
* while still letting us coalesce.
*/
assert(mov[i]->opcode == BRW_OPCODE_MOV);
assert(mov[i]->opcode == ELK_OPCODE_MOV);
assert(mov[i]->sources == 1);
mov[i]->src[0] = mov[i]->dst;
mov[i]->dst = retype(brw_null_reg(), mov[i]->dst.type);
mov[i]->dst = retype(elk_null_reg(), mov[i]->dst.type);
}
}
foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
foreach_block_and_inst(block, elk_fs_inst, scan_inst, cfg) {
if (scan_inst->dst.file == VGRF &&
scan_inst->dst.nr == src_reg) {
scan_inst->dst.nr = dst_reg;
@@ -329,8 +329,8 @@ fs_visitor::register_coalesce()
}
if (progress) {
foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) {
if (inst->opcode == BRW_OPCODE_NOP) {
foreach_block_and_inst_safe (block, elk_backend_instruction, inst, cfg) {
if (inst->opcode == ELK_OPCODE_NOP) {
inst->remove(block, true);
}
}
src/intel/compiler/elk/elk_fs_saturate_propagation.cpp
+13 -13
View File
@@ -45,15 +45,15 @@ using namespace elk;
*/
static bool
opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block)
opt_saturate_propagation_local(const fs_live_variables &live, elk_bblock_t *block)
{
bool progress = false;
int ip = block->end_ip + 1;
foreach_inst_in_block_reverse(fs_inst, inst, block) {
foreach_inst_in_block_reverse(elk_fs_inst, inst, block) {
ip--;
if (inst->opcode != BRW_OPCODE_MOV ||
if (inst->opcode != ELK_OPCODE_MOV ||
!inst->saturate ||
inst->dst.file != VGRF ||
inst->dst.type != inst->src[0].type ||
@@ -65,7 +65,7 @@ opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block)
int src_end_ip = live.end[src_var];
bool interfered = false;
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) {
if (scan_inst->exec_size == inst->exec_size &&
regions_overlap(scan_inst->dst, scan_inst->size_written,
inst->src[0], inst->size_read(0))) {
@@ -87,23 +87,23 @@ opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block)
}
if (inst->src[0].negate) {
if (scan_inst->opcode == BRW_OPCODE_MUL) {
if (scan_inst->opcode == ELK_OPCODE_MUL) {
scan_inst->src[0].negate = !scan_inst->src[0].negate;
inst->src[0].negate = false;
} else if (scan_inst->opcode == BRW_OPCODE_MAD) {
} else if (scan_inst->opcode == ELK_OPCODE_MAD) {
for (int i = 0; i < 2; i++) {
if (scan_inst->src[i].file == IMM) {
brw_negate_immediate(scan_inst->src[i].type,
&scan_inst->src[i].as_brw_reg());
elk_negate_immediate(scan_inst->src[i].type,
&scan_inst->src[i].as_elk_reg());
} else {
scan_inst->src[i].negate = !scan_inst->src[i].negate;
}
}
inst->src[0].negate = false;
} else if (scan_inst->opcode == BRW_OPCODE_ADD) {
} else if (scan_inst->opcode == ELK_OPCODE_ADD) {
if (scan_inst->src[1].file == IMM) {
if (!brw_negate_immediate(scan_inst->src[1].type,
&scan_inst->src[1].as_brw_reg())) {
if (!elk_negate_immediate(scan_inst->src[1].type,
&scan_inst->src[1].as_elk_reg())) {
break;
}
} else {
@@ -129,7 +129,7 @@ opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block)
regions_overlap(
scan_inst->src[i], scan_inst->size_read(i),
inst->src[0], inst->size_read(0))) {
if (scan_inst->opcode != BRW_OPCODE_MOV ||
if (scan_inst->opcode != ELK_OPCODE_MOV ||
!scan_inst->saturate ||
scan_inst->src[0].abs ||
scan_inst->src[0].negate ||
@@ -150,7 +150,7 @@ opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block)
}
bool
fs_visitor::opt_saturate_propagation()
elk_fs_visitor::opt_saturate_propagation()
{
const fs_live_variables &live = live_analysis.require();
bool progress = false;
src/intel/compiler/elk/elk_fs_sel_peephole.cpp
+20 -20
View File
@@ -44,7 +44,7 @@ using namespace elk;
* Scans forwards from an IF counting consecutive MOV instructions in the
* "then" and "else" blocks of the if statement.
*
* A pointer to the bblock_t following the IF is passed as the <then_block>
* A pointer to the elk_bblock_t following the IF is passed as the <then_block>
* argument. The function stores pointers to the MOV instructions in the
* <then_mov> and <else_mov> arrays.
*
@@ -65,12 +65,12 @@ using namespace elk;
*/
static int
count_movs_from_if(const intel_device_info *devinfo,
fs_inst *then_mov[MAX_MOVS], fs_inst *else_mov[MAX_MOVS],
bblock_t *then_block, bblock_t *else_block)
elk_fs_inst *then_mov[MAX_MOVS], elk_fs_inst *else_mov[MAX_MOVS],
elk_bblock_t *then_block, elk_bblock_t *else_block)
{
int then_movs = 0;
foreach_inst_in_block(fs_inst, inst, then_block) {
if (then_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV ||
foreach_inst_in_block(elk_fs_inst, inst, then_block) {
if (then_movs == MAX_MOVS || inst->opcode != ELK_OPCODE_MOV ||
inst->flags_written(devinfo))
break;
@@ -79,8 +79,8 @@ count_movs_from_if(const intel_device_info *devinfo,
}
int else_movs = 0;
foreach_inst_in_block(fs_inst, inst, else_block) {
if (else_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV ||
foreach_inst_in_block(elk_fs_inst, inst, else_block) {
if (else_movs == MAX_MOVS || inst->opcode != ELK_OPCODE_MOV ||
inst->flags_written(devinfo))
break;
@@ -126,7 +126,7 @@ count_movs_from_if(const intel_device_info *devinfo,
* If src0 is an immediate value, we promote it to a temporary GRF.
*/
bool
fs_visitor::opt_peephole_sel()
elk_fs_visitor::opt_peephole_sel()
{
bool progress = false;
@@ -134,18 +134,18 @@ fs_visitor::opt_peephole_sel()
/* IF instructions, by definition, can only be found at the ends of
* basic blocks.
*/
fs_inst *if_inst = (fs_inst *)block->end();
if (if_inst->opcode != BRW_OPCODE_IF)
elk_fs_inst *if_inst = (elk_fs_inst *)block->end();
if (if_inst->opcode != ELK_OPCODE_IF)
continue;
fs_inst *else_mov[MAX_MOVS] = { NULL };
fs_inst *then_mov[MAX_MOVS] = { NULL };
elk_fs_inst *else_mov[MAX_MOVS] = { NULL };
elk_fs_inst *then_mov[MAX_MOVS] = { NULL };
bblock_t *then_block = block->next();
bblock_t *else_block = NULL;
foreach_list_typed(bblock_link, child, link, &block->children) {
elk_bblock_t *then_block = block->next();
elk_bblock_t *else_block = NULL;
foreach_list_typed(elk_bblock_link, child, link, &block->children) {
if (child->block != then_block) {
if (child->block->prev()->end()->opcode == BRW_OPCODE_ELSE) {
if (child->block->prev()->end()->opcode == ELK_OPCODE_ELSE) {
else_block = child->block;
}
break;
@@ -171,8 +171,8 @@ fs_visitor::opt_peephole_sel()
then_mov[i]->force_writemask_all != else_mov[i]->force_writemask_all ||
then_mov[i]->is_partial_write() ||
else_mov[i]->is_partial_write() ||
then_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE ||
else_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE) {
then_mov[i]->conditional_mod != ELK_CONDITIONAL_NONE ||
else_mov[i]->conditional_mod != ELK_CONDITIONAL_NONE) {
movs = i;
break;
}
@@ -198,14 +198,14 @@ fs_visitor::opt_peephole_sel()
* in the "then" clause uses a constant, we need to put it in a
* temporary.
*/
fs_reg src0(then_mov[i]->src[0]);
elk_fs_reg src0(then_mov[i]->src[0]);
if (src0.file == IMM) {
src0 = ibld.vgrf(then_mov[i]->src[0].type);
ibld.MOV(src0, then_mov[i]->src[0]);
}
/* 64-bit immediates can't be placed in src1. */
fs_reg src1(else_mov[i]->src[0]);
elk_fs_reg src1(else_mov[i]->src[0]);
if (src1.file == IMM && type_sz(src1.type) == 8) {
src1 = ibld.vgrf(else_mov[i]->src[0].type);
ibld.MOV(src1, else_mov[i]->src[0]);
src/intel/compiler/elk/elk_fs_thread_payload.cpp
+62 -62
View File
@@ -26,7 +26,7 @@
using namespace elk;
vs_thread_payload::vs_thread_payload(const fs_visitor &v)
elk_vs_thread_payload::elk_vs_thread_payload(const elk_fs_visitor &v)
{
unsigned r = 0;
@@ -34,94 +34,94 @@ vs_thread_payload::vs_thread_payload(const fs_visitor &v)
r += reg_unit(v.devinfo);
/* R1: URB handles. */
urb_handles = brw_ud8_grf(r, 0);
urb_handles = elk_ud8_grf(r, 0);
r += reg_unit(v.devinfo);
num_regs = r;
}
tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
elk_tcs_thread_payload::elk_tcs_thread_payload(const elk_fs_visitor &v)
{
struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data);
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(v.prog_data);
struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) v.key;
struct elk_vue_prog_data *vue_prog_data = elk_vue_prog_data(v.prog_data);
struct elk_tcs_prog_data *tcs_prog_data = elk_tcs_prog_data(v.prog_data);
struct elk_tcs_prog_key *tcs_key = (struct elk_tcs_prog_key *) v.key;
if (vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH) {
patch_urb_output = brw_ud1_grf(0, 0);
primitive_id = brw_vec1_grf(0, 1);
patch_urb_output = elk_ud1_grf(0, 0);
primitive_id = elk_vec1_grf(0, 1);
/* r1-r4 contain the ICP handles. */
icp_handle_start = brw_ud8_grf(1, 0);
icp_handle_start = elk_ud8_grf(1, 0);
num_regs = 5;
} else {
assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH);
assert(tcs_key->input_vertices <= BRW_MAX_TCS_INPUT_VERTICES);
assert(tcs_key->input_vertices <= ELK_MAX_TCS_INPUT_VERTICES);
unsigned r = 0;
r += reg_unit(v.devinfo);
patch_urb_output = brw_ud8_grf(r, 0);
patch_urb_output = elk_ud8_grf(r, 0);
r += reg_unit(v.devinfo);
if (tcs_prog_data->include_primitive_id) {
primitive_id = brw_vec8_grf(r, 0);
primitive_id = elk_vec8_grf(r, 0);
r += reg_unit(v.devinfo);
}
/* ICP handles occupy the next 1-32 registers. */
icp_handle_start = brw_ud8_grf(r, 0);
r += brw_tcs_prog_key_input_vertices(tcs_key) * reg_unit(v.devinfo);
icp_handle_start = elk_ud8_grf(r, 0);
r += elk_tcs_prog_key_input_vertices(tcs_key) * reg_unit(v.devinfo);
num_regs = r;
}
}
tes_thread_payload::tes_thread_payload(const fs_visitor &v)
elk_tes_thread_payload::elk_tes_thread_payload(const elk_fs_visitor &v)
{
unsigned r = 0;
/* R0: Thread Header. */
patch_urb_input = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD);
primitive_id = brw_vec1_grf(0, 1);
patch_urb_input = retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_UD);
primitive_id = elk_vec1_grf(0, 1);
r += reg_unit(v.devinfo);
/* R1-3: gl_TessCoord.xyz. */
for (unsigned i = 0; i < 3; i++) {
coords[i] = brw_vec8_grf(r, 0);
coords[i] = elk_vec8_grf(r, 0);
r += reg_unit(v.devinfo);
}
/* R4: URB output handles. */
urb_output = brw_ud8_grf(r, 0);
urb_output = elk_ud8_grf(r, 0);
r += reg_unit(v.devinfo);
num_regs = r;
}
gs_thread_payload::gs_thread_payload(fs_visitor &v)
elk_gs_thread_payload::elk_gs_thread_payload(elk_fs_visitor &v)
{
struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data);
struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(v.prog_data);
struct elk_vue_prog_data *vue_prog_data = elk_vue_prog_data(v.prog_data);
struct elk_gs_prog_data *gs_prog_data = elk_gs_prog_data(v.prog_data);
const fs_builder bld = fs_builder(&v).at_end();
/* R0: thread header. */
unsigned r = reg_unit(v.devinfo);
/* R1: output URB handles. */
urb_handles = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.AND(urb_handles, brw_ud8_grf(r, 0),
v.devinfo->ver >= 20 ? brw_imm_ud(0xFFFFFF) : brw_imm_ud(0xFFFF));
urb_handles = bld.vgrf(ELK_REGISTER_TYPE_UD);
bld.AND(urb_handles, elk_ud8_grf(r, 0),
v.devinfo->ver >= 20 ? elk_imm_ud(0xFFFFFF) : elk_imm_ud(0xFFFF));
/* R1: Instance ID stored in bits 31:27 */
instance_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.SHR(instance_id, brw_ud8_grf(r, 0), brw_imm_ud(27u));
instance_id = bld.vgrf(ELK_REGISTER_TYPE_UD);
bld.SHR(instance_id, elk_ud8_grf(r, 0), elk_imm_ud(27u));
r += reg_unit(v.devinfo);
if (gs_prog_data->include_primitive_id) {
primitive_id = brw_ud8_grf(r, 0);
primitive_id = elk_ud8_grf(r, 0);
r += reg_unit(v.devinfo);
}
@@ -134,7 +134,7 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v)
gs_prog_data->base.include_vue_handles = true;
/* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
icp_handle_start = brw_ud8_grf(r, 0);
icp_handle_start = elk_ud8_grf(r, 0);
r += v.nir->info.gs.vertices_in * reg_unit(v.devinfo);
num_regs = r;
@@ -156,11 +156,11 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v)
}
static inline void
setup_fs_payload_gfx20(fs_thread_payload &payload,
const fs_visitor &v,
setup_fs_payload_gfx20(elk_fs_thread_payload &payload,
const elk_fs_visitor &v,
bool &source_depth_to_render_target)
{
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data);
struct elk_wm_prog_data *prog_data = elk_wm_prog_data(v.prog_data);
const unsigned payload_width = 16;
assert(v.dispatch_width % payload_width == 0);
assert(v.devinfo->ver >= 20);
@@ -173,12 +173,12 @@ setup_fs_payload_gfx20(fs_thread_payload &payload,
for (unsigned j = 0; j < v.dispatch_width / payload_width; j++) {
/* R2-13: Barycentric interpolation coordinates. These appear
* in the same order that they appear in the brw_barycentric_mode
* in the same order that they appear in the elk_barycentric_mode
* enum. Each set of coordinates occupies 2 64B registers per
* SIMD16 half. Coordinates only appear if they were enabled
* using the "Barycentric Interpolation Mode" bits in WM_STATE.
*/
for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
for (int i = 0; i < ELK_BARYCENTRIC_MODE_COUNT; ++i) {
if (prog_data->barycentric_interp_modes & (1 << i)) {
payload.barycentric_coord_reg[i][j] = payload.num_regs;
payload.num_regs += payload_width / 4;
@@ -230,11 +230,11 @@ setup_fs_payload_gfx20(fs_thread_payload &payload,
}
static inline void
setup_fs_payload_gfx6(fs_thread_payload &payload,
const fs_visitor &v,
setup_fs_payload_gfx6(elk_fs_thread_payload &payload,
const elk_fs_visitor &v,
bool &source_depth_to_render_target)
{
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data);
struct elk_wm_prog_data *prog_data = elk_wm_prog_data(v.prog_data);
const unsigned payload_width = MIN2(16, v.dispatch_width);
assert(v.dispatch_width % payload_width == 0);
@@ -252,13 +252,13 @@ setup_fs_payload_gfx6(fs_thread_payload &payload,
for (unsigned j = 0; j < v.dispatch_width / payload_width; j++) {
/* R3-26: barycentric interpolation coordinates. These appear in the
* same order that they appear in the brw_barycentric_mode enum. Each
* same order that they appear in the elk_barycentric_mode enum. Each
* set of coordinates occupies 2 registers if dispatch width == 8 and 4
* registers if dispatch width == 16. Coordinates only appear if they
* were enabled using the "Barycentric Interpolation Mode" bits in
* WM_STATE.
*/
for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
for (int i = 0; i < ELK_BARYCENTRIC_MODE_COUNT; ++i) {
if (prog_data->barycentric_interp_modes & (1 << i)) {
payload.barycentric_coord_reg[i][j] = payload.num_regs;
payload.num_regs += payload_width / 4;
@@ -317,7 +317,7 @@ static const struct {
GLuint sd_to_rt:1;
GLuint dd_present:1;
GLuint ds_present:1;
} wm_iz_table[BRW_WM_IZ_BIT_MAX] =
} wm_iz_table[ELK_WM_IZ_BIT_MAX] =
{
{ P, 0, 0, 0, 0 },
{ P, 0, 0, 0, 0 },
@@ -386,25 +386,25 @@ static const struct {
};
/**
* \param line_aa BRW_NEVER, BRW_ALWAYS or BRW_SOMETIMES
* \param lookup bitmask of BRW_WM_IZ_* flags
* \param line_aa ELK_NEVER, ELK_ALWAYS or ELK_SOMETIMES
* \param lookup bitmask of ELK_WM_IZ_* flags
*/
static inline void
setup_fs_payload_gfx4(fs_thread_payload &payload,
const fs_visitor &v,
setup_fs_payload_gfx4(elk_fs_thread_payload &payload,
const elk_fs_visitor &v,
bool &source_depth_to_render_target,
bool &runtime_check_aads_emit)
{
assert(v.dispatch_width <= 16);
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data);
brw_wm_prog_key *key = (brw_wm_prog_key *) v.key;
struct elk_wm_prog_data *prog_data = elk_wm_prog_data(v.prog_data);
elk_wm_prog_key *key = (elk_wm_prog_key *) v.key;
GLuint reg = 1;
bool kill_stats_promoted_workaround = false;
int lookup = key->iz_lookup;
assert(lookup < BRW_WM_IZ_BIT_MAX);
assert(lookup < ELK_WM_IZ_BIT_MAX);
/* Crazy workaround in the windowizer, which we need to track in
* our register allocation and render target writes. See the "If
@@ -412,7 +412,7 @@ setup_fs_payload_gfx4(fs_thread_payload &payload,
* Test Cases [Pre-DevGT] of the 3D Pipeline - Windower B-Spec.
*/
if (key->stats_wm &&
(lookup & BRW_WM_IZ_PS_KILL_ALPHATEST_BIT) &&
(lookup & ELK_WM_IZ_PS_KILL_ALPHATEST_BIT) &&
wm_iz_table[lookup].mode == P) {
kill_stats_promoted_workaround = true;
}
@@ -428,10 +428,10 @@ setup_fs_payload_gfx4(fs_thread_payload &payload,
if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround)
source_depth_to_render_target = true;
if (wm_iz_table[lookup].ds_present || key->line_aa != BRW_NEVER) {
if (wm_iz_table[lookup].ds_present || key->line_aa != ELK_NEVER) {
payload.aa_dest_stencil_reg[0] = reg;
runtime_check_aads_emit =
!wm_iz_table[lookup].ds_present && key->line_aa == BRW_SOMETIMES;
!wm_iz_table[lookup].ds_present && key->line_aa == ELK_SOMETIMES;
reg++;
}
@@ -447,7 +447,7 @@ setup_fs_payload_gfx4(fs_thread_payload &payload,
#undef C /* computed */
#undef N /* non-promoted? */
fs_thread_payload::fs_thread_payload(const fs_visitor &v,
elk_fs_thread_payload::elk_fs_thread_payload(const elk_fs_visitor &v,
bool &source_depth_to_render_target,
bool &runtime_check_aads_emit)
: subspan_coord_reg(),
@@ -469,24 +469,24 @@ fs_thread_payload::fs_thread_payload(const fs_visitor &v,
runtime_check_aads_emit);
}
cs_thread_payload::cs_thread_payload(const fs_visitor &v)
elk_cs_thread_payload::elk_cs_thread_payload(const elk_fs_visitor &v)
{
struct brw_cs_prog_data *prog_data = brw_cs_prog_data(v.prog_data);
struct elk_cs_prog_data *prog_data = elk_cs_prog_data(v.prog_data);
unsigned r = reg_unit(v.devinfo);
/* See nir_setup_uniforms for subgroup_id in earlier versions. */
if (v.devinfo->verx10 >= 125) {
subgroup_id_ = brw_ud1_grf(0, 2);
subgroup_id_ = elk_ud1_grf(0, 2);
for (int i = 0; i < 3; i++) {
if (prog_data->generate_local_id & (1 << i)) {
local_invocation_id[i] = brw_uw8_grf(r, 0);
local_invocation_id[i] = elk_uw8_grf(r, 0);
r += reg_unit(v.devinfo);
if (v.devinfo->ver < 20 && v.dispatch_width == 32)
r += reg_unit(v.devinfo);
} else {
local_invocation_id[i] = brw_imm_uw(0);
local_invocation_id[i] = elk_imm_uw(0);
}
}
@@ -499,21 +499,21 @@ cs_thread_payload::cs_thread_payload(const fs_visitor &v)
}
void
cs_thread_payload::load_subgroup_id(const fs_builder &bld,
fs_reg &dest) const
elk_cs_thread_payload::load_subgroup_id(const fs_builder &bld,
elk_fs_reg &dest) const
{
auto devinfo = bld.shader->devinfo;
dest = retype(dest, BRW_REGISTER_TYPE_UD);
dest = retype(dest, ELK_REGISTER_TYPE_UD);
if (subgroup_id_.file != BAD_FILE) {
assert(devinfo->verx10 >= 125);
bld.AND(dest, subgroup_id_, brw_imm_ud(INTEL_MASK(7, 0)));
bld.AND(dest, subgroup_id_, elk_imm_ud(INTEL_MASK(7, 0)));
} else {
assert(devinfo->verx10 < 125);
assert(gl_shader_stage_is_compute(bld.shader->stage));
int index = brw_get_subgroup_id_param_index(devinfo,
int index = elk_get_subgroup_id_param_index(devinfo,
bld.shader->stage_prog_data);
bld.MOV(dest, fs_reg(UNIFORM, index, BRW_REGISTER_TYPE_UD));
bld.MOV(dest, elk_fs_reg(UNIFORM, index, ELK_REGISTER_TYPE_UD));
}
}
src/intel/compiler/elk/elk_fs_validate.cpp
+19 -19
View File
@@ -88,17 +88,17 @@
#ifndef NDEBUG
void
fs_visitor::validate()
elk_fs_visitor::validate()
{
cfg->validate(_mesa_shader_stage_to_abbrev(stage));
foreach_block_and_inst (block, fs_inst, inst, cfg) {
foreach_block_and_inst (block, elk_fs_inst, inst, cfg) {
switch (inst->opcode) {
case SHADER_OPCODE_SEND:
case ELK_SHADER_OPCODE_SEND:
fsv_assert(is_uniform(inst->src[0]) && is_uniform(inst->src[1]));
break;
case BRW_OPCODE_MOV:
case ELK_OPCODE_MOV:
fsv_assert(inst->sources == 1);
break;
@@ -106,36 +106,36 @@ fs_visitor::validate()
break;
}
if (inst->is_3src(compiler)) {
if (inst->elk_is_3src(compiler)) {
const unsigned integer_sources =
brw_reg_type_is_integer(inst->src[0].type) +
brw_reg_type_is_integer(inst->src[1].type) +
brw_reg_type_is_integer(inst->src[2].type);
elk_reg_type_is_integer(inst->src[0].type) +
elk_reg_type_is_integer(inst->src[1].type) +
elk_reg_type_is_integer(inst->src[2].type);
const unsigned float_sources =
brw_reg_type_is_floating_point(inst->src[0].type) +
brw_reg_type_is_floating_point(inst->src[1].type) +
brw_reg_type_is_floating_point(inst->src[2].type);
elk_reg_type_is_floating_point(inst->src[0].type) +
elk_reg_type_is_floating_point(inst->src[1].type) +
elk_reg_type_is_floating_point(inst->src[2].type);
fsv_assert((integer_sources == 3 && float_sources == 0) ||
(integer_sources == 0 && float_sources == 3));
if (devinfo->ver >= 10) {
for (unsigned i = 0; i < 3; i++) {
if (inst->src[i].file == BRW_IMMEDIATE_VALUE)
if (inst->src[i].file == ELK_IMMEDIATE_VALUE)
continue;
switch (inst->src[i].vstride) {
case BRW_VERTICAL_STRIDE_0:
case BRW_VERTICAL_STRIDE_4:
case BRW_VERTICAL_STRIDE_8:
case BRW_VERTICAL_STRIDE_16:
case ELK_VERTICAL_STRIDE_0:
case ELK_VERTICAL_STRIDE_4:
case ELK_VERTICAL_STRIDE_8:
case ELK_VERTICAL_STRIDE_16:
break;
case BRW_VERTICAL_STRIDE_1:
case ELK_VERTICAL_STRIDE_1:
fsv_assert_lte(12, devinfo->ver);
break;
case BRW_VERTICAL_STRIDE_2:
case ELK_VERTICAL_STRIDE_2:
fsv_assert_lte(devinfo->ver, 11);
break;
@@ -153,7 +153,7 @@ fs_visitor::validate()
* passes (e.g., combine constants) will fix them.
*/
for (unsigned i = 0; i < 3; i++) {
fsv_assert_ne(inst->src[i].file, BRW_IMMEDIATE_VALUE);
fsv_assert_ne(inst->src[i].file, ELK_IMMEDIATE_VALUE);
/* A stride of 1 (the usual case) or 0, with a special
* "repctrl" bit, is allowed. The repctrl bit doesn't work for
src/intel/compiler/elk/elk_fs_visitor.cpp
+259 -259
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_gfx6_gs_visitor.cpp
+81 -81
View File
@@ -67,14 +67,14 @@ gfx6_gs_visitor::emit_prolog()
(prog_data->vue_map.num_slots + 1) *
nir->info.gs.vertices_out);
this->vertex_output_offset = src_reg(this, glsl_uint_type());
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
emit(MOV(dst_reg(this->vertex_output_offset), elk_imm_ud(0u)));
/* MRF 1 will be the header for all messages (FF_SYNC and URB_WRITES),
* so initialize it once to R0.
*/
vec4_instruction *inst = emit(MOV(dst_reg(MRF, 1),
retype(brw_vec8_grf(0, 0),
BRW_REGISTER_TYPE_UD)));
retype(elk_vec8_grf(0, 0),
ELK_REGISTER_TYPE_UD)));
inst->force_writemask_all = true;
/* This will be used as a temporary to store writeback data of FF_SYNC
@@ -89,13 +89,13 @@ gfx6_gs_visitor::emit_prolog()
* headers.
*/
this->first_vertex = src_reg(this, glsl_uint_type());
emit(MOV(dst_reg(this->first_vertex), brw_imm_ud(URB_WRITE_PRIM_START)));
emit(MOV(dst_reg(this->first_vertex), elk_imm_ud(URB_WRITE_PRIM_START)));
/* The FF_SYNC message requires to know the number of primitives generated,
* so keep a counter for this.
*/
this->prim_count = src_reg(this, glsl_uint_type());
emit(MOV(dst_reg(this->prim_count), brw_imm_ud(0u)));
emit(MOV(dst_reg(this->prim_count), elk_imm_ud(0u)));
if (gs_prog_data->num_transform_feedback_bindings) {
/* Create a virtual register to hold destination indices in SOL */
@@ -107,7 +107,7 @@ gfx6_gs_visitor::emit_prolog()
/* Create a virtual register to hold max values of SVBI */
this->max_svbi = src_reg(this, glsl_uvec4_type());
emit(MOV(dst_reg(this->max_svbi),
src_reg(retype(brw_vec1_grf(1, 4), BRW_REGISTER_TYPE_UD))));
src_reg(retype(elk_vec1_grf(1, 4), ELK_REGISTER_TYPE_UD))));
}
/* PrimitveID is delivered in r0.1 of the thread payload. If the program
@@ -130,8 +130,8 @@ gfx6_gs_visitor::emit_prolog()
*/
if (gs_prog_data->include_primitive_id) {
this->primitive_id =
src_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
emit(GS_OPCODE_SET_PRIMITIVE_ID, dst_reg(this->primitive_id));
src_reg(retype(elk_vec8_grf(1, 0), ELK_REGISTER_TYPE_UD));
emit(ELK_GS_OPCODE_SET_PRIMITIVE_ID, dst_reg(this->primitive_id));
}
}
@@ -170,7 +170,7 @@ gfx6_gs_visitor::gs_emit_vertex(int stream_id)
}
emit(ADD(dst_reg(this->vertex_output_offset),
this->vertex_output_offset, brw_imm_ud(1u)));
this->vertex_output_offset, elk_imm_ud(1u)));
}
/* Now buffer flags for this vertex */
@@ -181,9 +181,9 @@ gfx6_gs_visitor::gs_emit_vertex(int stream_id)
/* If we are outputting points, then every vertex has PrimStart and
* PrimEnd set.
*/
emit(MOV(dst, brw_imm_d((_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT) |
emit(MOV(dst, elk_imm_d((_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT) |
URB_WRITE_PRIM_START | URB_WRITE_PRIM_END)));
emit(ADD(dst_reg(this->prim_count), this->prim_count, brw_imm_ud(1u)));
emit(ADD(dst_reg(this->prim_count), this->prim_count, elk_imm_ud(1u)));
} else {
/* Otherwise, we can only set the PrimStart flag, which we have stored
* in the first_vertex register. We will have to wait until we execute
@@ -191,12 +191,12 @@ gfx6_gs_visitor::gs_emit_vertex(int stream_id)
* vertex.
*/
emit(OR(dst, this->first_vertex,
brw_imm_ud(gs_prog_data->output_topology <<
elk_imm_ud(gs_prog_data->output_topology <<
URB_WRITE_PRIM_TYPE_SHIFT)));
emit(MOV(dst_reg(this->first_vertex), brw_imm_ud(0u)));
emit(MOV(dst_reg(this->first_vertex), elk_imm_ud(0u)));
}
emit(ADD(dst_reg(this->vertex_output_offset),
this->vertex_output_offset, brw_imm_ud(1u)));
this->vertex_output_offset, elk_imm_ud(1u)));
}
void
@@ -220,33 +220,33 @@ gfx6_gs_visitor::gs_end_primitive()
*/
unsigned num_output_vertices = nir->info.gs.vertices_out;
emit(CMP(dst_null_ud(), this->vertex_count,
brw_imm_ud(num_output_vertices + 1), BRW_CONDITIONAL_L));
elk_imm_ud(num_output_vertices + 1), ELK_CONDITIONAL_L));
vec4_instruction *inst = emit(CMP(dst_null_ud(),
this->vertex_count, brw_imm_ud(0u),
BRW_CONDITIONAL_NEQ));
inst->predicate = BRW_PREDICATE_NORMAL;
emit(IF(BRW_PREDICATE_NORMAL));
this->vertex_count, elk_imm_ud(0u),
ELK_CONDITIONAL_NEQ));
inst->predicate = ELK_PREDICATE_NORMAL;
emit(IF(ELK_PREDICATE_NORMAL));
{
/* vertex_output_offset is already pointing at the first entry of the
* next vertex. So subtract 1 to modify the flags for the previous
* vertex.
*/
src_reg offset(this, glsl_uint_type());
emit(ADD(dst_reg(offset), this->vertex_output_offset, brw_imm_d(-1)));
emit(ADD(dst_reg(offset), this->vertex_output_offset, elk_imm_d(-1)));
src_reg dst(this->vertex_output);
dst.reladdr = ralloc(mem_ctx, src_reg);
memcpy(dst.reladdr, &offset, sizeof(src_reg));
emit(OR(dst_reg(dst), dst, brw_imm_d(URB_WRITE_PRIM_END)));
emit(ADD(dst_reg(this->prim_count), this->prim_count, brw_imm_ud(1u)));
emit(OR(dst_reg(dst), dst, elk_imm_d(URB_WRITE_PRIM_END)));
emit(ADD(dst_reg(this->prim_count), this->prim_count, elk_imm_ud(1u)));
/* Set the first vertex flag to indicate that the next vertex will start
* a primitive.
*/
emit(MOV(dst_reg(this->first_vertex), brw_imm_d(URB_WRITE_PRIM_START)));
emit(MOV(dst_reg(this->first_vertex), elk_imm_d(URB_WRITE_PRIM_START)));
}
emit(BRW_OPCODE_ENDIF);
emit(ELK_OPCODE_ENDIF);
}
void
@@ -264,13 +264,13 @@ gfx6_gs_visitor::emit_urb_write_header(int mrf)
src_reg flags_offset(this, glsl_uint_type());
emit(ADD(dst_reg(flags_offset),
this->vertex_output_offset,
brw_imm_d(prog_data->vue_map.num_slots)));
elk_imm_d(prog_data->vue_map.num_slots)));
src_reg flags_data(this->vertex_output);
flags_data.reladdr = ralloc(mem_ctx, src_reg);
memcpy(flags_data.reladdr, &flags_offset, sizeof(src_reg));
emit(GS_OPCODE_SET_DWORD_2, dst_reg(MRF, mrf), flags_data);
emit(ELK_GS_OPCODE_SET_DWORD_2, dst_reg(MRF, mrf), flags_data);
}
static unsigned
@@ -293,8 +293,8 @@ gfx6_gs_visitor::emit_snb_gs_urb_write_opcode(bool complete, int base_mrf,
if (!complete) {
/* If the vertex is not complete we don't have to do anything special */
inst = emit(VEC4_GS_OPCODE_URB_WRITE);
inst->urb_write_flags = BRW_URB_WRITE_NO_FLAGS;
inst = emit(ELK_VEC4_GS_OPCODE_URB_WRITE);
inst->urb_write_flags = ELK_URB_WRITE_NO_FLAGS;
} else {
/* Otherwise we always request to allocate a new VUE handle. If this is
* the last write before the EOT message and the new handle never gets
@@ -304,8 +304,8 @@ gfx6_gs_visitor::emit_snb_gs_urb_write_opcode(bool complete, int base_mrf,
* which would require to end the program with an IF/ELSE/ENDIF block,
* something we do not want.
*/
inst = emit(VEC4_GS_OPCODE_URB_WRITE_ALLOCATE);
inst->urb_write_flags = BRW_URB_WRITE_COMPLETE;
inst = emit(ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE);
inst->urb_write_flags = ELK_URB_WRITE_COMPLETE;
inst->dst = dst_reg(MRF, base_mrf);
inst->src[0] = this->temp;
}
@@ -323,10 +323,10 @@ gfx6_gs_visitor::emit_thread_end()
* points because in the point case we set PrimEnd on all vertices.
*/
if (nir->info.gs.output_primitive != MESA_PRIM_POINTS) {
emit(CMP(dst_null_ud(), this->first_vertex, brw_imm_ud(0u), BRW_CONDITIONAL_Z));
emit(IF(BRW_PREDICATE_NORMAL));
emit(CMP(dst_null_ud(), this->first_vertex, elk_imm_ud(0u), ELK_CONDITIONAL_Z));
emit(IF(ELK_PREDICATE_NORMAL));
gs_end_primitive();
emit(BRW_OPCODE_ENDIF);
emit(ELK_OPCODE_ENDIF);
}
/* Here we have to:
@@ -354,34 +354,34 @@ gfx6_gs_visitor::emit_thread_end()
vec4_instruction *inst = NULL;
if (gs_prog_data->num_transform_feedback_bindings) {
src_reg sol_temp(this, glsl_uvec4_type());
emit(GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
emit(ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
dst_reg(this->svbi),
this->vertex_count,
this->prim_count,
sol_temp);
inst = emit(GS_OPCODE_FF_SYNC,
inst = emit(ELK_GS_OPCODE_FF_SYNC,
dst_reg(this->temp), this->prim_count, this->svbi);
} else {
inst = emit(GS_OPCODE_FF_SYNC,
dst_reg(this->temp), this->prim_count, brw_imm_ud(0u));
inst = emit(ELK_GS_OPCODE_FF_SYNC,
dst_reg(this->temp), this->prim_count, elk_imm_ud(0u));
}
inst->base_mrf = base_mrf;
emit(CMP(dst_null_ud(), this->vertex_count, brw_imm_ud(0u), BRW_CONDITIONAL_G));
emit(IF(BRW_PREDICATE_NORMAL));
emit(CMP(dst_null_ud(), this->vertex_count, elk_imm_ud(0u), ELK_CONDITIONAL_G));
emit(IF(ELK_PREDICATE_NORMAL));
{
/* Loop over all buffered vertices and emit URB write messages */
this->current_annotation = "gfx6 thread end: urb writes init";
src_reg vertex(this, glsl_uint_type());
emit(MOV(dst_reg(vertex), brw_imm_ud(0u)));
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
emit(MOV(dst_reg(vertex), elk_imm_ud(0u)));
emit(MOV(dst_reg(this->vertex_output_offset), elk_imm_ud(0u)));
this->current_annotation = "gfx6 thread end: urb writes";
emit(BRW_OPCODE_DO);
emit(ELK_OPCODE_DO);
{
emit(CMP(dst_null_d(), vertex, this->vertex_count, BRW_CONDITIONAL_GE));
inst = emit(BRW_OPCODE_BREAK);
inst->predicate = BRW_PREDICATE_NORMAL;
emit(CMP(dst_null_d(), vertex, this->vertex_count, ELK_CONDITIONAL_GE));
inst = emit(ELK_OPCODE_BREAK);
inst->predicate = ELK_PREDICATE_NORMAL;
/* First we prepare the message header */
emit_urb_write_header(base_mrf);
@@ -418,13 +418,13 @@ gfx6_gs_visitor::emit_thread_end()
mrf++;
emit(ADD(dst_reg(this->vertex_output_offset),
this->vertex_output_offset, brw_imm_ud(1u)));
this->vertex_output_offset, elk_imm_ud(1u)));
/* If this was max_usable_mrf, we can't fit anything more into
* this URB WRITE. Same if we reached the max. message length.
*/
if (mrf > max_usable_mrf ||
align_interleaved_urb_mlen(mrf - base_mrf + 1) > BRW_MAX_MSG_LENGTH) {
align_interleaved_urb_mlen(mrf - base_mrf + 1) > ELK_MAX_MSG_LENGTH) {
slot++;
break;
}
@@ -439,16 +439,16 @@ gfx6_gs_visitor::emit_thread_end()
* writing the next vertex.
*/
emit(ADD(dst_reg(this->vertex_output_offset),
this->vertex_output_offset, brw_imm_ud(1u)));
this->vertex_output_offset, elk_imm_ud(1u)));
emit(ADD(dst_reg(vertex), vertex, brw_imm_ud(1u)));
emit(ADD(dst_reg(vertex), vertex, elk_imm_ud(1u)));
}
emit(BRW_OPCODE_WHILE);
emit(ELK_OPCODE_WHILE);
if (gs_prog_data->num_transform_feedback_bindings)
xfb_write();
}
emit(BRW_OPCODE_ENDIF);
emit(ELK_OPCODE_ENDIF);
/* Finally, emit EOT message.
*
@@ -470,13 +470,13 @@ gfx6_gs_visitor::emit_thread_end()
if (gs_prog_data->num_transform_feedback_bindings) {
/* When emitting EOT, set SONumPrimsWritten Increment Value. */
src_reg data(this, glsl_uint_type());
emit(AND(dst_reg(data), this->sol_prim_written, brw_imm_ud(0xffffu)));
emit(SHL(dst_reg(data), data, brw_imm_ud(16u)));
emit(GS_OPCODE_SET_DWORD_2, dst_reg(MRF, base_mrf), data);
emit(AND(dst_reg(data), this->sol_prim_written, elk_imm_ud(0xffffu)));
emit(SHL(dst_reg(data), data, elk_imm_ud(16u)));
emit(ELK_GS_OPCODE_SET_DWORD_2, dst_reg(MRF, base_mrf), data);
}
inst = emit(GS_OPCODE_THREAD_END);
inst->urb_write_flags = BRW_URB_WRITE_COMPLETE | BRW_URB_WRITE_UNUSED;
inst = emit(ELK_GS_OPCODE_THREAD_END);
inst->urb_write_flags = ELK_URB_WRITE_COMPLETE | ELK_URB_WRITE_UNUSED;
inst->base_mrf = base_mrf;
inst->mlen = 1;
}
@@ -484,7 +484,7 @@ gfx6_gs_visitor::emit_thread_end()
void
gfx6_gs_visitor::setup_payload()
{
int attribute_map[BRW_VARYING_SLOT_COUNT * MAX_GS_INPUT_VERTICES];
int attribute_map[ELK_VARYING_SLOT_COUNT * MAX_GS_INPUT_VERTICES];
/* Attributes are going to be interleaved, so one register contains two
* attribute slots.
@@ -551,8 +551,8 @@ gfx6_gs_visitor::xfb_write()
this->current_annotation = "gfx6 thread end: svb writes init";
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
emit(MOV(dst_reg(this->sol_prim_written), brw_imm_ud(0u)));
emit(MOV(dst_reg(this->vertex_output_offset), elk_imm_ud(0u)));
emit(MOV(dst_reg(this->sol_prim_written), elk_imm_ud(0u)));
/* Check that at least one primitive can be written
*
@@ -563,37 +563,37 @@ gfx6_gs_visitor::xfb_write()
* transform feedback is in interleaved or separate attribs mode.
*/
src_reg sol_temp(this, glsl_uvec4_type());
emit(ADD(dst_reg(sol_temp), this->svbi, brw_imm_ud(num_verts)));
emit(ADD(dst_reg(sol_temp), this->svbi, elk_imm_ud(num_verts)));
/* Compare SVBI calculated number with the maximum value, which is
* in R1.4 (previously saved in this->max_svbi) for gfx6.
*/
emit(CMP(dst_null_d(), sol_temp, this->max_svbi, BRW_CONDITIONAL_LE));
emit(IF(BRW_PREDICATE_NORMAL));
emit(CMP(dst_null_d(), sol_temp, this->max_svbi, ELK_CONDITIONAL_LE));
emit(IF(ELK_PREDICATE_NORMAL));
{
vec4_instruction *inst = emit(MOV(dst_reg(destination_indices),
brw_imm_vf4(brw_float_to_vf(0.0),
brw_float_to_vf(1.0),
brw_float_to_vf(2.0),
brw_float_to_vf(0.0))));
elk_imm_vf4(elk_float_to_vf(0.0),
elk_float_to_vf(1.0),
elk_float_to_vf(2.0),
elk_float_to_vf(0.0))));
inst->force_writemask_all = true;
emit(ADD(dst_reg(this->destination_indices),
this->destination_indices,
this->svbi));
}
emit(BRW_OPCODE_ENDIF);
emit(ELK_OPCODE_ENDIF);
/* Write transform feedback data for all processed vertices. */
for (int i = 0; i < (int)nir->info.gs.vertices_out; i++) {
emit(MOV(dst_reg(sol_temp), brw_imm_d(i)));
emit(MOV(dst_reg(sol_temp), elk_imm_d(i)));
emit(CMP(dst_null_d(), sol_temp, this->vertex_count,
BRW_CONDITIONAL_L));
emit(IF(BRW_PREDICATE_NORMAL));
ELK_CONDITIONAL_L));
emit(IF(ELK_PREDICATE_NORMAL));
{
xfb_program(i, num_verts);
}
emit(BRW_OPCODE_ENDIF);
emit(ELK_OPCODE_ENDIF);
}
}
@@ -607,11 +607,11 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts)
/* Check for buffer overflow: we need room to write the complete primitive
* (all vertices). Otherwise, avoid writing any vertices for it
*/
emit(ADD(dst_reg(sol_temp), this->sol_prim_written, brw_imm_ud(1u)));
emit(MUL(dst_reg(sol_temp), sol_temp, brw_imm_ud(num_verts)));
emit(ADD(dst_reg(sol_temp), this->sol_prim_written, elk_imm_ud(1u)));
emit(MUL(dst_reg(sol_temp), sol_temp, elk_imm_ud(num_verts)));
emit(ADD(dst_reg(sol_temp), sol_temp, this->svbi));
emit(CMP(dst_null_d(), sol_temp, this->max_svbi, BRW_CONDITIONAL_LE));
emit(IF(BRW_PREDICATE_NORMAL));
emit(CMP(dst_null_d(), sol_temp, this->max_svbi, ELK_CONDITIONAL_LE));
emit(IF(ELK_PREDICATE_NORMAL));
{
/* Avoid overwriting MRF 1 as it is used as URB write message header */
dst_reg mrf_reg(MRF, 2);
@@ -625,7 +625,7 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts)
gs_prog_data->transform_feedback_bindings[binding];
/* Set up the correct destination index for this vertex */
vec4_instruction *inst = emit(GS_OPCODE_SVB_SET_DST_INDEX,
vec4_instruction *inst = emit(ELK_GS_OPCODE_SVB_SET_DST_INDEX,
mrf_reg,
this->destination_indices);
inst->sol_vertex = vertex % num_verts;
@@ -646,13 +646,13 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts)
src_reg data(this->vertex_output);
data.reladdr = ralloc(mem_ctx, src_reg);
int offset = get_vertex_output_offset_for_varying(vertex, varying);
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_d(offset)));
emit(MOV(dst_reg(this->vertex_output_offset), elk_imm_d(offset)));
memcpy(data.reladdr, &this->vertex_output_offset, sizeof(src_reg));
data.type = output_reg[varying][0].type;
data.swizzle = gs_prog_data->transform_feedback_swizzles[binding];
/* Write data */
inst = emit(GS_OPCODE_SVB_WRITE, mrf_reg, data, sol_temp);
inst = emit(ELK_GS_OPCODE_SVB_WRITE, mrf_reg, data, sol_temp);
inst->sol_binding = binding;
inst->sol_final_write = final_write;
@@ -662,15 +662,15 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts)
*/
emit(ADD(dst_reg(this->destination_indices),
this->destination_indices,
brw_imm_ud(num_verts)));
elk_imm_ud(num_verts)));
emit(ADD(dst_reg(this->sol_prim_written),
this->sol_prim_written, brw_imm_ud(1u)));
this->sol_prim_written, elk_imm_ud(1u)));
}
}
this->current_annotation = NULL;
}
emit(BRW_OPCODE_ENDIF);
emit(ELK_OPCODE_ENDIF);
}
int
src/intel/compiler/elk/elk_gfx6_gs_visitor.h
+4 -4
View File
@@ -35,10 +35,10 @@ namespace elk {
class gfx6_gs_visitor : public vec4_gs_visitor
{
public:
gfx6_gs_visitor(const struct brw_compiler *comp,
const struct brw_compile_params *params,
struct brw_gs_compile *c,
struct brw_gs_prog_data *prog_data,
gfx6_gs_visitor(const struct elk_compiler *comp,
const struct elk_compile_params *params,
struct elk_gs_compile *c,
struct elk_gs_prog_data *prog_data,
const nir_shader *shader,
bool no_spills,
bool debug_enabled) :
src/intel/compiler/elk/elk_gram.y
+599 -599
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_inst.h
+344 -344
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_interpolation_map.c
+4 -4
View File
@@ -36,7 +36,7 @@ static char const *get_qual_name(int mode)
}
static void
gfx4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data,
gfx4_frag_prog_set_interp_modes(struct elk_wm_prog_data *prog_data,
const struct intel_vue_map *vue_map,
unsigned location, unsigned slot_count,
enum glsl_interp_mode interp)
@@ -57,8 +57,8 @@ gfx4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data,
/* Set up interpolation modes for every element in the VUE */
void
brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, nir_shader *nir,
struct brw_wm_prog_data *prog_data)
elk_setup_vue_interpolation(const struct intel_vue_map *vue_map, nir_shader *nir,
struct elk_wm_prog_data *prog_data)
{
/* Initialise interp_mode. INTERP_MODE_NONE == 0 */
memset(prog_data->interp_mode, 0, sizeof(prog_data->interp_mode));
@@ -102,7 +102,7 @@ brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, nir_shader *nir
fprintf(stderr, "%d: %d %s ofs %d\n",
i, varying,
get_qual_name(prog_data->interp_mode[i]),
brw_vue_slot_to_offset(i));
elk_vue_slot_to_offset(i));
}
}
}
src/intel/compiler/elk/elk_ir.h
+42 -42
View File
@@ -38,27 +38,27 @@
#define MAX_VGRF_SIZE(devinfo) ((devinfo)->ver >= 20 ? 40 : 20)
#ifdef __cplusplus
struct backend_reg : private brw_reg
struct elk_backend_reg : private elk_reg
{
backend_reg() {}
backend_reg(const struct brw_reg &reg) : brw_reg(reg), offset(0) {}
elk_backend_reg() {}
elk_backend_reg(const struct elk_reg &reg) : elk_reg(reg), offset(0) {}
const brw_reg &as_brw_reg() const
const elk_reg &as_elk_reg() const
{
assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
assert(offset == 0);
return static_cast<const brw_reg &>(*this);
return static_cast<const elk_reg &>(*this);
}
brw_reg &as_brw_reg()
elk_reg &as_elk_reg()
{
assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
assert(offset == 0);
return static_cast<brw_reg &>(*this);
return static_cast<elk_reg &>(*this);
}
bool equals(const backend_reg &r) const;
bool negative_equals(const backend_reg &r) const;
bool equals(const elk_backend_reg &r) const;
bool negative_equals(const elk_backend_reg &r) const;
bool is_zero() const;
bool is_one() const;
@@ -69,33 +69,33 @@ struct backend_reg : private brw_reg
/** Offset from the start of the (virtual) register in bytes. */
uint16_t offset;
using brw_reg::type;
using brw_reg::file;
using brw_reg::negate;
using brw_reg::abs;
using brw_reg::address_mode;
using brw_reg::subnr;
using brw_reg::nr;
using elk_reg::type;
using elk_reg::file;
using elk_reg::negate;
using elk_reg::abs;
using elk_reg::address_mode;
using elk_reg::subnr;
using elk_reg::nr;
using brw_reg::swizzle;
using brw_reg::writemask;
using brw_reg::indirect_offset;
using brw_reg::vstride;
using brw_reg::width;
using brw_reg::hstride;
using elk_reg::swizzle;
using elk_reg::writemask;
using elk_reg::indirect_offset;
using elk_reg::vstride;
using elk_reg::width;
using elk_reg::hstride;
using brw_reg::df;
using brw_reg::f;
using brw_reg::d;
using brw_reg::ud;
using brw_reg::d64;
using brw_reg::u64;
using elk_reg::df;
using elk_reg::f;
using elk_reg::d;
using elk_reg::ud;
using elk_reg::d64;
using elk_reg::u64;
};
struct bblock_t;
struct elk_bblock_t;
struct backend_instruction : public exec_node {
bool is_3src(const struct brw_compiler *compiler) const;
struct elk_backend_instruction : public exec_node {
bool elk_is_3src(const struct elk_compiler *compiler) const;
bool is_math() const;
bool is_control_flow_begin() const;
bool is_control_flow_end() const;
@@ -113,9 +113,9 @@ struct backend_instruction : public exec_node {
*/
bool uses_indirect_addressing() const;
void remove(bblock_t *block, bool defer_later_block_ip_updates = false);
void insert_after(bblock_t *block, backend_instruction *inst);
void insert_before(bblock_t *block, backend_instruction *inst);
void remove(elk_bblock_t *block, bool defer_later_block_ip_updates = false);
void insert_after(elk_bblock_t *block, elk_backend_instruction *inst);
void insert_before(elk_bblock_t *block, elk_backend_instruction *inst);
/**
* True if the instruction has side effects other than writing to
@@ -130,7 +130,7 @@ struct backend_instruction : public exec_node {
*/
bool is_volatile() const;
#else
struct backend_instruction {
struct elk_backend_instruction {
struct exec_node link;
#endif
/** @{
@@ -166,9 +166,9 @@ struct backend_instruction {
uint32_t ex_desc; /**< SEND[S] extended message descriptor immediate */
unsigned size_written; /**< Data written to the destination register in bytes. */
enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
enum brw_predicate predicate;
enum elk_opcode opcode; /* ELK_OPCODE_* or ELK_FS_OPCODE_* */
enum elk_conditional_mod conditional_mod; /**< ELK_CONDITIONAL_* */
enum elk_predicate predicate;
bool predicate_inverse:1;
bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
bool force_writemask_all:1;
@@ -177,13 +177,13 @@ struct backend_instruction {
bool saturate:1;
bool shadow_compare:1;
bool check_tdr:1; /**< Only valid for SEND; turns it into a SENDC */
bool send_has_side_effects:1; /**< Only valid for SHADER_OPCODE_SEND */
bool send_is_volatile:1; /**< Only valid for SHADER_OPCODE_SEND */
bool send_ex_desc_scratch:1; /**< Only valid for SHADER_OPCODE_SEND, use
bool send_has_side_effects:1; /**< Only valid for ELK_SHADER_OPCODE_SEND */
bool send_is_volatile:1; /**< Only valid for ELK_SHADER_OPCODE_SEND */
bool send_ex_desc_scratch:1; /**< Only valid for ELK_SHADER_OPCODE_SEND, use
* the scratch surface offset to build
* extended descriptor
*/
bool send_ex_bso:1; /**< Only for SHADER_OPCODE_SEND, use extended bindless
bool send_ex_bso:1; /**< Only for ELK_SHADER_OPCODE_SEND, use extended bindless
* surface offset (26bits instead of 20bits)
*/
bool predicate_trivial:1; /**< The predication mask applied to this
src/intel/compiler/elk/elk_ir_analysis.h
+4 -4
View File
@@ -131,19 +131,19 @@ namespace elk {
* is currently only used for validation in debug builds.
*/
template<class T, class C>
class brw_analysis {
class elk_analysis {
public:
/**
* Construct a program analysis. \p c is an arbitrary object
* passed as argument to the constructor of the analysis result
* object of type \p T.
*/
brw_analysis(const C *c) : c(c), p(NULL) {}
elk_analysis(const C *c) : c(c), p(NULL) {}
/**
* Destroy a program analysis.
*/
~brw_analysis()
~elk_analysis()
{
delete p;
}
@@ -167,7 +167,7 @@ public:
const T &
require() const
{
return const_cast<brw_analysis<T, C> *>(this)->require();
return const_cast<elk_analysis<T, C> *>(this)->require();
}
/**
src/intel/compiler/elk/elk_ir_fs.h
+110 -110
View File
@@ -27,21 +27,21 @@
#include "elk_shader.h"
class fs_inst;
class elk_fs_inst;
class fs_reg : public backend_reg {
class elk_fs_reg : public elk_backend_reg {
public:
DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
DECLARE_RALLOC_CXX_OPERATORS(elk_fs_reg)
void init();
fs_reg();
fs_reg(struct ::brw_reg reg);
fs_reg(enum brw_reg_file file, unsigned nr);
fs_reg(enum brw_reg_file file, unsigned nr, enum brw_reg_type type);
elk_fs_reg();
elk_fs_reg(struct ::elk_reg reg);
elk_fs_reg(enum elk_reg_file file, unsigned nr);
elk_fs_reg(enum elk_reg_file file, unsigned nr, enum elk_reg_type type);
bool equals(const fs_reg &r) const;
bool negative_equals(const fs_reg &r) const;
bool equals(const elk_fs_reg &r) const;
bool negative_equals(const elk_fs_reg &r) const;
bool is_contiguous() const;
/**
@@ -54,23 +54,23 @@ public:
uint8_t stride;
};
static inline fs_reg
negate(fs_reg reg)
static inline elk_fs_reg
negate(elk_fs_reg reg)
{
assert(reg.file != IMM);
reg.negate = !reg.negate;
return reg;
}
static inline fs_reg
retype(fs_reg reg, enum brw_reg_type type)
static inline elk_fs_reg
retype(elk_fs_reg reg, enum elk_reg_type type)
{
reg.type = type;
return reg;
}
static inline fs_reg
byte_offset(fs_reg reg, unsigned delta)
static inline elk_fs_reg
byte_offset(elk_fs_reg reg, unsigned delta)
{
switch (reg.file) {
case BAD_FILE:
@@ -100,8 +100,8 @@ byte_offset(fs_reg reg, unsigned delta)
return reg;
}
static inline fs_reg
horiz_offset(const fs_reg &reg, unsigned delta)
static inline elk_fs_reg
horiz_offset(const elk_fs_reg &reg, unsigned delta)
{
switch (reg.file) {
case BAD_FILE:
@@ -136,8 +136,8 @@ horiz_offset(const fs_reg &reg, unsigned delta)
unreachable("Invalid register file");
}
static inline fs_reg
offset(fs_reg reg, unsigned width, unsigned delta)
static inline elk_fs_reg
offset(elk_fs_reg reg, unsigned width, unsigned delta)
{
switch (reg.file) {
case BAD_FILE:
@@ -159,15 +159,15 @@ offset(fs_reg reg, unsigned width, unsigned delta)
* Get the scalar channel of \p reg given by \p idx and replicate it to all
* channels of the result.
*/
static inline fs_reg
component(fs_reg reg, unsigned idx)
static inline elk_fs_reg
component(elk_fs_reg reg, unsigned idx)
{
reg = horiz_offset(reg, idx);
reg.stride = 0;
if (reg.file == ARF || reg.file == FIXED_GRF) {
reg.vstride = BRW_VERTICAL_STRIDE_0;
reg.width = BRW_WIDTH_1;
reg.hstride = BRW_HORIZONTAL_STRIDE_0;
reg.vstride = ELK_VERTICAL_STRIDE_0;
reg.width = ELK_WIDTH_1;
reg.hstride = ELK_HORIZONTAL_STRIDE_0;
}
return reg;
}
@@ -181,7 +181,7 @@ component(fs_reg reg, unsigned idx)
* address spaces, one for each allocation and input attribute respectively.
*/
static inline uint32_t
reg_space(const fs_reg &r)
reg_space(const elk_fs_reg &r)
{
return r.file << 16 | (r.file == VGRF || r.file == ATTR ? r.nr : 0);
}
@@ -191,7 +191,7 @@ reg_space(const fs_reg &r)
* reg_space().
*/
static inline unsigned
reg_offset(const fs_reg &r)
reg_offset(const elk_fs_reg &r)
{
return (r.file == VGRF || r.file == IMM || r.file == ATTR ? 0 : r.nr) *
(r.file == UNIFORM ? 4 : REG_SIZE) + r.offset +
@@ -204,7 +204,7 @@ reg_offset(const fs_reg &r)
* one, or zero if components are tightly packed in the register file.
*/
static inline unsigned
reg_padding(const fs_reg &r)
reg_padding(const elk_fs_reg &r)
{
const unsigned stride = ((r.file != ARF && r.file != FIXED_GRF) ? r.stride :
r.hstride == 0 ? 0 :
@@ -214,11 +214,11 @@ reg_padding(const fs_reg &r)
/* Do not call this directly. Call regions_overlap() instead. */
static inline bool
regions_overlap_MRF(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
regions_overlap_MRF(const elk_fs_reg &r, unsigned dr, const elk_fs_reg &s, unsigned ds)
{
if (r.nr & BRW_MRF_COMPR4) {
fs_reg t = r;
t.nr &= ~BRW_MRF_COMPR4;
if (r.nr & ELK_MRF_COMPR4) {
elk_fs_reg t = r;
t.nr &= ~ELK_MRF_COMPR4;
/* COMPR4 regions are translated by the hardware during decompression
* into two separate half-regions 4 MRFs apart from each other.
*
@@ -229,7 +229,7 @@ regions_overlap_MRF(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
*/
return regions_overlap_MRF(s, ds, t, dr / 2) ||
regions_overlap_MRF(s, ds, byte_offset(t, 4 * REG_SIZE), dr / 2);
} else if (s.nr & BRW_MRF_COMPR4) {
} else if (s.nr & ELK_MRF_COMPR4) {
return regions_overlap_MRF(s, ds, r, dr);
}
@@ -243,7 +243,7 @@ regions_overlap_MRF(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
* spanning \p ds bytes.
*/
static inline bool
regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
regions_overlap(const elk_fs_reg &r, unsigned dr, const elk_fs_reg &s, unsigned ds)
{
if (r.file != s.file)
return false;
@@ -265,7 +265,7 @@ regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
* [s.offset, s.offset + ds[.
*/
static inline bool
region_contained_in(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
region_contained_in(const elk_fs_reg &r, unsigned dr, const elk_fs_reg &s, unsigned ds)
{
return reg_space(r) == reg_space(s) &&
reg_offset(r) >= reg_offset(s) &&
@@ -278,15 +278,15 @@ region_contained_in(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
* channels.
*/
static inline bool
is_periodic(const fs_reg &reg, unsigned n)
is_periodic(const elk_fs_reg &reg, unsigned n)
{
if (reg.file == BAD_FILE || reg.is_null()) {
return true;
} else if (reg.file == IMM) {
const unsigned period = (reg.type == BRW_REGISTER_TYPE_UV ||
reg.type == BRW_REGISTER_TYPE_V ? 8 :
reg.type == BRW_REGISTER_TYPE_VF ? 4 :
const unsigned period = (reg.type == ELK_REGISTER_TYPE_UV ||
reg.type == ELK_REGISTER_TYPE_V ? 8 :
reg.type == ELK_REGISTER_TYPE_VF ? 4 :
1);
return n % period == 0;
@@ -302,7 +302,7 @@ is_periodic(const fs_reg &reg, unsigned n)
}
static inline bool
is_uniform(const fs_reg &reg)
is_uniform(const elk_fs_reg &reg)
{
return is_periodic(reg, 1);
}
@@ -310,8 +310,8 @@ is_uniform(const fs_reg &reg)
/**
* Get the specified 8-component quarter of a register.
*/
static inline fs_reg
quarter(const fs_reg &reg, unsigned idx)
static inline elk_fs_reg
quarter(const elk_fs_reg &reg, unsigned idx)
{
assert(idx < 4);
return horiz_offset(reg, 8 * idx);
@@ -321,8 +321,8 @@ quarter(const fs_reg &reg, unsigned idx)
* Reinterpret each channel of register \p reg as a vector of values of the
* given smaller type and take the i-th subcomponent from each.
*/
static inline fs_reg
subscript(fs_reg reg, brw_reg_type type, unsigned i)
static inline elk_fs_reg
subscript(elk_fs_reg reg, elk_reg_type type, unsigned i)
{
assert((i + 1) * type_sz(type) <= type_sz(reg.type));
@@ -349,37 +349,37 @@ subscript(fs_reg reg, brw_reg_type type, unsigned i)
return byte_offset(retype(reg, type), i * type_sz(type));
}
static inline fs_reg
horiz_stride(fs_reg reg, unsigned s)
static inline elk_fs_reg
horiz_stride(elk_fs_reg reg, unsigned s)
{
reg.stride *= s;
return reg;
}
static const fs_reg reg_undef;
static const elk_fs_reg reg_undef;
class fs_inst : public backend_instruction {
fs_inst &operator=(const fs_inst &);
class elk_fs_inst : public elk_backend_instruction {
elk_fs_inst &operator=(const elk_fs_inst &);
void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
const fs_reg *src, unsigned sources);
void init(enum elk_opcode opcode, uint8_t exec_width, const elk_fs_reg &dst,
const elk_fs_reg *src, unsigned sources);
public:
DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
DECLARE_RALLOC_CXX_OPERATORS(elk_fs_inst)
fs_inst();
fs_inst(enum opcode opcode, uint8_t exec_size);
fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst);
fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
const fs_reg &src0);
fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
const fs_reg &src0, const fs_reg &src1);
fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
const fs_reg src[], unsigned sources);
fs_inst(const fs_inst &that);
~fs_inst();
elk_fs_inst();
elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size);
elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst);
elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst,
const elk_fs_reg &src0);
elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst,
const elk_fs_reg &src0, const elk_fs_reg &src1);
elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst,
const elk_fs_reg &src0, const elk_fs_reg &src1, const elk_fs_reg &src2);
elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst,
const elk_fs_reg src[], unsigned sources);
elk_fs_inst(const elk_fs_inst &that);
~elk_fs_inst();
void resize_sources(uint8_t num_sources);
@@ -419,10 +419,10 @@ public:
*/
bool has_sampler_residency() const;
fs_reg dst;
fs_reg *src;
elk_fs_reg dst;
elk_fs_reg *src;
uint8_t sources; /**< Number of fs_reg sources. */
uint8_t sources; /**< Number of elk_fs_reg sources. */
bool last_rt:1;
bool pi_noperspective:1; /**< Pixel interpolator noperspective flag */
@@ -435,9 +435,9 @@ public:
* Make the execution of \p inst dependent on the evaluation of a possibly
* inverted predicate.
*/
static inline fs_inst *
set_predicate_inv(enum brw_predicate pred, bool inverse,
fs_inst *inst)
static inline elk_fs_inst *
set_predicate_inv(enum elk_predicate pred, bool inverse,
elk_fs_inst *inst)
{
inst->predicate = pred;
inst->predicate_inverse = inverse;
@@ -447,8 +447,8 @@ set_predicate_inv(enum brw_predicate pred, bool inverse,
/**
* Make the execution of \p inst dependent on the evaluation of a predicate.
*/
static inline fs_inst *
set_predicate(enum brw_predicate pred, fs_inst *inst)
static inline elk_fs_inst *
set_predicate(enum elk_predicate pred, elk_fs_inst *inst)
{
return set_predicate_inv(pred, false, inst);
}
@@ -457,8 +457,8 @@ set_predicate(enum brw_predicate pred, fs_inst *inst)
* Write the result of evaluating the condition given by \p mod to a flag
* register.
*/
static inline fs_inst *
set_condmod(enum brw_conditional_mod mod, fs_inst *inst)
static inline elk_fs_inst *
set_condmod(enum elk_conditional_mod mod, elk_fs_inst *inst)
{
inst->conditional_mod = mod;
return inst;
@@ -468,8 +468,8 @@ set_condmod(enum brw_conditional_mod mod, fs_inst *inst)
* Clamp the result of \p inst to the saturation range of its destination
* datatype.
*/
static inline fs_inst *
set_saturate(bool saturate, fs_inst *inst)
static inline elk_fs_inst *
set_saturate(bool saturate, elk_fs_inst *inst)
{
inst->saturate = saturate;
return inst;
@@ -482,7 +482,7 @@ set_saturate(bool saturate, fs_inst *inst)
* UNIFORM and IMM files and 32B for all other files.
*/
inline unsigned
regs_written(const fs_inst *inst)
regs_written(const elk_fs_inst *inst)
{
assert(inst->dst.file != UNIFORM && inst->dst.file != IMM);
return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE +
@@ -498,7 +498,7 @@ regs_written(const fs_inst *inst)
* UNIFORM files and 32B for all other files.
*/
inline unsigned
regs_read(const fs_inst *inst, unsigned i)
regs_read(const elk_fs_inst *inst, unsigned i)
{
if (inst->src[i].file == IMM)
return 1;
@@ -510,27 +510,27 @@ regs_read(const fs_inst *inst, unsigned i)
reg_size);
}
static inline enum brw_reg_type
get_exec_type(const fs_inst *inst)
static inline enum elk_reg_type
get_exec_type(const elk_fs_inst *inst)
{
brw_reg_type exec_type = BRW_REGISTER_TYPE_B;
elk_reg_type exec_type = ELK_REGISTER_TYPE_B;
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].file != BAD_FILE &&
!inst->is_control_source(i)) {
const brw_reg_type t = get_exec_type(inst->src[i].type);
const elk_reg_type t = get_exec_type(inst->src[i].type);
if (type_sz(t) > type_sz(exec_type))
exec_type = t;
else if (type_sz(t) == type_sz(exec_type) &&
brw_reg_type_is_floating_point(t))
elk_reg_type_is_floating_point(t))
exec_type = t;
}
}
if (exec_type == BRW_REGISTER_TYPE_B)
if (exec_type == ELK_REGISTER_TYPE_B)
exec_type = inst->dst.type;
assert(exec_type != BRW_REGISTER_TYPE_B);
assert(exec_type != ELK_REGISTER_TYPE_B);
/* Promotion of the execution type to 32-bit for conversions from or to
* half-float seems to be consistent with the following text from the
@@ -547,23 +547,23 @@ get_exec_type(const fs_inst *inst)
*/
if (type_sz(exec_type) == 2 &&
inst->dst.type != exec_type) {
if (exec_type == BRW_REGISTER_TYPE_HF)
exec_type = BRW_REGISTER_TYPE_F;
else if (inst->dst.type == BRW_REGISTER_TYPE_HF)
exec_type = BRW_REGISTER_TYPE_D;
if (exec_type == ELK_REGISTER_TYPE_HF)
exec_type = ELK_REGISTER_TYPE_F;
else if (inst->dst.type == ELK_REGISTER_TYPE_HF)
exec_type = ELK_REGISTER_TYPE_D;
}
return exec_type;
}
static inline unsigned
get_exec_type_size(const fs_inst *inst)
get_exec_type_size(const elk_fs_inst *inst)
{
return type_sz(get_exec_type(inst));
}
static inline bool
is_send(const fs_inst *inst)
is_send(const elk_fs_inst *inst)
{
return inst->mlen || inst->is_send_from_grf();
}
@@ -573,13 +573,13 @@ is_send(const fs_inst *inst)
* assumed to complete in-order.
*/
static inline bool
is_unordered(const intel_device_info *devinfo, const fs_inst *inst)
is_unordered(const intel_device_info *devinfo, const elk_fs_inst *inst)
{
return is_send(inst) || (devinfo->ver < 20 && inst->is_math()) ||
inst->opcode == BRW_OPCODE_DPAS ||
inst->opcode == ELK_OPCODE_DPAS ||
(devinfo->has_64bit_float_via_math_pipe &&
(get_exec_type(inst) == BRW_REGISTER_TYPE_DF ||
inst->dst.type == BRW_REGISTER_TYPE_DF));
(get_exec_type(inst) == ELK_REGISTER_TYPE_DF ||
inst->dst.type == ELK_REGISTER_TYPE_DF));
}
/**
@@ -597,19 +597,19 @@ is_unordered(const intel_device_info *devinfo, const fs_inst *inst)
*/
static inline bool
has_dst_aligned_region_restriction(const intel_device_info *devinfo,
const fs_inst *inst,
brw_reg_type dst_type)
const elk_fs_inst *inst,
elk_reg_type dst_type)
{
const brw_reg_type exec_type = get_exec_type(inst);
const elk_reg_type exec_type = get_exec_type(inst);
/* Even though the hardware spec claims that "integer DWord multiply"
* operations are restricted, empirical evidence and the behavior of the
* simulator suggest that only 32x32-bit integer multiplication is
* restricted.
*/
const bool is_dword_multiply = !brw_reg_type_is_floating_point(exec_type) &&
((inst->opcode == BRW_OPCODE_MUL &&
const bool is_dword_multiply = !elk_reg_type_is_floating_point(exec_type) &&
((inst->opcode == ELK_OPCODE_MUL &&
MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4) ||
(inst->opcode == BRW_OPCODE_MAD &&
(inst->opcode == ELK_OPCODE_MAD &&
MIN2(type_sz(inst->src[1].type), type_sz(inst->src[2].type)) >= 4));
if (type_sz(dst_type) > 4 || type_sz(exec_type) > 4 ||
@@ -618,7 +618,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo,
intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125;
else if (brw_reg_type_is_floating_point(dst_type))
else if (elk_reg_type_is_floating_point(dst_type))
return devinfo->verx10 >= 125;
else
@@ -627,7 +627,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo,
static inline bool
has_dst_aligned_region_restriction(const intel_device_info *devinfo,
const fs_inst *inst)
const elk_fs_inst *inst)
{
return has_dst_aligned_region_restriction(devinfo, inst, inst->dst.type);
}
@@ -642,9 +642,9 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo,
* multiple virtual registers in any order is allowed.
*/
inline bool
is_copy_payload(brw_reg_file file, const fs_inst *inst)
is_copy_payload(elk_reg_file file, const elk_fs_inst *inst)
{
if (inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD ||
if (inst->opcode != ELK_SHADER_OPCODE_LOAD_PAYLOAD ||
inst->is_partial_write() || inst->saturate ||
inst->dst.file != VGRF)
return false;
@@ -671,9 +671,9 @@ is_copy_payload(brw_reg_file file, const fs_inst *inst)
* destination without any reordering.
*/
inline bool
is_identity_payload(brw_reg_file file, const fs_inst *inst) {
is_identity_payload(elk_reg_file file, const elk_fs_inst *inst) {
if (is_copy_payload(file, inst)) {
fs_reg reg = inst->src[0];
elk_fs_reg reg = inst->src[0];
for (unsigned i = 0; i < inst->sources; i++) {
reg.type = inst->src[i].type;
@@ -700,7 +700,7 @@ is_identity_payload(brw_reg_file file, const fs_inst *inst) {
* instructions.
*/
inline bool
is_multi_copy_payload(const fs_inst *inst) {
is_multi_copy_payload(const elk_fs_inst *inst) {
if (is_copy_payload(VGRF, inst)) {
for (unsigned i = 0; i < inst->sources; i++) {
if (inst->src[i].nr != inst->src[0].nr)
@@ -724,7 +724,7 @@ is_multi_copy_payload(const fs_inst *inst) {
* instruction.
*/
inline bool
is_coalescing_payload(const elk::simple_allocator &alloc, const fs_inst *inst)
is_coalescing_payload(const elk::simple_allocator &alloc, const elk_fs_inst *inst)
{
return is_identity_payload(VGRF, inst) &&
inst->src[0].offset == 0 &&
@@ -732,6 +732,6 @@ is_coalescing_payload(const elk::simple_allocator &alloc, const fs_inst *inst)
}
bool
has_bank_conflict(const struct brw_isa_info *isa, const fs_inst *inst);
elk_has_bank_conflict(const struct elk_isa_info *isa, const elk_fs_inst *inst);
#endif
src/intel/compiler/elk/elk_ir_performance.cpp
+256 -256
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_ir_performance.h
+3 -3
View File
@@ -25,7 +25,7 @@
#ifndef ELK_IR_PERFORMANCE_H
#define ELK_IR_PERFORMANCE_H
class fs_visitor;
class elk_fs_visitor;
namespace elk {
class vec4_visitor;
@@ -35,7 +35,7 @@ namespace elk {
* analysis.
*/
struct performance {
performance(const fs_visitor *v);
performance(const elk_fs_visitor *v);
performance(const vec4_visitor *v);
~performance();
@@ -47,7 +47,7 @@ namespace elk {
}
bool
validate(const backend_shader *) const
validate(const elk_backend_shader *) const
{
return true;
}
src/intel/compiler/elk/elk_ir_vec4.h
+66 -66
View File
@@ -31,16 +31,16 @@ namespace elk {
class dst_reg;
class src_reg : public backend_reg
class src_reg : public elk_backend_reg
{
public:
DECLARE_RALLOC_CXX_OPERATORS(src_reg)
void init();
src_reg(enum brw_reg_file file, int nr, const glsl_type *type);
src_reg(enum elk_reg_file file, int nr, const glsl_type *type);
src_reg();
src_reg(struct ::brw_reg reg);
src_reg(struct ::elk_reg reg);
bool equals(const src_reg &r) const;
bool negative_equals(const src_reg &r) const;
@@ -54,7 +54,7 @@ public:
};
static inline src_reg
retype(src_reg reg, enum brw_reg_type type)
retype(src_reg reg, enum elk_reg_type type)
{
reg.type = type;
return reg;
@@ -63,7 +63,7 @@ retype(src_reg reg, enum brw_reg_type type)
namespace detail {
static inline void
add_byte_offset(backend_reg *reg, unsigned bytes)
add_byte_offset(elk_backend_reg *reg, unsigned bytes)
{
switch (reg->file) {
case BAD_FILE:
@@ -119,15 +119,15 @@ horiz_offset(src_reg reg, unsigned delta)
/**
* Reswizzle a given source register.
* \sa brw_swizzle().
* \sa elk_swizzle().
*/
static inline src_reg
swizzle(src_reg reg, unsigned swizzle)
{
if (reg.file == IMM)
reg.ud = brw_swizzle_immediate(reg.type, reg.ud, swizzle);
reg.ud = elk_swizzle_immediate(reg.type, reg.ud, swizzle);
else
reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle);
reg.swizzle = elk_compose_swizzle(swizzle, reg.swizzle);
return reg;
}
@@ -147,7 +147,7 @@ is_uniform(const src_reg &reg)
(!reg.reladdr || is_uniform(*reg.reladdr));
}
class dst_reg : public backend_reg
class dst_reg : public elk_backend_reg
{
public:
DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
@@ -155,12 +155,12 @@ public:
void init();
dst_reg();
dst_reg(enum brw_reg_file file, int nr);
dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
dst_reg(enum elk_reg_file file, int nr);
dst_reg(enum elk_reg_file file, int nr, const glsl_type *type,
unsigned writemask);
dst_reg(enum brw_reg_file file, int nr, brw_reg_type type,
dst_reg(enum elk_reg_file file, int nr, elk_reg_type type,
unsigned writemask);
dst_reg(struct ::brw_reg reg);
dst_reg(struct ::elk_reg reg);
dst_reg(class vec4_visitor *v, const struct glsl_type *type);
explicit dst_reg(const src_reg &reg);
@@ -171,7 +171,7 @@ public:
};
static inline dst_reg
retype(dst_reg reg, enum brw_reg_type type)
retype(dst_reg reg, enum elk_reg_type type)
{
reg.type = type;
return reg;
@@ -219,7 +219,7 @@ writemask(dst_reg reg, unsigned mask)
* spaces, one for each VGRF allocation.
*/
static inline uint32_t
reg_space(const backend_reg &r)
reg_space(const elk_backend_reg &r)
{
return r.file << 16 | (r.file == VGRF ? r.nr : 0);
}
@@ -229,7 +229,7 @@ reg_space(const backend_reg &r)
* reg_space().
*/
static inline unsigned
reg_offset(const backend_reg &r)
reg_offset(const elk_backend_reg &r)
{
return (r.file == VGRF || r.file == IMM ? 0 : r.nr) *
(r.file == UNIFORM ? 16 : REG_SIZE) + r.offset +
@@ -242,21 +242,21 @@ reg_offset(const backend_reg &r)
* spanning \p ds bytes.
*/
static inline bool
regions_overlap(const backend_reg &r, unsigned dr,
const backend_reg &s, unsigned ds)
regions_overlap(const elk_backend_reg &r, unsigned dr,
const elk_backend_reg &s, unsigned ds)
{
if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) {
if (r.file == MRF && (r.nr & ELK_MRF_COMPR4)) {
/* COMPR4 regions are translated by the hardware during decompression
* into two separate half-regions 4 MRFs apart from each other.
*/
backend_reg t0 = r;
t0.nr &= ~BRW_MRF_COMPR4;
backend_reg t1 = t0;
elk_backend_reg t0 = r;
t0.nr &= ~ELK_MRF_COMPR4;
elk_backend_reg t1 = t0;
t1.offset += 4 * REG_SIZE;
return regions_overlap(t0, dr / 2, s, ds) ||
regions_overlap(t1, dr / 2, s, ds);
} else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) {
} else if (s.file == MRF && (s.nr & ELK_MRF_COMPR4)) {
return regions_overlap(s, ds, r, dr);
} else {
@@ -266,11 +266,11 @@ regions_overlap(const backend_reg &r, unsigned dr,
}
}
class vec4_instruction : public backend_instruction {
class vec4_instruction : public elk_backend_instruction {
public:
DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
vec4_instruction(enum opcode opcode,
vec4_instruction(enum elk_opcode opcode,
const dst_reg &dst = dst_reg(),
const src_reg &src0 = src_reg(),
const src_reg &src1 = src_reg(),
@@ -279,7 +279,7 @@ public:
dst_reg dst;
src_reg src[3];
enum brw_urb_write_flags urb_write_flags;
enum elk_urb_write_flags urb_write_flags;
unsigned sol_binding; /**< gfx6: SOL binding table index */
bool sol_final_write; /**< gfx6: send commit message */
@@ -300,30 +300,30 @@ public:
bool is_align1_partial_write()
{
return opcode == VEC4_OPCODE_SET_LOW_32BIT ||
opcode == VEC4_OPCODE_SET_HIGH_32BIT;
return opcode == ELK_VEC4_OPCODE_SET_LOW_32BIT ||
opcode == ELK_VEC4_OPCODE_SET_HIGH_32BIT;
}
bool reads_flag() const
{
return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
return predicate || opcode == ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
}
bool reads_flag(unsigned c)
{
if (opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2)
if (opcode == ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2)
return true;
switch (predicate) {
case BRW_PREDICATE_NONE:
case ELK_PREDICATE_NONE:
return false;
case BRW_PREDICATE_ALIGN16_REPLICATE_X:
case ELK_PREDICATE_ALIGN16_REPLICATE_X:
return c == 0;
case BRW_PREDICATE_ALIGN16_REPLICATE_Y:
case ELK_PREDICATE_ALIGN16_REPLICATE_Y:
return c == 1;
case BRW_PREDICATE_ALIGN16_REPLICATE_Z:
case ELK_PREDICATE_ALIGN16_REPLICATE_Z:
return c == 2;
case BRW_PREDICATE_ALIGN16_REPLICATE_W:
case ELK_PREDICATE_ALIGN16_REPLICATE_W:
return c == 3;
default:
return true;
@@ -332,31 +332,31 @@ public:
bool writes_flag(const intel_device_info *devinfo) const
{
return (conditional_mod && ((opcode != BRW_OPCODE_SEL || devinfo->ver <= 5) &&
opcode != BRW_OPCODE_CSEL &&
opcode != BRW_OPCODE_IF &&
opcode != BRW_OPCODE_WHILE));
return (conditional_mod && ((opcode != ELK_OPCODE_SEL || devinfo->ver <= 5) &&
opcode != ELK_OPCODE_CSEL &&
opcode != ELK_OPCODE_IF &&
opcode != ELK_OPCODE_WHILE));
}
bool reads_g0_implicitly() const
{
switch (opcode) {
case SHADER_OPCODE_TEX:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
case VS_OPCODE_PULL_CONSTANT_LOAD:
case GS_OPCODE_SET_PRIMITIVE_ID:
case GS_OPCODE_GET_INSTANCE_ID:
case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
case ELK_SHADER_OPCODE_TEX:
case ELK_SHADER_OPCODE_TXL:
case ELK_SHADER_OPCODE_TXD:
case ELK_SHADER_OPCODE_TXF:
case ELK_SHADER_OPCODE_TXF_CMS_W:
case ELK_SHADER_OPCODE_TXF_CMS:
case ELK_SHADER_OPCODE_TXF_MCS:
case ELK_SHADER_OPCODE_TXS:
case ELK_SHADER_OPCODE_TG4:
case ELK_SHADER_OPCODE_TG4_OFFSET:
case ELK_SHADER_OPCODE_SAMPLEINFO:
case ELK_VS_OPCODE_PULL_CONSTANT_LOAD:
case ELK_GS_OPCODE_SET_PRIMITIVE_ID:
case ELK_GS_OPCODE_GET_INSTANCE_ID:
case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ:
case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return true;
default:
return false;
@@ -369,7 +369,7 @@ public:
* inverted predicate.
*/
inline vec4_instruction *
set_predicate_inv(enum brw_predicate pred, bool inverse,
set_predicate_inv(enum elk_predicate pred, bool inverse,
vec4_instruction *inst)
{
inst->predicate = pred;
@@ -381,7 +381,7 @@ set_predicate_inv(enum brw_predicate pred, bool inverse,
* Make the execution of \p inst dependent on the evaluation of a predicate.
*/
inline vec4_instruction *
set_predicate(enum brw_predicate pred, vec4_instruction *inst)
set_predicate(enum elk_predicate pred, vec4_instruction *inst)
{
return set_predicate_inv(pred, false, inst);
}
@@ -391,7 +391,7 @@ set_predicate(enum brw_predicate pred, vec4_instruction *inst)
* register.
*/
inline vec4_instruction *
set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst)
set_condmod(enum elk_conditional_mod mod, vec4_instruction *inst)
{
inst->conditional_mod = mod;
return inst;
@@ -437,29 +437,29 @@ regs_read(const vec4_instruction *inst, unsigned i)
reg_size);
}
static inline enum brw_reg_type
static inline enum elk_reg_type
get_exec_type(const vec4_instruction *inst)
{
enum brw_reg_type exec_type = BRW_REGISTER_TYPE_B;
enum elk_reg_type exec_type = ELK_REGISTER_TYPE_B;
for (int i = 0; i < 3; i++) {
if (inst->src[i].file != BAD_FILE) {
const brw_reg_type t = get_exec_type(brw_reg_type(inst->src[i].type));
const elk_reg_type t = get_exec_type(elk_reg_type(inst->src[i].type));
if (type_sz(t) > type_sz(exec_type))
exec_type = t;
else if (type_sz(t) == type_sz(exec_type) &&
brw_reg_type_is_floating_point(t))
elk_reg_type_is_floating_point(t))
exec_type = t;
}
}
if (exec_type == BRW_REGISTER_TYPE_B)
if (exec_type == ELK_REGISTER_TYPE_B)
exec_type = inst->dst.type;
/* TODO: We need to handle half-float conversions. */
assert(exec_type != BRW_REGISTER_TYPE_HF ||
inst->dst.type == BRW_REGISTER_TYPE_HF);
assert(exec_type != BRW_REGISTER_TYPE_B);
assert(exec_type != ELK_REGISTER_TYPE_HF ||
inst->dst.type == ELK_REGISTER_TYPE_HF);
assert(exec_type != ELK_REGISTER_TYPE_B);
return exec_type;
}
src/intel/compiler/elk/elk_isa_info.h
+19 -19
View File
@@ -30,22 +30,22 @@
extern "C" {
#endif
struct opcode_desc;
struct elk_opcode_desc;
struct brw_isa_info {
struct elk_isa_info {
const struct intel_device_info *devinfo;
/* A mapping from enum opcode to the corresponding opcode_desc */
const struct opcode_desc *ir_to_descs[NUM_BRW_OPCODES];
/* A mapping from enum elk_opcode to the corresponding opcode_desc */
const struct elk_opcode_desc *ir_to_descs[NUM_ELK_OPCODES];
/** A mapping from a HW opcode encoding to the corresponding opcode_desc */
const struct opcode_desc *hw_to_descs[128];
const struct elk_opcode_desc *hw_to_descs[128];
};
void brw_init_isa_info(struct brw_isa_info *isa,
void elk_init_isa_info(struct elk_isa_info *isa,
const struct intel_device_info *devinfo);
struct opcode_desc {
struct elk_opcode_desc {
unsigned ir;
unsigned hw;
const char *name;
@@ -54,29 +54,29 @@ struct opcode_desc {
int gfx_vers;
};
const struct opcode_desc *
brw_opcode_desc(const struct brw_isa_info *isa, enum opcode opcode);
const struct elk_opcode_desc *
elk_opcode_desc(const struct elk_isa_info *isa, enum elk_opcode opcode);
const struct opcode_desc *
brw_opcode_desc_from_hw(const struct brw_isa_info *isa, unsigned hw);
const struct elk_opcode_desc *
elk_opcode_desc_from_hw(const struct elk_isa_info *isa, unsigned hw);
static inline unsigned
brw_opcode_encode(const struct brw_isa_info *isa, enum opcode opcode)
elk_opcode_encode(const struct elk_isa_info *isa, enum elk_opcode opcode)
{
return brw_opcode_desc(isa, opcode)->hw;
return elk_opcode_desc(isa, opcode)->hw;
}
static inline enum opcode
brw_opcode_decode(const struct brw_isa_info *isa, unsigned hw)
static inline enum elk_opcode
elk_opcode_decode(const struct elk_isa_info *isa, unsigned hw)
{
const struct opcode_desc *desc = brw_opcode_desc_from_hw(isa, hw);
return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
const struct elk_opcode_desc *desc = elk_opcode_desc_from_hw(isa, hw);
return desc ? (enum elk_opcode)desc->ir : ELK_OPCODE_ILLEGAL;
}
static inline bool
is_3src(const struct brw_isa_info *isa, enum opcode opcode)
elk_is_3src(const struct elk_isa_info *isa, enum elk_opcode opcode)
{
const struct opcode_desc *desc = brw_opcode_desc(isa, opcode);
const struct elk_opcode_desc *desc = elk_opcode_desc(isa, opcode);
return desc && desc->nsrc == 3;
}
src/intel/compiler/elk/elk_lex.l
+127 -127
View File
@@ -51,122 +51,122 @@ extern char *input_filename;
null { BEGIN(REG); return NULL_TOKEN; }
/* Opcodes */
add { yylval.integer = BRW_OPCODE_ADD; return ADD; }
add3 { yylval.integer = BRW_OPCODE_ADD3; return ADD3; }
addc { yylval.integer = BRW_OPCODE_ADDC; return ADDC; }
and { yylval.integer = BRW_OPCODE_AND; return AND; }
asr { yylval.integer = BRW_OPCODE_ASR; return ASR; }
avg { yylval.integer = BRW_OPCODE_AVG; return AVG; }
bfe { yylval.integer = BRW_OPCODE_BFE; return BFE; }
bfi1 { yylval.integer = BRW_OPCODE_BFI1; return BFI1; }
bfi2 { yylval.integer = BRW_OPCODE_BFI2; return BFI2; }
bfrev { yylval.integer = BRW_OPCODE_BFREV; return BFREV; }
brc { yylval.integer = BRW_OPCODE_BRC; return BRC; }
brd { yylval.integer = BRW_OPCODE_BRD; return BRD; }
break { yylval.integer = BRW_OPCODE_BREAK; return BREAK; }
call { yylval.integer = BRW_OPCODE_CALL; return CALL; }
calla { yylval.integer = BRW_OPCODE_CALLA; return CALLA; }
case { yylval.integer = BRW_OPCODE_CASE; return CASE; }
cbit { yylval.integer = BRW_OPCODE_CBIT; return CBIT; }
cmp { yylval.integer = BRW_OPCODE_CMP; return CMP; }
cmpn { yylval.integer = BRW_OPCODE_CMPN; return CMPN; }
cont { yylval.integer = BRW_OPCODE_CONTINUE; return CONT; }
csel { yylval.integer = BRW_OPCODE_CSEL; return CSEL; }
dim { yylval.integer = BRW_OPCODE_DIM; return DIM; }
do { yylval.integer = BRW_OPCODE_DO; return DO; }
dp2 { yylval.integer = BRW_OPCODE_DP2; return DP2; }
dp3 { yylval.integer = BRW_OPCODE_DP3; return DP3; }
dp4 { yylval.integer = BRW_OPCODE_DP4; return DP4; }
dp4a { yylval.integer = BRW_OPCODE_DP4A; return DP4A; }
dph { yylval.integer = BRW_OPCODE_DPH; return DPH; }
else { yylval.integer = BRW_OPCODE_ELSE; return ELSE; }
endif { yylval.integer = BRW_OPCODE_ENDIF; return ENDIF; }
f16to32 { yylval.integer = BRW_OPCODE_F16TO32; return F16TO32; }
f32to16 { yylval.integer = BRW_OPCODE_F32TO16; return F32TO16; }
fbh { yylval.integer = BRW_OPCODE_FBH; return FBH; }
fbl { yylval.integer = BRW_OPCODE_FBL; return FBL; }
fork { yylval.integer = BRW_OPCODE_FORK; return FORK; }
frc { yylval.integer = BRW_OPCODE_FRC; return FRC; }
goto { yylval.integer = BRW_OPCODE_GOTO; return GOTO; }
halt { yylval.integer = BRW_OPCODE_HALT; return HALT; }
if { yylval.integer = BRW_OPCODE_IF; return IF; }
iff { yylval.integer = BRW_OPCODE_IFF; return IFF; }
illegal { yylval.integer = BRW_OPCODE_ILLEGAL; return ILLEGAL; }
jmpi { yylval.integer = BRW_OPCODE_JMPI; return JMPI; }
line { yylval.integer = BRW_OPCODE_LINE; return LINE; }
lrp { yylval.integer = BRW_OPCODE_LRP; return LRP; }
lzd { yylval.integer = BRW_OPCODE_LZD; return LZD; }
mac { yylval.integer = BRW_OPCODE_MAC; return MAC; }
mach { yylval.integer = BRW_OPCODE_MACH; return MACH; }
mad { yylval.integer = BRW_OPCODE_MAD; return MAD; }
madm { yylval.integer = BRW_OPCODE_MADM; return MADM; }
mov { yylval.integer = BRW_OPCODE_MOV; return MOV; }
movi { yylval.integer = BRW_OPCODE_MOVI; return MOVI; }
mul { yylval.integer = BRW_OPCODE_MUL; return MUL; }
mrest { yylval.integer = BRW_OPCODE_MREST; return MREST; }
msave { yylval.integer = BRW_OPCODE_MSAVE; return MSAVE; }
nenop { yylval.integer = BRW_OPCODE_NENOP; return NENOP; }
nop { yylval.integer = BRW_OPCODE_NOP; return NOP; }
not { yylval.integer = BRW_OPCODE_NOT; return NOT; }
or { yylval.integer = BRW_OPCODE_OR; return OR; }
pln { yylval.integer = BRW_OPCODE_PLN; return PLN; }
pop { yylval.integer = BRW_OPCODE_POP; return POP; }
push { yylval.integer = BRW_OPCODE_PUSH; return PUSH; }
ret { yylval.integer = BRW_OPCODE_RET; return RET; }
rndd { yylval.integer = BRW_OPCODE_RNDD; return RNDD; }
rnde { yylval.integer = BRW_OPCODE_RNDE; return RNDE; }
rndu { yylval.integer = BRW_OPCODE_RNDU; return RNDU; }
rndz { yylval.integer = BRW_OPCODE_RNDZ; return RNDZ; }
rol { yylval.integer = BRW_OPCODE_ROL; return ROL; }
ror { yylval.integer = BRW_OPCODE_ROR; return ROR; }
sad2 { yylval.integer = BRW_OPCODE_SAD2; return SAD2; }
sada2 { yylval.integer = BRW_OPCODE_SADA2; return SADA2; }
sel { yylval.integer = BRW_OPCODE_SEL; return SEL; }
add { yylval.integer = ELK_OPCODE_ADD; return ADD; }
add3 { yylval.integer = ELK_OPCODE_ADD3; return ADD3; }
addc { yylval.integer = ELK_OPCODE_ADDC; return ADDC; }
and { yylval.integer = ELK_OPCODE_AND; return AND; }
asr { yylval.integer = ELK_OPCODE_ASR; return ASR; }
avg { yylval.integer = ELK_OPCODE_AVG; return AVG; }
bfe { yylval.integer = ELK_OPCODE_BFE; return BFE; }
bfi1 { yylval.integer = ELK_OPCODE_BFI1; return BFI1; }
bfi2 { yylval.integer = ELK_OPCODE_BFI2; return BFI2; }
bfrev { yylval.integer = ELK_OPCODE_BFREV; return BFREV; }
brc { yylval.integer = ELK_OPCODE_BRC; return BRC; }
brd { yylval.integer = ELK_OPCODE_BRD; return BRD; }
break { yylval.integer = ELK_OPCODE_BREAK; return BREAK; }
call { yylval.integer = ELK_OPCODE_CALL; return CALL; }
calla { yylval.integer = ELK_OPCODE_CALLA; return CALLA; }
case { yylval.integer = ELK_OPCODE_CASE; return CASE; }
cbit { yylval.integer = ELK_OPCODE_CBIT; return CBIT; }
cmp { yylval.integer = ELK_OPCODE_CMP; return CMP; }
cmpn { yylval.integer = ELK_OPCODE_CMPN; return CMPN; }
cont { yylval.integer = ELK_OPCODE_CONTINUE; return CONT; }
csel { yylval.integer = ELK_OPCODE_CSEL; return CSEL; }
dim { yylval.integer = ELK_OPCODE_DIM; return DIM; }
do { yylval.integer = ELK_OPCODE_DO; return DO; }
dp2 { yylval.integer = ELK_OPCODE_DP2; return DP2; }
dp3 { yylval.integer = ELK_OPCODE_DP3; return DP3; }
dp4 { yylval.integer = ELK_OPCODE_DP4; return DP4; }
dp4a { yylval.integer = ELK_OPCODE_DP4A; return DP4A; }
dph { yylval.integer = ELK_OPCODE_DPH; return DPH; }
else { yylval.integer = ELK_OPCODE_ELSE; return ELSE; }
endif { yylval.integer = ELK_OPCODE_ENDIF; return ENDIF; }
f16to32 { yylval.integer = ELK_OPCODE_F16TO32; return F16TO32; }
f32to16 { yylval.integer = ELK_OPCODE_F32TO16; return F32TO16; }
fbh { yylval.integer = ELK_OPCODE_FBH; return FBH; }
fbl { yylval.integer = ELK_OPCODE_FBL; return FBL; }
fork { yylval.integer = ELK_OPCODE_FORK; return FORK; }
frc { yylval.integer = ELK_OPCODE_FRC; return FRC; }
goto { yylval.integer = ELK_OPCODE_GOTO; return GOTO; }
halt { yylval.integer = ELK_OPCODE_HALT; return HALT; }
if { yylval.integer = ELK_OPCODE_IF; return IF; }
iff { yylval.integer = ELK_OPCODE_IFF; return IFF; }
illegal { yylval.integer = ELK_OPCODE_ILLEGAL; return ILLEGAL; }
jmpi { yylval.integer = ELK_OPCODE_JMPI; return JMPI; }
line { yylval.integer = ELK_OPCODE_LINE; return LINE; }
lrp { yylval.integer = ELK_OPCODE_LRP; return LRP; }
lzd { yylval.integer = ELK_OPCODE_LZD; return LZD; }
mac { yylval.integer = ELK_OPCODE_MAC; return MAC; }
mach { yylval.integer = ELK_OPCODE_MACH; return MACH; }
mad { yylval.integer = ELK_OPCODE_MAD; return MAD; }
madm { yylval.integer = ELK_OPCODE_MADM; return MADM; }
mov { yylval.integer = ELK_OPCODE_MOV; return MOV; }
movi { yylval.integer = ELK_OPCODE_MOVI; return MOVI; }
mul { yylval.integer = ELK_OPCODE_MUL; return MUL; }
mrest { yylval.integer = ELK_OPCODE_MREST; return MREST; }
msave { yylval.integer = ELK_OPCODE_MSAVE; return MSAVE; }
nenop { yylval.integer = ELK_OPCODE_NENOP; return NENOP; }
nop { yylval.integer = ELK_OPCODE_NOP; return NOP; }
not { yylval.integer = ELK_OPCODE_NOT; return NOT; }
or { yylval.integer = ELK_OPCODE_OR; return OR; }
pln { yylval.integer = ELK_OPCODE_PLN; return PLN; }
pop { yylval.integer = ELK_OPCODE_POP; return POP; }
push { yylval.integer = ELK_OPCODE_PUSH; return PUSH; }
ret { yylval.integer = ELK_OPCODE_RET; return RET; }
rndd { yylval.integer = ELK_OPCODE_RNDD; return RNDD; }
rnde { yylval.integer = ELK_OPCODE_RNDE; return RNDE; }
rndu { yylval.integer = ELK_OPCODE_RNDU; return RNDU; }
rndz { yylval.integer = ELK_OPCODE_RNDZ; return RNDZ; }
rol { yylval.integer = ELK_OPCODE_ROL; return ROL; }
ror { yylval.integer = ELK_OPCODE_ROR; return ROR; }
sad2 { yylval.integer = ELK_OPCODE_SAD2; return SAD2; }
sada2 { yylval.integer = ELK_OPCODE_SADA2; return SADA2; }
sel { yylval.integer = ELK_OPCODE_SEL; return SEL; }
send {
yylval.integer = BRW_OPCODE_SEND;
yylval.integer = ELK_OPCODE_SEND;
return p->devinfo->ver < 12 ? SEND_GFX4 : SEND_GFX12;
}
sendc {
yylval.integer = BRW_OPCODE_SENDC;
yylval.integer = ELK_OPCODE_SENDC;
return p->devinfo->ver < 12 ? SENDC_GFX4 : SENDC_GFX12;
}
sends { yylval.integer = BRW_OPCODE_SENDS; return SENDS; }
sendsc { yylval.integer = BRW_OPCODE_SENDSC; return SENDSC; }
shl { yylval.integer = BRW_OPCODE_SHL; return SHL; }
shr { yylval.integer = BRW_OPCODE_SHR; return SHR; }
smov { yylval.integer = BRW_OPCODE_SMOV; return SMOV; }
subb { yylval.integer = BRW_OPCODE_SUBB; return SUBB; }
wait { yylval.integer = BRW_OPCODE_WAIT; return WAIT; }
while { yylval.integer = BRW_OPCODE_WHILE; return WHILE; }
xor { yylval.integer = BRW_OPCODE_XOR; return XOR; }
sync { yylval.integer = BRW_OPCODE_SYNC; return SYNC; }
sends { yylval.integer = ELK_OPCODE_SENDS; return SENDS; }
sendsc { yylval.integer = ELK_OPCODE_SENDSC; return SENDSC; }
shl { yylval.integer = ELK_OPCODE_SHL; return SHL; }
shr { yylval.integer = ELK_OPCODE_SHR; return SHR; }
smov { yylval.integer = ELK_OPCODE_SMOV; return SMOV; }
subb { yylval.integer = ELK_OPCODE_SUBB; return SUBB; }
wait { yylval.integer = ELK_OPCODE_WAIT; return WAIT; }
while { yylval.integer = ELK_OPCODE_WHILE; return WHILE; }
xor { yylval.integer = ELK_OPCODE_XOR; return XOR; }
sync { yylval.integer = ELK_OPCODE_SYNC; return SYNC; }
/* extended math functions */
cos { yylval.integer = BRW_MATH_FUNCTION_COS; return COS; }
exp { yylval.integer = BRW_MATH_FUNCTION_EXP; return EXP; }
fdiv { yylval.integer = BRW_MATH_FUNCTION_FDIV; return FDIV; }
inv { yylval.integer = BRW_MATH_FUNCTION_INV; return INV; }
cos { yylval.integer = ELK_MATH_FUNCTION_COS; return COS; }
exp { yylval.integer = ELK_MATH_FUNCTION_EXP; return EXP; }
fdiv { yylval.integer = ELK_MATH_FUNCTION_FDIV; return FDIV; }
inv { yylval.integer = ELK_MATH_FUNCTION_INV; return INV; }
invm { yylval.integer = GFX8_MATH_FUNCTION_INVM; return INVM; }
intdiv {
yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
yylval.integer = ELK_MATH_FUNCTION_INT_DIV_QUOTIENT;
return INTDIV;
}
intdivmod {
yylval.integer =
BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER;
ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER;
return INTDIVMOD;
}
intmod {
yylval.integer = BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
yylval.integer = ELK_MATH_FUNCTION_INT_DIV_REMAINDER;
return INTMOD;
}
log { yylval.integer = BRW_MATH_FUNCTION_LOG; return LOG; }
pow { yylval.integer = BRW_MATH_FUNCTION_POW; return POW; }
rsq { yylval.integer = BRW_MATH_FUNCTION_RSQ; return RSQ; }
log { yylval.integer = ELK_MATH_FUNCTION_LOG; return LOG; }
pow { yylval.integer = ELK_MATH_FUNCTION_POW; return POW; }
rsq { yylval.integer = ELK_MATH_FUNCTION_RSQ; return RSQ; }
rsqrtm { yylval.integer = GFX8_MATH_FUNCTION_RSQRTM; return RSQRTM; }
sin { yylval.integer = BRW_MATH_FUNCTION_SIN; return SIN; }
sqrt { yylval.integer = BRW_MATH_FUNCTION_SQRT; return SQRT; }
sincos { yylval.integer = BRW_MATH_FUNCTION_SINCOS; return SINCOS; }
sin { yylval.integer = ELK_MATH_FUNCTION_SIN; return SIN; }
sqrt { yylval.integer = ELK_MATH_FUNCTION_SQRT; return SQRT; }
sincos { yylval.integer = ELK_MATH_FUNCTION_SINCOS; return SINCOS; }
/* sync instruction */
allrd { yylval.integer = TGL_SYNC_ALLRD; return ALLRD; }
@@ -225,10 +225,10 @@ ugm { return UGM; }
<REG>"." { BEGIN(DOTSEL); return DOT; }
<REG>";" { return SEMICOLON; }
<DOTSEL>"x" { yylval.integer = BRW_CHANNEL_X; return X; }
<DOTSEL>"y" { yylval.integer = BRW_CHANNEL_Y; return Y; }
<DOTSEL>"z" { yylval.integer = BRW_CHANNEL_Z; return Z; }
<DOTSEL>"w" { yylval.integer = BRW_CHANNEL_W; return W; }
<DOTSEL>"x" { yylval.integer = ELK_CHANNEL_X; return X; }
<DOTSEL>"y" { yylval.integer = ELK_CHANNEL_Y; return Y; }
<DOTSEL>"z" { yylval.integer = ELK_CHANNEL_Z; return Z; }
<DOTSEL>"w" { yylval.integer = ELK_CHANNEL_W; return W; }
<DOTSEL>[0-9][0-9]* {
yylval.integer = strtoul(yytext, NULL, 10);
BEGIN(REG);
@@ -264,10 +264,10 @@ EOT { return EOT; }
nomask { return MASK_DISABLE; }
/* Channel */
<CHANNEL>"x" { yylval.integer = BRW_CHANNEL_X; return X; }
<CHANNEL>"y" { yylval.integer = BRW_CHANNEL_Y; return Y; }
<CHANNEL>"z" { yylval.integer = BRW_CHANNEL_Z; return Z; }
<CHANNEL>"w" { yylval.integer = BRW_CHANNEL_W; return W; }
<CHANNEL>"x" { yylval.integer = ELK_CHANNEL_X; return X; }
<CHANNEL>"y" { yylval.integer = ELK_CHANNEL_Y; return Y; }
<CHANNEL>"z" { yylval.integer = ELK_CHANNEL_Z; return Z; }
<CHANNEL>"w" { yylval.integer = ELK_CHANNEL_W; return W; }
<CHANNEL>[0-9][0-9]* {
yylval.integer = strtoul(yytext, NULL, 10);
return INTEGER;
@@ -277,18 +277,18 @@ nomask { return MASK_DISABLE; }
/* Predicate Control */
<CHANNEL>".anyv" { yylval.integer = BRW_PREDICATE_ALIGN1_ANYV; return ANYV; }
<CHANNEL>".allv" { yylval.integer = BRW_PREDICATE_ALIGN1_ALLV; return ALLV; }
<CHANNEL>".any2h" { yylval.integer = BRW_PREDICATE_ALIGN1_ANY2H; return ANY2H; }
<CHANNEL>".all2h" { yylval.integer = BRW_PREDICATE_ALIGN1_ALL2H; return ALL2H; }
<CHANNEL>".any4h" { yylval.integer = BRW_PREDICATE_ALIGN16_ANY4H; return ANY4H; }
<CHANNEL>".all4h" { yylval.integer = BRW_PREDICATE_ALIGN16_ALL4H; return ALL4H; }
<CHANNEL>".any8h" { yylval.integer = BRW_PREDICATE_ALIGN1_ANY8H; return ANY8H; }
<CHANNEL>".all8h" { yylval.integer = BRW_PREDICATE_ALIGN1_ALL8H; return ALL8H; }
<CHANNEL>".any16h" { yylval.integer = BRW_PREDICATE_ALIGN1_ANY16H; return ANY16H; }
<CHANNEL>".all16h" { yylval.integer = BRW_PREDICATE_ALIGN1_ALL16H; return ALL16H; }
<CHANNEL>".any32h" { yylval.integer = BRW_PREDICATE_ALIGN1_ANY32H; return ANY32H; }
<CHANNEL>".all32h" { yylval.integer = BRW_PREDICATE_ALIGN1_ALL32H; return ALL32H; }
<CHANNEL>".anyv" { yylval.integer = ELK_PREDICATE_ALIGN1_ANYV; return ANYV; }
<CHANNEL>".allv" { yylval.integer = ELK_PREDICATE_ALIGN1_ALLV; return ALLV; }
<CHANNEL>".any2h" { yylval.integer = ELK_PREDICATE_ALIGN1_ANY2H; return ANY2H; }
<CHANNEL>".all2h" { yylval.integer = ELK_PREDICATE_ALIGN1_ALL2H; return ALL2H; }
<CHANNEL>".any4h" { yylval.integer = ELK_PREDICATE_ALIGN16_ANY4H; return ANY4H; }
<CHANNEL>".all4h" { yylval.integer = ELK_PREDICATE_ALIGN16_ALL4H; return ALL4H; }
<CHANNEL>".any8h" { yylval.integer = ELK_PREDICATE_ALIGN1_ANY8H; return ANY8H; }
<CHANNEL>".all8h" { yylval.integer = ELK_PREDICATE_ALIGN1_ALL8H; return ALL8H; }
<CHANNEL>".any16h" { yylval.integer = ELK_PREDICATE_ALIGN1_ANY16H; return ANY16H; }
<CHANNEL>".all16h" { yylval.integer = ELK_PREDICATE_ALIGN1_ALL16H; return ALL16H; }
<CHANNEL>".any32h" { yylval.integer = ELK_PREDICATE_ALIGN1_ANY32H; return ANY32H; }
<CHANNEL>".all32h" { yylval.integer = ELK_PREDICATE_ALIGN1_ALL32H; return ALL32H; }
/* Saturation */
".sat" { return SATURATE; }
@@ -375,17 +375,17 @@ sr[0-9]+ { yylval.integer = atoi(yytext + 2); return STATEREG; }
"mask"[0-9]+ { yylval.integer = atoi(yytext + 4); return MASKREG; }
/* Conditional modifiers */
".e" { yylval.integer = BRW_CONDITIONAL_Z; return EQUAL; }
".g" { yylval.integer = BRW_CONDITIONAL_G; return GREATER; }
".ge" { yylval.integer = BRW_CONDITIONAL_GE; return GREATER_EQUAL; }
".l" { yylval.integer = BRW_CONDITIONAL_L; return LESS; }
".le" { yylval.integer = BRW_CONDITIONAL_LE; return LESS_EQUAL; }
".ne" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_EQUAL; }
".nz" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_ZERO; }
".o" { yylval.integer = BRW_CONDITIONAL_O; return OVERFLOW; }
".r" { yylval.integer = BRW_CONDITIONAL_R; return ROUND_INCREMENT; }
".u" { yylval.integer = BRW_CONDITIONAL_U; return UNORDERED; }
".z" { yylval.integer = BRW_CONDITIONAL_Z; return ZERO; }
".e" { yylval.integer = ELK_CONDITIONAL_Z; return EQUAL; }
".g" { yylval.integer = ELK_CONDITIONAL_G; return GREATER; }
".ge" { yylval.integer = ELK_CONDITIONAL_GE; return GREATER_EQUAL; }
".l" { yylval.integer = ELK_CONDITIONAL_L; return LESS; }
".le" { yylval.integer = ELK_CONDITIONAL_LE; return LESS_EQUAL; }
".ne" { yylval.integer = ELK_CONDITIONAL_NZ; return NOT_EQUAL; }
".nz" { yylval.integer = ELK_CONDITIONAL_NZ; return NOT_ZERO; }
".o" { yylval.integer = ELK_CONDITIONAL_O; return OVERFLOW; }
".r" { yylval.integer = ELK_CONDITIONAL_R; return ROUND_INCREMENT; }
".u" { yylval.integer = ELK_CONDITIONAL_U; return UNORDERED; }
".z" { yylval.integer = ELK_CONDITIONAL_Z; return ZERO; }
/* Eat up JIP and UIP token, their values will be parsed
* in numeric section
src/intel/compiler/elk/elk_lower_logical_sends.cpp
+670 -670
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_nir.c
+102 -102
View File
@@ -234,7 +234,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
}
void
brw_nir_lower_vs_inputs(nir_shader *nir,
elk_nir_lower_vs_inputs(nir_shader *nir,
bool edgeflag_is_last,
const uint8_t *vs_attrib_wa_flags)
{
@@ -246,7 +246,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
* loaded as one vec4 or dvec4 per element (or matrix column), depending on
* whether it is a double-precision type or not.
*/
nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
nir_lower_io(nir, nir_var_shader_in, elk_type_size_vec4,
nir_lower_io_lower_64bit_to_32);
/* This pass needs actual constants */
@@ -254,7 +254,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
brw_nir_apply_attribute_workarounds(nir, vs_attrib_wa_flags);
elk_nir_apply_attribute_workarounds(nir, vs_attrib_wa_flags);
/* The last step is to remap VERT_ATTRIB_* to actual registers */
@@ -365,14 +365,14 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
}
void
brw_nir_lower_vue_inputs(nir_shader *nir,
elk_nir_lower_vue_inputs(nir_shader *nir,
const struct intel_vue_map *vue_map)
{
nir_foreach_shader_in_variable(var, nir)
var->data.driver_location = var->data.location;
/* Inputs are stored in vec4 slots, so use type_size_vec4(). */
nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
/* Inputs are stored in vec4 slots, so use elk_type_size_vec4(). */
nir_lower_io(nir, nir_var_shader_in, elk_type_size_vec4,
nir_lower_io_lower_64bit_to_32);
/* This pass needs actual constants */
@@ -415,12 +415,12 @@ brw_nir_lower_vue_inputs(nir_shader *nir,
}
void
brw_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue_map)
elk_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue_map)
{
nir_foreach_shader_in_variable(var, nir)
var->data.driver_location = var->data.location;
nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
nir_lower_io(nir, nir_var_shader_in, elk_type_size_vec4,
nir_lower_io_lower_64bit_to_32);
/* This pass needs actual constants */
@@ -490,9 +490,9 @@ lower_barycentric_at_offset(nir_builder *b, nir_intrinsic_instr *intrin,
}
void
brw_nir_lower_fs_inputs(nir_shader *nir,
elk_nir_lower_fs_inputs(nir_shader *nir,
const struct intel_device_info *devinfo,
const struct brw_wm_prog_key *key)
const struct elk_wm_prog_key *key)
{
nir_foreach_shader_in_variable(var, nir) {
var->data.driver_location = var->data.location;
@@ -521,14 +521,14 @@ brw_nir_lower_fs_inputs(nir_shader *nir,
}
}
nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
nir_lower_io(nir, nir_var_shader_in, elk_type_size_vec4,
nir_lower_io_lower_64bit_to_32);
if (devinfo->ver >= 11)
nir_lower_interpolation(nir, ~0);
if (key->multisample_fbo == BRW_NEVER) {
if (key->multisample_fbo == ELK_NEVER) {
nir_lower_single_sampled(nir);
} else if (key->persample_interp == BRW_ALWAYS) {
} else if (key->persample_interp == ELK_ALWAYS) {
nir_shader_intrinsics_pass(nir, lower_barycentric_per_sample,
nir_metadata_block_index |
nir_metadata_dominance,
@@ -547,25 +547,25 @@ brw_nir_lower_fs_inputs(nir_shader *nir,
}
void
brw_nir_lower_vue_outputs(nir_shader *nir)
elk_nir_lower_vue_outputs(nir_shader *nir)
{
nir_foreach_shader_out_variable(var, nir) {
var->data.driver_location = var->data.location;
}
nir_lower_io(nir, nir_var_shader_out, type_size_vec4,
nir_lower_io(nir, nir_var_shader_out, elk_type_size_vec4,
nir_lower_io_lower_64bit_to_32);
}
void
brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue_map,
elk_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue_map,
enum tess_primitive_mode tes_primitive_mode)
{
nir_foreach_shader_out_variable(var, nir) {
var->data.driver_location = var->data.location;
}
nir_lower_io(nir, nir_var_shader_out, type_size_vec4,
nir_lower_io(nir, nir_var_shader_out, elk_type_size_vec4,
nir_lower_io_lower_64bit_to_32);
/* This pass needs actual constants */
@@ -582,15 +582,15 @@ brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue_map,
}
void
brw_nir_lower_fs_outputs(nir_shader *nir)
elk_nir_lower_fs_outputs(nir_shader *nir)
{
nir_foreach_shader_out_variable(var, nir) {
var->data.driver_location =
SET_FIELD(var->data.index, BRW_NIR_FRAG_OUTPUT_INDEX) |
SET_FIELD(var->data.location, BRW_NIR_FRAG_OUTPUT_LOCATION);
SET_FIELD(var->data.index, ELK_NIR_FRAG_OUTPUT_INDEX) |
SET_FIELD(var->data.location, ELK_NIR_FRAG_OUTPUT_LOCATION);
}
nir_lower_io(nir, nir_var_shader_out, type_size_dvec4, 0);
nir_lower_io(nir, nir_var_shader_out, elk_type_size_dvec4, 0);
}
#define OPT(pass, ...) ({ \
@@ -602,7 +602,7 @@ brw_nir_lower_fs_outputs(nir_shader *nir)
})
void
brw_nir_optimize(nir_shader *nir, bool is_scalar,
elk_nir_optimize(nir_shader *nir, bool is_scalar,
const struct intel_device_info *devinfo)
{
bool progress;
@@ -729,7 +729,7 @@ brw_nir_optimize(nir_shader *nir, bool is_scalar,
static unsigned
lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
{
const struct brw_compiler *compiler = (const struct brw_compiler *) data;
const struct elk_compiler *compiler = (const struct elk_compiler *) data;
const struct intel_device_info *devinfo = compiler->devinfo;
switch (instr->type) {
@@ -888,15 +888,15 @@ lower_xehp_tg4_offset_filter(const nir_instr *instr, UNUSED const void *data)
* it is not at all generator-specific.
*/
void
brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
const struct brw_nir_compiler_opts *opts)
elk_preprocess_nir(const struct elk_compiler *compiler, nir_shader *nir,
const struct elk_nir_compiler_opts *opts)
{
const struct intel_device_info *devinfo = compiler->devinfo;
UNUSED bool progress; /* Written by OPT */
const bool is_scalar = compiler->scalar_stage[nir->info.stage];
nir_validate_ssa_dominance(nir, "before brw_preprocess_nir");
nir_validate_ssa_dominance(nir, "before elk_preprocess_nir");
OPT(nir_lower_frexp);
@@ -907,10 +907,10 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
if (nir->info.stage == MESA_SHADER_GEOMETRY)
OPT(nir_lower_gs_intrinsics, 0);
/* See also brw_nir_trig_workarounds.py */
/* See also elk_nir_trig_workarounds.py */
if (compiler->precise_trig &&
!(devinfo->ver >= 10 || devinfo->platform == INTEL_PLATFORM_KBL))
OPT(brw_nir_apply_trig_workarounds);
OPT(elk_nir_apply_trig_workarounds);
/* This workaround existing for performance reasons. Since it requires not
* setting RENDER_SURFACE_STATE::SurfaceArray when the array length is 1,
@@ -953,7 +953,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
OPT(nir_split_var_copies);
OPT(nir_split_struct_vars, nir_var_function_temp);
brw_nir_optimize(nir, is_scalar, devinfo);
elk_nir_optimize(nir, is_scalar, devinfo);
OPT(nir_lower_doubles, opts->softfp64, nir->options->lower_doubles_options);
if (OPT(nir_lower_int64_float_conversions)) {
@@ -998,7 +998,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
OPT(nir_lower_subgroups, &subgroups_options);
nir_variable_mode indirect_mask =
brw_nir_no_indirect_mask(compiler, nir->info.stage);
elk_nir_no_indirect_mask(compiler, nir->info.stage);
OPT(nir_lower_indirect_derefs, indirect_mask, UINT32_MAX);
/* Even in cases where we can handle indirect temporaries via scratch, we
@@ -1037,11 +1037,11 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
OPT(intel_nir_clamp_per_vertex_loads);
/* Get rid of split copies */
brw_nir_optimize(nir, is_scalar, devinfo);
elk_nir_optimize(nir, is_scalar, devinfo);
}
static bool
brw_nir_zero_inputs_instr(struct nir_builder *b, nir_intrinsic_instr *intrin,
elk_nir_zero_inputs_instr(struct nir_builder *b, nir_intrinsic_instr *intrin,
void *data)
{
if (intrin->intrinsic != nir_intrinsic_load_deref)
@@ -1072,15 +1072,15 @@ brw_nir_zero_inputs_instr(struct nir_builder *b, nir_intrinsic_instr *intrin,
}
static bool
brw_nir_zero_inputs(nir_shader *shader, uint64_t *zero_inputs)
elk_nir_zero_inputs(nir_shader *shader, uint64_t *zero_inputs)
{
return nir_shader_intrinsics_pass(shader, brw_nir_zero_inputs_instr,
return nir_shader_intrinsics_pass(shader, elk_nir_zero_inputs_instr,
nir_metadata_block_index | nir_metadata_dominance,
zero_inputs);
}
void
brw_nir_link_shaders(const struct brw_compiler *compiler,
elk_nir_link_shaders(const struct elk_compiler *compiler,
nir_shader *producer, nir_shader *consumer)
{
const struct intel_device_info *devinfo = compiler->devinfo;
@@ -1095,12 +1095,12 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
if (p_is_scalar && c_is_scalar) {
NIR_PASS(_, producer, nir_lower_io_to_scalar_early, nir_var_shader_out);
NIR_PASS(_, consumer, nir_lower_io_to_scalar_early, nir_var_shader_in);
brw_nir_optimize(producer, p_is_scalar, devinfo);
brw_nir_optimize(consumer, c_is_scalar, devinfo);
elk_nir_optimize(producer, p_is_scalar, devinfo);
elk_nir_optimize(consumer, c_is_scalar, devinfo);
}
if (nir_link_opt_varyings(producer, consumer))
brw_nir_optimize(consumer, c_is_scalar, devinfo);
elk_nir_optimize(consumer, c_is_scalar, devinfo);
NIR_PASS(_, producer, nir_remove_dead_variables, nir_var_shader_out, NULL);
NIR_PASS(_, consumer, nir_remove_dead_variables, nir_var_shader_in, NULL);
@@ -1123,14 +1123,14 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
* varyings we have demoted here.
*/
NIR_PASS(_, producer, nir_lower_indirect_derefs,
brw_nir_no_indirect_mask(compiler, producer->info.stage),
elk_nir_no_indirect_mask(compiler, producer->info.stage),
UINT32_MAX);
NIR_PASS(_, consumer, nir_lower_indirect_derefs,
brw_nir_no_indirect_mask(compiler, consumer->info.stage),
elk_nir_no_indirect_mask(compiler, consumer->info.stage),
UINT32_MAX);
brw_nir_optimize(producer, p_is_scalar, devinfo);
brw_nir_optimize(consumer, c_is_scalar, devinfo);
elk_nir_optimize(producer, p_is_scalar, devinfo);
elk_nir_optimize(consumer, c_is_scalar, devinfo);
}
NIR_PASS(_, producer, nir_lower_io_to_vector, nir_var_shader_out);
@@ -1158,7 +1158,7 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
}
bool
brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
elk_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
unsigned bit_size,
unsigned num_components,
nir_intrinsic_instr *low,
@@ -1189,7 +1189,7 @@ brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
}
} else {
/* We can handle at most a vec4 right now. Anything bigger would get
* immediately split by brw_nir_lower_mem_access_bit_sizes anyway.
* immediately split by elk_nir_lower_mem_access_bit_sizes anyway.
*/
if (num_components > 4)
return false;
@@ -1315,9 +1315,9 @@ get_mem_access_size_align(nir_intrinsic_op intrin, uint8_t bytes,
}
static void
brw_vectorize_lower_mem_access(nir_shader *nir,
const struct brw_compiler *compiler,
enum brw_robustness_flags robust_flags)
elk_vectorize_lower_mem_access(nir_shader *nir,
const struct elk_compiler *compiler,
enum elk_robustness_flags robust_flags)
{
bool progress = false;
const bool is_scalar = compiler->scalar_stage[nir->info.stage];
@@ -1326,13 +1326,13 @@ brw_vectorize_lower_mem_access(nir_shader *nir,
nir_load_store_vectorize_options options = {
.modes = nir_var_mem_ubo | nir_var_mem_ssbo |
nir_var_mem_global | nir_var_mem_shared,
.callback = brw_nir_should_vectorize_mem,
.callback = elk_nir_should_vectorize_mem,
.robust_modes = (nir_variable_mode)0,
};
if (robust_flags & BRW_ROBUSTNESS_UBO)
if (robust_flags & ELK_ROBUSTNESS_UBO)
options.robust_modes |= nir_var_mem_ubo | nir_var_mem_global;
if (robust_flags & BRW_ROBUSTNESS_SSBO)
if (robust_flags & ELK_ROBUSTNESS_SSBO)
options.robust_modes |= nir_var_mem_ssbo | nir_var_mem_global;
OPT(nir_opt_load_store_vectorize, &options);
@@ -1405,9 +1405,9 @@ nir_shader_has_local_variables(const nir_shader *nir)
* will not work.
*/
void
brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
elk_postprocess_nir(nir_shader *nir, const struct elk_compiler *compiler,
bool debug_enabled,
enum brw_robustness_flags robust_flags)
enum elk_robustness_flags robust_flags)
{
const struct intel_device_info *devinfo = compiler->devinfo;
const bool is_scalar = compiler->scalar_stage[nir->info.stage];
@@ -1437,20 +1437,20 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
if (gl_shader_stage_can_set_fragment_shading_rate(nir->info.stage))
NIR_PASS(_, nir, intel_nir_lower_shading_rate_output);
brw_nir_optimize(nir, is_scalar, devinfo);
elk_nir_optimize(nir, is_scalar, devinfo);
if (is_scalar && nir_shader_has_local_variables(nir)) {
OPT(nir_lower_vars_to_explicit_types, nir_var_function_temp,
glsl_get_natural_size_align_bytes);
OPT(nir_lower_explicit_io, nir_var_function_temp,
nir_address_format_32bit_offset);
brw_nir_optimize(nir, is_scalar, devinfo);
elk_nir_optimize(nir, is_scalar, devinfo);
}
brw_vectorize_lower_mem_access(nir, compiler, robust_flags);
elk_vectorize_lower_mem_access(nir, compiler, robust_flags);
if (OPT(nir_lower_int64))
brw_nir_optimize(nir, is_scalar, devinfo);
elk_nir_optimize(nir, is_scalar, devinfo);
if (devinfo->ver >= 6) {
/* Try and fuse multiply-adds, if successful, run shrink_vectors to
@@ -1481,7 +1481,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
* instruction from one of the branches of the if-statement, so now it
* might be under the threshold of conversion to bcsel.
*
* See brw_nir_optimize for the explanation of is_vec4_tessellation.
* See elk_nir_optimize for the explanation of is_vec4_tessellation.
*/
const bool is_vec4_tessellation = !is_scalar &&
(nir->info.stage == MESA_SHADER_TESS_CTRL ||
@@ -1510,7 +1510,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
if (OPT(nir_lower_fp16_casts, nir_lower_fp16_split_fp64)) {
if (OPT(nir_lower_int64)) {
brw_nir_optimize(nir, is_scalar, devinfo);
elk_nir_optimize(nir, is_scalar, devinfo);
}
}
@@ -1551,7 +1551,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
OPT(nir_lower_subgroups, &subgroups_options);
if (OPT(nir_lower_int64))
brw_nir_optimize(nir, is_scalar, devinfo);
elk_nir_optimize(nir, is_scalar, devinfo);
divergence_analysis_dirty = true;
}
@@ -1617,7 +1617,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
* want that to be squashed by other NIR passes.
*/
if (devinfo->ver <= 5)
brw_nir_analyze_boolean_resolves(nir);
elk_nir_analyze_boolean_resolves(nir);
nir_sweep(nir);
@@ -1629,9 +1629,9 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
}
static bool
brw_nir_apply_sampler_key(nir_shader *nir,
const struct brw_compiler *compiler,
const struct brw_sampler_prog_key_data *key_tex)
elk_nir_apply_sampler_key(nir_shader *nir,
const struct elk_compiler *compiler,
const struct elk_sampler_prog_key_data *key_tex)
{
const struct intel_device_info *devinfo = compiler->devinfo;
nir_lower_tex_options tex_options = {
@@ -1664,13 +1664,13 @@ get_subgroup_size(const struct shader_info *info, unsigned max_subgroup_size)
switch (info->subgroup_size) {
case SUBGROUP_SIZE_API_CONSTANT:
/* We have to use the global constant size. */
return BRW_SUBGROUP_SIZE;
return ELK_SUBGROUP_SIZE;
case SUBGROUP_SIZE_UNIFORM:
/* It has to be uniform across all invocations but can vary per stage
* if we want. This gives us a bit more freedom.
*
* For compute, brw_nir_apply_key is called per-dispatch-width so this
* For compute, elk_nir_apply_key is called per-dispatch-width so this
* is the actual subgroup size and not a maximum. However, we only
* invoke one size of any given compute shader so it's still guaranteed
* to be uniform across invocations.
@@ -1680,7 +1680,7 @@ get_subgroup_size(const struct shader_info *info, unsigned max_subgroup_size)
case SUBGROUP_SIZE_VARYING:
/* The subgroup size is allowed to be fully varying. For geometry
* stages, we know it's always 8 which is max_subgroup_size so we can
* return that. For compute, brw_nir_apply_key is called once per
* return that. For compute, elk_nir_apply_key is called once per
* dispatch-width so max_subgroup_size is the real subgroup size.
*
* For fragment, we return 0 and let it fall through to the back-end
@@ -1710,21 +1710,21 @@ get_subgroup_size(const struct shader_info *info, unsigned max_subgroup_size)
}
unsigned
brw_nir_api_subgroup_size(const nir_shader *nir,
elk_nir_api_subgroup_size(const nir_shader *nir,
unsigned hw_subgroup_size)
{
return get_subgroup_size(&nir->info, hw_subgroup_size);
}
void
brw_nir_apply_key(nir_shader *nir,
const struct brw_compiler *compiler,
const struct brw_base_prog_key *key,
elk_nir_apply_key(nir_shader *nir,
const struct elk_compiler *compiler,
const struct elk_base_prog_key *key,
unsigned max_subgroup_size)
{
bool progress = false;
OPT(brw_nir_apply_sampler_key, compiler, &key->tex);
OPT(elk_nir_apply_sampler_key, compiler, &key->tex);
const struct intel_nir_lower_texture_opts tex_opts = {
.combined_lod_and_array_index = compiler->devinfo->ver >= 20,
@@ -1740,16 +1740,16 @@ brw_nir_apply_key(nir_shader *nir,
OPT(nir_lower_subgroups, &subgroups_options);
if (key->limit_trig_input_range)
OPT(brw_nir_limit_trig_input_range_workaround);
OPT(elk_nir_limit_trig_input_range_workaround);
if (progress) {
const bool is_scalar = compiler->scalar_stage[nir->info.stage];
brw_nir_optimize(nir, is_scalar, compiler->devinfo);
elk_nir_optimize(nir, is_scalar, compiler->devinfo);
}
}
enum brw_conditional_mod
brw_cmod_for_nir_comparison(nir_op op)
enum elk_conditional_mod
elk_cmod_for_nir_comparison(nir_op op)
{
switch (op) {
case nir_op_flt:
@@ -1758,7 +1758,7 @@ brw_cmod_for_nir_comparison(nir_op op)
case nir_op_ilt32:
case nir_op_ult:
case nir_op_ult32:
return BRW_CONDITIONAL_L;
return ELK_CONDITIONAL_L;
case nir_op_fge:
case nir_op_fge32:
@@ -1766,7 +1766,7 @@ brw_cmod_for_nir_comparison(nir_op op)
case nir_op_ige32:
case nir_op_uge:
case nir_op_uge32:
return BRW_CONDITIONAL_GE;
return ELK_CONDITIONAL_GE;
case nir_op_feq:
case nir_op_feq32:
@@ -1778,7 +1778,7 @@ brw_cmod_for_nir_comparison(nir_op op)
case nir_op_b32all_iequal3:
case nir_op_b32all_fequal4:
case nir_op_b32all_iequal4:
return BRW_CONDITIONAL_Z;
return ELK_CONDITIONAL_Z;
case nir_op_fneu:
case nir_op_fneu32:
@@ -1790,15 +1790,15 @@ brw_cmod_for_nir_comparison(nir_op op)
case nir_op_b32any_inequal3:
case nir_op_b32any_fnequal4:
case nir_op_b32any_inequal4:
return BRW_CONDITIONAL_NZ;
return ELK_CONDITIONAL_NZ;
default:
unreachable("Unsupported NIR comparison op");
}
}
enum lsc_opcode
lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic)
enum elk_lsc_opcode
elk_lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic)
{
switch (nir_intrinsic_atomic_op(atomic)) {
case nir_atomic_op_iadd: {
@@ -1849,48 +1849,48 @@ lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic)
}
}
enum brw_reg_type
brw_type_for_nir_type(const struct intel_device_info *devinfo,
enum elk_reg_type
elk_type_for_nir_type(const struct intel_device_info *devinfo,
nir_alu_type type)
{
switch (type) {
case nir_type_uint:
case nir_type_uint32:
return BRW_REGISTER_TYPE_UD;
return ELK_REGISTER_TYPE_UD;
case nir_type_bool:
case nir_type_int:
case nir_type_bool32:
case nir_type_int32:
return BRW_REGISTER_TYPE_D;
return ELK_REGISTER_TYPE_D;
case nir_type_float:
case nir_type_float32:
return BRW_REGISTER_TYPE_F;
return ELK_REGISTER_TYPE_F;
case nir_type_float16:
return BRW_REGISTER_TYPE_HF;
return ELK_REGISTER_TYPE_HF;
case nir_type_float64:
return BRW_REGISTER_TYPE_DF;
return ELK_REGISTER_TYPE_DF;
case nir_type_int64:
return devinfo->ver < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_Q;
return devinfo->ver < 8 ? ELK_REGISTER_TYPE_DF : ELK_REGISTER_TYPE_Q;
case nir_type_uint64:
return devinfo->ver < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_UQ;
return devinfo->ver < 8 ? ELK_REGISTER_TYPE_DF : ELK_REGISTER_TYPE_UQ;
case nir_type_int16:
return BRW_REGISTER_TYPE_W;
return ELK_REGISTER_TYPE_W;
case nir_type_uint16:
return BRW_REGISTER_TYPE_UW;
return ELK_REGISTER_TYPE_UW;
case nir_type_int8:
return BRW_REGISTER_TYPE_B;
return ELK_REGISTER_TYPE_B;
case nir_type_uint8:
return BRW_REGISTER_TYPE_UB;
return ELK_REGISTER_TYPE_UB;
default:
unreachable("unknown type");
}
return BRW_REGISTER_TYPE_F;
return ELK_REGISTER_TYPE_F;
}
nir_shader *
brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler,
const struct brw_tcs_prog_key *key)
elk_nir_create_passthrough_tcs(void *mem_ctx, const struct elk_compiler *compiler,
const struct elk_tcs_prog_key *key)
{
assert(key->input_vertices > 0);
@@ -1914,16 +1914,16 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile
nir->info.inputs_read = inputs_read;
nir->info.tess._primitive_mode = key->_tes_primitive_mode;
nir_validate_shader(nir, "in brw_nir_create_passthrough_tcs");
nir_validate_shader(nir, "in elk_nir_create_passthrough_tcs");
struct brw_nir_compiler_opts opts = {};
brw_preprocess_nir(compiler, nir, &opts);
struct elk_nir_compiler_opts opts = {};
elk_preprocess_nir(compiler, nir, &opts);
return nir;
}
nir_def *
brw_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform,
elk_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform,
nir_def *base_addr, unsigned off)
{
assert(load_uniform->intrinsic == nir_intrinsic_load_uniform);
@@ -1967,7 +1967,7 @@ brw_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform,
}
const struct glsl_type *
brw_nir_get_var_type(const struct nir_shader *nir, nir_variable *var)
elk_nir_get_var_type(const struct nir_shader *nir, nir_variable *var)
{
const struct glsl_type *type = var->interface_type;
if (!type) {
src/intel/compiler/elk/elk_nir.h
+71 -71
View File
@@ -33,27 +33,27 @@
extern "C" {
#endif
extern const struct nir_shader_compiler_options brw_scalar_nir_options;
extern const struct nir_shader_compiler_options brw_vector_nir_options;
extern const struct nir_shader_compiler_options elk_scalar_nir_options;
extern const struct nir_shader_compiler_options elk_vector_nir_options;
int type_size_vec4(const struct glsl_type *type, bool bindless);
int type_size_dvec4(const struct glsl_type *type, bool bindless);
int elk_type_size_vec4(const struct glsl_type *type, bool bindless);
int elk_type_size_dvec4(const struct glsl_type *type, bool bindless);
static inline int
type_size_scalar_bytes(const struct glsl_type *type, bool bindless)
elk_type_size_scalar_bytes(const struct glsl_type *type, bool bindless)
{
return glsl_count_dword_slots(type, bindless) * 4;
}
static inline int
type_size_vec4_bytes(const struct glsl_type *type, bool bindless)
elk_type_size_vec4_bytes(const struct glsl_type *type, bool bindless)
{
return type_size_vec4(type, bindless) * 16;
return elk_type_size_vec4(type, bindless) * 16;
}
/* Flags set in the instr->pass_flags field by i965 analysis passes */
enum {
BRW_NIR_NON_BOOLEAN = 0x0,
ELK_NIR_NON_BOOLEAN = 0x0,
/* Indicates that the given instruction's destination is a boolean
* value but that it needs to be resolved before it can be used.
@@ -63,7 +63,7 @@ enum {
* "resolve" operation by replacing the value of the CMP with -(x & 1)
* to sign-extend the bottom bit to 0/~0.
*/
BRW_NIR_BOOLEAN_NEEDS_RESOLVE = 0x1,
ELK_NIR_BOOLEAN_NEEDS_RESOLVE = 0x1,
/* Indicates that the given instruction's destination is a boolean
* value that has intentionally been left unresolved. Not all boolean
@@ -77,25 +77,25 @@ enum {
* immediately because the AND still does an AND of the bottom bits.
* Instead, we can save ourselves instructions by delaying the resolve
* until after the AND. The result of the two CMP instructions is left
* as BRW_NIR_BOOLEAN_UNRESOLVED.
* as ELK_NIR_BOOLEAN_UNRESOLVED.
*/
BRW_NIR_BOOLEAN_UNRESOLVED = 0x2,
ELK_NIR_BOOLEAN_UNRESOLVED = 0x2,
/* Indicates a that the given instruction's destination is a boolean
* value that does not need a resolve. For instance, if you AND two
* values that are BRW_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both
* values that are ELK_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both
* values will be 0/~0 before we get them and the result of the AND is
* also guaranteed to be 0/~0 and does not need a resolve.
*/
BRW_NIR_BOOLEAN_NO_RESOLVE = 0x3,
ELK_NIR_BOOLEAN_NO_RESOLVE = 0x3,
/* A mask to mask the boolean status values off of instr->pass_flags */
BRW_NIR_BOOLEAN_MASK = 0x3,
ELK_NIR_BOOLEAN_MASK = 0x3,
};
void brw_nir_analyze_boolean_resolves(nir_shader *nir);
void elk_nir_analyze_boolean_resolves(nir_shader *nir);
struct brw_nir_compiler_opts {
struct elk_nir_compiler_opts {
/* Soft floating point implementation shader */
const nir_shader *softfp64;
@@ -117,7 +117,7 @@ struct brw_nir_compiler_opts {
* This function should only be called on src[0] of load_ubo intrinsics.
*/
static inline bool
brw_nir_ubo_surface_index_is_pushable(nir_src src)
elk_nir_ubo_surface_index_is_pushable(nir_src src)
{
nir_intrinsic_instr *intrin =
src.ssa->parent_instr->type == nir_instr_type_intrinsic ?
@@ -132,12 +132,12 @@ brw_nir_ubo_surface_index_is_pushable(nir_src src)
}
static inline unsigned
brw_nir_ubo_surface_index_get_push_block(nir_src src)
elk_nir_ubo_surface_index_get_push_block(nir_src src)
{
if (nir_src_is_const(src))
return nir_src_as_uint(src);
if (!brw_nir_ubo_surface_index_is_pushable(src))
if (!elk_nir_ubo_surface_index_is_pushable(src))
return UINT32_MAX;
assert(src.ssa->parent_instr->type == nir_instr_type_intrinsic);
@@ -157,7 +157,7 @@ brw_nir_ubo_surface_index_get_push_block(nir_src src)
* src[1] of that intrinsic.
*/
static inline unsigned
brw_nir_ubo_surface_index_get_bti(nir_src src)
elk_nir_ubo_surface_index_get_bti(nir_src src)
{
if (nir_src_is_const(src))
return nir_src_as_uint(src);
@@ -182,41 +182,41 @@ brw_nir_ubo_surface_index_get_bti(nir_src src)
return nir_src_as_uint(intrin->src[1]);
}
void brw_preprocess_nir(const struct brw_compiler *compiler,
void elk_preprocess_nir(const struct elk_compiler *compiler,
nir_shader *nir,
const struct brw_nir_compiler_opts *opts);
const struct elk_nir_compiler_opts *opts);
void
brw_nir_link_shaders(const struct brw_compiler *compiler,
elk_nir_link_shaders(const struct elk_compiler *compiler,
nir_shader *producer, nir_shader *consumer);
bool brw_nir_lower_cs_intrinsics(nir_shader *nir,
bool elk_nir_lower_cs_intrinsics(nir_shader *nir,
const struct intel_device_info *devinfo,
struct brw_cs_prog_data *prog_data);
bool brw_nir_lower_alpha_to_coverage(nir_shader *shader,
const struct brw_wm_prog_key *key,
const struct brw_wm_prog_data *prog_data);
void brw_nir_lower_vs_inputs(nir_shader *nir,
struct elk_cs_prog_data *prog_data);
bool elk_nir_lower_alpha_to_coverage(nir_shader *shader,
const struct elk_wm_prog_key *key,
const struct elk_wm_prog_data *prog_data);
void elk_nir_lower_vs_inputs(nir_shader *nir,
bool edgeflag_is_last,
const uint8_t *vs_attrib_wa_flags);
void brw_nir_lower_vue_inputs(nir_shader *nir,
void elk_nir_lower_vue_inputs(nir_shader *nir,
const struct intel_vue_map *vue_map);
void brw_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue);
void brw_nir_lower_fs_inputs(nir_shader *nir,
void elk_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue);
void elk_nir_lower_fs_inputs(nir_shader *nir,
const struct intel_device_info *devinfo,
const struct brw_wm_prog_key *key);
void brw_nir_lower_vue_outputs(nir_shader *nir);
void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue,
const struct elk_wm_prog_key *key);
void elk_nir_lower_vue_outputs(nir_shader *nir);
void elk_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue,
enum tess_primitive_mode tes_primitive_mode);
void brw_nir_lower_fs_outputs(nir_shader *nir);
void elk_nir_lower_fs_outputs(nir_shader *nir);
bool brw_nir_lower_cmat(nir_shader *nir, unsigned subgroup_size);
bool elk_nir_lower_cmat(nir_shader *nir, unsigned subgroup_size);
bool brw_nir_lower_shading_rate_output(nir_shader *nir);
bool elk_nir_lower_shading_rate_output(nir_shader *nir);
bool brw_nir_lower_sparse_intrinsics(nir_shader *nir);
bool elk_nir_lower_sparse_intrinsics(nir_shader *nir);
struct brw_nir_lower_storage_image_opts {
struct elk_nir_lower_storage_image_opts {
const struct intel_device_info *devinfo;
bool lower_loads;
@@ -225,71 +225,71 @@ struct brw_nir_lower_storage_image_opts {
bool lower_get_size;
};
bool brw_nir_lower_storage_image(nir_shader *nir,
const struct brw_nir_lower_storage_image_opts *opts);
bool elk_nir_lower_storage_image(nir_shader *nir,
const struct elk_nir_lower_storage_image_opts *opts);
bool brw_nir_lower_mem_access_bit_sizes(nir_shader *shader,
bool elk_nir_lower_mem_access_bit_sizes(nir_shader *shader,
const struct
intel_device_info *devinfo);
void brw_postprocess_nir(nir_shader *nir,
const struct brw_compiler *compiler,
void elk_postprocess_nir(nir_shader *nir,
const struct elk_compiler *compiler,
bool debug_enabled,
enum brw_robustness_flags robust_flags);
enum elk_robustness_flags robust_flags);
bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
bool elk_nir_apply_attribute_workarounds(nir_shader *nir,
const uint8_t *attrib_wa_flags);
bool brw_nir_apply_trig_workarounds(nir_shader *nir);
bool elk_nir_apply_trig_workarounds(nir_shader *nir);
bool brw_nir_limit_trig_input_range_workaround(nir_shader *nir);
bool elk_nir_limit_trig_input_range_workaround(nir_shader *nir);
void brw_nir_apply_key(nir_shader *nir,
const struct brw_compiler *compiler,
const struct brw_base_prog_key *key,
void elk_nir_apply_key(nir_shader *nir,
const struct elk_compiler *compiler,
const struct elk_base_prog_key *key,
unsigned max_subgroup_size);
unsigned brw_nir_api_subgroup_size(const nir_shader *nir,
unsigned elk_nir_api_subgroup_size(const nir_shader *nir,
unsigned hw_subgroup_size);
enum brw_conditional_mod brw_cmod_for_nir_comparison(nir_op op);
enum lsc_opcode lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic);
enum brw_reg_type brw_type_for_nir_type(const struct intel_device_info *devinfo,
enum elk_conditional_mod elk_cmod_for_nir_comparison(nir_op op);
enum elk_lsc_opcode elk_lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic);
enum elk_reg_type elk_type_for_nir_type(const struct intel_device_info *devinfo,
nir_alu_type type);
bool brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
bool elk_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
unsigned bit_size,
unsigned num_components,
nir_intrinsic_instr *low,
nir_intrinsic_instr *high,
void *data);
void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
void elk_nir_analyze_ubo_ranges(const struct elk_compiler *compiler,
nir_shader *nir,
struct brw_ubo_range out_ranges[4]);
struct elk_ubo_range out_ranges[4]);
void brw_nir_optimize(nir_shader *nir, bool is_scalar,
void elk_nir_optimize(nir_shader *nir, bool is_scalar,
const struct intel_device_info *devinfo);
nir_shader *brw_nir_create_passthrough_tcs(void *mem_ctx,
const struct brw_compiler *compiler,
const struct brw_tcs_prog_key *key);
nir_shader *elk_nir_create_passthrough_tcs(void *mem_ctx,
const struct elk_compiler *compiler,
const struct elk_tcs_prog_key *key);
#define BRW_NIR_FRAG_OUTPUT_INDEX_SHIFT 0
#define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
#define BRW_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1
#define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
#define ELK_NIR_FRAG_OUTPUT_INDEX_SHIFT 0
#define ELK_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
#define ELK_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1
#define ELK_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
bool brw_nir_move_interpolation_to_top(nir_shader *nir);
nir_def *brw_nir_load_global_const(nir_builder *b,
bool elk_nir_move_interpolation_to_top(nir_shader *nir);
nir_def *elk_nir_load_global_const(nir_builder *b,
nir_intrinsic_instr *load_uniform,
nir_def *base_addr,
unsigned off);
const struct glsl_type *brw_nir_get_var_type(const struct nir_shader *nir,
const struct glsl_type *elk_nir_get_var_type(const struct nir_shader *nir,
nir_variable *var);
void brw_nir_adjust_payload(nir_shader *shader);
void elk_nir_adjust_payload(nir_shader *shader);
#ifdef __cplusplus
}
src/intel/compiler/elk/elk_nir_analyze_boolean_resolves.c
+26 -26
View File
@@ -27,7 +27,7 @@
* This file implements an analysis pass that determines when we have to do
* a boolean resolve on Gen <= 5. Instructions that need a boolean resolve
* will have the booleans portion of the instr->pass_flags field set to
* BRW_NIR_BOOLEAN_NEEDS_RESOLVE.
* ELK_NIR_BOOLEAN_NEEDS_RESOLVE.
*/
@@ -41,13 +41,13 @@ static uint8_t
get_resolve_status_for_src(nir_src *src)
{
nir_instr *src_instr = src->ssa->parent_instr;
uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK;
uint8_t resolve_status = src_instr->pass_flags & ELK_NIR_BOOLEAN_MASK;
/* If the source instruction needs resolve, then from the perspective
* of the user, it's a true boolean.
*/
if (resolve_status == BRW_NIR_BOOLEAN_NEEDS_RESOLVE)
resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE;
if (resolve_status == ELK_NIR_BOOLEAN_NEEDS_RESOLVE)
resolve_status = ELK_NIR_BOOLEAN_NO_RESOLVE;
return resolve_status;
}
@@ -60,14 +60,14 @@ static bool
src_mark_needs_resolve(nir_src *src, void *void_state)
{
nir_instr *src_instr = src->ssa->parent_instr;
uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK;
uint8_t resolve_status = src_instr->pass_flags & ELK_NIR_BOOLEAN_MASK;
/* If the source instruction is unresolved, then mark it as needing
* to be resolved.
*/
if (resolve_status == BRW_NIR_BOOLEAN_UNRESOLVED) {
src_instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK;
src_instr->pass_flags |= BRW_NIR_BOOLEAN_NEEDS_RESOLVE;
if (resolve_status == ELK_NIR_BOOLEAN_UNRESOLVED) {
src_instr->pass_flags &= ~ELK_NIR_BOOLEAN_MASK;
src_instr->pass_flags |= ELK_NIR_BOOLEAN_NEEDS_RESOLVE;
}
return true;
@@ -116,7 +116,7 @@ analyze_boolean_resolves_block(nir_block *block)
* future, this may change and we'll have to remove some of the
* above cases.
*/
resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE;
resolve_status = ELK_NIR_BOOLEAN_NO_RESOLVE;
break;
case nir_op_mov:
@@ -143,12 +143,12 @@ analyze_boolean_resolves_block(nir_block *block)
if (src0_status == src1_status) {
resolve_status = src0_status;
} else if (src0_status == BRW_NIR_NON_BOOLEAN ||
src1_status == BRW_NIR_NON_BOOLEAN) {
} else if (src0_status == ELK_NIR_NON_BOOLEAN ||
src1_status == ELK_NIR_NON_BOOLEAN) {
/* If one of the sources is a non-boolean then the whole
* thing is a non-boolean.
*/
resolve_status = BRW_NIR_NON_BOOLEAN;
resolve_status = ELK_NIR_NON_BOOLEAN;
} else {
/* At this point one of them is a true boolean and one is a
* boolean that needs a resolve. We could either resolve the
@@ -157,7 +157,7 @@ analyze_boolean_resolves_block(nir_block *block)
* of one. Just set this one to BOOLEAN_NO_RESOLVE and we'll
* let the code below force a resolve on the unresolved source.
*/
resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE;
resolve_status = ELK_NIR_BOOLEAN_NO_RESOLVE;
}
break;
}
@@ -168,7 +168,7 @@ analyze_boolean_resolves_block(nir_block *block)
* them so the result will have to be resolved before it can be
* used.
*/
resolve_status = BRW_NIR_BOOLEAN_UNRESOLVED;
resolve_status = ELK_NIR_BOOLEAN_UNRESOLVED;
/* Even though the destination is allowed to be left
* unresolved, the sources are treated as regular integers or
@@ -176,25 +176,25 @@ analyze_boolean_resolves_block(nir_block *block)
*/
nir_foreach_src(instr, src_mark_needs_resolve, NULL);
} else {
resolve_status = BRW_NIR_NON_BOOLEAN;
resolve_status = ELK_NIR_NON_BOOLEAN;
}
}
/* Go ahead allow unresolved booleans. */
instr->pass_flags = (instr->pass_flags & ~BRW_NIR_BOOLEAN_MASK) |
instr->pass_flags = (instr->pass_flags & ~ELK_NIR_BOOLEAN_MASK) |
resolve_status;
/* Finally, resolve sources if it's needed */
switch (resolve_status) {
case BRW_NIR_BOOLEAN_NEEDS_RESOLVE:
case BRW_NIR_BOOLEAN_UNRESOLVED:
case ELK_NIR_BOOLEAN_NEEDS_RESOLVE:
case ELK_NIR_BOOLEAN_UNRESOLVED:
/* This instruction is either unresolved or we're doing the
* resolve here; leave the sources alone.
*/
break;
case BRW_NIR_BOOLEAN_NO_RESOLVE:
case BRW_NIR_NON_BOOLEAN:
case ELK_NIR_BOOLEAN_NO_RESOLVE:
case ELK_NIR_NON_BOOLEAN:
nir_foreach_src(instr, src_mark_needs_resolve, NULL);
break;
@@ -214,11 +214,11 @@ analyze_boolean_resolves_block(nir_block *block)
* Since load_const instructions don't have any sources, we don't
* have to worry about resolving them.
*/
instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK;
instr->pass_flags &= ~ELK_NIR_BOOLEAN_MASK;
if (load->value[0].u32 == NIR_TRUE || load->value[0].u32 == NIR_FALSE) {
instr->pass_flags |= BRW_NIR_BOOLEAN_NO_RESOLVE;
instr->pass_flags |= ELK_NIR_BOOLEAN_NO_RESOLVE;
} else {
instr->pass_flags |= BRW_NIR_NON_BOOLEAN;
instr->pass_flags |= ELK_NIR_NON_BOOLEAN;
}
continue;
}
@@ -227,8 +227,8 @@ analyze_boolean_resolves_block(nir_block *block)
/* Everything else is an unknown non-boolean value and needs to
* have all sources resolved.
*/
instr->pass_flags = (instr->pass_flags & ~BRW_NIR_BOOLEAN_MASK) |
BRW_NIR_NON_BOOLEAN;
instr->pass_flags = (instr->pass_flags & ~ELK_NIR_BOOLEAN_MASK) |
ELK_NIR_NON_BOOLEAN;
nir_foreach_src(instr, src_mark_needs_resolve, NULL);
continue;
}
@@ -250,7 +250,7 @@ analyze_boolean_resolves_impl(nir_function_impl *impl)
}
void
brw_nir_analyze_boolean_resolves(nir_shader *shader)
elk_nir_analyze_boolean_resolves(nir_shader *shader)
{
nir_foreach_function_impl(impl, shader) {
analyze_boolean_resolves_impl(impl);
src/intel/compiler/elk/elk_nir_analyze_ubo_ranges.c
+5 -5
View File
@@ -46,7 +46,7 @@
struct ubo_range_entry
{
struct brw_ubo_range range;
struct elk_ubo_range range;
int benefit;
};
@@ -141,9 +141,9 @@ analyze_ubos_block(struct ubo_analysis_state *state, nir_block *block)
continue; /* Not a uniform or UBO intrinsic */
}
if (brw_nir_ubo_surface_index_is_pushable(intrin->src[0]) &&
if (elk_nir_ubo_surface_index_is_pushable(intrin->src[0]) &&
nir_src_is_const(intrin->src[1])) {
const int block = brw_nir_ubo_surface_index_get_push_block(intrin->src[0]);
const int block = elk_nir_ubo_surface_index_get_push_block(intrin->src[0]);
const unsigned byte_offset = nir_src_as_uint(intrin->src[1]);
const int offset = byte_offset / 32;
@@ -187,9 +187,9 @@ print_ubo_entry(FILE *file,
}
void
brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
elk_nir_analyze_ubo_ranges(const struct elk_compiler *compiler,
nir_shader *nir,
struct brw_ubo_range out_ranges[4])
struct elk_ubo_range out_ranges[4])
{
void *mem_ctx = ralloc_context(NULL);
src/intel/compiler/elk/elk_nir_attribute_workarounds.c
+9 -9
View File
@@ -53,34 +53,34 @@ apply_attr_wa_instr(nir_builder *b, nir_instr *instr, void *cb_data)
/* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
* come in as floating point conversions of the integer values.
*/
if (wa_flags & BRW_ATTRIB_WA_COMPONENT_MASK) {
if (wa_flags & ELK_ATTRIB_WA_COMPONENT_MASK) {
nir_def *scaled =
nir_fmul_imm(b, val, 1.0f / 65536.0f);
nir_def *comps[4];
for (int i = 0; i < val->num_components; i++) {
bool rescale = i < (wa_flags & BRW_ATTRIB_WA_COMPONENT_MASK);
bool rescale = i < (wa_flags & ELK_ATTRIB_WA_COMPONENT_MASK);
comps[i] = nir_channel(b, rescale ? scaled : val, i);
}
val = nir_vec(b, comps, val->num_components);
}
/* Do sign recovery for 2101010 formats if required. */
if (wa_flags & BRW_ATTRIB_WA_SIGN) {
if (wa_flags & ELK_ATTRIB_WA_SIGN) {
/* sign recovery shift: <22, 22, 22, 30> */
nir_def *shift = nir_imm_ivec4(b, 22, 22, 22, 30);
val = nir_ishr(b, nir_ishl(b, val, shift), shift);
}
/* Apply BGRA swizzle if required. */
if (wa_flags & BRW_ATTRIB_WA_BGRA) {
if (wa_flags & ELK_ATTRIB_WA_BGRA) {
val = nir_swizzle(b, val, (unsigned[4]){2,1,0,3}, 4);
}
if (wa_flags & BRW_ATTRIB_WA_NORMALIZE) {
if (wa_flags & ELK_ATTRIB_WA_NORMALIZE) {
/* ES 3.0 has different rules for converting signed normalized
* fixed-point numbers than desktop GL.
*/
if (wa_flags & BRW_ATTRIB_WA_SIGN) {
if (wa_flags & ELK_ATTRIB_WA_SIGN) {
/* According to equation 2.2 of the ES 3.0 specification,
* signed normalization conversion is done by:
*
@@ -110,8 +110,8 @@ apply_attr_wa_instr(nir_builder *b, nir_instr *instr, void *cb_data)
}
}
if (wa_flags & BRW_ATTRIB_WA_SCALE) {
val = (wa_flags & BRW_ATTRIB_WA_SIGN) ? nir_i2f32(b, val)
if (wa_flags & ELK_ATTRIB_WA_SCALE) {
val = (wa_flags & ELK_ATTRIB_WA_SIGN) ? nir_i2f32(b, val)
: nir_u2f32(b, val);
}
@@ -122,7 +122,7 @@ apply_attr_wa_instr(nir_builder *b, nir_instr *instr, void *cb_data)
}
bool
brw_nir_apply_attribute_workarounds(nir_shader *shader,
elk_nir_apply_attribute_workarounds(nir_shader *shader,
const uint8_t *attrib_wa_flags)
{
return nir_shader_instructions_pass(shader, apply_attr_wa_instr,
src/intel/compiler/elk/elk_nir_lower_alpha_to_coverage.c
+8 -8
View File
@@ -78,12 +78,12 @@ build_dither_mask(nir_builder *b, nir_def *color)
}
bool
brw_nir_lower_alpha_to_coverage(nir_shader *shader,
const struct brw_wm_prog_key *key,
const struct brw_wm_prog_data *prog_data)
elk_nir_lower_alpha_to_coverage(nir_shader *shader,
const struct elk_wm_prog_key *key,
const struct elk_wm_prog_data *prog_data)
{
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
assert(key->alpha_to_coverage != BRW_NEVER);
assert(key->alpha_to_coverage != ELK_NEVER);
nir_function_impl *impl = nir_shader_get_entrypoint(shader);
@@ -113,14 +113,14 @@ brw_nir_lower_alpha_to_coverage(nir_shader *shader,
assert(block->cf_node.parent == &impl->cf_node);
assert(nir_cf_node_is_last(&block->cf_node));
/* See store_output in fs_visitor::nir_emit_fs_intrinsic */
/* See store_output in elk_fs_visitor::nir_emit_fs_intrinsic */
const unsigned store_offset = nir_src_as_uint(intrin->src[1]);
const unsigned driver_location = nir_intrinsic_base(intrin) +
SET_FIELD(store_offset, BRW_NIR_FRAG_OUTPUT_LOCATION);
SET_FIELD(store_offset, ELK_NIR_FRAG_OUTPUT_LOCATION);
/* Extract the FRAG_RESULT */
const unsigned location =
GET_FIELD(driver_location, BRW_NIR_FRAG_OUTPUT_LOCATION);
GET_FIELD(driver_location, ELK_NIR_FRAG_OUTPUT_LOCATION);
if (location == FRAG_RESULT_SAMPLE_MASK) {
assert(sample_mask_write == NULL);
@@ -171,7 +171,7 @@ brw_nir_lower_alpha_to_coverage(nir_shader *shader,
nir_def *dither_mask = build_dither_mask(&b, color0);
dither_mask = nir_iand(&b, sample_mask, dither_mask);
if (key->alpha_to_coverage == BRW_SOMETIMES) {
if (key->alpha_to_coverage == ELK_SOMETIMES) {
nir_def *push_flags =
nir_load_uniform(&b, 1, 32, nir_imm_int(&b, prog_data->msaa_flags_param * 4));
nir_def *alpha_to_coverage =
src/intel/compiler/elk/elk_nir_lower_cs_intrinsics.c
+2 -2
View File
@@ -295,9 +295,9 @@ lower_cs_intrinsics_convert_impl(struct lower_intrinsics_state *state)
}
bool
brw_nir_lower_cs_intrinsics(nir_shader *nir,
elk_nir_lower_cs_intrinsics(nir_shader *nir,
const struct intel_device_info *devinfo,
struct brw_cs_prog_data *prog_data)
struct elk_cs_prog_data *prog_data)
{
assert(gl_shader_stage_uses_workgroup(nir->info.stage));
src/intel/compiler/elk/elk_nir_lower_storage_image.c
+5 -5
View File
@@ -701,13 +701,13 @@ lower_image_size_instr(nir_builder *b,
}
static bool
brw_nir_lower_storage_image_instr(nir_builder *b,
elk_nir_lower_storage_image_instr(nir_builder *b,
nir_instr *instr,
void *cb_data)
{
if (instr->type != nir_instr_type_intrinsic)
return false;
const struct brw_nir_lower_storage_image_opts *opts = cb_data;
const struct elk_nir_lower_storage_image_opts *opts = cb_data;
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
switch (intrin->intrinsic) {
@@ -744,8 +744,8 @@ brw_nir_lower_storage_image_instr(nir_builder *b,
}
bool
brw_nir_lower_storage_image(nir_shader *shader,
const struct brw_nir_lower_storage_image_opts *opts)
elk_nir_lower_storage_image(nir_shader *shader,
const struct elk_nir_lower_storage_image_opts *opts)
{
bool progress = false;
@@ -757,7 +757,7 @@ brw_nir_lower_storage_image(nir_shader *shader,
progress |= nir_lower_image(shader, &image_options);
progress |= nir_shader_instructions_pass(shader,
brw_nir_lower_storage_image_instr,
elk_nir_lower_storage_image_instr,
nir_metadata_none,
(void *)opts);
src/intel/compiler/elk/elk_nir_trig_workarounds.py
+2 -2
View File
@@ -57,9 +57,9 @@ def run():
import nir_algebraic # pylint: disable=import-error
print('#include "elk_nir.h"')
print(nir_algebraic.AlgebraicPass("brw_nir_apply_trig_workarounds",
print(nir_algebraic.AlgebraicPass("elk_nir_apply_trig_workarounds",
TRIG_WORKAROUNDS).render())
print(nir_algebraic.AlgebraicPass("brw_nir_limit_trig_input_range_workaround",
print(nir_algebraic.AlgebraicPass("elk_nir_limit_trig_input_range_workaround",
LIMIT_TRIG_INPUT_RANGE_WORKAROUND).render())
src/intel/compiler/elk/elk_packed_float.c
+2 -2
View File
@@ -33,7 +33,7 @@ union fu {
};
int
brw_float_to_vf(float f)
elk_float_to_vf(float f)
{
union fu fu = { .f = f };
@@ -57,7 +57,7 @@ brw_float_to_vf(float f)
}
float
brw_vf_to_float(unsigned char vf)
elk_vf_to_float(unsigned char vf)
{
union fu fu;
src/intel/compiler/elk/elk_predicated_break.cpp
+25 -25
View File
@@ -99,7 +99,7 @@ has_continue(const struct loop_continue_tracking *s)
}
bool
opt_predicated_break(backend_shader *s)
elk_opt_predicated_break(elk_backend_shader *s)
{
bool progress = false;
struct loop_continue_tracking state = { {0, }, 0 };
@@ -108,51 +108,51 @@ opt_predicated_break(backend_shader *s)
/* DO instructions, by definition, can only be found at the beginning of
* basic blocks.
*/
backend_instruction *const do_inst = block->start();
elk_backend_instruction *const do_inst = block->start();
/* BREAK, CONTINUE, and WHILE instructions, by definition, can only be
* found at the ends of basic blocks.
*/
backend_instruction *jump_inst = block->end();
elk_backend_instruction *jump_inst = block->end();
if (do_inst->opcode == BRW_OPCODE_DO)
if (do_inst->opcode == ELK_OPCODE_DO)
enter_loop(&state);
if (jump_inst->opcode == BRW_OPCODE_CONTINUE)
if (jump_inst->opcode == ELK_OPCODE_CONTINUE)
set_continue(&state);
else if (jump_inst->opcode == BRW_OPCODE_WHILE)
else if (jump_inst->opcode == ELK_OPCODE_WHILE)
exit_loop(&state);
if (block->start_ip != block->end_ip)
continue;
if (jump_inst->opcode != BRW_OPCODE_BREAK &&
jump_inst->opcode != BRW_OPCODE_CONTINUE)
if (jump_inst->opcode != ELK_OPCODE_BREAK &&
jump_inst->opcode != ELK_OPCODE_CONTINUE)
continue;
backend_instruction *if_inst = block->prev()->end();
if (if_inst->opcode != BRW_OPCODE_IF)
elk_backend_instruction *if_inst = block->prev()->end();
if (if_inst->opcode != ELK_OPCODE_IF)
continue;
backend_instruction *endif_inst = block->next()->start();
if (endif_inst->opcode != BRW_OPCODE_ENDIF)
elk_backend_instruction *endif_inst = block->next()->start();
if (endif_inst->opcode != ELK_OPCODE_ENDIF)
continue;
bblock_t *jump_block = block;
bblock_t *if_block = jump_block->prev();
bblock_t *endif_block = jump_block->next();
elk_bblock_t *jump_block = block;
elk_bblock_t *if_block = jump_block->prev();
elk_bblock_t *endif_block = jump_block->next();
jump_inst->predicate = if_inst->predicate;
jump_inst->predicate_inverse = if_inst->predicate_inverse;
bblock_t *earlier_block = if_block;
elk_bblock_t *earlier_block = if_block;
if (if_block->start_ip == if_block->end_ip) {
earlier_block = if_block->prev();
}
if_inst->remove(if_block);
bblock_t *later_block = endif_block;
elk_bblock_t *later_block = endif_block;
if (endif_block->start_ip == endif_block->end_ip) {
later_block = endif_block->next();
}
@@ -165,7 +165,7 @@ opt_predicated_break(backend_shader *s)
* problem.
*/
assert(earlier_block->start() == NULL ||
earlier_block->start()->opcode != BRW_OPCODE_DO);
earlier_block->start()->opcode != ELK_OPCODE_DO);
earlier_block->unlink_children();
earlier_block->add_successor(s->cfg->mem_ctx, jump_block,
@@ -180,12 +180,12 @@ opt_predicated_break(backend_shader *s)
* one. Instead, promote the link to logical.
*/
bool need_to_link = true;
foreach_list_typed(bblock_link, link, link, &jump_block->children) {
foreach_list_typed(elk_bblock_link, link, link, &jump_block->children) {
if (link->block == later_block) {
assert(later_block->starts_with_control_flow());
/* Update the link from later_block back to jump_block. */
foreach_list_typed(bblock_link, parent_link, link, &later_block->parents) {
foreach_list_typed(elk_bblock_link, parent_link, link, &later_block->parents) {
if (parent_link->block == jump_block) {
parent_link->kind = bblock_link_logical;
}
@@ -218,12 +218,12 @@ opt_predicated_break(backend_shader *s)
* could terminate prematurely. This can occur if the loop contains a
* CONT instruction.
*/
bblock_t *while_block = earlier_block->next();
backend_instruction *while_inst = while_block->start();
elk_bblock_t *while_block = earlier_block->next();
elk_backend_instruction *while_inst = while_block->start();
if (jump_inst->opcode == BRW_OPCODE_BREAK &&
while_inst->opcode == BRW_OPCODE_WHILE &&
while_inst->predicate == BRW_PREDICATE_NONE &&
if (jump_inst->opcode == ELK_OPCODE_BREAK &&
while_inst->opcode == ELK_OPCODE_WHILE &&
while_inst->predicate == ELK_PREDICATE_NONE &&
!has_continue(&state)) {
jump_inst->remove(earlier_block);
while_inst->predicate = jump_inst->predicate;
src/intel/compiler/elk/elk_private.h
+13 -13
View File
@@ -29,15 +29,15 @@
#include <variant>
unsigned brw_required_dispatch_width(const struct shader_info *info);
unsigned elk_required_dispatch_width(const struct shader_info *info);
static constexpr int SIMD_COUNT = 3;
struct brw_simd_selection_state {
struct elk_simd_selection_state {
const struct intel_device_info *devinfo;
std::variant<struct brw_cs_prog_data *,
struct brw_bs_prog_data *> prog_data;
std::variant<struct elk_cs_prog_data *,
struct elk_bs_prog_data *> prog_data;
unsigned required_width;
@@ -47,7 +47,7 @@ struct brw_simd_selection_state {
bool spilled[SIMD_COUNT];
};
inline int brw_simd_first_compiled(const brw_simd_selection_state &state)
inline int elk_simd_first_compiled(const elk_simd_selection_state &state)
{
for (int i = 0; i < SIMD_COUNT; i++) {
if (state.compiled[i])
@@ -56,21 +56,21 @@ inline int brw_simd_first_compiled(const brw_simd_selection_state &state)
return -1;
}
inline bool brw_simd_any_compiled(const brw_simd_selection_state &state)
inline bool elk_simd_any_compiled(const elk_simd_selection_state &state)
{
return brw_simd_first_compiled(state) >= 0;
return elk_simd_first_compiled(state) >= 0;
}
bool brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd);
bool elk_simd_should_compile(elk_simd_selection_state &state, unsigned simd);
void brw_simd_mark_compiled(brw_simd_selection_state &state, unsigned simd, bool spilled);
void elk_simd_mark_compiled(elk_simd_selection_state &state, unsigned simd, bool spilled);
int brw_simd_select(const brw_simd_selection_state &state);
int elk_simd_select(const elk_simd_selection_state &state);
int brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo,
const struct brw_cs_prog_data *prog_data,
int elk_simd_select_for_workgroup_size(const struct intel_device_info *devinfo,
const struct elk_cs_prog_data *prog_data,
const unsigned *sizes);
bool brw_should_print_shader(const nir_shader *shader, uint64_t debug_flag);
bool elk_should_print_shader(const nir_shader *shader, uint64_t debug_flag);
#endif // ELK_PRIVATE_H
src/intel/compiler/elk/elk_reg.h
+477 -477
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_reg_type.c
+219 -219
View File
@@ -28,16 +28,16 @@
#define INVALID (-1)
enum hw_reg_type {
BRW_HW_REG_TYPE_UD = 0,
BRW_HW_REG_TYPE_D = 1,
BRW_HW_REG_TYPE_UW = 2,
BRW_HW_REG_TYPE_W = 3,
BRW_HW_REG_TYPE_F = 7,
ELK_HW_REG_TYPE_UD = 0,
ELK_HW_REG_TYPE_D = 1,
ELK_HW_REG_TYPE_UW = 2,
ELK_HW_REG_TYPE_W = 3,
ELK_HW_REG_TYPE_F = 7,
GFX8_HW_REG_TYPE_UQ = 8,
GFX8_HW_REG_TYPE_Q = 9,
BRW_HW_REG_TYPE_UB = 4,
BRW_HW_REG_TYPE_B = 5,
ELK_HW_REG_TYPE_UB = 4,
ELK_HW_REG_TYPE_B = 5,
GFX7_HW_REG_TYPE_DF = 6,
GFX8_HW_REG_TYPE_HF = 10,
@@ -56,17 +56,17 @@ enum hw_reg_type {
};
enum hw_imm_type {
BRW_HW_IMM_TYPE_UD = 0,
BRW_HW_IMM_TYPE_D = 1,
BRW_HW_IMM_TYPE_UW = 2,
BRW_HW_IMM_TYPE_W = 3,
BRW_HW_IMM_TYPE_F = 7,
ELK_HW_IMM_TYPE_UD = 0,
ELK_HW_IMM_TYPE_D = 1,
ELK_HW_IMM_TYPE_UW = 2,
ELK_HW_IMM_TYPE_W = 3,
ELK_HW_IMM_TYPE_F = 7,
GFX8_HW_IMM_TYPE_UQ = 8,
GFX8_HW_IMM_TYPE_Q = 9,
BRW_HW_IMM_TYPE_UV = 4,
BRW_HW_IMM_TYPE_VF = 5,
BRW_HW_IMM_TYPE_V = 6,
ELK_HW_IMM_TYPE_UV = 4,
ELK_HW_IMM_TYPE_VF = 5,
ELK_HW_IMM_TYPE_V = 6,
GFX8_HW_IMM_TYPE_DF = 10,
GFX8_HW_IMM_TYPE_HF = 11,
@@ -92,120 +92,120 @@ static const struct hw_type {
enum hw_reg_type reg_type;
enum hw_imm_type imm_type;
} gfx4_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF },
[ELK_REGISTER_TYPE_F] = { ELK_HW_REG_TYPE_F, ELK_HW_IMM_TYPE_F },
[ELK_REGISTER_TYPE_VF] = { INVALID, ELK_HW_IMM_TYPE_VF },
[BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD },
[BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W },
[BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
[BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID },
[BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V },
[ELK_REGISTER_TYPE_D] = { ELK_HW_REG_TYPE_D, ELK_HW_IMM_TYPE_D },
[ELK_REGISTER_TYPE_UD] = { ELK_HW_REG_TYPE_UD, ELK_HW_IMM_TYPE_UD },
[ELK_REGISTER_TYPE_W] = { ELK_HW_REG_TYPE_W, ELK_HW_IMM_TYPE_W },
[ELK_REGISTER_TYPE_UW] = { ELK_HW_REG_TYPE_UW, ELK_HW_IMM_TYPE_UW },
[ELK_REGISTER_TYPE_B] = { ELK_HW_REG_TYPE_B, INVALID },
[ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V },
}, gfx6_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF },
[ELK_REGISTER_TYPE_F] = { ELK_HW_REG_TYPE_F, ELK_HW_IMM_TYPE_F },
[ELK_REGISTER_TYPE_VF] = { INVALID, ELK_HW_IMM_TYPE_VF },
[BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD },
[BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W },
[BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
[BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID },
[BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V },
[BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV },
[ELK_REGISTER_TYPE_D] = { ELK_HW_REG_TYPE_D, ELK_HW_IMM_TYPE_D },
[ELK_REGISTER_TYPE_UD] = { ELK_HW_REG_TYPE_UD, ELK_HW_IMM_TYPE_UD },
[ELK_REGISTER_TYPE_W] = { ELK_HW_REG_TYPE_W, ELK_HW_IMM_TYPE_W },
[ELK_REGISTER_TYPE_UW] = { ELK_HW_REG_TYPE_UW, ELK_HW_IMM_TYPE_UW },
[ELK_REGISTER_TYPE_B] = { ELK_HW_REG_TYPE_B, INVALID },
[ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V },
[ELK_REGISTER_TYPE_UV] = { INVALID, ELK_HW_IMM_TYPE_UV },
}, gfx7_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, INVALID },
[BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF },
[ELK_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, INVALID },
[ELK_REGISTER_TYPE_F] = { ELK_HW_REG_TYPE_F, ELK_HW_IMM_TYPE_F },
[ELK_REGISTER_TYPE_VF] = { INVALID, ELK_HW_IMM_TYPE_VF },
[BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD },
[BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W },
[BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
[BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID },
[BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V },
[BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV },
[ELK_REGISTER_TYPE_D] = { ELK_HW_REG_TYPE_D, ELK_HW_IMM_TYPE_D },
[ELK_REGISTER_TYPE_UD] = { ELK_HW_REG_TYPE_UD, ELK_HW_IMM_TYPE_UD },
[ELK_REGISTER_TYPE_W] = { ELK_HW_REG_TYPE_W, ELK_HW_IMM_TYPE_W },
[ELK_REGISTER_TYPE_UW] = { ELK_HW_REG_TYPE_UW, ELK_HW_IMM_TYPE_UW },
[ELK_REGISTER_TYPE_B] = { ELK_HW_REG_TYPE_B, INVALID },
[ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V },
[ELK_REGISTER_TYPE_UV] = { INVALID, ELK_HW_IMM_TYPE_UV },
}, gfx8_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, GFX8_HW_IMM_TYPE_DF },
[BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_HF] = { GFX8_HW_REG_TYPE_HF, GFX8_HW_IMM_TYPE_HF },
[BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF },
[ELK_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, GFX8_HW_IMM_TYPE_DF },
[ELK_REGISTER_TYPE_F] = { ELK_HW_REG_TYPE_F, ELK_HW_IMM_TYPE_F },
[ELK_REGISTER_TYPE_HF] = { GFX8_HW_REG_TYPE_HF, GFX8_HW_IMM_TYPE_HF },
[ELK_REGISTER_TYPE_VF] = { INVALID, ELK_HW_IMM_TYPE_VF },
[BRW_REGISTER_TYPE_Q] = { GFX8_HW_REG_TYPE_Q, GFX8_HW_IMM_TYPE_Q },
[BRW_REGISTER_TYPE_UQ] = { GFX8_HW_REG_TYPE_UQ, GFX8_HW_IMM_TYPE_UQ },
[BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD },
[BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W },
[BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
[BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID },
[BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V },
[BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV },
[ELK_REGISTER_TYPE_Q] = { GFX8_HW_REG_TYPE_Q, GFX8_HW_IMM_TYPE_Q },
[ELK_REGISTER_TYPE_UQ] = { GFX8_HW_REG_TYPE_UQ, GFX8_HW_IMM_TYPE_UQ },
[ELK_REGISTER_TYPE_D] = { ELK_HW_REG_TYPE_D, ELK_HW_IMM_TYPE_D },
[ELK_REGISTER_TYPE_UD] = { ELK_HW_REG_TYPE_UD, ELK_HW_IMM_TYPE_UD },
[ELK_REGISTER_TYPE_W] = { ELK_HW_REG_TYPE_W, ELK_HW_IMM_TYPE_W },
[ELK_REGISTER_TYPE_UW] = { ELK_HW_REG_TYPE_UW, ELK_HW_IMM_TYPE_UW },
[ELK_REGISTER_TYPE_B] = { ELK_HW_REG_TYPE_B, INVALID },
[ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V },
[ELK_REGISTER_TYPE_UV] = { INVALID, ELK_HW_IMM_TYPE_UV },
}, gfx11_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID },
[BRW_REGISTER_TYPE_F] = { GFX11_HW_REG_TYPE_F, GFX11_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_HF] = { GFX11_HW_REG_TYPE_HF, GFX11_HW_IMM_TYPE_HF },
[BRW_REGISTER_TYPE_VF] = { INVALID, GFX11_HW_IMM_TYPE_VF },
[ELK_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID },
[ELK_REGISTER_TYPE_F] = { GFX11_HW_REG_TYPE_F, GFX11_HW_IMM_TYPE_F },
[ELK_REGISTER_TYPE_HF] = { GFX11_HW_REG_TYPE_HF, GFX11_HW_IMM_TYPE_HF },
[ELK_REGISTER_TYPE_VF] = { INVALID, GFX11_HW_IMM_TYPE_VF },
[BRW_REGISTER_TYPE_D] = { GFX11_HW_REG_TYPE_D, GFX11_HW_IMM_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GFX11_HW_REG_TYPE_UD, GFX11_HW_IMM_TYPE_UD },
[BRW_REGISTER_TYPE_W] = { GFX11_HW_REG_TYPE_W, GFX11_HW_IMM_TYPE_W },
[BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
[BRW_REGISTER_TYPE_B] = { GFX11_HW_REG_TYPE_B, INVALID },
[BRW_REGISTER_TYPE_UB] = { GFX11_HW_REG_TYPE_UB, INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, GFX11_HW_IMM_TYPE_V },
[BRW_REGISTER_TYPE_UV] = { INVALID, GFX11_HW_IMM_TYPE_UV },
[ELK_REGISTER_TYPE_D] = { GFX11_HW_REG_TYPE_D, GFX11_HW_IMM_TYPE_D },
[ELK_REGISTER_TYPE_UD] = { GFX11_HW_REG_TYPE_UD, GFX11_HW_IMM_TYPE_UD },
[ELK_REGISTER_TYPE_W] = { GFX11_HW_REG_TYPE_W, GFX11_HW_IMM_TYPE_W },
[ELK_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
[ELK_REGISTER_TYPE_B] = { GFX11_HW_REG_TYPE_B, INVALID },
[ELK_REGISTER_TYPE_UB] = { GFX11_HW_REG_TYPE_UB, INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, GFX11_HW_IMM_TYPE_V },
[ELK_REGISTER_TYPE_UV] = { INVALID, GFX11_HW_IMM_TYPE_UV },
}, gfx12_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) },
[BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
[BRW_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) },
[ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) },
[ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
[ELK_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) },
[BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) },
[BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) },
[BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) },
[BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) },
[BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID },
[BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) },
[BRW_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) },
[ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) },
[ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) },
[ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) },
[ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) },
[ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID },
[ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) },
[ELK_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) },
}, gfx125_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_FLOAT(3), GFX12_HW_REG_TYPE_FLOAT(3) },
[BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) },
[BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
[BRW_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) },
[ELK_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_FLOAT(3), GFX12_HW_REG_TYPE_FLOAT(3) },
[ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) },
[ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
[ELK_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) },
[BRW_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), GFX12_HW_REG_TYPE_SINT(3) },
[BRW_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), GFX12_HW_REG_TYPE_UINT(3) },
[BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) },
[BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) },
[BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) },
[BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) },
[BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID },
[BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID },
[BRW_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) },
[BRW_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) },
[ELK_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), GFX12_HW_REG_TYPE_SINT(3) },
[ELK_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), GFX12_HW_REG_TYPE_UINT(3) },
[ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) },
[ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) },
[ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) },
[ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) },
[ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID },
[ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) },
[ELK_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) },
};
/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
* the types were implied. IVB adds BFE and BFI2 that operate on doublewords
* and unsigned doublewords, so a new field is also available in the da3src
* struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
* struct (part of struct elk_instruction.bits1 in elk_structs.h) to select
* dst and shared-src types.
*
* CNL adds support for 3-src instructions in align1 mode, and with it support
@@ -239,90 +239,90 @@ static const struct hw_3src_type {
enum hw_3src_reg_type reg_type;
enum gfx10_align1_3src_exec_type exec_type;
} gfx6_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
[ELK_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
}, gfx7_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
[BRW_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD },
[BRW_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF },
[ELK_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
[ELK_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D },
[ELK_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD },
[ELK_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF },
}, gfx8_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
[BRW_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD },
[BRW_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF },
[BRW_REGISTER_TYPE_HF] = { GFX8_3SRC_TYPE_HF },
[ELK_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F },
[ELK_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D },
[ELK_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD },
[ELK_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF },
[ELK_REGISTER_TYPE_HF] = { GFX8_3SRC_TYPE_HF },
}, gfx10_hw_3src_align1_type[] = {
#define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
#define E(x) ELK_ALIGN1_3SRC_EXEC_TYPE_##x
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_DF] = { GFX10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) },
[BRW_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[BRW_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[ELK_REGISTER_TYPE_DF] = { GFX10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) },
[ELK_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[ELK_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[BRW_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[BRW_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
[ELK_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[ELK_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[ELK_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[ELK_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[ELK_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[ELK_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
}, gfx11_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) },
[BRW_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[BRW_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[ELK_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) },
[ELK_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[ELK_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[BRW_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[BRW_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
[ELK_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[ELK_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[ELK_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[ELK_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[ELK_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[ELK_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
}, gfx12_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), },
[BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), },
[ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), },
[ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), },
[BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), },
[BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), },
[BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), },
[BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
[BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), },
[BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), },
[ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), },
[ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), },
[ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), },
[ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
[ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), },
[ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), },
}, gfx125_hw_3src_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_UINT(3), E(FLOAT), },
[BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), },
[BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), },
[ELK_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_UINT(3), E(FLOAT), },
[ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), },
[ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), },
[BRW_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), E(INT), },
[BRW_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), E(INT), },
[BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), },
[BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), },
[BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), },
[BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
[BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), },
[BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), },
[ELK_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), E(INT), },
[ELK_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), E(INT), },
[ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), },
[ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), },
[ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), },
[ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
[ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), },
[ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), },
#undef E
};
/**
* Convert a brw_reg_type enumeration value into the hardware representation.
* Convert a elk_reg_type enumeration value into the hardware representation.
*
* The hardware encoding may depend on whether the value is an immediate.
*/
unsigned
brw_reg_type_to_hw_type(const struct intel_device_info *devinfo,
enum brw_reg_file file,
enum brw_reg_type type)
elk_reg_type_to_hw_type(const struct intel_device_info *devinfo,
enum elk_reg_file file,
enum elk_reg_type type)
{
const struct hw_type *table;
@@ -349,7 +349,7 @@ brw_reg_type_to_hw_type(const struct intel_device_info *devinfo,
table = gfx4_hw_type;
}
if (file == BRW_IMMEDIATE_VALUE) {
if (file == ELK_IMMEDIATE_VALUE) {
assert(table[type].imm_type != (enum hw_imm_type)INVALID);
return table[type].imm_type;
} else {
@@ -359,13 +359,13 @@ brw_reg_type_to_hw_type(const struct intel_device_info *devinfo,
}
/**
* Convert the hardware representation into a brw_reg_type enumeration value.
* Convert the hardware representation into a elk_reg_type enumeration value.
*
* The hardware encoding may depend on whether the value is an immediate.
*/
enum brw_reg_type
brw_hw_type_to_reg_type(const struct intel_device_info *devinfo,
enum brw_reg_file file, unsigned hw_type)
enum elk_reg_type
elk_hw_type_to_reg_type(const struct intel_device_info *devinfo,
enum elk_reg_file file, unsigned hw_type)
{
const struct hw_type *table;
@@ -385,14 +385,14 @@ brw_hw_type_to_reg_type(const struct intel_device_info *devinfo,
table = gfx4_hw_type;
}
if (file == BRW_IMMEDIATE_VALUE) {
for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
if (file == ELK_IMMEDIATE_VALUE) {
for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) {
if (table[i].imm_type == (enum hw_imm_type)hw_type) {
return i;
}
}
} else {
for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) {
if (table[i].reg_type == (enum hw_reg_type)hw_type) {
return i;
}
@@ -402,12 +402,12 @@ brw_hw_type_to_reg_type(const struct intel_device_info *devinfo,
}
/**
* Convert a brw_reg_type enumeration value into the hardware representation
* Convert a elk_reg_type enumeration value into the hardware representation
* for a 3-src align16 instruction
*/
unsigned
brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
enum brw_reg_type type)
elk_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
enum elk_reg_type type)
{
const struct hw_3src_type *table;
@@ -427,12 +427,12 @@ brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
}
/**
* Convert a brw_reg_type enumeration value into the hardware representation
* Convert a elk_reg_type enumeration value into the hardware representation
* for a 3-src align1 instruction
*/
unsigned
brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
enum brw_reg_type type)
elk_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
enum elk_reg_type type)
{
if (devinfo->verx10 >= 125) {
assert(type < ARRAY_SIZE(gfx125_hw_3src_type));
@@ -451,10 +451,10 @@ brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
/**
* Convert the hardware representation for a 3-src align16 instruction into a
* brw_reg_type enumeration value.
* elk_reg_type enumeration value.
*/
enum brw_reg_type
brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
enum elk_reg_type
elk_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type)
{
const struct hw_3src_type *table = NULL;
@@ -467,7 +467,7 @@ brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
table = gfx6_hw_3src_type;
}
for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) {
if (table[i].reg_type == hw_type) {
return i;
}
@@ -477,10 +477,10 @@ brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
/**
* Convert the hardware representation for a 3-src align1 instruction into a
* brw_reg_type enumeration value.
* elk_reg_type enumeration value.
*/
enum brw_reg_type
brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
enum elk_reg_type
elk_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type)
{
const struct hw_3src_type *table =
@@ -489,7 +489,7 @@ brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
devinfo->ver >= 11 ? gfx11_hw_3src_type :
gfx10_hw_3src_align1_type);
for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) {
if (table[i].reg_type == hw_type &&
table[i].exec_type == exec_type) {
return i;
@@ -502,25 +502,25 @@ brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
* Return the element size given a register type.
*/
unsigned
brw_reg_type_to_size(enum brw_reg_type type)
elk_reg_type_to_size(enum elk_reg_type type)
{
static const unsigned type_size[] = {
[BRW_REGISTER_TYPE_NF] = 8,
[BRW_REGISTER_TYPE_DF] = 8,
[BRW_REGISTER_TYPE_F] = 4,
[BRW_REGISTER_TYPE_HF] = 2,
[BRW_REGISTER_TYPE_VF] = 4,
[ELK_REGISTER_TYPE_NF] = 8,
[ELK_REGISTER_TYPE_DF] = 8,
[ELK_REGISTER_TYPE_F] = 4,
[ELK_REGISTER_TYPE_HF] = 2,
[ELK_REGISTER_TYPE_VF] = 4,
[BRW_REGISTER_TYPE_Q] = 8,
[BRW_REGISTER_TYPE_UQ] = 8,
[BRW_REGISTER_TYPE_D] = 4,
[BRW_REGISTER_TYPE_UD] = 4,
[BRW_REGISTER_TYPE_W] = 2,
[BRW_REGISTER_TYPE_UW] = 2,
[BRW_REGISTER_TYPE_B] = 1,
[BRW_REGISTER_TYPE_UB] = 1,
[BRW_REGISTER_TYPE_V] = 2,
[BRW_REGISTER_TYPE_UV] = 2,
[ELK_REGISTER_TYPE_Q] = 8,
[ELK_REGISTER_TYPE_UQ] = 8,
[ELK_REGISTER_TYPE_D] = 4,
[ELK_REGISTER_TYPE_UD] = 4,
[ELK_REGISTER_TYPE_W] = 2,
[ELK_REGISTER_TYPE_UW] = 2,
[ELK_REGISTER_TYPE_B] = 1,
[ELK_REGISTER_TYPE_UB] = 1,
[ELK_REGISTER_TYPE_V] = 2,
[ELK_REGISTER_TYPE_UV] = 2,
};
if (type >= ARRAY_SIZE(type_size))
return -1;
@@ -529,31 +529,31 @@ brw_reg_type_to_size(enum brw_reg_type type)
}
/**
* Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
* Converts a ELK_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
*
* This is different than reg_encoding from brw_disasm.c in that it operates
* This is different than reg_encoding from elk_disasm.c in that it operates
* on the abstract enum values, rather than the generation-specific encoding.
*/
const char *
brw_reg_type_to_letters(enum brw_reg_type type)
elk_reg_type_to_letters(enum elk_reg_type type)
{
static const char letters[][3] = {
[BRW_REGISTER_TYPE_NF] = "NF",
[BRW_REGISTER_TYPE_DF] = "DF",
[BRW_REGISTER_TYPE_F] = "F",
[BRW_REGISTER_TYPE_HF] = "HF",
[BRW_REGISTER_TYPE_VF] = "VF",
[ELK_REGISTER_TYPE_NF] = "NF",
[ELK_REGISTER_TYPE_DF] = "DF",
[ELK_REGISTER_TYPE_F] = "F",
[ELK_REGISTER_TYPE_HF] = "HF",
[ELK_REGISTER_TYPE_VF] = "VF",
[BRW_REGISTER_TYPE_Q] = "Q",
[BRW_REGISTER_TYPE_UQ] = "UQ",
[BRW_REGISTER_TYPE_D] = "D",
[BRW_REGISTER_TYPE_UD] = "UD",
[BRW_REGISTER_TYPE_W] = "W",
[BRW_REGISTER_TYPE_UW] = "UW",
[BRW_REGISTER_TYPE_B] = "B",
[BRW_REGISTER_TYPE_UB] = "UB",
[BRW_REGISTER_TYPE_V] = "V",
[BRW_REGISTER_TYPE_UV] = "UV",
[ELK_REGISTER_TYPE_Q] = "Q",
[ELK_REGISTER_TYPE_UQ] = "UQ",
[ELK_REGISTER_TYPE_D] = "D",
[ELK_REGISTER_TYPE_UD] = "UD",
[ELK_REGISTER_TYPE_W] = "W",
[ELK_REGISTER_TYPE_UW] = "UW",
[ELK_REGISTER_TYPE_B] = "B",
[ELK_REGISTER_TYPE_UB] = "UB",
[ELK_REGISTER_TYPE_V] = "V",
[ELK_REGISTER_TYPE_UV] = "UV",
};
if (type >= ARRAY_SIZE(letters))
return "INVALID";
src/intel/compiler/elk/elk_reg_type.h
+78 -78
View File
@@ -36,46 +36,46 @@ extern "C" {
#define ATTRIBUTE_PURE
#endif
enum brw_reg_file;
enum elk_reg_file;
struct intel_device_info;
/*
* The ordering has been chosen so that no enum value is the same as a
* compatible hardware encoding.
*/
enum PACKED brw_reg_type {
enum PACKED elk_reg_type {
/** Floating-point types: @{ */
BRW_REGISTER_TYPE_NF, /* >64-bit (accumulator-only) native float (gfx11+) */
BRW_REGISTER_TYPE_DF, /* 64-bit float (double float) */
BRW_REGISTER_TYPE_F, /* 32-bit float */
BRW_REGISTER_TYPE_HF, /* 16-bit float (half float) */
BRW_REGISTER_TYPE_VF, /* 32-bit vector of 4 8-bit floats */
ELK_REGISTER_TYPE_NF, /* >64-bit (accumulator-only) native float (gfx11+) */
ELK_REGISTER_TYPE_DF, /* 64-bit float (double float) */
ELK_REGISTER_TYPE_F, /* 32-bit float */
ELK_REGISTER_TYPE_HF, /* 16-bit float (half float) */
ELK_REGISTER_TYPE_VF, /* 32-bit vector of 4 8-bit floats */
/** @} */
/** Integer types: @{ */
BRW_REGISTER_TYPE_Q, /* 64-bit signed integer (quad word) */
BRW_REGISTER_TYPE_UQ, /* 64-bit unsigned integer (quad word) */
BRW_REGISTER_TYPE_D, /* 32-bit signed integer (double word) */
BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */
BRW_REGISTER_TYPE_W, /* 16-bit signed integer (word) */
BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */
BRW_REGISTER_TYPE_B, /* 8-bit signed integer (byte) */
BRW_REGISTER_TYPE_UB, /* 8-bit unsigned integer (byte) */
BRW_REGISTER_TYPE_V, /* vector of 8 signed 4-bit integers (treated as W) */
BRW_REGISTER_TYPE_UV, /* vector of 8 unsigned 4-bit integers (treated as UW) */
ELK_REGISTER_TYPE_Q, /* 64-bit signed integer (quad word) */
ELK_REGISTER_TYPE_UQ, /* 64-bit unsigned integer (quad word) */
ELK_REGISTER_TYPE_D, /* 32-bit signed integer (double word) */
ELK_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */
ELK_REGISTER_TYPE_W, /* 16-bit signed integer (word) */
ELK_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */
ELK_REGISTER_TYPE_B, /* 8-bit signed integer (byte) */
ELK_REGISTER_TYPE_UB, /* 8-bit unsigned integer (byte) */
ELK_REGISTER_TYPE_V, /* vector of 8 signed 4-bit integers (treated as W) */
ELK_REGISTER_TYPE_UV, /* vector of 8 unsigned 4-bit integers (treated as UW) */
/** @} */
BRW_REGISTER_TYPE_LAST = BRW_REGISTER_TYPE_UV
ELK_REGISTER_TYPE_LAST = ELK_REGISTER_TYPE_UV
};
static inline bool
brw_reg_type_is_floating_point(enum brw_reg_type type)
elk_reg_type_is_floating_point(enum elk_reg_type type)
{
switch (type) {
case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
case ELK_REGISTER_TYPE_NF:
case ELK_REGISTER_TYPE_DF:
case ELK_REGISTER_TYPE_F:
case ELK_REGISTER_TYPE_HF:
return true;
default:
return false;
@@ -83,17 +83,17 @@ brw_reg_type_is_floating_point(enum brw_reg_type type)
}
static inline bool
brw_reg_type_is_integer(enum brw_reg_type type)
elk_reg_type_is_integer(enum elk_reg_type type)
{
switch (type) {
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_UB:
case ELK_REGISTER_TYPE_Q:
case ELK_REGISTER_TYPE_UQ:
case ELK_REGISTER_TYPE_D:
case ELK_REGISTER_TYPE_UD:
case ELK_REGISTER_TYPE_W:
case ELK_REGISTER_TYPE_UW:
case ELK_REGISTER_TYPE_B:
case ELK_REGISTER_TYPE_UB:
return true;
default:
return false;
@@ -101,65 +101,65 @@ brw_reg_type_is_integer(enum brw_reg_type type)
}
static inline bool
brw_reg_type_is_unsigned_integer(enum brw_reg_type tp)
elk_reg_type_is_unsigned_integer(enum elk_reg_type tp)
{
return tp == BRW_REGISTER_TYPE_UB ||
tp == BRW_REGISTER_TYPE_UW ||
tp == BRW_REGISTER_TYPE_UD ||
tp == BRW_REGISTER_TYPE_UQ;
return tp == ELK_REGISTER_TYPE_UB ||
tp == ELK_REGISTER_TYPE_UW ||
tp == ELK_REGISTER_TYPE_UD ||
tp == ELK_REGISTER_TYPE_UQ;
}
/*
* Returns a type based on a reference_type (word, float, half-float) and a
* given bit_size.
*/
static inline enum brw_reg_type
brw_reg_type_from_bit_size(unsigned bit_size,
enum brw_reg_type reference_type)
static inline enum elk_reg_type
elk_reg_type_from_bit_size(unsigned bit_size,
enum elk_reg_type reference_type)
{
switch(reference_type) {
case BRW_REGISTER_TYPE_HF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_DF:
case ELK_REGISTER_TYPE_HF:
case ELK_REGISTER_TYPE_F:
case ELK_REGISTER_TYPE_DF:
switch(bit_size) {
case 16:
return BRW_REGISTER_TYPE_HF;
return ELK_REGISTER_TYPE_HF;
case 32:
return BRW_REGISTER_TYPE_F;
return ELK_REGISTER_TYPE_F;
case 64:
return BRW_REGISTER_TYPE_DF;
return ELK_REGISTER_TYPE_DF;
default:
unreachable("Invalid bit size");
}
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_Q:
case ELK_REGISTER_TYPE_B:
case ELK_REGISTER_TYPE_W:
case ELK_REGISTER_TYPE_D:
case ELK_REGISTER_TYPE_Q:
switch(bit_size) {
case 8:
return BRW_REGISTER_TYPE_B;
return ELK_REGISTER_TYPE_B;
case 16:
return BRW_REGISTER_TYPE_W;
return ELK_REGISTER_TYPE_W;
case 32:
return BRW_REGISTER_TYPE_D;
return ELK_REGISTER_TYPE_D;
case 64:
return BRW_REGISTER_TYPE_Q;
return ELK_REGISTER_TYPE_Q;
default:
unreachable("Invalid bit size");
}
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_UQ:
case ELK_REGISTER_TYPE_UB:
case ELK_REGISTER_TYPE_UW:
case ELK_REGISTER_TYPE_UD:
case ELK_REGISTER_TYPE_UQ:
switch(bit_size) {
case 8:
return BRW_REGISTER_TYPE_UB;
return ELK_REGISTER_TYPE_UB;
case 16:
return BRW_REGISTER_TYPE_UW;
return ELK_REGISTER_TYPE_UW;
case 32:
return BRW_REGISTER_TYPE_UD;
return ELK_REGISTER_TYPE_UD;
case 64:
return BRW_REGISTER_TYPE_UQ;
return ELK_REGISTER_TYPE_UQ;
default:
unreachable("Invalid bit size");
}
@@ -169,38 +169,38 @@ brw_reg_type_from_bit_size(unsigned bit_size,
}
#define INVALID_REG_TYPE ((enum brw_reg_type)-1)
#define INVALID_REG_TYPE ((enum elk_reg_type)-1)
#define INVALID_HW_REG_TYPE ((unsigned)-1)
unsigned
brw_reg_type_to_hw_type(const struct intel_device_info *devinfo,
enum brw_reg_file file, enum brw_reg_type type);
elk_reg_type_to_hw_type(const struct intel_device_info *devinfo,
enum elk_reg_file file, enum elk_reg_type type);
enum brw_reg_type ATTRIBUTE_PURE
brw_hw_type_to_reg_type(const struct intel_device_info *devinfo,
enum brw_reg_file file, unsigned hw_type);
enum elk_reg_type ATTRIBUTE_PURE
elk_hw_type_to_reg_type(const struct intel_device_info *devinfo,
enum elk_reg_file file, unsigned hw_type);
unsigned
brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
enum brw_reg_type type);
elk_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
enum elk_reg_type type);
unsigned
brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
enum brw_reg_type type);
elk_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
enum elk_reg_type type);
enum brw_reg_type
brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
enum elk_reg_type
elk_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type);
enum brw_reg_type
brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
enum elk_reg_type
elk_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type);
unsigned
brw_reg_type_to_size(enum brw_reg_type type);
elk_reg_type_to_size(enum elk_reg_type type);
const char *
brw_reg_type_to_letters(enum brw_reg_type type);
elk_reg_type_to_letters(enum elk_reg_type type);
#ifdef __cplusplus
}
src/intel/compiler/elk/elk_schedule_instructions.cpp
+197 -197
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_shader.cpp
+520 -520
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_shader.h
+35 -35
View File
@@ -43,47 +43,47 @@ enum instruction_scheduler_mode {
#define UBO_START ((1 << 16) - 4)
struct backend_shader {
struct elk_backend_shader {
protected:
backend_shader(const struct brw_compiler *compiler,
const struct brw_compile_params *params,
elk_backend_shader(const struct elk_compiler *compiler,
const struct elk_compile_params *params,
const nir_shader *shader,
struct brw_stage_prog_data *stage_prog_data,
struct elk_stage_prog_data *stage_prog_data,
bool debug_enabled);
public:
virtual ~backend_shader();
virtual ~elk_backend_shader();
const struct brw_compiler *compiler;
const struct elk_compiler *compiler;
void *log_data; /* Passed to compiler->*_log functions */
const struct intel_device_info * const devinfo;
const nir_shader *nir;
struct brw_stage_prog_data * const stage_prog_data;
struct elk_stage_prog_data * const stage_prog_data;
/** ralloc context for temporary data used during compile */
void *mem_ctx;
/**
* List of either fs_inst or vec4_instruction (inheriting from
* backend_instruction)
* List of either elk_fs_inst or vec4_instruction (inheriting from
* elk_backend_instruction)
*/
exec_list instructions;
cfg_t *cfg;
brw_analysis<elk::idom_tree, backend_shader> idom_analysis;
elk_cfg_t *cfg;
elk_analysis<elk::idom_tree, elk_backend_shader> idom_analysis;
gl_shader_stage stage;
bool debug_enabled;
elk::simple_allocator alloc;
virtual void dump_instruction_to_file(const backend_instruction *inst, FILE *file) const = 0;
virtual void dump_instruction_to_file(const elk_backend_instruction *inst, FILE *file) const = 0;
virtual void dump_instructions_to_file(FILE *file) const;
/* Convenience functions based on the above. */
void dump_instruction(const backend_instruction *inst, FILE *file = stderr) const {
void dump_instruction(const elk_backend_instruction *inst, FILE *file = stderr) const {
dump_instruction_to_file(inst, file);
}
void dump_instructions(const char *name = nullptr) const;
@@ -94,43 +94,43 @@ public:
};
#else
struct backend_shader;
struct elk_backend_shader;
#endif /* __cplusplus */
enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
uint32_t brw_math_function(enum opcode op);
const char *brw_instruction_name(const struct brw_isa_info *isa,
enum opcode op);
bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
enum elk_reg_type elk_type_for_base_type(const struct glsl_type *type);
uint32_t elk_math_function(enum elk_opcode op);
const char *elk_instruction_name(const struct elk_isa_info *isa,
enum elk_opcode op);
bool elk_saturate_immediate(enum elk_reg_type type, struct elk_reg *reg);
bool elk_negate_immediate(enum elk_reg_type type, struct elk_reg *reg);
bool elk_abs_immediate(enum elk_reg_type type, struct elk_reg *reg);
bool opt_predicated_break(struct backend_shader *s);
bool elk_opt_predicated_break(struct elk_backend_shader *s);
#ifdef __cplusplus
extern "C" {
#endif
/* brw_fs_reg_allocate.cpp */
void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
/* elk_fs_reg_allocate.cpp */
void elk_fs_alloc_reg_sets(struct elk_compiler *compiler);
/* brw_vec4_reg_allocate.cpp */
void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
/* elk_vec4_reg_allocate.cpp */
void elk_vec4_alloc_reg_set(struct elk_compiler *compiler);
/* brw_disasm.c */
extern const char *const conditional_modifier[16];
extern const char *const pred_ctrl_align16[16];
/* elk_disasm.c */
extern const char *const elk_conditional_modifier[16];
extern const char *const elk_pred_ctrl_align16[16];
/* Per-thread scratch space is a power-of-two multiple of 1KB. */
static inline unsigned
brw_get_scratch_size(int size)
elk_get_scratch_size(int size)
{
return MAX2(1024, util_next_power_of_two(size));
}
static inline nir_variable_mode
brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
elk_nir_no_indirect_mask(const struct elk_compiler *compiler,
gl_shader_stage stage)
{
const struct intel_device_info *devinfo = compiler->devinfo;
@@ -158,7 +158,7 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
/* On HSW+, we allow indirects in scalar shaders. They get implemented
* using nir_lower_vars_to_explicit_types and nir_lower_explicit_io in
* brw_postprocess_nir.
* elk_postprocess_nir.
*
* We haven't plumbed through the indirect scratch messages on gfx6 or
* earlier so doing indirects via scratch doesn't work there. On gfx7 and
@@ -172,15 +172,15 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
return indirect_mask;
}
bool brw_texture_offset(const nir_tex_instr *tex, unsigned src,
bool elk_texture_offset(const nir_tex_instr *tex, unsigned src,
uint32_t *offset_bits);
/**
* Scratch data used when compiling a GLSL geometry shader.
*/
struct brw_gs_compile
struct elk_gs_compile
{
struct brw_gs_prog_key key;
struct elk_gs_prog_key key;
struct intel_vue_map input_vue_map;
unsigned control_data_bits_per_vertex;
src/intel/compiler/elk/elk_simd_selection.cpp
+23 -23
View File
@@ -28,7 +28,7 @@
#include "util/ralloc.h"
unsigned
brw_required_dispatch_width(const struct shader_info *info)
elk_required_dispatch_width(const struct shader_info *info)
{
if ((int)info->subgroup_size >= (int)SUBGROUP_SIZE_REQUIRE_8) {
assert(gl_shader_stage_uses_workgroup(info->stage));
@@ -48,20 +48,20 @@ test_bit(unsigned mask, unsigned bit) {
namespace {
struct brw_cs_prog_data *
get_cs_prog_data(brw_simd_selection_state &state)
struct elk_cs_prog_data *
get_cs_prog_data(elk_simd_selection_state &state)
{
if (std::holds_alternative<struct brw_cs_prog_data *>(state.prog_data))
return std::get<struct brw_cs_prog_data *>(state.prog_data);
if (std::holds_alternative<struct elk_cs_prog_data *>(state.prog_data))
return std::get<struct elk_cs_prog_data *>(state.prog_data);
else
return nullptr;
}
struct brw_stage_prog_data *
get_prog_data(brw_simd_selection_state &state)
struct elk_stage_prog_data *
get_prog_data(elk_simd_selection_state &state)
{
if (std::holds_alternative<struct brw_cs_prog_data *>(state.prog_data))
return &std::get<struct brw_cs_prog_data *>(state.prog_data)->base;
if (std::holds_alternative<struct elk_cs_prog_data *>(state.prog_data))
return &std::get<struct elk_cs_prog_data *>(state.prog_data)->base;
else
return nullptr;
}
@@ -69,7 +69,7 @@ get_prog_data(brw_simd_selection_state &state)
}
bool
brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd)
elk_simd_should_compile(elk_simd_selection_state &state, unsigned simd)
{
assert(simd < SIMD_COUNT);
assert(!state.compiled[simd]);
@@ -148,7 +148,7 @@ brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd)
start = DEBUG_CS_SIMD8;
break;
default:
unreachable("unknown shader stage in brw_simd_should_compile");
unreachable("unknown shader stage in elk_simd_should_compile");
}
const bool env_skip[] = {
@@ -168,7 +168,7 @@ brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd)
}
void
brw_simd_mark_compiled(brw_simd_selection_state &state, unsigned simd, bool spilled)
elk_simd_mark_compiled(elk_simd_selection_state &state, unsigned simd, bool spilled)
{
assert(simd < SIMD_COUNT);
assert(!state.compiled[simd]);
@@ -190,7 +190,7 @@ brw_simd_mark_compiled(brw_simd_selection_state &state, unsigned simd, bool spil
}
int
brw_simd_select(const struct brw_simd_selection_state &state)
elk_simd_select(const struct elk_simd_selection_state &state)
{
for (int i = SIMD_COUNT - 1; i >= 0; i--) {
if (state.compiled[i] && !state.spilled[i])
@@ -204,15 +204,15 @@ brw_simd_select(const struct brw_simd_selection_state &state)
}
int
brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo,
const struct brw_cs_prog_data *prog_data,
elk_simd_select_for_workgroup_size(const struct intel_device_info *devinfo,
const struct elk_cs_prog_data *prog_data,
const unsigned *sizes)
{
if (!sizes || (prog_data->local_size[0] == sizes[0] &&
prog_data->local_size[1] == sizes[1] &&
prog_data->local_size[2] == sizes[2])) {
brw_simd_selection_state simd_state{
.prog_data = const_cast<struct brw_cs_prog_data *>(prog_data),
elk_simd_selection_state simd_state{
.prog_data = const_cast<struct elk_cs_prog_data *>(prog_data),
};
/* Propagate the prog_data information back to the simd_state,
@@ -223,17 +223,17 @@ brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo,
simd_state.spilled[i] = test_bit(prog_data->prog_spilled, i);
}
return brw_simd_select(simd_state);
return elk_simd_select(simd_state);
}
struct brw_cs_prog_data cloned = *prog_data;
struct elk_cs_prog_data cloned = *prog_data;
for (unsigned i = 0; i < 3; i++)
cloned.local_size[i] = sizes[i];
cloned.prog_mask = 0;
cloned.prog_spilled = 0;
brw_simd_selection_state simd_state{
elk_simd_selection_state simd_state{
.devinfo = devinfo,
.prog_data = &cloned,
};
@@ -242,11 +242,11 @@ brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo,
/* We are not recompiling, so use original results of prog_mask and
* prog_spilled as they will already contain all possible compilations.
*/
if (brw_simd_should_compile(simd_state, simd) &&
if (elk_simd_should_compile(simd_state, simd) &&
test_bit(prog_data->prog_mask, simd)) {
brw_simd_mark_compiled(simd_state, simd, test_bit(prog_data->prog_spilled, simd));
elk_simd_mark_compiled(simd_state, simd, test_bit(prog_data->prog_spilled, simd));
}
}
return brw_simd_select(simd_state);
return elk_simd_select(simd_state);
}
src/intel/compiler/elk/elk_test_eu_compact.cpp
+85 -85
View File
@@ -42,10 +42,10 @@ get_compact_params_name(const testing::TestParamInfo<CompactParams> p)
std::stringstream ss;
ss << params.verx10 << "_";
switch (params.align) {
case BRW_ALIGN_1:
case ELK_ALIGN_1:
ss << "Align_1";
break;
case BRW_ALIGN_16:
case ELK_ALIGN_16:
ss << "Align_16";
break;
default:
@@ -55,27 +55,27 @@ get_compact_params_name(const testing::TestParamInfo<CompactParams> p)
}
static bool
test_compact_instruction(struct brw_codegen *p, brw_inst src)
test_compact_instruction(struct elk_codegen *p, elk_inst src)
{
brw_compact_inst dst;
elk_compact_inst dst;
memset(&dst, 0xd0, sizeof(dst));
if (brw_try_compact_instruction(p->isa, &dst, &src)) {
brw_inst uncompacted;
if (elk_try_compact_instruction(p->isa, &dst, &src)) {
elk_inst uncompacted;
brw_uncompact_instruction(p->isa, &uncompacted, &dst);
elk_uncompact_instruction(p->isa, &uncompacted, &dst);
if (memcmp(&uncompacted, &src, sizeof(src))) {
brw_debug_compact_uncompact(p->isa, &src, &uncompacted);
elk_debug_compact_uncompact(p->isa, &src, &uncompacted);
return false;
}
} else {
brw_compact_inst unchanged;
elk_compact_inst unchanged;
memset(&unchanged, 0xd0, sizeof(unchanged));
/* It's not supposed to change dst unless it compacted. */
if (memcmp(&unchanged, &dst, sizeof(dst))) {
fprintf(stderr, "Failed to compact, but dst changed\n");
fprintf(stderr, " Instruction: ");
brw_disassemble_inst(stderr, p->isa, &src, false, 0, NULL);
elk_disassemble_inst(stderr, p->isa, &src, false, 0, NULL);
return false;
}
}
@@ -91,27 +91,27 @@ test_compact_instruction(struct brw_codegen *p, brw_inst src)
* become meaningless once fuzzing twiddles a related bit.
*/
static void
clear_pad_bits(const struct brw_isa_info *isa, brw_inst *inst)
clear_pad_bits(const struct elk_isa_info *isa, elk_inst *inst)
{
const struct intel_device_info *devinfo = isa->devinfo;
if (brw_inst_opcode(isa, inst) != BRW_OPCODE_SEND &&
brw_inst_opcode(isa, inst) != BRW_OPCODE_SENDC &&
brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
brw_inst_set_bits(inst, 127, 111, 0);
if (elk_inst_opcode(isa, inst) != ELK_OPCODE_SEND &&
elk_inst_opcode(isa, inst) != ELK_OPCODE_SENDC &&
elk_inst_src0_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE &&
elk_inst_src1_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE) {
elk_inst_set_bits(inst, 127, 111, 0);
}
if (devinfo->ver == 8 && devinfo->platform != INTEL_PLATFORM_CHV &&
is_3src(isa, brw_inst_opcode(isa, inst))) {
brw_inst_set_bits(inst, 105, 105, 0);
brw_inst_set_bits(inst, 84, 84, 0);
brw_inst_set_bits(inst, 36, 35, 0);
elk_is_3src(isa, elk_inst_opcode(isa, inst))) {
elk_inst_set_bits(inst, 105, 105, 0);
elk_inst_set_bits(inst, 84, 84, 0);
elk_inst_set_bits(inst, 36, 35, 0);
}
}
static bool
skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit)
skip_bit(const struct elk_isa_info *isa, elk_inst *src, int bit)
{
const struct intel_device_info *devinfo = isa->devinfo;
@@ -123,7 +123,7 @@ skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit)
if (bit == 29)
return true;
if (is_3src(isa, brw_inst_opcode(isa, src))) {
if (elk_is_3src(isa, elk_inst_opcode(isa, src))) {
if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
if (bit == 127)
return true;
@@ -160,10 +160,10 @@ skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit)
}
/* sometimes these are pad bits. */
if (brw_inst_opcode(isa, src) != BRW_OPCODE_SEND &&
brw_inst_opcode(isa, src) != BRW_OPCODE_SENDC &&
brw_inst_src0_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
if (elk_inst_opcode(isa, src) != ELK_OPCODE_SEND &&
elk_inst_opcode(isa, src) != ELK_OPCODE_SENDC &&
elk_inst_src0_reg_file(devinfo, src) != ELK_IMMEDIATE_VALUE &&
elk_inst_src1_reg_file(devinfo, src) != ELK_IMMEDIATE_VALUE &&
bit >= 121) {
return true;
}
@@ -172,14 +172,14 @@ skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit)
}
static bool
test_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src)
test_fuzz_compact_instruction(struct elk_codegen *p, elk_inst src)
{
for (int bit0 = 0; bit0 < 128; bit0++) {
if (skip_bit(p->isa, &src, bit0))
continue;
for (int bit1 = 0; bit1 < 128; bit1++) {
brw_inst instr = src;
elk_inst instr = src;
uint64_t *bits = instr.data;
if (skip_bit(p->isa, &src, bit1))
@@ -190,7 +190,7 @@ test_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src)
clear_pad_bits(p->isa, &instr);
if (!brw_validate_instruction(p->isa, &instr, 0, sizeof(brw_inst), NULL))
if (!elk_validate_instruction(p->isa, &instr, 0, sizeof(elk_inst), NULL))
continue;
if (!test_compact_instruction(p, instr)) {
@@ -209,15 +209,15 @@ protected:
CompactParams params = GetParam();
mem_ctx = ralloc_context(NULL);
devinfo = rzalloc(mem_ctx, intel_device_info);
p = rzalloc(mem_ctx, brw_codegen);
p = rzalloc(mem_ctx, elk_codegen);
devinfo->verx10 = params.verx10;
devinfo->ver = devinfo->verx10 / 10;
brw_init_isa_info(&isa, devinfo);
brw_init_codegen(&isa, p, p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_access_mode(p, params.align);
elk_init_isa_info(&isa, devinfo);
elk_init_codegen(&isa, p, p);
elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
elk_set_default_access_mode(p, params.align);
};
virtual void TearDown() {
@@ -229,9 +229,9 @@ protected:
};
void *mem_ctx;
struct brw_isa_info isa;
struct elk_isa_info isa;
intel_device_info *devinfo;
brw_codegen *p;
elk_codegen *p;
};
class Instructions : public CompactTestFixture {};
@@ -240,15 +240,15 @@ INSTANTIATE_TEST_SUITE_P(
CompactTest,
Instructions,
testing::Values(
CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 },
CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 },
CompactParams{ 70, BRW_ALIGN_1 }, CompactParams{ 70, BRW_ALIGN_16 },
CompactParams{ 75, BRW_ALIGN_1 }, CompactParams{ 75, BRW_ALIGN_16 },
CompactParams{ 80, BRW_ALIGN_1 }, CompactParams{ 80, BRW_ALIGN_16 },
CompactParams{ 90, BRW_ALIGN_1 }, CompactParams{ 90, BRW_ALIGN_16 },
CompactParams{ 110, BRW_ALIGN_1 },
CompactParams{ 120, BRW_ALIGN_1 },
CompactParams{ 125, BRW_ALIGN_1 }
CompactParams{ 50, ELK_ALIGN_1 }, CompactParams{ 50, ELK_ALIGN_16 },
CompactParams{ 60, ELK_ALIGN_1 }, CompactParams{ 60, ELK_ALIGN_16 },
CompactParams{ 70, ELK_ALIGN_1 }, CompactParams{ 70, ELK_ALIGN_16 },
CompactParams{ 75, ELK_ALIGN_1 }, CompactParams{ 75, ELK_ALIGN_16 },
CompactParams{ 80, ELK_ALIGN_1 }, CompactParams{ 80, ELK_ALIGN_16 },
CompactParams{ 90, ELK_ALIGN_1 }, CompactParams{ 90, ELK_ALIGN_16 },
CompactParams{ 110, ELK_ALIGN_1 },
CompactParams{ 120, ELK_ALIGN_1 },
CompactParams{ 125, ELK_ALIGN_1 }
),
get_compact_params_name);
@@ -258,81 +258,81 @@ INSTANTIATE_TEST_SUITE_P(
CompactTest,
InstructionsBeforeIvyBridge,
testing::Values(
CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 },
CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 }
CompactParams{ 50, ELK_ALIGN_1 }, CompactParams{ 50, ELK_ALIGN_16 },
CompactParams{ 60, ELK_ALIGN_1 }, CompactParams{ 60, ELK_ALIGN_16 }
),
get_compact_params_name);
TEST_P(Instructions, ADD_GRF_GRF_GRF)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
struct brw_reg g4 = brw_vec8_grf(4, 0);
struct elk_reg g0 = elk_vec8_grf(0, 0);
struct elk_reg g2 = elk_vec8_grf(2, 0);
struct elk_reg g4 = elk_vec8_grf(4, 0);
brw_ADD(p, g0, g2, g4);
elk_ADD(p, g0, g2, g4);
}
TEST_P(Instructions, ADD_GRF_GRF_IMM)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
struct elk_reg g0 = elk_vec8_grf(0, 0);
struct elk_reg g2 = elk_vec8_grf(2, 0);
brw_ADD(p, g0, g2, brw_imm_f(1.0));
elk_ADD(p, g0, g2, elk_imm_f(1.0));
}
TEST_P(Instructions, ADD_GRF_GRF_IMM_d)
{
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D);
struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D);
struct elk_reg g0 = retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_D);
struct elk_reg g2 = retype(elk_vec8_grf(2, 0), ELK_REGISTER_TYPE_D);
brw_ADD(p, g0, g2, brw_imm_d(1));
elk_ADD(p, g0, g2, elk_imm_d(1));
}
TEST_P(Instructions, MOV_GRF_GRF)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
struct elk_reg g0 = elk_vec8_grf(0, 0);
struct elk_reg g2 = elk_vec8_grf(2, 0);
brw_MOV(p, g0, g2);
elk_MOV(p, g0, g2);
}
TEST_P(InstructionsBeforeIvyBridge, ADD_MRF_GRF_GRF)
{
struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
struct brw_reg g4 = brw_vec8_grf(4, 0);
struct elk_reg m6 = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 6, 0);
struct elk_reg g2 = elk_vec8_grf(2, 0);
struct elk_reg g4 = elk_vec8_grf(4, 0);
brw_ADD(p, m6, g2, g4);
elk_ADD(p, m6, g2, g4);
}
TEST_P(Instructions, ADD_vec1_GRF_GRF_GRF)
{
struct brw_reg g0 = brw_vec1_grf(0, 0);
struct brw_reg g2 = brw_vec1_grf(2, 0);
struct brw_reg g4 = brw_vec1_grf(4, 0);
struct elk_reg g0 = elk_vec1_grf(0, 0);
struct elk_reg g2 = elk_vec1_grf(2, 0);
struct elk_reg g4 = elk_vec1_grf(4, 0);
brw_ADD(p, g0, g2, g4);
elk_ADD(p, g0, g2, g4);
}
TEST_P(InstructionsBeforeIvyBridge, PLN_MRF_GRF_GRF)
{
struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
struct brw_reg interp = brw_vec1_grf(2, 0);
struct brw_reg g4 = brw_vec8_grf(4, 0);
struct elk_reg m6 = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 6, 0);
struct elk_reg interp = elk_vec1_grf(2, 0);
struct elk_reg g4 = elk_vec8_grf(4, 0);
brw_PLN(p, m6, interp, g4);
elk_PLN(p, m6, interp, g4);
}
TEST_P(Instructions, f0_0_MOV_GRF_GRF)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
struct elk_reg g0 = elk_vec8_grf(0, 0);
struct elk_reg g2 = elk_vec8_grf(2, 0);
brw_push_insn_state(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_MOV(p, g0, g2);
brw_pop_insn_state(p);
elk_push_insn_state(p);
elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL);
elk_MOV(p, g0, g2);
elk_pop_insn_state(p);
}
/* The handling of f0.1 vs f0.0 changes between gfx6 and gfx7. Explicitly test
@@ -341,12 +341,12 @@ TEST_P(Instructions, f0_0_MOV_GRF_GRF)
*/
TEST_P(Instructions, f0_1_MOV_GRF_GRF)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
struct elk_reg g0 = elk_vec8_grf(0, 0);
struct elk_reg g2 = elk_vec8_grf(2, 0);
brw_push_insn_state(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_inst *mov = brw_MOV(p, g0, g2);
brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1);
brw_pop_insn_state(p);
elk_push_insn_state(p);
elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL);
elk_inst *mov = elk_MOV(p, g0, g2);
elk_inst_set_flag_subreg_nr(p->devinfo, mov, 1);
elk_pop_insn_state(p);
}
src/intel/compiler/elk/elk_test_eu_validate.cpp
+943 -943
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_test_fs_cmod_propagation.cpp
+797 -797
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_test_fs_combine_constants.cpp
+18 -18
View File
@@ -20,7 +20,7 @@ struct FSCombineConstantsTest : public ::testing::Test {
compiler = {};
compiler.devinfo = &devinfo;
brw_init_isa_info(&compiler.isa, &devinfo);
elk_init_isa_info(&compiler.isa, &devinfo);
params = {};
params.mem_ctx = mem_ctx;
@@ -29,7 +29,7 @@ struct FSCombineConstantsTest : public ::testing::Test {
nir_shader *nir =
nir_shader_create(mem_ctx, MESA_SHADER_COMPUTE, NULL, NULL);
shader = new fs_visitor(&compiler, &params, NULL,
shader = new elk_fs_visitor(&compiler, &params, NULL,
&prog_data.base, nir, 8, false, false);
}
@@ -40,15 +40,15 @@ struct FSCombineConstantsTest : public ::testing::Test {
}
void *mem_ctx;
brw_compiler compiler;
brw_compile_params params;
elk_compiler compiler;
elk_compile_params params;
intel_device_info devinfo;
struct brw_wm_prog_data prog_data;
struct elk_wm_prog_data prog_data;
struct gl_shader_program *shader_prog;
fs_visitor *shader;
elk_fs_visitor *shader;
bool opt_combine_constants(fs_visitor *s) {
bool opt_combine_constants(elk_fs_visitor *s) {
const bool print = getenv("TEST_DEBUG");
if (print) {
@@ -68,7 +68,7 @@ struct FSCombineConstantsTest : public ::testing::Test {
};
static fs_builder
make_builder(fs_visitor *s)
make_builder(elk_fs_visitor *s)
{
return fs_builder(s, s->dispatch_width).at_end();
}
@@ -77,9 +77,9 @@ TEST_F(FSCombineConstantsTest, Simple)
{
fs_builder bld = make_builder(shader);
fs_reg r = brw_vec8_grf(1, 0);
fs_reg imm_a = brw_imm_ud(1);
fs_reg imm_b = brw_imm_ud(2);
elk_fs_reg r = elk_vec8_grf(1, 0);
elk_fs_reg imm_a = elk_imm_ud(1);
elk_fs_reg imm_b = elk_imm_ud(2);
bld.SEL(r, imm_a, imm_b);
shader->calculate_cfg();
@@ -88,24 +88,24 @@ TEST_F(FSCombineConstantsTest, Simple)
ASSERT_TRUE(progress);
ASSERT_EQ(shader->cfg->num_blocks, 1);
bblock_t *block = cfg_first_block(shader->cfg);
elk_bblock_t *block = cfg_first_block(shader->cfg);
ASSERT_NE(block, nullptr);
/* We can do better but for now sanity check that
* there's a MOV and a SEL.
*/
ASSERT_EQ(bblock_start(block)->opcode, BRW_OPCODE_MOV);
ASSERT_EQ(bblock_end(block)->opcode, BRW_OPCODE_SEL);
ASSERT_EQ(bblock_start(block)->opcode, ELK_OPCODE_MOV);
ASSERT_EQ(bblock_end(block)->opcode, ELK_OPCODE_SEL);
}
TEST_F(FSCombineConstantsTest, DoContainingDo)
{
fs_builder bld = make_builder(shader);
fs_reg r1 = brw_vec8_grf(1, 0);
fs_reg r2 = brw_vec8_grf(2, 0);
fs_reg imm_a = brw_imm_ud(1);
fs_reg imm_b = brw_imm_ud(2);
elk_fs_reg r1 = elk_vec8_grf(1, 0);
elk_fs_reg r2 = elk_vec8_grf(2, 0);
elk_fs_reg imm_a = elk_imm_ud(1);
elk_fs_reg imm_b = elk_imm_ud(2);
bld.DO();
bld.DO();
src/intel/compiler/elk/elk_test_fs_copy_propagation.cpp
+54 -54
View File
@@ -33,24 +33,24 @@ protected:
copy_propagation_test();
~copy_propagation_test() override;
struct brw_compiler *compiler;
struct brw_compile_params params;
struct elk_compiler *compiler;
struct elk_compile_params params;
struct intel_device_info *devinfo;
void *ctx;
struct brw_wm_prog_data *prog_data;
struct elk_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
fs_visitor *v;
elk_fs_visitor *v;
fs_builder bld;
};
class copy_propagation_fs_visitor : public fs_visitor
class copy_propagation_fs_visitor : public elk_fs_visitor
{
public:
copy_propagation_fs_visitor(struct brw_compiler *compiler,
struct brw_compile_params *params,
struct brw_wm_prog_data *prog_data,
copy_propagation_fs_visitor(struct elk_compiler *compiler,
struct elk_compile_params *params,
struct elk_wm_prog_data *prog_data,
nir_shader *shader)
: fs_visitor(compiler, params, NULL,
: elk_fs_visitor(compiler, params, NULL,
&prog_data->base, shader, 8, false, false) {}
};
@@ -59,14 +59,14 @@ copy_propagation_test::copy_propagation_test()
: bld(NULL, 0)
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
compiler = rzalloc(ctx, struct elk_compiler);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
params = {};
params.mem_ctx = ctx;
prog_data = ralloc(ctx, struct brw_wm_prog_data);
prog_data = ralloc(ctx, struct elk_wm_prog_data);
nir_shader *shader =
nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL);
@@ -87,18 +87,18 @@ copy_propagation_test::~copy_propagation_test()
ctx = NULL;
}
static fs_inst *
instruction(bblock_t *block, int num)
static elk_fs_inst *
instruction(elk_bblock_t *block, int num)
{
fs_inst *inst = (fs_inst *)block->start();
elk_fs_inst *inst = (elk_fs_inst *)block->start();
for (int i = 0; i < num; i++) {
inst = (fs_inst *)inst->next;
inst = (elk_fs_inst *)inst->next;
}
return inst;
}
static bool
copy_propagation(fs_visitor *v)
copy_propagation(elk_fs_visitor *v)
{
const bool print = getenv("TEST_DEBUG");
@@ -119,10 +119,10 @@ copy_propagation(fs_visitor *v)
TEST_F(copy_propagation_test, basic)
{
fs_reg vgrf0 = v->vgrf(glsl_float_type());
fs_reg vgrf1 = v->vgrf(glsl_float_type());
fs_reg vgrf2 = v->vgrf(glsl_float_type());
fs_reg vgrf3 = v->vgrf(glsl_float_type());
elk_fs_reg vgrf0 = v->vgrf(glsl_float_type());
elk_fs_reg vgrf1 = v->vgrf(glsl_float_type());
elk_fs_reg vgrf2 = v->vgrf(glsl_float_type());
elk_fs_reg vgrf3 = v->vgrf(glsl_float_type());
bld.MOV(vgrf0, vgrf2);
bld.ADD(vgrf1, vgrf0, vgrf3);
@@ -137,7 +137,7 @@ TEST_F(copy_propagation_test, basic)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -146,13 +146,13 @@ TEST_F(copy_propagation_test, basic)
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
fs_inst *mov = instruction(block0, 0);
EXPECT_EQ(BRW_OPCODE_MOV, mov->opcode);
elk_fs_inst *mov = instruction(block0, 0);
EXPECT_EQ(ELK_OPCODE_MOV, mov->opcode);
EXPECT_TRUE(mov->dst.equals(vgrf0));
EXPECT_TRUE(mov->src[0].equals(vgrf2));
fs_inst *add = instruction(block0, 1);
EXPECT_EQ(BRW_OPCODE_ADD, add->opcode);
elk_fs_inst *add = instruction(block0, 1);
EXPECT_EQ(ELK_OPCODE_ADD, add->opcode);
EXPECT_TRUE(add->dst.equals(vgrf1));
EXPECT_TRUE(add->src[0].equals(vgrf2));
EXPECT_TRUE(add->src[1].equals(vgrf3));
@@ -160,46 +160,46 @@ TEST_F(copy_propagation_test, basic)
TEST_F(copy_propagation_test, maxmax_sat_imm)
{
fs_reg vgrf0 = v->vgrf(glsl_float_type());
fs_reg vgrf1 = v->vgrf(glsl_float_type());
fs_reg vgrf2 = v->vgrf(glsl_float_type());
elk_fs_reg vgrf0 = v->vgrf(glsl_float_type());
elk_fs_reg vgrf1 = v->vgrf(glsl_float_type());
elk_fs_reg vgrf2 = v->vgrf(glsl_float_type());
static const struct {
enum brw_conditional_mod conditional_mod;
enum elk_conditional_mod conditional_mod;
float immediate;
bool expected_result;
} test[] = {
/* conditional mod, imm, expected_result */
{ BRW_CONDITIONAL_GE , 0.1f, false },
{ BRW_CONDITIONAL_L , 0.1f, false },
{ BRW_CONDITIONAL_GE , 0.5f, false },
{ BRW_CONDITIONAL_L , 0.5f, false },
{ BRW_CONDITIONAL_GE , 0.9f, false },
{ BRW_CONDITIONAL_L , 0.9f, false },
{ BRW_CONDITIONAL_GE , -1.5f, false },
{ BRW_CONDITIONAL_L , -1.5f, false },
{ BRW_CONDITIONAL_GE , 1.5f, false },
{ BRW_CONDITIONAL_L , 1.5f, false },
{ ELK_CONDITIONAL_GE , 0.1f, false },
{ ELK_CONDITIONAL_L , 0.1f, false },
{ ELK_CONDITIONAL_GE , 0.5f, false },
{ ELK_CONDITIONAL_L , 0.5f, false },
{ ELK_CONDITIONAL_GE , 0.9f, false },
{ ELK_CONDITIONAL_L , 0.9f, false },
{ ELK_CONDITIONAL_GE , -1.5f, false },
{ ELK_CONDITIONAL_L , -1.5f, false },
{ ELK_CONDITIONAL_GE , 1.5f, false },
{ ELK_CONDITIONAL_L , 1.5f, false },
{ BRW_CONDITIONAL_NONE, 0.5f, false },
{ BRW_CONDITIONAL_Z , 0.5f, false },
{ BRW_CONDITIONAL_NZ , 0.5f, false },
{ BRW_CONDITIONAL_G , 0.5f, false },
{ BRW_CONDITIONAL_LE , 0.5f, false },
{ BRW_CONDITIONAL_R , 0.5f, false },
{ BRW_CONDITIONAL_O , 0.5f, false },
{ BRW_CONDITIONAL_U , 0.5f, false },
{ ELK_CONDITIONAL_NONE, 0.5f, false },
{ ELK_CONDITIONAL_Z , 0.5f, false },
{ ELK_CONDITIONAL_NZ , 0.5f, false },
{ ELK_CONDITIONAL_G , 0.5f, false },
{ ELK_CONDITIONAL_LE , 0.5f, false },
{ ELK_CONDITIONAL_R , 0.5f, false },
{ ELK_CONDITIONAL_O , 0.5f, false },
{ ELK_CONDITIONAL_U , 0.5f, false },
};
for (unsigned i = 0; i < sizeof(test) / sizeof(test[0]); i++) {
fs_inst *mov = set_saturate(true, bld.MOV(vgrf0, vgrf1));
fs_inst *sel = set_condmod(test[i].conditional_mod,
elk_fs_inst *mov = set_saturate(true, bld.MOV(vgrf0, vgrf1));
elk_fs_inst *sel = set_condmod(test[i].conditional_mod,
bld.SEL(vgrf2, vgrf0,
brw_imm_f(test[i].immediate)));
elk_imm_f(test[i].immediate)));
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -208,12 +208,12 @@ TEST_F(copy_propagation_test, maxmax_sat_imm)
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MOV, mov->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, mov->opcode);
EXPECT_TRUE(mov->saturate);
EXPECT_TRUE(mov->dst.equals(vgrf0));
EXPECT_TRUE(mov->src[0].equals(vgrf1));
EXPECT_EQ(BRW_OPCODE_SEL, sel->opcode);
EXPECT_EQ(ELK_OPCODE_SEL, sel->opcode);
EXPECT_EQ(test[i].conditional_mod, sel->conditional_mod);
EXPECT_EQ(test[i].expected_result, sel->saturate);
EXPECT_TRUE(sel->dst.equals(vgrf2));
@@ -222,7 +222,7 @@ TEST_F(copy_propagation_test, maxmax_sat_imm)
} else {
EXPECT_TRUE(sel->src[0].equals(vgrf0));
}
EXPECT_TRUE(sel->src[1].equals(brw_imm_f(test[i].immediate)));
EXPECT_TRUE(sel->src[1].equals(elk_imm_f(test[i].immediate)));
delete v->cfg;
v->cfg = NULL;
src/intel/compiler/elk/elk_test_fs_saturate_propagation.cpp
+169 -169
View File
@@ -33,24 +33,24 @@ protected:
saturate_propagation_test();
~saturate_propagation_test() override;
struct brw_compiler *compiler;
struct brw_compile_params params;
struct elk_compiler *compiler;
struct elk_compile_params params;
struct intel_device_info *devinfo;
void *ctx;
struct brw_wm_prog_data *prog_data;
struct elk_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
fs_visitor *v;
elk_fs_visitor *v;
fs_builder bld;
};
class saturate_propagation_fs_visitor : public fs_visitor
class saturate_propagation_fs_visitor : public elk_fs_visitor
{
public:
saturate_propagation_fs_visitor(struct brw_compiler *compiler,
struct brw_compile_params *params,
struct brw_wm_prog_data *prog_data,
saturate_propagation_fs_visitor(struct elk_compiler *compiler,
struct elk_compile_params *params,
struct elk_wm_prog_data *prog_data,
nir_shader *shader)
: fs_visitor(compiler, params, NULL,
: elk_fs_visitor(compiler, params, NULL,
&prog_data->base, shader, 16, false, false) {}
};
@@ -59,14 +59,14 @@ saturate_propagation_test::saturate_propagation_test()
: bld(NULL, 0)
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
compiler = rzalloc(ctx, struct elk_compiler);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
params = {};
params.mem_ctx = ctx;
prog_data = ralloc(ctx, struct brw_wm_prog_data);
prog_data = ralloc(ctx, struct elk_wm_prog_data);
nir_shader *shader =
nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL);
@@ -88,18 +88,18 @@ saturate_propagation_test::~saturate_propagation_test()
}
static fs_inst *
instruction(bblock_t *block, int num)
static elk_fs_inst *
instruction(elk_bblock_t *block, int num)
{
fs_inst *inst = (fs_inst *)block->start();
elk_fs_inst *inst = (elk_fs_inst *)block->start();
for (int i = 0; i < num; i++) {
inst = (fs_inst *)inst->next;
inst = (elk_fs_inst *)inst->next;
}
return inst;
}
static bool
saturate_propagation(fs_visitor *v)
saturate_propagation(elk_fs_visitor *v)
{
const bool print = false;
@@ -120,10 +120,10 @@ saturate_propagation(fs_visitor *v)
TEST_F(saturate_propagation_test, basic)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.ADD(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
@@ -138,7 +138,7 @@ TEST_F(saturate_propagation_test, basic)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -146,19 +146,19 @@ TEST_F(saturate_propagation_test, basic)
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, other_non_saturated_use)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg dst2 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg dst2 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.ADD(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
bld.ADD(dst2, dst0, src0);
@@ -174,7 +174,7 @@ TEST_F(saturate_propagation_test, other_non_saturated_use)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -182,21 +182,21 @@ TEST_F(saturate_propagation_test, other_non_saturated_use)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->saturate);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 2)->opcode);
}
TEST_F(saturate_propagation_test, predicated_instruction)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.ADD(dst0, src0, src1)
->predicate = BRW_PREDICATE_NORMAL;
->predicate = ELK_PREDICATE_NORMAL;
set_saturate(true, bld.MOV(dst1, dst0));
/* = Before =
@@ -209,7 +209,7 @@ TEST_F(saturate_propagation_test, predicated_instruction)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -217,17 +217,17 @@ TEST_F(saturate_propagation_test, predicated_instruction)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, neg_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
bld.RNDU(dst0, src0);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@@ -242,7 +242,7 @@ TEST_F(saturate_propagation_test, neg_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -250,18 +250,18 @@ TEST_F(saturate_propagation_test, neg_mov_sat)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_RNDU, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_RNDU, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, add_neg_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.ADD(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@@ -277,7 +277,7 @@ TEST_F(saturate_propagation_test, add_neg_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -285,20 +285,20 @@ TEST_F(saturate_propagation_test, add_neg_mov_sat)
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_TRUE(instruction(block0, 0)->src[0].negate);
EXPECT_TRUE(instruction(block0, 0)->src[1].negate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = brw_imm_f(1.0f);
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = elk_imm_f(1.0f);
bld.ADD(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@@ -314,7 +314,7 @@ TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -322,20 +322,20 @@ TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat)
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_TRUE(instruction(block0, 0)->src[0].negate);
EXPECT_EQ(instruction(block0, 0)->src[1].f, -1.0f);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, mul_neg_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.MUL(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@@ -351,7 +351,7 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -359,21 +359,21 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat)
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_TRUE(instruction(block0, 0)->src[0].negate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
EXPECT_FALSE(instruction(block0, 1)->src[0].negate);
}
TEST_F(saturate_propagation_test, mad_neg_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
fs_reg src2 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg src2 = v->vgrf(glsl_float_type());
bld.MAD(dst0, src0, src1, src2);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@@ -389,7 +389,7 @@ TEST_F(saturate_propagation_test, mad_neg_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -397,27 +397,27 @@ TEST_F(saturate_propagation_test, mad_neg_mov_sat)
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_MAD, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_TRUE(instruction(block0, 0)->src[0].negate);
EXPECT_TRUE(instruction(block0, 0)->src[1].negate);
EXPECT_FALSE(instruction(block0, 0)->src[2].negate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
EXPECT_FALSE(instruction(block0, 1)->src[0].negate);
}
TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = brw_imm_f(1.0f);
fs_reg src1 = brw_imm_f(-2.0f);
fs_reg src2 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = elk_imm_f(1.0f);
elk_fs_reg src1 = elk_imm_f(-2.0f);
elk_fs_reg src2 = v->vgrf(glsl_float_type());
/* The builder for MAD tries to be helpful and not put immediates as direct
* sources. We want to test specifically that case.
*/
fs_inst *mad = bld.MAD(dst0, src2, src2, src2);
elk_fs_inst *mad = bld.MAD(dst0, src2, src2, src2);
mad->src[0]= src0;
mad->src[1] = src1;
dst0.negate = true;
@@ -434,7 +434,7 @@ TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -442,22 +442,22 @@ TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat)
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_MAD, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_EQ(instruction(block0, 0)->src[0].f, -1.0f);
EXPECT_EQ(instruction(block0, 0)->src[1].f, 2.0f);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
EXPECT_FALSE(instruction(block0, 1)->src[0].negate);
}
TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg dst2 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg dst2 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.MUL(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
dst0.negate = true;
@@ -474,7 +474,7 @@ TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -482,23 +482,23 @@ TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_FALSE(instruction(block0, 0)->src[1].negate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_TRUE(instruction(block0, 2)->src[0].negate);
EXPECT_TRUE(instruction(block0, 2)->saturate);
}
TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg dst2 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg dst2 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.MUL(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@@ -515,7 +515,7 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -523,23 +523,23 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_FALSE(instruction(block0, 0)->src[1].negate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->src[0].negate);
EXPECT_TRUE(instruction(block0, 1)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_TRUE(instruction(block0, 2)->src[0].negate);
EXPECT_TRUE(instruction(block0, 2)->saturate);
}
TEST_F(saturate_propagation_test, abs_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.ADD(dst0, src0, src1);
dst0.abs = true;
set_saturate(true, bld.MOV(dst1, dst0));
@@ -554,7 +554,7 @@ TEST_F(saturate_propagation_test, abs_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -562,19 +562,19 @@ TEST_F(saturate_propagation_test, abs_mov_sat)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, producer_saturates)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg dst2 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg dst2 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
set_saturate(true, bld.ADD(dst0, src0, src1));
set_saturate(true, bld.MOV(dst1, dst0));
bld.MOV(dst2, dst0);
@@ -592,7 +592,7 @@ TEST_F(saturate_propagation_test, producer_saturates)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -600,19 +600,19 @@ TEST_F(saturate_propagation_test, producer_saturates)
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, intervening_saturating_copy)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg dst2 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg dst2 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.ADD(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
set_saturate(true, bld.MOV(dst2, dst0));
@@ -630,7 +630,7 @@ TEST_F(saturate_propagation_test, intervening_saturating_copy)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -638,23 +638,23 @@ TEST_F(saturate_propagation_test, intervening_saturating_copy)
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_FALSE(instruction(block0, 2)->saturate);
}
TEST_F(saturate_propagation_test, intervening_dest_write)
{
fs_reg dst0 = v->vgrf(glsl_vec4_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
fs_reg src2 = v->vgrf(glsl_vec2_type());
elk_fs_reg dst0 = v->vgrf(glsl_vec4_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg src2 = v->vgrf(glsl_vec2_type());
bld.ADD(offset(dst0, bld, 2), src0, src1);
bld.emit(SHADER_OPCODE_TEX, dst0, src2)
bld.emit(ELK_SHADER_OPCODE_TEX, dst0, src2)
->size_written = 8 * REG_SIZE;
set_saturate(true, bld.MOV(dst1, offset(dst0, bld, 2)));
@@ -669,7 +669,7 @@ TEST_F(saturate_propagation_test, intervening_dest_write)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -677,21 +677,21 @@ TEST_F(saturate_propagation_test, intervening_dest_write)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_TRUE(instruction(block0, 2)->saturate);
}
TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg dst2 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg dst2 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.MUL(dst0, src0, src1);
dst0.negate = true;
set_saturate(true, bld.MOV(dst1, dst0));
@@ -709,7 +709,7 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -717,22 +717,22 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_FALSE(instruction(block0, 0)->src[1].negate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->saturate);
EXPECT_TRUE(instruction(block0, 1)->src[0].negate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_TRUE(instruction(block0, 2)->saturate);
}
TEST_F(saturate_propagation_test, smaller_exec_size_consumer)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.ADD(dst0, src0, src1);
set_saturate(true, bld.group(8, 0).MOV(dst1, dst0));
@@ -746,7 +746,7 @@ TEST_F(saturate_propagation_test, smaller_exec_size_consumer)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -754,18 +754,18 @@ TEST_F(saturate_propagation_test, smaller_exec_size_consumer)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, larger_exec_size_consumer)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.group(8, 0).ADD(dst0, src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
@@ -779,7 +779,7 @@ TEST_F(saturate_propagation_test, larger_exec_size_consumer)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -787,21 +787,21 @@ TEST_F(saturate_propagation_test, larger_exec_size_consumer)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_TRUE(instruction(block0, 1)->saturate);
}
TEST_F(saturate_propagation_test, offset_source_barrier)
{
fs_reg dst0 = v->vgrf(glsl_float_type());
fs_reg dst1 = v->vgrf(glsl_float_type());
fs_reg dst2 = v->vgrf(glsl_float_type());
fs_reg src0 = v->vgrf(glsl_float_type());
fs_reg src1 = v->vgrf(glsl_float_type());
elk_fs_reg dst0 = v->vgrf(glsl_float_type());
elk_fs_reg dst1 = v->vgrf(glsl_float_type());
elk_fs_reg dst2 = v->vgrf(glsl_float_type());
elk_fs_reg src0 = v->vgrf(glsl_float_type());
elk_fs_reg src1 = v->vgrf(glsl_float_type());
bld.group(16, 0).ADD(dst0, src0, src1);
bld.group(1, 0).ADD(dst1, component(dst0, 8), brw_imm_f(1.0f));
bld.group(1, 0).ADD(dst1, component(dst0, 8), elk_imm_f(1.0f));
set_saturate(true, bld.group(16, 0).MOV(dst2, dst0));
/* = Before =
@@ -815,7 +815,7 @@ TEST_F(saturate_propagation_test, offset_source_barrier)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -823,10 +823,10 @@ TEST_F(saturate_propagation_test, offset_source_barrier)
EXPECT_FALSE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 0)->saturate);
EXPECT_FALSE(instruction(block0, 1)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode);
EXPECT_TRUE(instruction(block0, 2)->saturate);
}
src/intel/compiler/elk/elk_test_predicated_break.cpp
+65 -65
View File
@@ -17,16 +17,16 @@ class PredicatedBreakTest : public ::testing::Test {
public:
bool debug;
void *mem_ctx;
brw_compiler compiler;
brw_compile_params params;
elk_compiler compiler;
elk_compile_params params;
intel_device_info devinfo;
struct brw_wm_prog_data prog_data;
struct elk_wm_prog_data prog_data;
struct gl_shader_program *shader_prog;
fs_visitor *shader_a;
fs_visitor *shader_b;
elk_fs_visitor *shader_a;
elk_fs_visitor *shader_b;
bool opt_predicated_break(fs_visitor *s);
bool elk_opt_predicated_break(elk_fs_visitor *s);
};
void
@@ -42,7 +42,7 @@ PredicatedBreakTest::SetUp()
compiler = {};
compiler.devinfo = &devinfo;
brw_init_isa_info(&compiler.isa, &devinfo);
elk_init_isa_info(&compiler.isa, &devinfo);
params = {};
params.mem_ctx = mem_ctx;
@@ -51,10 +51,10 @@ PredicatedBreakTest::SetUp()
nir_shader *nir =
nir_shader_create(mem_ctx, MESA_SHADER_FRAGMENT, NULL, NULL);
shader_a = new fs_visitor(&compiler, &params, NULL,
shader_a = new elk_fs_visitor(&compiler, &params, NULL,
&prog_data.base, nir, 8, false, false);
shader_b = new fs_visitor(&compiler, &params, NULL,
shader_b = new elk_fs_visitor(&compiler, &params, NULL,
&prog_data.base, nir, 8, false, false);
}
@@ -68,7 +68,7 @@ PredicatedBreakTest::TearDown()
}
bool
PredicatedBreakTest::opt_predicated_break(fs_visitor *s)
PredicatedBreakTest::elk_opt_predicated_break(elk_fs_visitor *s)
{
const bool print = getenv("TEST_DEBUG");
@@ -77,7 +77,7 @@ PredicatedBreakTest::opt_predicated_break(fs_visitor *s)
s->cfg->dump();
}
bool ret = ::opt_predicated_break(s);
bool ret = ::elk_opt_predicated_break(s);
if (print) {
fprintf(stderr, "\n= After =\n");
@@ -88,14 +88,14 @@ PredicatedBreakTest::opt_predicated_break(fs_visitor *s)
}
static fs_builder
make_builder(fs_visitor *s)
make_builder(elk_fs_visitor *s)
{
return fs_builder(s, s->dispatch_width).at_end();
}
static testing::AssertionResult
shaders_match(const char *a_expr, const char *b_expr,
fs_visitor *a, fs_visitor *b)
elk_fs_visitor *a, elk_fs_visitor *b)
{
/* Using the CFG string dump for this. Not ideal but it is
* convenient that covers some CFG information, helping to
@@ -140,13 +140,13 @@ TEST_F(PredicatedBreakTest, TopBreakWithoutContinue)
fs_builder a = make_builder(shader_a);
fs_builder b = make_builder(shader_b);
fs_reg r1 = brw_vec8_grf(1, 0);
fs_reg r2 = brw_vec8_grf(2, 0);
fs_reg r3 = brw_vec8_grf(3, 0);
elk_fs_reg r1 = elk_vec8_grf(1, 0);
elk_fs_reg r2 = elk_vec8_grf(2, 0);
elk_fs_reg r3 = elk_vec8_grf(3, 0);
a.DO();
a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
a.IF(BRW_PREDICATE_NORMAL);
a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
a.IF(ELK_PREDICATE_NORMAL);
a.BREAK();
a.ENDIF();
a.ADD(r1, r2, r3);
@@ -155,12 +155,12 @@ TEST_F(PredicatedBreakTest, TopBreakWithoutContinue)
shader_a->calculate_cfg();
/* The IF/ENDIF around the BREAK is expected to be removed. */
bool progress = opt_predicated_break(shader_a);
bool progress = elk_opt_predicated_break(shader_a);
EXPECT_TRUE(progress);
b.DO();
b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
b.BREAK()->predicate = BRW_PREDICATE_NORMAL;
b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
b.BREAK()->predicate = ELK_PREDICATE_NORMAL;
b.ADD(r1, r2, r3);
b.WHILE();
b.NOP();
@@ -174,18 +174,18 @@ TEST_F(PredicatedBreakTest, TopBreakWithContinue)
fs_builder a = make_builder(shader_a);
fs_builder b = make_builder(shader_b);
fs_reg r1 = brw_vec8_grf(1, 0);
fs_reg r2 = brw_vec8_grf(2, 0);
fs_reg r3 = brw_vec8_grf(3, 0);
elk_fs_reg r1 = elk_vec8_grf(1, 0);
elk_fs_reg r2 = elk_vec8_grf(2, 0);
elk_fs_reg r3 = elk_vec8_grf(3, 0);
a.DO();
a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
a.IF(BRW_PREDICATE_NORMAL);
a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
a.IF(ELK_PREDICATE_NORMAL);
a.BREAK();
a.ENDIF();
a.ADD(r1, r2, r3);
a.CMP(r1, r2, r3, BRW_CONDITIONAL_GE);
a.IF(BRW_PREDICATE_NORMAL);
a.CMP(r1, r2, r3, ELK_CONDITIONAL_GE);
a.IF(ELK_PREDICATE_NORMAL);
a.CONTINUE();
a.ENDIF();
a.MUL(r1, r2, r3);
@@ -196,15 +196,15 @@ TEST_F(PredicatedBreakTest, TopBreakWithContinue)
/* The IF/ENDIF around the BREAK and the CONTINUE are expected to be
* removed.
*/
bool progress = opt_predicated_break(shader_a);
bool progress = elk_opt_predicated_break(shader_a);
EXPECT_TRUE(progress);
b.DO();
b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
b.BREAK()->predicate = BRW_PREDICATE_NORMAL;
b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
b.BREAK()->predicate = ELK_PREDICATE_NORMAL;
b.ADD(r1, r2, r3);
b.CMP(r1, r2, r3, BRW_CONDITIONAL_GE);
b.CONTINUE()->predicate = BRW_PREDICATE_NORMAL;
b.CMP(r1, r2, r3, ELK_CONDITIONAL_GE);
b.CONTINUE()->predicate = ELK_PREDICATE_NORMAL;
b.MUL(r1, r2, r3);
b.WHILE();
b.NOP();
@@ -218,14 +218,14 @@ TEST_F(PredicatedBreakTest, DISABLED_BottomBreakWithoutContinue)
fs_builder a = make_builder(shader_a);
fs_builder b = make_builder(shader_b);
fs_reg r1 = brw_vec8_grf(1, 0);
fs_reg r2 = brw_vec8_grf(2, 0);
fs_reg r3 = brw_vec8_grf(3, 0);
elk_fs_reg r1 = elk_vec8_grf(1, 0);
elk_fs_reg r2 = elk_vec8_grf(2, 0);
elk_fs_reg r3 = elk_vec8_grf(3, 0);
a.DO();
a.ADD(r1, r2, r3);
a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
a.IF(BRW_PREDICATE_NORMAL);
a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
a.IF(ELK_PREDICATE_NORMAL);
a.BREAK();
a.ENDIF();
a.WHILE();
@@ -235,14 +235,14 @@ TEST_F(PredicatedBreakTest, DISABLED_BottomBreakWithoutContinue)
/* BREAK is the only way to exit the loop, so expect to remove the
* IF/BREAK/ENDIF and add a predicate to WHILE.
*/
bool progress = opt_predicated_break(shader_a);
bool progress = elk_opt_predicated_break(shader_a);
EXPECT_TRUE(progress);
b.DO();
b.ADD(r1, r2, r3);
b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
auto w = b.WHILE();
w->predicate = BRW_PREDICATE_NORMAL;
w->predicate = ELK_PREDICATE_NORMAL;
w->predicate_inverse = true;
b.NOP();
shader_b->calculate_cfg();
@@ -256,19 +256,19 @@ TEST_F(PredicatedBreakTest, BottomBreakWithContinue)
fs_builder a = make_builder(shader_a);
fs_builder b = make_builder(shader_b);
fs_reg r1 = brw_vec8_grf(1, 0);
fs_reg r2 = brw_vec8_grf(2, 0);
fs_reg r3 = brw_vec8_grf(3, 0);
elk_fs_reg r1 = elk_vec8_grf(1, 0);
elk_fs_reg r2 = elk_vec8_grf(2, 0);
elk_fs_reg r3 = elk_vec8_grf(3, 0);
a.DO();
a.ADD(r1, r2, r3);
a.CMP(r1, r2, r3, BRW_CONDITIONAL_GE);
a.IF(BRW_PREDICATE_NORMAL);
a.CMP(r1, r2, r3, ELK_CONDITIONAL_GE);
a.IF(ELK_PREDICATE_NORMAL);
a.CONTINUE();
a.ENDIF();
a.MUL(r1, r2, r3);
a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
a.IF(BRW_PREDICATE_NORMAL);
a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
a.IF(ELK_PREDICATE_NORMAL);
a.BREAK();
a.ENDIF();
a.WHILE();
@@ -278,16 +278,16 @@ TEST_F(PredicatedBreakTest, BottomBreakWithContinue)
/* With a CONTINUE, the BREAK can't be removed, but still remove the
* IF/ENDIF around both of them.
*/
bool progress = opt_predicated_break(shader_a);
bool progress = elk_opt_predicated_break(shader_a);
EXPECT_TRUE(progress);
b.DO();
b.ADD(r1, r2, r3);
b.CMP(r1, r2, r3, BRW_CONDITIONAL_GE);
b.CONTINUE()->predicate = BRW_PREDICATE_NORMAL;
b.CMP(r1, r2, r3, ELK_CONDITIONAL_GE);
b.CONTINUE()->predicate = ELK_PREDICATE_NORMAL;
b.MUL(r1, r2, r3);
b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
b.BREAK()->predicate = BRW_PREDICATE_NORMAL;
b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
b.BREAK()->predicate = ELK_PREDICATE_NORMAL;
b.WHILE();
b.NOP();
shader_b->calculate_cfg();
@@ -300,19 +300,19 @@ TEST_F(PredicatedBreakTest, TwoBreaks)
fs_builder a = make_builder(shader_a);
fs_builder b = make_builder(shader_b);
fs_reg r1 = brw_vec8_grf(1, 0);
fs_reg r2 = brw_vec8_grf(2, 0);
fs_reg r3 = brw_vec8_grf(3, 0);
elk_fs_reg r1 = elk_vec8_grf(1, 0);
elk_fs_reg r2 = elk_vec8_grf(2, 0);
elk_fs_reg r3 = elk_vec8_grf(3, 0);
a.DO();
a.ADD(r1, r2, r3);
a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
a.IF(BRW_PREDICATE_NORMAL);
a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
a.IF(ELK_PREDICATE_NORMAL);
a.BREAK();
a.ENDIF();
a.MUL(r1, r2, r3);
a.CMP(r1, r2, r3, BRW_CONDITIONAL_GE);
a.IF(BRW_PREDICATE_NORMAL);
a.CMP(r1, r2, r3, ELK_CONDITIONAL_GE);
a.IF(ELK_PREDICATE_NORMAL);
a.BREAK();
a.ENDIF();
a.AND(r1, r2, r3);
@@ -321,16 +321,16 @@ TEST_F(PredicatedBreakTest, TwoBreaks)
shader_a->calculate_cfg();
/* The IF/ENDIF around the breaks are expected to be removed. */
bool progress = opt_predicated_break(shader_a);
bool progress = elk_opt_predicated_break(shader_a);
EXPECT_TRUE(progress);
b.DO();
b.ADD(r1, r2, r3);
b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ);
b.BREAK()->predicate = BRW_PREDICATE_NORMAL;
b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ);
b.BREAK()->predicate = ELK_PREDICATE_NORMAL;
b.MUL(r1, r2, r3);
b.CMP(r1, r2, r3, BRW_CONDITIONAL_GE);
b.BREAK()->predicate = BRW_PREDICATE_NORMAL;
b.CMP(r1, r2, r3, ELK_CONDITIONAL_GE);
b.BREAK()->predicate = ELK_PREDICATE_NORMAL;
b.AND(r1, r2, r3);
b.WHILE();
b.NOP(); /* There's always going to be something after a WHILE. */
src/intel/compiler/elk/elk_test_simd_selection.cpp
+132 -132
View File
@@ -44,7 +44,7 @@ protected:
SIMDSelectionTest()
: mem_ctx(ralloc_context(NULL))
, devinfo(rzalloc(mem_ctx, intel_device_info))
, prog_data(rzalloc(mem_ctx, struct brw_cs_prog_data))
, prog_data(rzalloc(mem_ctx, struct elk_cs_prog_data))
, simd_state{
.devinfo = devinfo,
.prog_data = prog_data,
@@ -59,8 +59,8 @@ protected:
void *mem_ctx;
intel_device_info *devinfo;
struct brw_cs_prog_data *prog_data;
brw_simd_selection_state simd_state;
struct elk_cs_prog_data *prog_data;
elk_simd_selection_state simd_state;
};
class SIMDSelectionCS : public SIMDSelectionTest {
@@ -77,13 +77,13 @@ protected:
TEST_F(SIMDSelectionCS, DefaultsToSIMD16)
{
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), SIMD16);
ASSERT_EQ(elk_simd_select(simd_state), SIMD16);
}
TEST_F(SIMDSelectionCS, TooBigFor16)
@@ -92,12 +92,12 @@ TEST_F(SIMDSelectionCS, TooBigFor16)
prog_data->local_size[1] = 32;
prog_data->local_size[2] = 1;
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, spilled);
ASSERT_EQ(brw_simd_select(simd_state), SIMD32);
ASSERT_EQ(elk_simd_select(simd_state), SIMD32);
}
TEST_F(SIMDSelectionCS, WorkgroupSize1)
@@ -106,12 +106,12 @@ TEST_F(SIMDSelectionCS, WorkgroupSize1)
prog_data->local_size[1] = 1;
prog_data->local_size[2] = 1;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
ASSERT_EQ(elk_simd_select(simd_state), SIMD8);
}
TEST_F(SIMDSelectionCS, WorkgroupSize8)
@@ -120,12 +120,12 @@ TEST_F(SIMDSelectionCS, WorkgroupSize8)
prog_data->local_size[1] = 1;
prog_data->local_size[2] = 1;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
ASSERT_EQ(elk_simd_select(simd_state), SIMD8);
}
TEST_F(SIMDSelectionCS, WorkgroupSizeVariable)
@@ -134,23 +134,23 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariable)
prog_data->local_size[1] = 0;
prog_data->local_size[2] = 0;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD16 | 1u << SIMD32);
const unsigned wg_8_1_1[] = { 8, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
const unsigned wg_16_1_1[] = { 16, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16);
const unsigned wg_32_1_1[] = { 32, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16);
}
TEST_F(SIMDSelectionCS, WorkgroupSizeVariableSpilled)
@@ -159,23 +159,23 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariableSpilled)
prog_data->local_size[1] = 0;
prog_data->local_size[2] = 0;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, spilled);
ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD16 | 1u << SIMD32);
const unsigned wg_8_1_1[] = { 8, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
const unsigned wg_16_1_1[] = { 16, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8);
const unsigned wg_32_1_1[] = { 32, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8);
}
TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8)
@@ -184,22 +184,22 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8)
prog_data->local_size[1] = 0;
prog_data->local_size[2] = 0;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_EQ(prog_data->prog_mask, 1u << SIMD16 | 1u << SIMD32);
const unsigned wg_8_1_1[] = { 8, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD16);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD16);
const unsigned wg_16_1_1[] = { 16, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16);
const unsigned wg_32_1_1[] = { 32, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16);
}
TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD16)
@@ -208,22 +208,22 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD16)
prog_data->local_size[1] = 0;
prog_data->local_size[2] = 0;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD32);
const unsigned wg_8_1_1[] = { 8, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
const unsigned wg_16_1_1[] = { 16, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8);
const unsigned wg_32_1_1[] = { 32, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8);
}
TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8NoSIMD16)
@@ -232,167 +232,167 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8NoSIMD16)
prog_data->local_size[1] = 0;
prog_data->local_size[2] = 0;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_EQ(prog_data->prog_mask, 1u << SIMD32);
const unsigned wg_8_1_1[] = { 8, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD32);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD32);
const unsigned wg_16_1_1[] = { 16, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD32);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD32);
const unsigned wg_32_1_1[] = { 32, 1, 1 };
ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD32);
ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD32);
}
TEST_F(SIMDSelectionCS, SpillAtSIMD8)
{
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, spilled);
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
ASSERT_EQ(elk_simd_select(simd_state), SIMD8);
}
TEST_F(SIMDSelectionCS, SpillAtSIMD16)
{
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, spilled);
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
ASSERT_EQ(elk_simd_select(simd_state), SIMD8);
}
TEST_F(SIMDSelectionCS, EnvironmentVariable32)
{
intel_debug |= DEBUG_DO32;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_EQ(brw_simd_select(simd_state), SIMD32);
ASSERT_EQ(elk_simd_select(simd_state), SIMD32);
}
TEST_F(SIMDSelectionCS, EnvironmentVariable32ButSpills)
{
intel_debug |= DEBUG_DO32;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, spilled);
ASSERT_EQ(brw_simd_select(simd_state), SIMD16);
ASSERT_EQ(elk_simd_select(simd_state), SIMD16);
}
TEST_F(SIMDSelectionCS, Require8)
{
simd_state.required_width = 8;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
ASSERT_EQ(elk_simd_select(simd_state), SIMD8);
}
TEST_F(SIMDSelectionCS, Require8ErrorWhenNotCompile)
{
simd_state.required_width = 8;
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), -1);
ASSERT_EQ(elk_simd_select(simd_state), -1);
}
TEST_F(SIMDSelectionCS, Require16)
{
simd_state.required_width = 16;
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), SIMD16);
ASSERT_EQ(elk_simd_select(simd_state), SIMD16);
}
TEST_F(SIMDSelectionCS, Require16ErrorWhenNotCompile)
{
simd_state.required_width = 16;
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), -1);
ASSERT_EQ(elk_simd_select(simd_state), -1);
}
TEST_F(SIMDSelectionCS, Require32)
{
simd_state.required_width = 32;
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_EQ(brw_simd_select(simd_state), SIMD32);
ASSERT_EQ(elk_simd_select(simd_state), SIMD32);
}
TEST_F(SIMDSelectionCS, Require32ErrorWhenNotCompile)
{
simd_state.required_width = 32;
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
ASSERT_EQ(brw_simd_select(simd_state), -1);
ASSERT_EQ(elk_simd_select(simd_state), -1);
}
TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD8)
{
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
elk_simd_mark_compiled(simd_state, SIMD8, not_spilled);
ASSERT_TRUE(brw_simd_any_compiled(simd_state));
ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD8);
ASSERT_TRUE(elk_simd_any_compiled(simd_state));
ASSERT_EQ(elk_simd_first_compiled(simd_state), SIMD8);
}
TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD16)
{
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
elk_simd_mark_compiled(simd_state, SIMD16, not_spilled);
ASSERT_TRUE(brw_simd_any_compiled(simd_state));
ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD16);
ASSERT_TRUE(elk_simd_any_compiled(simd_state));
ASSERT_EQ(elk_simd_first_compiled(simd_state), SIMD16);
}
TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD32)
{
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16));
ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32));
elk_simd_mark_compiled(simd_state, SIMD32, not_spilled);
ASSERT_TRUE(brw_simd_any_compiled(simd_state));
ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD32);
ASSERT_TRUE(elk_simd_any_compiled(simd_state));
ASSERT_EQ(elk_simd_first_compiled(simd_state), SIMD32);
}
src/intel/compiler/elk/elk_test_vec4_cmod_propagation.cpp
+179 -179
View File
@@ -35,22 +35,22 @@ class cmod_propagation_vec4_test : public ::testing::Test {
virtual void TearDown();
public:
struct brw_compiler *compiler;
struct brw_compile_params params;
struct elk_compiler *compiler;
struct elk_compile_params params;
struct intel_device_info *devinfo;
void *ctx;
struct gl_shader_program *shader_prog;
struct brw_vue_prog_data *prog_data;
struct elk_vue_prog_data *prog_data;
vec4_visitor *v;
};
class cmod_propagation_vec4_visitor : public vec4_visitor
{
public:
cmod_propagation_vec4_visitor(struct brw_compiler *compiler,
struct brw_compile_params *params,
cmod_propagation_vec4_visitor(struct elk_compiler *compiler,
struct elk_compile_params *params,
nir_shader *shader,
struct brw_vue_prog_data *prog_data)
struct elk_vue_prog_data *prog_data)
: vec4_visitor(compiler, params, NULL, prog_data, shader,
false, false)
{
@@ -99,14 +99,14 @@ protected:
void cmod_propagation_vec4_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
compiler = rzalloc(ctx, struct elk_compiler);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
params = {};
params.mem_ctx = ctx;
prog_data = ralloc(ctx, struct brw_vue_prog_data);
prog_data = ralloc(ctx, struct elk_vue_prog_data);
nir_shader *shader =
nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL);
@@ -126,7 +126,7 @@ void cmod_propagation_vec4_test::TearDown()
}
static vec4_instruction *
instruction(bblock_t *block, int num)
instruction(elk_bblock_t *block, int num)
{
vec4_instruction *inst = (vec4_instruction *)block->start();
for (int i = 0; i < num; i++) {
@@ -161,12 +161,12 @@ TEST_F(cmod_propagation_vec4_test, basic)
dst_reg dest = dst_reg(v, glsl_float_type());
src_reg src0 = src_reg(v, glsl_float_type());
src_reg src1 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
bld.ADD(dest, src0, src1);
bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE);
bld.CMP(dest_null, src_reg(dest), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -178,7 +178,7 @@ TEST_F(cmod_propagation_vec4_test, basic)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -187,8 +187,8 @@ TEST_F(cmod_propagation_vec4_test, basic)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(0, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask)
@@ -197,11 +197,11 @@ TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask)
dst_reg dest = dst_reg(v, glsl_float_type());
src_reg src0 = src_reg(v, glsl_float_type());
src_reg src1 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
bld.ADD(dest, src0, src1);
bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE);
bld.CMP(dest_null, src_reg(dest), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -213,7 +213,7 @@ TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -222,10 +222,10 @@ TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, andz_one)
@@ -233,11 +233,11 @@ TEST_F(cmod_propagation_vec4_test, andz_one)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_int_type());
src_reg src0 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg one(brw_imm_d(1));
src_reg zero(elk_imm_f(0.0f));
src_reg one(elk_imm_d(1));
bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L);
set_condmod(BRW_CONDITIONAL_Z,
bld.CMP(retype(dest, ELK_REGISTER_TYPE_F), src0, zero, ELK_CONDITIONAL_L);
set_condmod(ELK_CONDITIONAL_Z,
bld.AND(bld.null_reg_d(), src_reg(dest), one));
/* = Before =
@@ -249,7 +249,7 @@ TEST_F(cmod_propagation_vec4_test, andz_one)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -258,10 +258,10 @@ TEST_F(cmod_propagation_vec4_test, andz_one)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_AND, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, non_cmod_instruction)
@@ -269,9 +269,9 @@ TEST_F(cmod_propagation_vec4_test, non_cmod_instruction)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_uint_type());
src_reg src0 = src_reg(v, glsl_uint_type());
src_reg zero(brw_imm_ud(0u));
src_reg zero(elk_imm_ud(0u));
bld.FBL(dest, src0);
bld.CMP(bld.null_reg_ud(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
bld.CMP(bld.null_reg_ud(), src_reg(dest), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -283,7 +283,7 @@ TEST_F(cmod_propagation_vec4_test, non_cmod_instruction)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -292,9 +292,9 @@ TEST_F(cmod_propagation_vec4_test, non_cmod_instruction)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_FBL, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_FBL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, intervening_flag_write)
@@ -304,10 +304,10 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_write)
src_reg src0 = src_reg(v, glsl_float_type());
src_reg src1 = src_reg(v, glsl_float_type());
src_reg src2 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
bld.ADD(dest, src0, src1);
bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE);
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
bld.CMP(bld.null_reg_f(), src2, zero, ELK_CONDITIONAL_GE);
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -320,7 +320,7 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_write)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -329,11 +329,11 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_write)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, intervening_flag_read)
@@ -344,10 +344,10 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read)
src_reg src0 = src_reg(v, glsl_float_type());
src_reg src1 = src_reg(v, glsl_float_type());
src_reg src2 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
bld.ADD(dest0, src0, src1);
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
bld.CMP(bld.null_reg_f(), src_reg(dest0), zero, BRW_CONDITIONAL_GE);
set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
bld.CMP(bld.null_reg_f(), src_reg(dest0), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -360,7 +360,7 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -369,11 +369,11 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, intervening_dest_write)
@@ -383,11 +383,11 @@ TEST_F(cmod_propagation_vec4_test, intervening_dest_write)
src_reg src0 = src_reg(v, glsl_float_type());
src_reg src1 = src_reg(v, glsl_float_type());
src_reg src2 = src_reg(v, glsl_vec2_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
bld.ADD(offset(dest, 8, 2), src0, src1);
bld.emit(SHADER_OPCODE_TEX, dest, src2)
bld.emit(ELK_SHADER_OPCODE_TEX, dest, src2)
->size_written = 4 * REG_SIZE;
bld.CMP(bld.null_reg_f(), offset(src_reg(dest), 8, 2), zero, BRW_CONDITIONAL_GE);
bld.CMP(bld.null_reg_f(), offset(src_reg(dest), 8, 2), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -400,7 +400,7 @@ TEST_F(cmod_propagation_vec4_test, intervening_dest_write)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -409,12 +409,12 @@ TEST_F(cmod_propagation_vec4_test, intervening_dest_write)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value)
@@ -425,13 +425,13 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value)
src_reg src0 = src_reg(v, glsl_float_type());
src_reg src1 = src_reg(v, glsl_float_type());
src_reg src2 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
set_condmod(BRW_CONDITIONAL_GE, bld.ADD(dest0, src0, src1));
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
bld.CMP(dest_null, src_reg(dest0), zero, BRW_CONDITIONAL_GE);
set_condmod(ELK_CONDITIONAL_GE, bld.ADD(dest0, src0, src1));
set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
bld.CMP(dest_null, src_reg(dest0), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -445,7 +445,7 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -453,10 +453,10 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value)
EXPECT_TRUE(cmod_propagation(v));
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
}
TEST_F(cmod_propagation_vec4_test, negate)
@@ -465,13 +465,13 @@ TEST_F(cmod_propagation_vec4_test, negate)
dst_reg dest = dst_reg(v, glsl_float_type());
src_reg src0 = src_reg(v, glsl_float_type());
src_reg src1 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
bld.ADD(dest, src0, src1);
src_reg tmp_src = src_reg(dest);
tmp_src.negate = true;
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
bld.CMP(dest_null, tmp_src, zero, BRW_CONDITIONAL_GE);
bld.CMP(dest_null, tmp_src, zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -483,7 +483,7 @@ TEST_F(cmod_propagation_vec4_test, negate)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -491,8 +491,8 @@ TEST_F(cmod_propagation_vec4_test, negate)
EXPECT_TRUE(cmod_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(0, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, movnz)
@@ -504,8 +504,8 @@ TEST_F(cmod_propagation_vec4_test, movnz)
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
bld.CMP(dest, src0, src1, BRW_CONDITIONAL_L);
set_condmod(BRW_CONDITIONAL_NZ,
bld.CMP(dest, src0, src1, ELK_CONDITIONAL_L);
set_condmod(ELK_CONDITIONAL_NZ,
bld.MOV(dest_null, src_reg(dest)));
/* = Before =
@@ -518,7 +518,7 @@ TEST_F(cmod_propagation_vec4_test, movnz)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -527,8 +527,8 @@ TEST_F(cmod_propagation_vec4_test, movnz)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(0, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero)
@@ -537,10 +537,10 @@ TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero)
dst_reg dest = dst_reg(v, glsl_int_type());
src_reg src0 = src_reg(v, glsl_int_type());
src_reg src1 = src_reg(v, glsl_int_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
bld.ADD(dest, src0, src1);
bld.CMP(bld.null_reg_f(), retype(src_reg(dest), BRW_REGISTER_TYPE_F), zero,
BRW_CONDITIONAL_GE);
bld.CMP(bld.null_reg_f(), retype(src_reg(dest), ELK_REGISTER_TYPE_F), zero,
ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -552,7 +552,7 @@ TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -561,9 +561,9 @@ TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, andnz_non_one)
@@ -571,11 +571,11 @@ TEST_F(cmod_propagation_vec4_test, andnz_non_one)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_int_type());
src_reg src0 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg nonone(brw_imm_d(38));
src_reg zero(elk_imm_f(0.0f));
src_reg nonone(elk_imm_d(38));
bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L);
set_condmod(BRW_CONDITIONAL_NZ,
bld.CMP(retype(dest, ELK_REGISTER_TYPE_F), src0, zero, ELK_CONDITIONAL_L);
set_condmod(ELK_CONDITIONAL_NZ,
bld.AND(bld.null_reg_d(), src_reg(dest), nonone));
/* = Before =
@@ -587,7 +587,7 @@ TEST_F(cmod_propagation_vec4_test, andnz_non_one)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -596,10 +596,10 @@ TEST_F(cmod_propagation_vec4_test, andnz_non_one)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_AND, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
}
/* Note that basic is using glsl_type:float types, while this one is using
@@ -610,10 +610,10 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4)
dst_reg dest = dst_reg(v, glsl_vec4_type());
src_reg src0 = src_reg(v, glsl_vec4_type());
src_reg src1 = src_reg(v, glsl_vec4_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
bld.MUL(dest, src0, src1);
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_NZ);
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, ELK_CONDITIONAL_NZ);
/* = Before =
* 0: mul dest.xyzw src0.xyzw src1.xyzw
@@ -624,7 +624,7 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -633,8 +633,8 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(0, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask)
@@ -644,11 +644,11 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask)
dest.writemask = WRITEMASK_X;
src_reg src0 = src_reg(v, glsl_vec4_type());
src_reg src1 = src_reg(v, glsl_vec4_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
bld.MUL(dest, src0, src1);
bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_NZ);
bld.CMP(dest_null, src_reg(dest), zero, ELK_CONDITIONAL_NZ);
/* = Before =
* 0: mul dest.x src0 src1
@@ -659,7 +659,7 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -668,10 +668,10 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4)
@@ -682,16 +682,16 @@ TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4)
src_reg src0 = src_reg(v, glsl_vec4_type());
src_reg src1 = src_reg(v, glsl_vec4_type());
src_reg src2 = src_reg(v, glsl_vec4_type());
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
src0.swizzle = src1.swizzle = src2.swizzle = ELK_SWIZZLE_XXXX;
src2.negate = true;
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
src_reg tmp(dest);
tmp.swizzle = BRW_SWIZZLE_XXXX;
tmp.swizzle = ELK_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
bld.MAD(dest, src0, src1, src2);
bld.CMP(dest_null, tmp, zero, BRW_CONDITIONAL_L);
bld.CMP(dest_null, tmp, zero, ELK_CONDITIONAL_L);
/* = Before =
*
@@ -703,7 +703,7 @@ TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -712,8 +712,8 @@ TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(0, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_MAD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4)
@@ -724,15 +724,15 @@ TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4)
src_reg src0 = src_reg(v, glsl_vec4_type());
src_reg src1 = src_reg(v, glsl_vec4_type());
src_reg src2 = src_reg(v, glsl_vec4_type());
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
src0.swizzle = src1.swizzle = src2.swizzle = ELK_SWIZZLE_XXXX;
src2.negate = true;
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
src_reg tmp(dest);
tmp.swizzle = BRW_SWIZZLE_XXXX;
tmp.swizzle = ELK_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_f();
bld.MAD(dest, src0, src1, src2);
bld.CMP(dest_null, tmp, zero, BRW_CONDITIONAL_L);
bld.CMP(dest_null, tmp, zero, ELK_CONDITIONAL_L);
/* = Before =
*
@@ -744,7 +744,7 @@ TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -753,10 +753,10 @@ TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_MAD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4)
@@ -765,16 +765,16 @@ TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4)
dst_reg dest = dst_reg(v, glsl_ivec4_type());
dest.writemask = WRITEMASK_X;
src_reg src0 = src_reg(v, glsl_ivec4_type());
src0.swizzle = BRW_SWIZZLE_XXXX;
src0.swizzle = ELK_SWIZZLE_XXXX;
src0.file = UNIFORM;
src_reg nonone = retype(brw_imm_d(16), BRW_REGISTER_TYPE_D);
src_reg nonone = retype(elk_imm_d(16), ELK_REGISTER_TYPE_D);
src_reg mov_src = src_reg(dest);
mov_src.swizzle = BRW_SWIZZLE_XXXX;
mov_src.swizzle = ELK_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_d();
dest_null.writemask = WRITEMASK_X;
bld.CMP(dest, src0, nonone, BRW_CONDITIONAL_GE);
set_condmod(BRW_CONDITIONAL_NZ,
bld.CMP(dest, src0, nonone, ELK_CONDITIONAL_GE);
set_condmod(ELK_CONDITIONAL_NZ,
bld.MOV(dest_null, mov_src));
/* = Before =
@@ -787,7 +787,7 @@ TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -796,8 +796,8 @@ TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(0, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4)
@@ -806,12 +806,12 @@ TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4)
dst_reg dest = dst_reg(v, glsl_vec4_type());
src_reg src0 = src_reg(v, glsl_vec4_type());
src_reg src1 = src_reg(v, glsl_vec4_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
src_reg cmp_src = src_reg(dest);
cmp_src.swizzle = BRW_SWIZZLE4(0,1,3,2);
cmp_src.swizzle = ELK_SWIZZLE4(0,1,3,2);
bld.MUL(dest, src0, src1);
bld.CMP(bld.null_reg_f(), cmp_src, zero, BRW_CONDITIONAL_NZ);
bld.CMP(bld.null_reg_f(), cmp_src, zero, ELK_CONDITIONAL_NZ);
/* = Before =
* 0: mul dest src0 src1
@@ -822,7 +822,7 @@ TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -831,10 +831,10 @@ TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask)
@@ -846,7 +846,7 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask)
dst_reg dest_null = bld.null_reg_f();
bld.ADD(dest, src0, src1);
vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE);
vec4_instruction *inst = bld.CMP(dest_null, src0, src1, ELK_CONDITIONAL_GE);
inst->src[1].negate = true;
/* = Before =
@@ -859,7 +859,7 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -868,8 +868,8 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(0, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask)
@@ -881,7 +881,7 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask)
dst_reg dest_null = bld.null_reg_f();
bld.ADD(dest, src0, src1);
vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE);
vec4_instruction *inst = bld.CMP(dest_null, src0, src1, ELK_CONDITIONAL_GE);
inst->src[1].negate = true;
/* = Before =
@@ -894,7 +894,7 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -903,10 +903,10 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7)
@@ -918,14 +918,14 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7)
src_reg src1 = src_reg(v, glsl_float_type());
src_reg src2 = src_reg(v, glsl_float_type());
src_reg src3 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
bld.ADD(dest1, src0, src1);
bld.SEL(dest2, src2, src3)
->conditional_mod = BRW_CONDITIONAL_GE;
bld.CMP(dest_null, src_reg(dest1), zero, BRW_CONDITIONAL_GE);
->conditional_mod = ELK_CONDITIONAL_GE;
bld.CMP(dest_null, src_reg(dest1), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -939,7 +939,7 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -948,10 +948,10 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5)
@@ -966,14 +966,14 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5)
src_reg src1 = src_reg(v, glsl_float_type());
src_reg src2 = src_reg(v, glsl_float_type());
src_reg src3 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
bld.ADD(dest1, src0, src1);
bld.SEL(dest2, src2, src3)
->conditional_mod = BRW_CONDITIONAL_GE;
bld.CMP(dest_null, src_reg(dest1), zero, BRW_CONDITIONAL_GE);
->conditional_mod = ELK_CONDITIONAL_GE;
bld.CMP(dest_null, src_reg(dest1), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -991,7 +991,7 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(2, block0->end_ip);
@@ -1000,12 +1000,12 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(2, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
}
TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5)
@@ -1017,13 +1017,13 @@ TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5)
dst_reg dest = dst_reg(v, glsl_float_type());
src_reg src0 = src_reg(v, glsl_float_type());
src_reg src1 = src_reg(v, glsl_float_type());
src_reg zero(brw_imm_f(0.0f));
src_reg zero(elk_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
bld.SEL(dest, src0, src1)
->conditional_mod = BRW_CONDITIONAL_GE;
bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE);
->conditional_mod = ELK_CONDITIONAL_GE;
bld.CMP(dest_null, src_reg(dest), zero, ELK_CONDITIONAL_GE);
/* = Before =
*
@@ -1040,7 +1040,7 @@ TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5)
*/
v->calculate_cfg();
bblock_t *block0 = v->cfg->blocks[0];
elk_bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
@@ -1049,8 +1049,8 @@ TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5)
ASSERT_EQ(0, block0->start_ip);
ASSERT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 0)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 0)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode);
EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
src/intel/compiler/elk/elk_test_vec4_copy_propagation.cpp
+33 -33
View File
@@ -31,22 +31,22 @@ class copy_propagation_vec4_test : public ::testing::Test {
virtual void TearDown();
public:
struct brw_compiler *compiler;
struct brw_compile_params params;
struct elk_compiler *compiler;
struct elk_compile_params params;
struct intel_device_info *devinfo;
void *ctx;
struct gl_shader_program *shader_prog;
struct brw_vue_prog_data *prog_data;
struct elk_vue_prog_data *prog_data;
vec4_visitor *v;
};
class copy_propagation_vec4_visitor : public vec4_visitor
{
public:
copy_propagation_vec4_visitor(struct brw_compiler *compiler,
struct brw_compile_params *params,
copy_propagation_vec4_visitor(struct elk_compiler *compiler,
struct elk_compile_params *params,
nir_shader *shader,
struct brw_vue_prog_data *prog_data)
struct elk_vue_prog_data *prog_data)
: vec4_visitor(compiler, params, NULL, prog_data, shader,
false /* no_spills */, false)
{
@@ -89,14 +89,14 @@ protected:
void copy_propagation_vec4_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
compiler = rzalloc(ctx, struct elk_compiler);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
params = {};
params.mem_ctx = ctx;
prog_data = ralloc(ctx, struct brw_vue_prog_data);
prog_data = ralloc(ctx, struct elk_vue_prog_data);
nir_shader *shader =
nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL);
@@ -143,25 +143,25 @@ TEST_F(copy_propagation_vec4_test, test_swizzle_swizzle)
v->emit(v->ADD(a, src_reg(a), src_reg(a)));
v->emit(v->MOV(b, swizzle(src_reg(a), BRW_SWIZZLE4(BRW_SWIZZLE_Y,
BRW_SWIZZLE_Z,
BRW_SWIZZLE_W,
BRW_SWIZZLE_X))));
v->emit(v->MOV(b, swizzle(src_reg(a), ELK_SWIZZLE4(ELK_SWIZZLE_Y,
ELK_SWIZZLE_Z,
ELK_SWIZZLE_W,
ELK_SWIZZLE_X))));
vec4_instruction *test_mov =
v->MOV(c, swizzle(src_reg(b), BRW_SWIZZLE4(BRW_SWIZZLE_Y,
BRW_SWIZZLE_Z,
BRW_SWIZZLE_W,
BRW_SWIZZLE_X)));
v->MOV(c, swizzle(src_reg(b), ELK_SWIZZLE4(ELK_SWIZZLE_Y,
ELK_SWIZZLE_Z,
ELK_SWIZZLE_W,
ELK_SWIZZLE_X)));
v->emit(test_mov);
copy_propagation(v);
EXPECT_EQ(test_mov->src[0].nr, a.nr);
EXPECT_EQ(test_mov->src[0].swizzle, BRW_SWIZZLE4(BRW_SWIZZLE_Z,
BRW_SWIZZLE_W,
BRW_SWIZZLE_X,
BRW_SWIZZLE_Y));
EXPECT_EQ(test_mov->src[0].swizzle, ELK_SWIZZLE4(ELK_SWIZZLE_Z,
ELK_SWIZZLE_W,
ELK_SWIZZLE_X,
ELK_SWIZZLE_Y));
}
TEST_F(copy_propagation_vec4_test, test_swizzle_writemask)
@@ -170,26 +170,26 @@ TEST_F(copy_propagation_vec4_test, test_swizzle_writemask)
dst_reg b = dst_reg(v, glsl_vec4_type());
dst_reg c = dst_reg(v, glsl_vec4_type());
v->emit(v->MOV(b, swizzle(src_reg(a), BRW_SWIZZLE4(BRW_SWIZZLE_X,
BRW_SWIZZLE_Y,
BRW_SWIZZLE_X,
BRW_SWIZZLE_Z))));
v->emit(v->MOV(b, swizzle(src_reg(a), ELK_SWIZZLE4(ELK_SWIZZLE_X,
ELK_SWIZZLE_Y,
ELK_SWIZZLE_X,
ELK_SWIZZLE_Z))));
v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), brw_imm_f(1.0f)));
v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), elk_imm_f(1.0f)));
vec4_instruction *test_mov =
v->MOV(c, swizzle(src_reg(b), BRW_SWIZZLE4(BRW_SWIZZLE_W,
BRW_SWIZZLE_W,
BRW_SWIZZLE_W,
BRW_SWIZZLE_W)));
v->MOV(c, swizzle(src_reg(b), ELK_SWIZZLE4(ELK_SWIZZLE_W,
ELK_SWIZZLE_W,
ELK_SWIZZLE_W,
ELK_SWIZZLE_W)));
v->emit(test_mov);
copy_propagation(v);
/* should not copy propagate */
EXPECT_EQ(test_mov->src[0].nr, b.nr);
EXPECT_EQ(test_mov->src[0].swizzle, BRW_SWIZZLE4(BRW_SWIZZLE_W,
BRW_SWIZZLE_W,
BRW_SWIZZLE_W,
BRW_SWIZZLE_W));
EXPECT_EQ(test_mov->src[0].swizzle, ELK_SWIZZLE4(ELK_SWIZZLE_W,
ELK_SWIZZLE_W,
ELK_SWIZZLE_W,
ELK_SWIZZLE_W));
}
src/intel/compiler/elk/elk_test_vec4_dead_code_eliminate.cpp
+13 -13
View File
@@ -31,22 +31,22 @@ class dead_code_eliminate_vec4_test : public ::testing::Test {
virtual void TearDown();
public:
struct brw_compiler *compiler;
struct brw_compile_params params;
struct elk_compiler *compiler;
struct elk_compile_params params;
struct intel_device_info *devinfo;
void *ctx;
struct gl_shader_program *shader_prog;
struct brw_vue_prog_data *prog_data;
struct elk_vue_prog_data *prog_data;
vec4_visitor *v;
};
class dead_code_eliminate_vec4_visitor : public vec4_visitor
{
public:
dead_code_eliminate_vec4_visitor(struct brw_compiler *compiler,
struct brw_compile_params *params,
dead_code_eliminate_vec4_visitor(struct elk_compiler *compiler,
struct elk_compile_params *params,
nir_shader *shader,
struct brw_vue_prog_data *prog_data)
struct elk_vue_prog_data *prog_data)
: vec4_visitor(compiler, params, NULL, prog_data, shader,
false /* no_spills */, false)
{
@@ -89,14 +89,14 @@ protected:
void dead_code_eliminate_vec4_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
compiler = rzalloc(ctx, struct elk_compiler);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
params = {};
params.mem_ctx = ctx;
prog_data = ralloc(ctx, struct brw_vue_prog_data);
prog_data = ralloc(ctx, struct elk_vue_prog_data);
nir_shader *shader =
nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL);
@@ -151,21 +151,21 @@ TEST_F(dead_code_eliminate_vec4_test, some_dead_channels_all_flags_used)
* (+f0.x) sel(8) g6<1>UD g3<4>UD g6<4>UD
*/
vec4_instruction *test_cmp =
bld.CMP(dst_reg(r4), r2, r1, BRW_CONDITIONAL_L);
bld.CMP(dst_reg(r4), r2, r1, ELK_CONDITIONAL_L);
test_cmp->src[0].swizzle = BRW_SWIZZLE_WWWW;
test_cmp->src[1].swizzle = BRW_SWIZZLE_XXXX;
test_cmp->src[0].swizzle = ELK_SWIZZLE_WWWW;
test_cmp->src[1].swizzle = ELK_SWIZZLE_XXXX;
vec4_instruction *test_mov =
bld.MOV(dst_reg(r5), r4);
test_mov->dst.writemask = WRITEMASK_X;
test_mov->src[0].swizzle = BRW_SWIZZLE_XXXX;
test_mov->src[0].swizzle = ELK_SWIZZLE_XXXX;
vec4_instruction *test_sel =
bld.SEL(dst_reg(r6), r3, r6);
set_predicate(BRW_PREDICATE_NORMAL, test_sel);
set_predicate(ELK_PREDICATE_NORMAL, test_sel);
/* The scratch write is here just to make r5 and r6 be live so that the
* whole program doesn't get eliminated by DCE.
src/intel/compiler/elk/elk_test_vec4_register_coalesce.cpp
+16 -16
View File
@@ -33,12 +33,12 @@ class register_coalesce_vec4_test : public ::testing::Test {
virtual void TearDown();
public:
struct brw_compiler *compiler;
struct brw_compile_params params;
struct elk_compiler *compiler;
struct elk_compile_params params;
struct intel_device_info *devinfo;
void *ctx;
struct gl_shader_program *shader_prog;
struct brw_vue_prog_data *prog_data;
struct elk_vue_prog_data *prog_data;
vec4_visitor *v;
};
@@ -46,10 +46,10 @@ public:
class register_coalesce_vec4_visitor : public vec4_visitor
{
public:
register_coalesce_vec4_visitor(struct brw_compiler *compiler,
struct brw_compile_params *params,
register_coalesce_vec4_visitor(struct elk_compiler *compiler,
struct elk_compile_params *params,
nir_shader *shader,
struct brw_vue_prog_data *prog_data)
struct elk_vue_prog_data *prog_data)
: vec4_visitor(compiler, params, NULL, prog_data, shader,
false /* no_spills */, false)
{
@@ -92,11 +92,11 @@ protected:
void register_coalesce_vec4_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
compiler = rzalloc(ctx, struct elk_compiler);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
prog_data = ralloc(ctx, struct brw_vue_prog_data);
prog_data = ralloc(ctx, struct elk_vue_prog_data);
params = {};
params.mem_ctx = ctx;
@@ -146,9 +146,9 @@ TEST_F(register_coalesce_vec4_test, test_compute_to_mrf)
dst_reg m0 = dst_reg(MRF, 0);
m0.writemask = WRITEMASK_X;
m0.type = BRW_REGISTER_TYPE_F;
m0.type = ELK_REGISTER_TYPE_F;
vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
vec4_instruction *mul = v->emit(v->MUL(temp, something, elk_imm_f(1.0f)));
v->emit(v->MOV(m0, src_reg(temp)));
register_coalesce(v);
@@ -165,17 +165,17 @@ TEST_F(register_coalesce_vec4_test, test_multiple_use)
dst_reg m0 = dst_reg(MRF, 0);
m0.writemask = WRITEMASK_X;
m0.type = BRW_REGISTER_TYPE_F;
m0.type = ELK_REGISTER_TYPE_F;
dst_reg m1 = dst_reg(MRF, 1);
m1.writemask = WRITEMASK_XYZW;
m1.type = BRW_REGISTER_TYPE_F;
m1.type = ELK_REGISTER_TYPE_F;
src_reg src = src_reg(temp);
vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
src.swizzle = BRW_SWIZZLE_XXXX;
vec4_instruction *mul = v->emit(v->MUL(temp, something, elk_imm_f(1.0f)));
src.swizzle = ELK_SWIZZLE_XXXX;
v->emit(v->MOV(m0, src));
src.swizzle = BRW_SWIZZLE_XYZW;
src.swizzle = ELK_SWIZZLE_XYZW;
v->emit(v->MOV(m1, src));
register_coalesce(v);
@@ -191,7 +191,7 @@ TEST_F(register_coalesce_vec4_test, test_dp4_mrf)
dst_reg m0 = dst_reg(MRF, 0);
m0.writemask = WRITEMASK_Y;
m0.type = BRW_REGISTER_TYPE_F;
m0.type = ELK_REGISTER_TYPE_F;
dst_reg temp = dst_reg(v, glsl_float_type());
src/intel/compiler/elk/elk_test_vf_float_conversions.cpp
+14 -14
View File
@@ -67,7 +67,7 @@ TEST_F(vf_float_conversion_test, test_vf_to_float)
if (vf > 127)
expected = -expected;
EXPECT_EQ(f2u(expected), f2u(brw_vf_to_float(vf)));
EXPECT_EQ(f2u(expected), f2u(elk_vf_to_float(vf)));
}
}
@@ -78,7 +78,7 @@ TEST_F(vf_float_conversion_test, test_float_to_vf)
if (vf > 127)
f = -f;
EXPECT_EQ(vf, brw_float_to_vf(f));
EXPECT_EQ(vf, elk_float_to_vf(f));
}
}
@@ -87,24 +87,24 @@ TEST_F(vf_float_conversion_test, test_special_case_0)
/* ±0.0f are special cased to the VFs that would otherwise correspond
* to ±0.125f. Make sure we can't convert these values to VF.
*/
EXPECT_EQ(brw_float_to_vf(+0.125f), -1);
EXPECT_EQ(brw_float_to_vf(-0.125f), -1);
EXPECT_EQ(elk_float_to_vf(+0.125f), -1);
EXPECT_EQ(elk_float_to_vf(-0.125f), -1);
EXPECT_EQ(f2u(brw_vf_to_float(brw_float_to_vf(+0.0f))), f2u(+0.0f));
EXPECT_EQ(f2u(brw_vf_to_float(brw_float_to_vf(-0.0f))), f2u(-0.0f));
EXPECT_EQ(f2u(elk_vf_to_float(elk_float_to_vf(+0.0f))), f2u(+0.0f));
EXPECT_EQ(f2u(elk_vf_to_float(elk_float_to_vf(-0.0f))), f2u(-0.0f));
}
TEST_F(vf_float_conversion_test, test_nonrepresentable_float_input)
{
EXPECT_EQ(brw_float_to_vf(+32.0f), -1);
EXPECT_EQ(brw_float_to_vf(-32.0f), -1);
EXPECT_EQ(elk_float_to_vf(+32.0f), -1);
EXPECT_EQ(elk_float_to_vf(-32.0f), -1);
EXPECT_EQ(brw_float_to_vf(+16.5f), -1);
EXPECT_EQ(brw_float_to_vf(-16.5f), -1);
EXPECT_EQ(elk_float_to_vf(+16.5f), -1);
EXPECT_EQ(elk_float_to_vf(-16.5f), -1);
EXPECT_EQ(brw_float_to_vf(+8.25f), -1);
EXPECT_EQ(brw_float_to_vf(-8.25f), -1);
EXPECT_EQ(elk_float_to_vf(+8.25f), -1);
EXPECT_EQ(elk_float_to_vf(-8.25f), -1);
EXPECT_EQ(brw_float_to_vf(+4.125f), -1);
EXPECT_EQ(brw_float_to_vf(-4.125f), -1);
EXPECT_EQ(elk_float_to_vf(+4.125f), -1);
EXPECT_EQ(elk_float_to_vf(-4.125f), -1);
}
src/intel/compiler/elk/elk_vec4.cpp
+328 -328
View File
File diff suppressed because it is too large Load Diff
src/intel/compiler/elk/elk_vec4.h
+40 -40
View File
@@ -42,11 +42,11 @@ extern "C" {
#endif
const unsigned *
brw_vec4_generate_assembly(const struct brw_compiler *compiler,
const struct brw_compile_params *params,
elk_vec4_generate_assembly(const struct elk_compiler *compiler,
const struct elk_compile_params *params,
const nir_shader *nir,
struct brw_vue_prog_data *prog_data,
const struct cfg_t *cfg,
struct elk_vue_prog_data *prog_data,
const struct elk_cfg_t *cfg,
const elk::performance &perf,
bool debug_enabled);
@@ -60,39 +60,39 @@ namespace elk {
* Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
* fixed-function) into VS IR.
*/
class vec4_visitor : public backend_shader
class vec4_visitor : public elk_backend_shader
{
public:
vec4_visitor(const struct brw_compiler *compiler,
const struct brw_compile_params *params,
const struct brw_sampler_prog_key_data *key,
struct brw_vue_prog_data *prog_data,
vec4_visitor(const struct elk_compiler *compiler,
const struct elk_compile_params *params,
const struct elk_sampler_prog_key_data *key,
struct elk_vue_prog_data *prog_data,
const nir_shader *shader,
bool no_spills,
bool debug_enabled);
dst_reg dst_null_f()
{
return dst_reg(brw_null_reg());
return dst_reg(elk_null_reg());
}
dst_reg dst_null_df()
{
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF));
return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_DF));
}
dst_reg dst_null_d()
{
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_D));
}
dst_reg dst_null_ud()
{
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD));
}
const struct brw_sampler_prog_key_data * const key_tex;
struct brw_vue_prog_data * const prog_data;
const struct elk_sampler_prog_key_data * const key_tex;
struct elk_vue_prog_data * const prog_data;
char *fail_msg;
bool failed;
@@ -107,8 +107,8 @@ public:
unsigned ubo_push_start[4];
unsigned push_length;
unsigned int max_grf;
brw_analysis<elk::vec4_live_variables, backend_shader> live_analysis;
brw_analysis<elk::performance, vec4_visitor> performance_analysis;
elk_analysis<elk::vec4_live_variables, elk_backend_shader> live_analysis;
elk_analysis<elk::performance, vec4_visitor> performance_analysis;
/* Regs for vertex results. Generated at ir_variable visiting time
* for the ir->location's used.
@@ -138,7 +138,7 @@ public:
bool dead_code_eliminate();
bool opt_cmod_propagation();
bool opt_copy_propagation(bool do_constant_prop = true);
bool opt_cse_local(bblock_t *block, const vec4_live_variables &live);
bool opt_cse_local(elk_bblock_t *block, const vec4_live_variables &live);
bool opt_cse();
bool opt_algebraic();
bool opt_register_coalesce();
@@ -153,22 +153,22 @@ public:
bool lower_simd_width();
bool scalarize_df();
bool lower_64bit_mad_to_mul_add();
void apply_logical_swizzle(struct brw_reg *hw_reg,
void apply_logical_swizzle(struct elk_reg *hw_reg,
vec4_instruction *inst, int arg);
vec4_instruction *emit(vec4_instruction *inst);
vec4_instruction *emit(enum opcode opcode);
vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
vec4_instruction *emit(enum elk_opcode opcode);
vec4_instruction *emit(enum elk_opcode opcode, const dst_reg &dst);
vec4_instruction *emit(enum elk_opcode opcode, const dst_reg &dst,
const src_reg &src0);
vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
vec4_instruction *emit(enum elk_opcode opcode, const dst_reg &dst,
const src_reg &src0, const src_reg &src1);
vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
vec4_instruction *emit(enum elk_opcode opcode, const dst_reg &dst,
const src_reg &src0, const src_reg &src1,
const src_reg &src2);
vec4_instruction *emit_before(bblock_t *block,
vec4_instruction *emit_before(elk_bblock_t *block,
vec4_instruction *inst,
vec4_instruction *new_inst);
@@ -197,10 +197,10 @@ public:
EMIT2(SHR)
EMIT2(ASR)
vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
enum brw_conditional_mod condition);
enum elk_conditional_mod condition);
vec4_instruction *IF(src_reg src0, src_reg src1,
enum brw_conditional_mod condition);
vec4_instruction *IF(enum brw_predicate predicate);
enum elk_conditional_mod condition);
vec4_instruction *IF(enum elk_predicate predicate);
EMIT1(SCRATCH_READ)
EMIT2(SCRATCH_WRITE)
EMIT3(LRP)
@@ -221,7 +221,7 @@ public:
#undef EMIT2
#undef EMIT3
vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
vec4_instruction *emit_minmax(enum elk_conditional_mod conditionalmod, dst_reg dst,
src_reg src0, src_reg src1);
/**
@@ -235,7 +235,7 @@ public:
src_reg fix_3src_operand(const src_reg &src);
vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
vec4_instruction *emit_math(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0,
const src_reg &src1 = src_reg());
src_reg fix_math_operand(const src_reg &src);
@@ -255,20 +255,20 @@ public:
vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying, int comp);
virtual void emit_urb_slot(dst_reg reg, int varying);
src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
src_reg get_scratch_offset(elk_bblock_t *block, vec4_instruction *inst,
src_reg *reladdr, int reg_offset);
void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
void emit_scratch_read(elk_bblock_t *block, vec4_instruction *inst,
dst_reg dst,
src_reg orig_src,
int base_offset);
void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
void emit_scratch_write(elk_bblock_t *block, vec4_instruction *inst,
int base_offset);
void emit_pull_constant_load_reg(dst_reg dst,
src_reg surf_index,
src_reg offset,
bblock_t *before_block,
elk_bblock_t *before_block,
vec4_instruction *before_inst);
src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
src_reg emit_resolve_reladdr(int scratch_loc[], elk_bblock_t *block,
vec4_instruction *inst, src_reg src);
void resolve_ud_negate(src_reg *reg);
@@ -279,9 +279,9 @@ public:
src_reg get_timestamp();
virtual void dump_instruction_to_file(const backend_instruction *inst, FILE *file) const;
virtual void dump_instruction_to_file(const elk_backend_instruction *inst, FILE *file) const;
bool optimize_predicate(nir_alu_instr *instr, enum brw_predicate *predicate);
bool optimize_predicate(nir_alu_instr *instr, enum elk_predicate *predicate);
void emit_conversion_from_double(dst_reg dst, src_reg src);
void emit_conversion_to_double(dst_reg dst, src_reg src);
@@ -289,7 +289,7 @@ public:
vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src,
bool for_write,
bool for_scratch = false,
bblock_t *block = NULL,
elk_bblock_t *block = NULL,
vec4_instruction *ref = NULL);
virtual void emit_nir_code();
@@ -309,10 +309,10 @@ public:
virtual void nir_emit_undef(nir_undef_instr *instr);
virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr);
dst_reg get_nir_def(const nir_def &def, enum brw_reg_type type);
dst_reg get_nir_def(const nir_def &def, enum elk_reg_type type);
dst_reg get_nir_def(const nir_def &def, nir_alu_type type);
dst_reg get_nir_def(const nir_def &def);
src_reg get_nir_src(const nir_src &src, enum brw_reg_type type,
src_reg get_nir_src(const nir_src &src, enum elk_reg_type type,
unsigned num_components = 4);
src_reg get_nir_src(const nir_src &src, nir_alu_type type,
unsigned num_components = 4);

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