Files
mesa/src/intel/compiler/elk/elk_fs_validate.cpp
T
Caio Oliveira 6648e0ebd3 intel/elk: Rename symbols
Either replace the BRW prefix with ELK or add an extra ELK prefix.  Used
the following sed script to perform the renames in this patch:

```
    # Simple prefix changes.
    s/\<BRW_/ELK_/g
    s/\<brw_/elk_/g
    s/nir_to_brw/nir_to_elk/g
    s/\<as_brw_reg\>/as_elk_reg/g
    s/\<_brw_/_elk_/g

    # Add prefix to various symbols.
    #
    # Initially I've considered using C++ namespaces here, but in various
    # cases the structs or functions had to be also visible from C code.
    # So added explicit prefix instead.
    s/\<backend_instruction/elk_\0/g
    s/\<backend_reg/elk_\0/g
    s/\<backend_shader/elk_\0/g
    s/\<bblock_t\>/elk_\0/g
    s/\<bblock_link\>/elk_\0/g
    s/\<cfg_t\>/elk_\0/g
    s/\<fs_visitor\>/elk_\0/g
    s/\<fs_reg\>/elk_\0/g
    s/\<fs_instruction_scheduler\>/elk_\0/g
    s/\<vec4_instruction_scheduler\>/elk_\0/g
    s/\<instruction_scheduler\>/elk_\0/g
    s/\<schedule_node\>/elk_\0/g
    s/\<schedule_node_child\>/elk_\0/g
    s/\<\([a-z]*_\)\?thread_payload\>/elk_\1thread_payload/g
    s/\<fs_generator\>/elk_\0/g
    s/\<fs_inst\>/elk_\0/g
    s/\<fs_reg_alloc\>/elk_\0/g
    s/\<disasm_info\>/elk_\0/g
    s/\<gfx._math\>/elk_\0/g
    s/\<gfx7_block_read_scratch\>/elk_\0/g
    s/\<gfx6_IF\>/elk_\0/g
    s/\<gfx9_fb_READ\>/elk_\0/g
    s/\<gfx6_resolve_implied_move\>/elk_\0/g

    # Opcodes.
    s/\<opcode op\>/elk_\0/g
    s/\<opcode mov_op\>/elk_\0/g
    s/\<opcode opcode\>/elk_\0/g
    s/enum opcode\>/enum elk_opcode/g
    s/static opcode\>/static elk_opcode/g
    s/\<opcode elk_op/elk_opcode elk_op/g
    s/struct opcode_desc/struct elk_opcode_desc/g
    s/NUM_BRW_OPCODES/NUM_ELK_OPCODES/g
    s/\<.._OPCODE_/ELK_\0/g
    s/\<T.._OPCODE_/ELK_\0/g
    s/\<VEC4_OPCODE_/ELK_\0/g
    s/\<VEC4_...\?_OPCODE_/ELK_\0/g
    s/\<SHADER_OPCODE_/ELK_\0/g

    # Remaining specific cases.
    s/\<wm_prog_data_barycentric_modes\>/elk_\0/g
    s/\<encode_slm_size\>/elk_\0/g
    s/\<intel_calculate_slm_size\>/elk_\0/g
    s/\<gfx6_gather_sampler_wa\>/elk_\0/g
    s/\<is_3src\>/elk_\0/g
    s/\<WA_/ELK_\0/g
    s/\<conditional_modifier\>/elk_\0/g
    s/\<pred_ctrl_align16\>/elk_\0/g
    s/\<shuffle_from_32bit_read\>/elk_\0/g
    s/\<shuffle_src_to_dst\>/elk_\0/g
    s/\<setup_imm_..\?\>/elk_\0/g

    s/\<opt_predicated_break\>/elk_\0/g
    s/\<has_bank_conflict\>/elk_\0/g
    s/\<dead_control_flow_eliminate\>/elk_\0/g

    s/\<disasm_new_inst_group\>/elk_\0/g
    s/\<disasm_initialize\>/elk_\0/g
    s/\<dump_assembly\>/elk_\0/g
    s/\<disasm_insert_error\>/elk_\0/g
    s/\<disasm_annotate\>/elk_\0/g

    s/\<enum lsc_opcode\>/enum elk_lsc_opcode/g
    s/\<lsc_opcode_/elk_lsc_opcode_/g
    s/\<lsc_aop_[a-z_]\+\>/elk_\0/g

    s/\<type_size_vec4\>/elk_\0/g
    s/\<type_size_dvec4\>/elk_\0/g
    s/\<type_size_xvec4\>/elk_\0/g
    s/\<type_size_[a-z4]\+_bytes\>/elk_\0/g

    s/\<gfx12_systolic_depth\>/elk_\0/g
```

Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:31 +00:00

200 lines
8.7 KiB
C++

/*
* Copyright © 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
/** @file elk_fs_validate.cpp
*
* Implements a pass that validates various invariants of the IR. The current
* pass only validates that GRF's uses are sane. More can be added later.
*/
#include "elk_fs.h"
#include "elk_cfg.h"
#define fsv_assert(assertion) \
{ \
if (!(assertion)) { \
fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \
_mesa_shader_stage_to_abbrev(stage)); \
dump_instruction(inst, stderr); \
fprintf(stderr, "%s:%d: '%s' failed\n", __FILE__, __LINE__, #assertion); \
abort(); \
} \
}
#define fsv_assert_eq(first, second) \
{ \
unsigned f = (first); \
unsigned s = (second); \
if (f != s) { \
fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \
_mesa_shader_stage_to_abbrev(stage)); \
dump_instruction(inst, stderr); \
fprintf(stderr, "%s:%d: A == B failed\n", __FILE__, __LINE__); \
fprintf(stderr, " A = %s = %u\n", #first, f); \
fprintf(stderr, " B = %s = %u\n", #second, s); \
abort(); \
} \
}
#define fsv_assert_ne(first, second) \
{ \
unsigned f = (first); \
unsigned s = (second); \
if (f == s) { \
fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \
_mesa_shader_stage_to_abbrev(stage)); \
dump_instruction(inst, stderr); \
fprintf(stderr, "%s:%d: A != B failed\n", __FILE__, __LINE__); \
fprintf(stderr, " A = %s = %u\n", #first, f); \
fprintf(stderr, " B = %s = %u\n", #second, s); \
abort(); \
} \
}
#define fsv_assert_lte(first, second) \
{ \
unsigned f = (first); \
unsigned s = (second); \
if (f > s) { \
fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \
_mesa_shader_stage_to_abbrev(stage)); \
dump_instruction(inst, stderr); \
fprintf(stderr, "%s:%d: A <= B failed\n", __FILE__, __LINE__); \
fprintf(stderr, " A = %s = %u\n", #first, f); \
fprintf(stderr, " B = %s = %u\n", #second, s); \
abort(); \
} \
}
#ifndef NDEBUG
void
elk_fs_visitor::validate()
{
cfg->validate(_mesa_shader_stage_to_abbrev(stage));
foreach_block_and_inst (block, elk_fs_inst, inst, cfg) {
switch (inst->opcode) {
case ELK_SHADER_OPCODE_SEND:
fsv_assert(is_uniform(inst->src[0]) && is_uniform(inst->src[1]));
break;
case ELK_OPCODE_MOV:
fsv_assert(inst->sources == 1);
break;
default:
break;
}
if (inst->elk_is_3src(compiler)) {
const unsigned integer_sources =
elk_reg_type_is_integer(inst->src[0].type) +
elk_reg_type_is_integer(inst->src[1].type) +
elk_reg_type_is_integer(inst->src[2].type);
const unsigned float_sources =
elk_reg_type_is_floating_point(inst->src[0].type) +
elk_reg_type_is_floating_point(inst->src[1].type) +
elk_reg_type_is_floating_point(inst->src[2].type);
fsv_assert((integer_sources == 3 && float_sources == 0) ||
(integer_sources == 0 && float_sources == 3));
if (devinfo->ver >= 10) {
for (unsigned i = 0; i < 3; i++) {
if (inst->src[i].file == ELK_IMMEDIATE_VALUE)
continue;
switch (inst->src[i].vstride) {
case ELK_VERTICAL_STRIDE_0:
case ELK_VERTICAL_STRIDE_4:
case ELK_VERTICAL_STRIDE_8:
case ELK_VERTICAL_STRIDE_16:
break;
case ELK_VERTICAL_STRIDE_1:
fsv_assert_lte(12, devinfo->ver);
break;
case ELK_VERTICAL_STRIDE_2:
fsv_assert_lte(devinfo->ver, 11);
break;
default:
fsv_assert(!"invalid vstride");
break;
}
}
} else if (grf_used != 0) {
/* Only perform the pre-Gfx10 checks after register allocation has
* occured.
*
* Many passes (e.g., constant copy propagation) will genenerate
* invalid 3-source instructions with the expectation that later
* passes (e.g., combine constants) will fix them.
*/
for (unsigned i = 0; i < 3; i++) {
fsv_assert_ne(inst->src[i].file, ELK_IMMEDIATE_VALUE);
/* A stride of 1 (the usual case) or 0, with a special
* "repctrl" bit, is allowed. The repctrl bit doesn't work for
* 64-bit datatypes, so if the source type is 64-bit then only
* a stride of 1 is allowed. From the Broadwell PRM, Volume 7
* "3D Media GPGPU", page 944:
*
* This is applicable to 32b datatypes and 16b datatype. 64b
* datatypes cannot use the replicate control.
*/
fsv_assert_lte(inst->src[i].vstride, 1);
if (type_sz(inst->src[i].type) > 4)
fsv_assert_eq(inst->src[i].vstride, 1);
}
}
}
if (inst->dst.file == VGRF) {
fsv_assert_lte(inst->dst.offset / REG_SIZE + regs_written(inst),
alloc.sizes[inst->dst.nr]);
}
for (unsigned i = 0; i < inst->sources; i++) {
if (inst->src[i].file == VGRF) {
fsv_assert_lte(inst->src[i].offset / REG_SIZE + regs_read(inst, i),
alloc.sizes[inst->src[i].nr]);
}
}
/* Accumulator Registers, bspec 47251:
*
* "When destination is accumulator with offset 0, destination
* horizontal stride must be 1."
*/
if (intel_needs_workaround(devinfo, 14014617373) &&
inst->dst.is_accumulator() &&
inst->dst.offset == 0) {
fsv_assert_eq(inst->dst.stride, 1);
}
}
}
#endif