diff --git a/src/intel/compiler/elk/elk_asm.h b/src/intel/compiler/elk/elk_asm.h index 6a10671cc00..47b9d309dbd 100644 --- a/src/intel/compiler/elk/elk_asm.h +++ b/src/intel/compiler/elk/elk_asm.h @@ -44,7 +44,7 @@ int yyparse(void); int yylex(void); char *lex_text(void); -extern struct brw_codegen *p; +extern struct elk_codegen *p; extern int errors; extern char *input_filename; diff --git a/src/intel/compiler/elk/elk_asm_tool.c b/src/intel/compiler/elk/elk_asm_tool.c index 1ffab038111..61be3cfba4f 100644 --- a/src/intel/compiler/elk/elk_asm_tool.c +++ b/src/intel/compiler/elk/elk_asm_tool.c @@ -34,7 +34,7 @@ enum opt_output_type { }; extern FILE *yyin; -struct brw_codegen *p; +struct elk_codegen *p; static enum opt_output_type output_type = OPT_OUTPUT_BIN; char *input_filename = NULL; int errors; @@ -61,7 +61,7 @@ print_help(const char *progname, FILE *file) } static uint32_t -get_dword(const brw_inst *inst, int idx) +get_dword(const elk_inst *inst, int idx) { uint32_t dword; memcpy(&dword, (char *)inst + 4 * idx, sizeof(dword)); @@ -69,7 +69,7 @@ get_dword(const brw_inst *inst, int idx) } static void -print_instruction(FILE *output, bool compact, const brw_inst *instruction) +print_instruction(FILE *output, bool compact, const elk_inst *instruction) { int byte_limit; @@ -133,34 +133,34 @@ i965_postprocess_labels() struct target_label *tlabel; struct instr_label *ilabel, *s; - const unsigned to_bytes_scale = brw_jump_scale(p->devinfo); + const unsigned to_bytes_scale = elk_jump_scale(p->devinfo); LIST_FOR_EACH_ENTRY(tlabel, &target_labels, link) { LIST_FOR_EACH_ENTRY_SAFE(ilabel, s, &instr_labels, link) { if (!strcmp(tlabel->name, ilabel->name)) { - brw_inst *inst = store + ilabel->offset; + elk_inst *inst = store + ilabel->offset; - int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(brw_inst); + int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(elk_inst); relative_offset *= to_bytes_scale; - unsigned opcode = brw_inst_opcode(p->isa, inst); + unsigned opcode = elk_inst_opcode(p->isa, inst); if (ilabel->type == INSTR_LABEL_JIP) { switch (opcode) { - case BRW_OPCODE_IF: - case BRW_OPCODE_ELSE: - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_WHILE: + case ELK_OPCODE_IF: + case ELK_OPCODE_ELSE: + case ELK_OPCODE_ENDIF: + case ELK_OPCODE_WHILE: if (p->devinfo->ver >= 7) { - brw_inst_set_jip(p->devinfo, inst, relative_offset); + elk_inst_set_jip(p->devinfo, inst, relative_offset); } else if (p->devinfo->ver == 6) { - brw_inst_set_gfx6_jump_count(p->devinfo, inst, relative_offset); + elk_inst_set_gfx6_jump_count(p->devinfo, inst, relative_offset); } break; - case BRW_OPCODE_BREAK: - case BRW_OPCODE_HALT: - case BRW_OPCODE_CONTINUE: - brw_inst_set_jip(p->devinfo, inst, relative_offset); + case ELK_OPCODE_BREAK: + case ELK_OPCODE_HALT: + case ELK_OPCODE_CONTINUE: + elk_inst_set_jip(p->devinfo, inst, relative_offset); break; default: fprintf(stderr, "Unknown opcode %d with JIP label\n", opcode); @@ -168,24 +168,24 @@ i965_postprocess_labels() } } else { switch (opcode) { - case BRW_OPCODE_IF: - case BRW_OPCODE_ELSE: + case ELK_OPCODE_IF: + case ELK_OPCODE_ELSE: if (p->devinfo->ver > 7) { - brw_inst_set_uip(p->devinfo, inst, relative_offset); + elk_inst_set_uip(p->devinfo, inst, relative_offset); } else if (p->devinfo->ver == 7) { - brw_inst_set_uip(p->devinfo, inst, relative_offset); + elk_inst_set_uip(p->devinfo, inst, relative_offset); } else if (p->devinfo->ver == 6) { // Nothing } break; - case BRW_OPCODE_WHILE: - case BRW_OPCODE_ENDIF: + case ELK_OPCODE_WHILE: + case ELK_OPCODE_ENDIF: fprintf(stderr, "WHILE/ENDIF cannot have UIP offset\n"); return false; - case BRW_OPCODE_BREAK: - case BRW_OPCODE_CONTINUE: - case BRW_OPCODE_HALT: - brw_inst_set_uip(p->devinfo, inst, relative_offset); + case ELK_OPCODE_BREAK: + case ELK_OPCODE_CONTINUE: + case ELK_OPCODE_HALT: + elk_inst_set_uip(p->devinfo, inst, relative_offset); break; default: fprintf(stderr, "Unknown opcode %d with UIP label\n", opcode); @@ -215,7 +215,7 @@ int main(int argc, char **argv) uint64_t pci_id = 0; int offset = 0, err; int start_offset = 0; - struct disasm_info *disasm_info; + struct elk_disasm_info *elk_disasm_info; struct intel_device_info *devinfo = NULL; int result = EXIT_FAILURE; list_inithead(&instr_labels); @@ -310,11 +310,11 @@ int main(int argc, char **argv) goto end; } - struct brw_isa_info isa; - brw_init_isa_info(&isa, devinfo); + struct elk_isa_info isa; + elk_init_isa_info(&isa, devinfo); - p = rzalloc(NULL, struct brw_codegen); - brw_init_codegen(&isa, p, p); + p = rzalloc(NULL, struct elk_codegen); + elk_init_codegen(&isa, p, p); p->automatic_exec_sizes = false; err = yyparse(); @@ -326,28 +326,28 @@ int main(int argc, char **argv) store = p->store; - disasm_info = disasm_initialize(p->isa, NULL); - if (!disasm_info) { - fprintf(stderr, "Unable to initialize disasm_info struct instance\n"); + elk_disasm_info = elk_disasm_initialize(p->isa, NULL); + if (!elk_disasm_info) { + fprintf(stderr, "Unable to initialize elk_disasm_info struct instance\n"); goto end; } if (output_type == OPT_OUTPUT_C_LITERAL) fprintf(output, "{\n"); - brw_validate_instructions(p->isa, p->store, 0, - p->next_insn_offset, disasm_info); + elk_validate_instructions(p->isa, p->store, 0, + p->next_insn_offset, elk_disasm_info); const int nr_insn = (p->next_insn_offset - start_offset) / 16; if (compact) - brw_compact_instructions(p, start_offset, disasm_info); + elk_compact_instructions(p, start_offset, elk_disasm_info); for (int i = 0; i < nr_insn; i++) { - const brw_inst *insn = store + offset; + const elk_inst *insn = store + offset; bool compacted = false; - if (compact && brw_inst_cmpt_control(p->devinfo, insn)) { + if (compact && elk_inst_cmpt_control(p->devinfo, insn)) { offset += 8; compacted = true; } else { @@ -357,7 +357,7 @@ int main(int argc, char **argv) print_instruction(output, compacted, insn); } - ralloc_free(disasm_info); + ralloc_free(elk_disasm_info); if (output_type == OPT_OUTPUT_C_LITERAL) fprintf(output, "}"); diff --git a/src/intel/compiler/elk/elk_cfg.cpp b/src/intel/compiler/elk/elk_cfg.cpp index c1a25983c32..44c04f96124 100644 --- a/src/intel/compiler/elk/elk_cfg.cpp +++ b/src/intel/compiler/elk/elk_cfg.cpp @@ -37,25 +37,25 @@ using namespace elk; -static bblock_t * +static elk_bblock_t * pop_stack(exec_list *list) { - bblock_link *link = (bblock_link *)list->get_tail(); - bblock_t *block = link->block; + elk_bblock_link *link = (elk_bblock_link *)list->get_tail(); + elk_bblock_t *block = link->block; link->link.remove(); return block; } static exec_node * -link(void *mem_ctx, bblock_t *block, enum bblock_link_kind kind) +link(void *mem_ctx, elk_bblock_t *block, enum bblock_link_kind kind) { - bblock_link *l = new(mem_ctx) bblock_link(block, kind); + elk_bblock_link *l = new(mem_ctx) elk_bblock_link(block, kind); return &l->link; } void -push_stack(exec_list *list, void *mem_ctx, bblock_t *block) +push_stack(exec_list *list, void *mem_ctx, elk_bblock_t *block) { /* The kind of the link is immaterial, but we need to provide one since * this is (ab)using the edge data structure in order to implement a stack. @@ -63,7 +63,7 @@ push_stack(exec_list *list, void *mem_ctx, bblock_t *block) list->push_tail(link(mem_ctx, block, bblock_link_logical)); } -bblock_t::bblock_t(cfg_t *cfg) : +elk_bblock_t::elk_bblock_t(elk_cfg_t *cfg) : cfg(cfg), start_ip(0), end_ip(0), end_ip_delta(0), num(0) { instructions.make_empty(); @@ -72,7 +72,7 @@ bblock_t::bblock_t(cfg_t *cfg) : } void -bblock_t::add_successor(void *mem_ctx, bblock_t *successor, +elk_bblock_t::add_successor(void *mem_ctx, elk_bblock_t *successor, enum bblock_link_kind kind) { successor->parents.push_tail(::link(mem_ctx, this, kind)); @@ -80,10 +80,10 @@ bblock_t::add_successor(void *mem_ctx, bblock_t *successor, } bool -bblock_t::is_predecessor_of(const bblock_t *block, +elk_bblock_t::is_predecessor_of(const elk_bblock_t *block, enum bblock_link_kind kind) const { - foreach_list_typed_safe (bblock_link, parent, link, &block->parents) { + foreach_list_typed_safe (elk_bblock_link, parent, link, &block->parents) { if (parent->block == this && parent->kind <= kind) { return true; } @@ -93,10 +93,10 @@ bblock_t::is_predecessor_of(const bblock_t *block, } bool -bblock_t::is_successor_of(const bblock_t *block, +elk_bblock_t::is_successor_of(const elk_bblock_t *block, enum bblock_link_kind kind) const { - foreach_list_typed_safe (bblock_link, child, link, &block->children) { + foreach_list_typed_safe (elk_bblock_link, child, link, &block->children) { if (child->block == this && child->kind <= kind) { return true; } @@ -106,31 +106,31 @@ bblock_t::is_successor_of(const bblock_t *block, } static bool -ends_block(const backend_instruction *inst) +ends_block(const elk_backend_instruction *inst) { - enum opcode op = inst->opcode; + enum elk_opcode op = inst->opcode; - return op == BRW_OPCODE_IF || - op == BRW_OPCODE_ELSE || - op == BRW_OPCODE_CONTINUE || - op == BRW_OPCODE_BREAK || - op == BRW_OPCODE_DO || - op == BRW_OPCODE_WHILE; + return op == ELK_OPCODE_IF || + op == ELK_OPCODE_ELSE || + op == ELK_OPCODE_CONTINUE || + op == ELK_OPCODE_BREAK || + op == ELK_OPCODE_DO || + op == ELK_OPCODE_WHILE; } static bool -starts_block(const backend_instruction *inst) +starts_block(const elk_backend_instruction *inst) { - enum opcode op = inst->opcode; + enum elk_opcode op = inst->opcode; - return op == BRW_OPCODE_DO || - op == BRW_OPCODE_ENDIF; + return op == ELK_OPCODE_DO || + op == ELK_OPCODE_ENDIF; } bool -bblock_t::can_combine_with(const bblock_t *that) const +elk_bblock_t::can_combine_with(const elk_bblock_t *that) const { - if ((const bblock_t *)this->link.next != that) + if ((const elk_bblock_t *)this->link.next != that) return false; if (ends_block(this->end()) || @@ -141,10 +141,10 @@ bblock_t::can_combine_with(const bblock_t *that) const } void -bblock_t::combine_with(bblock_t *that) +elk_bblock_t::combine_with(elk_bblock_t *that) { assert(this->can_combine_with(that)); - foreach_list_typed (bblock_link, link, link, &that->parents) { + foreach_list_typed (elk_bblock_link, link, link, &that->parents) { assert(link->block == this); } @@ -155,12 +155,12 @@ bblock_t::combine_with(bblock_t *that) } void -bblock_t::dump(FILE *file) const +elk_bblock_t::dump(FILE *file) const { - const backend_shader *s = this->cfg->s; + const elk_backend_shader *s = this->cfg->s; int ip = this->start_ip; - foreach_inst_in_block(backend_instruction, inst, this) { + foreach_inst_in_block(elk_backend_instruction, inst, this) { fprintf(file, "%5d: ", ip); s->dump_instruction(inst, file); ip++; @@ -168,16 +168,16 @@ bblock_t::dump(FILE *file) const } void -bblock_t::unlink_list(exec_list *list) +elk_bblock_t::unlink_list(exec_list *list) { assert(list == &parents || list == &children); const bool remove_parent = list == &children; - foreach_list_typed_safe(bblock_link, link, link, list) { + foreach_list_typed_safe(elk_bblock_link, link, link, list) { /* Also break the links from the other block back to this block. */ exec_list *sub_list = remove_parent ? &link->block->parents : &link->block->children; - foreach_list_typed_safe(bblock_link, sub_link, link, sub_list) { + foreach_list_typed_safe(elk_bblock_link, sub_link, link, sub_list) { if (sub_link->block == this) { sub_link->link.remove(); ralloc_free(sub_link); @@ -189,7 +189,7 @@ bblock_t::unlink_list(exec_list *list) } } -cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : +elk_cfg_t::elk_cfg_t(const elk_backend_shader *s, exec_list *instructions) : s(s) { mem_ctx = ralloc_context(NULL); @@ -197,27 +197,27 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : blocks = NULL; num_blocks = 0; - bblock_t *cur = NULL; + elk_bblock_t *cur = NULL; int ip = 0; - bblock_t *entry = new_block(); - bblock_t *cur_if = NULL; /**< BB ending with IF. */ - bblock_t *cur_else = NULL; /**< BB ending with ELSE. */ - bblock_t *cur_do = NULL; /**< BB starting with DO. */ - bblock_t *cur_while = NULL; /**< BB immediately following WHILE. */ + elk_bblock_t *entry = new_block(); + elk_bblock_t *cur_if = NULL; /**< BB ending with IF. */ + elk_bblock_t *cur_else = NULL; /**< BB ending with ELSE. */ + elk_bblock_t *cur_do = NULL; /**< BB starting with DO. */ + elk_bblock_t *cur_while = NULL; /**< BB immediately following WHILE. */ exec_list if_stack, else_stack, do_stack, while_stack; - bblock_t *next; + elk_bblock_t *next; set_next_block(&cur, entry, ip); - foreach_in_list_safe(backend_instruction, inst, instructions) { + foreach_in_list_safe(elk_backend_instruction, inst, instructions) { /* set_next_block wants the post-incremented ip */ ip++; inst->exec_node::remove(); switch (inst->opcode) { - case BRW_OPCODE_IF: + case ELK_OPCODE_IF: cur->instructions.push_tail(inst); /* Push our information onto a stack so we can recover from @@ -238,7 +238,7 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : set_next_block(&cur, next, ip); break; - case BRW_OPCODE_ELSE: + case ELK_OPCODE_ELSE: cur->instructions.push_tail(inst); cur_else = cur; @@ -251,8 +251,8 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : set_next_block(&cur, next, ip); break; - case BRW_OPCODE_ENDIF: { - bblock_t *cur_endif; + case ELK_OPCODE_ENDIF: { + elk_bblock_t *cur_endif; if (cur->instructions.is_empty()) { /* New block was just created; use it. */ @@ -274,15 +274,15 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : cur_if->add_successor(mem_ctx, cur_endif, bblock_link_logical); } - assert(cur_if->end()->opcode == BRW_OPCODE_IF); - assert(!cur_else || cur_else->end()->opcode == BRW_OPCODE_ELSE); + assert(cur_if->end()->opcode == ELK_OPCODE_IF); + assert(!cur_else || cur_else->end()->opcode == ELK_OPCODE_ELSE); /* Pop the stack so we're in the previous if/else/endif */ cur_if = pop_stack(&if_stack); cur_else = pop_stack(&else_stack); break; } - case BRW_OPCODE_DO: + case ELK_OPCODE_DO: /* Push our information onto a stack so we can recover from * nested loops. */ @@ -339,7 +339,7 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : set_next_block(&cur, next, ip); break; - case BRW_OPCODE_CONTINUE: + case ELK_OPCODE_CONTINUE: cur->instructions.push_tail(inst); /* A conditional CONTINUE may start a region of divergent control @@ -367,7 +367,7 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : set_next_block(&cur, next, ip); break; - case BRW_OPCODE_BREAK: + case ELK_OPCODE_BREAK: cur->instructions.push_tail(inst); /* A conditional BREAK instruction may start a region of divergent @@ -393,7 +393,7 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : set_next_block(&cur, next, ip); break; - case BRW_OPCODE_WHILE: + case ELK_OPCODE_WHILE: cur->instructions.push_tail(inst); assert(cur_do != NULL && cur_while != NULL); @@ -431,16 +431,16 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) : make_block_array(); } -cfg_t::~cfg_t() +elk_cfg_t::~elk_cfg_t() { ralloc_free(mem_ctx); } void -cfg_t::remove_block(bblock_t *block) +elk_cfg_t::remove_block(elk_bblock_t *block) { - foreach_list_typed_safe (bblock_link, predecessor, link, &block->parents) { - /* cfg_t::validate checks that predecessor and successor lists are well + foreach_list_typed_safe (elk_bblock_link, predecessor, link, &block->parents) { + /* elk_cfg_t::validate checks that predecessor and successor lists are well * formed, so it is known that the loop here would find exactly one * block. Set old_link_kind to silence "variable used but not set" * warnings. @@ -448,7 +448,7 @@ cfg_t::remove_block(bblock_t *block) bblock_link_kind old_link_kind = bblock_link_logical; /* Remove block from all of its predecessors' successor lists. */ - foreach_list_typed_safe (bblock_link, successor, link, + foreach_list_typed_safe (elk_bblock_link, successor, link, &predecessor->block->children) { if (block == successor->block) { old_link_kind = successor->kind; @@ -459,11 +459,11 @@ cfg_t::remove_block(bblock_t *block) } /* Add removed-block's successors to its predecessors' successor lists. */ - foreach_list_typed (bblock_link, successor, link, &block->children) { + foreach_list_typed (elk_bblock_link, successor, link, &block->children) { bool need_to_link = true; bblock_link_kind new_link_kind = MAX2(old_link_kind, successor->kind); - foreach_list_typed_safe (bblock_link, child, link, &predecessor->block->children) { + foreach_list_typed_safe (elk_bblock_link, child, link, &predecessor->block->children) { /* There is already a link between the two blocks. If the links * are the same kind or the link is logical, do nothing. If the * existing link is physical and the proposed new link is logical, @@ -487,8 +487,8 @@ cfg_t::remove_block(bblock_t *block) } } - foreach_list_typed_safe (bblock_link, successor, link, &block->children) { - /* cfg_t::validate checks that predecessor and successor lists are well + foreach_list_typed_safe (elk_bblock_link, successor, link, &block->children) { + /* elk_cfg_t::validate checks that predecessor and successor lists are well * formed, so it is known that the loop here would find exactly one * block. Set old_link_kind to silence "variable used but not set" * warnings. @@ -496,7 +496,7 @@ cfg_t::remove_block(bblock_t *block) bblock_link_kind old_link_kind = bblock_link_logical; /* Remove block from all of its childrens' parents lists. */ - foreach_list_typed_safe (bblock_link, predecessor, link, + foreach_list_typed_safe (elk_bblock_link, predecessor, link, &successor->block->parents) { if (block == predecessor->block) { old_link_kind = predecessor->kind; @@ -506,11 +506,11 @@ cfg_t::remove_block(bblock_t *block) } /* Add removed-block's predecessors to its successors' predecessor lists. */ - foreach_list_typed (bblock_link, predecessor, link, &block->parents) { + foreach_list_typed (elk_bblock_link, predecessor, link, &block->parents) { bool need_to_link = true; bblock_link_kind new_link_kind = MAX2(old_link_kind, predecessor->kind); - foreach_list_typed_safe (bblock_link, parent, link, &successor->block->parents) { + foreach_list_typed_safe (elk_bblock_link, parent, link, &successor->block->parents) { /* There is already a link between the two blocks. If the links * are the same kind or the link is logical, do nothing. If the * existing link is physical and the proposed new link is logical, @@ -545,16 +545,16 @@ cfg_t::remove_block(bblock_t *block) this->num_blocks--; } -bblock_t * -cfg_t::new_block() +elk_bblock_t * +elk_cfg_t::new_block() { - bblock_t *block = new(mem_ctx) bblock_t(this); + elk_bblock_t *block = new(mem_ctx) elk_bblock_t(this); return block; } void -cfg_t::set_next_block(bblock_t **cur, bblock_t *block, int ip) +elk_cfg_t::set_next_block(elk_bblock_t **cur, elk_bblock_t *block, int ip) { if (*cur) { (*cur)->end_ip = ip - 1; @@ -567,9 +567,9 @@ cfg_t::set_next_block(bblock_t **cur, bblock_t *block, int ip) } void -cfg_t::make_block_array() +elk_cfg_t::make_block_array() { - blocks = ralloc_array(mem_ctx, bblock_t *, num_blocks); + blocks = ralloc_array(mem_ctx, elk_bblock_t *, num_blocks); int i = 0; foreach_block (block, this) { @@ -602,7 +602,7 @@ void sort_links(util_dynarray *scratch, exec_list *list) { util_dynarray_clear(scratch); - foreach_list_typed(bblock_link, link, link, list) { + foreach_list_typed(elk_bblock_link, link, link, list) { link_desc l; l.kind = link->kind == bblock_link_logical ? '-' : '~'; l.num = link->block->num; @@ -615,7 +615,7 @@ sort_links(util_dynarray *scratch, exec_list *list) } /* namespace */ void -cfg_t::dump(FILE *file) +elk_cfg_t::dump(FILE *file) { const idom_tree *idom = (s ? &s->idom_analysis.require() : NULL); @@ -658,9 +658,9 @@ cfg_t::dump(FILE *file) * (less than 1000 nodes) that this algorithm is significantly faster than * others like Lengauer-Tarjan. */ -idom_tree::idom_tree(const backend_shader *s) : +idom_tree::idom_tree(const elk_backend_shader *s) : num_parents(s->cfg->num_blocks), - parents(new bblock_t *[num_parents]()) + parents(new elk_bblock_t *[num_parents]()) { bool changed; @@ -673,8 +673,8 @@ idom_tree::idom_tree(const backend_shader *s) : if (block->num == 0) continue; - bblock_t *new_idom = NULL; - foreach_list_typed(bblock_link, parent_link, link, &block->parents) { + elk_bblock_t *new_idom = NULL; + foreach_list_typed(elk_bblock_link, parent_link, link, &block->parents) { if (parent(parent_link->block)) { new_idom = (new_idom ? intersect(new_idom, parent_link->block) : parent_link->block); @@ -694,8 +694,8 @@ idom_tree::~idom_tree() delete[] parents; } -bblock_t * -idom_tree::intersect(bblock_t *b1, bblock_t *b2) const +elk_bblock_t * +idom_tree::intersect(elk_bblock_t *b1, elk_bblock_t *b2) const { /* Note, the comparisons here are the opposite of what the paper says * because we index blocks from beginning -> end (i.e. reverse post-order) @@ -721,13 +721,13 @@ idom_tree::dump() const } void -cfg_t::dump_cfg() +elk_cfg_t::dump_cfg() { printf("digraph CFG {\n"); for (int b = 0; b < num_blocks; b++) { - bblock_t *block = this->blocks[b]; + elk_bblock_t *block = this->blocks[b]; - foreach_list_typed_safe (bblock_link, child, link, &block->children) { + foreach_list_typed_safe (elk_bblock_link, child, link, &block->children) { printf("\t%d -> %d\n", b, child->block->num); } } @@ -745,17 +745,17 @@ cfg_t::dump_cfg() #ifndef NDEBUG void -cfg_t::validate(const char *stage_abbrev) +elk_cfg_t::validate(const char *stage_abbrev) { foreach_block(block, this) { - foreach_list_typed(bblock_link, successor, link, &block->children) { + foreach_list_typed(elk_bblock_link, successor, link, &block->children) { /* Each successor of a block must have one predecessor link back to * the block. */ bool successor_links_back_to_predecessor = false; - bblock_t *succ_block = successor->block; + elk_bblock_t *succ_block = successor->block; - foreach_list_typed(bblock_link, predecessor, link, &succ_block->parents) { + foreach_list_typed(elk_bblock_link, predecessor, link, &succ_block->parents) { if (predecessor->block == block) { cfgv_assert(!successor_links_back_to_predecessor); cfgv_assert(successor->kind == predecessor->kind); @@ -768,20 +768,20 @@ cfg_t::validate(const char *stage_abbrev) /* Each successor block must appear only once in the list of * successors. */ - foreach_list_typed_from(bblock_link, later_successor, link, + foreach_list_typed_from(elk_bblock_link, later_successor, link, &block->children, successor->link.next) { cfgv_assert(successor->block != later_successor->block); } } - foreach_list_typed(bblock_link, predecessor, link, &block->parents) { + foreach_list_typed(elk_bblock_link, predecessor, link, &block->parents) { /* Each predecessor of a block must have one successor link back to * the block. */ bool predecessor_links_back_to_successor = false; - bblock_t *pred_block = predecessor->block; + elk_bblock_t *pred_block = predecessor->block; - foreach_list_typed(bblock_link, successor, link, &pred_block->children) { + foreach_list_typed(elk_bblock_link, successor, link, &pred_block->children) { if (successor->block == block) { cfgv_assert(!predecessor_links_back_to_successor); cfgv_assert(successor->kind == predecessor->kind); @@ -794,14 +794,14 @@ cfg_t::validate(const char *stage_abbrev) /* Each precessor block must appear only once in the list of * precessors. */ - foreach_list_typed_from(bblock_link, later_precessor, link, + foreach_list_typed_from(elk_bblock_link, later_precessor, link, &block->parents, predecessor->link.next) { cfgv_assert(predecessor->block != later_precessor->block); } } - backend_instruction *first_inst = block->start(); - if (first_inst->opcode == BRW_OPCODE_DO) { + elk_backend_instruction *first_inst = block->start(); + if (first_inst->opcode == ELK_OPCODE_DO) { /* DO instructions both begin and end a block, so the DO instruction * must be the only instruction in the block. */ @@ -812,10 +812,10 @@ cfg_t::validate(const char *stage_abbrev) * instruction. The other is a logical link to the block starting the * body of the loop. */ - bblock_t *physical_block = nullptr; - bblock_t *logical_block = nullptr; + elk_bblock_t *physical_block = nullptr; + elk_bblock_t *logical_block = nullptr; - foreach_list_typed(bblock_link, child, link, &block->children) { + foreach_list_typed(elk_bblock_link, child, link, &block->children) { if (child->kind == bblock_link_physical) { cfgv_assert(physical_block == nullptr); physical_block = child->block; diff --git a/src/intel/compiler/elk/elk_cfg.h b/src/intel/compiler/elk/elk_cfg.h index 4f60e0729ec..86eb9d56402 100644 --- a/src/intel/compiler/elk/elk_cfg.h +++ b/src/intel/compiler/elk/elk_cfg.h @@ -33,7 +33,7 @@ #include "elk_ir_analysis.h" #endif -struct bblock_t; +struct elk_bblock_t; /** * CFG edge types. @@ -53,18 +53,18 @@ enum bblock_link_kind { bblock_link_physical }; -struct bblock_link { +struct elk_bblock_link { #ifdef __cplusplus - DECLARE_RALLOC_CXX_OPERATORS(bblock_link) + DECLARE_RALLOC_CXX_OPERATORS(elk_bblock_link) - bblock_link(bblock_t *block, enum bblock_link_kind kind) + elk_bblock_link(elk_bblock_t *block, enum bblock_link_kind kind) : block(block), kind(kind) { } #endif struct exec_node link; - struct bblock_t *block; + struct elk_bblock_t *block; /* Type of this CFG edge. Because bblock_link_logical also implies * bblock_link_physical, the proper way to test for membership of edge 'l' @@ -73,40 +73,40 @@ struct bblock_link { enum bblock_link_kind kind; }; -struct backend_shader; -struct cfg_t; +struct elk_backend_shader; +struct elk_cfg_t; -struct bblock_t { +struct elk_bblock_t { #ifdef __cplusplus - DECLARE_RALLOC_CXX_OPERATORS(bblock_t) + DECLARE_RALLOC_CXX_OPERATORS(elk_bblock_t) - explicit bblock_t(cfg_t *cfg); + explicit elk_bblock_t(elk_cfg_t *cfg); - void add_successor(void *mem_ctx, bblock_t *successor, + void add_successor(void *mem_ctx, elk_bblock_t *successor, enum bblock_link_kind kind); - bool is_predecessor_of(const bblock_t *block, + bool is_predecessor_of(const elk_bblock_t *block, enum bblock_link_kind kind) const; - bool is_successor_of(const bblock_t *block, + bool is_successor_of(const elk_bblock_t *block, enum bblock_link_kind kind) const; - bool can_combine_with(const bblock_t *that) const; - void combine_with(bblock_t *that); + bool can_combine_with(const elk_bblock_t *that) const; + void combine_with(elk_bblock_t *that); void dump(FILE *file = stderr) const; - backend_instruction *start(); - const backend_instruction *start() const; - backend_instruction *end(); - const backend_instruction *end() const; + elk_backend_instruction *start(); + const elk_backend_instruction *start() const; + elk_backend_instruction *end(); + const elk_backend_instruction *end() const; - bblock_t *next(); - const bblock_t *next() const; - bblock_t *prev(); - const bblock_t *prev() const; + elk_bblock_t *next(); + const elk_bblock_t *next() const; + elk_bblock_t *prev(); + const elk_bblock_t *prev() const; bool starts_with_control_flow() const; bool ends_with_control_flow() const; - backend_instruction *first_non_control_flow_inst(); - backend_instruction *last_non_control_flow_inst(); + elk_backend_instruction *first_non_control_flow_inst(); + elk_backend_instruction *last_non_control_flow_inst(); private: /** @@ -127,7 +127,7 @@ public: #endif struct exec_node link; - struct cfg_t *cfg; + struct elk_cfg_t *cfg; int start_ip; int end_ip; @@ -143,200 +143,200 @@ public: int num; }; -static inline struct backend_instruction * -bblock_start(struct bblock_t *block) +static inline struct elk_backend_instruction * +bblock_start(struct elk_bblock_t *block) { - return (struct backend_instruction *)exec_list_get_head(&block->instructions); + return (struct elk_backend_instruction *)exec_list_get_head(&block->instructions); } -static inline const struct backend_instruction * -bblock_start_const(const struct bblock_t *block) +static inline const struct elk_backend_instruction * +bblock_start_const(const struct elk_bblock_t *block) { - return (const struct backend_instruction *)exec_list_get_head_const(&block->instructions); + return (const struct elk_backend_instruction *)exec_list_get_head_const(&block->instructions); } -static inline struct backend_instruction * -bblock_end(struct bblock_t *block) +static inline struct elk_backend_instruction * +bblock_end(struct elk_bblock_t *block) { - return (struct backend_instruction *)exec_list_get_tail(&block->instructions); + return (struct elk_backend_instruction *)exec_list_get_tail(&block->instructions); } -static inline const struct backend_instruction * -bblock_end_const(const struct bblock_t *block) +static inline const struct elk_backend_instruction * +bblock_end_const(const struct elk_bblock_t *block) { - return (const struct backend_instruction *)exec_list_get_tail_const(&block->instructions); + return (const struct elk_backend_instruction *)exec_list_get_tail_const(&block->instructions); } -static inline struct bblock_t * -bblock_next(struct bblock_t *block) +static inline struct elk_bblock_t * +bblock_next(struct elk_bblock_t *block) { if (exec_node_is_tail_sentinel(block->link.next)) return NULL; - return (struct bblock_t *)block->link.next; + return (struct elk_bblock_t *)block->link.next; } -static inline const struct bblock_t * -bblock_next_const(const struct bblock_t *block) +static inline const struct elk_bblock_t * +bblock_next_const(const struct elk_bblock_t *block) { if (exec_node_is_tail_sentinel(block->link.next)) return NULL; - return (const struct bblock_t *)block->link.next; + return (const struct elk_bblock_t *)block->link.next; } -static inline struct bblock_t * -bblock_prev(struct bblock_t *block) +static inline struct elk_bblock_t * +bblock_prev(struct elk_bblock_t *block) { if (exec_node_is_head_sentinel(block->link.prev)) return NULL; - return (struct bblock_t *)block->link.prev; + return (struct elk_bblock_t *)block->link.prev; } -static inline const struct bblock_t * -bblock_prev_const(const struct bblock_t *block) +static inline const struct elk_bblock_t * +bblock_prev_const(const struct elk_bblock_t *block) { if (exec_node_is_head_sentinel(block->link.prev)) return NULL; - return (const struct bblock_t *)block->link.prev; + return (const struct elk_bblock_t *)block->link.prev; } static inline bool -bblock_starts_with_control_flow(const struct bblock_t *block) +bblock_starts_with_control_flow(const struct elk_bblock_t *block) { - enum opcode op = bblock_start_const(block)->opcode; - return op == BRW_OPCODE_DO || op == BRW_OPCODE_ENDIF; + enum elk_opcode op = bblock_start_const(block)->opcode; + return op == ELK_OPCODE_DO || op == ELK_OPCODE_ENDIF; } static inline bool -bblock_ends_with_control_flow(const struct bblock_t *block) +bblock_ends_with_control_flow(const struct elk_bblock_t *block) { - enum opcode op = bblock_end_const(block)->opcode; - return op == BRW_OPCODE_IF || - op == BRW_OPCODE_ELSE || - op == BRW_OPCODE_WHILE || - op == BRW_OPCODE_BREAK || - op == BRW_OPCODE_CONTINUE; + enum elk_opcode op = bblock_end_const(block)->opcode; + return op == ELK_OPCODE_IF || + op == ELK_OPCODE_ELSE || + op == ELK_OPCODE_WHILE || + op == ELK_OPCODE_BREAK || + op == ELK_OPCODE_CONTINUE; } -static inline struct backend_instruction * -bblock_first_non_control_flow_inst(struct bblock_t *block) +static inline struct elk_backend_instruction * +bblock_first_non_control_flow_inst(struct elk_bblock_t *block) { - struct backend_instruction *inst = bblock_start(block); + struct elk_backend_instruction *inst = bblock_start(block); if (bblock_starts_with_control_flow(block)) #ifdef __cplusplus - inst = (struct backend_instruction *)inst->next; + inst = (struct elk_backend_instruction *)inst->next; #else - inst = (struct backend_instruction *)inst->link.next; + inst = (struct elk_backend_instruction *)inst->link.next; #endif return inst; } -static inline struct backend_instruction * -bblock_last_non_control_flow_inst(struct bblock_t *block) +static inline struct elk_backend_instruction * +bblock_last_non_control_flow_inst(struct elk_bblock_t *block) { - struct backend_instruction *inst = bblock_end(block); + struct elk_backend_instruction *inst = bblock_end(block); if (bblock_ends_with_control_flow(block)) #ifdef __cplusplus - inst = (struct backend_instruction *)inst->prev; + inst = (struct elk_backend_instruction *)inst->prev; #else - inst = (struct backend_instruction *)inst->link.prev; + inst = (struct elk_backend_instruction *)inst->link.prev; #endif return inst; } #ifdef __cplusplus -inline backend_instruction * -bblock_t::start() +inline elk_backend_instruction * +elk_bblock_t::start() { return bblock_start(this); } -inline const backend_instruction * -bblock_t::start() const +inline const elk_backend_instruction * +elk_bblock_t::start() const { return bblock_start_const(this); } -inline backend_instruction * -bblock_t::end() +inline elk_backend_instruction * +elk_bblock_t::end() { return bblock_end(this); } -inline const backend_instruction * -bblock_t::end() const +inline const elk_backend_instruction * +elk_bblock_t::end() const { return bblock_end_const(this); } -inline bblock_t * -bblock_t::next() +inline elk_bblock_t * +elk_bblock_t::next() { return bblock_next(this); } -inline const bblock_t * -bblock_t::next() const +inline const elk_bblock_t * +elk_bblock_t::next() const { return bblock_next_const(this); } -inline bblock_t * -bblock_t::prev() +inline elk_bblock_t * +elk_bblock_t::prev() { return bblock_prev(this); } -inline const bblock_t * -bblock_t::prev() const +inline const elk_bblock_t * +elk_bblock_t::prev() const { return bblock_prev_const(this); } inline bool -bblock_t::starts_with_control_flow() const +elk_bblock_t::starts_with_control_flow() const { return bblock_starts_with_control_flow(this); } inline bool -bblock_t::ends_with_control_flow() const +elk_bblock_t::ends_with_control_flow() const { return bblock_ends_with_control_flow(this); } -inline backend_instruction * -bblock_t::first_non_control_flow_inst() +inline elk_backend_instruction * +elk_bblock_t::first_non_control_flow_inst() { return bblock_first_non_control_flow_inst(this); } -inline backend_instruction * -bblock_t::last_non_control_flow_inst() +inline elk_backend_instruction * +elk_bblock_t::last_non_control_flow_inst() { return bblock_last_non_control_flow_inst(this); } #endif -struct cfg_t { +struct elk_cfg_t { #ifdef __cplusplus - DECLARE_RALLOC_CXX_OPERATORS(cfg_t) + DECLARE_RALLOC_CXX_OPERATORS(elk_cfg_t) - cfg_t(const backend_shader *s, exec_list *instructions); - ~cfg_t(); + elk_cfg_t(const elk_backend_shader *s, exec_list *instructions); + ~elk_cfg_t(); - void remove_block(bblock_t *block); + void remove_block(elk_bblock_t *block); - bblock_t *first_block(); - const bblock_t *first_block() const; - bblock_t *last_block(); - const bblock_t *last_block() const; + elk_bblock_t *first_block(); + const elk_bblock_t *first_block() const; + elk_bblock_t *last_block(); + const elk_bblock_t *last_block() const; - bblock_t *new_block(); - void set_next_block(bblock_t **cur, bblock_t *block, int ip); + elk_bblock_t *new_block(); + void set_next_block(elk_bblock_t **cur, elk_bblock_t *block, int ip); void make_block_array(); void dump(FILE *file = stderr); @@ -349,65 +349,65 @@ struct cfg_t { #endif /** - * Propagate bblock_t::end_ip_delta data through the CFG. + * Propagate elk_bblock_t::end_ip_delta data through the CFG. */ inline void adjust_block_ips(); #endif - const struct backend_shader *s; + const struct elk_backend_shader *s; void *mem_ctx; /** Ordered list (by ip) of basic blocks */ struct exec_list block_list; - struct bblock_t **blocks; + struct elk_bblock_t **blocks; int num_blocks; }; -static inline struct bblock_t * -cfg_first_block(struct cfg_t *cfg) +static inline struct elk_bblock_t * +cfg_first_block(struct elk_cfg_t *cfg) { - return (struct bblock_t *)exec_list_get_head(&cfg->block_list); + return (struct elk_bblock_t *)exec_list_get_head(&cfg->block_list); } -static inline const struct bblock_t * -cfg_first_block_const(const struct cfg_t *cfg) +static inline const struct elk_bblock_t * +cfg_first_block_const(const struct elk_cfg_t *cfg) { - return (const struct bblock_t *)exec_list_get_head_const(&cfg->block_list); + return (const struct elk_bblock_t *)exec_list_get_head_const(&cfg->block_list); } -static inline struct bblock_t * -cfg_last_block(struct cfg_t *cfg) +static inline struct elk_bblock_t * +cfg_last_block(struct elk_cfg_t *cfg) { - return (struct bblock_t *)exec_list_get_tail(&cfg->block_list); + return (struct elk_bblock_t *)exec_list_get_tail(&cfg->block_list); } -static inline const struct bblock_t * -cfg_last_block_const(const struct cfg_t *cfg) +static inline const struct elk_bblock_t * +cfg_last_block_const(const struct elk_cfg_t *cfg) { - return (const struct bblock_t *)exec_list_get_tail_const(&cfg->block_list); + return (const struct elk_bblock_t *)exec_list_get_tail_const(&cfg->block_list); } #ifdef __cplusplus -inline bblock_t * -cfg_t::first_block() +inline elk_bblock_t * +elk_cfg_t::first_block() { return cfg_first_block(this); } -const inline bblock_t * -cfg_t::first_block() const +const inline elk_bblock_t * +elk_cfg_t::first_block() const { return cfg_first_block_const(this); } -inline bblock_t * -cfg_t::last_block() +inline elk_bblock_t * +elk_cfg_t::last_block() { return cfg_last_block(this); } -const inline bblock_t * -cfg_t::last_block() const +const inline elk_bblock_t * +elk_cfg_t::last_block() const { return cfg_last_block_const(this); } @@ -428,16 +428,16 @@ cfg_t::last_block() const foreach_inst_in_block_safe (__type, __inst, __block) #define foreach_block(__block, __cfg) \ - foreach_list_typed (bblock_t, __block, link, &(__cfg)->block_list) + foreach_list_typed (elk_bblock_t, __block, link, &(__cfg)->block_list) #define foreach_block_reverse(__block, __cfg) \ - foreach_list_typed_reverse (bblock_t, __block, link, &(__cfg)->block_list) + foreach_list_typed_reverse (elk_bblock_t, __block, link, &(__cfg)->block_list) #define foreach_block_safe(__block, __cfg) \ - foreach_list_typed_safe (bblock_t, __block, link, &(__cfg)->block_list) + foreach_list_typed_safe (elk_bblock_t, __block, link, &(__cfg)->block_list) #define foreach_block_reverse_safe(__block, __cfg) \ - foreach_list_typed_reverse_safe (bblock_t, __block, link, &(__cfg)->block_list) + foreach_list_typed_reverse_safe (elk_bblock_t, __block, link, &(__cfg)->block_list) #define foreach_inst_in_block(__type, __inst, __block) \ foreach_in_list(__type, __inst, &(__block)->instructions) @@ -467,7 +467,7 @@ cfg_t::last_block() const #ifdef __cplusplus inline void -cfg_t::adjust_block_ips() +elk_cfg_t::adjust_block_ips() { int delta = 0; @@ -486,11 +486,11 @@ namespace elk { * Immediate dominator tree analysis of a shader. */ struct idom_tree { - idom_tree(const backend_shader *s); + idom_tree(const elk_backend_shader *s); ~idom_tree(); bool - validate(const backend_shader *) const + validate(const elk_backend_shader *) const { /* FINISHME */ return true; @@ -502,29 +502,29 @@ namespace elk { return DEPENDENCY_BLOCKS; } - const bblock_t * - parent(const bblock_t *b) const + const elk_bblock_t * + parent(const elk_bblock_t *b) const { assert(unsigned(b->num) < num_parents); return parents[b->num]; } - bblock_t * - parent(bblock_t *b) const + elk_bblock_t * + parent(elk_bblock_t *b) const { assert(unsigned(b->num) < num_parents); return parents[b->num]; } - bblock_t * - intersect(bblock_t *b1, bblock_t *b2) const; + elk_bblock_t * + intersect(elk_bblock_t *b1, elk_bblock_t *b2) const; void dump() const; private: unsigned num_parents; - bblock_t **parents; + elk_bblock_t **parents; }; } #endif diff --git a/src/intel/compiler/elk/elk_clip.h b/src/intel/compiler/elk/elk_clip.h index 9afee1b1224..b065157a4b3 100644 --- a/src/intel/compiler/elk/elk_clip.h +++ b/src/intel/compiler/elk/elk_clip.h @@ -43,37 +43,37 @@ #define PRIM_MASK (0x1f) -struct brw_clip_compile { - struct brw_codegen func; - struct brw_clip_prog_key key; - struct brw_clip_prog_data prog_data; +struct elk_clip_compile { + struct elk_codegen func; + struct elk_clip_prog_key key; + struct elk_clip_prog_data prog_data; struct { - struct brw_reg R0; - struct brw_reg vertex[MAX_VERTS]; + struct elk_reg R0; + struct elk_reg vertex[MAX_VERTS]; - struct brw_reg t; - struct brw_reg t0, t1; - struct brw_reg dp0, dp1; + struct elk_reg t; + struct elk_reg t0, t1; + struct elk_reg dp0, dp1; - struct brw_reg dpPrev; - struct brw_reg dp; - struct brw_reg loopcount; - struct brw_reg nr_verts; - struct brw_reg planemask; + struct elk_reg dpPrev; + struct elk_reg dp; + struct elk_reg loopcount; + struct elk_reg nr_verts; + struct elk_reg planemask; - struct brw_reg inlist; - struct brw_reg outlist; - struct brw_reg freelist; + struct elk_reg inlist; + struct elk_reg outlist; + struct elk_reg freelist; - struct brw_reg dir; - struct brw_reg tmp0, tmp1; - struct brw_reg offset; + struct elk_reg dir; + struct elk_reg tmp0, tmp1; + struct elk_reg offset; - struct brw_reg fixed_planes; - struct brw_reg plane_equation; + struct elk_reg fixed_planes; + struct elk_reg plane_equation; - struct brw_reg ff_sync; + struct elk_reg ff_sync; /* Bitmask indicating which coordinate attribute should be used for * comparison to each clipping plane. A 0 indicates that VARYING_SLOT_POS @@ -82,10 +82,10 @@ struct brw_clip_compile { * VARYING_SLOT_CLIP_VERTEX should be used (if available) since it's a user- * defined clipping plane. */ - struct brw_reg vertex_src_mask; + struct elk_reg vertex_src_mask; /* Offset into the vertex of the current plane's clipdistance value */ - struct brw_reg clipdistance_offset; + struct elk_reg clipdistance_offset; } reg; /* Number of registers storing VUE data */ @@ -102,7 +102,7 @@ struct brw_clip_compile { /** * True if the given varying is one of the outputs of the vertex shader. */ -static inline bool brw_clip_have_varying(struct brw_clip_compile *c, +static inline bool elk_clip_have_varying(struct elk_clip_compile *c, GLuint varying) { return (c->key.attrs & BITFIELD64_BIT(varying)) ? 1 : 0; @@ -111,53 +111,53 @@ static inline bool brw_clip_have_varying(struct brw_clip_compile *c, /* Points are only culled, so no need for a clip routine, however it * works out easier to have a dummy one. */ -void brw_emit_unfilled_clip( struct brw_clip_compile *c ); -void brw_emit_tri_clip( struct brw_clip_compile *c ); -void brw_emit_line_clip( struct brw_clip_compile *c ); -void brw_emit_point_clip( struct brw_clip_compile *c ); +void elk_emit_unfilled_clip( struct elk_clip_compile *c ); +void elk_emit_tri_clip( struct elk_clip_compile *c ); +void elk_emit_line_clip( struct elk_clip_compile *c ); +void elk_emit_point_clip( struct elk_clip_compile *c ); -/* brw_clip_tri.c, for use by the unfilled clip routine: +/* elk_clip_tri.c, for use by the unfilled clip routine: */ -void brw_clip_tri_init_vertices( struct brw_clip_compile *c ); -void brw_clip_tri_flat_shade( struct brw_clip_compile *c ); -void brw_clip_tri( struct brw_clip_compile *c ); -void brw_clip_tri_emit_polygon( struct brw_clip_compile *c ); -void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, +void elk_clip_tri_init_vertices( struct elk_clip_compile *c ); +void elk_clip_tri_flat_shade( struct elk_clip_compile *c ); +void elk_clip_tri( struct elk_clip_compile *c ); +void elk_clip_tri_emit_polygon( struct elk_clip_compile *c ); +void elk_clip_tri_alloc_regs( struct elk_clip_compile *c, GLuint nr_verts ); /* Utils: */ -void brw_clip_interp_vertex( struct brw_clip_compile *c, - struct brw_indirect dest_ptr, - struct brw_indirect v0_ptr, /* from */ - struct brw_indirect v1_ptr, /* to */ - struct brw_reg t0, +void elk_clip_interp_vertex( struct elk_clip_compile *c, + struct elk_indirect dest_ptr, + struct elk_indirect v0_ptr, /* from */ + struct elk_indirect v1_ptr, /* to */ + struct elk_reg t0, bool force_edgeflag ); -void brw_clip_init_planes( struct brw_clip_compile *c ); +void elk_clip_init_planes( struct elk_clip_compile *c ); -void brw_clip_emit_vue(struct brw_clip_compile *c, - struct brw_indirect vert, - enum brw_urb_write_flags flags, +void elk_clip_emit_vue(struct elk_clip_compile *c, + struct elk_indirect vert, + enum elk_urb_write_flags flags, GLuint header); -void brw_clip_kill_thread(struct brw_clip_compile *c); +void elk_clip_kill_thread(struct elk_clip_compile *c); -struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c ); -struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c ); +struct elk_reg elk_clip_plane_stride( struct elk_clip_compile *c ); +struct elk_reg elk_clip_plane0_address( struct elk_clip_compile *c ); -void brw_clip_copy_flatshaded_attributes( struct brw_clip_compile *c, +void elk_clip_copy_flatshaded_attributes( struct elk_clip_compile *c, GLuint to, GLuint from ); -void brw_clip_init_clipmask( struct brw_clip_compile *c ); +void elk_clip_init_clipmask( struct elk_clip_compile *c ); -struct brw_reg get_tmp( struct brw_clip_compile *c ); +struct elk_reg get_tmp( struct elk_clip_compile *c ); -void brw_clip_project_position(struct brw_clip_compile *c, - struct brw_reg pos ); -void brw_clip_ff_sync(struct brw_clip_compile *c); -void brw_clip_init_ff_sync(struct brw_clip_compile *c); +void elk_clip_project_position(struct elk_clip_compile *c, + struct elk_reg pos ); +void elk_clip_ff_sync(struct elk_clip_compile *c); +void elk_clip_init_ff_sync(struct elk_clip_compile *c); #endif diff --git a/src/intel/compiler/elk/elk_clip_line.c b/src/intel/compiler/elk/elk_clip_line.c index 7e1e7976882..f90c70315f9 100644 --- a/src/intel/compiler/elk/elk_clip_line.c +++ b/src/intel/compiler/elk/elk_clip_line.c @@ -32,17 +32,17 @@ #include "elk_clip.h" #include "elk_prim.h" -static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) +static void elk_clip_line_alloc_regs( struct elk_clip_compile *c ) { const struct intel_device_info *devinfo = c->func.devinfo; GLuint i = 0,j; /* Register usage is static, precompute here: */ - c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; + c->reg.R0 = retype(elk_vec8_grf(i, 0), ELK_REGISTER_TYPE_UD); i++; if (c->key.nr_userclip) { - c->reg.fixed_planes = brw_vec4_grf(i, 0); + c->reg.fixed_planes = elk_vec4_grf(i, 0); i += (6 + c->key.nr_userclip + 1) / 2; c->prog_data.curb_read_length = (6 + c->key.nr_userclip + 1) / 2; @@ -54,32 +54,32 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) /* Payload vertices plus space for more generated vertices: */ for (j = 0; j < 4; j++) { - c->reg.vertex[j] = brw_vec4_grf(i, 0); + c->reg.vertex[j] = elk_vec4_grf(i, 0); i += c->nr_regs; } - c->reg.t = brw_vec1_grf(i, 0); - c->reg.t0 = brw_vec1_grf(i, 1); - c->reg.t1 = brw_vec1_grf(i, 2); - c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); - c->reg.plane_equation = brw_vec4_grf(i, 4); + c->reg.t = elk_vec1_grf(i, 0); + c->reg.t0 = elk_vec1_grf(i, 1); + c->reg.t1 = elk_vec1_grf(i, 2); + c->reg.planemask = retype(elk_vec1_grf(i, 3), ELK_REGISTER_TYPE_UD); + c->reg.plane_equation = elk_vec4_grf(i, 4); i++; - c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ - c->reg.dp1 = brw_vec1_grf(i, 4); + c->reg.dp0 = elk_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ + c->reg.dp1 = elk_vec1_grf(i, 4); i++; if (!c->key.nr_userclip) { - c->reg.fixed_planes = brw_vec8_grf(i, 0); + c->reg.fixed_planes = elk_vec8_grf(i, 0); i++; } - c->reg.vertex_src_mask = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); - c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W); + c->reg.vertex_src_mask = retype(elk_vec1_grf(i, 0), ELK_REGISTER_TYPE_UD); + c->reg.clipdistance_offset = retype(elk_vec1_grf(i, 1), ELK_REGISTER_TYPE_W); i++; if (devinfo->ver == 5) { - c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); + c->reg.ff_sync = retype(elk_vec1_grf(i, 0), ELK_REGISTER_TYPE_UD); i++; } @@ -115,111 +115,111 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) * interp( ctx, newvtx1, vtx1, vtx0, t1 ); * */ -static void clip_and_emit_line( struct brw_clip_compile *c ) +static void clip_and_emit_line( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_indirect vtx0 = brw_indirect(0, 0); - struct brw_indirect vtx1 = brw_indirect(1, 0); - struct brw_indirect newvtx0 = brw_indirect(2, 0); - struct brw_indirect newvtx1 = brw_indirect(3, 0); - struct brw_indirect plane_ptr = brw_indirect(4, 0); - struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD); - GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); + struct elk_codegen *p = &c->func; + struct elk_indirect vtx0 = elk_indirect(0, 0); + struct elk_indirect vtx1 = elk_indirect(1, 0); + struct elk_indirect newvtx0 = elk_indirect(2, 0); + struct elk_indirect newvtx1 = elk_indirect(3, 0); + struct elk_indirect plane_ptr = elk_indirect(4, 0); + struct elk_reg v1_null_ud = retype(vec1(elk_null_reg()), ELK_REGISTER_TYPE_UD); + GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); GLint clipdist0_offset = c->key.nr_userclip - ? brw_varying_to_offset(&c->vue_map, VARYING_SLOT_CLIP_DIST0) + ? elk_varying_to_offset(&c->vue_map, VARYING_SLOT_CLIP_DIST0) : 0; - brw_MOV(p, get_addr_reg(vtx0), brw_address(c->reg.vertex[0])); - brw_MOV(p, get_addr_reg(vtx1), brw_address(c->reg.vertex[1])); - brw_MOV(p, get_addr_reg(newvtx0), brw_address(c->reg.vertex[2])); - brw_MOV(p, get_addr_reg(newvtx1), brw_address(c->reg.vertex[3])); - brw_MOV(p, get_addr_reg(plane_ptr), brw_clip_plane0_address(c)); + elk_MOV(p, get_addr_reg(vtx0), elk_address(c->reg.vertex[0])); + elk_MOV(p, get_addr_reg(vtx1), elk_address(c->reg.vertex[1])); + elk_MOV(p, get_addr_reg(newvtx0), elk_address(c->reg.vertex[2])); + elk_MOV(p, get_addr_reg(newvtx1), elk_address(c->reg.vertex[3])); + elk_MOV(p, get_addr_reg(plane_ptr), elk_clip_plane0_address(c)); /* Note: init t0, t1 together: */ - brw_MOV(p, vec2(c->reg.t0), brw_imm_f(0)); + elk_MOV(p, vec2(c->reg.t0), elk_imm_f(0)); - brw_clip_init_planes(c); - brw_clip_init_clipmask(c); + elk_clip_init_planes(c); + elk_clip_init_clipmask(c); /* -ve rhw workaround */ if (p->devinfo->has_negative_rhw_bug) { - brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), - brw_imm_ud(1<<20)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f)); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_AND(p, elk_null_reg(), get_element_ud(c->reg.R0, 2), + elk_imm_ud(1<<20)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud(0x3f)); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); } /* Set the initial vertex source mask: The first 6 planes are the bounds * of the view volume; the next 8 planes are the user clipping planes. */ - brw_MOV(p, c->reg.vertex_src_mask, brw_imm_ud(0x3fc0)); + elk_MOV(p, c->reg.vertex_src_mask, elk_imm_ud(0x3fc0)); /* Set the initial clipdistance offset to be 6 floats before gl_ClipDistance[0]. * We'll increment 6 times before we start hitting actual user clipping. */ - brw_MOV(p, c->reg.clipdistance_offset, brw_imm_d(clipdist0_offset - 6*sizeof(float))); + elk_MOV(p, c->reg.clipdistance_offset, elk_imm_d(clipdist0_offset - 6*sizeof(float))); - brw_DO(p, BRW_EXECUTE_1); + elk_DO(p, ELK_EXECUTE_1); { /* if (planemask & 1) */ - brw_AND(p, v1_null_ud, c->reg.planemask, brw_imm_ud(1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); + elk_AND(p, v1_null_ud, c->reg.planemask, elk_imm_ud(1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { - brw_AND(p, v1_null_ud, c->reg.vertex_src_mask, brw_imm_ud(1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_IF(p, BRW_EXECUTE_1); + elk_AND(p, v1_null_ud, c->reg.vertex_src_mask, elk_imm_ud(1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_IF(p, ELK_EXECUTE_1); { /* user clip distance: just fetch the correct float from each vertex */ - struct brw_indirect temp_ptr = brw_indirect(7, 0); - brw_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx0), c->reg.clipdistance_offset); - brw_MOV(p, c->reg.dp0, deref_1f(temp_ptr, 0)); - brw_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx1), c->reg.clipdistance_offset); - brw_MOV(p, c->reg.dp1, deref_1f(temp_ptr, 0)); + struct elk_indirect temp_ptr = elk_indirect(7, 0); + elk_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx0), c->reg.clipdistance_offset); + elk_MOV(p, c->reg.dp0, deref_1f(temp_ptr, 0)); + elk_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx1), c->reg.clipdistance_offset); + elk_MOV(p, c->reg.dp1, deref_1f(temp_ptr, 0)); } - brw_ELSE(p); + elk_ELSE(p); { /* fixed plane: fetch the hpos, dp4 against the plane. */ if (c->key.nr_userclip) - brw_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0)); + elk_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0)); else - brw_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0)); + elk_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0)); - brw_DP4(p, vec4(c->reg.dp0), deref_4f(vtx0, hpos_offset), c->reg.plane_equation); - brw_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1, hpos_offset), c->reg.plane_equation); + elk_DP4(p, vec4(c->reg.dp0), deref_4f(vtx0, hpos_offset), c->reg.plane_equation); + elk_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1, hpos_offset), c->reg.plane_equation); } - brw_ENDIF(p); + elk_ENDIF(p); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, vec1(c->reg.dp1), brw_imm_f(0.0f)); + elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_L, vec1(c->reg.dp1), elk_imm_f(0.0f)); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { /* * Both can be negative on GM965/G965 due to RHW workaround * if so, this object should be rejected. */ if (p->devinfo->has_negative_rhw_bug) { - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0)); - brw_IF(p, BRW_EXECUTE_1); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_LE, c->reg.dp0, elk_imm_f(0.0)); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_kill_thread(c); + elk_clip_kill_thread(c); } - brw_ENDIF(p); + elk_ENDIF(p); } - brw_ADD(p, c->reg.t, c->reg.dp1, negate(c->reg.dp0)); - brw_math_invert(p, c->reg.t, c->reg.t); - brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp1); + elk_ADD(p, c->reg.t, c->reg.dp1, negate(c->reg.dp0)); + elk_math_invert(p, c->reg.t, c->reg.t); + elk_MUL(p, c->reg.t, c->reg.t, c->reg.dp1); - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t1 ); - brw_MOV(p, c->reg.t1, c->reg.t); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, - BRW_PREDICATE_NORMAL); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_G, c->reg.t, c->reg.t1 ); + elk_MOV(p, c->reg.t1, c->reg.t); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, + ELK_PREDICATE_NORMAL); } - brw_ELSE(p); + elk_ELSE(p); { /* Coming back in. We know that both cannot be negative * because the line would have been culled in that case. @@ -228,75 +228,75 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) /* If both are positive, do nothing */ /* Only on GM965/G965 */ if (p->devinfo->has_negative_rhw_bug) { - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0)); - brw_IF(p, BRW_EXECUTE_1); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_L, c->reg.dp0, elk_imm_f(0.0)); + elk_IF(p, ELK_EXECUTE_1); } { - brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1)); - brw_math_invert(p, c->reg.t, c->reg.t); - brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0); + elk_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1)); + elk_math_invert(p, c->reg.t, c->reg.t); + elk_MUL(p, c->reg.t, c->reg.t, c->reg.dp0); - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 ); - brw_MOV(p, c->reg.t0, c->reg.t); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, - BRW_PREDICATE_NORMAL); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_G, c->reg.t, c->reg.t0 ); + elk_MOV(p, c->reg.t0, c->reg.t); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, + ELK_PREDICATE_NORMAL); } if (p->devinfo->has_negative_rhw_bug) { - brw_ENDIF(p); + elk_ENDIF(p); } } - brw_ENDIF(p); + elk_ENDIF(p); } - brw_ENDIF(p); + elk_ENDIF(p); /* plane_ptr++; */ - brw_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), brw_clip_plane_stride(c)); + elk_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), elk_clip_plane_stride(c)); /* while (planemask>>=1) != 0 */ - brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, brw_imm_ud(1)); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); - brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, brw_imm_w(sizeof(float))); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_SHR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud(1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, elk_imm_ud(1)); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); + elk_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, elk_imm_w(sizeof(float))); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); } - brw_WHILE(p); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_WHILE(p); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); - brw_ADD(p, c->reg.t, c->reg.t0, c->reg.t1); - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.t, brw_imm_f(1.0)); - brw_IF(p, BRW_EXECUTE_1); + elk_ADD(p, c->reg.t, c->reg.t0, c->reg.t1); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_L, c->reg.t, elk_imm_f(1.0)); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, false); - brw_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, false); + elk_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, false); + elk_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, false); - brw_clip_emit_vue(c, newvtx0, BRW_URB_WRITE_ALLOCATE_COMPLETE, + elk_clip_emit_vue(c, newvtx0, ELK_URB_WRITE_ALLOCATE_COMPLETE, (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START); - brw_clip_emit_vue(c, newvtx1, BRW_URB_WRITE_EOT_COMPLETE, + elk_clip_emit_vue(c, newvtx1, ELK_URB_WRITE_EOT_COMPLETE, (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END); } - brw_ENDIF(p); - brw_clip_kill_thread(c); + elk_ENDIF(p); + elk_clip_kill_thread(c); } -void brw_emit_line_clip( struct brw_clip_compile *c ) +void elk_emit_line_clip( struct elk_clip_compile *c ) { - brw_clip_line_alloc_regs(c); - brw_clip_init_ff_sync(c); + elk_clip_line_alloc_regs(c); + elk_clip_init_ff_sync(c); if (c->key.contains_flat_varying) { if (c->key.pv_first) - brw_clip_copy_flatshaded_attributes(c, 1, 0); + elk_clip_copy_flatshaded_attributes(c, 1, 0); else - brw_clip_copy_flatshaded_attributes(c, 0, 1); + elk_clip_copy_flatshaded_attributes(c, 0, 1); } clip_and_emit_line(c); diff --git a/src/intel/compiler/elk/elk_clip_point.c b/src/intel/compiler/elk/elk_clip_point.c index 04a8be61d1c..9f462147da3 100644 --- a/src/intel/compiler/elk/elk_clip_point.c +++ b/src/intel/compiler/elk/elk_clip_point.c @@ -34,12 +34,12 @@ /* Point clipping, nothing to do? */ -void brw_emit_point_clip( struct brw_clip_compile *c ) +void elk_emit_point_clip( struct elk_clip_compile *c ) { /* Send an empty message to kill the thread: */ - brw_clip_tri_alloc_regs(c, 0); - brw_clip_init_ff_sync(c); + elk_clip_tri_alloc_regs(c, 0); + elk_clip_init_ff_sync(c); - brw_clip_kill_thread(c); + elk_clip_kill_thread(c); } diff --git a/src/intel/compiler/elk/elk_clip_tri.c b/src/intel/compiler/elk/elk_clip_tri.c index f645776ef5c..5aea21060bf 100644 --- a/src/intel/compiler/elk/elk_clip_tri.c +++ b/src/intel/compiler/elk/elk_clip_tri.c @@ -32,13 +32,13 @@ #include "elk_clip.h" #include "elk_prim.h" -static void release_tmps( struct brw_clip_compile *c ) +static void release_tmps( struct elk_clip_compile *c ) { c->last_tmp = c->first_tmp; } -void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, +void elk_clip_tri_alloc_regs( struct elk_clip_compile *c, GLuint nr_verts ) { const struct intel_device_info *devinfo = c->func.devinfo; @@ -46,10 +46,10 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, /* Register usage is static, precompute here: */ - c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; + c->reg.R0 = retype(elk_vec8_grf(i, 0), ELK_REGISTER_TYPE_UD); i++; if (c->key.nr_userclip) { - c->reg.fixed_planes = brw_vec4_grf(i, 0); + c->reg.fixed_planes = elk_vec4_grf(i, 0); i += (6 + c->key.nr_userclip + 1) / 2; c->prog_data.curb_read_length = (6 + c->key.nr_userclip + 1) / 2; @@ -61,7 +61,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, /* Payload vertices plus space for more generated vertices: */ for (j = 0; j < nr_verts; j++) { - c->reg.vertex[j] = brw_vec4_grf(i, 0); + c->reg.vertex[j] = elk_vec4_grf(i, 0); i += c->nr_regs; } @@ -70,52 +70,52 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, * used. Fill the second half with zero. */ for (j = 0; j < 3; j++) { - GLuint delta = brw_vue_slot_to_offset(c->vue_map.num_slots); + GLuint delta = elk_vue_slot_to_offset(c->vue_map.num_slots); - brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0)); + elk_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), elk_imm_f(0)); } } - c->reg.t = brw_vec1_grf(i, 0); - c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D); - c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD); - c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); - c->reg.plane_equation = brw_vec4_grf(i, 4); + c->reg.t = elk_vec1_grf(i, 0); + c->reg.loopcount = retype(elk_vec1_grf(i, 1), ELK_REGISTER_TYPE_D); + c->reg.nr_verts = retype(elk_vec1_grf(i, 2), ELK_REGISTER_TYPE_UD); + c->reg.planemask = retype(elk_vec1_grf(i, 3), ELK_REGISTER_TYPE_UD); + c->reg.plane_equation = elk_vec4_grf(i, 4); i++; - c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ - c->reg.dp = brw_vec1_grf(i, 4); + c->reg.dpPrev = elk_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ + c->reg.dp = elk_vec1_grf(i, 4); i++; - c->reg.inlist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0); + c->reg.inlist = elk_uw16_reg(ELK_GENERAL_REGISTER_FILE, i, 0); i++; - c->reg.outlist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0); + c->reg.outlist = elk_uw16_reg(ELK_GENERAL_REGISTER_FILE, i, 0); i++; - c->reg.freelist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0); + c->reg.freelist = elk_uw16_reg(ELK_GENERAL_REGISTER_FILE, i, 0); i++; if (!c->key.nr_userclip) { - c->reg.fixed_planes = brw_vec8_grf(i, 0); + c->reg.fixed_planes = elk_vec8_grf(i, 0); i++; } if (c->key.do_unfilled) { - c->reg.dir = brw_vec4_grf(i, 0); - c->reg.offset = brw_vec4_grf(i, 4); + c->reg.dir = elk_vec4_grf(i, 0); + c->reg.offset = elk_vec4_grf(i, 4); i++; - c->reg.tmp0 = brw_vec4_grf(i, 0); - c->reg.tmp1 = brw_vec4_grf(i, 4); + c->reg.tmp0 = elk_vec4_grf(i, 0); + c->reg.tmp1 = elk_vec4_grf(i, 4); i++; } - c->reg.vertex_src_mask = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); - c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W); + c->reg.vertex_src_mask = retype(elk_vec1_grf(i, 0), ELK_REGISTER_TYPE_UD); + c->reg.clipdistance_offset = retype(elk_vec1_grf(i, 1), ELK_REGISTER_TYPE_W); i++; if (devinfo->ver == 5) { - c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); + c->reg.ff_sync = retype(elk_vec1_grf(i, 0), ELK_REGISTER_TYPE_UD); i++; } @@ -128,89 +128,89 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, -void brw_clip_tri_init_vertices( struct brw_clip_compile *c ) +void elk_clip_tri_init_vertices( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */ + struct elk_codegen *p = &c->func; + struct elk_reg tmp0 = c->reg.loopcount; /* handy temporary */ /* Initial list of indices for incoming vertices: */ - brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK)); - brw_CMP(p, - vec1(brw_null_reg()), - BRW_CONDITIONAL_EQ, + elk_AND(p, tmp0, get_element_ud(c->reg.R0, 2), elk_imm_ud(PRIM_MASK)); + elk_CMP(p, + vec1(elk_null_reg()), + ELK_CONDITIONAL_EQ, tmp0, - brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE)); + elk_imm_ud(_3DPRIM_TRISTRIP_REVERSE)); /* XXX: Is there an easier way to do this? Need to reverse every * second tristrip element: Can ignore sometimes? */ - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { - brw_MOV(p, get_element(c->reg.inlist, 0), brw_address(c->reg.vertex[1]) ); - brw_MOV(p, get_element(c->reg.inlist, 1), brw_address(c->reg.vertex[0]) ); + elk_MOV(p, get_element(c->reg.inlist, 0), elk_address(c->reg.vertex[1]) ); + elk_MOV(p, get_element(c->reg.inlist, 1), elk_address(c->reg.vertex[0]) ); if (c->need_direction) - brw_MOV(p, c->reg.dir, brw_imm_f(-1)); + elk_MOV(p, c->reg.dir, elk_imm_f(-1)); } - brw_ELSE(p); + elk_ELSE(p); { - brw_MOV(p, get_element(c->reg.inlist, 0), brw_address(c->reg.vertex[0]) ); - brw_MOV(p, get_element(c->reg.inlist, 1), brw_address(c->reg.vertex[1]) ); + elk_MOV(p, get_element(c->reg.inlist, 0), elk_address(c->reg.vertex[0]) ); + elk_MOV(p, get_element(c->reg.inlist, 1), elk_address(c->reg.vertex[1]) ); if (c->need_direction) - brw_MOV(p, c->reg.dir, brw_imm_f(1)); + elk_MOV(p, c->reg.dir, elk_imm_f(1)); } - brw_ENDIF(p); + elk_ENDIF(p); - brw_MOV(p, get_element(c->reg.inlist, 2), brw_address(c->reg.vertex[2]) ); - brw_MOV(p, brw_vec8_grf(c->reg.outlist.nr, 0), brw_imm_f(0)); - brw_MOV(p, c->reg.nr_verts, brw_imm_ud(3)); + elk_MOV(p, get_element(c->reg.inlist, 2), elk_address(c->reg.vertex[2]) ); + elk_MOV(p, elk_vec8_grf(c->reg.outlist.nr, 0), elk_imm_f(0)); + elk_MOV(p, c->reg.nr_verts, elk_imm_ud(3)); } -void brw_clip_tri_flat_shade( struct brw_clip_compile *c ) +void elk_clip_tri_flat_shade( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */ + struct elk_codegen *p = &c->func; + struct elk_reg tmp0 = c->reg.loopcount; /* handy temporary */ - brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK)); - brw_CMP(p, - vec1(brw_null_reg()), - BRW_CONDITIONAL_EQ, + elk_AND(p, tmp0, get_element_ud(c->reg.R0, 2), elk_imm_ud(PRIM_MASK)); + elk_CMP(p, + vec1(elk_null_reg()), + ELK_CONDITIONAL_EQ, tmp0, - brw_imm_ud(_3DPRIM_POLYGON)); + elk_imm_ud(_3DPRIM_POLYGON)); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_copy_flatshaded_attributes(c, 1, 0); - brw_clip_copy_flatshaded_attributes(c, 2, 0); + elk_clip_copy_flatshaded_attributes(c, 1, 0); + elk_clip_copy_flatshaded_attributes(c, 2, 0); } - brw_ELSE(p); + elk_ELSE(p); { if (c->key.pv_first) { - brw_CMP(p, - vec1(brw_null_reg()), - BRW_CONDITIONAL_EQ, + elk_CMP(p, + vec1(elk_null_reg()), + ELK_CONDITIONAL_EQ, tmp0, - brw_imm_ud(_3DPRIM_TRIFAN)); - brw_IF(p, BRW_EXECUTE_1); + elk_imm_ud(_3DPRIM_TRIFAN)); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_copy_flatshaded_attributes(c, 0, 1); - brw_clip_copy_flatshaded_attributes(c, 2, 1); + elk_clip_copy_flatshaded_attributes(c, 0, 1); + elk_clip_copy_flatshaded_attributes(c, 2, 1); } - brw_ELSE(p); + elk_ELSE(p); { - brw_clip_copy_flatshaded_attributes(c, 1, 0); - brw_clip_copy_flatshaded_attributes(c, 2, 0); + elk_clip_copy_flatshaded_attributes(c, 1, 0); + elk_clip_copy_flatshaded_attributes(c, 2, 0); } - brw_ENDIF(p); + elk_ENDIF(p); } else { - brw_clip_copy_flatshaded_attributes(c, 0, 2); - brw_clip_copy_flatshaded_attributes(c, 1, 2); + elk_clip_copy_flatshaded_attributes(c, 0, 2); + elk_clip_copy_flatshaded_attributes(c, 1, 2); } } - brw_ENDIF(p); + elk_ENDIF(p); } @@ -222,438 +222,438 @@ void brw_clip_tri_flat_shade( struct brw_clip_compile *c ) * - If using a user clip plane, the distance is directly available in the vertex. */ static inline void -load_clip_distance(struct brw_clip_compile *c, struct brw_indirect vtx, - struct brw_reg dst, GLuint hpos_offset, int cond) +load_clip_distance(struct elk_clip_compile *c, struct elk_indirect vtx, + struct elk_reg dst, GLuint hpos_offset, int cond) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; dst = vec4(dst); - brw_AND(p, vec1(brw_null_reg()), c->reg.vertex_src_mask, brw_imm_ud(1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_IF(p, BRW_EXECUTE_1); + elk_AND(p, vec1(elk_null_reg()), c->reg.vertex_src_mask, elk_imm_ud(1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_IF(p, ELK_EXECUTE_1); { - struct brw_indirect temp_ptr = brw_indirect(7, 0); - brw_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx), c->reg.clipdistance_offset); - brw_MOV(p, vec1(dst), deref_1f(temp_ptr, 0)); + struct elk_indirect temp_ptr = elk_indirect(7, 0); + elk_ADD(p, get_addr_reg(temp_ptr), get_addr_reg(vtx), c->reg.clipdistance_offset); + elk_MOV(p, vec1(dst), deref_1f(temp_ptr, 0)); } - brw_ELSE(p); + elk_ELSE(p); { - brw_MOV(p, dst, deref_4f(vtx, hpos_offset)); - brw_DP4(p, dst, dst, c->reg.plane_equation); + elk_MOV(p, dst, deref_4f(vtx, hpos_offset)); + elk_DP4(p, dst, dst, c->reg.plane_equation); } - brw_ENDIF(p); + elk_ENDIF(p); - brw_CMP(p, brw_null_reg(), cond, vec1(dst), brw_imm_f(0.0f)); + elk_CMP(p, elk_null_reg(), cond, vec1(dst), elk_imm_f(0.0f)); } /* Use mesa's clipping algorithms, translated to GFX4 assembly. */ -void brw_clip_tri( struct brw_clip_compile *c ) +void elk_clip_tri( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_indirect vtx = brw_indirect(0, 0); - struct brw_indirect vtxPrev = brw_indirect(1, 0); - struct brw_indirect vtxOut = brw_indirect(2, 0); - struct brw_indirect plane_ptr = brw_indirect(3, 0); - struct brw_indirect inlist_ptr = brw_indirect(4, 0); - struct brw_indirect outlist_ptr = brw_indirect(5, 0); - struct brw_indirect freelist_ptr = brw_indirect(6, 0); - GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); + struct elk_codegen *p = &c->func; + struct elk_indirect vtx = elk_indirect(0, 0); + struct elk_indirect vtxPrev = elk_indirect(1, 0); + struct elk_indirect vtxOut = elk_indirect(2, 0); + struct elk_indirect plane_ptr = elk_indirect(3, 0); + struct elk_indirect inlist_ptr = elk_indirect(4, 0); + struct elk_indirect outlist_ptr = elk_indirect(5, 0); + struct elk_indirect freelist_ptr = elk_indirect(6, 0); + GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); GLint clipdist0_offset = c->key.nr_userclip - ? brw_varying_to_offset(&c->vue_map, VARYING_SLOT_CLIP_DIST0) + ? elk_varying_to_offset(&c->vue_map, VARYING_SLOT_CLIP_DIST0) : 0; - brw_MOV(p, get_addr_reg(vtxPrev), brw_address(c->reg.vertex[2]) ); - brw_MOV(p, get_addr_reg(plane_ptr), brw_clip_plane0_address(c)); - brw_MOV(p, get_addr_reg(inlist_ptr), brw_address(c->reg.inlist)); - brw_MOV(p, get_addr_reg(outlist_ptr), brw_address(c->reg.outlist)); + elk_MOV(p, get_addr_reg(vtxPrev), elk_address(c->reg.vertex[2]) ); + elk_MOV(p, get_addr_reg(plane_ptr), elk_clip_plane0_address(c)); + elk_MOV(p, get_addr_reg(inlist_ptr), elk_address(c->reg.inlist)); + elk_MOV(p, get_addr_reg(outlist_ptr), elk_address(c->reg.outlist)); - brw_MOV(p, get_addr_reg(freelist_ptr), brw_address(c->reg.vertex[3]) ); + elk_MOV(p, get_addr_reg(freelist_ptr), elk_address(c->reg.vertex[3]) ); /* Set the initial vertex source mask: The first 6 planes are the bounds * of the view volume; the next 8 planes are the user clipping planes. */ - brw_MOV(p, c->reg.vertex_src_mask, brw_imm_ud(0x3fc0)); + elk_MOV(p, c->reg.vertex_src_mask, elk_imm_ud(0x3fc0)); /* Set the initial clipdistance offset to be 6 floats before gl_ClipDistance[0]. * We'll increment 6 times before we start hitting actual user clipping. */ - brw_MOV(p, c->reg.clipdistance_offset, brw_imm_d(clipdist0_offset - 6*sizeof(float))); + elk_MOV(p, c->reg.clipdistance_offset, elk_imm_d(clipdist0_offset - 6*sizeof(float))); - brw_DO(p, BRW_EXECUTE_1); + elk_DO(p, ELK_EXECUTE_1); { /* if (planemask & 1) */ - brw_AND(p, vec1(brw_null_reg()), c->reg.planemask, brw_imm_ud(1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); + elk_AND(p, vec1(elk_null_reg()), c->reg.planemask, elk_imm_ud(1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { /* vtxOut = freelist_ptr++ */ - brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(freelist_ptr) ); - brw_ADD(p, get_addr_reg(freelist_ptr), get_addr_reg(freelist_ptr), brw_imm_uw(c->nr_regs * REG_SIZE)); + elk_MOV(p, get_addr_reg(vtxOut), get_addr_reg(freelist_ptr) ); + elk_ADD(p, get_addr_reg(freelist_ptr), get_addr_reg(freelist_ptr), elk_imm_uw(c->nr_regs * REG_SIZE)); if (c->key.nr_userclip) - brw_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0)); + elk_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0)); else - brw_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0)); + elk_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0)); - brw_MOV(p, c->reg.loopcount, c->reg.nr_verts); - brw_MOV(p, c->reg.nr_verts, brw_imm_ud(0)); + elk_MOV(p, c->reg.loopcount, c->reg.nr_verts); + elk_MOV(p, c->reg.nr_verts, elk_imm_ud(0)); - brw_DO(p, BRW_EXECUTE_1); + elk_DO(p, ELK_EXECUTE_1); { /* vtx = *input_ptr; */ - brw_MOV(p, get_addr_reg(vtx), deref_1uw(inlist_ptr, 0)); + elk_MOV(p, get_addr_reg(vtx), deref_1uw(inlist_ptr, 0)); - load_clip_distance(c, vtxPrev, c->reg.dpPrev, hpos_offset, BRW_CONDITIONAL_L); + load_clip_distance(c, vtxPrev, c->reg.dpPrev, hpos_offset, ELK_CONDITIONAL_L); /* (prev < 0.0f) */ - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { - load_clip_distance(c, vtx, c->reg.dp, hpos_offset, BRW_CONDITIONAL_GE); + load_clip_distance(c, vtx, c->reg.dp, hpos_offset, ELK_CONDITIONAL_GE); /* IS_POSITIVE(next) */ - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { /* Coming back in. */ - brw_ADD(p, c->reg.t, c->reg.dpPrev, negate(c->reg.dp)); - brw_math_invert(p, c->reg.t, c->reg.t); - brw_MUL(p, c->reg.t, c->reg.t, c->reg.dpPrev); + elk_ADD(p, c->reg.t, c->reg.dpPrev, negate(c->reg.dp)); + elk_math_invert(p, c->reg.t, c->reg.t); + elk_MUL(p, c->reg.t, c->reg.t, c->reg.dpPrev); /* If (vtxOut == 0) vtxOut = vtxPrev */ - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, get_addr_reg(vtxOut), brw_imm_uw(0) ); - brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtxPrev)); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, - BRW_PREDICATE_NORMAL); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_EQ, get_addr_reg(vtxOut), elk_imm_uw(0) ); + elk_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtxPrev)); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, + ELK_PREDICATE_NORMAL); - brw_clip_interp_vertex(c, vtxOut, vtxPrev, vtx, c->reg.t, false); + elk_clip_interp_vertex(c, vtxOut, vtxPrev, vtx, c->reg.t, false); /* *outlist_ptr++ = vtxOut; * nr_verts++; * vtxOut = 0; */ - brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut)); - brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short))); - brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1)); - brw_MOV(p, get_addr_reg(vtxOut), brw_imm_uw(0) ); + elk_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut)); + elk_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), elk_imm_uw(sizeof(short))); + elk_ADD(p, c->reg.nr_verts, c->reg.nr_verts, elk_imm_ud(1)); + elk_MOV(p, get_addr_reg(vtxOut), elk_imm_uw(0) ); } - brw_ENDIF(p); + elk_ENDIF(p); } - brw_ELSE(p); + elk_ELSE(p); { /* *outlist_ptr++ = vtxPrev; * nr_verts++; */ - brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxPrev)); - brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short))); - brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1)); + elk_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxPrev)); + elk_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), elk_imm_uw(sizeof(short))); + elk_ADD(p, c->reg.nr_verts, c->reg.nr_verts, elk_imm_ud(1)); - load_clip_distance(c, vtx, c->reg.dp, hpos_offset, BRW_CONDITIONAL_L); + load_clip_distance(c, vtx, c->reg.dp, hpos_offset, ELK_CONDITIONAL_L); /* (next < 0.0f) */ - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { /* Going out of bounds. Avoid division by zero as we * know dp != dpPrev from DIFFERENT_SIGNS, above. */ - brw_ADD(p, c->reg.t, c->reg.dp, negate(c->reg.dpPrev)); - brw_math_invert(p, c->reg.t, c->reg.t); - brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp); + elk_ADD(p, c->reg.t, c->reg.dp, negate(c->reg.dpPrev)); + elk_math_invert(p, c->reg.t, c->reg.t); + elk_MUL(p, c->reg.t, c->reg.t, c->reg.dp); /* If (vtxOut == 0) vtxOut = vtx */ - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, get_addr_reg(vtxOut), brw_imm_uw(0) ); - brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtx)); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, - BRW_PREDICATE_NORMAL); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_EQ, get_addr_reg(vtxOut), elk_imm_uw(0) ); + elk_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtx)); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, + ELK_PREDICATE_NORMAL); - brw_clip_interp_vertex(c, vtxOut, vtx, vtxPrev, c->reg.t, true); + elk_clip_interp_vertex(c, vtxOut, vtx, vtxPrev, c->reg.t, true); /* *outlist_ptr++ = vtxOut; * nr_verts++; * vtxOut = 0; */ - brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut)); - brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short))); - brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1)); - brw_MOV(p, get_addr_reg(vtxOut), brw_imm_uw(0) ); + elk_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut)); + elk_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), elk_imm_uw(sizeof(short))); + elk_ADD(p, c->reg.nr_verts, c->reg.nr_verts, elk_imm_ud(1)); + elk_MOV(p, get_addr_reg(vtxOut), elk_imm_uw(0) ); } - brw_ENDIF(p); + elk_ENDIF(p); } - brw_ENDIF(p); + elk_ENDIF(p); /* vtxPrev = vtx; * inlist_ptr++; */ - brw_MOV(p, get_addr_reg(vtxPrev), get_addr_reg(vtx)); - brw_ADD(p, get_addr_reg(inlist_ptr), get_addr_reg(inlist_ptr), brw_imm_uw(sizeof(short))); + elk_MOV(p, get_addr_reg(vtxPrev), get_addr_reg(vtx)); + elk_ADD(p, get_addr_reg(inlist_ptr), get_addr_reg(inlist_ptr), elk_imm_uw(sizeof(short))); /* while (--loopcount != 0) */ - brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); + elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); } - brw_WHILE(p); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_WHILE(p); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); /* vtxPrev = *(outlist_ptr-1) OR: outlist[nr_verts-1] * inlist = outlist * inlist_ptr = &inlist[0] * outlist_ptr = &outlist[0] */ - brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_w(-2)); - brw_MOV(p, get_addr_reg(vtxPrev), deref_1uw(outlist_ptr, 0)); - brw_MOV(p, brw_vec8_grf(c->reg.inlist.nr, 0), brw_vec8_grf(c->reg.outlist.nr, 0)); - brw_MOV(p, get_addr_reg(inlist_ptr), brw_address(c->reg.inlist)); - brw_MOV(p, get_addr_reg(outlist_ptr), brw_address(c->reg.outlist)); + elk_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), elk_imm_w(-2)); + elk_MOV(p, get_addr_reg(vtxPrev), deref_1uw(outlist_ptr, 0)); + elk_MOV(p, elk_vec8_grf(c->reg.inlist.nr, 0), elk_vec8_grf(c->reg.outlist.nr, 0)); + elk_MOV(p, get_addr_reg(inlist_ptr), elk_address(c->reg.inlist)); + elk_MOV(p, get_addr_reg(outlist_ptr), elk_address(c->reg.outlist)); } - brw_ENDIF(p); + elk_ENDIF(p); /* plane_ptr++; */ - brw_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), brw_clip_plane_stride(c)); + elk_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), elk_clip_plane_stride(c)); /* nr_verts >= 3 */ - brw_CMP(p, - vec1(brw_null_reg()), - BRW_CONDITIONAL_GE, + elk_CMP(p, + vec1(elk_null_reg()), + ELK_CONDITIONAL_GE, c->reg.nr_verts, - brw_imm_ud(3)); - brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); + elk_imm_ud(3)); + elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL); /* && (planemask>>=1) != 0 */ - brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, brw_imm_ud(1)); - brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, brw_imm_w(sizeof(float))); + elk_SHR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud(1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, elk_imm_ud(1)); + elk_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, elk_imm_w(sizeof(float))); } - brw_WHILE(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_WHILE(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); } -void brw_clip_tri_emit_polygon(struct brw_clip_compile *c) +void elk_clip_tri_emit_polygon(struct elk_clip_compile *c) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; /* for (loopcount = nr_verts-2; loopcount > 0; loopcount--) */ - brw_ADD(p, + elk_ADD(p, c->reg.loopcount, c->reg.nr_verts, - brw_imm_d(-2)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_G); + elk_imm_d(-2)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_G); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { - struct brw_indirect v0 = brw_indirect(0, 0); - struct brw_indirect vptr = brw_indirect(1, 0); + struct elk_indirect v0 = elk_indirect(0, 0); + struct elk_indirect vptr = elk_indirect(1, 0); - brw_MOV(p, get_addr_reg(vptr), brw_address(c->reg.inlist)); - brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); + elk_MOV(p, get_addr_reg(vptr), elk_address(c->reg.inlist)); + elk_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); - brw_clip_emit_vue(c, v0, BRW_URB_WRITE_ALLOCATE_COMPLETE, + elk_clip_emit_vue(c, v0, ELK_URB_WRITE_ALLOCATE_COMPLETE, ((_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START)); - brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2)); - brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); + elk_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), elk_imm_uw(2)); + elk_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); - brw_DO(p, BRW_EXECUTE_1); + elk_DO(p, ELK_EXECUTE_1); { - brw_clip_emit_vue(c, v0, BRW_URB_WRITE_ALLOCATE_COMPLETE, + elk_clip_emit_vue(c, v0, ELK_URB_WRITE_ALLOCATE_COMPLETE, (_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT)); - brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2)); - brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); + elk_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), elk_imm_uw(2)); + elk_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); - brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); + elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); } - brw_WHILE(p); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_WHILE(p); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); - brw_clip_emit_vue(c, v0, BRW_URB_WRITE_EOT_COMPLETE, + elk_clip_emit_vue(c, v0, ELK_URB_WRITE_EOT_COMPLETE, ((_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); } - brw_ENDIF(p); + elk_ENDIF(p); } -static void do_clip_tri( struct brw_clip_compile *c ) +static void do_clip_tri( struct elk_clip_compile *c ) { - brw_clip_init_planes(c); + elk_clip_init_planes(c); - brw_clip_tri(c); + elk_clip_tri(c); } -static void maybe_do_clip_tri( struct brw_clip_compile *c ) +static void maybe_do_clip_tri( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, c->reg.planemask, brw_imm_ud(0)); - brw_IF(p, BRW_EXECUTE_1); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_NZ, c->reg.planemask, elk_imm_ud(0)); + elk_IF(p, ELK_EXECUTE_1); { do_clip_tri(c); } - brw_ENDIF(p); + elk_ENDIF(p); } -static void brw_clip_test( struct brw_clip_compile *c ) +static void elk_clip_test( struct elk_clip_compile *c ) { - struct brw_reg t = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); - struct brw_reg t1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); - struct brw_reg t2 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); - struct brw_reg t3 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); + struct elk_reg t = retype(get_tmp(c), ELK_REGISTER_TYPE_UD); + struct elk_reg t1 = retype(get_tmp(c), ELK_REGISTER_TYPE_UD); + struct elk_reg t2 = retype(get_tmp(c), ELK_REGISTER_TYPE_UD); + struct elk_reg t3 = retype(get_tmp(c), ELK_REGISTER_TYPE_UD); - struct brw_reg v0 = get_tmp(c); - struct brw_reg v1 = get_tmp(c); - struct brw_reg v2 = get_tmp(c); + struct elk_reg v0 = get_tmp(c); + struct elk_reg v1 = get_tmp(c); + struct elk_reg v2 = get_tmp(c); - struct brw_indirect vt0 = brw_indirect(0, 0); - struct brw_indirect vt1 = brw_indirect(1, 0); - struct brw_indirect vt2 = brw_indirect(2, 0); + struct elk_indirect vt0 = elk_indirect(0, 0); + struct elk_indirect vt1 = elk_indirect(1, 0); + struct elk_indirect vt2 = elk_indirect(2, 0); - struct brw_codegen *p = &c->func; - struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */ + struct elk_codegen *p = &c->func; + struct elk_reg tmp0 = c->reg.loopcount; /* handy temporary */ - GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, + GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); - brw_MOV(p, get_addr_reg(vt0), brw_address(c->reg.vertex[0])); - brw_MOV(p, get_addr_reg(vt1), brw_address(c->reg.vertex[1])); - brw_MOV(p, get_addr_reg(vt2), brw_address(c->reg.vertex[2])); - brw_MOV(p, v0, deref_4f(vt0, hpos_offset)); - brw_MOV(p, v1, deref_4f(vt1, hpos_offset)); - brw_MOV(p, v2, deref_4f(vt2, hpos_offset)); - brw_AND(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(~0x3f)); + elk_MOV(p, get_addr_reg(vt0), elk_address(c->reg.vertex[0])); + elk_MOV(p, get_addr_reg(vt1), elk_address(c->reg.vertex[1])); + elk_MOV(p, get_addr_reg(vt2), elk_address(c->reg.vertex[2])); + elk_MOV(p, v0, deref_4f(vt0, hpos_offset)); + elk_MOV(p, v1, deref_4f(vt1, hpos_offset)); + elk_MOV(p, v2, deref_4f(vt2, hpos_offset)); + elk_AND(p, c->reg.planemask, c->reg.planemask, elk_imm_ud(~0x3f)); /* test nearz, xmin, ymin plane */ /* clip.xyz < -clip.w */ - brw_CMP(p, t1, BRW_CONDITIONAL_L, v0, negate(get_element(v0, 3))); - brw_CMP(p, t2, BRW_CONDITIONAL_L, v1, negate(get_element(v1, 3))); - brw_CMP(p, t3, BRW_CONDITIONAL_L, v2, negate(get_element(v2, 3))); + elk_CMP(p, t1, ELK_CONDITIONAL_L, v0, negate(get_element(v0, 3))); + elk_CMP(p, t2, ELK_CONDITIONAL_L, v1, negate(get_element(v1, 3))); + elk_CMP(p, t3, ELK_CONDITIONAL_L, v2, negate(get_element(v2, 3))); /* All vertices are outside of a plane, rejected */ - brw_AND(p, t, t1, t2); - brw_AND(p, t, t, t3); - brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1)); - brw_OR(p, tmp0, tmp0, get_element(t, 2)); - brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_IF(p, BRW_EXECUTE_1); + elk_AND(p, t, t1, t2); + elk_AND(p, t, t, t3); + elk_OR(p, tmp0, get_element(t, 0), get_element(t, 1)); + elk_OR(p, tmp0, tmp0, get_element(t, 2)); + elk_AND(p, elk_null_reg(), tmp0, elk_imm_ud(0x1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_kill_thread(c); + elk_clip_kill_thread(c); } - brw_ENDIF(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_ENDIF(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); /* some vertices are inside a plane, some are outside,need to clip */ - brw_XOR(p, t, t1, t2); - brw_XOR(p, t1, t2, t3); - brw_OR(p, t, t, t1); - brw_AND(p, t, t, brw_imm_ud(0x1)); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, - get_element(t, 0), brw_imm_ud(0)); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<5))); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, - get_element(t, 1), brw_imm_ud(0)); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<3))); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, - get_element(t, 2), brw_imm_ud(0)); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<1))); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_XOR(p, t, t1, t2); + elk_XOR(p, t1, t2, t3); + elk_OR(p, t, t, t1); + elk_AND(p, t, t, elk_imm_ud(0x1)); + elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ, + get_element(t, 0), elk_imm_ud(0)); + elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<5))); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); + elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ, + get_element(t, 1), elk_imm_ud(0)); + elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<3))); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); + elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ, + get_element(t, 2), elk_imm_ud(0)); + elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<1))); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); /* test farz, xmax, ymax plane */ /* clip.xyz > clip.w */ - brw_CMP(p, t1, BRW_CONDITIONAL_G, v0, get_element(v0, 3)); - brw_CMP(p, t2, BRW_CONDITIONAL_G, v1, get_element(v1, 3)); - brw_CMP(p, t3, BRW_CONDITIONAL_G, v2, get_element(v2, 3)); + elk_CMP(p, t1, ELK_CONDITIONAL_G, v0, get_element(v0, 3)); + elk_CMP(p, t2, ELK_CONDITIONAL_G, v1, get_element(v1, 3)); + elk_CMP(p, t3, ELK_CONDITIONAL_G, v2, get_element(v2, 3)); /* All vertices are outside of a plane, rejected */ - brw_AND(p, t, t1, t2); - brw_AND(p, t, t, t3); - brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1)); - brw_OR(p, tmp0, tmp0, get_element(t, 2)); - brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_IF(p, BRW_EXECUTE_1); + elk_AND(p, t, t1, t2); + elk_AND(p, t, t, t3); + elk_OR(p, tmp0, get_element(t, 0), get_element(t, 1)); + elk_OR(p, tmp0, tmp0, get_element(t, 2)); + elk_AND(p, elk_null_reg(), tmp0, elk_imm_ud(0x1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_kill_thread(c); + elk_clip_kill_thread(c); } - brw_ENDIF(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_ENDIF(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); /* some vertices are inside a plane, some are outside,need to clip */ - brw_XOR(p, t, t1, t2); - brw_XOR(p, t1, t2, t3); - brw_OR(p, t, t, t1); - brw_AND(p, t, t, brw_imm_ud(0x1)); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, - get_element(t, 0), brw_imm_ud(0)); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<4))); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, - get_element(t, 1), brw_imm_ud(0)); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<2))); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, - get_element(t, 2), brw_imm_ud(0)); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<0))); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_XOR(p, t, t1, t2); + elk_XOR(p, t1, t2, t3); + elk_OR(p, t, t, t1); + elk_AND(p, t, t, elk_imm_ud(0x1)); + elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ, + get_element(t, 0), elk_imm_ud(0)); + elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<4))); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); + elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ, + get_element(t, 1), elk_imm_ud(0)); + elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<2))); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); + elk_CMP(p, elk_null_reg(), ELK_CONDITIONAL_NZ, + get_element(t, 2), elk_imm_ud(0)); + elk_OR(p, c->reg.planemask, c->reg.planemask, elk_imm_ud((1<<0))); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); release_tmps(c); } -void brw_emit_tri_clip( struct brw_clip_compile *c ) +void elk_emit_tri_clip( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6); - brw_clip_tri_init_vertices(c); - brw_clip_init_clipmask(c); - brw_clip_init_ff_sync(c); + struct elk_codegen *p = &c->func; + elk_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6); + elk_clip_tri_init_vertices(c); + elk_clip_init_clipmask(c); + elk_clip_init_ff_sync(c); /* if -ve rhw workaround bit is set, do cliptest */ if (p->devinfo->has_negative_rhw_bug) { - brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), - brw_imm_ud(1<<20)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_IF(p, BRW_EXECUTE_1); + elk_AND(p, elk_null_reg(), get_element_ud(c->reg.R0, 2), + elk_imm_ud(1<<20)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_test(c); + elk_clip_test(c); } - brw_ENDIF(p); + elk_ENDIF(p); } /* Can't push into do_clip_tri because with polygon (or quad) * flatshading, need to apply the flatshade here because we don't * respect the PV when converting to trifan for emit: */ if (c->key.contains_flat_varying) - brw_clip_tri_flat_shade(c); + elk_clip_tri_flat_shade(c); - if ((c->key.clip_mode == BRW_CLIP_MODE_NORMAL) || - (c->key.clip_mode == BRW_CLIP_MODE_KERNEL_CLIP)) + if ((c->key.clip_mode == ELK_CLIP_MODE_NORMAL) || + (c->key.clip_mode == ELK_CLIP_MODE_KERNEL_CLIP)) do_clip_tri(c); else maybe_do_clip_tri(c); - brw_clip_tri_emit_polygon(c); + elk_clip_tri_emit_polygon(c); /* Send an empty message to kill the thread: */ - brw_clip_kill_thread(c); + elk_clip_kill_thread(c); } diff --git a/src/intel/compiler/elk/elk_clip_unfilled.c b/src/intel/compiler/elk/elk_clip_unfilled.c index 74e0dbc3705..0ef1122ccc1 100644 --- a/src/intel/compiler/elk/elk_clip_unfilled.c +++ b/src/intel/compiler/elk/elk_clip_unfilled.c @@ -37,20 +37,20 @@ * required: BZZZT! */ -static void compute_tri_direction( struct brw_clip_compile *c ) +static void compute_tri_direction( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_reg e = c->reg.tmp0; - struct brw_reg f = c->reg.tmp1; - GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); - struct brw_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset); - struct brw_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset); - struct brw_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset); + struct elk_codegen *p = &c->func; + struct elk_reg e = c->reg.tmp0; + struct elk_reg f = c->reg.tmp1; + GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); + struct elk_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset); + struct elk_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset); + struct elk_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset); - struct brw_reg v0n = get_tmp(c); - struct brw_reg v1n = get_tmp(c); - struct brw_reg v2n = get_tmp(c); + struct elk_reg v0n = get_tmp(c); + struct elk_reg v1n = get_tmp(c); + struct elk_reg v2n = get_tmp(c); /* Convert to NDC. * NOTE: We can't modify the original vertex coordinates, @@ -60,71 +60,71 @@ static void compute_tri_direction( struct brw_clip_compile *c ) * TBD-KC * Try to optimize unnecessary MOV's. */ - brw_MOV(p, v0n, v0); - brw_MOV(p, v1n, v1); - brw_MOV(p, v2n, v2); + elk_MOV(p, v0n, v0); + elk_MOV(p, v1n, v1); + elk_MOV(p, v2n, v2); - brw_clip_project_position(c, v0n); - brw_clip_project_position(c, v1n); - brw_clip_project_position(c, v2n); + elk_clip_project_position(c, v0n); + elk_clip_project_position(c, v1n); + elk_clip_project_position(c, v2n); /* Calculate the vectors of two edges of the triangle: */ - brw_ADD(p, e, v0n, negate(v2n)); - brw_ADD(p, f, v1n, negate(v2n)); + elk_ADD(p, e, v0n, negate(v2n)); + elk_ADD(p, f, v1n, negate(v2n)); /* Take their crossproduct: */ - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_MUL(p, vec4(brw_null_reg()), brw_swizzle(e, BRW_SWIZZLE_YZXW), - brw_swizzle(f, BRW_SWIZZLE_ZXYW)); - brw_MAC(p, vec4(e), negate(brw_swizzle(e, BRW_SWIZZLE_ZXYW)), - brw_swizzle(f, BRW_SWIZZLE_YZXW)); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_MUL(p, vec4(elk_null_reg()), elk_swizzle(e, ELK_SWIZZLE_YZXW), + elk_swizzle(f, ELK_SWIZZLE_ZXYW)); + elk_MAC(p, vec4(e), negate(elk_swizzle(e, ELK_SWIZZLE_ZXYW)), + elk_swizzle(f, ELK_SWIZZLE_YZXW)); + elk_set_default_access_mode(p, ELK_ALIGN_1); - brw_MUL(p, c->reg.dir, c->reg.dir, vec4(e)); + elk_MUL(p, c->reg.dir, c->reg.dir, vec4(e)); } -static void cull_direction( struct brw_clip_compile *c ) +static void cull_direction( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint conditional; - assert (!(c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL && - c->key.fill_cw == BRW_CLIP_FILL_MODE_CULL)); + assert (!(c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL && + c->key.fill_cw == ELK_CLIP_FILL_MODE_CULL)); - if (c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL) - conditional = BRW_CONDITIONAL_GE; + if (c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL) + conditional = ELK_CONDITIONAL_GE; else - conditional = BRW_CONDITIONAL_L; + conditional = ELK_CONDITIONAL_L; - brw_CMP(p, - vec1(brw_null_reg()), + elk_CMP(p, + vec1(elk_null_reg()), conditional, get_element(c->reg.dir, 2), - brw_imm_f(0)); + elk_imm_f(0)); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_kill_thread(c); + elk_clip_kill_thread(c); } - brw_ENDIF(p); + elk_ENDIF(p); } -static void copy_bfc( struct brw_clip_compile *c ) +static void copy_bfc( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint conditional; /* Do we have any colors to copy? */ - if (!(brw_clip_have_varying(c, VARYING_SLOT_COL0) && - brw_clip_have_varying(c, VARYING_SLOT_BFC0)) && - !(brw_clip_have_varying(c, VARYING_SLOT_COL1) && - brw_clip_have_varying(c, VARYING_SLOT_BFC1))) + if (!(elk_clip_have_varying(c, VARYING_SLOT_COL0) && + elk_clip_have_varying(c, VARYING_SLOT_BFC0)) && + !(elk_clip_have_varying(c, VARYING_SLOT_COL1) && + elk_clip_have_varying(c, VARYING_SLOT_BFC1))) return; /* In some weird degenerate cases we can end up testing the @@ -132,43 +132,43 @@ static void copy_bfc( struct brw_clip_compile *c ) * well, that's what you get for setting weird GL state. */ if (c->key.copy_bfc_ccw) - conditional = BRW_CONDITIONAL_GE; + conditional = ELK_CONDITIONAL_GE; else - conditional = BRW_CONDITIONAL_L; + conditional = ELK_CONDITIONAL_L; - brw_CMP(p, - vec1(brw_null_reg()), + elk_CMP(p, + vec1(elk_null_reg()), conditional, get_element(c->reg.dir, 2), - brw_imm_f(0)); + elk_imm_f(0)); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { GLuint i; for (i = 0; i < 3; i++) { - if (brw_clip_have_varying(c, VARYING_SLOT_COL0) && - brw_clip_have_varying(c, VARYING_SLOT_BFC0)) - brw_MOV(p, + if (elk_clip_have_varying(c, VARYING_SLOT_COL0) && + elk_clip_have_varying(c, VARYING_SLOT_BFC0)) + elk_MOV(p, byte_offset(c->reg.vertex[i], - brw_varying_to_offset(&c->vue_map, + elk_varying_to_offset(&c->vue_map, VARYING_SLOT_COL0)), byte_offset(c->reg.vertex[i], - brw_varying_to_offset(&c->vue_map, + elk_varying_to_offset(&c->vue_map, VARYING_SLOT_BFC0))); - if (brw_clip_have_varying(c, VARYING_SLOT_COL1) && - brw_clip_have_varying(c, VARYING_SLOT_BFC1)) - brw_MOV(p, + if (elk_clip_have_varying(c, VARYING_SLOT_COL1) && + elk_clip_have_varying(c, VARYING_SLOT_BFC1)) + elk_MOV(p, byte_offset(c->reg.vertex[i], - brw_varying_to_offset(&c->vue_map, + elk_varying_to_offset(&c->vue_map, VARYING_SLOT_COL1)), byte_offset(c->reg.vertex[i], - brw_varying_to_offset(&c->vue_map, + elk_varying_to_offset(&c->vue_map, VARYING_SLOT_BFC1))); } } - brw_ENDIF(p); + elk_ENDIF(p); } @@ -188,86 +188,86 @@ static void copy_bfc( struct brw_clip_compile *c ) } offset *= MRD; */ -static void compute_offset( struct brw_clip_compile *c ) +static void compute_offset( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_reg off = c->reg.offset; - struct brw_reg dir = c->reg.dir; + struct elk_codegen *p = &c->func; + struct elk_reg off = c->reg.offset; + struct elk_reg dir = c->reg.dir; - brw_math_invert(p, get_element(off, 2), get_element(dir, 2)); - brw_MUL(p, vec2(off), vec2(dir), get_element(off, 2)); + elk_math_invert(p, get_element(off, 2), get_element(dir, 2)); + elk_MUL(p, vec2(off), vec2(dir), get_element(off, 2)); - brw_CMP(p, - vec1(brw_null_reg()), - BRW_CONDITIONAL_GE, - brw_abs(get_element(off, 0)), - brw_abs(get_element(off, 1))); + elk_CMP(p, + vec1(elk_null_reg()), + ELK_CONDITIONAL_GE, + elk_abs(get_element(off, 0)), + elk_abs(get_element(off, 1))); - brw_SEL(p, vec1(off), - brw_abs(get_element(off, 0)), brw_abs(get_element(off, 1))); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_SEL(p, vec1(off), + elk_abs(get_element(off, 0)), elk_abs(get_element(off, 1))); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); - brw_MUL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_factor)); - brw_ADD(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_units)); + elk_MUL(p, vec1(off), vec1(off), elk_imm_f(c->key.offset_factor)); + elk_ADD(p, vec1(off), vec1(off), elk_imm_f(c->key.offset_units)); if (c->key.offset_clamp && isfinite(c->key.offset_clamp)) { - brw_CMP(p, - vec1(brw_null_reg()), - c->key.offset_clamp < 0 ? BRW_CONDITIONAL_GE : BRW_CONDITIONAL_L, + elk_CMP(p, + vec1(elk_null_reg()), + c->key.offset_clamp < 0 ? ELK_CONDITIONAL_GE : ELK_CONDITIONAL_L, vec1(off), - brw_imm_f(c->key.offset_clamp)); - brw_SEL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_clamp)); + elk_imm_f(c->key.offset_clamp)); + elk_SEL(p, vec1(off), vec1(off), elk_imm_f(c->key.offset_clamp)); } } -static void merge_edgeflags( struct brw_clip_compile *c ) +static void merge_edgeflags( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_reg tmp0 = get_element_ud(c->reg.tmp0, 0); + struct elk_codegen *p = &c->func; + struct elk_reg tmp0 = get_element_ud(c->reg.tmp0, 0); - brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK)); - brw_CMP(p, - vec1(brw_null_reg()), - BRW_CONDITIONAL_EQ, + elk_AND(p, tmp0, get_element_ud(c->reg.R0, 2), elk_imm_ud(PRIM_MASK)); + elk_CMP(p, + vec1(elk_null_reg()), + ELK_CONDITIONAL_EQ, tmp0, - brw_imm_ud(_3DPRIM_POLYGON)); + elk_imm_ud(_3DPRIM_POLYGON)); /* Get away with using reg.vertex because we know that this is not * a _3DPRIM_TRISTRIP_REVERSE: */ - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { - brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_EQ); - brw_MOV(p, byte_offset(c->reg.vertex[0], - brw_varying_to_offset(&c->vue_map, + elk_AND(p, vec1(elk_null_reg()), get_element_ud(c->reg.R0, 2), elk_imm_ud(1<<8)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_EQ); + elk_MOV(p, byte_offset(c->reg.vertex[0], + elk_varying_to_offset(&c->vue_map, VARYING_SLOT_EDGE)), - brw_imm_f(0)); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_imm_f(0)); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); - brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_EQ); - brw_MOV(p, byte_offset(c->reg.vertex[2], - brw_varying_to_offset(&c->vue_map, + elk_AND(p, vec1(elk_null_reg()), get_element_ud(c->reg.R0, 2), elk_imm_ud(1<<9)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_EQ); + elk_MOV(p, byte_offset(c->reg.vertex[2], + elk_varying_to_offset(&c->vue_map, VARYING_SLOT_EDGE)), - brw_imm_f(0)); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_imm_f(0)); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); } - brw_ENDIF(p); + elk_ENDIF(p); } -static void apply_one_offset( struct brw_clip_compile *c, - struct brw_indirect vert ) +static void apply_one_offset( struct elk_clip_compile *c, + struct elk_indirect vert ) { - struct brw_codegen *p = &c->func; - GLuint ndc_offset = brw_varying_to_offset(&c->vue_map, - BRW_VARYING_SLOT_NDC); - struct brw_reg z = deref_1f(vert, ndc_offset + - 2 * type_sz(BRW_REGISTER_TYPE_F)); + struct elk_codegen *p = &c->func; + GLuint ndc_offset = elk_varying_to_offset(&c->vue_map, + ELK_VARYING_SLOT_NDC); + struct elk_reg z = deref_1f(vert, ndc_offset + + 2 * type_sz(ELK_REGISTER_TYPE_F)); - brw_ADD(p, z, z, vec1(c->reg.offset)); + elk_ADD(p, z, z, vec1(c->reg.offset)); } @@ -275,115 +275,115 @@ static void apply_one_offset( struct brw_clip_compile *c, /*********************************************************************** * Output clipped polygon as an unfilled primitive: */ -static void emit_lines(struct brw_clip_compile *c, +static void emit_lines(struct elk_clip_compile *c, bool do_offset) { - struct brw_codegen *p = &c->func; - struct brw_indirect v0 = brw_indirect(0, 0); - struct brw_indirect v1 = brw_indirect(1, 0); - struct brw_indirect v0ptr = brw_indirect(2, 0); - struct brw_indirect v1ptr = brw_indirect(3, 0); + struct elk_codegen *p = &c->func; + struct elk_indirect v0 = elk_indirect(0, 0); + struct elk_indirect v1 = elk_indirect(1, 0); + struct elk_indirect v0ptr = elk_indirect(2, 0); + struct elk_indirect v1ptr = elk_indirect(3, 0); /* Need a separate loop for offset: */ if (do_offset) { - brw_MOV(p, c->reg.loopcount, c->reg.nr_verts); - brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist)); + elk_MOV(p, c->reg.loopcount, c->reg.nr_verts); + elk_MOV(p, get_addr_reg(v0ptr), elk_address(c->reg.inlist)); - brw_DO(p, BRW_EXECUTE_1); + elk_DO(p, ELK_EXECUTE_1); { - brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); - brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2)); + elk_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); + elk_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), elk_imm_uw(2)); apply_one_offset(c, v0); - brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_G); + elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_G); } - brw_WHILE(p); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_WHILE(p); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); } /* v1ptr = &inlist[nr_verts] * *v1ptr = v0 */ - brw_MOV(p, c->reg.loopcount, c->reg.nr_verts); - brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist)); - brw_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v0ptr), retype(c->reg.nr_verts, BRW_REGISTER_TYPE_UW)); - brw_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v1ptr), retype(c->reg.nr_verts, BRW_REGISTER_TYPE_UW)); - brw_MOV(p, deref_1uw(v1ptr, 0), deref_1uw(v0ptr, 0)); + elk_MOV(p, c->reg.loopcount, c->reg.nr_verts); + elk_MOV(p, get_addr_reg(v0ptr), elk_address(c->reg.inlist)); + elk_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v0ptr), retype(c->reg.nr_verts, ELK_REGISTER_TYPE_UW)); + elk_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v1ptr), retype(c->reg.nr_verts, ELK_REGISTER_TYPE_UW)); + elk_MOV(p, deref_1uw(v1ptr, 0), deref_1uw(v0ptr, 0)); - brw_DO(p, BRW_EXECUTE_1); + elk_DO(p, ELK_EXECUTE_1); { - brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); - brw_MOV(p, get_addr_reg(v1), deref_1uw(v0ptr, 2)); - brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2)); + elk_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); + elk_MOV(p, get_addr_reg(v1), deref_1uw(v0ptr, 2)); + elk_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), elk_imm_uw(2)); /* draw edge if edgeflag != 0 */ - brw_CMP(p, - vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, - deref_1f(v0, brw_varying_to_offset(&c->vue_map, + elk_CMP(p, + vec1(elk_null_reg()), ELK_CONDITIONAL_NZ, + deref_1f(v0, elk_varying_to_offset(&c->vue_map, VARYING_SLOT_EDGE)), - brw_imm_f(0)); - brw_IF(p, BRW_EXECUTE_1); + elk_imm_f(0)); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_emit_vue(c, v0, BRW_URB_WRITE_ALLOCATE_COMPLETE, + elk_clip_emit_vue(c, v0, ELK_URB_WRITE_ALLOCATE_COMPLETE, (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START); - brw_clip_emit_vue(c, v1, BRW_URB_WRITE_ALLOCATE_COMPLETE, + elk_clip_emit_vue(c, v1, ELK_URB_WRITE_ALLOCATE_COMPLETE, (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END); } - brw_ENDIF(p); + elk_ENDIF(p); - brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); + elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); } - brw_WHILE(p); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_WHILE(p); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); } -static void emit_points(struct brw_clip_compile *c, +static void emit_points(struct elk_clip_compile *c, bool do_offset ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; - struct brw_indirect v0 = brw_indirect(0, 0); - struct brw_indirect v0ptr = brw_indirect(2, 0); + struct elk_indirect v0 = elk_indirect(0, 0); + struct elk_indirect v0ptr = elk_indirect(2, 0); - brw_MOV(p, c->reg.loopcount, c->reg.nr_verts); - brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist)); + elk_MOV(p, c->reg.loopcount, c->reg.nr_verts); + elk_MOV(p, get_addr_reg(v0ptr), elk_address(c->reg.inlist)); - brw_DO(p, BRW_EXECUTE_1); + elk_DO(p, ELK_EXECUTE_1); { - brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); - brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2)); + elk_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); + elk_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), elk_imm_uw(2)); /* draw if edgeflag != 0 */ - brw_CMP(p, - vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, - deref_1f(v0, brw_varying_to_offset(&c->vue_map, + elk_CMP(p, + vec1(elk_null_reg()), ELK_CONDITIONAL_NZ, + deref_1f(v0, elk_varying_to_offset(&c->vue_map, VARYING_SLOT_EDGE)), - brw_imm_f(0)); - brw_IF(p, BRW_EXECUTE_1); + elk_imm_f(0)); + elk_IF(p, ELK_EXECUTE_1); { if (do_offset) apply_one_offset(c, v0); - brw_clip_emit_vue(c, v0, BRW_URB_WRITE_ALLOCATE_COMPLETE, + elk_clip_emit_vue(c, v0, ELK_URB_WRITE_ALLOCATE_COMPLETE, (_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START | URB_WRITE_PRIM_END); } - brw_ENDIF(p); + elk_ENDIF(p); - brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); + elk_ADD(p, c->reg.loopcount, c->reg.loopcount, elk_imm_d(-1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); } - brw_WHILE(p); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, BRW_PREDICATE_NORMAL); + elk_WHILE(p); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, ELK_PREDICATE_NORMAL); } @@ -392,60 +392,60 @@ static void emit_points(struct brw_clip_compile *c, -static void emit_primitives( struct brw_clip_compile *c, +static void emit_primitives( struct elk_clip_compile *c, GLuint mode, bool do_offset ) { switch (mode) { - case BRW_CLIP_FILL_MODE_FILL: - brw_clip_tri_emit_polygon(c); + case ELK_CLIP_FILL_MODE_FILL: + elk_clip_tri_emit_polygon(c); break; - case BRW_CLIP_FILL_MODE_LINE: + case ELK_CLIP_FILL_MODE_LINE: emit_lines(c, do_offset); break; - case BRW_CLIP_FILL_MODE_POINT: + case ELK_CLIP_FILL_MODE_POINT: emit_points(c, do_offset); break; - case BRW_CLIP_FILL_MODE_CULL: + case ELK_CLIP_FILL_MODE_CULL: unreachable("not reached"); } } -static void emit_unfilled_primitives( struct brw_clip_compile *c ) +static void emit_unfilled_primitives( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; /* Direction culling has already been done. */ if (c->key.fill_ccw != c->key.fill_cw && - c->key.fill_ccw != BRW_CLIP_FILL_MODE_CULL && - c->key.fill_cw != BRW_CLIP_FILL_MODE_CULL) + c->key.fill_ccw != ELK_CLIP_FILL_MODE_CULL && + c->key.fill_cw != ELK_CLIP_FILL_MODE_CULL) { - brw_CMP(p, - vec1(brw_null_reg()), - BRW_CONDITIONAL_GE, + elk_CMP(p, + vec1(elk_null_reg()), + ELK_CONDITIONAL_GE, get_element(c->reg.dir, 2), - brw_imm_f(0)); + elk_imm_f(0)); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); { emit_primitives(c, c->key.fill_ccw, c->key.offset_ccw); } - brw_ELSE(p); + elk_ELSE(p); { emit_primitives(c, c->key.fill_cw, c->key.offset_cw); } - brw_ENDIF(p); + elk_ENDIF(p); } - else if (c->key.fill_cw != BRW_CLIP_FILL_MODE_CULL) { + else if (c->key.fill_cw != ELK_CLIP_FILL_MODE_CULL) { emit_primitives(c, c->key.fill_cw, c->key.offset_cw); } - else if (c->key.fill_ccw != BRW_CLIP_FILL_MODE_CULL) { + else if (c->key.fill_ccw != ELK_CLIP_FILL_MODE_CULL) { emit_primitives(c, c->key.fill_ccw, c->key.offset_ccw); } } @@ -453,39 +453,39 @@ static void emit_unfilled_primitives( struct brw_clip_compile *c ) -static void check_nr_verts( struct brw_clip_compile *c ) +static void check_nr_verts( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.nr_verts, brw_imm_d(3)); - brw_IF(p, BRW_EXECUTE_1); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_L, c->reg.nr_verts, elk_imm_d(3)); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_kill_thread(c); + elk_clip_kill_thread(c); } - brw_ENDIF(p); + elk_ENDIF(p); } -void brw_emit_unfilled_clip( struct brw_clip_compile *c ) +void elk_emit_unfilled_clip( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; c->need_direction = ((c->key.offset_ccw || c->key.offset_cw) || (c->key.fill_ccw != c->key.fill_cw) || - c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL || - c->key.fill_cw == BRW_CLIP_FILL_MODE_CULL || + c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL || + c->key.fill_cw == ELK_CLIP_FILL_MODE_CULL || c->key.copy_bfc_cw || c->key.copy_bfc_ccw); - brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6); - brw_clip_tri_init_vertices(c); - brw_clip_init_ff_sync(c); + elk_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6); + elk_clip_tri_init_vertices(c); + elk_clip_init_ff_sync(c); - assert(brw_clip_have_varying(c, VARYING_SLOT_EDGE)); + assert(elk_clip_have_varying(c, VARYING_SLOT_EDGE)); - if (c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL && - c->key.fill_cw == BRW_CLIP_FILL_MODE_CULL) { - brw_clip_kill_thread(c); + if (c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL && + c->key.fill_cw == ELK_CLIP_FILL_MODE_CULL) { + elk_clip_kill_thread(c); return; } @@ -496,8 +496,8 @@ void brw_emit_unfilled_clip( struct brw_clip_compile *c ) if (c->need_direction) compute_tri_direction(c); - if (c->key.fill_ccw == BRW_CLIP_FILL_MODE_CULL || - c->key.fill_cw == BRW_CLIP_FILL_MODE_CULL) + if (c->key.fill_ccw == ELK_CLIP_FILL_MODE_CULL || + c->key.fill_cw == ELK_CLIP_FILL_MODE_CULL) cull_direction(c); if (c->key.offset_ccw || @@ -511,18 +511,18 @@ void brw_emit_unfilled_clip( struct brw_clip_compile *c ) /* Need to do this whether we clip or not: */ if (c->key.contains_flat_varying) - brw_clip_tri_flat_shade(c); + elk_clip_tri_flat_shade(c); - brw_clip_init_clipmask(c); - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, c->reg.planemask, brw_imm_ud(0)); - brw_IF(p, BRW_EXECUTE_1); + elk_clip_init_clipmask(c); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_NZ, c->reg.planemask, elk_imm_ud(0)); + elk_IF(p, ELK_EXECUTE_1); { - brw_clip_init_planes(c); - brw_clip_tri(c); + elk_clip_init_planes(c); + elk_clip_tri(c); check_nr_verts(c); } - brw_ENDIF(p); + elk_ENDIF(p); emit_unfilled_primitives(c); - brw_clip_kill_thread(c); + elk_clip_kill_thread(c); } diff --git a/src/intel/compiler/elk/elk_clip_util.c b/src/intel/compiler/elk/elk_clip_util.c index ac76f05afae..d3cf35e75a7 100644 --- a/src/intel/compiler/elk/elk_clip_util.c +++ b/src/intel/compiler/elk/elk_clip_util.c @@ -32,9 +32,9 @@ #include "elk_clip.h" -struct brw_reg get_tmp( struct brw_clip_compile *c ) +struct elk_reg get_tmp( struct elk_clip_compile *c ) { - struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0); + struct elk_reg tmp = elk_vec4_grf(c->last_tmp, 0); if (++c->last_tmp > c->prog_data.total_grf) c->prog_data.total_grf = c->last_tmp; @@ -42,30 +42,30 @@ struct brw_reg get_tmp( struct brw_clip_compile *c ) return tmp; } -static void release_tmp( struct brw_clip_compile *c, struct brw_reg tmp ) +static void release_tmp( struct elk_clip_compile *c, struct elk_reg tmp ) { if (tmp.nr == c->last_tmp-1) c->last_tmp--; } -static struct brw_reg make_plane_ud(GLuint x, GLuint y, GLuint z, GLuint w) +static struct elk_reg make_plane_ud(GLuint x, GLuint y, GLuint z, GLuint w) { - return brw_imm_ud((w<<24) | (z<<16) | (y<<8) | x); + return elk_imm_ud((w<<24) | (z<<16) | (y<<8) | x); } -void brw_clip_init_planes( struct brw_clip_compile *c ) +void elk_clip_init_planes( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; if (!c->key.nr_userclip) { - brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1)); - brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1)); - brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1)); - brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1)); - brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1)); - brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1)); + elk_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1)); + elk_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1)); + elk_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1)); + elk_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1)); + elk_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1)); + elk_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1)); } } @@ -75,38 +75,38 @@ void brw_clip_init_planes( struct brw_clip_compile *c ) /* Project 'pos' to screen space (or back again), overwrite with results: */ -void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos ) +void elk_clip_project_position(struct elk_clip_compile *c, struct elk_reg pos ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; /* calc rhw */ - brw_math_invert(p, get_element(pos, W), get_element(pos, W)); + elk_math_invert(p, get_element(pos, W), get_element(pos, W)); /* value.xyz *= value.rhw */ - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos, - brw_swizzle(pos, BRW_SWIZZLE_WWWW)); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_MUL(p, elk_writemask(pos, WRITEMASK_XYZ), pos, + elk_swizzle(pos, ELK_SWIZZLE_WWWW)); + elk_set_default_access_mode(p, ELK_ALIGN_1); } -static void brw_clip_project_vertex( struct brw_clip_compile *c, - struct brw_indirect vert_addr ) +static void elk_clip_project_vertex( struct elk_clip_compile *c, + struct elk_indirect vert_addr ) { - struct brw_codegen *p = &c->func; - struct brw_reg tmp = get_tmp(c); - GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); - GLuint ndc_offset = brw_varying_to_offset(&c->vue_map, - BRW_VARYING_SLOT_NDC); + struct elk_codegen *p = &c->func; + struct elk_reg tmp = get_tmp(c); + GLuint hpos_offset = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); + GLuint ndc_offset = elk_varying_to_offset(&c->vue_map, + ELK_VARYING_SLOT_NDC); /* Fixup position. Extract from the original vertex and re-project * to screen space: */ - brw_MOV(p, tmp, deref_4f(vert_addr, hpos_offset)); - brw_clip_project_position(c, tmp); - brw_MOV(p, deref_4f(vert_addr, ndc_offset), tmp); + elk_MOV(p, tmp, deref_4f(vert_addr, hpos_offset)); + elk_clip_project_position(c, tmp); + elk_MOV(p, deref_4f(vert_addr, ndc_offset), tmp); release_tmp(c, tmp); } @@ -119,15 +119,15 @@ static void brw_clip_project_vertex( struct brw_clip_compile *c, * * Beware that dest_ptr can be equal to v0_ptr! */ -void brw_clip_interp_vertex( struct brw_clip_compile *c, - struct brw_indirect dest_ptr, - struct brw_indirect v0_ptr, /* from */ - struct brw_indirect v1_ptr, /* to */ - struct brw_reg t0, +void elk_clip_interp_vertex( struct elk_clip_compile *c, + struct elk_indirect dest_ptr, + struct elk_indirect v0_ptr, /* from */ + struct elk_indirect v1_ptr, /* to */ + struct elk_reg t0, bool force_edgeflag) { - struct brw_codegen *p = &c->func; - struct brw_reg t_nopersp, v0_ndc_copy; + struct elk_codegen *p = &c->func; + struct elk_reg t_nopersp, v0_ndc_copy; GLuint slot; /* Just copy the vertex header: @@ -136,7 +136,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, * After CLIP stage, only first 256 bits of the VUE are read * back on Ironlake, so needn't change it */ - brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1); + elk_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1); /* First handle the 3D and NDC interpolation, in case we @@ -146,10 +146,10 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, /* Take a copy of the v0 NDC coordinates, in case dest == v0. */ if (c->key.contains_noperspective_varying) { - GLuint offset = brw_varying_to_offset(&c->vue_map, - BRW_VARYING_SLOT_NDC); + GLuint offset = elk_varying_to_offset(&c->vue_map, + ELK_VARYING_SLOT_NDC); v0_ndc_copy = get_tmp(c); - brw_MOV(p, v0_ndc_copy, deref_4f(v0_ptr, offset)); + elk_MOV(p, v0_ndc_copy, deref_4f(v0_ptr, offset)); } /* Compute the new 3D position @@ -157,37 +157,37 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, * dest_hpos = v0_hpos * (1 - t0) + v1_hpos * t0 */ { - GLuint delta = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); - struct brw_reg tmp = get_tmp(c); - brw_MUL(p, vec4(brw_null_reg()), deref_4f(v1_ptr, delta), t0); - brw_MAC(p, tmp, negate(deref_4f(v0_ptr, delta)), t0); - brw_ADD(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta), tmp); + GLuint delta = elk_varying_to_offset(&c->vue_map, VARYING_SLOT_POS); + struct elk_reg tmp = get_tmp(c); + elk_MUL(p, vec4(elk_null_reg()), deref_4f(v1_ptr, delta), t0); + elk_MAC(p, tmp, negate(deref_4f(v0_ptr, delta)), t0); + elk_ADD(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta), tmp); release_tmp(c, tmp); } /* Recreate the projected (NDC) coordinate in the new vertex header */ - brw_clip_project_vertex(c, dest_ptr); + elk_clip_project_vertex(c, dest_ptr); /* If we have noperspective attributes, * we need to compute the screen-space t */ if (c->key.contains_noperspective_varying) { - GLuint delta = brw_varying_to_offset(&c->vue_map, - BRW_VARYING_SLOT_NDC); - struct brw_reg tmp = get_tmp(c); + GLuint delta = elk_varying_to_offset(&c->vue_map, + ELK_VARYING_SLOT_NDC); + struct elk_reg tmp = get_tmp(c); t_nopersp = get_tmp(c); /* t_nopersp = vec4(v1.xy, dest.xy) */ - brw_MOV(p, t_nopersp, deref_4f(v1_ptr, delta)); - brw_MOV(p, tmp, deref_4f(dest_ptr, delta)); - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_MOV(p, - brw_writemask(t_nopersp, WRITEMASK_ZW), - brw_swizzle(tmp, BRW_SWIZZLE_XYXY)); + elk_MOV(p, t_nopersp, deref_4f(v1_ptr, delta)); + elk_MOV(p, tmp, deref_4f(dest_ptr, delta)); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_MOV(p, + elk_writemask(t_nopersp, WRITEMASK_ZW), + elk_swizzle(tmp, ELK_SWIZZLE_XYXY)); /* t_nopersp = vec4(v1.xy, dest.xy) - v0.xyxy */ - brw_ADD(p, t_nopersp, t_nopersp, - negate(brw_swizzle(v0_ndc_copy, BRW_SWIZZLE_XYXY))); + elk_ADD(p, t_nopersp, t_nopersp, + negate(elk_swizzle(v0_ndc_copy, ELK_SWIZZLE_XYXY))); /* Add the absolute values of the X and Y deltas so that if * the points aren't in the same place on the screen we get @@ -199,32 +199,32 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, * t_nopersp = vec2(|v1.x -v0.x| + |v1.y -v0.y|, * |dest.x-v0.x| + |dest.y-v0.y|) */ - brw_ADD(p, - brw_writemask(t_nopersp, WRITEMASK_XY), - brw_abs(brw_swizzle(t_nopersp, BRW_SWIZZLE_XZXZ)), - brw_abs(brw_swizzle(t_nopersp, BRW_SWIZZLE_YWYW))); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_ADD(p, + elk_writemask(t_nopersp, WRITEMASK_XY), + elk_abs(elk_swizzle(t_nopersp, ELK_SWIZZLE_XZXZ)), + elk_abs(elk_swizzle(t_nopersp, ELK_SWIZZLE_YWYW))); + elk_set_default_access_mode(p, ELK_ALIGN_1); /* If the points are in the same place, just substitute a * value to avoid divide-by-zero */ - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_EQ, vec1(t_nopersp), - brw_imm_f(0)); - brw_IF(p, BRW_EXECUTE_1); - brw_MOV(p, t_nopersp, brw_imm_vf4(brw_float_to_vf(1.0), - brw_float_to_vf(0.0), - brw_float_to_vf(0.0), - brw_float_to_vf(0.0))); - brw_ENDIF(p); + elk_imm_f(0)); + elk_IF(p, ELK_EXECUTE_1); + elk_MOV(p, t_nopersp, elk_imm_vf4(elk_float_to_vf(1.0), + elk_float_to_vf(0.0), + elk_float_to_vf(0.0), + elk_float_to_vf(0.0))); + elk_ENDIF(p); /* Now compute t_nopersp = t_nopersp.y/t_nopersp.x and broadcast it. */ - brw_math_invert(p, get_element(t_nopersp, 0), get_element(t_nopersp, 0)); - brw_MUL(p, vec1(t_nopersp), vec1(t_nopersp), + elk_math_invert(p, get_element(t_nopersp, 0), get_element(t_nopersp, 0)); + elk_MUL(p, vec1(t_nopersp), vec1(t_nopersp), vec1(suboffset(t_nopersp, 1))); - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_MOV(p, t_nopersp, brw_swizzle(t_nopersp, BRW_SWIZZLE_XXXX)); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_MOV(p, t_nopersp, elk_swizzle(t_nopersp, ELK_SWIZZLE_XXXX)); + elk_set_default_access_mode(p, ELK_ALIGN_1); release_tmp(c, tmp); release_tmp(c, v0_ndc_copy); @@ -235,18 +235,18 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, */ for (slot = 0; slot < c->vue_map.num_slots; slot++) { int varying = c->vue_map.slot_to_varying[slot]; - GLuint delta = brw_vue_slot_to_offset(slot); + GLuint delta = elk_vue_slot_to_offset(slot); /* HPOS, NDC already handled above */ - if (varying == VARYING_SLOT_POS || varying == BRW_VARYING_SLOT_NDC) + if (varying == VARYING_SLOT_POS || varying == ELK_VARYING_SLOT_NDC) continue; if (varying == VARYING_SLOT_EDGE) { if (force_edgeflag) - brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1)); + elk_MOV(p, deref_4f(dest_ptr, delta), elk_imm_f(1)); else - brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta)); + elk_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta)); } else if (varying == VARYING_SLOT_PSIZ) { /* PSIZ doesn't need interpolation because it isn't used by the * fragment shader. @@ -263,21 +263,21 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, GLuint interp = c->key.interp_mode[slot]; if (interp != INTERP_MODE_FLAT) { - struct brw_reg tmp = get_tmp(c); - struct brw_reg t = + struct elk_reg tmp = get_tmp(c); + struct elk_reg t = interp == INTERP_MODE_NOPERSPECTIVE ? t_nopersp : t0; - brw_MUL(p, - vec4(brw_null_reg()), + elk_MUL(p, + vec4(elk_null_reg()), deref_4f(v1_ptr, delta), t); - brw_MAC(p, + elk_MAC(p, tmp, negate(deref_4f(v0_ptr, delta)), t); - brw_ADD(p, + elk_ADD(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta), tmp); @@ -285,7 +285,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, release_tmp(c, tmp); } else { - brw_MOV(p, + elk_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta)); } @@ -293,94 +293,94 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, } if (c->vue_map.num_slots % 2) { - GLuint delta = brw_vue_slot_to_offset(c->vue_map.num_slots); + GLuint delta = elk_vue_slot_to_offset(c->vue_map.num_slots); - brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0)); + elk_MOV(p, deref_4f(dest_ptr, delta), elk_imm_f(0)); } if (c->key.contains_noperspective_varying) release_tmp(c, t_nopersp); } -void brw_clip_emit_vue(struct brw_clip_compile *c, - struct brw_indirect vert, - enum brw_urb_write_flags flags, +void elk_clip_emit_vue(struct elk_clip_compile *c, + struct elk_indirect vert, + enum elk_urb_write_flags flags, GLuint header) { - struct brw_codegen *p = &c->func; - bool allocate = flags & BRW_URB_WRITE_ALLOCATE; + struct elk_codegen *p = &c->func; + bool allocate = flags & ELK_URB_WRITE_ALLOCATE; - brw_clip_ff_sync(c); + elk_clip_ff_sync(c); /* Any URB entry that is allocated must subsequently be used or discarded, * so it doesn't make sense to mark EOT and ALLOCATE at the same time. */ - assert(!(allocate && (flags & BRW_URB_WRITE_EOT))); + assert(!(allocate && (flags & ELK_URB_WRITE_EOT))); /* Copy the vertex from vertn into m1..mN+1: */ - brw_copy_from_indirect(p, brw_message_reg(1), vert, c->nr_regs); + elk_copy_from_indirect(p, elk_message_reg(1), vert, c->nr_regs); /* Overwrite PrimType and PrimStart in the message header, for * each vertex in turn: */ - brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header)); + elk_MOV(p, get_element_ud(c->reg.R0, 2), elk_imm_ud(header)); /* Send each vertex as a separate write to the urb. This - * is different to the concept in brw_sf_emit.c, where + * is different to the concept in elk_sf_emit.c, where * subsequent writes are used to build up a single urb * entry. Each of these writes instantiates a separate * urb entry - (I think... what about 'allocate'?) */ - brw_urb_WRITE(p, - allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), + elk_urb_WRITE(p, + allocate ? c->reg.R0 : retype(elk_null_reg(), ELK_REGISTER_TYPE_UD), 0, c->reg.R0, flags, c->nr_regs + 1, /* msg length */ allocate ? 1 : 0, /* response_length */ 0, /* urb offset */ - BRW_URB_SWIZZLE_NONE); + ELK_URB_SWIZZLE_NONE); } -void brw_clip_kill_thread(struct brw_clip_compile *c) +void elk_clip_kill_thread(struct elk_clip_compile *c) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; - brw_clip_ff_sync(c); + elk_clip_ff_sync(c); /* Send an empty message to kill the thread and release any * allocated urb entry: */ - brw_urb_WRITE(p, - retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), + elk_urb_WRITE(p, + retype(elk_null_reg(), ELK_REGISTER_TYPE_UD), 0, c->reg.R0, - BRW_URB_WRITE_UNUSED | BRW_URB_WRITE_EOT_COMPLETE, + ELK_URB_WRITE_UNUSED | ELK_URB_WRITE_EOT_COMPLETE, 1, /* msg len */ 0, /* response len */ 0, - BRW_URB_SWIZZLE_NONE); + ELK_URB_SWIZZLE_NONE); } -struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c ) +struct elk_reg elk_clip_plane0_address( struct elk_clip_compile *c ) { - return brw_address(c->reg.fixed_planes); + return elk_address(c->reg.fixed_planes); } -struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c ) +struct elk_reg elk_clip_plane_stride( struct elk_clip_compile *c ) { if (c->key.nr_userclip) { - return brw_imm_uw(16); + return elk_imm_uw(16); } else { - return brw_imm_uw(4); + return elk_imm_uw(4); } } @@ -388,60 +388,60 @@ struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c ) /* Distribute flatshaded attributes from provoking vertex prior to * clipping. */ -void brw_clip_copy_flatshaded_attributes( struct brw_clip_compile *c, +void elk_clip_copy_flatshaded_attributes( struct elk_clip_compile *c, GLuint to, GLuint from ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; for (int i = 0; i < c->vue_map.num_slots; i++) { if (c->key.interp_mode[i] == INTERP_MODE_FLAT) { - brw_MOV(p, - byte_offset(c->reg.vertex[to], brw_vue_slot_to_offset(i)), - byte_offset(c->reg.vertex[from], brw_vue_slot_to_offset(i))); + elk_MOV(p, + byte_offset(c->reg.vertex[to], elk_vue_slot_to_offset(i)), + byte_offset(c->reg.vertex[from], elk_vue_slot_to_offset(i))); } } } -void brw_clip_init_clipmask( struct brw_clip_compile *c ) +void elk_clip_init_clipmask( struct elk_clip_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_reg incoming = get_element_ud(c->reg.R0, 2); + struct elk_codegen *p = &c->func; + struct elk_reg incoming = get_element_ud(c->reg.R0, 2); /* Shift so that lowest outcode bit is rightmost: */ - brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26)); + elk_SHR(p, c->reg.planemask, incoming, elk_imm_ud(26)); if (c->key.nr_userclip) { - struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD); + struct elk_reg tmp = retype(vec1(get_tmp(c)), ELK_REGISTER_TYPE_UD); /* Rearrange userclip outcodes so that they come directly after * the fixed plane bits. */ if (p->devinfo->ver == 5 || p->devinfo->verx10 == 45) - brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14)); + elk_AND(p, tmp, incoming, elk_imm_ud(0xff<<14)); else - brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14)); + elk_AND(p, tmp, incoming, elk_imm_ud(0x3f<<14)); - brw_SHR(p, tmp, tmp, brw_imm_ud(8)); - brw_OR(p, c->reg.planemask, c->reg.planemask, tmp); + elk_SHR(p, tmp, tmp, elk_imm_ud(8)); + elk_OR(p, c->reg.planemask, c->reg.planemask, tmp); release_tmp(c, tmp); } } -void brw_clip_ff_sync(struct brw_clip_compile *c) +void elk_clip_ff_sync(struct elk_clip_compile *c) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; if (p->devinfo->ver == 5) { - brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z); - brw_IF(p, BRW_EXECUTE_1); + elk_AND(p, elk_null_reg(), c->reg.ff_sync, elk_imm_ud(0x1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_Z); + elk_IF(p, ELK_EXECUTE_1); { - brw_OR(p, c->reg.ff_sync, c->reg.ff_sync, brw_imm_ud(0x1)); - brw_ff_sync(p, + elk_OR(p, c->reg.ff_sync, c->reg.ff_sync, elk_imm_ud(0x1)); + elk_ff_sync(p, c->reg.R0, 0, c->reg.R0, @@ -449,16 +449,16 @@ void brw_clip_ff_sync(struct brw_clip_compile *c) 1, /* response length */ 0 /* eot */); } - brw_ENDIF(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_ENDIF(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); } } -void brw_clip_init_ff_sync(struct brw_clip_compile *c) +void elk_clip_init_ff_sync(struct elk_clip_compile *c) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; if (p->devinfo->ver == 5) { - brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0)); + elk_MOV(p, c->reg.ff_sync, elk_imm_ud(0)); } } diff --git a/src/intel/compiler/elk/elk_compile_clip.c b/src/intel/compiler/elk/elk_compile_clip.c index 18fc4e6c23c..0a18d089147 100644 --- a/src/intel/compiler/elk/elk_compile_clip.c +++ b/src/intel/compiler/elk/elk_compile_clip.c @@ -27,19 +27,19 @@ #include "dev/intel_debug.h" const unsigned * -brw_compile_clip(const struct brw_compiler *compiler, +elk_compile_clip(const struct elk_compiler *compiler, void *mem_ctx, - const struct brw_clip_prog_key *key, - struct brw_clip_prog_data *prog_data, + const struct elk_clip_prog_key *key, + struct elk_clip_prog_data *prog_data, struct intel_vue_map *vue_map, unsigned *final_assembly_size) { - struct brw_clip_compile c; + struct elk_clip_compile c; memset(&c, 0, sizeof(c)); /* Begin the compilation: */ - brw_init_codegen(&compiler->isa, &c.func, mem_ctx); + elk_init_codegen(&compiler->isa, &c.func, mem_ctx); c.func.single_program_flow = 1; @@ -58,7 +58,7 @@ brw_compile_clip(const struct brw_compiler *compiler, /* For some reason the thread is spawned with only 4 channels * unmasked. */ - brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE); + elk_set_default_mask_control(&c.func, ELK_MASK_DISABLE); /* Would ideally have the option of producing a program which could * do all three: @@ -66,29 +66,29 @@ brw_compile_clip(const struct brw_compiler *compiler, switch (key->primitive) { case MESA_PRIM_TRIANGLES: if (key->do_unfilled) - brw_emit_unfilled_clip( &c ); + elk_emit_unfilled_clip( &c ); else - brw_emit_tri_clip( &c ); + elk_emit_tri_clip( &c ); break; case MESA_PRIM_LINES: - brw_emit_line_clip( &c ); + elk_emit_line_clip( &c ); break; case MESA_PRIM_POINTS: - brw_emit_point_clip( &c ); + elk_emit_point_clip( &c ); break; default: unreachable("not reached"); } - brw_compact_instructions(&c.func, 0, NULL); + elk_compact_instructions(&c.func, 0, NULL); *prog_data = c.prog_data; - const unsigned *program = brw_get_program(&c.func, final_assembly_size); + const unsigned *program = elk_get_program(&c.func, final_assembly_size); if (INTEL_DEBUG(DEBUG_CLIP)) { fprintf(stderr, "clip:\n"); - brw_disassemble_with_labels(&compiler->isa, + elk_disassemble_with_labels(&compiler->isa, program, 0, *final_assembly_size, stderr); fprintf(stderr, "\n"); } diff --git a/src/intel/compiler/elk/elk_compile_ff_gs.c b/src/intel/compiler/elk/elk_compile_ff_gs.c index 73182aa1e58..6b0d778bff8 100644 --- a/src/intel/compiler/elk/elk_compile_ff_gs.c +++ b/src/intel/compiler/elk/elk_compile_ff_gs.c @@ -38,30 +38,30 @@ #define MAX_GS_VERTS (4) -struct brw_ff_gs_compile { - struct brw_codegen func; - struct brw_ff_gs_prog_key key; - struct brw_ff_gs_prog_data *prog_data; +struct elk_ff_gs_compile { + struct elk_codegen func; + struct elk_ff_gs_prog_key key; + struct elk_ff_gs_prog_data *prog_data; struct { - struct brw_reg R0; + struct elk_reg R0; /** * Register holding streamed vertex buffer pointers -- see the Sandy * Bridge PRM, volume 2 part 1, section 4.4.2 (GS Thread Payload * [DevSNB]). These pointers are delivered in GRF 1. */ - struct brw_reg SVBI; + struct elk_reg SVBI; - struct brw_reg vertex[MAX_GS_VERTS]; - struct brw_reg header; - struct brw_reg temp; + struct elk_reg vertex[MAX_GS_VERTS]; + struct elk_reg header; + struct elk_reg temp; /** * Register holding destination indices for streamed buffer writes. * Only used for SOL programs. */ - struct brw_reg destination_indices; + struct elk_reg destination_indices; } reg; /* Number of registers used to store vertex data */ @@ -80,7 +80,7 @@ struct brw_ff_gs_compile { * * - The thread will need to use the destination_indices register. */ -static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c, +static void elk_ff_gs_alloc_regs(struct elk_ff_gs_compile *c, GLuint nr_verts, bool sol_program) { @@ -88,25 +88,25 @@ static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c, /* Register usage is static, precompute here: */ - c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; + c->reg.R0 = retype(elk_vec8_grf(i, 0), ELK_REGISTER_TYPE_UD); i++; /* Streamed vertex buffer indices */ if (sol_program) - c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); + c->reg.SVBI = retype(elk_vec8_grf(i++, 0), ELK_REGISTER_TYPE_UD); /* Payload vertices plus space for more generated vertices: */ for (j = 0; j < nr_verts; j++) { - c->reg.vertex[j] = brw_vec4_grf(i, 0); + c->reg.vertex[j] = elk_vec4_grf(i, 0); i += c->nr_regs; } - c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); - c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); + c->reg.header = retype(elk_vec8_grf(i++, 0), ELK_REGISTER_TYPE_UD); + c->reg.temp = retype(elk_vec8_grf(i++, 0), ELK_REGISTER_TYPE_UD); if (sol_program) { c->reg.destination_indices = - retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD); + retype(elk_vec4_grf(i++, 0), ELK_REGISTER_TYPE_UD); } c->prog_data->urb_read_length = c->nr_regs; @@ -128,10 +128,10 @@ static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c, * This function sets up the above data by copying by copying the contents of * R0 to the header register. */ -static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c) +static void elk_ff_gs_initialize_header(struct elk_ff_gs_compile *c) { - struct brw_codegen *p = &c->func; - brw_MOV(p, c->reg.header, c->reg.R0); + struct elk_codegen *p = &c->func; + elk_MOV(p, c->reg.header, c->reg.R0); } /** @@ -141,11 +141,11 @@ static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c) * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we * need to be able to update on a per-vertex basis. */ -static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c, +static void elk_ff_gs_overwrite_header_dw2(struct elk_ff_gs_compile *c, unsigned dw2) { - struct brw_codegen *p = &c->func; - brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2)); + struct elk_codegen *p = &c->func; + elk_MOV(p, get_element_ud(c->reg.header, 2), elk_imm_ud(dw2)); } /** @@ -156,13 +156,13 @@ static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c, * DWORD 2. So this function extracts the primitive type field, bitshifts it * appropriately, and stores it in c->reg.header. */ -static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c) +static void elk_ff_gs_overwrite_header_dw2_from_r0(struct elk_ff_gs_compile *c) { - struct brw_codegen *p = &c->func; - brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2), - brw_imm_ud(0x1f)); - brw_SHL(p, get_element_ud(c->reg.header, 2), - get_element_ud(c->reg.header, 2), brw_imm_ud(2)); + struct elk_codegen *p = &c->func; + elk_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2), + elk_imm_ud(0x1f)); + elk_SHL(p, get_element_ud(c->reg.header, 2), + get_element_ud(c->reg.header, 2), elk_imm_ud(2)); } /** @@ -171,12 +171,12 @@ static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c) * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately * for each vertex. */ -static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c, +static void elk_ff_gs_offset_header_dw2(struct elk_ff_gs_compile *c, int offset) { - struct brw_codegen *p = &c->func; - brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2), - brw_imm_d(offset)); + struct elk_codegen *p = &c->func; + elk_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2), + elk_imm_d(offset)); } @@ -192,11 +192,11 @@ static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c, * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE * message. */ -static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c, - struct brw_reg vert, +static void elk_ff_gs_emit_vue(struct elk_ff_gs_compile *c, + struct elk_reg vert, bool last) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; int write_offset = 0; bool complete = false; @@ -208,36 +208,36 @@ static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c, /* Copy the vertex from vertn into m1..mN+1: */ - brw_copy8(p, brw_message_reg(1), offset(vert, write_offset), write_len); + elk_copy8(p, elk_message_reg(1), offset(vert, write_offset), write_len); /* Send the vertex data to the URB. If this is the last write for this * vertex, then we mark it as complete, and either end the thread or * allocate another vertex URB entry (depending whether this is the last * vertex). */ - enum brw_urb_write_flags flags; + enum elk_urb_write_flags flags; if (!complete) - flags = BRW_URB_WRITE_NO_FLAGS; + flags = ELK_URB_WRITE_NO_FLAGS; else if (last) - flags = BRW_URB_WRITE_EOT_COMPLETE; + flags = ELK_URB_WRITE_EOT_COMPLETE; else - flags = BRW_URB_WRITE_ALLOCATE_COMPLETE; - brw_urb_WRITE(p, - (flags & BRW_URB_WRITE_ALLOCATE) ? c->reg.temp - : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), + flags = ELK_URB_WRITE_ALLOCATE_COMPLETE; + elk_urb_WRITE(p, + (flags & ELK_URB_WRITE_ALLOCATE) ? c->reg.temp + : retype(elk_null_reg(), ELK_REGISTER_TYPE_UD), 0, c->reg.header, flags, write_len + 1, /* msg length */ - (flags & BRW_URB_WRITE_ALLOCATE) ? 1 + (flags & ELK_URB_WRITE_ALLOCATE) ? 1 : 0, /* response length */ write_offset, /* urb offset */ - BRW_URB_SWIZZLE_NONE); + ELK_URB_SWIZZLE_NONE); write_offset += write_len; } while (!complete); if (!last) { - brw_MOV(p, get_element_ud(c->reg.header, 0), + elk_MOV(p, get_element_ud(c->reg.header, 0), get_element_ud(c->reg.temp, 0)); } } @@ -252,112 +252,112 @@ static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c, * the allocated URB entry (which will be needed by the URB_WRITE meesage that * follows). */ -static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile *c, int num_prim) +static void elk_ff_gs_ff_sync(struct elk_ff_gs_compile *c, int num_prim) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; - brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim)); - brw_ff_sync(p, + elk_MOV(p, get_element_ud(c->reg.header, 1), elk_imm_ud(num_prim)); + elk_ff_sync(p, c->reg.temp, 0, c->reg.header, 1, /* allocate */ 1, /* response length */ 0 /* eot */); - brw_MOV(p, get_element_ud(c->reg.header, 0), + elk_MOV(p, get_element_ud(c->reg.header, 0), get_element_ud(c->reg.temp, 0)); } static void -brw_ff_gs_quads(struct brw_ff_gs_compile *c, - const struct brw_ff_gs_prog_key *key) +elk_ff_gs_quads(struct elk_ff_gs_compile *c, + const struct elk_ff_gs_prog_key *key) { - brw_ff_gs_alloc_regs(c, 4, false); - brw_ff_gs_initialize_header(c); + elk_ff_gs_alloc_regs(c, 4, false); + elk_ff_gs_initialize_header(c); /* Use polygons for correct edgeflag behaviour. Note that vertex 3 * is the PV for quads, but vertex 0 for polygons: */ if (c->func.devinfo->ver == 5) - brw_ff_gs_ff_sync(c, 1); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_ff_sync(c, 1); + elk_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START)); if (key->pv_first) { - brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + elk_ff_gs_overwrite_header_dw2( c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); - brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0); - brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[1], 0); + elk_ff_gs_emit_vue(c, c->reg.vertex[2], 0); + elk_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1); + elk_ff_gs_emit_vue(c, c->reg.vertex[3], 1); } else { - brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[3], 0); + elk_ff_gs_overwrite_header_dw2( c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); - brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + elk_ff_gs_emit_vue(c, c->reg.vertex[1], 0); + elk_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_ff_gs_emit_vue(c, c->reg.vertex[2], 1); + elk_ff_gs_emit_vue(c, c->reg.vertex[2], 1); } } static void -brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c, - const struct brw_ff_gs_prog_key *key) +elk_ff_gs_quad_strip(struct elk_ff_gs_compile *c, + const struct elk_ff_gs_prog_key *key) { - brw_ff_gs_alloc_regs(c, 4, false); - brw_ff_gs_initialize_header(c); + elk_ff_gs_alloc_regs(c, 4, false); + elk_ff_gs_initialize_header(c); if (c->func.devinfo->ver == 5) - brw_ff_gs_ff_sync(c, 1); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_ff_sync(c, 1); + elk_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START)); if (key->pv_first) { - brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + elk_ff_gs_overwrite_header_dw2( c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); - brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0); - brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[1], 0); + elk_ff_gs_emit_vue(c, c->reg.vertex[2], 0); + elk_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1); + elk_ff_gs_emit_vue(c, c->reg.vertex[3], 1); } else { - brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[2], 0); + elk_ff_gs_overwrite_header_dw2( c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); - brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0); - brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[3], 0); + elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + elk_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1); + elk_ff_gs_emit_vue(c, c->reg.vertex[1], 1); } } -static void brw_ff_gs_lines(struct brw_ff_gs_compile *c) +static void elk_ff_gs_lines(struct elk_ff_gs_compile *c) { - brw_ff_gs_alloc_regs(c, 2, false); - brw_ff_gs_initialize_header(c); + elk_ff_gs_alloc_regs(c, 2, false); + elk_ff_gs_initialize_header(c); if (c->func.devinfo->ver == 5) - brw_ff_gs_ff_sync(c, 1); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_ff_sync(c, 1); + elk_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START)); - brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_ff_gs_overwrite_header_dw2( + elk_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + elk_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1); + elk_ff_gs_emit_vue(c, c->reg.vertex[1], 1); } /** @@ -365,20 +365,20 @@ static void brw_ff_gs_lines(struct brw_ff_gs_compile *c) * (transform feedback). */ static void -gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *key, +gfx6_sol_program(struct elk_ff_gs_compile *c, const struct elk_ff_gs_prog_key *key, unsigned num_verts, bool check_edge_flags) { - struct brw_codegen *p = &c->func; - brw_inst *inst; + struct elk_codegen *p = &c->func; + elk_inst *inst; c->prog_data->svbi_postincrement_value = num_verts; - brw_ff_gs_alloc_regs(c, num_verts, true); - brw_ff_gs_initialize_header(c); + elk_ff_gs_alloc_regs(c, num_verts, true); + elk_ff_gs_initialize_header(c); if (key->num_transform_feedback_bindings > 0) { unsigned vertex, binding; - struct brw_reg destination_indices_uw = - vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW)); + struct elk_reg destination_indices_uw = + vec8(retype(c->reg.destination_indices, ELK_REGISTER_TYPE_UW)); /* Note: since we use the binding table to keep track of buffer offsets * and stride, the GS doesn't need to keep track of a separate pointer @@ -388,12 +388,12 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k * * Make sure that the buffers have enough room for all the vertices. */ - brw_ADD(p, get_element_ud(c->reg.temp, 0), - get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts)); - brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, + elk_ADD(p, get_element_ud(c->reg.temp, 0), + get_element_ud(c->reg.SVBI, 0), elk_imm_ud(num_verts)); + elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_LE, get_element_ud(c->reg.temp, 0), get_element_ud(c->reg.SVBI, 4)); - brw_IF(p, BRW_EXECUTE_1); + elk_IF(p, ELK_EXECUTE_1); /* Compute the destination indices to write to. Usually we use SVBI[0] * + (0, 1, 2). However, for odd-numbered triangles in tristrips, the @@ -404,7 +404,7 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using * the last provoking vertex convention. * - * Note: since brw_imm_v can only be used in instructions in + * Note: since elk_imm_v can only be used in instructions in * packed-word execution mode, and SVBI is a double-word, we need to * first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1), * or (1, 0, 2)) to the destination_indices register, and then add SVBI @@ -413,42 +413,42 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k * destination_indices, we need to intersperse zeros to fill the upper * halves of each double-word. */ - brw_MOV(p, destination_indices_uw, - brw_imm_v(0x00020100)); /* (0, 1, 2) */ + elk_MOV(p, destination_indices_uw, + elk_imm_v(0x00020100)); /* (0, 1, 2) */ if (num_verts == 3) { /* Get primitive type into temp register. */ - brw_AND(p, get_element_ud(c->reg.temp, 0), - get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f)); + elk_AND(p, get_element_ud(c->reg.temp, 0), + get_element_ud(c->reg.R0, 2), elk_imm_ud(0x1f)); /* Test if primitive type is TRISTRIP_REVERSE. We need to do this as * an 8-wide comparison so that the conditional MOV that follows * moves all 8 words correctly. */ - brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ, + elk_CMP(p, vec8(elk_null_reg()), ELK_CONDITIONAL_EQ, get_element_ud(c->reg.temp, 0), - brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE)); + elk_imm_ud(_3DPRIM_TRISTRIP_REVERSE)); /* If so, then overwrite destination_indices_uw with the appropriate * reordering. */ - inst = brw_MOV(p, destination_indices_uw, - brw_imm_v(key->pv_first ? 0x00010200 /* (0, 2, 1) */ + inst = elk_MOV(p, destination_indices_uw, + elk_imm_v(key->pv_first ? 0x00010200 /* (0, 2, 1) */ : 0x00020001)); /* (1, 0, 2) */ - brw_inst_set_pred_control(p->devinfo, inst, BRW_PREDICATE_NORMAL); + elk_inst_set_pred_control(p->devinfo, inst, ELK_PREDICATE_NORMAL); } - assert(c->reg.destination_indices.width == BRW_EXECUTE_4); - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_4); - brw_ADD(p, c->reg.destination_indices, + assert(c->reg.destination_indices.width == ELK_EXECUTE_4); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_4); + elk_ADD(p, c->reg.destination_indices, c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); /* For each vertex, generate code to output each varying using the * appropriate binding table entry. */ for (vertex = 0; vertex < num_verts; ++vertex) { /* Set up the correct destination index for this vertex */ - brw_MOV(p, get_element_ud(c->reg.header, 5), + elk_MOV(p, get_element_ud(c->reg.header, 5), get_element_ud(c->reg.destination_indices, vertex)); for (binding = 0; binding < key->num_transform_feedback_bindings; @@ -465,36 +465,36 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k bool final_write = binding == key->num_transform_feedback_bindings - 1 && vertex == num_verts - 1; - struct brw_reg vertex_slot = c->reg.vertex[vertex]; + struct elk_reg vertex_slot = c->reg.vertex[vertex]; vertex_slot.nr += slot / 2; vertex_slot.subnr = (slot % 2) * 16; /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */ vertex_slot.swizzle = varying == VARYING_SLOT_PSIZ - ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding]; - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_4); + ? ELK_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding]; + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_4); - brw_MOV(p, stride(c->reg.header, 4, 4, 1), - retype(vertex_slot, BRW_REGISTER_TYPE_UD)); - brw_pop_insn_state(p); + elk_MOV(p, stride(c->reg.header, 4, 4, 1), + retype(vertex_slot, ELK_REGISTER_TYPE_UD)); + elk_pop_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_svb_write(p, - final_write ? c->reg.temp : brw_null_reg(), /* dest */ + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_svb_write(p, + final_write ? c->reg.temp : elk_null_reg(), /* dest */ 1, /* msg_reg_nr */ c->reg.header, /* src0 */ - BRW_GFX6_SOL_BINDING_START + binding, /* binding_table_index */ + ELK_GFX6_SOL_BINDING_START + binding, /* binding_table_index */ final_write); /* send_commit_msg */ } } - brw_ENDIF(p); + elk_ENDIF(p); /* Now, reinitialize the header register from R0 to restore the parts of * the register that we overwrote while streaming out transform feedback * data. */ - brw_ff_gs_initialize_header(c); + elk_ff_gs_initialize_header(c); /* Finally, wait for the write commit to occur so that we can proceed to * other things safely. @@ -506,68 +506,68 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, const struct brw_ff_gs_prog_key *k * register. Thus, a simple “mov” instruction using the register as a * source is sufficient to wait for the write commit to occur. */ - brw_MOV(p, c->reg.temp, c->reg.temp); + elk_MOV(p, c->reg.temp, c->reg.temp); } - brw_ff_gs_ff_sync(c, 1); + elk_ff_gs_ff_sync(c, 1); - brw_ff_gs_overwrite_header_dw2_from_r0(c); + elk_ff_gs_overwrite_header_dw2_from_r0(c); switch (num_verts) { case 1: - brw_ff_gs_offset_header_dw2(c, + elk_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START | URB_WRITE_PRIM_END); - brw_ff_gs_emit_vue(c, c->reg.vertex[0], true); + elk_ff_gs_emit_vue(c, c->reg.vertex[0], true); break; case 2: - brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); - brw_ff_gs_emit_vue(c, c->reg.vertex[0], false); - brw_ff_gs_offset_header_dw2(c, + elk_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); + elk_ff_gs_emit_vue(c, c->reg.vertex[0], false); + elk_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END - URB_WRITE_PRIM_START); - brw_ff_gs_emit_vue(c, c->reg.vertex[1], true); + elk_ff_gs_emit_vue(c, c->reg.vertex[1], true); break; case 3: if (check_edge_flags) { /* Only emit vertices 0 and 1 if this is the first triangle of the * polygon. Otherwise they are redundant. */ - brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), + elk_AND(p, retype(elk_null_reg(), ELK_REGISTER_TYPE_UD), get_element_ud(c->reg.R0, 2), - brw_imm_ud(BRW_GS_EDGE_INDICATOR_0)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_IF(p, BRW_EXECUTE_1); + elk_imm_ud(ELK_GS_EDGE_INDICATOR_0)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_IF(p, ELK_EXECUTE_1); } - brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); - brw_ff_gs_emit_vue(c, c->reg.vertex[0], false); - brw_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START); - brw_ff_gs_emit_vue(c, c->reg.vertex[1], false); + elk_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); + elk_ff_gs_emit_vue(c, c->reg.vertex[0], false); + elk_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START); + elk_ff_gs_emit_vue(c, c->reg.vertex[1], false); if (check_edge_flags) { - brw_ENDIF(p); + elk_ENDIF(p); /* Only emit vertex 2 in PRIM_END mode if this is the last triangle * of the polygon. Otherwise leave the primitive incomplete because * there are more polygon vertices coming. */ - brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), + elk_AND(p, retype(elk_null_reg(), ELK_REGISTER_TYPE_UD), get_element_ud(c->reg.R0, 2), - brw_imm_ud(BRW_GS_EDGE_INDICATOR_1)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); - brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); + elk_imm_ud(ELK_GS_EDGE_INDICATOR_1)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); + elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL); } - brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_ff_gs_emit_vue(c, c->reg.vertex[2], true); + elk_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_ff_gs_emit_vue(c, c->reg.vertex[2], true); break; } } const unsigned * -brw_compile_ff_gs_prog(struct brw_compiler *compiler, +elk_compile_ff_gs_prog(struct elk_compiler *compiler, void *mem_ctx, - const struct brw_ff_gs_prog_key *key, - struct brw_ff_gs_prog_data *prog_data, + const struct elk_ff_gs_prog_key *key, + struct elk_ff_gs_prog_data *prog_data, struct intel_vue_map *vue_map, unsigned *final_assembly_size) { - struct brw_ff_gs_compile c; + struct elk_ff_gs_compile c; const GLuint *program; memset(&c, 0, sizeof(c)); @@ -581,14 +581,14 @@ brw_compile_ff_gs_prog(struct brw_compiler *compiler, /* Begin the compilation: */ - brw_init_codegen(&compiler->isa, &c.func, mem_ctx); + elk_init_codegen(&compiler->isa, &c.func, mem_ctx); c.func.single_program_flow = 1; /* For some reason the thread is spawned with only 4 channels * unmasked. */ - brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE); + elk_set_default_mask_control(&c.func, ELK_MASK_DISABLE); if (compiler->devinfo->ver >= 6) { unsigned num_verts; @@ -631,28 +631,28 @@ brw_compile_ff_gs_prog(struct brw_compiler *compiler, */ switch (key->primitive) { case _3DPRIM_QUADLIST: - brw_ff_gs_quads( &c, key ); + elk_ff_gs_quads( &c, key ); break; case _3DPRIM_QUADSTRIP: - brw_ff_gs_quad_strip( &c, key ); + elk_ff_gs_quad_strip( &c, key ); break; case _3DPRIM_LINELOOP: - brw_ff_gs_lines( &c ); + elk_ff_gs_lines( &c ); break; default: return NULL; } } - brw_compact_instructions(&c.func, 0, NULL); + elk_compact_instructions(&c.func, 0, NULL); /* get the program */ - program = brw_get_program(&c.func, final_assembly_size); + program = elk_get_program(&c.func, final_assembly_size); if (INTEL_DEBUG(DEBUG_GS)) { fprintf(stderr, "gs:\n"); - brw_disassemble_with_labels(&compiler->isa, c.func.store, + elk_disassemble_with_labels(&compiler->isa, c.func.store, 0, *final_assembly_size, stderr); fprintf(stderr, "\n"); } diff --git a/src/intel/compiler/elk/elk_compile_sf.c b/src/intel/compiler/elk/elk_compile_sf.c index 306b8f47f24..a41e2720465 100644 --- a/src/intel/compiler/elk/elk_compile_sf.c +++ b/src/intel/compiler/elk/elk_compile_sf.c @@ -28,37 +28,37 @@ #include "dev/intel_debug.h" -struct brw_sf_compile { - struct brw_codegen func; - struct brw_sf_prog_key key; - struct brw_sf_prog_data prog_data; +struct elk_sf_compile { + struct elk_codegen func; + struct elk_sf_prog_key key; + struct elk_sf_prog_data prog_data; - struct brw_reg pv; - struct brw_reg det; - struct brw_reg dx0; - struct brw_reg dx2; - struct brw_reg dy0; - struct brw_reg dy2; + struct elk_reg pv; + struct elk_reg det; + struct elk_reg dx0; + struct elk_reg dx2; + struct elk_reg dy0; + struct elk_reg dy2; /* z and 1/w passed in separately: */ - struct brw_reg z[3]; - struct brw_reg inv_w[3]; + struct elk_reg z[3]; + struct elk_reg inv_w[3]; /* The vertices: */ - struct brw_reg vert[3]; + struct elk_reg vert[3]; /* Temporaries, allocated after last vertex reg. */ - struct brw_reg inv_det; - struct brw_reg a1_sub_a0; - struct brw_reg a2_sub_a0; - struct brw_reg tmp; + struct elk_reg inv_det; + struct elk_reg a1_sub_a0; + struct elk_reg a2_sub_a0; + struct elk_reg tmp; - struct brw_reg m1Cx; - struct brw_reg m2Cy; - struct brw_reg m3C0; + struct elk_reg m1Cx; + struct elk_reg m2Cy; + struct elk_reg m3C0; GLuint nr_verts; GLuint nr_attr_regs; @@ -74,7 +74,7 @@ struct brw_sf_compile { /** * Determine the vue slot corresponding to the given half of the given register. */ -static inline int vert_reg_to_vue_slot(struct brw_sf_compile *c, GLuint reg, +static inline int vert_reg_to_vue_slot(struct elk_sf_compile *c, GLuint reg, int half) { return (reg + c->urb_entry_read_offset) * 2 + half; @@ -85,7 +85,7 @@ static inline int vert_reg_to_vue_slot(struct brw_sf_compile *c, GLuint reg, * register. half=0 means the first half of a register, half=1 means the * second half. */ -static inline int vert_reg_to_varying(struct brw_sf_compile *c, GLuint reg, +static inline int vert_reg_to_varying(struct elk_sf_compile *c, GLuint reg, int half) { int vue_slot = vert_reg_to_vue_slot(c, reg, half); @@ -95,21 +95,21 @@ static inline int vert_reg_to_varying(struct brw_sf_compile *c, GLuint reg, /** * Determine the register corresponding to the given vue slot */ -static struct brw_reg get_vue_slot(struct brw_sf_compile *c, - struct brw_reg vert, +static struct elk_reg get_vue_slot(struct elk_sf_compile *c, + struct elk_reg vert, int vue_slot) { GLuint off = vue_slot / 2 - c->urb_entry_read_offset; GLuint sub = vue_slot % 2; - return brw_vec4_grf(vert.nr + off, sub * 4); + return elk_vec4_grf(vert.nr + off, sub * 4); } /** * Determine the register corresponding to the given varying. */ -static struct brw_reg get_varying(struct brw_sf_compile *c, - struct brw_reg vert, +static struct elk_reg get_varying(struct elk_sf_compile *c, + struct elk_reg vert, GLuint varying) { int vue_slot = c->vue_map.varying_to_slot[varying]; @@ -118,7 +118,7 @@ static struct brw_reg get_varying(struct brw_sf_compile *c, } static bool -have_attr(struct brw_sf_compile *c, GLuint attr) +have_attr(struct elk_sf_compile *c, GLuint attr) { return (c->key.attrs & BITFIELD64_BIT(attr)) ? 1 : 0; } @@ -126,30 +126,30 @@ have_attr(struct brw_sf_compile *c, GLuint attr) /*********************************************************************** * Twoside lighting */ -static void copy_bfc( struct brw_sf_compile *c, - struct brw_reg vert ) +static void copy_bfc( struct elk_sf_compile *c, + struct elk_reg vert ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint i; for (i = 0; i < 2; i++) { if (have_attr(c, VARYING_SLOT_COL0+i) && have_attr(c, VARYING_SLOT_BFC0+i)) - brw_MOV(p, + elk_MOV(p, get_varying(c, vert, VARYING_SLOT_COL0+i), get_varying(c, vert, VARYING_SLOT_BFC0+i)); } } -static void do_twoside_color( struct brw_sf_compile *c ) +static void do_twoside_color( struct elk_sf_compile *c ) { - struct brw_codegen *p = &c->func; - GLuint backface_conditional = c->key.frontface_ccw ? BRW_CONDITIONAL_G : BRW_CONDITIONAL_L; + struct elk_codegen *p = &c->func; + GLuint backface_conditional = c->key.frontface_ccw ? ELK_CONDITIONAL_G : ELK_CONDITIONAL_L; /* Already done in clip program: */ - if (c->key.primitive == BRW_SF_PRIM_UNFILLED_TRIS) + if (c->key.primitive == ELK_SF_PRIM_UNFILLED_TRIS) return; /* If the vertex shader provides backface color, do the selection. The VS @@ -160,13 +160,13 @@ static void do_twoside_color( struct brw_sf_compile *c ) !(have_attr(c, VARYING_SLOT_COL1) && have_attr(c, VARYING_SLOT_BFC1))) return; - /* Need to use BRW_EXECUTE_4 and also do an 4-wide compare in order + /* Need to use ELK_EXECUTE_4 and also do an 4-wide compare in order * to get all channels active inside the IF. In the clipping code * we run with NoMask, so it's not an option and we can use - * BRW_EXECUTE_1 for all comparisons. + * ELK_EXECUTE_1 for all comparisons. */ - brw_CMP(p, vec4(brw_null_reg()), backface_conditional, c->det, brw_imm_f(0)); - brw_IF(p, BRW_EXECUTE_4); + elk_CMP(p, vec4(elk_null_reg()), backface_conditional, c->det, elk_imm_f(0)); + elk_IF(p, ELK_EXECUTE_4); { switch (c->nr_verts) { case 3: copy_bfc(c, c->vert[2]); FALLTHROUGH; @@ -174,7 +174,7 @@ static void do_twoside_color( struct brw_sf_compile *c ) case 1: copy_bfc(c, c->vert[0]); } } - brw_ENDIF(p); + elk_ENDIF(p); } @@ -183,23 +183,23 @@ static void do_twoside_color( struct brw_sf_compile *c ) * Flat shading */ -static void copy_flatshaded_attributes(struct brw_sf_compile *c, - struct brw_reg dst, - struct brw_reg src) +static void copy_flatshaded_attributes(struct elk_sf_compile *c, + struct elk_reg dst, + struct elk_reg src) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; int i; for (i = 0; i < c->vue_map.num_slots; i++) { if (c->key.interp_mode[i] == INTERP_MODE_FLAT) { - brw_MOV(p, + elk_MOV(p, get_vue_slot(c, dst, i), get_vue_slot(c, src, i)); } } } -static int count_flatshaded_attributes(struct brw_sf_compile *c) +static int count_flatshaded_attributes(struct elk_sf_compile *c) { int i; int count = 0; @@ -217,15 +217,15 @@ static int count_flatshaded_attributes(struct brw_sf_compile *c) * vertices are ordered according to y-coordinate before reaching this * point, so the PV could be anywhere. */ -static void do_flatshade_triangle( struct brw_sf_compile *c ) +static void do_flatshade_triangle( struct elk_sf_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint nr; GLuint jmpi = 1; /* Already done in clip program: */ - if (c->key.primitive == BRW_SF_PRIM_UNFILLED_TRIS) + if (c->key.primitive == ELK_SF_PRIM_UNFILLED_TRIS) return; if (p->devinfo->ver == 5) @@ -233,31 +233,31 @@ static void do_flatshade_triangle( struct brw_sf_compile *c ) nr = count_flatshaded_attributes(c); - brw_MUL(p, c->pv, c->pv, brw_imm_d(jmpi*(nr*2+1))); - brw_JMPI(p, c->pv, BRW_PREDICATE_NONE); + elk_MUL(p, c->pv, c->pv, elk_imm_d(jmpi*(nr*2+1))); + elk_JMPI(p, c->pv, ELK_PREDICATE_NONE); copy_flatshaded_attributes(c, c->vert[1], c->vert[0]); copy_flatshaded_attributes(c, c->vert[2], c->vert[0]); - brw_JMPI(p, brw_imm_d(jmpi*(nr*4+1)), BRW_PREDICATE_NONE); + elk_JMPI(p, elk_imm_d(jmpi*(nr*4+1)), ELK_PREDICATE_NONE); copy_flatshaded_attributes(c, c->vert[0], c->vert[1]); copy_flatshaded_attributes(c, c->vert[2], c->vert[1]); - brw_JMPI(p, brw_imm_d(jmpi*nr*2), BRW_PREDICATE_NONE); + elk_JMPI(p, elk_imm_d(jmpi*nr*2), ELK_PREDICATE_NONE); copy_flatshaded_attributes(c, c->vert[0], c->vert[2]); copy_flatshaded_attributes(c, c->vert[1], c->vert[2]); } -static void do_flatshade_line( struct brw_sf_compile *c ) +static void do_flatshade_line( struct elk_sf_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint nr; GLuint jmpi = 1; /* Already done in clip program: */ - if (c->key.primitive == BRW_SF_PRIM_UNFILLED_TRIS) + if (c->key.primitive == ELK_SF_PRIM_UNFILLED_TRIS) return; if (p->devinfo->ver == 5) @@ -265,11 +265,11 @@ static void do_flatshade_line( struct brw_sf_compile *c ) nr = count_flatshaded_attributes(c); - brw_MUL(p, c->pv, c->pv, brw_imm_d(jmpi*(nr+1))); - brw_JMPI(p, c->pv, BRW_PREDICATE_NONE); + elk_MUL(p, c->pv, c->pv, elk_imm_d(jmpi*(nr+1))); + elk_JMPI(p, c->pv, ELK_PREDICATE_NONE); copy_flatshaded_attributes(c, c->vert[1], c->vert[0]); - brw_JMPI(p, brw_imm_ud(jmpi*nr), BRW_PREDICATE_NONE); + elk_JMPI(p, elk_imm_ud(jmpi*nr), ELK_PREDICATE_NONE); copy_flatshaded_attributes(c, c->vert[0], c->vert[1]); } @@ -279,42 +279,42 @@ static void do_flatshade_line( struct brw_sf_compile *c ) */ -static void alloc_regs( struct brw_sf_compile *c ) +static void alloc_regs( struct elk_sf_compile *c ) { GLuint reg, i; /* Values computed by fixed function unit: */ - c->pv = retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_D); - c->det = brw_vec1_grf(1, 2); - c->dx0 = brw_vec1_grf(1, 3); - c->dx2 = brw_vec1_grf(1, 4); - c->dy0 = brw_vec1_grf(1, 5); - c->dy2 = brw_vec1_grf(1, 6); + c->pv = retype(elk_vec1_grf(1, 1), ELK_REGISTER_TYPE_D); + c->det = elk_vec1_grf(1, 2); + c->dx0 = elk_vec1_grf(1, 3); + c->dx2 = elk_vec1_grf(1, 4); + c->dy0 = elk_vec1_grf(1, 5); + c->dy2 = elk_vec1_grf(1, 6); /* z and 1/w passed in separately: */ - c->z[0] = brw_vec1_grf(2, 0); - c->inv_w[0] = brw_vec1_grf(2, 1); - c->z[1] = brw_vec1_grf(2, 2); - c->inv_w[1] = brw_vec1_grf(2, 3); - c->z[2] = brw_vec1_grf(2, 4); - c->inv_w[2] = brw_vec1_grf(2, 5); + c->z[0] = elk_vec1_grf(2, 0); + c->inv_w[0] = elk_vec1_grf(2, 1); + c->z[1] = elk_vec1_grf(2, 2); + c->inv_w[1] = elk_vec1_grf(2, 3); + c->z[2] = elk_vec1_grf(2, 4); + c->inv_w[2] = elk_vec1_grf(2, 5); /* The vertices: */ reg = 3; for (i = 0; i < c->nr_verts; i++) { - c->vert[i] = brw_vec8_grf(reg, 0); + c->vert[i] = elk_vec8_grf(reg, 0); reg += c->nr_attr_regs; } /* Temporaries, allocated after last vertex reg. */ - c->inv_det = brw_vec1_grf(reg, 0); reg++; - c->a1_sub_a0 = brw_vec8_grf(reg, 0); reg++; - c->a2_sub_a0 = brw_vec8_grf(reg, 0); reg++; - c->tmp = brw_vec8_grf(reg, 0); reg++; + c->inv_det = elk_vec1_grf(reg, 0); reg++; + c->a1_sub_a0 = elk_vec8_grf(reg, 0); reg++; + c->a2_sub_a0 = elk_vec8_grf(reg, 0); reg++; + c->tmp = elk_vec8_grf(reg, 0); reg++; /* Note grf allocation: */ @@ -324,41 +324,41 @@ static void alloc_regs( struct brw_sf_compile *c ) /* Outputs of this program - interpolation coefficients for * rasterization: */ - c->m1Cx = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 1, 0); - c->m2Cy = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 2, 0); - c->m3C0 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 3, 0); + c->m1Cx = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 1, 0); + c->m2Cy = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 2, 0); + c->m3C0 = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 3, 0); } -static void copy_z_inv_w( struct brw_sf_compile *c ) +static void copy_z_inv_w( struct elk_sf_compile *c ) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint i; /* Copy both scalars with a single MOV: */ for (i = 0; i < c->nr_verts; i++) - brw_MOV(p, vec2(suboffset(c->vert[i], 2)), vec2(c->z[i])); + elk_MOV(p, vec2(suboffset(c->vert[i], 2)), vec2(c->z[i])); } -static void invert_det( struct brw_sf_compile *c) +static void invert_det( struct elk_sf_compile *c) { /* Looks like we invert all 8 elements just to get 1/det in * position 2 !?! */ - gfx4_math(&c->func, + elk_gfx4_math(&c->func, c->inv_det, - BRW_MATH_FUNCTION_INV, + ELK_MATH_FUNCTION_INV, 0, c->det, - BRW_MATH_PRECISION_FULL); + ELK_MATH_PRECISION_FULL); } static bool -calculate_masks(struct brw_sf_compile *c, +calculate_masks(struct elk_sf_compile *c, GLuint reg, GLushort *pc, GLushort *pc_persp, @@ -380,7 +380,7 @@ calculate_masks(struct brw_sf_compile *c, /* Maybe only process one attribute on the final round: */ - if (vert_reg_to_varying(c, reg, 1) != BRW_VARYING_SLOT_COUNT) { + if (vert_reg_to_varying(c, reg, 1) != ELK_VARYING_SLOT_COUNT) { *pc |= 0xf0; interp = c->key.interp_mode[vert_reg_to_vue_slot(c, reg, 1)]; @@ -398,7 +398,7 @@ calculate_masks(struct brw_sf_compile *c, * (containing 2 attrs) to do point sprite coordinate replacement on. */ static uint16_t -calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg) +calculate_point_sprite_mask(struct elk_sf_compile *c, GLuint reg) { int varying1, varying2; uint16_t pc = 0; @@ -408,7 +408,7 @@ calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg) if (c->key.point_sprite_coord_replace & (1 << (varying1 - VARYING_SLOT_TEX0))) pc |= 0x0f; } - if (varying1 == BRW_VARYING_SLOT_PNTC) + if (varying1 == ELK_VARYING_SLOT_PNTC) pc |= 0x0f; varying2 = vert_reg_to_varying(c, reg, 1); @@ -417,32 +417,32 @@ calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg) VARYING_SLOT_TEX0))) pc |= 0xf0; } - if (varying2 == BRW_VARYING_SLOT_PNTC) + if (varying2 == ELK_VARYING_SLOT_PNTC) pc |= 0xf0; return pc; } static void -set_predicate_control_flag_value(struct brw_codegen *p, - struct brw_sf_compile *c, +set_predicate_control_flag_value(struct elk_codegen *p, + struct elk_sf_compile *c, unsigned value) { - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); if (value != 0xff) { if (value != c->flag_value) { - brw_MOV(p, brw_flag_reg(0, 0), brw_imm_uw(value)); + elk_MOV(p, elk_flag_reg(0, 0), elk_imm_uw(value)); c->flag_value = value; } - brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); + elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL); } } -static void brw_emit_tri_setup(struct brw_sf_compile *c, bool allocate) +static void elk_emit_tri_setup(struct elk_sf_compile *c, bool allocate) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint i; c->flag_value = 0xff; @@ -465,18 +465,18 @@ static void brw_emit_tri_setup(struct brw_sf_compile *c, bool allocate) { /* Pair of incoming attributes: */ - struct brw_reg a0 = offset(c->vert[0], i); - struct brw_reg a1 = offset(c->vert[1], i); - struct brw_reg a2 = offset(c->vert[2], i); + struct elk_reg a0 = offset(c->vert[0], i); + struct elk_reg a1 = offset(c->vert[1], i); + struct elk_reg a2 = offset(c->vert[2], i); GLushort pc, pc_persp, pc_linear; bool last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear); if (pc_persp) { set_predicate_control_flag_value(p, c, pc_persp); - brw_MUL(p, a0, a0, c->inv_w[0]); - brw_MUL(p, a1, a1, c->inv_w[1]); - brw_MUL(p, a2, a2, c->inv_w[2]); + elk_MUL(p, a0, a0, c->inv_w[0]); + elk_MUL(p, a1, a1, c->inv_w[1]); + elk_MUL(p, a2, a2, c->inv_w[2]); } @@ -486,52 +486,52 @@ static void brw_emit_tri_setup(struct brw_sf_compile *c, bool allocate) { set_predicate_control_flag_value(p, c, pc_linear); - brw_ADD(p, c->a1_sub_a0, a1, negate(a0)); - brw_ADD(p, c->a2_sub_a0, a2, negate(a0)); + elk_ADD(p, c->a1_sub_a0, a1, negate(a0)); + elk_ADD(p, c->a2_sub_a0, a2, negate(a0)); /* calculate dA/dx */ - brw_MUL(p, brw_null_reg(), c->a1_sub_a0, c->dy2); - brw_MAC(p, c->tmp, c->a2_sub_a0, negate(c->dy0)); - brw_MUL(p, c->m1Cx, c->tmp, c->inv_det); + elk_MUL(p, elk_null_reg(), c->a1_sub_a0, c->dy2); + elk_MAC(p, c->tmp, c->a2_sub_a0, negate(c->dy0)); + elk_MUL(p, c->m1Cx, c->tmp, c->inv_det); /* calculate dA/dy */ - brw_MUL(p, brw_null_reg(), c->a2_sub_a0, c->dx0); - brw_MAC(p, c->tmp, c->a1_sub_a0, negate(c->dx2)); - brw_MUL(p, c->m2Cy, c->tmp, c->inv_det); + elk_MUL(p, elk_null_reg(), c->a2_sub_a0, c->dx0); + elk_MAC(p, c->tmp, c->a1_sub_a0, negate(c->dx2)); + elk_MUL(p, c->m2Cy, c->tmp, c->inv_det); } { set_predicate_control_flag_value(p, c, pc); /* start point for interpolation */ - brw_MOV(p, c->m3C0, a0); + elk_MOV(p, c->m3C0, a0); /* Copy m0..m3 to URB. m0 is implicitly copied from r0 in * the send instruction: */ - brw_urb_WRITE(p, - brw_null_reg(), + elk_urb_WRITE(p, + elk_null_reg(), 0, - brw_vec8_grf(0, 0), /* r0, will be copied to m0 */ - last ? BRW_URB_WRITE_EOT_COMPLETE - : BRW_URB_WRITE_NO_FLAGS, + elk_vec8_grf(0, 0), /* r0, will be copied to m0 */ + last ? ELK_URB_WRITE_EOT_COMPLETE + : ELK_URB_WRITE_NO_FLAGS, 4, /* msg len */ 0, /* response len */ i*4, /* offset */ - BRW_URB_SWIZZLE_TRANSPOSE); /* XXX: Swizzle control "SF to windower" */ + ELK_URB_SWIZZLE_TRANSPOSE); /* XXX: Swizzle control "SF to windower" */ } } - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); } -static void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate) +static void elk_emit_line_setup(struct elk_sf_compile *c, bool allocate) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint i; c->flag_value = 0xff; @@ -550,16 +550,16 @@ static void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate) { /* Pair of incoming attributes: */ - struct brw_reg a0 = offset(c->vert[0], i); - struct brw_reg a1 = offset(c->vert[1], i); + struct elk_reg a0 = offset(c->vert[0], i); + struct elk_reg a1 = offset(c->vert[1], i); GLushort pc, pc_persp, pc_linear; bool last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear); if (pc_persp) { set_predicate_control_flag_value(p, c, pc_persp); - brw_MUL(p, a0, a0, c->inv_w[0]); - brw_MUL(p, a1, a1, c->inv_w[1]); + elk_MUL(p, a0, a0, c->inv_w[0]); + elk_MUL(p, a1, a1, c->inv_w[1]); } /* Calculate coefficients for position, color: @@ -567,13 +567,13 @@ static void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate) if (pc_linear) { set_predicate_control_flag_value(p, c, pc_linear); - brw_ADD(p, c->a1_sub_a0, a1, negate(a0)); + elk_ADD(p, c->a1_sub_a0, a1, negate(a0)); - brw_MUL(p, c->tmp, c->a1_sub_a0, c->dx0); - brw_MUL(p, c->m1Cx, c->tmp, c->inv_det); + elk_MUL(p, c->tmp, c->a1_sub_a0, c->dx0); + elk_MUL(p, c->m1Cx, c->tmp, c->inv_det); - brw_MUL(p, c->tmp, c->a1_sub_a0, c->dy0); - brw_MUL(p, c->m2Cy, c->tmp, c->inv_det); + elk_MUL(p, c->tmp, c->a1_sub_a0, c->dy0); + elk_MUL(p, c->m2Cy, c->tmp, c->inv_det); } { @@ -581,29 +581,29 @@ static void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate) /* start point for interpolation */ - brw_MOV(p, c->m3C0, a0); + elk_MOV(p, c->m3C0, a0); /* Copy m0..m3 to URB. */ - brw_urb_WRITE(p, - brw_null_reg(), + elk_urb_WRITE(p, + elk_null_reg(), 0, - brw_vec8_grf(0, 0), - last ? BRW_URB_WRITE_EOT_COMPLETE - : BRW_URB_WRITE_NO_FLAGS, + elk_vec8_grf(0, 0), + last ? ELK_URB_WRITE_EOT_COMPLETE + : ELK_URB_WRITE_NO_FLAGS, 4, /* msg len */ 0, /* response len */ i*4, /* urb destination offset */ - BRW_URB_SWIZZLE_TRANSPOSE); + ELK_URB_SWIZZLE_TRANSPOSE); } } - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); } -static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate) +static void elk_emit_point_sprite_setup(struct elk_sf_compile *c, bool allocate) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint i; c->flag_value = 0xff; @@ -615,7 +615,7 @@ static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate) copy_z_inv_w(c); for (i = 0; i < c->nr_setup_regs; i++) { - struct brw_reg a0 = offset(c->vert[0], i); + struct elk_reg a0 = offset(c->vert[0], i); GLushort pc, pc_persp, pc_linear, pc_coord_replace; bool last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear); @@ -624,7 +624,7 @@ static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate) if (pc_persp) { set_predicate_control_flag_value(p, c, pc_persp); - brw_MUL(p, a0, a0, c->inv_w[0]); + elk_MUL(p, a0, a0, c->inv_w[0]); } /* Point sprite coordinate replacement: A texcoord with this @@ -635,67 +635,67 @@ static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate) if (pc_coord_replace) { set_predicate_control_flag_value(p, c, pc_coord_replace); /* Calculate 1.0/PointWidth */ - gfx4_math(&c->func, + elk_gfx4_math(&c->func, c->tmp, - BRW_MATH_FUNCTION_INV, + ELK_MATH_FUNCTION_INV, 0, c->dx0, - BRW_MATH_PRECISION_FULL); + ELK_MATH_PRECISION_FULL); - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); /* dA/dx, dA/dy */ - brw_MOV(p, c->m1Cx, brw_imm_f(0.0)); - brw_MOV(p, c->m2Cy, brw_imm_f(0.0)); - brw_MOV(p, brw_writemask(c->m1Cx, WRITEMASK_X), c->tmp); + elk_MOV(p, c->m1Cx, elk_imm_f(0.0)); + elk_MOV(p, c->m2Cy, elk_imm_f(0.0)); + elk_MOV(p, elk_writemask(c->m1Cx, WRITEMASK_X), c->tmp); if (c->key.sprite_origin_lower_left) { - brw_MOV(p, brw_writemask(c->m2Cy, WRITEMASK_Y), negate(c->tmp)); + elk_MOV(p, elk_writemask(c->m2Cy, WRITEMASK_Y), negate(c->tmp)); } else { - brw_MOV(p, brw_writemask(c->m2Cy, WRITEMASK_Y), c->tmp); + elk_MOV(p, elk_writemask(c->m2Cy, WRITEMASK_Y), c->tmp); } /* attribute constant offset */ - brw_MOV(p, c->m3C0, brw_imm_f(0.0)); + elk_MOV(p, c->m3C0, elk_imm_f(0.0)); if (c->key.sprite_origin_lower_left) { - brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_YW), brw_imm_f(1.0)); + elk_MOV(p, elk_writemask(c->m3C0, WRITEMASK_YW), elk_imm_f(1.0)); } else { - brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_W), brw_imm_f(1.0)); + elk_MOV(p, elk_writemask(c->m3C0, WRITEMASK_W), elk_imm_f(1.0)); } - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_1); } if (pc & ~pc_coord_replace) { set_predicate_control_flag_value(p, c, pc & ~pc_coord_replace); - brw_MOV(p, c->m1Cx, brw_imm_ud(0)); - brw_MOV(p, c->m2Cy, brw_imm_ud(0)); - brw_MOV(p, c->m3C0, a0); /* constant value */ + elk_MOV(p, c->m1Cx, elk_imm_ud(0)); + elk_MOV(p, c->m2Cy, elk_imm_ud(0)); + elk_MOV(p, c->m3C0, a0); /* constant value */ } set_predicate_control_flag_value(p, c, pc); /* Copy m0..m3 to URB. */ - brw_urb_WRITE(p, - brw_null_reg(), + elk_urb_WRITE(p, + elk_null_reg(), 0, - brw_vec8_grf(0, 0), - last ? BRW_URB_WRITE_EOT_COMPLETE - : BRW_URB_WRITE_NO_FLAGS, + elk_vec8_grf(0, 0), + last ? ELK_URB_WRITE_EOT_COMPLETE + : ELK_URB_WRITE_NO_FLAGS, 4, /* msg len */ 0, /* response len */ i*4, /* urb destination offset */ - BRW_URB_SWIZZLE_TRANSPOSE); + ELK_URB_SWIZZLE_TRANSPOSE); } - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); } /* Points setup - several simplifications as all attributes are * constant across the face of the point (point sprites excluded!) */ -static void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate) +static void elk_emit_point_setup(struct elk_sf_compile *c, bool allocate) { - struct brw_codegen *p = &c->func; + struct elk_codegen *p = &c->func; GLuint i; c->flag_value = 0xff; @@ -706,12 +706,12 @@ static void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate) copy_z_inv_w(c); - brw_MOV(p, c->m1Cx, brw_imm_ud(0)); /* zero - move out of loop */ - brw_MOV(p, c->m2Cy, brw_imm_ud(0)); /* zero - move out of loop */ + elk_MOV(p, c->m1Cx, elk_imm_ud(0)); /* zero - move out of loop */ + elk_MOV(p, c->m2Cy, elk_imm_ud(0)); /* zero - move out of loop */ for (i = 0; i < c->nr_setup_regs; i++) { - struct brw_reg a0 = offset(c->vert[0], i); + struct elk_reg a0 = offset(c->vert[0], i); GLushort pc, pc_persp, pc_linear; bool last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear); @@ -721,7 +721,7 @@ static void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate) * fragment shader will be expecting it: */ set_predicate_control_flag_value(p, c, pc_persp); - brw_MUL(p, a0, a0, c->inv_w[0]); + elk_MUL(p, a0, a0, c->inv_w[0]); } @@ -732,89 +732,89 @@ static void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate) { set_predicate_control_flag_value(p, c, pc); - brw_MOV(p, c->m3C0, a0); /* constant value */ + elk_MOV(p, c->m3C0, a0); /* constant value */ /* Copy m0..m3 to URB. */ - brw_urb_WRITE(p, - brw_null_reg(), + elk_urb_WRITE(p, + elk_null_reg(), 0, - brw_vec8_grf(0, 0), - last ? BRW_URB_WRITE_EOT_COMPLETE - : BRW_URB_WRITE_NO_FLAGS, + elk_vec8_grf(0, 0), + last ? ELK_URB_WRITE_EOT_COMPLETE + : ELK_URB_WRITE_NO_FLAGS, 4, /* msg len */ 0, /* response len */ i*4, /* urb destination offset */ - BRW_URB_SWIZZLE_TRANSPOSE); + ELK_URB_SWIZZLE_TRANSPOSE); } } - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); } -static void brw_emit_anyprim_setup( struct brw_sf_compile *c ) +static void elk_emit_anyprim_setup( struct elk_sf_compile *c ) { - struct brw_codegen *p = &c->func; - struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0); - struct brw_reg payload_attr = get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0); - struct brw_reg primmask; + struct elk_codegen *p = &c->func; + struct elk_reg payload_prim = elk_uw1_reg(ELK_GENERAL_REGISTER_FILE, 1, 0); + struct elk_reg payload_attr = get_element_ud(elk_vec1_reg(ELK_GENERAL_REGISTER_FILE, 1, 0), 0); + struct elk_reg primmask; int jmp; - struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); + struct elk_reg v1_null_ud = vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD)); c->nr_verts = 3; alloc_regs(c); - primmask = retype(get_element(c->tmp, 0), BRW_REGISTER_TYPE_UD); + primmask = retype(get_element(c->tmp, 0), ELK_REGISTER_TYPE_UD); - brw_MOV(p, primmask, brw_imm_ud(1)); - brw_SHL(p, primmask, primmask, payload_prim); + elk_MOV(p, primmask, elk_imm_ud(1)); + elk_SHL(p, primmask, primmask, payload_prim); - brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_TRILIST) | + elk_AND(p, v1_null_ud, primmask, elk_imm_ud((1<<_3DPRIM_TRILIST) | (1<<_3DPRIM_TRISTRIP) | (1<<_3DPRIM_TRIFAN) | (1<<_3DPRIM_TRISTRIP_REVERSE) | (1<<_3DPRIM_POLYGON) | (1<<_3DPRIM_RECTLIST) | (1<<_3DPRIM_TRIFAN_NOSTIPPLE))); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z); - jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; - brw_emit_tri_setup(c, false); - brw_land_fwd_jump(p, jmp); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_Z); + jmp = elk_JMPI(p, elk_imm_d(0), ELK_PREDICATE_NORMAL) - p->store; + elk_emit_tri_setup(c, false); + elk_land_fwd_jump(p, jmp); - brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_LINELIST) | + elk_AND(p, v1_null_ud, primmask, elk_imm_ud((1<<_3DPRIM_LINELIST) | (1<<_3DPRIM_LINESTRIP) | (1<<_3DPRIM_LINELOOP) | (1<<_3DPRIM_LINESTRIP_CONT) | (1<<_3DPRIM_LINESTRIP_BF) | (1<<_3DPRIM_LINESTRIP_CONT_BF))); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z); - jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; - brw_emit_line_setup(c, false); - brw_land_fwd_jump(p, jmp); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_Z); + jmp = elk_JMPI(p, elk_imm_d(0), ELK_PREDICATE_NORMAL) - p->store; + elk_emit_line_setup(c, false); + elk_land_fwd_jump(p, jmp); - brw_AND(p, v1_null_ud, payload_attr, brw_imm_ud(1<devinfo, brw_last_inst, BRW_CONDITIONAL_Z); - jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; - brw_emit_point_sprite_setup(c, false); - brw_land_fwd_jump(p, jmp); + elk_AND(p, v1_null_ud, payload_attr, elk_imm_ud(1<devinfo, elk_last_inst, ELK_CONDITIONAL_Z); + jmp = elk_JMPI(p, elk_imm_d(0), ELK_PREDICATE_NORMAL) - p->store; + elk_emit_point_sprite_setup(c, false); + elk_land_fwd_jump(p, jmp); - brw_emit_point_setup( c, false ); + elk_emit_point_setup( c, false ); } const unsigned * -brw_compile_sf(const struct brw_compiler *compiler, +elk_compile_sf(const struct elk_compiler *compiler, void *mem_ctx, - const struct brw_sf_prog_key *key, - struct brw_sf_prog_data *prog_data, + const struct elk_sf_prog_key *key, + struct elk_sf_prog_data *prog_data, struct intel_vue_map *vue_map, unsigned *final_assembly_size) { - struct brw_sf_compile c; + struct elk_sf_compile c; memset(&c, 0, sizeof(c)); /* Begin the compilation: */ - brw_init_codegen(&compiler->isa, &c.func, mem_ctx); + elk_init_codegen(&compiler->isa, &c.func, mem_ctx); c.key = *key; c.vue_map = *vue_map; @@ -825,10 +825,10 @@ brw_compile_sf(const struct brw_compiler *compiler, * it manually to let SF shader generate the needed interpolation * coefficient for FS shader. */ - c.vue_map.varying_to_slot[BRW_VARYING_SLOT_PNTC] = c.vue_map.num_slots; - c.vue_map.slot_to_varying[c.vue_map.num_slots++] = BRW_VARYING_SLOT_PNTC; + c.vue_map.varying_to_slot[ELK_VARYING_SLOT_PNTC] = c.vue_map.num_slots; + c.vue_map.slot_to_varying[c.vue_map.num_slots++] = ELK_VARYING_SLOT_PNTC; } - c.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET; + c.urb_entry_read_offset = ELK_SF_URB_ENTRY_READ_OFFSET; c.nr_attr_regs = (c.vue_map.num_slots + 1)/2 - c.urb_entry_read_offset; c.nr_setup_regs = c.nr_attr_regs; @@ -838,24 +838,24 @@ brw_compile_sf(const struct brw_compiler *compiler, /* Which primitive? Or all three? */ switch (key->primitive) { - case BRW_SF_PRIM_TRIANGLES: + case ELK_SF_PRIM_TRIANGLES: c.nr_verts = 3; - brw_emit_tri_setup( &c, true ); + elk_emit_tri_setup( &c, true ); break; - case BRW_SF_PRIM_LINES: + case ELK_SF_PRIM_LINES: c.nr_verts = 2; - brw_emit_line_setup( &c, true ); + elk_emit_line_setup( &c, true ); break; - case BRW_SF_PRIM_POINTS: + case ELK_SF_PRIM_POINTS: c.nr_verts = 1; if (key->do_point_sprite) - brw_emit_point_sprite_setup( &c, true ); + elk_emit_point_sprite_setup( &c, true ); else - brw_emit_point_setup( &c, true ); + elk_emit_point_setup( &c, true ); break; - case BRW_SF_PRIM_UNFILLED_TRIS: + case ELK_SF_PRIM_UNFILLED_TRIS: c.nr_verts = 3; - brw_emit_anyprim_setup( &c ); + elk_emit_anyprim_setup( &c ); break; default: unreachable("not reached"); @@ -864,15 +864,15 @@ brw_compile_sf(const struct brw_compiler *compiler, /* FINISHME: SF programs use calculated jumps (i.e., JMPI with a register * source). Compacting would be difficult. */ - /* brw_compact_instructions(&c.func, 0, 0, NULL); */ + /* elk_compact_instructions(&c.func, 0, 0, NULL); */ *prog_data = c.prog_data; - const unsigned *program = brw_get_program(&c.func, final_assembly_size); + const unsigned *program = elk_get_program(&c.func, final_assembly_size); if (INTEL_DEBUG(DEBUG_SF)) { fprintf(stderr, "sf:\n"); - brw_disassemble_with_labels(&compiler->isa, + elk_disassemble_with_labels(&compiler->isa, program, 0, *final_assembly_size, stderr); fprintf(stderr, "\n"); } diff --git a/src/intel/compiler/elk/elk_compiler.c b/src/intel/compiler/elk/elk_compiler.c index 3cc2490bd7b..a0c657bd4d7 100644 --- a/src/intel/compiler/elk/elk_compiler.c +++ b/src/intel/compiler/elk/elk_compiler.c @@ -77,12 +77,12 @@ nir_divergence_single_patch_per_tes_subgroup | \ nir_divergence_shader_record_ptr_uniform) -const struct nir_shader_compiler_options brw_scalar_nir_options = { +const struct nir_shader_compiler_options elk_scalar_nir_options = { COMMON_OPTIONS, COMMON_SCALAR_OPTIONS, }; -const struct nir_shader_compiler_options brw_vector_nir_options = { +const struct nir_shader_compiler_options elk_vector_nir_options = { COMMON_OPTIONS, /* In the vec4 backend, our dpN instruction replicates its result to all the @@ -102,20 +102,20 @@ const struct nir_shader_compiler_options brw_vector_nir_options = { .max_unroll_iterations = 32, }; -struct brw_compiler * -brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) +struct elk_compiler * +elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) { assert(devinfo->ver <= 8); - struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler); + struct elk_compiler *compiler = rzalloc(mem_ctx, struct elk_compiler); compiler->devinfo = devinfo; - brw_init_isa_info(&compiler->isa, devinfo); + elk_init_isa_info(&compiler->isa, devinfo); - brw_fs_alloc_reg_sets(compiler); + elk_fs_alloc_reg_sets(compiler); if (devinfo->ver < 8) - brw_vec4_alloc_reg_set(compiler); + elk_vec4_alloc_reg_set(compiler); compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false); @@ -175,10 +175,10 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) rzalloc(compiler, struct nir_shader_compiler_options); bool is_scalar = compiler->scalar_stage[i]; if (is_scalar) { - *nir_options = brw_scalar_nir_options; + *nir_options = elk_scalar_nir_options; int64_options |= nir_lower_usub_sat64; } else { - *nir_options = brw_vector_nir_options; + *nir_options = elk_vector_nir_options; } /* Prior to Gfx6, there are no three source operations, and Gfx11 loses @@ -214,7 +214,7 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT; nir_options->force_indirect_unrolling |= - brw_nir_no_indirect_mask(compiler, i); + elk_nir_no_indirect_mask(compiler, i); nir_options->force_indirect_unrolling_sampler = devinfo->ver < 7; if (compiler->use_tcs_multi_patch) { @@ -240,7 +240,7 @@ insert_u64_bit(uint64_t *val, bool add) } uint64_t -brw_get_compiler_config_value(const struct brw_compiler *compiler) +elk_get_compiler_config_value(const struct elk_compiler *compiler) { uint64_t config = 0; unsigned bits = 0; @@ -271,40 +271,40 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler) } unsigned -brw_prog_data_size(gl_shader_stage stage) +elk_prog_data_size(gl_shader_stage stage) { static const size_t stage_sizes[] = { - [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data), - [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_data), - [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_data), - [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data), - [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data), - [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data), + [MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_data), + [MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_data), + [MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_data), + [MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_data), + [MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_data), + [MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_data), }; assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes)); return stage_sizes[stage]; } unsigned -brw_prog_key_size(gl_shader_stage stage) +elk_prog_key_size(gl_shader_stage stage) { static const size_t stage_sizes[] = { - [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key), - [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_key), - [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_key), - [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key), - [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key), - [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key), + [MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_key), + [MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_key), + [MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_key), + [MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_key), + [MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_key), + [MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_key), }; assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes)); return stage_sizes[stage]; } void -brw_write_shader_relocs(const struct brw_isa_info *isa, +elk_write_shader_relocs(const struct elk_isa_info *isa, void *program, - const struct brw_stage_prog_data *prog_data, - struct brw_shader_reloc_value *values, + const struct elk_stage_prog_data *prog_data, + struct elk_shader_reloc_value *values, unsigned num_values) { for (unsigned i = 0; i < prog_data->num_relocs; i++) { @@ -314,11 +314,11 @@ brw_write_shader_relocs(const struct brw_isa_info *isa, if (prog_data->relocs[i].id == values[j].id) { uint32_t value = values[j].value + prog_data->relocs[i].delta; switch (prog_data->relocs[i].type) { - case BRW_SHADER_RELOC_TYPE_U32: + case ELK_SHADER_RELOC_TYPE_U32: *(uint32_t *)dst = value; break; - case BRW_SHADER_RELOC_TYPE_MOV_IMM: - brw_update_reloc_imm(isa, dst, value); + case ELK_SHADER_RELOC_TYPE_MOV_IMM: + elk_update_reloc_imm(isa, dst, value); break; default: unreachable("Invalid relocation type"); diff --git a/src/intel/compiler/elk/elk_compiler.h b/src/intel/compiler/elk/elk_compiler.h index 146f80c8cde..908e5e12bc8 100644 --- a/src/intel/compiler/elk/elk_compiler.h +++ b/src/intel/compiler/elk/elk_compiler.h @@ -47,7 +47,7 @@ struct shader_info; struct nir_shader_compiler_options; typedef struct nir_shader nir_shader; -struct brw_compiler { +struct elk_compiler { const struct intel_device_info *devinfo; /* This lock must be taken if the compiler is to be modified in any way, @@ -55,7 +55,7 @@ struct brw_compiler { */ mtx_t mutex; - struct brw_isa_info isa; + struct elk_isa_info isa; struct { struct ra_regs *regs; @@ -151,12 +151,12 @@ struct brw_compiler { struct nir_shader *clc_shader; }; -#define brw_shader_debug_log(compiler, data, fmt, ... ) do { \ +#define elk_shader_debug_log(compiler, data, fmt, ... ) do { \ static unsigned id = 0; \ compiler->shader_debug_log(data, &id, fmt, ##__VA_ARGS__); \ } while (0) -#define brw_shader_perf_log(compiler, data, fmt, ... ) do { \ +#define elk_shader_perf_log(compiler, data, fmt, ... ) do { \ static unsigned id = 0; \ compiler->shader_perf_log(data, &id, fmt, ##__VA_ARGS__); \ } while (0) @@ -168,7 +168,7 @@ struct brw_compiler { * subgroup size of 32 but will act as if 16 or 24 of those channels are * disabled. */ -#define BRW_SUBGROUP_SIZE 32 +#define ELK_SUBGROUP_SIZE 32 /** * Program key structures. @@ -190,13 +190,13 @@ struct brw_compiler { * @{ */ -enum PACKED gfx6_gather_sampler_wa { - WA_SIGN = 1, /* whether we need to sign extend */ - WA_8BIT = 2, /* if we have an 8bit format needing wa */ - WA_16BIT = 4, /* if we have a 16bit format needing wa */ +enum PACKED elk_gfx6_gather_sampler_wa { + ELK_WA_SIGN = 1, /* whether we need to sign extend */ + ELK_WA_8BIT = 2, /* if we have an 8bit format needing wa */ + ELK_WA_16BIT = 4, /* if we have a 16bit format needing wa */ }; -#define BRW_MAX_SAMPLERS 32 +#define ELK_MAX_SAMPLERS 32 /* Provide explicit padding for each member, to ensure that the compiler * initializes every bit in the shader cache keys. The keys will be compared @@ -208,14 +208,14 @@ PRAGMA_DIAGNOSTIC_ERROR(-Wpadded) /** * Sampler information needed by VS, WM, and GS program cache keys. */ -struct brw_sampler_prog_key_data { +struct elk_sampler_prog_key_data { /** * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles. * * This field is not consumed by the back-end compiler and is only relevant * for the crocus OpenGL driver for Broadwell and earlier hardware. */ - uint16_t swizzles[BRW_MAX_SAMPLERS]; + uint16_t swizzles[ELK_MAX_SAMPLERS]; uint32_t gl_clamp_mask[3]; @@ -227,18 +227,18 @@ struct brw_sampler_prog_key_data { /** * For Sandybridge, which shader w/a we need for gather quirks. */ - enum gfx6_gather_sampler_wa gfx6_gather_wa[BRW_MAX_SAMPLERS]; + enum elk_gfx6_gather_sampler_wa gfx6_gather_wa[ELK_MAX_SAMPLERS]; }; -enum brw_robustness_flags { - BRW_ROBUSTNESS_UBO = BITFIELD_BIT(0), - BRW_ROBUSTNESS_SSBO = BITFIELD_BIT(1), +enum elk_robustness_flags { + ELK_ROBUSTNESS_UBO = BITFIELD_BIT(0), + ELK_ROBUSTNESS_SSBO = BITFIELD_BIT(1), }; -struct brw_base_prog_key { +struct elk_base_prog_key { unsigned program_string_id; - enum brw_robustness_flags robust_flags:2; + enum elk_robustness_flags robust_flags:2; unsigned padding:22; @@ -249,7 +249,7 @@ struct brw_base_prog_key { */ bool limit_trig_input_range; - struct brw_sampler_prog_key_data tex; + struct elk_sampler_prog_key_data tex; }; /** @@ -257,11 +257,11 @@ struct brw_base_prog_key { * or most 10_10_10_2 types. These flags enable various VS workarounds to * "fix" attributes at the beginning of shaders. */ -#define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */ -#define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */ -#define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */ -#define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */ -#define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */ +#define ELK_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */ +#define ELK_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */ +#define ELK_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */ +#define ELK_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */ +#define ELK_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */ /** * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range @@ -295,16 +295,16 @@ struct brw_base_prog_key { * allocate the number of binding table entries we will need once the bug is * fixed. */ -#define BRW_MAX_SOL_BINDINGS 64 +#define ELK_MAX_SOL_BINDINGS 64 /** The program key for Vertex Shaders. */ -struct brw_vs_prog_key { - struct brw_base_prog_key base; +struct elk_vs_prog_key { + struct elk_base_prog_key base; /** * Per-attribute workaround flags * - * For each attribute, a combination of BRW_ATTRIB_WA_*. + * For each attribute, a combination of ELK_ATTRIB_WA_*. * * For OpenGL, where we expose a maximum of 16 user input attributes * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan @@ -343,9 +343,9 @@ struct brw_vs_prog_key { }; /** The program key for Tessellation Control Shaders. */ -struct brw_tcs_prog_key +struct elk_tcs_prog_key { - struct brw_base_prog_key base; + struct elk_base_prog_key base; /** A bitfield of per-vertex outputs written. */ uint64_t outputs_written; @@ -362,19 +362,19 @@ struct brw_tcs_prog_key uint32_t padding:24; }; -#define BRW_MAX_TCS_INPUT_VERTICES (32) +#define ELK_MAX_TCS_INPUT_VERTICES (32) static inline uint32_t -brw_tcs_prog_key_input_vertices(const struct brw_tcs_prog_key *key) +elk_tcs_prog_key_input_vertices(const struct elk_tcs_prog_key *key) { return key->input_vertices != 0 ? - key->input_vertices : BRW_MAX_TCS_INPUT_VERTICES; + key->input_vertices : ELK_MAX_TCS_INPUT_VERTICES; } /** The program key for Tessellation Evaluation Shaders. */ -struct brw_tes_prog_key +struct elk_tes_prog_key { - struct brw_base_prog_key base; + struct elk_base_prog_key base; /** A bitfield of per-vertex inputs read. */ uint64_t inputs_read; @@ -395,9 +395,9 @@ struct brw_tes_prog_key }; /** The program key for Geometry Shaders. */ -struct brw_gs_prog_key +struct elk_gs_prog_key { - struct brw_base_prog_key base; + struct elk_base_prog_key base; /** * How many user clipping planes are being uploaded to the geometry shader @@ -411,19 +411,19 @@ struct brw_gs_prog_key unsigned padding:27; }; -enum brw_sf_primitive { - BRW_SF_PRIM_POINTS = 0, - BRW_SF_PRIM_LINES = 1, - BRW_SF_PRIM_TRIANGLES = 2, - BRW_SF_PRIM_UNFILLED_TRIS = 3, +enum elk_sf_primitive { + ELK_SF_PRIM_POINTS = 0, + ELK_SF_PRIM_LINES = 1, + ELK_SF_PRIM_TRIANGLES = 2, + ELK_SF_PRIM_UNFILLED_TRIS = 3, }; -struct brw_sf_prog_key { +struct elk_sf_prog_key { uint64_t attrs; bool contains_flat_varying; - unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */ + unsigned char interp_mode[65]; /* ELK_VARYING_SLOT_COUNT */ uint8_t point_sprite_coord_replace; - enum brw_sf_primitive primitive:2; + enum elk_sf_primitive primitive:2; bool do_twoside_color:1; bool frontface_ccw:1; bool do_point_sprite:1; @@ -433,44 +433,44 @@ struct brw_sf_prog_key { unsigned padding: 32; }; -enum brw_clip_mode { - BRW_CLIP_MODE_NORMAL = 0, - BRW_CLIP_MODE_CLIP_ALL = 1, - BRW_CLIP_MODE_CLIP_NON_REJECTED = 2, - BRW_CLIP_MODE_REJECT_ALL = 3, - BRW_CLIP_MODE_ACCEPT_ALL = 4, - BRW_CLIP_MODE_KERNEL_CLIP = 5, +enum elk_clip_mode { + ELK_CLIP_MODE_NORMAL = 0, + ELK_CLIP_MODE_CLIP_ALL = 1, + ELK_CLIP_MODE_CLIP_NON_REJECTED = 2, + ELK_CLIP_MODE_REJECT_ALL = 3, + ELK_CLIP_MODE_ACCEPT_ALL = 4, + ELK_CLIP_MODE_KERNEL_CLIP = 5, }; -enum brw_clip_fill_mode { - BRW_CLIP_FILL_MODE_LINE = 0, - BRW_CLIP_FILL_MODE_POINT = 1, - BRW_CLIP_FILL_MODE_FILL = 2, - BRW_CLIP_FILL_MODE_CULL = 3, +enum elk_clip_fill_mode { + ELK_CLIP_FILL_MODE_LINE = 0, + ELK_CLIP_FILL_MODE_POINT = 1, + ELK_CLIP_FILL_MODE_FILL = 2, + ELK_CLIP_FILL_MODE_CULL = 3, }; /* Note that if unfilled primitives are being emitted, we have to fix * up polygon offset and flatshading at this point: */ -struct brw_clip_prog_key { +struct elk_clip_prog_key { uint64_t attrs; float offset_factor; float offset_units; float offset_clamp; bool contains_flat_varying; bool contains_noperspective_varying; - unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */ + unsigned char interp_mode[65]; /* ELK_VARYING_SLOT_COUNT */ unsigned primitive:4; unsigned nr_userclip:4; bool pv_first:1; bool do_unfilled:1; - enum brw_clip_fill_mode fill_cw:2; /* includes cull information */ - enum brw_clip_fill_mode fill_ccw:2; /* includes cull information */ + enum elk_clip_fill_mode fill_cw:2; /* includes cull information */ + enum elk_clip_fill_mode fill_ccw:2; /* includes cull information */ bool offset_cw:1; bool offset_ccw:1; bool copy_bfc_cw:1; bool copy_bfc_ccw:1; - enum brw_clip_mode clip_mode:3; + enum elk_clip_mode clip_mode:3; uint64_t padding:51; }; @@ -479,37 +479,37 @@ struct brw_clip_prog_key { * program execution. These mainly relate to depth and stencil * processing and the early-depth-test optimization. */ -enum brw_wm_iz_bits { - BRW_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1, - BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2, - BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4, - BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8, - BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10, - BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20, - BRW_WM_IZ_BIT_MAX = 0x40 +enum elk_wm_iz_bits { + ELK_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1, + ELK_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2, + ELK_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4, + ELK_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8, + ELK_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10, + ELK_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20, + ELK_WM_IZ_BIT_MAX = 0x40 }; -enum brw_sometimes { - BRW_NEVER = 0, - BRW_SOMETIMES, - BRW_ALWAYS +enum elk_sometimes { + ELK_NEVER = 0, + ELK_SOMETIMES, + ELK_ALWAYS }; -static inline enum brw_sometimes -brw_sometimes_invert(enum brw_sometimes x) +static inline enum elk_sometimes +elk_sometimes_invert(enum elk_sometimes x) { - return (enum brw_sometimes)((int)BRW_ALWAYS - (int)x); + return (enum elk_sometimes)((int)ELK_ALWAYS - (int)x); } /** The program key for Fragment/Pixel Shaders. */ -struct brw_wm_prog_key { - struct brw_base_prog_key base; +struct elk_wm_prog_key { + struct elk_base_prog_key base; uint64_t input_slots_valid; float alpha_test_ref; uint8_t color_outputs_valid; - /* Some collection of BRW_WM_IZ_* */ + /* Some collection of ELK_WM_IZ_* */ uint8_t iz_lookup; bool stats_wm:1; bool flat_shade:1; @@ -517,7 +517,7 @@ struct brw_wm_prog_key { bool emit_alpha_test:1; enum compare_func alpha_test_func:3; /* < For Gfx4/5 MRT alpha test */ bool alpha_test_replicate_alpha:1; - enum brw_sometimes alpha_to_coverage:2; + enum elk_sometimes alpha_to_coverage:2; bool clamp_fragment_color:1; bool force_dual_color_blend:1; @@ -530,12 +530,12 @@ struct brw_wm_prog_key { * us to run per-sample. Even when running per-sample due to gl_SampleID, * we may still interpolate unqualified inputs at the pixel center. */ - enum brw_sometimes persample_interp:2; + enum elk_sometimes persample_interp:2; /* Whether or not we are running on a multisampled framebuffer */ - enum brw_sometimes multisample_fbo:2; + enum elk_sometimes multisample_fbo:2; - enum brw_sometimes line_aa:2; + enum elk_sometimes line_aa:2; bool coherent_fb_fetch:1; bool ignore_sample_mask_out:1; @@ -544,11 +544,11 @@ struct brw_wm_prog_key { uint64_t padding:55; }; -struct brw_cs_prog_key { - struct brw_base_prog_key base; +struct elk_cs_prog_key { + struct elk_base_prog_key base; }; -struct brw_ff_gs_prog_key { +struct elk_ff_gs_prog_key { uint64_t attrs; /** @@ -556,14 +556,14 @@ struct brw_ff_gs_prog_key { * gl_varying_slot that should be streamed out through that binding table * entry. */ - unsigned char transform_feedback_bindings[BRW_MAX_SOL_BINDINGS]; + unsigned char transform_feedback_bindings[ELK_MAX_SOL_BINDINGS]; /** * Map from the index of a transform feedback binding table entry to the * swizzles that should be used when streaming out data through that * binding table entry. */ - unsigned char transform_feedback_swizzles[BRW_MAX_SOL_BINDINGS]; + unsigned char transform_feedback_swizzles[ELK_MAX_SOL_BINDINGS]; /** * Hardware primitive type being drawn, e.g. _3DPRIM_TRILIST. @@ -576,32 +576,32 @@ struct brw_ff_gs_prog_key { /** * Number of varyings that are output to transform feedback. */ - unsigned num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */ + unsigned num_transform_feedback_bindings:7; /* 0-ELK_MAX_SOL_BINDINGS */ uint64_t padding:47; }; -/* brw_any_prog_key is any of the keys that map to an API stage */ -union brw_any_prog_key { - struct brw_base_prog_key base; - struct brw_vs_prog_key vs; - struct brw_tcs_prog_key tcs; - struct brw_tes_prog_key tes; - struct brw_gs_prog_key gs; - struct brw_wm_prog_key wm; - struct brw_cs_prog_key cs; +/* elk_any_prog_key is any of the keys that map to an API stage */ +union elk_any_prog_key { + struct elk_base_prog_key base; + struct elk_vs_prog_key vs; + struct elk_tcs_prog_key tcs; + struct elk_tes_prog_key tes; + struct elk_gs_prog_key gs; + struct elk_wm_prog_key wm; + struct elk_cs_prog_key cs; }; PRAGMA_DIAGNOSTIC_POP /** Max number of render targets in a shader */ -#define BRW_MAX_DRAW_BUFFERS 8 +#define ELK_MAX_DRAW_BUFFERS 8 /** * Binding table index for the first gfx6 SOL binding. */ -#define BRW_GFX6_SOL_BINDING_START 0 +#define ELK_GFX6_SOL_BINDING_START 0 -struct brw_ubo_range +struct elk_ubo_range { uint16_t block; @@ -611,88 +611,88 @@ struct brw_ubo_range }; /* We reserve the first 2^16 values for builtins */ -#define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0) +#define ELK_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0) -enum brw_param_builtin { - BRW_PARAM_BUILTIN_ZERO, +enum elk_param_builtin { + ELK_PARAM_BUILTIN_ZERO, - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X, - BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y, - BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z, - BRW_PARAM_BUILTIN_CLIP_PLANE_0_W, - BRW_PARAM_BUILTIN_CLIP_PLANE_1_X, - BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y, - BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z, - BRW_PARAM_BUILTIN_CLIP_PLANE_1_W, - BRW_PARAM_BUILTIN_CLIP_PLANE_2_X, - BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y, - BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z, - BRW_PARAM_BUILTIN_CLIP_PLANE_2_W, - BRW_PARAM_BUILTIN_CLIP_PLANE_3_X, - BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y, - BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z, - BRW_PARAM_BUILTIN_CLIP_PLANE_3_W, - BRW_PARAM_BUILTIN_CLIP_PLANE_4_X, - BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y, - BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z, - BRW_PARAM_BUILTIN_CLIP_PLANE_4_W, - BRW_PARAM_BUILTIN_CLIP_PLANE_5_X, - BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y, - BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z, - BRW_PARAM_BUILTIN_CLIP_PLANE_5_W, - BRW_PARAM_BUILTIN_CLIP_PLANE_6_X, - BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y, - BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z, - BRW_PARAM_BUILTIN_CLIP_PLANE_6_W, - BRW_PARAM_BUILTIN_CLIP_PLANE_7_X, - BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y, - BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z, - BRW_PARAM_BUILTIN_CLIP_PLANE_7_W, + ELK_PARAM_BUILTIN_CLIP_PLANE_0_X, + ELK_PARAM_BUILTIN_CLIP_PLANE_0_Y, + ELK_PARAM_BUILTIN_CLIP_PLANE_0_Z, + ELK_PARAM_BUILTIN_CLIP_PLANE_0_W, + ELK_PARAM_BUILTIN_CLIP_PLANE_1_X, + ELK_PARAM_BUILTIN_CLIP_PLANE_1_Y, + ELK_PARAM_BUILTIN_CLIP_PLANE_1_Z, + ELK_PARAM_BUILTIN_CLIP_PLANE_1_W, + ELK_PARAM_BUILTIN_CLIP_PLANE_2_X, + ELK_PARAM_BUILTIN_CLIP_PLANE_2_Y, + ELK_PARAM_BUILTIN_CLIP_PLANE_2_Z, + ELK_PARAM_BUILTIN_CLIP_PLANE_2_W, + ELK_PARAM_BUILTIN_CLIP_PLANE_3_X, + ELK_PARAM_BUILTIN_CLIP_PLANE_3_Y, + ELK_PARAM_BUILTIN_CLIP_PLANE_3_Z, + ELK_PARAM_BUILTIN_CLIP_PLANE_3_W, + ELK_PARAM_BUILTIN_CLIP_PLANE_4_X, + ELK_PARAM_BUILTIN_CLIP_PLANE_4_Y, + ELK_PARAM_BUILTIN_CLIP_PLANE_4_Z, + ELK_PARAM_BUILTIN_CLIP_PLANE_4_W, + ELK_PARAM_BUILTIN_CLIP_PLANE_5_X, + ELK_PARAM_BUILTIN_CLIP_PLANE_5_Y, + ELK_PARAM_BUILTIN_CLIP_PLANE_5_Z, + ELK_PARAM_BUILTIN_CLIP_PLANE_5_W, + ELK_PARAM_BUILTIN_CLIP_PLANE_6_X, + ELK_PARAM_BUILTIN_CLIP_PLANE_6_Y, + ELK_PARAM_BUILTIN_CLIP_PLANE_6_Z, + ELK_PARAM_BUILTIN_CLIP_PLANE_6_W, + ELK_PARAM_BUILTIN_CLIP_PLANE_7_X, + ELK_PARAM_BUILTIN_CLIP_PLANE_7_Y, + ELK_PARAM_BUILTIN_CLIP_PLANE_7_Z, + ELK_PARAM_BUILTIN_CLIP_PLANE_7_W, - BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X, - BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y, - BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z, - BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W, - BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X, - BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y, + ELK_PARAM_BUILTIN_TESS_LEVEL_OUTER_X, + ELK_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y, + ELK_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z, + ELK_PARAM_BUILTIN_TESS_LEVEL_OUTER_W, + ELK_PARAM_BUILTIN_TESS_LEVEL_INNER_X, + ELK_PARAM_BUILTIN_TESS_LEVEL_INNER_Y, - BRW_PARAM_BUILTIN_PATCH_VERTICES_IN, + ELK_PARAM_BUILTIN_PATCH_VERTICES_IN, - BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X, - BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y, - BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z, - BRW_PARAM_BUILTIN_SUBGROUP_ID, - BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X, - BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Y, - BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z, - BRW_PARAM_BUILTIN_WORK_DIM, + ELK_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X, + ELK_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y, + ELK_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z, + ELK_PARAM_BUILTIN_SUBGROUP_ID, + ELK_PARAM_BUILTIN_WORK_GROUP_SIZE_X, + ELK_PARAM_BUILTIN_WORK_GROUP_SIZE_Y, + ELK_PARAM_BUILTIN_WORK_GROUP_SIZE_Z, + ELK_PARAM_BUILTIN_WORK_DIM, }; -#define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \ - (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp)) +#define ELK_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \ + (ELK_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp)) -#define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \ - ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \ - (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W) +#define ELK_PARAM_BUILTIN_IS_CLIP_PLANE(param) \ + ((param) >= ELK_PARAM_BUILTIN_CLIP_PLANE_0_X && \ + (param) <= ELK_PARAM_BUILTIN_CLIP_PLANE_7_W) -#define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \ - (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2) +#define ELK_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \ + (((param) - ELK_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2) -#define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \ - (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3) +#define ELK_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \ + (((param) - ELK_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3) -enum brw_shader_reloc_id { - BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW, - BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH, - BRW_SHADER_RELOC_SHADER_START_OFFSET, - BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH, +enum elk_shader_reloc_id { + ELK_SHADER_RELOC_CONST_DATA_ADDR_LOW, + ELK_SHADER_RELOC_CONST_DATA_ADDR_HIGH, + ELK_SHADER_RELOC_SHADER_START_OFFSET, + ELK_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH, }; -enum brw_shader_reloc_type { +enum elk_shader_reloc_type { /** An arbitrary 32-bit value */ - BRW_SHADER_RELOC_TYPE_U32, + ELK_SHADER_RELOC_TYPE_U32, /** A MOV instruction with an immediate source */ - BRW_SHADER_RELOC_TYPE_MOV_IMM, + ELK_SHADER_RELOC_TYPE_MOV_IMM, }; /** Represents a code relocation @@ -700,12 +700,12 @@ enum brw_shader_reloc_type { * Relocatable constants are immediates in the code which we want to be able * to replace post-compile with the actual value. */ -struct brw_shader_reloc { +struct elk_shader_reloc { /** The 32-bit ID of the relocatable constant */ uint32_t id; /** Type of this relocation */ - enum brw_shader_reloc_type type; + enum elk_shader_reloc_type type; /** The offset in the shader to the relocated value * @@ -719,7 +719,7 @@ struct brw_shader_reloc { }; /** A value to write to a relocation */ -struct brw_shader_reloc_value { +struct elk_shader_reloc_value { /** The 32-bit ID of the relocatable constant */ uint32_t id; @@ -727,8 +727,8 @@ struct brw_shader_reloc_value { uint32_t value; }; -struct brw_stage_prog_data { - struct brw_ubo_range ubo_ranges[4]; +struct elk_stage_prog_data { + struct elk_ubo_range ubo_ranges[4]; unsigned nr_params; /**< number of float params/constants */ @@ -742,7 +742,7 @@ struct brw_stage_prog_data { * * reg_used & zero_push_reg & ~*push_reg_mask_param & (1ull << i) * - * If this field is set, brw_compiler::compact_params must be false. + * If this field is set, elk_compiler::compact_params must be false. */ uint64_t zero_push_reg; unsigned push_reg_mask_param; @@ -757,7 +757,7 @@ struct brw_stage_prog_data { unsigned const_data_offset; unsigned num_relocs; - const struct brw_shader_reloc *relocs; + const struct elk_shader_reloc *relocs; /** Does this program pull from any UBO or other constant buffers? */ bool has_ubo_pull; @@ -776,7 +776,7 @@ struct brw_stage_prog_data { /* 32-bit identifiers for all push/pull parameters. These can be anything * the driver wishes them to be; the core of the back-end compiler simply * re-arranges them. The one restriction is that the bottom 2^16 values - * are reserved for builtins defined in the brw_param_builtin enum defined + * are reserved for builtins defined in the elk_param_builtin enum defined * above. */ uint32_t *param; @@ -786,7 +786,7 @@ struct brw_stage_prog_data { }; static inline uint32_t * -brw_stage_prog_data_add_params(struct brw_stage_prog_data *prog_data, +elk_stage_prog_data_add_params(struct elk_stage_prog_data *prog_data, unsigned nr_new_params) { unsigned old_nr_params = prog_data->nr_params; @@ -797,38 +797,38 @@ brw_stage_prog_data_add_params(struct brw_stage_prog_data *prog_data, return prog_data->param + old_nr_params; } -enum brw_barycentric_mode { - BRW_BARYCENTRIC_PERSPECTIVE_PIXEL = 0, - BRW_BARYCENTRIC_PERSPECTIVE_CENTROID = 1, - BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE = 2, - BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL = 3, - BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4, - BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE = 5, - BRW_BARYCENTRIC_MODE_COUNT = 6 +enum elk_barycentric_mode { + ELK_BARYCENTRIC_PERSPECTIVE_PIXEL = 0, + ELK_BARYCENTRIC_PERSPECTIVE_CENTROID = 1, + ELK_BARYCENTRIC_PERSPECTIVE_SAMPLE = 2, + ELK_BARYCENTRIC_NONPERSPECTIVE_PIXEL = 3, + ELK_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4, + ELK_BARYCENTRIC_NONPERSPECTIVE_SAMPLE = 5, + ELK_BARYCENTRIC_MODE_COUNT = 6 }; -#define BRW_BARYCENTRIC_PERSPECTIVE_BITS \ - ((1 << BRW_BARYCENTRIC_PERSPECTIVE_PIXEL) | \ - (1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID) | \ - (1 << BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE)) -#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \ - ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \ - (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \ - (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE)) +#define ELK_BARYCENTRIC_PERSPECTIVE_BITS \ + ((1 << ELK_BARYCENTRIC_PERSPECTIVE_PIXEL) | \ + (1 << ELK_BARYCENTRIC_PERSPECTIVE_CENTROID) | \ + (1 << ELK_BARYCENTRIC_PERSPECTIVE_SAMPLE)) +#define ELK_BARYCENTRIC_NONPERSPECTIVE_BITS \ + ((1 << ELK_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \ + (1 << ELK_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \ + (1 << ELK_BARYCENTRIC_NONPERSPECTIVE_SAMPLE)) -enum brw_pixel_shader_computed_depth_mode { - BRW_PSCDEPTH_OFF = 0, /* PS does not compute depth */ - BRW_PSCDEPTH_ON = 1, /* PS computes depth; no guarantee about value */ - BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */ - BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */ +enum elk_pixel_shader_computed_depth_mode { + ELK_PSCDEPTH_OFF = 0, /* PS does not compute depth */ + ELK_PSCDEPTH_ON = 1, /* PS computes depth; no guarantee about value */ + ELK_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */ + ELK_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */ }; /* Data about a particular attempt to compile a program. Note that * there can be many of these, each in a different GL state - * corresponding to a different brw_wm_prog_key struct, with different + * corresponding to a different elk_wm_prog_key struct, with different * compiled programs. */ -struct brw_wm_prog_data { - struct brw_stage_prog_data base; +struct elk_wm_prog_data { + struct elk_stage_prog_data base; unsigned num_per_primitive_inputs; unsigned num_varying_inputs; @@ -897,18 +897,18 @@ struct brw_wm_prog_data { bool sample_shading; /** Should this shader be dispatched per-sample */ - enum brw_sometimes persample_dispatch; + enum elk_sometimes persample_dispatch; /** * Shader is ran at the coarse pixel shading dispatch rate (3DSTATE_CPS). */ - enum brw_sometimes coarse_pixel_dispatch; + enum elk_sometimes coarse_pixel_dispatch; /** * Shader writes the SampleMask and this is AND-ed with the API's * SampleMask to generate a new coverage mask. */ - enum brw_sometimes alpha_to_coverage; + enum elk_sometimes alpha_to_coverage; unsigned msaa_flags_param; @@ -939,7 +939,7 @@ struct brw_wm_prog_data { /* Mapping of VUE slots to interpolation modes. * Used by the Gfx4-5 clip/sf/wm stages. */ - unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */ + unsigned char interp_mode[65]; /* ELK_VARYING_SLOT_COUNT */ /** * Map from gl_varying_slot to the position within the FS setup data @@ -972,11 +972,11 @@ struct brw_wm_prog_data { * If the given KSP is enabled, a SIMD width of 8, 16, or 32 is * returned. Note that for a multipolygon dispatch kernel 8 is always * returned, since multipolygon kernels use the "_8" fields from - * brw_wm_prog_data regardless of their SIMD width. If the KSP is + * elk_wm_prog_data regardless of their SIMD width. If the KSP is * invalid, 0 is returned. */ static inline unsigned -brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool enabled, unsigned width_sel) +elk_fs_simd_width_for_ksp(unsigned ksp_idx, bool enabled, unsigned width_sel) { assert(ksp_idx < 2); return !enabled ? 0 : @@ -984,11 +984,11 @@ brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool enabled, unsigned width_sel) 16; } -#define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \ +#define elk_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \ (ksp_idx == 0 && (wm_state).Kernel0MaximumPolysperThread ? 8 : \ - ksp_idx == 0 ? brw_fs_simd_width_for_ksp(ksp_idx, (wm_state).Kernel0Enable, \ + ksp_idx == 0 ? elk_fs_simd_width_for_ksp(ksp_idx, (wm_state).Kernel0Enable, \ (wm_state).Kernel0SIMDWidth): \ - brw_fs_simd_width_for_ksp(ksp_idx, (wm_state).Kernel1Enable, \ + elk_fs_simd_width_for_ksp(ksp_idx, (wm_state).Kernel1Enable, \ (wm_state).Kernel1SIMDWidth)) #else @@ -1004,7 +1004,7 @@ brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool enabled, unsigned width_sel) * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned. */ static inline unsigned -brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled, +elk_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled, bool simd16_enabled, bool simd32_enabled) { /* This function strictly ignores contiguous dispatch */ @@ -1022,8 +1022,8 @@ brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled, } } -#define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \ - brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \ +#define elk_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \ + elk_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \ (wm_state)._16PixelDispatchEnable, \ (wm_state)._32PixelDispatchEnable) @@ -1031,11 +1031,11 @@ brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled, #endif -#define brw_wm_state_has_ksp(wm_state, ksp_idx) \ - (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0) +#define elk_wm_state_has_ksp(wm_state, ksp_idx) \ + (elk_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0) static inline uint32_t -_brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data, +_elk_wm_prog_data_prog_offset(const struct elk_wm_prog_data *prog_data, unsigned simd_width) { switch (simd_width) { @@ -1046,12 +1046,12 @@ _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data, } } -#define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \ - _brw_wm_prog_data_prog_offset(prog_data, \ - brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) +#define elk_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \ + _elk_wm_prog_data_prog_offset(prog_data, \ + elk_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) static inline uint8_t -_brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_data, +_elk_wm_prog_data_dispatch_grf_start_reg(const struct elk_wm_prog_data *prog_data, unsigned simd_width) { switch (simd_width) { @@ -1062,12 +1062,12 @@ _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_dat } } -#define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \ - _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \ - brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) +#define elk_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \ + _elk_wm_prog_data_dispatch_grf_start_reg(prog_data, \ + elk_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) static inline uint8_t -_brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data, +_elk_wm_prog_data_reg_blocks(const struct elk_wm_prog_data *prog_data, unsigned simd_width) { switch (simd_width) { @@ -1078,12 +1078,12 @@ _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data, } } -#define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \ - _brw_wm_prog_data_reg_blocks(prog_data, \ - brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) +#define elk_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \ + _elk_wm_prog_data_reg_blocks(prog_data, \ + elk_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) static inline bool -brw_wm_prog_data_is_persample(const struct brw_wm_prog_data *prog_data, +elk_wm_prog_data_is_persample(const struct elk_wm_prog_data *prog_data, enum intel_msaa_flags pushed_msaa_flags) { if (pushed_msaa_flags & INTEL_MSAA_FLAG_ENABLE_DYNAMIC) { @@ -1094,21 +1094,21 @@ brw_wm_prog_data_is_persample(const struct brw_wm_prog_data *prog_data, assert(pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH); if (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH) - assert(prog_data->persample_dispatch != BRW_NEVER); + assert(prog_data->persample_dispatch != ELK_NEVER); else - assert(prog_data->persample_dispatch != BRW_ALWAYS); + assert(prog_data->persample_dispatch != ELK_ALWAYS); return (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH) != 0; } - assert(prog_data->persample_dispatch == BRW_ALWAYS || - prog_data->persample_dispatch == BRW_NEVER); + assert(prog_data->persample_dispatch == ELK_ALWAYS || + prog_data->persample_dispatch == ELK_NEVER); return prog_data->persample_dispatch; } static inline uint32_t -wm_prog_data_barycentric_modes(const struct brw_wm_prog_data *prog_data, +elk_wm_prog_data_barycentric_modes(const struct elk_wm_prog_data *prog_data, enum intel_msaa_flags pushed_msaa_flags) { uint32_t modes = prog_data->barycentric_interp_modes; @@ -1120,7 +1120,7 @@ wm_prog_data_barycentric_modes(const struct brw_wm_prog_data *prog_data, return modes; if (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_INTERP) { - assert(prog_data->persample_dispatch == BRW_ALWAYS || + assert(prog_data->persample_dispatch == ELK_ALWAYS || (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH)); /* Making dynamic per-sample interpolation work is a bit tricky. The @@ -1137,24 +1137,24 @@ wm_prog_data_barycentric_modes(const struct brw_wm_prog_data *prog_data, * which one we replace. The important thing is that we keep the number * of barycentrics in each [non]perspective grouping the same. */ - if ((modes & BRW_BARYCENTRIC_PERSPECTIVE_BITS) && - !(modes & BITFIELD_BIT(BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE))) { + if ((modes & ELK_BARYCENTRIC_PERSPECTIVE_BITS) && + !(modes & BITFIELD_BIT(ELK_BARYCENTRIC_PERSPECTIVE_SAMPLE))) { int sample_mode = - util_last_bit(modes & BRW_BARYCENTRIC_PERSPECTIVE_BITS) - 1; + util_last_bit(modes & ELK_BARYCENTRIC_PERSPECTIVE_BITS) - 1; assert(modes & BITFIELD_BIT(sample_mode)); modes &= ~BITFIELD_BIT(sample_mode); - modes |= BITFIELD_BIT(BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE); + modes |= BITFIELD_BIT(ELK_BARYCENTRIC_PERSPECTIVE_SAMPLE); } - if ((modes & BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) && - !(modes & BITFIELD_BIT(BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))) { + if ((modes & ELK_BARYCENTRIC_NONPERSPECTIVE_BITS) && + !(modes & BITFIELD_BIT(ELK_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))) { int sample_mode = - util_last_bit(modes & BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) - 1; + util_last_bit(modes & ELK_BARYCENTRIC_NONPERSPECTIVE_BITS) - 1; assert(modes & BITFIELD_BIT(sample_mode)); modes &= ~BITFIELD_BIT(sample_mode); - modes |= BITFIELD_BIT(BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE); + modes |= BITFIELD_BIT(ELK_BARYCENTRIC_NONPERSPECTIVE_SAMPLE); } } else { /* If we're not using per-sample interpolation, we need to disable the @@ -1166,40 +1166,40 @@ wm_prog_data_barycentric_modes(const struct brw_wm_prog_data *prog_data, * "MSDISPMODE_PERSAMPLE is required in order to select Perspective * Sample or Non-perspective Sample barycentric coordinates." */ - modes &= ~(BITFIELD_BIT(BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE) | - BITFIELD_BIT(BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE)); + modes &= ~(BITFIELD_BIT(ELK_BARYCENTRIC_PERSPECTIVE_SAMPLE) | + BITFIELD_BIT(ELK_BARYCENTRIC_NONPERSPECTIVE_SAMPLE)); } return modes; } static inline bool -brw_wm_prog_data_is_coarse(const struct brw_wm_prog_data *prog_data, +elk_wm_prog_data_is_coarse(const struct elk_wm_prog_data *prog_data, enum intel_msaa_flags pushed_msaa_flags) { if (pushed_msaa_flags & INTEL_MSAA_FLAG_ENABLE_DYNAMIC) { if (pushed_msaa_flags & INTEL_MSAA_FLAG_COARSE_RT_WRITES) - assert(prog_data->coarse_pixel_dispatch != BRW_NEVER); + assert(prog_data->coarse_pixel_dispatch != ELK_NEVER); else - assert(prog_data->coarse_pixel_dispatch != BRW_ALWAYS); + assert(prog_data->coarse_pixel_dispatch != ELK_ALWAYS); return pushed_msaa_flags & INTEL_MSAA_FLAG_COARSE_RT_WRITES; } - assert(prog_data->coarse_pixel_dispatch == BRW_ALWAYS || - prog_data->coarse_pixel_dispatch == BRW_NEVER); + assert(prog_data->coarse_pixel_dispatch == ELK_ALWAYS || + prog_data->coarse_pixel_dispatch == ELK_NEVER); return prog_data->coarse_pixel_dispatch; } -struct brw_push_const_block { +struct elk_push_const_block { unsigned dwords; /* Dword count, not reg aligned */ unsigned regs; unsigned size; /* Bytes, register aligned */ }; -struct brw_cs_prog_data { - struct brw_stage_prog_data base; +struct elk_cs_prog_data { + struct elk_stage_prog_data base; unsigned local_size[3]; @@ -1224,8 +1224,8 @@ struct brw_cs_prog_data { enum intel_compute_walk_order walk_order; struct { - struct brw_push_const_block cross_thread; - struct brw_push_const_block per_thread; + struct elk_push_const_block cross_thread; + struct elk_push_const_block per_thread; } push; struct { @@ -1238,7 +1238,7 @@ struct brw_cs_prog_data { }; static inline uint32_t -brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data *prog_data, +elk_cs_prog_data_prog_offset(const struct elk_cs_prog_data *prog_data, unsigned dispatch_width) { assert(dispatch_width == 8 || @@ -1249,7 +1249,7 @@ brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data *prog_data, return prog_data->prog_offset[index]; } -struct brw_ff_gs_prog_data { +struct elk_ff_gs_prog_data { unsigned urb_read_length; unsigned total_grf; @@ -1267,72 +1267,72 @@ struct brw_ff_gs_prog_data { */ typedef enum { - BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX, - BRW_VARYING_SLOT_PAD, + ELK_VARYING_SLOT_NDC = VARYING_SLOT_MAX, + ELK_VARYING_SLOT_PAD, /** * Technically this is not a varying but just a placeholder that * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord * builtin variable to be compiled correctly. see compile_sf_prog() for * more info. */ - BRW_VARYING_SLOT_PNTC, - BRW_VARYING_SLOT_COUNT -} brw_varying_slot; + ELK_VARYING_SLOT_PNTC, + ELK_VARYING_SLOT_COUNT +} elk_varying_slot; /** * We always program SF to start reading at an offset of 1 (2 varying slots) * from the start of the vertex URB entry. This causes it to skip: - * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gfx4-5 + * - VARYING_SLOT_PSIZ and ELK_VARYING_SLOT_NDC on gfx4-5 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gfx6+ */ -#define BRW_SF_URB_ENTRY_READ_OFFSET 1 +#define ELK_SF_URB_ENTRY_READ_OFFSET 1 /** * Bitmask indicating which fragment shader inputs represent varyings (and * hence have to be delivered to the fragment shader by the SF/SBE stage). */ -#define BRW_FS_VARYING_INPUT_MASK \ +#define ELK_FS_VARYING_INPUT_MASK \ (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \ ~VARYING_BIT_POS & ~VARYING_BIT_FACE) -void brw_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, +void elk_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, gl_shader_stage stage); /** * Convert a VUE slot number into a byte offset within the VUE. */ -static inline unsigned brw_vue_slot_to_offset(unsigned slot) +static inline unsigned elk_vue_slot_to_offset(unsigned slot) { return 16*slot; } /** - * Convert a vertex output (brw_varying_slot) into a byte offset within the + * Convert a vertex output (elk_varying_slot) into a byte offset within the * VUE. */ static inline unsigned -brw_varying_to_offset(const struct intel_vue_map *vue_map, unsigned varying) +elk_varying_to_offset(const struct intel_vue_map *vue_map, unsigned varying) { - return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]); + return elk_vue_slot_to_offset(vue_map->varying_to_slot[varying]); } -void brw_compute_vue_map(const struct intel_device_info *devinfo, +void elk_compute_vue_map(const struct intel_device_info *devinfo, struct intel_vue_map *vue_map, uint64_t slots_valid, bool separate_shader, uint32_t pos_slots); -void brw_compute_tess_vue_map(struct intel_vue_map *const vue_map, +void elk_compute_tess_vue_map(struct intel_vue_map *const vue_map, uint64_t slots_valid, uint32_t is_patch); -/* brw_interpolation_map.c */ -void brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, +/* elk_interpolation_map.c */ +void elk_setup_vue_interpolation(const struct intel_vue_map *vue_map, struct nir_shader *nir, - struct brw_wm_prog_data *prog_data); + struct elk_wm_prog_data *prog_data); -struct brw_vue_prog_data { - struct brw_stage_prog_data base; +struct elk_vue_prog_data { + struct elk_stage_prog_data base; struct intel_vue_map vue_map; /** Should the hardware deliver input VUE handles for URB pull loads? */ @@ -1353,8 +1353,8 @@ struct brw_vue_prog_data { enum intel_shader_dispatch_mode dispatch_mode; }; -struct brw_vs_prog_data { - struct brw_vue_prog_data base; +struct elk_vs_prog_data { + struct elk_vue_prog_data base; uint64_t inputs_read; uint64_t double_inputs_read; @@ -1369,9 +1369,9 @@ struct brw_vs_prog_data { bool uses_drawid; }; -struct brw_tcs_prog_data +struct elk_tcs_prog_data { - struct brw_vue_prog_data base; + struct elk_vue_prog_data base; /** Should the non-SINGLE_PATCH payload provide primitive ID? */ bool include_primitive_id; @@ -1384,9 +1384,9 @@ struct brw_tcs_prog_data }; -struct brw_tes_prog_data +struct elk_tes_prog_data { - struct brw_vue_prog_data base; + struct elk_vue_prog_data base; enum intel_tess_partitioning partitioning; enum intel_tess_output_topology output_topology; @@ -1394,9 +1394,9 @@ struct brw_tes_prog_data bool include_primitive_id; }; -struct brw_gs_prog_data +struct elk_gs_prog_data { - struct brw_vue_prog_data base; + struct elk_vue_prog_data base; unsigned vertices_in; @@ -1439,24 +1439,24 @@ struct brw_gs_prog_data /** * Gfx6: Number of varyings that are output to transform feedback. */ - unsigned num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */ + unsigned num_transform_feedback_bindings:7; /* 0-ELK_MAX_SOL_BINDINGS */ /** * Gfx6: Map from the index of a transform feedback binding table entry to the * gl_varying_slot that should be streamed out through that binding table * entry. */ - unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */]; + unsigned char transform_feedback_bindings[64 /* ELK_MAX_SOL_BINDINGS */]; /** * Gfx6: Map from the index of a transform feedback binding table entry to the * swizzles that should be used when streaming out data through that * binding table entry. */ - unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */]; + unsigned char transform_feedback_swizzles[64 /* ELK_MAX_SOL_BINDINGS */]; }; -struct brw_sf_prog_data { +struct elk_sf_prog_data { uint32_t urb_read_length; uint32_t total_grf; @@ -1469,39 +1469,39 @@ struct brw_sf_prog_data { unsigned urb_entry_size; }; -struct brw_clip_prog_data { +struct elk_clip_prog_data { uint32_t curb_read_length; /* user planes? */ uint32_t clip_mode; uint32_t urb_read_length; uint32_t total_grf; }; -/* brw_any_prog_data is prog_data for any stage that maps to an API stage */ -union brw_any_prog_data { - struct brw_stage_prog_data base; - struct brw_vue_prog_data vue; - struct brw_vs_prog_data vs; - struct brw_tcs_prog_data tcs; - struct brw_tes_prog_data tes; - struct brw_gs_prog_data gs; - struct brw_wm_prog_data wm; - struct brw_cs_prog_data cs; +/* elk_any_prog_data is prog_data for any stage that maps to an API stage */ +union elk_any_prog_data { + struct elk_stage_prog_data base; + struct elk_vue_prog_data vue; + struct elk_vs_prog_data vs; + struct elk_tcs_prog_data tcs; + struct elk_tes_prog_data tes; + struct elk_gs_prog_data gs; + struct elk_wm_prog_data wm; + struct elk_cs_prog_data cs; }; #define DEFINE_PROG_DATA_DOWNCAST(STAGE, CHECK) \ -static inline struct brw_##STAGE##_prog_data * \ -brw_##STAGE##_prog_data(struct brw_stage_prog_data *prog_data) \ +static inline struct elk_##STAGE##_prog_data * \ +elk_##STAGE##_prog_data(struct elk_stage_prog_data *prog_data) \ { \ if (prog_data) \ assert(CHECK); \ - return (struct brw_##STAGE##_prog_data *) prog_data; \ + return (struct elk_##STAGE##_prog_data *) prog_data; \ } \ -static inline const struct brw_##STAGE##_prog_data * \ -brw_##STAGE##_prog_data_const(const struct brw_stage_prog_data *prog_data) \ +static inline const struct elk_##STAGE##_prog_data * \ +elk_##STAGE##_prog_data_const(const struct elk_stage_prog_data *prog_data) \ { \ if (prog_data) \ assert(CHECK); \ - return (const struct brw_##STAGE##_prog_data *) prog_data; \ + return (const struct elk_##STAGE##_prog_data *) prog_data; \ } DEFINE_PROG_DATA_DOWNCAST(vs, prog_data->stage == MESA_SHADER_VERTEX) @@ -1516,13 +1516,13 @@ DEFINE_PROG_DATA_DOWNCAST(vue, prog_data->stage == MESA_SHADER_VERTEX || prog_data->stage == MESA_SHADER_TESS_EVAL || prog_data->stage == MESA_SHADER_GEOMETRY) -/* These are not really brw_stage_prog_data. */ +/* These are not really elk_stage_prog_data. */ DEFINE_PROG_DATA_DOWNCAST(ff_gs, true) DEFINE_PROG_DATA_DOWNCAST(clip, true) DEFINE_PROG_DATA_DOWNCAST(sf, true) #undef DEFINE_PROG_DATA_DOWNCAST -struct brw_compile_stats { +struct elk_compile_stats { uint32_t dispatch_width; /**< 0 for vec4 */ uint32_t max_polygons; uint32_t max_dispatch_width; @@ -1537,8 +1537,8 @@ struct brw_compile_stats { /** @} */ -struct brw_compiler * -brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo); +struct elk_compiler * +elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo); /** * Returns a compiler configuration for use with disk shader cache @@ -1550,20 +1550,20 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo); * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used. */ uint64_t -brw_get_compiler_config_value(const struct brw_compiler *compiler); +elk_get_compiler_config_value(const struct elk_compiler *compiler); unsigned -brw_prog_data_size(gl_shader_stage stage); +elk_prog_data_size(gl_shader_stage stage); unsigned -brw_prog_key_size(gl_shader_stage stage); +elk_prog_key_size(gl_shader_stage stage); -struct brw_compile_params { +struct elk_compile_params { void *mem_ctx; nir_shader *nir; - struct brw_compile_stats *stats; + struct elk_compile_stats *stats; void *log_data; @@ -1579,11 +1579,11 @@ struct brw_compile_params { * * Some of these will be modified during the shader compilation. */ -struct brw_compile_vs_params { - struct brw_compile_params base; +struct elk_compile_vs_params { + struct elk_compile_params base; - const struct brw_vs_prog_key *key; - struct brw_vs_prog_data *prog_data; + const struct elk_vs_prog_key *key; + struct elk_vs_prog_data *prog_data; bool edgeflag_is_last; /* true for gallium */ }; @@ -1594,19 +1594,19 @@ struct brw_compile_vs_params { * Returns the final assembly and updates the parameters structure. */ const unsigned * -brw_compile_vs(const struct brw_compiler *compiler, - struct brw_compile_vs_params *params); +elk_compile_vs(const struct elk_compiler *compiler, + struct elk_compile_vs_params *params); /** * Parameters for compiling a tessellation control shader. * * Some of these will be modified during the shader compilation. */ -struct brw_compile_tcs_params { - struct brw_compile_params base; +struct elk_compile_tcs_params { + struct elk_compile_params base; - const struct brw_tcs_prog_key *key; - struct brw_tcs_prog_data *prog_data; + const struct elk_tcs_prog_key *key; + struct elk_tcs_prog_data *prog_data; }; /** @@ -1615,19 +1615,19 @@ struct brw_compile_tcs_params { * Returns the final assembly and updates the parameters structure. */ const unsigned * -brw_compile_tcs(const struct brw_compiler *compiler, - struct brw_compile_tcs_params *params); +elk_compile_tcs(const struct elk_compiler *compiler, + struct elk_compile_tcs_params *params); /** * Parameters for compiling a tessellation evaluation shader. * * Some of these will be modified during the shader compilation. */ -struct brw_compile_tes_params { - struct brw_compile_params base; +struct elk_compile_tes_params { + struct elk_compile_params base; - const struct brw_tes_prog_key *key; - struct brw_tes_prog_data *prog_data; + const struct elk_tes_prog_key *key; + struct elk_tes_prog_data *prog_data; const struct intel_vue_map *input_vue_map; }; @@ -1637,19 +1637,19 @@ struct brw_compile_tes_params { * Returns the final assembly and updates the parameters structure. */ const unsigned * -brw_compile_tes(const struct brw_compiler *compiler, - struct brw_compile_tes_params *params); +elk_compile_tes(const struct elk_compiler *compiler, + struct elk_compile_tes_params *params); /** * Parameters for compiling a geometry shader. * * Some of these will be modified during the shader compilation. */ -struct brw_compile_gs_params { - struct brw_compile_params base; +struct elk_compile_gs_params { + struct elk_compile_params base; - const struct brw_gs_prog_key *key; - struct brw_gs_prog_data *prog_data; + const struct elk_gs_prog_key *key; + struct elk_gs_prog_data *prog_data; }; /** @@ -1658,8 +1658,8 @@ struct brw_compile_gs_params { * Returns the final assembly and updates the parameters structure. */ const unsigned * -brw_compile_gs(const struct brw_compiler *compiler, - struct brw_compile_gs_params *params); +elk_compile_gs(const struct elk_compiler *compiler, + struct elk_compile_gs_params *params); /** * Compile a strips and fans shader. @@ -1670,10 +1670,10 @@ brw_compile_gs(const struct brw_compiler *compiler, * Returns the final assembly and the program's size. */ const unsigned * -brw_compile_sf(const struct brw_compiler *compiler, +elk_compile_sf(const struct elk_compiler *compiler, void *mem_ctx, - const struct brw_sf_prog_key *key, - struct brw_sf_prog_data *prog_data, + const struct elk_sf_prog_key *key, + struct elk_sf_prog_data *prog_data, struct intel_vue_map *vue_map, unsigned *final_assembly_size); @@ -1686,10 +1686,10 @@ brw_compile_sf(const struct brw_compiler *compiler, * Returns the final assembly and the program's size. */ const unsigned * -brw_compile_clip(const struct brw_compiler *compiler, +elk_compile_clip(const struct elk_compiler *compiler, void *mem_ctx, - const struct brw_clip_prog_key *key, - struct brw_clip_prog_data *prog_data, + const struct elk_clip_prog_key *key, + struct elk_clip_prog_data *prog_data, struct intel_vue_map *vue_map, unsigned *final_assembly_size); @@ -1698,14 +1698,14 @@ brw_compile_clip(const struct brw_compiler *compiler, * * Some of these will be modified during the shader compilation. */ -struct brw_compile_fs_params { - struct brw_compile_params base; +struct elk_compile_fs_params { + struct elk_compile_params base; - const struct brw_wm_prog_key *key; - struct brw_wm_prog_data *prog_data; + const struct elk_wm_prog_key *key; + struct elk_wm_prog_data *prog_data; const struct intel_vue_map *vue_map; - const struct brw_mue_map *mue_map; + const struct elk_mue_map *mue_map; bool allow_spilling; bool use_rep_send; @@ -1718,19 +1718,19 @@ struct brw_compile_fs_params { * Returns the final assembly and updates the parameters structure. */ const unsigned * -brw_compile_fs(const struct brw_compiler *compiler, - struct brw_compile_fs_params *params); +elk_compile_fs(const struct elk_compiler *compiler, + struct elk_compile_fs_params *params); /** * Parameters for compiling a compute shader. * * Some of these will be modified during the shader compilation. */ -struct brw_compile_cs_params { - struct brw_compile_params base; +struct elk_compile_cs_params { + struct elk_compile_params base; - const struct brw_cs_prog_key *key; - struct brw_cs_prog_data *prog_data; + const struct elk_cs_prog_key *key; + struct elk_cs_prog_data *prog_data; }; /** @@ -1739,8 +1739,8 @@ struct brw_compile_cs_params { * Returns the final assembly and updates the parameters structure. */ const unsigned * -brw_compile_cs(const struct brw_compiler *compiler, - struct brw_compile_cs_params *params); +elk_compile_cs(const struct elk_compiler *compiler, + struct elk_compile_cs_params *params); /** * Compile a fixed function geometry shader. @@ -1748,23 +1748,23 @@ brw_compile_cs(const struct brw_compiler *compiler, * Returns the final assembly and the program's size. */ const unsigned * -brw_compile_ff_gs_prog(struct brw_compiler *compiler, +elk_compile_ff_gs_prog(struct elk_compiler *compiler, void *mem_ctx, - const struct brw_ff_gs_prog_key *key, - struct brw_ff_gs_prog_data *prog_data, + const struct elk_ff_gs_prog_key *key, + struct elk_ff_gs_prog_data *prog_data, struct intel_vue_map *vue_map, unsigned *final_assembly_size); -void brw_debug_key_recompile(const struct brw_compiler *c, void *log, +void elk_debug_key_recompile(const struct elk_compiler *c, void *log, gl_shader_stage stage, - const struct brw_base_prog_key *old_key, - const struct brw_base_prog_key *key); + const struct elk_base_prog_key *old_key, + const struct elk_base_prog_key *key); /* Shared Local Memory Size is specified as powers of two, * and also have a Gen-dependent minimum value if not zero. */ static inline uint32_t -intel_calculate_slm_size(unsigned gen, uint32_t bytes) +elk_calculate_slm_size(unsigned gen, uint32_t bytes) { assert(bytes <= 64 * 1024); if (bytes > 0) @@ -1774,7 +1774,7 @@ intel_calculate_slm_size(unsigned gen, uint32_t bytes) } static inline uint32_t -encode_slm_size(unsigned gen, uint32_t bytes) +elk_encode_slm_size(unsigned gen, uint32_t bytes) { uint32_t slm_size = 0; @@ -1789,7 +1789,7 @@ encode_slm_size(unsigned gen, uint32_t bytes) */ if (bytes > 0) { - slm_size = intel_calculate_slm_size(gen, bytes); + slm_size = elk_calculate_slm_size(gen, bytes); assert(util_is_power_of_two_nonzero(slm_size)); if (gen >= 9) { @@ -1807,14 +1807,14 @@ encode_slm_size(unsigned gen, uint32_t bytes) } unsigned -brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data, +elk_cs_push_const_total_size(const struct elk_cs_prog_data *cs_prog_data, unsigned threads); void -brw_write_shader_relocs(const struct brw_isa_info *isa, +elk_write_shader_relocs(const struct elk_isa_info *isa, void *program, - const struct brw_stage_prog_data *prog_data, - struct brw_shader_reloc_value *values, + const struct elk_stage_prog_data *prog_data, + struct elk_shader_reloc_value *values, unsigned num_values); /** @@ -1827,8 +1827,8 @@ brw_write_shader_relocs(const struct brw_isa_info *isa, * time (so prog_data is outdated). */ struct intel_cs_dispatch_info -brw_cs_get_dispatch_info(const struct intel_device_info *devinfo, - const struct brw_cs_prog_data *prog_data, +elk_cs_get_dispatch_info(const struct intel_device_info *devinfo, + const struct elk_cs_prog_data *prog_data, const unsigned *override_local_size); /** @@ -1838,13 +1838,13 @@ brw_cs_get_dispatch_info(const struct intel_device_info *devinfo, * '2^n - 1' for some n. */ static inline bool -brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo, +elk_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo, gl_shader_stage stage, unsigned max_polygons, - const struct brw_stage_prog_data *prog_data) + const struct elk_stage_prog_data *prog_data) { /* The code below makes assumptions about the hardware's thread dispatch * behavior that could be proven wrong in future generations -- Make sure - * to do a full test run with brw_fs_test_dispatch_packing() hooked up to + * to do a full test run with elk_fs_test_dispatch_packing() hooked up to * the NIR front-end before changing this assertion. */ assert(devinfo->ver <= 12); @@ -1859,8 +1859,8 @@ brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo, * the SIMD thread, so dispatch of unlit samples cannot be avoided in * general and we should return false. */ - const struct brw_wm_prog_data *wm_prog_data = - (const struct brw_wm_prog_data *)prog_data; + const struct elk_wm_prog_data *wm_prog_data = + (const struct elk_wm_prog_data *)prog_data; return devinfo->verx10 < 125 && !wm_prog_data->persample_dispatch && wm_prog_data->uses_vmask && @@ -1898,7 +1898,7 @@ brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo, * part of the vue header, so if these are read we can't skip anything. */ static inline int -brw_compute_first_urb_slot_required(uint64_t inputs_read, +elk_compute_first_urb_slot_required(uint64_t inputs_read, const struct intel_vue_map *prev_stage_vue_map) { if ((inputs_read & (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PRIMITIVE_SHADING_RATE)) == 0) { @@ -1917,17 +1917,17 @@ brw_compute_first_urb_slot_required(uint64_t inputs_read, * intrinsic. This is used to return different values based on some aspect of * the topology of the device. */ -enum brw_topology_id +enum elk_topology_id { /* A value based of the DSS identifier the shader is currently running on. * Be mindful that the DSS ID can be higher than the total number of DSS on * the device. This is because of the fusing that can occur on different * parts. */ - BRW_TOPOLOGY_ID_DSS, + ELK_TOPOLOGY_ID_DSS, /* A value composed of EU ID, thread ID & SIMD lane ID. */ - BRW_TOPOLOGY_ID_EU_THREAD_SIMD, + ELK_TOPOLOGY_ID_EU_THREAD_SIMD, }; #ifdef __cplusplus diff --git a/src/intel/compiler/elk/elk_dead_control_flow.cpp b/src/intel/compiler/elk/elk_dead_control_flow.cpp index 7bb549a5aac..e4618292735 100644 --- a/src/intel/compiler/elk/elk_dead_control_flow.cpp +++ b/src/intel/compiler/elk/elk_dead_control_flow.cpp @@ -38,37 +38,37 @@ using namespace elk; * - then in if/else/endif */ bool -dead_control_flow_eliminate(backend_shader *s) +elk_dead_control_flow_eliminate(elk_backend_shader *s) { bool progress = false; foreach_block_safe (block, s->cfg) { - bblock_t *prev_block = block->prev(); + elk_bblock_t *prev_block = block->prev(); if (!prev_block) continue; - backend_instruction *const inst = block->start(); - backend_instruction *const prev_inst = prev_block->end(); + elk_backend_instruction *const inst = block->start(); + elk_backend_instruction *const prev_inst = prev_block->end(); /* ENDIF instructions, by definition, can only be found at the start of * basic blocks. */ - if (inst->opcode == BRW_OPCODE_ENDIF && - prev_inst->opcode == BRW_OPCODE_ELSE) { - bblock_t *const else_block = prev_block; - backend_instruction *const else_inst = prev_inst; + if (inst->opcode == ELK_OPCODE_ENDIF && + prev_inst->opcode == ELK_OPCODE_ELSE) { + elk_bblock_t *const else_block = prev_block; + elk_backend_instruction *const else_inst = prev_inst; else_inst->remove(else_block); progress = true; - } else if (inst->opcode == BRW_OPCODE_ENDIF && - prev_inst->opcode == BRW_OPCODE_IF) { - bblock_t *const endif_block = block; - bblock_t *const if_block = prev_block; - backend_instruction *const endif_inst = inst; - backend_instruction *const if_inst = prev_inst; + } else if (inst->opcode == ELK_OPCODE_ENDIF && + prev_inst->opcode == ELK_OPCODE_IF) { + elk_bblock_t *const endif_block = block; + elk_bblock_t *const if_block = prev_block; + elk_backend_instruction *const endif_inst = inst; + elk_backend_instruction *const if_inst = prev_inst; - bblock_t *earlier_block = NULL, *later_block = NULL; + elk_bblock_t *earlier_block = NULL, *later_block = NULL; if (if_block->start_ip == if_block->end_ip) { earlier_block = if_block->prev(); @@ -98,11 +98,11 @@ dead_control_flow_eliminate(backend_shader *s) } progress = true; - } else if (inst->opcode == BRW_OPCODE_ELSE && - prev_inst->opcode == BRW_OPCODE_IF) { - bblock_t *const else_block = block; - backend_instruction *const if_inst = prev_inst; - backend_instruction *const else_inst = inst; + } else if (inst->opcode == ELK_OPCODE_ELSE && + prev_inst->opcode == ELK_OPCODE_IF) { + elk_bblock_t *const else_block = block; + elk_backend_instruction *const if_inst = prev_inst; + elk_backend_instruction *const else_inst = inst; /* Since the else-branch is becoming the new then-branch, the * condition has to be inverted. diff --git a/src/intel/compiler/elk/elk_dead_control_flow.h b/src/intel/compiler/elk/elk_dead_control_flow.h index e97f1cc125f..bd8956b9307 100644 --- a/src/intel/compiler/elk/elk_dead_control_flow.h +++ b/src/intel/compiler/elk/elk_dead_control_flow.h @@ -26,6 +26,6 @@ #include "elk_shader.h" -bool dead_control_flow_eliminate(backend_shader *s); +bool elk_dead_control_flow_eliminate(elk_backend_shader *s); #endif /* ELK_DEAD_CONTROL_FLOW_H */ diff --git a/src/intel/compiler/elk/elk_debug_recompile.c b/src/intel/compiler/elk/elk_debug_recompile.c index 20f6337fb97..7ea62378292 100644 --- a/src/intel/compiler/elk/elk_debug_recompile.c +++ b/src/intel/compiler/elk/elk_debug_recompile.c @@ -29,22 +29,22 @@ #include "elk_compiler.h" static bool -key_debug(const struct brw_compiler *c, void *log, +key_debug(const struct elk_compiler *c, void *log, const char *name, int a, int b) { if (a != b) { - brw_shader_perf_log(c, log, " %s %d->%d\n", name, a, b); + elk_shader_perf_log(c, log, " %s %d->%d\n", name, a, b); return true; } return false; } static bool -key_debug_float(const struct brw_compiler *c, void *log, +key_debug_float(const struct elk_compiler *c, void *log, const char *name, float a, float b) { if (a != b) { - brw_shader_perf_log(c, log, " %s %f->%f\n", name, a, b); + elk_shader_perf_log(c, log, " %s %f->%f\n", name, a, b); return true; } return false; @@ -56,15 +56,15 @@ key_debug_float(const struct brw_compiler *c, void *log, key_debug_float(c, log, name, old_key->field, key->field) static bool -debug_sampler_recompile(const struct brw_compiler *c, void *log, - const struct brw_sampler_prog_key_data *old_key, - const struct brw_sampler_prog_key_data *key) +debug_sampler_recompile(const struct elk_compiler *c, void *log, + const struct elk_sampler_prog_key_data *old_key, + const struct elk_sampler_prog_key_data *key) { bool found = false; found |= check("gather channel quirk", gather_channel_quirk_mask); - for (unsigned i = 0; i < BRW_MAX_SAMPLERS; i++) { + for (unsigned i = 0; i < ELK_MAX_SAMPLERS; i++) { found |= check("EXT_texture_swizzle or DEPTH_TEXTURE_MODE", swizzles[i]); found |= check("textureGather workarounds", gfx6_gather_wa[i]); } @@ -77,17 +77,17 @@ debug_sampler_recompile(const struct brw_compiler *c, void *log, } static bool -debug_base_recompile(const struct brw_compiler *c, void *log, - const struct brw_base_prog_key *old_key, - const struct brw_base_prog_key *key) +debug_base_recompile(const struct elk_compiler *c, void *log, + const struct elk_base_prog_key *old_key, + const struct elk_base_prog_key *key) { return debug_sampler_recompile(c, log, &old_key->tex, &key->tex); } static void -debug_vs_recompile(const struct brw_compiler *c, void *log, - const struct brw_vs_prog_key *old_key, - const struct brw_vs_prog_key *key) +debug_vs_recompile(const struct elk_compiler *c, void *log, + const struct elk_vs_prog_key *old_key, + const struct elk_vs_prog_key *key) { bool found = debug_base_recompile(c, log, &old_key->base, &key->base); @@ -101,14 +101,14 @@ debug_vs_recompile(const struct brw_compiler *c, void *log, found |= check("vertex color clamping", clamp_vertex_color); if (!found) { - brw_shader_perf_log(c, log, " something else\n"); + elk_shader_perf_log(c, log, " something else\n"); } } static void -debug_tcs_recompile(const struct brw_compiler *c, void *log, - const struct brw_tcs_prog_key *old_key, - const struct brw_tcs_prog_key *key) +debug_tcs_recompile(const struct elk_compiler *c, void *log, + const struct elk_tcs_prog_key *old_key, + const struct elk_tcs_prog_key *key) { bool found = debug_base_recompile(c, log, &old_key->base, &key->base); @@ -119,14 +119,14 @@ debug_tcs_recompile(const struct brw_compiler *c, void *log, found |= check("quads and equal_spacing workaround", quads_workaround); if (!found) { - brw_shader_perf_log(c, log, " something else\n"); + elk_shader_perf_log(c, log, " something else\n"); } } static void -debug_tes_recompile(const struct brw_compiler *c, void *log, - const struct brw_tes_prog_key *old_key, - const struct brw_tes_prog_key *key) +debug_tes_recompile(const struct elk_compiler *c, void *log, + const struct elk_tes_prog_key *old_key, + const struct elk_tes_prog_key *key) { bool found = debug_base_recompile(c, log, &old_key->base, &key->base); @@ -134,26 +134,26 @@ debug_tes_recompile(const struct brw_compiler *c, void *log, found |= check("patch inputs read", patch_inputs_read); if (!found) { - brw_shader_perf_log(c, log, " something else\n"); + elk_shader_perf_log(c, log, " something else\n"); } } static void -debug_gs_recompile(const struct brw_compiler *c, void *log, - const struct brw_gs_prog_key *old_key, - const struct brw_gs_prog_key *key) +debug_gs_recompile(const struct elk_compiler *c, void *log, + const struct elk_gs_prog_key *old_key, + const struct elk_gs_prog_key *key) { bool found = debug_base_recompile(c, log, &old_key->base, &key->base); if (!found) { - brw_shader_perf_log(c, log, " something else\n"); + elk_shader_perf_log(c, log, " something else\n"); } } static void -debug_fs_recompile(const struct brw_compiler *c, void *log, - const struct brw_wm_prog_key *old_key, - const struct brw_wm_prog_key *key) +debug_fs_recompile(const struct elk_compiler *c, void *log, + const struct elk_wm_prog_key *old_key, + const struct elk_wm_prog_key *key) { bool found = false; @@ -180,57 +180,57 @@ debug_fs_recompile(const struct brw_compiler *c, void *log, found |= debug_base_recompile(c, log, &old_key->base, &key->base); if (!found) { - brw_shader_perf_log(c, log, " something else\n"); + elk_shader_perf_log(c, log, " something else\n"); } } static void -debug_cs_recompile(const struct brw_compiler *c, void *log, - const struct brw_cs_prog_key *old_key, - const struct brw_cs_prog_key *key) +debug_cs_recompile(const struct elk_compiler *c, void *log, + const struct elk_cs_prog_key *old_key, + const struct elk_cs_prog_key *key) { bool found = debug_base_recompile(c, log, &old_key->base, &key->base); if (!found) { - brw_shader_perf_log(c, log, " something else\n"); + elk_shader_perf_log(c, log, " something else\n"); } } void -brw_debug_key_recompile(const struct brw_compiler *c, void *log, +elk_debug_key_recompile(const struct elk_compiler *c, void *log, gl_shader_stage stage, - const struct brw_base_prog_key *old_key, - const struct brw_base_prog_key *key) + const struct elk_base_prog_key *old_key, + const struct elk_base_prog_key *key) { if (!old_key) { - brw_shader_perf_log(c, log, " No previous compile found...\n"); + elk_shader_perf_log(c, log, " No previous compile found...\n"); return; } switch (stage) { case MESA_SHADER_VERTEX: - debug_vs_recompile(c, log, (const struct brw_vs_prog_key *)old_key, - (const struct brw_vs_prog_key *)key); + debug_vs_recompile(c, log, (const struct elk_vs_prog_key *)old_key, + (const struct elk_vs_prog_key *)key); break; case MESA_SHADER_TESS_CTRL: - debug_tcs_recompile(c, log, (const struct brw_tcs_prog_key *)old_key, - (const struct brw_tcs_prog_key *)key); + debug_tcs_recompile(c, log, (const struct elk_tcs_prog_key *)old_key, + (const struct elk_tcs_prog_key *)key); break; case MESA_SHADER_TESS_EVAL: - debug_tes_recompile(c, log, (const struct brw_tes_prog_key *)old_key, - (const struct brw_tes_prog_key *)key); + debug_tes_recompile(c, log, (const struct elk_tes_prog_key *)old_key, + (const struct elk_tes_prog_key *)key); break; case MESA_SHADER_GEOMETRY: - debug_gs_recompile(c, log, (const struct brw_gs_prog_key *)old_key, - (const struct brw_gs_prog_key *)key); + debug_gs_recompile(c, log, (const struct elk_gs_prog_key *)old_key, + (const struct elk_gs_prog_key *)key); break; case MESA_SHADER_FRAGMENT: - debug_fs_recompile(c, log, (const struct brw_wm_prog_key *)old_key, - (const struct brw_wm_prog_key *)key); + debug_fs_recompile(c, log, (const struct elk_wm_prog_key *)old_key, + (const struct elk_wm_prog_key *)key); break; case MESA_SHADER_COMPUTE: - debug_cs_recompile(c, log, (const struct brw_cs_prog_key *)old_key, - (const struct brw_cs_prog_key *)key); + debug_cs_recompile(c, log, (const struct elk_cs_prog_key *)old_key, + (const struct elk_cs_prog_key *)key); break; default: break; diff --git a/src/intel/compiler/elk/elk_disasm.c b/src/intel/compiler/elk/elk_disasm.c index 01bf11d99d2..0a00aab3114 100644 --- a/src/intel/compiler/elk/elk_disasm.c +++ b/src/intel/compiler/elk/elk_disasm.c @@ -37,60 +37,60 @@ #include "util/half_float.h" bool -brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode) +elk_has_jip(const struct intel_device_info *devinfo, enum elk_opcode opcode) { if (devinfo->ver < 6) return false; - return opcode == BRW_OPCODE_IF || - opcode == BRW_OPCODE_ELSE || - opcode == BRW_OPCODE_ENDIF || - opcode == BRW_OPCODE_WHILE || - opcode == BRW_OPCODE_BREAK || - opcode == BRW_OPCODE_CONTINUE || - opcode == BRW_OPCODE_HALT; + return opcode == ELK_OPCODE_IF || + opcode == ELK_OPCODE_ELSE || + opcode == ELK_OPCODE_ENDIF || + opcode == ELK_OPCODE_WHILE || + opcode == ELK_OPCODE_BREAK || + opcode == ELK_OPCODE_CONTINUE || + opcode == ELK_OPCODE_HALT; } bool -brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode) +elk_has_uip(const struct intel_device_info *devinfo, enum elk_opcode opcode) { if (devinfo->ver < 6) return false; - return (devinfo->ver >= 7 && opcode == BRW_OPCODE_IF) || - (devinfo->ver >= 8 && opcode == BRW_OPCODE_ELSE) || - opcode == BRW_OPCODE_BREAK || - opcode == BRW_OPCODE_CONTINUE || - opcode == BRW_OPCODE_HALT; + return (devinfo->ver >= 7 && opcode == ELK_OPCODE_IF) || + (devinfo->ver >= 8 && opcode == ELK_OPCODE_ELSE) || + opcode == ELK_OPCODE_BREAK || + opcode == ELK_OPCODE_CONTINUE || + opcode == ELK_OPCODE_HALT; } static bool -has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode) +has_branch_ctrl(const struct intel_device_info *devinfo, enum elk_opcode opcode) { if (devinfo->ver < 8) return false; - return opcode == BRW_OPCODE_IF || - opcode == BRW_OPCODE_ELSE; - /* opcode == BRW_OPCODE_GOTO; */ + return opcode == ELK_OPCODE_IF || + opcode == ELK_OPCODE_ELSE; + /* opcode == ELK_OPCODE_GOTO; */ } static bool is_logic_instruction(unsigned opcode) { - return opcode == BRW_OPCODE_AND || - opcode == BRW_OPCODE_NOT || - opcode == BRW_OPCODE_OR || - opcode == BRW_OPCODE_XOR; + return opcode == ELK_OPCODE_AND || + opcode == ELK_OPCODE_NOT || + opcode == ELK_OPCODE_OR || + opcode == ELK_OPCODE_XOR; } static bool is_send(unsigned opcode) { - return opcode == BRW_OPCODE_SEND || - opcode == BRW_OPCODE_SENDC || - opcode == BRW_OPCODE_SENDS || - opcode == BRW_OPCODE_SENDSC; + return opcode == ELK_OPCODE_SEND || + opcode == ELK_OPCODE_SENDC || + opcode == ELK_OPCODE_SENDS || + opcode == ELK_OPCODE_SENDSC; } static bool @@ -99,21 +99,21 @@ is_split_send(UNUSED const struct intel_device_info *devinfo, unsigned opcode) if (devinfo->ver >= 12) return is_send(opcode); else - return opcode == BRW_OPCODE_SENDS || - opcode == BRW_OPCODE_SENDSC; + return opcode == ELK_OPCODE_SENDS || + opcode == ELK_OPCODE_SENDSC; } -const char *const conditional_modifier[16] = { - [BRW_CONDITIONAL_NONE] = "", - [BRW_CONDITIONAL_Z] = ".z", - [BRW_CONDITIONAL_NZ] = ".nz", - [BRW_CONDITIONAL_G] = ".g", - [BRW_CONDITIONAL_GE] = ".ge", - [BRW_CONDITIONAL_L] = ".l", - [BRW_CONDITIONAL_LE] = ".le", - [BRW_CONDITIONAL_R] = ".r", - [BRW_CONDITIONAL_O] = ".o", - [BRW_CONDITIONAL_U] = ".u", +const char *const elk_conditional_modifier[16] = { + [ELK_CONDITIONAL_NONE] = "", + [ELK_CONDITIONAL_Z] = ".z", + [ELK_CONDITIONAL_NZ] = ".nz", + [ELK_CONDITIONAL_G] = ".g", + [ELK_CONDITIONAL_GE] = ".ge", + [ELK_CONDITIONAL_L] = ".l", + [ELK_CONDITIONAL_LE] = ".le", + [ELK_CONDITIONAL_R] = ".r", + [ELK_CONDITIONAL_O] = ".o", + [ELK_CONDITIONAL_U] = ".u", }; static const char *const m_negate[2] = { @@ -205,7 +205,7 @@ static const char *const pred_inv[2] = { [1] = "-" }; -const char *const pred_ctrl_align16[16] = { +const char *const elk_pred_ctrl_align16[16] = { [1] = "", [2] = ".x", [3] = ".y", @@ -216,31 +216,31 @@ const char *const pred_ctrl_align16[16] = { }; static const char *const pred_ctrl_align1[16] = { - [BRW_PREDICATE_NORMAL] = "", - [BRW_PREDICATE_ALIGN1_ANYV] = ".anyv", - [BRW_PREDICATE_ALIGN1_ALLV] = ".allv", - [BRW_PREDICATE_ALIGN1_ANY2H] = ".any2h", - [BRW_PREDICATE_ALIGN1_ALL2H] = ".all2h", - [BRW_PREDICATE_ALIGN1_ANY4H] = ".any4h", - [BRW_PREDICATE_ALIGN1_ALL4H] = ".all4h", - [BRW_PREDICATE_ALIGN1_ANY8H] = ".any8h", - [BRW_PREDICATE_ALIGN1_ALL8H] = ".all8h", - [BRW_PREDICATE_ALIGN1_ANY16H] = ".any16h", - [BRW_PREDICATE_ALIGN1_ALL16H] = ".all16h", - [BRW_PREDICATE_ALIGN1_ANY32H] = ".any32h", - [BRW_PREDICATE_ALIGN1_ALL32H] = ".all32h", + [ELK_PREDICATE_NORMAL] = "", + [ELK_PREDICATE_ALIGN1_ANYV] = ".anyv", + [ELK_PREDICATE_ALIGN1_ALLV] = ".allv", + [ELK_PREDICATE_ALIGN1_ANY2H] = ".any2h", + [ELK_PREDICATE_ALIGN1_ALL2H] = ".all2h", + [ELK_PREDICATE_ALIGN1_ANY4H] = ".any4h", + [ELK_PREDICATE_ALIGN1_ALL4H] = ".all4h", + [ELK_PREDICATE_ALIGN1_ANY8H] = ".any8h", + [ELK_PREDICATE_ALIGN1_ALL8H] = ".all8h", + [ELK_PREDICATE_ALIGN1_ANY16H] = ".any16h", + [ELK_PREDICATE_ALIGN1_ALL16H] = ".all16h", + [ELK_PREDICATE_ALIGN1_ANY32H] = ".any32h", + [ELK_PREDICATE_ALIGN1_ALL32H] = ".all32h", }; static const char *const xe2_pred_ctrl[4] = { - [BRW_PREDICATE_NORMAL] = "", + [ELK_PREDICATE_NORMAL] = "", [XE2_PREDICATE_ANY] = ".any", [XE2_PREDICATE_ALL] = ".all", }; static const char *const thread_ctrl[4] = { - [BRW_THREAD_NORMAL] = "", - [BRW_THREAD_ATOMIC] = "atomic", - [BRW_THREAD_SWITCH] = "switch", + [ELK_THREAD_NORMAL] = "", + [ELK_THREAD_ATOMIC] = "atomic", + [ELK_THREAD_SWITCH] = "switch", }; static const char *const compr_ctrl[4] = { @@ -300,24 +300,24 @@ static const char *const end_of_thread[2] = { /* SFIDs on Gfx4-5 */ static const char *const gfx4_sfid[16] = { - [BRW_SFID_NULL] = "null", - [BRW_SFID_MATH] = "math", - [BRW_SFID_SAMPLER] = "sampler", - [BRW_SFID_MESSAGE_GATEWAY] = "gateway", - [BRW_SFID_DATAPORT_READ] = "read", - [BRW_SFID_DATAPORT_WRITE] = "write", - [BRW_SFID_URB] = "urb", - [BRW_SFID_THREAD_SPAWNER] = "thread_spawner", - [BRW_SFID_VME] = "vme", + [ELK_SFID_NULL] = "null", + [ELK_SFID_MATH] = "math", + [ELK_SFID_SAMPLER] = "sampler", + [ELK_SFID_MESSAGE_GATEWAY] = "gateway", + [ELK_SFID_DATAPORT_READ] = "read", + [ELK_SFID_DATAPORT_WRITE] = "write", + [ELK_SFID_URB] = "urb", + [ELK_SFID_THREAD_SPAWNER] = "thread_spawner", + [ELK_SFID_VME] = "vme", }; static const char *const gfx6_sfid[16] = { - [BRW_SFID_NULL] = "null", - [BRW_SFID_MATH] = "math", - [BRW_SFID_SAMPLER] = "sampler", - [BRW_SFID_MESSAGE_GATEWAY] = "gateway", - [BRW_SFID_URB] = "urb", - [BRW_SFID_THREAD_SPAWNER] = "thread_spawner", + [ELK_SFID_NULL] = "null", + [ELK_SFID_MATH] = "math", + [ELK_SFID_SAMPLER] = "sampler", + [ELK_SFID_MESSAGE_GATEWAY] = "gateway", + [ELK_SFID_URB] = "urb", + [ELK_SFID_THREAD_SPAWNER] = "thread_spawner", [GFX6_SFID_DATAPORT_SAMPLER_CACHE] = "dp_sampler", [GFX6_SFID_DATAPORT_RENDER_CACHE] = "render", [GFX6_SFID_DATAPORT_CONSTANT_CACHE] = "const", @@ -331,13 +331,13 @@ static const char *const gfx6_sfid[16] = { }; static const char *const gfx7_gateway_subfuncid[8] = { - [BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY] = "open", - [BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY] = "close", - [BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG] = "forward msg", - [BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP] = "get timestamp", - [BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG] = "barrier msg", - [BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE] = "update state", - [BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE] = "mmio read/write", + [ELK_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY] = "open", + [ELK_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY] = "close", + [ELK_MESSAGE_GATEWAY_SFID_FORWARD_MSG] = "forward msg", + [ELK_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP] = "get timestamp", + [ELK_MESSAGE_GATEWAY_SFID_BARRIER_MSG] = "barrier msg", + [ELK_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE] = "update state", + [ELK_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE] = "mmio read/write", }; static const char *const gfx4_dp_read_port_msg_type[4] = { @@ -368,7 +368,7 @@ static const char *const dp_write_port_msg_type[8] = { }; static const char *const dp_rc_msg_type_gfx6[16] = { - [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read", + [ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read", [GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read", [GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read", [GFX6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read", @@ -439,11 +439,11 @@ static const char *const dp_dc0_msg_type_gfx7[16] = { }; static const char *const dp_oword_block_rw[8] = { - [BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW] = "1-low", - [BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH] = "1-high", - [BRW_DATAPORT_OWORD_BLOCK_2_OWORDS] = "2", - [BRW_DATAPORT_OWORD_BLOCK_4_OWORDS] = "4", - [BRW_DATAPORT_OWORD_BLOCK_8_OWORDS] = "8", + [ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW] = "1-low", + [ELK_DATAPORT_OWORD_BLOCK_1_OWORDHIGH] = "1-high", + [ELK_DATAPORT_OWORD_BLOCK_2_OWORDS] = "2", + [ELK_DATAPORT_OWORD_BLOCK_4_OWORDS] = "4", + [ELK_DATAPORT_OWORD_BLOCK_8_OWORDS] = "8", }; static const char *const dp_dc1_msg_type_hsw[32] = { @@ -479,28 +479,28 @@ static const char *const dp_dc1_msg_type_hsw[32] = { }; static const char *const aop[16] = { - [BRW_AOP_AND] = "and", - [BRW_AOP_OR] = "or", - [BRW_AOP_XOR] = "xor", - [BRW_AOP_MOV] = "mov", - [BRW_AOP_INC] = "inc", - [BRW_AOP_DEC] = "dec", - [BRW_AOP_ADD] = "add", - [BRW_AOP_SUB] = "sub", - [BRW_AOP_REVSUB] = "revsub", - [BRW_AOP_IMAX] = "imax", - [BRW_AOP_IMIN] = "imin", - [BRW_AOP_UMAX] = "umax", - [BRW_AOP_UMIN] = "umin", - [BRW_AOP_CMPWR] = "cmpwr", - [BRW_AOP_PREDEC] = "predec", + [ELK_AOP_AND] = "and", + [ELK_AOP_OR] = "or", + [ELK_AOP_XOR] = "xor", + [ELK_AOP_MOV] = "mov", + [ELK_AOP_INC] = "inc", + [ELK_AOP_DEC] = "dec", + [ELK_AOP_ADD] = "add", + [ELK_AOP_SUB] = "sub", + [ELK_AOP_REVSUB] = "revsub", + [ELK_AOP_IMAX] = "imax", + [ELK_AOP_IMIN] = "imin", + [ELK_AOP_UMAX] = "umax", + [ELK_AOP_UMIN] = "umin", + [ELK_AOP_CMPWR] = "cmpwr", + [ELK_AOP_PREDEC] = "predec", }; static const char *const aop_float[5] = { - [BRW_AOP_FMAX] = "fmax", - [BRW_AOP_FMIN] = "fmin", - [BRW_AOP_FCMPWR] = "fcmpwr", - [BRW_AOP_FADD] = "fadd", + [ELK_AOP_FMAX] = "fmax", + [ELK_AOP_FMIN] = "fmin", + [ELK_AOP_FCMPWR] = "fcmpwr", + [ELK_AOP_FADD] = "fadd", }; static const char * const pixel_interpolator_msg_types[4] = { @@ -511,19 +511,19 @@ static const char * const pixel_interpolator_msg_types[4] = { }; static const char *const math_function[16] = { - [BRW_MATH_FUNCTION_INV] = "inv", - [BRW_MATH_FUNCTION_LOG] = "log", - [BRW_MATH_FUNCTION_EXP] = "exp", - [BRW_MATH_FUNCTION_SQRT] = "sqrt", - [BRW_MATH_FUNCTION_RSQ] = "rsq", - [BRW_MATH_FUNCTION_SIN] = "sin", - [BRW_MATH_FUNCTION_COS] = "cos", - [BRW_MATH_FUNCTION_SINCOS] = "sincos", - [BRW_MATH_FUNCTION_FDIV] = "fdiv", - [BRW_MATH_FUNCTION_POW] = "pow", - [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod", - [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv", - [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod", + [ELK_MATH_FUNCTION_INV] = "inv", + [ELK_MATH_FUNCTION_LOG] = "log", + [ELK_MATH_FUNCTION_EXP] = "exp", + [ELK_MATH_FUNCTION_SQRT] = "sqrt", + [ELK_MATH_FUNCTION_RSQ] = "rsq", + [ELK_MATH_FUNCTION_SIN] = "sin", + [ELK_MATH_FUNCTION_COS] = "cos", + [ELK_MATH_FUNCTION_SINCOS] = "sincos", + [ELK_MATH_FUNCTION_FDIV] = "fdiv", + [ELK_MATH_FUNCTION_POW] = "pow", + [ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod", + [ELK_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv", + [ELK_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod", [GFX8_MATH_FUNCTION_INVM] = "invm", [GFX8_MATH_FUNCTION_RSQRTM] = "rsqrtm", }; @@ -563,10 +563,10 @@ static const char *const gfx5_urb_opcode[] = { }; static const char *const gfx7_urb_opcode[] = { - [BRW_URB_OPCODE_WRITE_HWORD] = "write HWord", - [BRW_URB_OPCODE_WRITE_OWORD] = "write OWord", - [BRW_URB_OPCODE_READ_HWORD] = "read HWord", - [BRW_URB_OPCODE_READ_OWORD] = "read OWord", + [ELK_URB_OPCODE_WRITE_HWORD] = "write HWord", + [ELK_URB_OPCODE_WRITE_OWORD] = "write OWord", + [ELK_URB_OPCODE_READ_HWORD] = "read HWord", + [ELK_URB_OPCODE_READ_OWORD] = "read OWord", [GFX7_URB_OPCODE_ATOMIC_MOV] = "atomic mov", /* Gfx7+ */ [GFX7_URB_OPCODE_ATOMIC_INC] = "atomic inc", /* Gfx7+ */ [GFX8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gfx8+ */ @@ -577,9 +577,9 @@ static const char *const gfx7_urb_opcode[] = { }; static const char *const urb_swizzle[4] = { - [BRW_URB_SWIZZLE_NONE] = "", - [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave", - [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose", + [ELK_URB_SWIZZLE_NONE] = "", + [ELK_URB_SWIZZLE_INTERLEAVE] = "interleave", + [ELK_URB_SWIZZLE_TRANSPOSE] = "transpose", }; static const char *const urb_allocate[2] = { @@ -651,10 +651,10 @@ static const char *const xe2_sampler_msg_type[] = { }; static const char *const gfx5_sampler_simd_mode[7] = { - [BRW_SAMPLER_SIMD_MODE_SIMD4X2] = "SIMD4x2", - [BRW_SAMPLER_SIMD_MODE_SIMD8] = "SIMD8", - [BRW_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16", - [BRW_SAMPLER_SIMD_MODE_SIMD32_64] = "SIMD32/64", + [ELK_SAMPLER_SIMD_MODE_SIMD4X2] = "SIMD4x2", + [ELK_SAMPLER_SIMD_MODE_SIMD8] = "SIMD8", + [ELK_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16", + [ELK_SAMPLER_SIMD_MODE_SIMD32_64] = "SIMD32/64", [GFX10_SAMPLER_SIMD_MODE_SIMD8H] = "SIMD8H", [GFX10_SAMPLER_SIMD_MODE_SIMD16H] = "SIMD16H", }; @@ -891,10 +891,10 @@ control(FILE *file, const char *name, const char *const ctrl[], } static int -print_opcode(FILE *file, const struct brw_isa_info *isa, - enum opcode id) +print_opcode(FILE *file, const struct elk_isa_info *isa, + enum elk_opcode id) { - const struct opcode_desc *desc = brw_opcode_desc(isa, id); + const struct elk_opcode_desc *desc = elk_opcode_desc(isa, id); if (!desc) { format(file, "*** invalid opcode value %d ", id); return 1; @@ -909,49 +909,49 @@ reg(FILE *file, unsigned _reg_file, unsigned _reg_nr) int err = 0; /* Clear the Compr4 instruction compression bit. */ - if (_reg_file == BRW_MESSAGE_REGISTER_FILE) - _reg_nr &= ~BRW_MRF_COMPR4; + if (_reg_file == ELK_MESSAGE_REGISTER_FILE) + _reg_nr &= ~ELK_MRF_COMPR4; - if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) { + if (_reg_file == ELK_ARCHITECTURE_REGISTER_FILE) { switch (_reg_nr & 0xf0) { - case BRW_ARF_NULL: + case ELK_ARF_NULL: string(file, "null"); break; - case BRW_ARF_ADDRESS: + case ELK_ARF_ADDRESS: format(file, "a%d", _reg_nr & 0x0f); break; - case BRW_ARF_ACCUMULATOR: + case ELK_ARF_ACCUMULATOR: format(file, "acc%d", _reg_nr & 0x0f); break; - case BRW_ARF_FLAG: + case ELK_ARF_FLAG: format(file, "f%d", _reg_nr & 0x0f); break; - case BRW_ARF_MASK: + case ELK_ARF_MASK: format(file, "mask%d", _reg_nr & 0x0f); break; - case BRW_ARF_MASK_STACK: + case ELK_ARF_MASK_STACK: format(file, "ms%d", _reg_nr & 0x0f); break; - case BRW_ARF_MASK_STACK_DEPTH: + case ELK_ARF_MASK_STACK_DEPTH: format(file, "msd%d", _reg_nr & 0x0f); break; - case BRW_ARF_STATE: + case ELK_ARF_STATE: format(file, "sr%d", _reg_nr & 0x0f); break; - case BRW_ARF_CONTROL: + case ELK_ARF_CONTROL: format(file, "cr%d", _reg_nr & 0x0f); break; - case BRW_ARF_NOTIFICATION_COUNT: + case ELK_ARF_NOTIFICATION_COUNT: format(file, "n%d", _reg_nr & 0x0f); break; - case BRW_ARF_IP: + case ELK_ARF_IP: string(file, "ip"); return -1; break; - case BRW_ARF_TDR: + case ELK_ARF_TDR: format(file, "tdr0"); return -1; - case BRW_ARF_TIMESTAMP: + case ELK_ARF_TIMESTAMP: format(file, "tm%d", _reg_nr & 0x0f); break; default: @@ -966,77 +966,77 @@ reg(FILE *file, unsigned _reg_file, unsigned _reg_nr) } static int -dest(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) +dest(FILE *file, const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - enum brw_reg_type type = brw_inst_dst_type(devinfo, inst); - unsigned elem_size = brw_reg_type_to_size(type); + enum elk_reg_type type = elk_inst_dst_type(devinfo, inst); + unsigned elem_size = elk_reg_type_to_size(type); int err = 0; - if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) { + if (is_split_send(devinfo, elk_inst_opcode(isa, inst))) { /* These are fixed for split sends */ - type = BRW_REGISTER_TYPE_UD; + type = ELK_REGISTER_TYPE_UD; elem_size = 4; if (devinfo->ver >= 12) { - err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst), - brw_inst_dst_da_reg_nr(devinfo, inst)); - string(file, brw_reg_type_to_letters(type)); - } else if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { - err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst), - brw_inst_dst_da_reg_nr(devinfo, inst)); - unsigned subreg_nr = brw_inst_dst_da16_subreg_nr(devinfo, inst); + err |= reg(file, elk_inst_send_dst_reg_file(devinfo, inst), + elk_inst_dst_da_reg_nr(devinfo, inst)); + string(file, elk_reg_type_to_letters(type)); + } else if (elk_inst_dst_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { + err |= reg(file, elk_inst_send_dst_reg_file(devinfo, inst), + elk_inst_dst_da_reg_nr(devinfo, inst)); + unsigned subreg_nr = elk_inst_dst_da16_subreg_nr(devinfo, inst); if (subreg_nr) format(file, ".%u", subreg_nr); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); } else { string(file, "g[a0"); - if (brw_inst_dst_ia_subreg_nr(devinfo, inst)) - format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) / + if (elk_inst_dst_ia_subreg_nr(devinfo, inst)) + format(file, ".%"PRIu64, elk_inst_dst_ia_subreg_nr(devinfo, inst) / elem_size); - if (brw_inst_send_dst_ia16_addr_imm(devinfo, inst)) - format(file, " %d", brw_inst_send_dst_ia16_addr_imm(devinfo, inst)); + if (elk_inst_send_dst_ia16_addr_imm(devinfo, inst)) + format(file, " %d", elk_inst_send_dst_ia16_addr_imm(devinfo, inst)); string(file, "]<"); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); } - } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { - err |= reg(file, brw_inst_dst_reg_file(devinfo, inst), - brw_inst_dst_da_reg_nr(devinfo, inst)); + } else if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + if (elk_inst_dst_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { + err |= reg(file, elk_inst_dst_reg_file(devinfo, inst), + elk_inst_dst_da_reg_nr(devinfo, inst)); if (err == -1) return 0; - if (brw_inst_dst_da1_subreg_nr(devinfo, inst)) - format(file, ".%"PRIu64, brw_inst_dst_da1_subreg_nr(devinfo, inst) / + if (elk_inst_dst_da1_subreg_nr(devinfo, inst)) + format(file, ".%"PRIu64, elk_inst_dst_da1_subreg_nr(devinfo, inst) / elem_size); string(file, "<"); err |= control(file, "horiz stride", horiz_stride, - brw_inst_dst_hstride(devinfo, inst), NULL); + elk_inst_dst_hstride(devinfo, inst), NULL); string(file, ">"); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); } else { string(file, "g[a0"); - if (brw_inst_dst_ia_subreg_nr(devinfo, inst)) - format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) / + if (elk_inst_dst_ia_subreg_nr(devinfo, inst)) + format(file, ".%"PRIu64, elk_inst_dst_ia_subreg_nr(devinfo, inst) / elem_size); - if (brw_inst_dst_ia1_addr_imm(devinfo, inst)) - format(file, " %d", brw_inst_dst_ia1_addr_imm(devinfo, inst)); + if (elk_inst_dst_ia1_addr_imm(devinfo, inst)) + format(file, " %d", elk_inst_dst_ia1_addr_imm(devinfo, inst)); string(file, "]<"); err |= control(file, "horiz stride", horiz_stride, - brw_inst_dst_hstride(devinfo, inst), NULL); + elk_inst_dst_hstride(devinfo, inst), NULL); string(file, ">"); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); } } else { - if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { - err |= reg(file, brw_inst_dst_reg_file(devinfo, inst), - brw_inst_dst_da_reg_nr(devinfo, inst)); + if (elk_inst_dst_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { + err |= reg(file, elk_inst_dst_reg_file(devinfo, inst), + elk_inst_dst_da_reg_nr(devinfo, inst)); if (err == -1) return 0; - if (brw_inst_dst_da16_subreg_nr(devinfo, inst)) + if (elk_inst_dst_da16_subreg_nr(devinfo, inst)) format(file, ".%u", 16 / elem_size); string(file, "<1>"); err |= control(file, "writemask", writemask, - brw_inst_da16_writemask(devinfo, inst), NULL); - string(file, brw_reg_type_to_letters(type)); + elk_inst_da16_writemask(devinfo, inst), NULL); + string(file, elk_reg_type_to_letters(type)); } else { err = 1; string(file, "Indirect align16 address mode not supported"); @@ -1048,38 +1048,38 @@ dest(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) static int dest_3src(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { - bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; + bool is_align1 = elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1; int err = 0; uint32_t reg_file; unsigned subreg_nr; - enum brw_reg_type type; + enum elk_reg_type type; if (devinfo->ver < 10 && is_align1) return 0; - if (devinfo->ver == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst)) - reg_file = BRW_MESSAGE_REGISTER_FILE; + if (devinfo->ver == 6 && elk_inst_3src_a16_dst_reg_file(devinfo, inst)) + reg_file = ELK_MESSAGE_REGISTER_FILE; else if (devinfo->ver >= 12) - reg_file = brw_inst_3src_a1_dst_reg_file(devinfo, inst); - else if (is_align1 && brw_inst_3src_a1_dst_reg_file(devinfo, inst)) - reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + reg_file = elk_inst_3src_a1_dst_reg_file(devinfo, inst); + else if (is_align1 && elk_inst_3src_a1_dst_reg_file(devinfo, inst)) + reg_file = ELK_ARCHITECTURE_REGISTER_FILE; else - reg_file = BRW_GENERAL_REGISTER_FILE; + reg_file = ELK_GENERAL_REGISTER_FILE; - err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst)); + err |= reg(file, reg_file, elk_inst_3src_dst_reg_nr(devinfo, inst)); if (err == -1) return 0; if (is_align1) { - type = brw_inst_3src_a1_dst_type(devinfo, inst); - subreg_nr = brw_inst_3src_a1_dst_subreg_nr(devinfo, inst); + type = elk_inst_3src_a1_dst_type(devinfo, inst); + subreg_nr = elk_inst_3src_a1_dst_subreg_nr(devinfo, inst); } else { - type = brw_inst_3src_a16_dst_type(devinfo, inst); - subreg_nr = brw_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4; + type = elk_inst_3src_a16_dst_type(devinfo, inst); + subreg_nr = elk_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4; } - subreg_nr /= brw_reg_type_to_size(type); + subreg_nr /= elk_reg_type_to_size(type); if (subreg_nr) format(file, ".%u", subreg_nr); @@ -1087,30 +1087,30 @@ dest_3src(FILE *file, const struct intel_device_info *devinfo, if (!is_align1) { err |= control(file, "writemask", writemask, - brw_inst_3src_a16_dst_writemask(devinfo, inst), NULL); + elk_inst_3src_a16_dst_writemask(devinfo, inst), NULL); } - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return 0; } static int dest_dpas_3src(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { - uint32_t reg_file = brw_inst_dpas_3src_dst_reg_file(devinfo, inst); + uint32_t reg_file = elk_inst_dpas_3src_dst_reg_file(devinfo, inst); - if (reg(file, reg_file, brw_inst_dpas_3src_dst_reg_nr(devinfo, inst)) == -1) + if (reg(file, reg_file, elk_inst_dpas_3src_dst_reg_nr(devinfo, inst)) == -1) return 0; - enum brw_reg_type type = brw_inst_dpas_3src_dst_type(devinfo, inst); - unsigned subreg_nr = brw_inst_dpas_3src_dst_subreg_nr(devinfo, inst); + enum elk_reg_type type = elk_inst_dpas_3src_dst_type(devinfo, inst); + unsigned subreg_nr = elk_inst_dpas_3src_dst_subreg_nr(devinfo, inst); if (subreg_nr) format(file, ".%u", subreg_nr); string(file, "<1>"); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return 0; } @@ -1135,7 +1135,7 @@ static int src_da1(FILE *file, const struct intel_device_info *devinfo, unsigned opcode, - enum brw_reg_type type, unsigned _reg_file, + enum elk_reg_type type, unsigned _reg_file, unsigned _vert_stride, unsigned _width, unsigned _horiz_stride, unsigned reg_num, unsigned sub_reg_num, unsigned __abs, unsigned _negate) @@ -1153,11 +1153,11 @@ src_da1(FILE *file, if (err == -1) return 0; if (sub_reg_num) { - unsigned elem_size = brw_reg_type_to_size(type); + unsigned elem_size = elk_reg_type_to_size(type); format(file, ".%d", sub_reg_num / elem_size); /* use formal style like spec */ } src_align1_region(file, _vert_stride, _width, _horiz_stride); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return err; } @@ -1165,7 +1165,7 @@ static int src_ia1(FILE *file, const struct intel_device_info *devinfo, unsigned opcode, - enum brw_reg_type type, + enum elk_reg_type type, int _addr_imm, unsigned _addr_subreg_nr, unsigned _negate, @@ -1188,23 +1188,23 @@ src_ia1(FILE *file, format(file, " %d", _addr_imm); string(file, "]"); src_align1_region(file, _vert_stride, _width, _horiz_stride); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return err; } static int src_swizzle(FILE *file, unsigned swiz) { - unsigned x = BRW_GET_SWZ(swiz, BRW_CHANNEL_X); - unsigned y = BRW_GET_SWZ(swiz, BRW_CHANNEL_Y); - unsigned z = BRW_GET_SWZ(swiz, BRW_CHANNEL_Z); - unsigned w = BRW_GET_SWZ(swiz, BRW_CHANNEL_W); + unsigned x = ELK_GET_SWZ(swiz, ELK_CHANNEL_X); + unsigned y = ELK_GET_SWZ(swiz, ELK_CHANNEL_Y); + unsigned z = ELK_GET_SWZ(swiz, ELK_CHANNEL_Z); + unsigned w = ELK_GET_SWZ(swiz, ELK_CHANNEL_W); int err = 0; if (x == y && x == z && x == w) { string(file, "."); err |= control(file, "channel select", chan_sel, x, NULL); - } else if (swiz != BRW_SWIZZLE_XYZW) { + } else if (swiz != ELK_SWIZZLE_XYZW) { string(file, "."); err |= control(file, "channel select", chan_sel, x, NULL); err |= control(file, "channel select", chan_sel, y, NULL); @@ -1218,7 +1218,7 @@ static int src_da16(FILE *file, const struct intel_device_info *devinfo, unsigned opcode, - enum brw_reg_type type, + enum elk_reg_type type, unsigned _reg_file, unsigned _vert_stride, unsigned _reg_nr, @@ -1240,7 +1240,7 @@ src_da16(FILE *file, if (err == -1) return 0; if (_subreg_nr) { - unsigned elem_size = brw_reg_type_to_size(type); + unsigned elem_size = elk_reg_type_to_size(type); /* bit4 for subreg number byte addressing. Make this same meaning as in da1 case, so output looks consistent. */ @@ -1249,50 +1249,50 @@ src_da16(FILE *file, string(file, "<"); err |= control(file, "vert stride", vert_stride, _vert_stride, NULL); string(file, ">"); - err |= src_swizzle(file, BRW_SWIZZLE4(swz_x, swz_y, swz_z, swz_w)); - string(file, brw_reg_type_to_letters(type)); + err |= src_swizzle(file, ELK_SWIZZLE4(swz_x, swz_y, swz_z, swz_w)); + string(file, elk_reg_type_to_letters(type)); return err; } -static enum brw_vertical_stride +static enum elk_vertical_stride vstride_from_align1_3src_vstride(const struct intel_device_info *devinfo, enum gfx10_align1_3src_vertical_stride vstride) { switch (vstride) { - case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0; - case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2: + case ELK_ALIGN1_3SRC_VERTICAL_STRIDE_0: return ELK_VERTICAL_STRIDE_0; + case ELK_ALIGN1_3SRC_VERTICAL_STRIDE_2: if (devinfo->ver >= 12) - return BRW_VERTICAL_STRIDE_1; + return ELK_VERTICAL_STRIDE_1; else - return BRW_VERTICAL_STRIDE_2; - case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4; - case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8: return BRW_VERTICAL_STRIDE_8; + return ELK_VERTICAL_STRIDE_2; + case ELK_ALIGN1_3SRC_VERTICAL_STRIDE_4: return ELK_VERTICAL_STRIDE_4; + case ELK_ALIGN1_3SRC_VERTICAL_STRIDE_8: return ELK_VERTICAL_STRIDE_8; default: unreachable("not reached"); } } -static enum brw_horizontal_stride +static enum elk_horizontal_stride hstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride) { switch (hstride) { - case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_HORIZONTAL_STRIDE_0; - case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return BRW_HORIZONTAL_STRIDE_1; - case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_HORIZONTAL_STRIDE_2; - case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_HORIZONTAL_STRIDE_4; + case ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return ELK_HORIZONTAL_STRIDE_0; + case ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return ELK_HORIZONTAL_STRIDE_1; + case ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return ELK_HORIZONTAL_STRIDE_2; + case ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return ELK_HORIZONTAL_STRIDE_4; default: unreachable("not reached"); } } -static enum brw_vertical_stride +static enum elk_vertical_stride vstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride) { switch (hstride) { - case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0; - case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return BRW_VERTICAL_STRIDE_1; - case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_VERTICAL_STRIDE_2; - case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4; + case ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return ELK_VERTICAL_STRIDE_0; + case ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return ELK_VERTICAL_STRIDE_1; + case ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return ELK_VERTICAL_STRIDE_2; + case ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return ELK_VERTICAL_STRIDE_4; default: unreachable("not reached"); } @@ -1301,23 +1301,23 @@ vstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hs /* From "GFX10 Regioning Rules for Align1 Ternary Operations" in the * "Register Region Restrictions" documentation */ -static enum brw_width -implied_width(enum brw_vertical_stride _vert_stride, - enum brw_horizontal_stride _horiz_stride) +static enum elk_width +implied_width(enum elk_vertical_stride _vert_stride, + enum elk_horizontal_stride _horiz_stride) { /* "1. Width is 1 when Vertical and Horizontal Strides are both zero." */ - if (_vert_stride == BRW_VERTICAL_STRIDE_0 && - _horiz_stride == BRW_HORIZONTAL_STRIDE_0) { - return BRW_WIDTH_1; + if (_vert_stride == ELK_VERTICAL_STRIDE_0 && + _horiz_stride == ELK_HORIZONTAL_STRIDE_0) { + return ELK_WIDTH_1; /* "2. Width is equal to vertical stride when Horizontal Stride is zero." */ - } else if (_horiz_stride == BRW_HORIZONTAL_STRIDE_0) { + } else if (_horiz_stride == ELK_HORIZONTAL_STRIDE_0) { switch (_vert_stride) { - case BRW_VERTICAL_STRIDE_1: return BRW_WIDTH_1; - case BRW_VERTICAL_STRIDE_2: return BRW_WIDTH_2; - case BRW_VERTICAL_STRIDE_4: return BRW_WIDTH_4; - case BRW_VERTICAL_STRIDE_8: return BRW_WIDTH_8; - case BRW_VERTICAL_STRIDE_0: + case ELK_VERTICAL_STRIDE_1: return ELK_WIDTH_1; + case ELK_VERTICAL_STRIDE_2: return ELK_WIDTH_2; + case ELK_VERTICAL_STRIDE_4: return ELK_WIDTH_4; + case ELK_VERTICAL_STRIDE_8: return ELK_WIDTH_8; + case ELK_VERTICAL_STRIDE_0: default: unreachable("not reached"); } @@ -1342,78 +1342,78 @@ implied_width(enum brw_vertical_stride _vert_stride, static int src0_3src(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { int err = 0; unsigned reg_nr, subreg_nr; - enum brw_reg_file _file; - enum brw_reg_type type; - enum brw_vertical_stride _vert_stride; - enum brw_width _width; - enum brw_horizontal_stride _horiz_stride; + enum elk_reg_file _file; + enum elk_reg_type type; + enum elk_vertical_stride _vert_stride; + enum elk_width _width; + enum elk_horizontal_stride _horiz_stride; bool is_scalar_region; - bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; + bool is_align1 = elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1; if (devinfo->ver < 10 && is_align1) return 0; if (is_align1) { - if (devinfo->ver >= 12 && !brw_inst_3src_a1_src0_is_imm(devinfo, inst)) { - _file = brw_inst_3src_a1_src0_reg_file(devinfo, inst); - } else if (brw_inst_3src_a1_src0_reg_file(devinfo, inst) == - BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) { - _file = BRW_GENERAL_REGISTER_FILE; - } else if (brw_inst_3src_a1_src0_type(devinfo, inst) == - BRW_REGISTER_TYPE_NF) { - _file = BRW_ARCHITECTURE_REGISTER_FILE; + if (devinfo->ver >= 12 && !elk_inst_3src_a1_src0_is_imm(devinfo, inst)) { + _file = elk_inst_3src_a1_src0_reg_file(devinfo, inst); + } else if (elk_inst_3src_a1_src0_reg_file(devinfo, inst) == + ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE) { + _file = ELK_GENERAL_REGISTER_FILE; + } else if (elk_inst_3src_a1_src0_type(devinfo, inst) == + ELK_REGISTER_TYPE_NF) { + _file = ELK_ARCHITECTURE_REGISTER_FILE; } else { - _file = BRW_IMMEDIATE_VALUE; - uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst); - enum brw_reg_type type = brw_inst_3src_a1_src0_type(devinfo, inst); + _file = ELK_IMMEDIATE_VALUE; + uint16_t imm_val = elk_inst_3src_a1_src0_imm(devinfo, inst); + enum elk_reg_type type = elk_inst_3src_a1_src0_type(devinfo, inst); - if (type == BRW_REGISTER_TYPE_W) { + if (type == ELK_REGISTER_TYPE_W) { format(file, "%dW", imm_val); - } else if (type == BRW_REGISTER_TYPE_UW) { + } else if (type == ELK_REGISTER_TYPE_UW) { format(file, "0x%04xUW", imm_val); - } else if (type == BRW_REGISTER_TYPE_HF) { + } else if (type == ELK_REGISTER_TYPE_HF) { format(file, "0x%04xHF", imm_val); } return 0; } - reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst); - subreg_nr = brw_inst_3src_a1_src0_subreg_nr(devinfo, inst); - type = brw_inst_3src_a1_src0_type(devinfo, inst); + reg_nr = elk_inst_3src_src0_reg_nr(devinfo, inst); + subreg_nr = elk_inst_3src_a1_src0_subreg_nr(devinfo, inst); + type = elk_inst_3src_a1_src0_type(devinfo, inst); _vert_stride = vstride_from_align1_3src_vstride( - devinfo, brw_inst_3src_a1_src0_vstride(devinfo, inst)); + devinfo, elk_inst_3src_a1_src0_vstride(devinfo, inst)); _horiz_stride = hstride_from_align1_3src_hstride( - brw_inst_3src_a1_src0_hstride(devinfo, inst)); + elk_inst_3src_a1_src0_hstride(devinfo, inst)); _width = implied_width(_vert_stride, _horiz_stride); } else { - _file = BRW_GENERAL_REGISTER_FILE; - reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst); - subreg_nr = brw_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4; - type = brw_inst_3src_a16_src_type(devinfo, inst); + _file = ELK_GENERAL_REGISTER_FILE; + reg_nr = elk_inst_3src_src0_reg_nr(devinfo, inst); + subreg_nr = elk_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4; + type = elk_inst_3src_a16_src_type(devinfo, inst); - if (brw_inst_3src_a16_src0_rep_ctrl(devinfo, inst)) { - _vert_stride = BRW_VERTICAL_STRIDE_0; - _width = BRW_WIDTH_1; - _horiz_stride = BRW_HORIZONTAL_STRIDE_0; + if (elk_inst_3src_a16_src0_rep_ctrl(devinfo, inst)) { + _vert_stride = ELK_VERTICAL_STRIDE_0; + _width = ELK_WIDTH_1; + _horiz_stride = ELK_HORIZONTAL_STRIDE_0; } else { - _vert_stride = BRW_VERTICAL_STRIDE_4; - _width = BRW_WIDTH_4; - _horiz_stride = BRW_HORIZONTAL_STRIDE_1; + _vert_stride = ELK_VERTICAL_STRIDE_4; + _width = ELK_WIDTH_4; + _horiz_stride = ELK_HORIZONTAL_STRIDE_1; } } - is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 && - _width == BRW_WIDTH_1 && - _horiz_stride == BRW_HORIZONTAL_STRIDE_0; + is_scalar_region = _vert_stride == ELK_VERTICAL_STRIDE_0 && + _width == ELK_WIDTH_1 && + _horiz_stride == ELK_HORIZONTAL_STRIDE_0; - subreg_nr /= brw_reg_type_to_size(type); + subreg_nr /= elk_reg_type_to_size(type); err |= control(file, "negate", m_negate, - brw_inst_3src_src0_negate(devinfo, inst), NULL); - err |= control(file, "abs", _abs, brw_inst_3src_src0_abs(devinfo, inst), NULL); + elk_inst_3src_src0_negate(devinfo, inst), NULL); + err |= control(file, "abs", _abs, elk_inst_3src_src0_abs(devinfo, inst), NULL); err |= reg(file, _file, reg_nr); if (err == -1) @@ -1422,72 +1422,72 @@ src0_3src(FILE *file, const struct intel_device_info *devinfo, format(file, ".%d", subreg_nr); src_align1_region(file, _vert_stride, _width, _horiz_stride); if (!is_scalar_region && !is_align1) - err |= src_swizzle(file, brw_inst_3src_a16_src0_swizzle(devinfo, inst)); - string(file, brw_reg_type_to_letters(type)); + err |= src_swizzle(file, elk_inst_3src_a16_src0_swizzle(devinfo, inst)); + string(file, elk_reg_type_to_letters(type)); return err; } static int src1_3src(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { int err = 0; unsigned reg_nr, subreg_nr; - enum brw_reg_file _file; - enum brw_reg_type type; - enum brw_vertical_stride _vert_stride; - enum brw_width _width; - enum brw_horizontal_stride _horiz_stride; + enum elk_reg_file _file; + enum elk_reg_type type; + enum elk_vertical_stride _vert_stride; + enum elk_width _width; + enum elk_horizontal_stride _horiz_stride; bool is_scalar_region; - bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; + bool is_align1 = elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1; if (devinfo->ver < 10 && is_align1) return 0; if (is_align1) { if (devinfo->ver >= 12) { - _file = brw_inst_3src_a1_src1_reg_file(devinfo, inst); - } else if (brw_inst_3src_a1_src1_reg_file(devinfo, inst) == - BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) { - _file = BRW_GENERAL_REGISTER_FILE; + _file = elk_inst_3src_a1_src1_reg_file(devinfo, inst); + } else if (elk_inst_3src_a1_src1_reg_file(devinfo, inst) == + ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE) { + _file = ELK_GENERAL_REGISTER_FILE; } else { - _file = BRW_ARCHITECTURE_REGISTER_FILE; + _file = ELK_ARCHITECTURE_REGISTER_FILE; } - reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst); - subreg_nr = brw_inst_3src_a1_src1_subreg_nr(devinfo, inst); - type = brw_inst_3src_a1_src1_type(devinfo, inst); + reg_nr = elk_inst_3src_src1_reg_nr(devinfo, inst); + subreg_nr = elk_inst_3src_a1_src1_subreg_nr(devinfo, inst); + type = elk_inst_3src_a1_src1_type(devinfo, inst); _vert_stride = vstride_from_align1_3src_vstride( - devinfo, brw_inst_3src_a1_src1_vstride(devinfo, inst)); + devinfo, elk_inst_3src_a1_src1_vstride(devinfo, inst)); _horiz_stride = hstride_from_align1_3src_hstride( - brw_inst_3src_a1_src1_hstride(devinfo, inst)); + elk_inst_3src_a1_src1_hstride(devinfo, inst)); _width = implied_width(_vert_stride, _horiz_stride); } else { - _file = BRW_GENERAL_REGISTER_FILE; - reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst); - subreg_nr = brw_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4; - type = brw_inst_3src_a16_src_type(devinfo, inst); + _file = ELK_GENERAL_REGISTER_FILE; + reg_nr = elk_inst_3src_src1_reg_nr(devinfo, inst); + subreg_nr = elk_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4; + type = elk_inst_3src_a16_src_type(devinfo, inst); - if (brw_inst_3src_a16_src1_rep_ctrl(devinfo, inst)) { - _vert_stride = BRW_VERTICAL_STRIDE_0; - _width = BRW_WIDTH_1; - _horiz_stride = BRW_HORIZONTAL_STRIDE_0; + if (elk_inst_3src_a16_src1_rep_ctrl(devinfo, inst)) { + _vert_stride = ELK_VERTICAL_STRIDE_0; + _width = ELK_WIDTH_1; + _horiz_stride = ELK_HORIZONTAL_STRIDE_0; } else { - _vert_stride = BRW_VERTICAL_STRIDE_4; - _width = BRW_WIDTH_4; - _horiz_stride = BRW_HORIZONTAL_STRIDE_1; + _vert_stride = ELK_VERTICAL_STRIDE_4; + _width = ELK_WIDTH_4; + _horiz_stride = ELK_HORIZONTAL_STRIDE_1; } } - is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 && - _width == BRW_WIDTH_1 && - _horiz_stride == BRW_HORIZONTAL_STRIDE_0; + is_scalar_region = _vert_stride == ELK_VERTICAL_STRIDE_0 && + _width == ELK_WIDTH_1 && + _horiz_stride == ELK_HORIZONTAL_STRIDE_0; - subreg_nr /= brw_reg_type_to_size(type); + subreg_nr /= elk_reg_type_to_size(type); err |= control(file, "negate", m_negate, - brw_inst_3src_src1_negate(devinfo, inst), NULL); - err |= control(file, "abs", _abs, brw_inst_3src_src1_abs(devinfo, inst), NULL); + elk_inst_3src_src1_negate(devinfo, inst), NULL); + err |= control(file, "abs", _abs, elk_inst_3src_src1_abs(devinfo, inst), NULL); err |= reg(file, _file, reg_nr); if (err == -1) @@ -1496,86 +1496,86 @@ src1_3src(FILE *file, const struct intel_device_info *devinfo, format(file, ".%d", subreg_nr); src_align1_region(file, _vert_stride, _width, _horiz_stride); if (!is_scalar_region && !is_align1) - err |= src_swizzle(file, brw_inst_3src_a16_src1_swizzle(devinfo, inst)); - string(file, brw_reg_type_to_letters(type)); + err |= src_swizzle(file, elk_inst_3src_a16_src1_swizzle(devinfo, inst)); + string(file, elk_reg_type_to_letters(type)); return err; } static int src2_3src(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { int err = 0; unsigned reg_nr, subreg_nr; - enum brw_reg_file _file; - enum brw_reg_type type; - enum brw_vertical_stride _vert_stride; - enum brw_width _width; - enum brw_horizontal_stride _horiz_stride; + enum elk_reg_file _file; + enum elk_reg_type type; + enum elk_vertical_stride _vert_stride; + enum elk_width _width; + enum elk_horizontal_stride _horiz_stride; bool is_scalar_region; - bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; + bool is_align1 = elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1; if (devinfo->ver < 10 && is_align1) return 0; if (is_align1) { - if (devinfo->ver >= 12 && !brw_inst_3src_a1_src2_is_imm(devinfo, inst)) { - _file = brw_inst_3src_a1_src2_reg_file(devinfo, inst); - } else if (brw_inst_3src_a1_src2_reg_file(devinfo, inst) == - BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) { - _file = BRW_GENERAL_REGISTER_FILE; + if (devinfo->ver >= 12 && !elk_inst_3src_a1_src2_is_imm(devinfo, inst)) { + _file = elk_inst_3src_a1_src2_reg_file(devinfo, inst); + } else if (elk_inst_3src_a1_src2_reg_file(devinfo, inst) == + ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE) { + _file = ELK_GENERAL_REGISTER_FILE; } else { - _file = BRW_IMMEDIATE_VALUE; - uint16_t imm_val = brw_inst_3src_a1_src2_imm(devinfo, inst); - enum brw_reg_type type = brw_inst_3src_a1_src2_type(devinfo, inst); + _file = ELK_IMMEDIATE_VALUE; + uint16_t imm_val = elk_inst_3src_a1_src2_imm(devinfo, inst); + enum elk_reg_type type = elk_inst_3src_a1_src2_type(devinfo, inst); - if (type == BRW_REGISTER_TYPE_W) { + if (type == ELK_REGISTER_TYPE_W) { format(file, "%dW", imm_val); - } else if (type == BRW_REGISTER_TYPE_UW) { + } else if (type == ELK_REGISTER_TYPE_UW) { format(file, "0x%04xUW", imm_val); - } else if (type == BRW_REGISTER_TYPE_HF) { + } else if (type == ELK_REGISTER_TYPE_HF) { format(file, "0x%04xHF", imm_val); } return 0; } - reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst); - subreg_nr = brw_inst_3src_a1_src2_subreg_nr(devinfo, inst); - type = brw_inst_3src_a1_src2_type(devinfo, inst); + reg_nr = elk_inst_3src_src2_reg_nr(devinfo, inst); + subreg_nr = elk_inst_3src_a1_src2_subreg_nr(devinfo, inst); + type = elk_inst_3src_a1_src2_type(devinfo, inst); /* FINISHME: No vertical stride on src2. Is using the hstride in place * correct? Doesn't seem like it, since there's hstride=1 but * no vstride=1. */ _vert_stride = vstride_from_align1_3src_hstride( - brw_inst_3src_a1_src2_hstride(devinfo, inst)); + elk_inst_3src_a1_src2_hstride(devinfo, inst)); _horiz_stride = hstride_from_align1_3src_hstride( - brw_inst_3src_a1_src2_hstride(devinfo, inst)); + elk_inst_3src_a1_src2_hstride(devinfo, inst)); _width = implied_width(_vert_stride, _horiz_stride); } else { - _file = BRW_GENERAL_REGISTER_FILE; - reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst); - subreg_nr = brw_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4; - type = brw_inst_3src_a16_src_type(devinfo, inst); + _file = ELK_GENERAL_REGISTER_FILE; + reg_nr = elk_inst_3src_src2_reg_nr(devinfo, inst); + subreg_nr = elk_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4; + type = elk_inst_3src_a16_src_type(devinfo, inst); - if (brw_inst_3src_a16_src2_rep_ctrl(devinfo, inst)) { - _vert_stride = BRW_VERTICAL_STRIDE_0; - _width = BRW_WIDTH_1; - _horiz_stride = BRW_HORIZONTAL_STRIDE_0; + if (elk_inst_3src_a16_src2_rep_ctrl(devinfo, inst)) { + _vert_stride = ELK_VERTICAL_STRIDE_0; + _width = ELK_WIDTH_1; + _horiz_stride = ELK_HORIZONTAL_STRIDE_0; } else { - _vert_stride = BRW_VERTICAL_STRIDE_4; - _width = BRW_WIDTH_4; - _horiz_stride = BRW_HORIZONTAL_STRIDE_1; + _vert_stride = ELK_VERTICAL_STRIDE_4; + _width = ELK_WIDTH_4; + _horiz_stride = ELK_HORIZONTAL_STRIDE_1; } } - is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 && - _width == BRW_WIDTH_1 && - _horiz_stride == BRW_HORIZONTAL_STRIDE_0; + is_scalar_region = _vert_stride == ELK_VERTICAL_STRIDE_0 && + _width == ELK_WIDTH_1 && + _horiz_stride == ELK_HORIZONTAL_STRIDE_0; - subreg_nr /= brw_reg_type_to_size(type); + subreg_nr /= elk_reg_type_to_size(type); err |= control(file, "negate", m_negate, - brw_inst_3src_src2_negate(devinfo, inst), NULL); - err |= control(file, "abs", _abs, brw_inst_3src_src2_abs(devinfo, inst), NULL); + elk_inst_3src_src2_negate(devinfo, inst), NULL); + err |= control(file, "abs", _abs, elk_inst_3src_src2_abs(devinfo, inst), NULL); err |= reg(file, _file, reg_nr); if (err == -1) @@ -1584,143 +1584,143 @@ src2_3src(FILE *file, const struct intel_device_info *devinfo, format(file, ".%d", subreg_nr); src_align1_region(file, _vert_stride, _width, _horiz_stride); if (!is_scalar_region && !is_align1) - err |= src_swizzle(file, brw_inst_3src_a16_src2_swizzle(devinfo, inst)); - string(file, brw_reg_type_to_letters(type)); + err |= src_swizzle(file, elk_inst_3src_a16_src2_swizzle(devinfo, inst)); + string(file, elk_reg_type_to_letters(type)); return err; } static int src0_dpas_3src(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { - uint32_t reg_file = brw_inst_dpas_3src_src0_reg_file(devinfo, inst); + uint32_t reg_file = elk_inst_dpas_3src_src0_reg_file(devinfo, inst); - if (reg(file, reg_file, brw_inst_dpas_3src_src0_reg_nr(devinfo, inst)) == -1) + if (reg(file, reg_file, elk_inst_dpas_3src_src0_reg_nr(devinfo, inst)) == -1) return 0; - unsigned subreg_nr = brw_inst_dpas_3src_src0_subreg_nr(devinfo, inst); - enum brw_reg_type type = brw_inst_dpas_3src_src0_type(devinfo, inst); + unsigned subreg_nr = elk_inst_dpas_3src_src0_subreg_nr(devinfo, inst); + enum elk_reg_type type = elk_inst_dpas_3src_src0_type(devinfo, inst); if (subreg_nr) format(file, ".%d", subreg_nr); src_align1_region(file, 1, 1, 0); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return 0; } static int src1_dpas_3src(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { - uint32_t reg_file = brw_inst_dpas_3src_src1_reg_file(devinfo, inst); + uint32_t reg_file = elk_inst_dpas_3src_src1_reg_file(devinfo, inst); - if (reg(file, reg_file, brw_inst_dpas_3src_src1_reg_nr(devinfo, inst)) == -1) + if (reg(file, reg_file, elk_inst_dpas_3src_src1_reg_nr(devinfo, inst)) == -1) return 0; - unsigned subreg_nr = brw_inst_dpas_3src_src1_subreg_nr(devinfo, inst); - enum brw_reg_type type = brw_inst_dpas_3src_src1_type(devinfo, inst); + unsigned subreg_nr = elk_inst_dpas_3src_src1_subreg_nr(devinfo, inst); + enum elk_reg_type type = elk_inst_dpas_3src_src1_type(devinfo, inst); if (subreg_nr) format(file, ".%d", subreg_nr); src_align1_region(file, 1, 1, 0); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return 0; } static int src2_dpas_3src(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { - uint32_t reg_file = brw_inst_dpas_3src_src2_reg_file(devinfo, inst); + uint32_t reg_file = elk_inst_dpas_3src_src2_reg_file(devinfo, inst); - if (reg(file, reg_file, brw_inst_dpas_3src_src2_reg_nr(devinfo, inst)) == -1) + if (reg(file, reg_file, elk_inst_dpas_3src_src2_reg_nr(devinfo, inst)) == -1) return 0; - unsigned subreg_nr = brw_inst_dpas_3src_src2_subreg_nr(devinfo, inst); - enum brw_reg_type type = brw_inst_dpas_3src_src2_type(devinfo, inst); + unsigned subreg_nr = elk_inst_dpas_3src_src2_subreg_nr(devinfo, inst); + enum elk_reg_type type = elk_inst_dpas_3src_src2_type(devinfo, inst); if (subreg_nr) format(file, ".%d", subreg_nr); src_align1_region(file, 1, 1, 0); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return 0; } static int -imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type, - const brw_inst *inst) +imm(FILE *file, const struct elk_isa_info *isa, enum elk_reg_type type, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; switch (type) { - case BRW_REGISTER_TYPE_UQ: - format(file, "0x%016"PRIx64"UQ", brw_inst_imm_uq(devinfo, inst)); + case ELK_REGISTER_TYPE_UQ: + format(file, "0x%016"PRIx64"UQ", elk_inst_imm_uq(devinfo, inst)); break; - case BRW_REGISTER_TYPE_Q: - format(file, "0x%016"PRIx64"Q", brw_inst_imm_uq(devinfo, inst)); + case ELK_REGISTER_TYPE_Q: + format(file, "0x%016"PRIx64"Q", elk_inst_imm_uq(devinfo, inst)); break; - case BRW_REGISTER_TYPE_UD: - format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst)); + case ELK_REGISTER_TYPE_UD: + format(file, "0x%08xUD", elk_inst_imm_ud(devinfo, inst)); break; - case BRW_REGISTER_TYPE_D: - format(file, "%dD", brw_inst_imm_d(devinfo, inst)); + case ELK_REGISTER_TYPE_D: + format(file, "%dD", elk_inst_imm_d(devinfo, inst)); break; - case BRW_REGISTER_TYPE_UW: - format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(devinfo, inst)); + case ELK_REGISTER_TYPE_UW: + format(file, "0x%04xUW", (uint16_t) elk_inst_imm_ud(devinfo, inst)); break; - case BRW_REGISTER_TYPE_W: - format(file, "%dW", (int16_t) brw_inst_imm_d(devinfo, inst)); + case ELK_REGISTER_TYPE_W: + format(file, "%dW", (int16_t) elk_inst_imm_d(devinfo, inst)); break; - case BRW_REGISTER_TYPE_UV: - format(file, "0x%08xUV", brw_inst_imm_ud(devinfo, inst)); + case ELK_REGISTER_TYPE_UV: + format(file, "0x%08xUV", elk_inst_imm_ud(devinfo, inst)); break; - case BRW_REGISTER_TYPE_VF: - format(file, "0x%"PRIx64"VF", brw_inst_bits(inst, 127, 96)); + case ELK_REGISTER_TYPE_VF: + format(file, "0x%"PRIx64"VF", elk_inst_bits(inst, 127, 96)); pad(file, 48); format(file, "/* [%-gF, %-gF, %-gF, %-gF]VF */", - brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)), - brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8), - brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16), - brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24)); + elk_vf_to_float(elk_inst_imm_ud(devinfo, inst)), + elk_vf_to_float(elk_inst_imm_ud(devinfo, inst) >> 8), + elk_vf_to_float(elk_inst_imm_ud(devinfo, inst) >> 16), + elk_vf_to_float(elk_inst_imm_ud(devinfo, inst) >> 24)); break; - case BRW_REGISTER_TYPE_V: - format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst)); + case ELK_REGISTER_TYPE_V: + format(file, "0x%08xV", elk_inst_imm_ud(devinfo, inst)); break; - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: /* The DIM instruction's src0 uses an F type but contains a * 64-bit immediate */ - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_DIM) { - format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 64)); + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_DIM) { + format(file, "0x%"PRIx64"F", elk_inst_bits(inst, 127, 64)); pad(file, 48); - format(file, "/* %-gF */", brw_inst_imm_df(devinfo, inst)); + format(file, "/* %-gF */", elk_inst_imm_df(devinfo, inst)); } else { - format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96)); + format(file, "0x%"PRIx64"F", elk_inst_bits(inst, 127, 96)); pad(file, 48); - format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst)); + format(file, " /* %-gF */", elk_inst_imm_f(devinfo, inst)); } break; - case BRW_REGISTER_TYPE_DF: - format(file, "0x%016"PRIx64"DF", brw_inst_imm_uq(devinfo, inst)); + case ELK_REGISTER_TYPE_DF: + format(file, "0x%016"PRIx64"DF", elk_inst_imm_uq(devinfo, inst)); pad(file, 48); - format(file, "/* %-gDF */", brw_inst_imm_df(devinfo, inst)); + format(file, "/* %-gDF */", elk_inst_imm_df(devinfo, inst)); break; - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: format(file, "0x%04xHF", - (uint16_t) brw_inst_imm_ud(devinfo, inst)); + (uint16_t) elk_inst_imm_ud(devinfo, inst)); pad(file, 48); format(file, "/* %-gHF */", - _mesa_half_to_float((uint16_t) brw_inst_imm_ud(devinfo, inst))); + _mesa_half_to_float((uint16_t) elk_inst_imm_ud(devinfo, inst))); break; - case BRW_REGISTER_TYPE_NF: - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_B: format(file, "*** invalid immediate type %d ", type); } return 0; @@ -1729,8 +1729,8 @@ imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type, static int src_sends_da(FILE *file, const struct intel_device_info *devinfo, - enum brw_reg_type type, - enum brw_reg_file _reg_file, + enum elk_reg_type type, + enum elk_reg_file _reg_file, unsigned _reg_nr, unsigned _reg_subnr) { @@ -1741,7 +1741,7 @@ src_sends_da(FILE *file, return 0; if (_reg_subnr) format(file, ".1"); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return err; } @@ -1749,7 +1749,7 @@ src_sends_da(FILE *file, static int src_sends_ia(FILE *file, const struct intel_device_info *devinfo, - enum brw_reg_type type, + enum elk_reg_type type, int _addr_imm, unsigned _addr_subreg_nr) { @@ -1759,7 +1759,7 @@ src_sends_ia(FILE *file, if (_addr_imm) format(file, " %d", _addr_imm); string(file, "]"); - string(file, brw_reg_type_to_letters(type)); + string(file, elk_reg_type_to_letters(type)); return 0; } @@ -1778,77 +1778,77 @@ src_send_desc_ia(FILE *file, } static int -src0(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) +src0(FILE *file, const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) { + if (is_split_send(devinfo, elk_inst_opcode(isa, inst))) { if (devinfo->ver >= 12) { return src_sends_da(file, devinfo, - BRW_REGISTER_TYPE_UD, - brw_inst_send_src0_reg_file(devinfo, inst), - brw_inst_src0_da_reg_nr(devinfo, inst), + ELK_REGISTER_TYPE_UD, + elk_inst_send_src0_reg_file(devinfo, inst), + elk_inst_src0_da_reg_nr(devinfo, inst), 0); - } else if (brw_inst_send_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { + } else if (elk_inst_send_src0_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { return src_sends_da(file, devinfo, - BRW_REGISTER_TYPE_UD, - BRW_GENERAL_REGISTER_FILE, - brw_inst_src0_da_reg_nr(devinfo, inst), - brw_inst_src0_da16_subreg_nr(devinfo, inst)); + ELK_REGISTER_TYPE_UD, + ELK_GENERAL_REGISTER_FILE, + elk_inst_src0_da_reg_nr(devinfo, inst), + elk_inst_src0_da16_subreg_nr(devinfo, inst)); } else { return src_sends_ia(file, devinfo, - BRW_REGISTER_TYPE_UD, - brw_inst_send_src0_ia16_addr_imm(devinfo, inst), - brw_inst_src0_ia_subreg_nr(devinfo, inst)); + ELK_REGISTER_TYPE_UD, + elk_inst_send_src0_ia16_addr_imm(devinfo, inst), + elk_inst_src0_ia_subreg_nr(devinfo, inst)); } - } else if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { - return imm(file, isa, brw_inst_src0_type(devinfo, inst), inst); - } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { + } else if (elk_inst_src0_reg_file(devinfo, inst) == ELK_IMMEDIATE_VALUE) { + return imm(file, isa, elk_inst_src0_type(devinfo, inst), inst); + } else if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + if (elk_inst_src0_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { return src_da1(file, devinfo, - brw_inst_opcode(isa, inst), - brw_inst_src0_type(devinfo, inst), - brw_inst_src0_reg_file(devinfo, inst), - brw_inst_src0_vstride(devinfo, inst), - brw_inst_src0_width(devinfo, inst), - brw_inst_src0_hstride(devinfo, inst), - brw_inst_src0_da_reg_nr(devinfo, inst), - brw_inst_src0_da1_subreg_nr(devinfo, inst), - brw_inst_src0_abs(devinfo, inst), - brw_inst_src0_negate(devinfo, inst)); + elk_inst_opcode(isa, inst), + elk_inst_src0_type(devinfo, inst), + elk_inst_src0_reg_file(devinfo, inst), + elk_inst_src0_vstride(devinfo, inst), + elk_inst_src0_width(devinfo, inst), + elk_inst_src0_hstride(devinfo, inst), + elk_inst_src0_da_reg_nr(devinfo, inst), + elk_inst_src0_da1_subreg_nr(devinfo, inst), + elk_inst_src0_abs(devinfo, inst), + elk_inst_src0_negate(devinfo, inst)); } else { return src_ia1(file, devinfo, - brw_inst_opcode(isa, inst), - brw_inst_src0_type(devinfo, inst), - brw_inst_src0_ia1_addr_imm(devinfo, inst), - brw_inst_src0_ia_subreg_nr(devinfo, inst), - brw_inst_src0_negate(devinfo, inst), - brw_inst_src0_abs(devinfo, inst), - brw_inst_src0_hstride(devinfo, inst), - brw_inst_src0_width(devinfo, inst), - brw_inst_src0_vstride(devinfo, inst)); + elk_inst_opcode(isa, inst), + elk_inst_src0_type(devinfo, inst), + elk_inst_src0_ia1_addr_imm(devinfo, inst), + elk_inst_src0_ia_subreg_nr(devinfo, inst), + elk_inst_src0_negate(devinfo, inst), + elk_inst_src0_abs(devinfo, inst), + elk_inst_src0_hstride(devinfo, inst), + elk_inst_src0_width(devinfo, inst), + elk_inst_src0_vstride(devinfo, inst)); } } else { - if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { + if (elk_inst_src0_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { return src_da16(file, devinfo, - brw_inst_opcode(isa, inst), - brw_inst_src0_type(devinfo, inst), - brw_inst_src0_reg_file(devinfo, inst), - brw_inst_src0_vstride(devinfo, inst), - brw_inst_src0_da_reg_nr(devinfo, inst), - brw_inst_src0_da16_subreg_nr(devinfo, inst), - brw_inst_src0_abs(devinfo, inst), - brw_inst_src0_negate(devinfo, inst), - brw_inst_src0_da16_swiz_x(devinfo, inst), - brw_inst_src0_da16_swiz_y(devinfo, inst), - brw_inst_src0_da16_swiz_z(devinfo, inst), - brw_inst_src0_da16_swiz_w(devinfo, inst)); + elk_inst_opcode(isa, inst), + elk_inst_src0_type(devinfo, inst), + elk_inst_src0_reg_file(devinfo, inst), + elk_inst_src0_vstride(devinfo, inst), + elk_inst_src0_da_reg_nr(devinfo, inst), + elk_inst_src0_da16_subreg_nr(devinfo, inst), + elk_inst_src0_abs(devinfo, inst), + elk_inst_src0_negate(devinfo, inst), + elk_inst_src0_da16_swiz_x(devinfo, inst), + elk_inst_src0_da16_swiz_y(devinfo, inst), + elk_inst_src0_da16_swiz_z(devinfo, inst), + elk_inst_src0_da16_swiz_w(devinfo, inst)); } else { string(file, "Indirect align16 address mode not supported"); return 1; @@ -1857,62 +1857,62 @@ src0(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) } static int -src1(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) +src1(FILE *file, const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) { + if (is_split_send(devinfo, elk_inst_opcode(isa, inst))) { return src_sends_da(file, devinfo, - BRW_REGISTER_TYPE_UD, - brw_inst_send_src1_reg_file(devinfo, inst), - brw_inst_send_src1_reg_nr(devinfo, inst), + ELK_REGISTER_TYPE_UD, + elk_inst_send_src1_reg_file(devinfo, inst), + elk_inst_send_src1_reg_nr(devinfo, inst), 0 /* subreg_nr */); - } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { - return imm(file, isa, brw_inst_src1_type(devinfo, inst), inst); - } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { + } else if (elk_inst_src1_reg_file(devinfo, inst) == ELK_IMMEDIATE_VALUE) { + return imm(file, isa, elk_inst_src1_type(devinfo, inst), inst); + } else if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + if (elk_inst_src1_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { return src_da1(file, devinfo, - brw_inst_opcode(isa, inst), - brw_inst_src1_type(devinfo, inst), - brw_inst_src1_reg_file(devinfo, inst), - brw_inst_src1_vstride(devinfo, inst), - brw_inst_src1_width(devinfo, inst), - brw_inst_src1_hstride(devinfo, inst), - brw_inst_src1_da_reg_nr(devinfo, inst), - brw_inst_src1_da1_subreg_nr(devinfo, inst), - brw_inst_src1_abs(devinfo, inst), - brw_inst_src1_negate(devinfo, inst)); + elk_inst_opcode(isa, inst), + elk_inst_src1_type(devinfo, inst), + elk_inst_src1_reg_file(devinfo, inst), + elk_inst_src1_vstride(devinfo, inst), + elk_inst_src1_width(devinfo, inst), + elk_inst_src1_hstride(devinfo, inst), + elk_inst_src1_da_reg_nr(devinfo, inst), + elk_inst_src1_da1_subreg_nr(devinfo, inst), + elk_inst_src1_abs(devinfo, inst), + elk_inst_src1_negate(devinfo, inst)); } else { return src_ia1(file, devinfo, - brw_inst_opcode(isa, inst), - brw_inst_src1_type(devinfo, inst), - brw_inst_src1_ia1_addr_imm(devinfo, inst), - brw_inst_src1_ia_subreg_nr(devinfo, inst), - brw_inst_src1_negate(devinfo, inst), - brw_inst_src1_abs(devinfo, inst), - brw_inst_src1_hstride(devinfo, inst), - brw_inst_src1_width(devinfo, inst), - brw_inst_src1_vstride(devinfo, inst)); + elk_inst_opcode(isa, inst), + elk_inst_src1_type(devinfo, inst), + elk_inst_src1_ia1_addr_imm(devinfo, inst), + elk_inst_src1_ia_subreg_nr(devinfo, inst), + elk_inst_src1_negate(devinfo, inst), + elk_inst_src1_abs(devinfo, inst), + elk_inst_src1_hstride(devinfo, inst), + elk_inst_src1_width(devinfo, inst), + elk_inst_src1_vstride(devinfo, inst)); } } else { - if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { + if (elk_inst_src1_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { return src_da16(file, devinfo, - brw_inst_opcode(isa, inst), - brw_inst_src1_type(devinfo, inst), - brw_inst_src1_reg_file(devinfo, inst), - brw_inst_src1_vstride(devinfo, inst), - brw_inst_src1_da_reg_nr(devinfo, inst), - brw_inst_src1_da16_subreg_nr(devinfo, inst), - brw_inst_src1_abs(devinfo, inst), - brw_inst_src1_negate(devinfo, inst), - brw_inst_src1_da16_swiz_x(devinfo, inst), - brw_inst_src1_da16_swiz_y(devinfo, inst), - brw_inst_src1_da16_swiz_z(devinfo, inst), - brw_inst_src1_da16_swiz_w(devinfo, inst)); + elk_inst_opcode(isa, inst), + elk_inst_src1_type(devinfo, inst), + elk_inst_src1_reg_file(devinfo, inst), + elk_inst_src1_vstride(devinfo, inst), + elk_inst_src1_da_reg_nr(devinfo, inst), + elk_inst_src1_da16_subreg_nr(devinfo, inst), + elk_inst_src1_abs(devinfo, inst), + elk_inst_src1_negate(devinfo, inst), + elk_inst_src1_da16_swiz_x(devinfo, inst), + elk_inst_src1_da16_swiz_y(devinfo, inst), + elk_inst_src1_da16_swiz_z(devinfo, inst), + elk_inst_src1_da16_swiz_w(devinfo, inst)); } else { string(file, "Indirect align16 address mode not supported"); return 1; @@ -1922,12 +1922,12 @@ src1(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) static int qtr_ctrl(FILE *file, const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { - int qtr_ctl = brw_inst_qtr_control(devinfo, inst); - int exec_size = 1 << brw_inst_exec_size(devinfo, inst); + int qtr_ctl = elk_inst_qtr_control(devinfo, inst); + int exec_size = 1 << elk_inst_exec_size(devinfo, inst); const unsigned nib_ctl = devinfo->ver < 7 || devinfo->ver >= 20 ? 0 : - brw_inst_nib_control(devinfo, inst); + elk_inst_nib_control(devinfo, inst); if (exec_size < 8 || nib_ctl) { format(file, " %dN", qtr_ctl * 2 + nib_ctl + 1); @@ -1956,42 +1956,42 @@ qtr_ctrl(FILE *file, const struct intel_device_info *devinfo, } static bool -inst_has_type(const struct brw_isa_info *isa, - const brw_inst *inst, - enum brw_reg_type type) +inst_has_type(const struct elk_isa_info *isa, + const elk_inst *inst, + enum elk_reg_type type) { const struct intel_device_info *devinfo = isa->devinfo; - const unsigned num_sources = brw_num_sources_from_inst(isa, inst); + const unsigned num_sources = elk_num_sources_from_inst(isa, inst); - if (brw_inst_dst_type(devinfo, inst) == type) + if (elk_inst_dst_type(devinfo, inst) == type) return true; if (num_sources >= 3) { - if (brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1) - return brw_inst_3src_a1_src0_type(devinfo, inst) == type || - brw_inst_3src_a1_src1_type(devinfo, inst) == type || - brw_inst_3src_a1_src2_type(devinfo, inst) == type; + if (elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1) + return elk_inst_3src_a1_src0_type(devinfo, inst) == type || + elk_inst_3src_a1_src1_type(devinfo, inst) == type || + elk_inst_3src_a1_src2_type(devinfo, inst) == type; else - return brw_inst_3src_a16_src_type(devinfo, inst) == type; + return elk_inst_3src_a16_src_type(devinfo, inst) == type; } else if (num_sources == 2) { - return brw_inst_src0_type(devinfo, inst) == type || - brw_inst_src1_type(devinfo, inst) == type; + return elk_inst_src0_type(devinfo, inst) == type || + elk_inst_src1_type(devinfo, inst) == type; } else { - return brw_inst_src0_type(devinfo, inst) == type; + return elk_inst_src0_type(devinfo, inst) == type; } } static int -swsb(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) +swsb(FILE *file, const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - const enum opcode opcode = brw_inst_opcode(isa, inst); - const uint32_t x = brw_inst_swsb(devinfo, inst); + const enum elk_opcode opcode = elk_inst_opcode(isa, inst); + const uint32_t x = elk_inst_swsb(devinfo, inst); const bool is_unordered = - opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC || - opcode == BRW_OPCODE_MATH || opcode == BRW_OPCODE_DPAS || + opcode == ELK_OPCODE_SEND || opcode == ELK_OPCODE_SENDC || + opcode == ELK_OPCODE_MATH || opcode == ELK_OPCODE_DPAS || (devinfo->has_64bit_float_via_math_pipe && - inst_has_type(isa, inst, BRW_REGISTER_TYPE_DF)); + inst_has_type(isa, inst, ELK_REGISTER_TYPE_DF)); const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, is_unordered, x); if (swsb.regdist) format(file, " %s@%d", @@ -2009,25 +2009,25 @@ swsb(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst) #ifdef DEBUG static __attribute__((__unused__)) int -brw_disassemble_imm(const struct brw_isa_info *isa, +elk_disassemble_imm(const struct elk_isa_info *isa, uint32_t dw3, uint32_t dw2, uint32_t dw1, uint32_t dw0) { - brw_inst inst; + elk_inst inst; inst.data[0] = (((uint64_t) dw1) << 32) | ((uint64_t) dw0); inst.data[1] = (((uint64_t) dw3) << 32) | ((uint64_t) dw2); - return brw_disassemble_inst(stderr, isa, &inst, false, 0, NULL); + return elk_disassemble_inst(stderr, isa, &inst, false, 0, NULL); } #endif static void write_label(FILE *file, const struct intel_device_info *devinfo, - const struct brw_label *root_label, + const struct elk_label *root_label, int offset, int jump) { if (root_label != NULL) { - int to_bytes_scale = sizeof(brw_inst) / brw_jump_scale(devinfo); - const struct brw_label *label = - brw_find_label(root_label, offset + jump * to_bytes_scale); + int to_bytes_scale = sizeof(elk_inst) / elk_jump_scale(devinfo); + const struct elk_label *label = + elk_find_label(root_label, offset + jump * to_bytes_scale); if (label != NULL) { format(file, " LABEL%d", label->number); } @@ -2064,7 +2064,7 @@ lsc_disassemble_ex_desc(const struct intel_device_info *devinfo, } static inline bool -brw_sfid_is_lsc(unsigned sfid) +elk_sfid_is_lsc(unsigned sfid) { switch (sfid) { case GFX12_SFID_UGM: @@ -2079,34 +2079,34 @@ brw_sfid_is_lsc(unsigned sfid) } int -brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, - const brw_inst *inst, bool is_compacted, - int offset, const struct brw_label *root_label) +elk_disassemble_inst(FILE *file, const struct elk_isa_info *isa, + const elk_inst *inst, bool is_compacted, + int offset, const struct elk_label *root_label) { const struct intel_device_info *devinfo = isa->devinfo; int err = 0; int space = 0; - const enum opcode opcode = brw_inst_opcode(isa, inst); - const struct opcode_desc *desc = brw_opcode_desc(isa, opcode); + const enum elk_opcode opcode = elk_inst_opcode(isa, inst); + const struct elk_opcode_desc *desc = elk_opcode_desc(isa, opcode); - if (brw_inst_pred_control(devinfo, inst)) { + if (elk_inst_pred_control(devinfo, inst)) { string(file, "("); err |= control(file, "predicate inverse", pred_inv, - brw_inst_pred_inv(devinfo, inst), NULL); + elk_inst_pred_inv(devinfo, inst), NULL); format(file, "f%"PRIu64".%"PRIu64, - devinfo->ver >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0, - brw_inst_flag_subreg_nr(devinfo, inst)); + devinfo->ver >= 7 ? elk_inst_flag_reg_nr(devinfo, inst) : 0, + elk_inst_flag_subreg_nr(devinfo, inst)); if (devinfo->ver >= 20) { err |= control(file, "predicate control", xe2_pred_ctrl, - brw_inst_pred_control(devinfo, inst), NULL); - } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { + elk_inst_pred_control(devinfo, inst), NULL); + } else if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { err |= control(file, "predicate control align1", pred_ctrl_align1, - brw_inst_pred_control(devinfo, inst), NULL); + elk_inst_pred_control(devinfo, inst), NULL); } else { - err |= control(file, "predicate control align16", pred_ctrl_align16, - brw_inst_pred_control(devinfo, inst), NULL); + err |= control(file, "predicate control align16", elk_pred_ctrl_align16, + elk_inst_pred_control(devinfo, inst), NULL); } string(file, ") "); } @@ -2114,103 +2114,103 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, err |= print_opcode(file, isa, opcode); if (!is_send(opcode)) - err |= control(file, "saturate", saturate, brw_inst_saturate(devinfo, inst), + err |= control(file, "saturate", saturate, elk_inst_saturate(devinfo, inst), NULL); err |= control(file, "debug control", debug_ctrl, - brw_inst_debug_control(devinfo, inst), NULL); + elk_inst_debug_control(devinfo, inst), NULL); - if (opcode == BRW_OPCODE_MATH) { + if (opcode == ELK_OPCODE_MATH) { string(file, " "); err |= control(file, "function", math_function, - brw_inst_math_function(devinfo, inst), NULL); + elk_inst_math_function(devinfo, inst), NULL); - } else if (opcode == BRW_OPCODE_SYNC) { + } else if (opcode == ELK_OPCODE_SYNC) { string(file, " "); err |= control(file, "function", sync_function, - brw_inst_cond_modifier(devinfo, inst), NULL); + elk_inst_cond_modifier(devinfo, inst), NULL); - } else if (opcode == BRW_OPCODE_DPAS) { + } else if (opcode == ELK_OPCODE_DPAS) { string(file, "."); err |= control(file, "systolic depth", dpas_systolic_depth, - brw_inst_dpas_3src_sdepth(devinfo, inst), NULL); + elk_inst_dpas_3src_sdepth(devinfo, inst), NULL); - const unsigned rcount = brw_inst_dpas_3src_rcount(devinfo, inst) + 1; + const unsigned rcount = elk_inst_dpas_3src_rcount(devinfo, inst) + 1; format(file, "x%d", rcount); } else if (!is_send(opcode) && (devinfo->ver < 12 || - brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE || - type_sz(brw_inst_src0_type(devinfo, inst)) < 8)) { - err |= control(file, "conditional modifier", conditional_modifier, - brw_inst_cond_modifier(devinfo, inst), NULL); + elk_inst_src0_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE || + type_sz(elk_inst_src0_type(devinfo, inst)) < 8)) { + err |= control(file, "conditional modifier", elk_conditional_modifier, + elk_inst_cond_modifier(devinfo, inst), NULL); /* If we're using the conditional modifier, print which flags reg is * used for it. Note that on gfx6+, the embedded-condition SEL and * control flow doesn't update flags. */ - if (brw_inst_cond_modifier(devinfo, inst) && - (devinfo->ver < 6 || (opcode != BRW_OPCODE_SEL && - opcode != BRW_OPCODE_CSEL && - opcode != BRW_OPCODE_IF && - opcode != BRW_OPCODE_WHILE))) { + if (elk_inst_cond_modifier(devinfo, inst) && + (devinfo->ver < 6 || (opcode != ELK_OPCODE_SEL && + opcode != ELK_OPCODE_CSEL && + opcode != ELK_OPCODE_IF && + opcode != ELK_OPCODE_WHILE))) { format(file, ".f%"PRIu64".%"PRIu64, - devinfo->ver >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0, - brw_inst_flag_subreg_nr(devinfo, inst)); + devinfo->ver >= 7 ? elk_inst_flag_reg_nr(devinfo, inst) : 0, + elk_inst_flag_subreg_nr(devinfo, inst)); } } - if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) { + if (opcode != ELK_OPCODE_NOP && opcode != ELK_OPCODE_NENOP) { string(file, "("); err |= control(file, "execution size", exec_size, - brw_inst_exec_size(devinfo, inst), NULL); + elk_inst_exec_size(devinfo, inst), NULL); string(file, ")"); } - if (opcode == BRW_OPCODE_SEND && devinfo->ver < 6) - format(file, " %"PRIu64, brw_inst_base_mrf(devinfo, inst)); + if (opcode == ELK_OPCODE_SEND && devinfo->ver < 6) + format(file, " %"PRIu64, elk_inst_base_mrf(devinfo, inst)); - if (brw_has_uip(devinfo, opcode)) { + if (elk_has_uip(devinfo, opcode)) { /* Instructions that have UIP also have JIP. */ pad(file, 16); string(file, "JIP: "); - write_label(file, devinfo, root_label, offset, brw_inst_jip(devinfo, inst)); + write_label(file, devinfo, root_label, offset, elk_inst_jip(devinfo, inst)); pad(file, 38); string(file, "UIP: "); - write_label(file, devinfo, root_label, offset, brw_inst_uip(devinfo, inst)); - } else if (brw_has_jip(devinfo, opcode)) { + write_label(file, devinfo, root_label, offset, elk_inst_uip(devinfo, inst)); + } else if (elk_has_jip(devinfo, opcode)) { int jip; if (devinfo->ver >= 7) { - jip = brw_inst_jip(devinfo, inst); + jip = elk_inst_jip(devinfo, inst); } else { - jip = brw_inst_gfx6_jump_count(devinfo, inst); + jip = elk_inst_gfx6_jump_count(devinfo, inst); } pad(file, 16); string(file, "JIP: "); write_label(file, devinfo, root_label, offset, jip); - } else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_BREAK || - opcode == BRW_OPCODE_CONTINUE || - opcode == BRW_OPCODE_ELSE)) { + } else if (devinfo->ver < 6 && (opcode == ELK_OPCODE_BREAK || + opcode == ELK_OPCODE_CONTINUE || + opcode == ELK_OPCODE_ELSE)) { pad(file, 16); - format(file, "Jump: %d", brw_inst_gfx4_jump_count(devinfo, inst)); + format(file, "Jump: %d", elk_inst_gfx4_jump_count(devinfo, inst)); pad(file, 32); - format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst)); - } else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_IF || - opcode == BRW_OPCODE_IFF || - opcode == BRW_OPCODE_HALT || - opcode == BRW_OPCODE_WHILE)) { + format(file, "Pop: %"PRIu64, elk_inst_gfx4_pop_count(devinfo, inst)); + } else if (devinfo->ver < 6 && (opcode == ELK_OPCODE_IF || + opcode == ELK_OPCODE_IFF || + opcode == ELK_OPCODE_HALT || + opcode == ELK_OPCODE_WHILE)) { pad(file, 16); - format(file, "Jump: %d", brw_inst_gfx4_jump_count(devinfo, inst)); - } else if (devinfo->ver < 6 && opcode == BRW_OPCODE_ENDIF) { + format(file, "Jump: %d", elk_inst_gfx4_jump_count(devinfo, inst)); + } else if (devinfo->ver < 6 && opcode == ELK_OPCODE_ENDIF) { pad(file, 16); - format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst)); - } else if (opcode == BRW_OPCODE_JMPI) { + format(file, "Pop: %"PRIu64, elk_inst_gfx4_pop_count(devinfo, inst)); + } else if (opcode == ELK_OPCODE_JMPI) { pad(file, 16); err |= src1(file, isa, inst); - } else if (opcode == BRW_OPCODE_DPAS) { + } else if (opcode == ELK_OPCODE_DPAS) { pad(file, 16); err |= dest_dpas_3src(file, devinfo, inst); @@ -2253,40 +2253,40 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, } if (is_send(opcode)) { - enum brw_message_target sfid = brw_inst_sfid(devinfo, inst); + enum elk_message_target sfid = elk_inst_sfid(devinfo, inst); bool has_imm_desc = false, has_imm_ex_desc = false; uint32_t imm_desc = 0, imm_ex_desc = 0; if (is_split_send(devinfo, opcode)) { pad(file, 64); - if (brw_inst_send_sel_reg32_desc(devinfo, inst)) { + if (elk_inst_send_sel_reg32_desc(devinfo, inst)) { /* show the indirect descriptor source */ err |= src_send_desc_ia(file, devinfo, 0); } else { has_imm_desc = true; - imm_desc = brw_inst_send_desc(devinfo, inst); + imm_desc = elk_inst_send_desc(devinfo, inst); fprintf(file, "0x%08"PRIx32, imm_desc); } pad(file, 80); - if (brw_inst_send_sel_reg32_ex_desc(devinfo, inst)) { + if (elk_inst_send_sel_reg32_ex_desc(devinfo, inst)) { /* show the indirect descriptor source */ err |= src_send_desc_ia(file, devinfo, - brw_inst_send_ex_desc_ia_subreg_nr(devinfo, inst)); + elk_inst_send_ex_desc_ia_subreg_nr(devinfo, inst)); } else { has_imm_ex_desc = true; - imm_ex_desc = brw_inst_sends_ex_desc(devinfo, inst); + imm_ex_desc = elk_inst_sends_ex_desc(devinfo, inst); fprintf(file, "0x%08"PRIx32, imm_ex_desc); } } else { - if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) { + if (elk_inst_src1_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE) { /* show the indirect descriptor source */ pad(file, 48); err |= src1(file, isa, inst); pad(file, 64); } else { has_imm_desc = true; - imm_desc = brw_inst_send_desc(devinfo, inst); + imm_desc = elk_inst_send_desc(devinfo, inst); pad(file, 48); } @@ -2308,55 +2308,55 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, } else { bool unsupported = false; switch (sfid) { - case BRW_SFID_MATH: + case ELK_SFID_MATH: err |= control(file, "math function", math_function, - brw_inst_math_msg_function(devinfo, inst), &space); + elk_inst_math_msg_function(devinfo, inst), &space); err |= control(file, "math saturate", math_saturate, - brw_inst_math_msg_saturate(devinfo, inst), &space); + elk_inst_math_msg_saturate(devinfo, inst), &space); err |= control(file, "math signed", math_signed, - brw_inst_math_msg_signed_int(devinfo, inst), &space); + elk_inst_math_msg_signed_int(devinfo, inst), &space); err |= control(file, "math scalar", math_scalar, - brw_inst_math_msg_data_type(devinfo, inst), &space); + elk_inst_math_msg_data_type(devinfo, inst), &space); err |= control(file, "math precision", math_precision, - brw_inst_math_msg_precision(devinfo, inst), &space); + elk_inst_math_msg_precision(devinfo, inst), &space); break; - case BRW_SFID_SAMPLER: + case ELK_SFID_SAMPLER: if (devinfo->ver >= 20) { err |= control(file, "sampler message", xe2_sampler_msg_type, - brw_sampler_desc_msg_type(devinfo, imm_desc), + elk_sampler_desc_msg_type(devinfo, imm_desc), &space); err |= control(file, "sampler simd mode", xe2_sampler_simd_mode, - brw_sampler_desc_simd_mode(devinfo, imm_desc), + elk_sampler_desc_simd_mode(devinfo, imm_desc), &space); - if (brw_sampler_desc_return_format(devinfo, imm_desc)) { + if (elk_sampler_desc_return_format(devinfo, imm_desc)) { string(file, " HP"); } format(file, " Surface = %u Sampler = %u", - brw_sampler_desc_binding_table_index(devinfo, imm_desc), - brw_sampler_desc_sampler(devinfo, imm_desc)); + elk_sampler_desc_binding_table_index(devinfo, imm_desc), + elk_sampler_desc_sampler(devinfo, imm_desc)); } else if (devinfo->ver >= 5) { err |= control(file, "sampler message", gfx5_sampler_msg_type, - brw_sampler_desc_msg_type(devinfo, imm_desc), + elk_sampler_desc_msg_type(devinfo, imm_desc), &space); err |= control(file, "sampler simd mode", gfx5_sampler_simd_mode, - brw_sampler_desc_simd_mode(devinfo, imm_desc), + elk_sampler_desc_simd_mode(devinfo, imm_desc), &space); if (devinfo->ver >= 8 && - brw_sampler_desc_return_format(devinfo, imm_desc)) { + elk_sampler_desc_return_format(devinfo, imm_desc)) { string(file, " HP"); } format(file, " Surface = %u Sampler = %u", - brw_sampler_desc_binding_table_index(devinfo, imm_desc), - brw_sampler_desc_sampler(devinfo, imm_desc)); + elk_sampler_desc_binding_table_index(devinfo, imm_desc), + elk_sampler_desc_sampler(devinfo, imm_desc)); } else { format(file, " (bti %u, sampler %u, msg_type %u, ", - brw_sampler_desc_binding_table_index(devinfo, imm_desc), - brw_sampler_desc_sampler(devinfo, imm_desc), - brw_sampler_desc_msg_type(devinfo, imm_desc)); + elk_sampler_desc_binding_table_index(devinfo, imm_desc), + elk_sampler_desc_sampler(devinfo, imm_desc), + elk_sampler_desc_msg_type(devinfo, imm_desc)); if (devinfo->verx10 != 45) { err |= control(file, "sampler target format", sampler_target_format, - brw_sampler_desc_return_format(devinfo, imm_desc), + elk_sampler_desc_return_format(devinfo, imm_desc), NULL); } string(file, ")"); @@ -2364,68 +2364,68 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, break; case GFX6_SFID_DATAPORT_SAMPLER_CACHE: case GFX6_SFID_DATAPORT_CONSTANT_CACHE: - /* aka BRW_SFID_DATAPORT_READ on Gfx4-5 */ + /* aka ELK_SFID_DATAPORT_READ on Gfx4-5 */ if (devinfo->ver >= 6) { format(file, " (bti %u, msg_ctrl %u, msg_type %u, write_commit %u)", - brw_dp_desc_binding_table_index(devinfo, imm_desc), - brw_dp_desc_msg_control(devinfo, imm_desc), - brw_dp_desc_msg_type(devinfo, imm_desc), + elk_dp_desc_binding_table_index(devinfo, imm_desc), + elk_dp_desc_msg_control(devinfo, imm_desc), + elk_dp_desc_msg_type(devinfo, imm_desc), devinfo->ver >= 7 ? 0u : - brw_dp_write_desc_write_commit(devinfo, imm_desc)); + elk_dp_write_desc_write_commit(devinfo, imm_desc)); } else { bool is_965 = devinfo->verx10 == 40; err |= control(file, "DP read message type", is_965 ? gfx4_dp_read_port_msg_type : g45_dp_read_port_msg_type, - brw_dp_read_desc_msg_type(devinfo, imm_desc), + elk_dp_read_desc_msg_type(devinfo, imm_desc), &space); format(file, " MsgCtrl = 0x%u", - brw_dp_read_desc_msg_control(devinfo, imm_desc)); + elk_dp_read_desc_msg_control(devinfo, imm_desc)); format(file, " Surface = %u", - brw_dp_desc_binding_table_index(devinfo, imm_desc)); + elk_dp_desc_binding_table_index(devinfo, imm_desc)); } break; case GFX6_SFID_DATAPORT_RENDER_CACHE: { - /* aka BRW_SFID_DATAPORT_WRITE on Gfx4-5 */ - unsigned msg_type = brw_fb_write_desc_msg_type(devinfo, imm_desc); + /* aka ELK_SFID_DATAPORT_WRITE on Gfx4-5 */ + unsigned msg_type = elk_fb_write_desc_msg_type(devinfo, imm_desc); err |= control(file, "DP rc message type", dp_rc_msg_type(devinfo), msg_type, &space); bool is_rt_write = msg_type == (devinfo->ver >= 6 ? GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE - : BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE); + : ELK_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE); if (is_rt_write) { err |= control(file, "RT message type", m_rt_write_subtype, - brw_inst_rt_message_type(devinfo, inst), &space); - if (devinfo->ver >= 6 && brw_inst_rt_slot_group(devinfo, inst)) + elk_inst_rt_message_type(devinfo, inst), &space); + if (devinfo->ver >= 6 && elk_inst_rt_slot_group(devinfo, inst)) string(file, " Hi"); - if (brw_fb_write_desc_last_render_target(devinfo, imm_desc)) + if (elk_fb_write_desc_last_render_target(devinfo, imm_desc)) string(file, " LastRT"); if (devinfo->ver >= 10 && - brw_fb_write_desc_coarse_write(devinfo, imm_desc)) + elk_fb_write_desc_coarse_write(devinfo, imm_desc)) string(file, " CoarseWrite"); if (devinfo->ver < 7 && - brw_fb_write_desc_write_commit(devinfo, imm_desc)) + elk_fb_write_desc_write_commit(devinfo, imm_desc)) string(file, " WriteCommit"); } else { format(file, " MsgCtrl = 0x%u", - brw_fb_write_desc_msg_control(devinfo, imm_desc)); + elk_fb_write_desc_msg_control(devinfo, imm_desc)); } format(file, " Surface = %u", - brw_fb_desc_binding_table_index(devinfo, imm_desc)); + elk_fb_desc_binding_table_index(devinfo, imm_desc)); break; } - case BRW_SFID_URB: { + case ELK_SFID_URB: { if (devinfo->ver >= 20) { format(file, " ("); - const enum lsc_opcode op = lsc_msg_desc_opcode(devinfo, imm_desc); + const enum elk_lsc_opcode op = lsc_msg_desc_opcode(devinfo, imm_desc); err |= control(file, "operation", lsc_operation, op, &space); format(file, ","); @@ -2438,7 +2438,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, lsc_msg_desc_data_size(devinfo, imm_desc), &space); format(file, ","); - if (lsc_opcode_has_cmask(op)) { + if (elk_lsc_opcode_has_cmask(op)) { err |= control(file, "component_mask", lsc_cmask_str, lsc_msg_desc_cmask(devinfo, imm_desc), @@ -2471,14 +2471,14 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, format(file, " dst_len = %u,", lsc_msg_desc_dest_len(devinfo, imm_desc)); format(file, " src0_len = %u,", lsc_msg_desc_src0_len(devinfo, imm_desc)); - format(file, " src1_len = %d", brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc)); + format(file, " src1_len = %d", elk_message_ex_desc_ex_mlen(devinfo, imm_ex_desc)); err |= control(file, "address_type", lsc_addr_surface_type, lsc_msg_desc_addr_type(devinfo, imm_desc), &space); format(file, " )"); } else { - unsigned urb_opcode = brw_inst_urb_opcode(devinfo, inst); + unsigned urb_opcode = elk_inst_urb_opcode(devinfo, inst); - format(file, " offset %"PRIu64, brw_inst_urb_global_offset(devinfo, inst)); + format(file, " offset %"PRIu64, elk_inst_urb_global_offset(devinfo, inst)); space = 1; @@ -2488,39 +2488,39 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, urb_opcode, &space); if (devinfo->ver >= 7 && - brw_inst_urb_per_slot_offset(devinfo, inst)) { + elk_inst_urb_per_slot_offset(devinfo, inst)) { string(file, " per-slot"); } if (urb_opcode == GFX8_URB_OPCODE_SIMD8_WRITE || urb_opcode == GFX8_URB_OPCODE_SIMD8_READ) { - if (brw_inst_urb_channel_mask_present(devinfo, inst)) + if (elk_inst_urb_channel_mask_present(devinfo, inst)) string(file, " masked"); } else if (urb_opcode != GFX125_URB_OPCODE_FENCE) { err |= control(file, "urb swizzle", urb_swizzle, - brw_inst_urb_swizzle_control(devinfo, inst), + elk_inst_urb_swizzle_control(devinfo, inst), &space); } if (devinfo->ver < 7) { err |= control(file, "urb allocate", urb_allocate, - brw_inst_urb_allocate(devinfo, inst), &space); + elk_inst_urb_allocate(devinfo, inst), &space); err |= control(file, "urb used", urb_used, - brw_inst_urb_used(devinfo, inst), &space); + elk_inst_urb_used(devinfo, inst), &space); } if (devinfo->ver < 8) { err |= control(file, "urb complete", urb_complete, - brw_inst_urb_complete(devinfo, inst), &space); + elk_inst_urb_complete(devinfo, inst), &space); } } break; } - case BRW_SFID_THREAD_SPAWNER: + case ELK_SFID_THREAD_SPAWNER: break; - case BRW_SFID_MESSAGE_GATEWAY: + case ELK_SFID_MESSAGE_GATEWAY: format(file, " (%s)", - gfx7_gateway_subfuncid[brw_inst_gateway_subfuncid(devinfo, inst)]); + gfx7_gateway_subfuncid[elk_inst_gateway_subfuncid(devinfo, inst)]); break; case GFX12_SFID_SLM: @@ -2528,7 +2528,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, case GFX12_SFID_UGM: { assert(devinfo->has_lsc); format(file, " ("); - const enum lsc_opcode op = lsc_msg_desc_opcode(devinfo, imm_desc); + const enum elk_lsc_opcode op = lsc_msg_desc_opcode(devinfo, imm_desc); err |= control(file, "operation", lsc_operation, op, &space); format(file, ","); @@ -2556,7 +2556,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, lsc_msg_desc_data_size(devinfo, imm_desc), &space); format(file, ","); - if (lsc_opcode_has_cmask(op)) { + if (elk_lsc_opcode_has_cmask(op)) { err |= control(file, "component_mask", lsc_cmask_str, lsc_msg_desc_cmask(devinfo, imm_desc), @@ -2594,9 +2594,9 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, format(file, " dst_len = %u,", lsc_msg_desc_dest_len(devinfo, imm_desc)); format(file, " src0_len = %u,", lsc_msg_desc_src0_len(devinfo, imm_desc)); - if (!brw_inst_send_sel_reg32_ex_desc(devinfo, inst)) + if (!elk_inst_send_sel_reg32_ex_desc(devinfo, inst)) format(file, " src1_len = %d", - brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc)); + elk_message_ex_desc_ex_mlen(devinfo, imm_ex_desc)); err |= control(file, "address_type", lsc_addr_surface_type, lsc_msg_desc_addr_type(devinfo, imm_desc), &space); @@ -2611,20 +2611,20 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, err |= control(file, "DP DC0 message type", dp_dc0_msg_type_gfx7, - brw_dp_desc_msg_type(devinfo, imm_desc), &space); + elk_dp_desc_msg_type(devinfo, imm_desc), &space); format(file, ", bti %u, ", - brw_dp_desc_binding_table_index(devinfo, imm_desc)); + elk_dp_desc_binding_table_index(devinfo, imm_desc)); - switch (brw_inst_dp_msg_type(devinfo, inst)) { + switch (elk_inst_dp_msg_type(devinfo, inst)) { case GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP: control(file, "atomic op", aop, - brw_dp_desc_msg_control(devinfo, imm_desc) & 0xf, + elk_dp_desc_msg_control(devinfo, imm_desc) & 0xf, &space); break; case GFX7_DATAPORT_DC_OWORD_BLOCK_READ: case GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE: { - unsigned msg_ctrl = brw_dp_desc_msg_control(devinfo, imm_desc); + unsigned msg_ctrl = elk_dp_desc_msg_control(devinfo, imm_desc); assert(dp_oword_block_rw[msg_ctrl & 7]); format(file, "owords = %s, aligned = %d", dp_oword_block_rw[msg_ctrl & 7], (msg_ctrl >> 3) & 3); @@ -2632,7 +2632,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, } default: format(file, "%u", - brw_dp_desc_msg_control(devinfo, imm_desc)); + elk_dp_desc_msg_control(devinfo, imm_desc)); } format(file, ")"); } else { @@ -2645,16 +2645,16 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, format(file, " ("); space = 0; - unsigned msg_ctrl = brw_dp_desc_msg_control(devinfo, imm_desc); + unsigned msg_ctrl = elk_dp_desc_msg_control(devinfo, imm_desc); err |= control(file, "DP DC1 message type", dp_dc1_msg_type_hsw, - brw_dp_desc_msg_type(devinfo, imm_desc), &space); + elk_dp_desc_msg_type(devinfo, imm_desc), &space); format(file, ", Surface = %u, ", - brw_dp_desc_binding_table_index(devinfo, imm_desc)); + elk_dp_desc_binding_table_index(devinfo, imm_desc)); - switch (brw_inst_dp_msg_type(devinfo, inst)) { + switch (elk_inst_dp_msg_type(devinfo, inst)) { case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP: case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP: case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP: @@ -2704,9 +2704,9 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, case GFX7_SFID_PIXEL_INTERPOLATOR: if (devinfo->ver >= 7) { format(file, " (%s, %s, 0x%02"PRIx64")", - brw_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp", - pixel_interpolator_msg_types[brw_inst_pi_message_type(devinfo, inst)], - brw_inst_pi_message_data(devinfo, inst)); + elk_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp", + pixel_interpolator_msg_types[elk_inst_pi_message_type(devinfo, inst)], + elk_inst_pi_message_data(devinfo, inst)); } else { unsupported = true; } @@ -2724,58 +2724,58 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, string(file, " "); } if (devinfo->verx10 >= 125 && - brw_inst_send_sel_reg32_ex_desc(devinfo, inst) && - brw_inst_send_ex_bso(devinfo, inst)) { + elk_inst_send_sel_reg32_ex_desc(devinfo, inst) && + elk_inst_send_ex_bso(devinfo, inst)) { format(file, " src1_len = %u", - (unsigned) brw_inst_send_src1_len(devinfo, inst)); + (unsigned) elk_inst_send_src1_len(devinfo, inst)); format(file, " ex_bso"); } - if (brw_sfid_is_lsc(sfid) || - (sfid == BRW_SFID_URB && devinfo->ver >= 20)) { + if (elk_sfid_is_lsc(sfid) || + (sfid == ELK_SFID_URB && devinfo->ver >= 20)) { lsc_disassemble_ex_desc(devinfo, imm_desc, imm_ex_desc, file); } else { if (has_imm_desc) - format(file, " mlen %u", brw_message_desc_mlen(devinfo, imm_desc)); + format(file, " mlen %u", elk_message_desc_mlen(devinfo, imm_desc)); if (has_imm_ex_desc) { format(file, " ex_mlen %u", - brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc)); + elk_message_ex_desc_ex_mlen(devinfo, imm_ex_desc)); } if (has_imm_desc) - format(file, " rlen %u", brw_message_desc_rlen(devinfo, imm_desc)); + format(file, " rlen %u", elk_message_desc_rlen(devinfo, imm_desc)); } } pad(file, 64); - if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) { + if (opcode != ELK_OPCODE_NOP && opcode != ELK_OPCODE_NENOP) { string(file, "{"); space = 1; err |= control(file, "access mode", access_mode, - brw_inst_access_mode(devinfo, inst), &space); + elk_inst_access_mode(devinfo, inst), &space); if (devinfo->ver >= 6) { err |= control(file, "write enable control", wectrl, - brw_inst_mask_control(devinfo, inst), &space); + elk_inst_mask_control(devinfo, inst), &space); } else { err |= control(file, "mask control", mask_ctrl, - brw_inst_mask_control(devinfo, inst), &space); + elk_inst_mask_control(devinfo, inst), &space); } if (devinfo->ver < 12) { err |= control(file, "dependency control", dep_ctrl, - ((brw_inst_no_dd_check(devinfo, inst) << 1) | - brw_inst_no_dd_clear(devinfo, inst)), &space); + ((elk_inst_no_dd_check(devinfo, inst) << 1) | + elk_inst_no_dd_clear(devinfo, inst)), &space); } if (devinfo->ver >= 6) err |= qtr_ctrl(file, devinfo, inst); else { - if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_COMPRESSED && + if (elk_inst_qtr_control(devinfo, inst) == ELK_COMPRESSION_COMPRESSED && desc && desc->ndst > 0 && - brw_inst_dst_reg_file(devinfo, inst) == BRW_MESSAGE_REGISTER_FILE && - brw_inst_dst_da_reg_nr(devinfo, inst) & BRW_MRF_COMPR4) { + elk_inst_dst_reg_file(devinfo, inst) == ELK_MESSAGE_REGISTER_FILE && + elk_inst_dst_da_reg_nr(devinfo, inst) & ELK_MRF_COMPR4) { format(file, " compr4"); } else { err |= control(file, "compression control", compr_ctrl, - brw_inst_qtr_control(devinfo, inst), &space); + elk_inst_qtr_control(devinfo, inst), &space); } } @@ -2784,19 +2784,19 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space); err |= control(file, "thread control", thread_ctrl, - (devinfo->ver >= 12 ? brw_inst_atomic_control(devinfo, inst) : - brw_inst_thread_control(devinfo, inst)), + (devinfo->ver >= 12 ? elk_inst_atomic_control(devinfo, inst) : + elk_inst_thread_control(devinfo, inst)), &space); if (has_branch_ctrl(devinfo, opcode)) { err |= control(file, "branch ctrl", branch_ctrl, - brw_inst_branch_control(devinfo, inst), &space); + elk_inst_branch_control(devinfo, inst), &space); } else if (devinfo->ver >= 6 && devinfo->ver < 20) { err |= control(file, "acc write control", accwr, - brw_inst_acc_wr_control(devinfo, inst), &space); + elk_inst_acc_wr_control(devinfo, inst), &space); } if (is_send(opcode)) err |= control(file, "end of thread", end_of_thread, - brw_inst_eot(devinfo, inst), &space); + elk_inst_eot(devinfo, inst), &space); if (space) string(file, " "); string(file, "}"); @@ -2807,7 +2807,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, } int -brw_disassemble_find_end(const struct brw_isa_info *isa, +elk_disassemble_find_end(const struct elk_isa_info *isa, const void *assembly, int start) { const struct intel_device_info *devinfo = isa->devinfo; @@ -2815,17 +2815,17 @@ brw_disassemble_find_end(const struct brw_isa_info *isa, /* This loop exits when send-with-EOT or when opcode is 0 */ while (true) { - const brw_inst *insn = assembly + offset; + const elk_inst *insn = assembly + offset; - if (brw_inst_cmpt_control(devinfo, insn)) { + if (elk_inst_cmpt_control(devinfo, insn)) { offset += 8; } else { offset += 16; } /* Simplistic, but efficient way to terminate disasm */ - uint32_t opcode = brw_inst_opcode(isa, insn); - if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo, insn))) { + uint32_t opcode = elk_inst_opcode(isa, insn); + if (opcode == 0 || (is_send(opcode) && elk_inst_eot(devinfo, insn))) { break; } } @@ -2834,26 +2834,26 @@ brw_disassemble_find_end(const struct brw_isa_info *isa, } void -brw_disassemble_with_errors(const struct brw_isa_info *isa, +elk_disassemble_with_errors(const struct elk_isa_info *isa, const void *assembly, int start, FILE *out) { - int end = brw_disassemble_find_end(isa, assembly, start); + int end = elk_disassemble_find_end(isa, assembly, start); - /* Make a dummy disasm structure that brw_validate_instructions + /* Make a dummy disasm structure that elk_validate_instructions * can work from. */ - struct disasm_info *disasm_info = disasm_initialize(isa, NULL); - disasm_new_inst_group(disasm_info, start); - disasm_new_inst_group(disasm_info, end); + struct elk_disasm_info *elk_disasm_info = elk_disasm_initialize(isa, NULL); + elk_disasm_new_inst_group(elk_disasm_info, start); + elk_disasm_new_inst_group(elk_disasm_info, end); - brw_validate_instructions(isa, assembly, start, end, disasm_info); + elk_validate_instructions(isa, assembly, start, end, elk_disasm_info); void *mem_ctx = ralloc_context(NULL); - const struct brw_label *root_label = - brw_label_assembly(isa, assembly, start, end, mem_ctx); + const struct elk_label *root_label = + elk_label_assembly(isa, assembly, start, end, mem_ctx); foreach_list_typed(struct inst_group, group, link, - &disasm_info->group_list) { + &elk_disasm_info->group_list) { struct exec_node *next_node = exec_node_get_next(&group->link); if (exec_node_is_tail_sentinel(next_node)) break; @@ -2864,7 +2864,7 @@ brw_disassemble_with_errors(const struct brw_isa_info *isa, int start_offset = group->offset; int end_offset = next->offset; - brw_disassemble(isa, assembly, start_offset, end_offset, + elk_disassemble(isa, assembly, start_offset, end_offset, root_label, out); if (group->error) { @@ -2873,5 +2873,5 @@ brw_disassemble_with_errors(const struct brw_isa_info *isa, } ralloc_free(mem_ctx); - ralloc_free(disasm_info); + ralloc_free(elk_disasm_info); } diff --git a/src/intel/compiler/elk/elk_disasm.h b/src/intel/compiler/elk/elk_disasm.h index 65f14c97f3c..c88461ed185 100644 --- a/src/intel/compiler/elk/elk_disasm.h +++ b/src/intel/compiler/elk/elk_disasm.h @@ -13,26 +13,26 @@ extern "C" { #endif -struct brw_isa_info; -struct brw_inst; +struct elk_isa_info; +struct elk_inst; -const struct brw_label *brw_find_label(const struct brw_label *root, int offset); -void brw_create_label(struct brw_label **labels, int offset, void *mem_ctx); -int brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, - const struct brw_inst *inst, bool is_compacted, - int offset, const struct brw_label *root_label); +const struct elk_label *elk_find_label(const struct elk_label *root, int offset); +void elk_create_label(struct elk_label **labels, int offset, void *mem_ctx); +int elk_disassemble_inst(FILE *file, const struct elk_isa_info *isa, + const struct elk_inst *inst, bool is_compacted, + int offset, const struct elk_label *root_label); const struct -brw_label *brw_label_assembly(const struct brw_isa_info *isa, +elk_label *elk_label_assembly(const struct elk_isa_info *isa, const void *assembly, int start, int end, void *mem_ctx); -void brw_disassemble_with_labels(const struct brw_isa_info *isa, +void elk_disassemble_with_labels(const struct elk_isa_info *isa, const void *assembly, int start, int end, FILE *out); -void brw_disassemble(const struct brw_isa_info *isa, +void elk_disassemble(const struct elk_isa_info *isa, const void *assembly, int start, int end, - const struct brw_label *root_label, FILE *out); -int brw_disassemble_find_end(const struct brw_isa_info *isa, + const struct elk_label *root_label, FILE *out); +int elk_disassemble_find_end(const struct elk_isa_info *isa, const void *assembly, int start); -void brw_disassemble_with_errors(const struct brw_isa_info *isa, +void elk_disassemble_with_errors(const struct elk_isa_info *isa, const void *assembly, int start, FILE *out); #ifdef __cplusplus diff --git a/src/intel/compiler/elk/elk_disasm_info.c b/src/intel/compiler/elk/elk_disasm_info.c index 9fac62fd238..85d91063153 100644 --- a/src/intel/compiler/elk/elk_disasm_info.c +++ b/src/intel/compiler/elk/elk_disasm_info.c @@ -32,16 +32,16 @@ __attribute__((weak)) void nir_print_instr(UNUSED const nir_instr *instr, UNUSED FILE *fp) {} void -dump_assembly(void *assembly, int start_offset, int end_offset, - struct disasm_info *disasm, const unsigned *block_latency) +elk_dump_assembly(void *assembly, int start_offset, int end_offset, + struct elk_disasm_info *disasm, const unsigned *block_latency) { - const struct brw_isa_info *isa = disasm->isa; + const struct elk_isa_info *isa = disasm->isa; const char *last_annotation_string = NULL; const void *last_annotation_ir = NULL; void *mem_ctx = ralloc_context(NULL); - const struct brw_label *root_label = - brw_label_assembly(isa, assembly, start_offset, end_offset, mem_ctx); + const struct elk_label *root_label = + elk_label_assembly(isa, assembly, start_offset, end_offset, mem_ctx); foreach_list_typed(struct inst_group, group, link, &disasm->group_list) { struct exec_node *next_node = exec_node_get_next(&group->link); @@ -56,9 +56,9 @@ dump_assembly(void *assembly, int start_offset, int end_offset, if (group->block_start) { fprintf(stderr, " START B%d", group->block_start->num); - foreach_list_typed(struct bblock_link, predecessor_link, link, + foreach_list_typed(struct elk_bblock_link, predecessor_link, link, &group->block_start->parents) { - struct bblock_t *predecessor_block = predecessor_link->block; + struct elk_bblock_t *predecessor_block = predecessor_link->block; fprintf(stderr, " <-B%d", predecessor_block->num); } if (block_latency) @@ -82,7 +82,7 @@ dump_assembly(void *assembly, int start_offset, int end_offset, fprintf(stderr, " %s\n", last_annotation_string); } - brw_disassemble(isa, assembly, start_offset, end_offset, + elk_disassemble(isa, assembly, start_offset, end_offset, root_label, stderr); if (group->error) { @@ -91,9 +91,9 @@ dump_assembly(void *assembly, int start_offset, int end_offset, if (group->block_end) { fprintf(stderr, " END B%d", group->block_end->num); - foreach_list_typed(struct bblock_link, successor_link, link, + foreach_list_typed(struct elk_bblock_link, successor_link, link, &group->block_end->children) { - struct bblock_t *successor_block = successor_link->block; + struct elk_bblock_t *successor_block = successor_link->block; fprintf(stderr, " ->B%d", successor_block->num); } fprintf(stderr, "\n"); @@ -104,11 +104,11 @@ dump_assembly(void *assembly, int start_offset, int end_offset, ralloc_free(mem_ctx); } -struct disasm_info * -disasm_initialize(const struct brw_isa_info *isa, - const struct cfg_t *cfg) +struct elk_disasm_info * +elk_disasm_initialize(const struct elk_isa_info *isa, + const struct elk_cfg_t *cfg) { - struct disasm_info *disasm = ralloc(NULL, struct disasm_info); + struct elk_disasm_info *disasm = ralloc(NULL, struct elk_disasm_info); exec_list_make_empty(&disasm->group_list); disasm->isa = isa; disasm->cfg = cfg; @@ -118,7 +118,7 @@ disasm_initialize(const struct brw_isa_info *isa, } struct inst_group * -disasm_new_inst_group(struct disasm_info *disasm, unsigned next_inst_offset) +elk_disasm_new_inst_group(struct elk_disasm_info *disasm, unsigned next_inst_offset) { struct inst_group *tail = rzalloc(disasm, struct inst_group); tail->offset = next_inst_offset; @@ -127,15 +127,15 @@ disasm_new_inst_group(struct disasm_info *disasm, unsigned next_inst_offset) } void -disasm_annotate(struct disasm_info *disasm, - struct backend_instruction *inst, unsigned offset) +elk_disasm_annotate(struct elk_disasm_info *disasm, + struct elk_backend_instruction *inst, unsigned offset) { const struct intel_device_info *devinfo = disasm->isa->devinfo; - const struct cfg_t *cfg = disasm->cfg; + const struct elk_cfg_t *cfg = disasm->cfg; struct inst_group *group; if (!disasm->use_tail) { - group = disasm_new_inst_group(disasm, offset); + group = elk_disasm_new_inst_group(disasm, offset); } else { disasm->use_tail = false; group = exec_node_data(struct inst_group, @@ -159,7 +159,7 @@ disasm_annotate(struct disasm_info *disasm, * There's also only complication from emitting an annotation without * a corresponding hardware instruction to disassemble. */ - if (devinfo->ver >= 6 && inst->opcode == BRW_OPCODE_DO) { + if (devinfo->ver >= 6 && inst->opcode == ELK_OPCODE_DO) { disasm->use_tail = true; } @@ -170,7 +170,7 @@ disasm_annotate(struct disasm_info *disasm, } void -disasm_insert_error(struct disasm_info *disasm, unsigned offset, +elk_disasm_insert_error(struct elk_disasm_info *disasm, unsigned offset, unsigned inst_size, const char *error) { foreach_list_typed(struct inst_group, cur, link, &disasm->group_list) { diff --git a/src/intel/compiler/elk/elk_disasm_info.h b/src/intel/compiler/elk/elk_disasm_info.h index 0693567a780..b4739a0bd2c 100644 --- a/src/intel/compiler/elk/elk_disasm_info.h +++ b/src/intel/compiler/elk/elk_disasm_info.h @@ -30,8 +30,8 @@ extern "C" { #endif -struct cfg_t; -struct backend_instruction; +struct elk_cfg_t; +struct elk_backend_instruction; struct intel_device_info; struct inst_group { @@ -45,19 +45,19 @@ struct inst_group { /* Pointers to the basic block in the CFG if the instruction group starts * or ends a basic block. */ - struct bblock_t *block_start; - struct bblock_t *block_end; + struct elk_bblock_t *block_start; + struct elk_bblock_t *block_end; /* Annotation for the generated IR. One of the two can be set. */ const void *ir; const char *annotation; }; -struct disasm_info { +struct elk_disasm_info { struct exec_list group_list; - const struct brw_isa_info *isa; - const struct cfg_t *cfg; + const struct elk_isa_info *isa; + const struct elk_cfg_t *cfg; /** Block index in the cfg. */ int cur_block; @@ -65,22 +65,22 @@ struct disasm_info { }; void -dump_assembly(void *assembly, int start_offset, int end_offset, - struct disasm_info *disasm, const unsigned *block_latency); +elk_dump_assembly(void *assembly, int start_offset, int end_offset, + struct elk_disasm_info *disasm, const unsigned *block_latency); -struct disasm_info * -disasm_initialize(const struct brw_isa_info *isa, - const struct cfg_t *cfg); +struct elk_disasm_info * +elk_disasm_initialize(const struct elk_isa_info *isa, + const struct elk_cfg_t *cfg); struct inst_group * -disasm_new_inst_group(struct disasm_info *disasm, unsigned offset); +elk_disasm_new_inst_group(struct elk_disasm_info *disasm, unsigned offset); void -disasm_annotate(struct disasm_info *disasm, - struct backend_instruction *inst, unsigned offset); +elk_disasm_annotate(struct elk_disasm_info *disasm, + struct elk_backend_instruction *inst, unsigned offset); void -disasm_insert_error(struct disasm_info *disasm, unsigned offset, +elk_disasm_insert_error(struct elk_disasm_info *disasm, unsigned offset, unsigned inst_size, const char *error); #ifdef __cplusplus diff --git a/src/intel/compiler/elk/elk_disasm_tool.c b/src/intel/compiler/elk/elk_disasm_tool.c index ca60e9c04f5..8ca9ecb065b 100644 --- a/src/intel/compiler/elk/elk_disasm_tool.c +++ b/src/intel/compiler/elk/elk_disasm_tool.c @@ -209,8 +209,8 @@ int main(int argc, char *argv[]) exit(EXIT_FAILURE); } - struct brw_isa_info isa; - brw_init_isa_info(&isa, &devinfo); + struct elk_isa_info isa; + elk_init_isa_info(&isa, &devinfo); if (input_type == OPT_INPUT_BINARY) assembly = i965_disasm_read_binary(fp, &end); @@ -227,7 +227,7 @@ int main(int argc, char *argv[]) } /* Disassemble i965 instructions from buffer assembly */ - brw_disassemble_with_labels(&isa, assembly, start, end, stdout); + elk_disassemble_with_labels(&isa, assembly, start, end, stdout); result = EXIT_SUCCESS; diff --git a/src/intel/compiler/elk/elk_eu.c b/src/intel/compiler/elk/elk_eu.c index 89133e926f5..883a9c1e1e3 100644 --- a/src/intel/compiler/elk/elk_eu.c +++ b/src/intel/compiler/elk/elk_eu.c @@ -43,22 +43,22 @@ #include "util/ralloc.h" /* Returns a conditional modifier that negates the condition. */ -enum brw_conditional_mod -brw_negate_cmod(enum brw_conditional_mod cmod) +enum elk_conditional_mod +elk_negate_cmod(enum elk_conditional_mod cmod) { switch (cmod) { - case BRW_CONDITIONAL_Z: - return BRW_CONDITIONAL_NZ; - case BRW_CONDITIONAL_NZ: - return BRW_CONDITIONAL_Z; - case BRW_CONDITIONAL_G: - return BRW_CONDITIONAL_LE; - case BRW_CONDITIONAL_GE: - return BRW_CONDITIONAL_L; - case BRW_CONDITIONAL_L: - return BRW_CONDITIONAL_GE; - case BRW_CONDITIONAL_LE: - return BRW_CONDITIONAL_G; + case ELK_CONDITIONAL_Z: + return ELK_CONDITIONAL_NZ; + case ELK_CONDITIONAL_NZ: + return ELK_CONDITIONAL_Z; + case ELK_CONDITIONAL_G: + return ELK_CONDITIONAL_LE; + case ELK_CONDITIONAL_GE: + return ELK_CONDITIONAL_L; + case ELK_CONDITIONAL_L: + return ELK_CONDITIONAL_GE; + case ELK_CONDITIONAL_LE: + return ELK_CONDITIONAL_G; default: unreachable("Can't negate this cmod"); } @@ -67,23 +67,23 @@ brw_negate_cmod(enum brw_conditional_mod cmod) /* Returns the corresponding conditional mod for swapping src0 and * src1 in e.g. CMP. */ -enum brw_conditional_mod -brw_swap_cmod(enum brw_conditional_mod cmod) +enum elk_conditional_mod +elk_swap_cmod(enum elk_conditional_mod cmod) { switch (cmod) { - case BRW_CONDITIONAL_Z: - case BRW_CONDITIONAL_NZ: + case ELK_CONDITIONAL_Z: + case ELK_CONDITIONAL_NZ: return cmod; - case BRW_CONDITIONAL_G: - return BRW_CONDITIONAL_L; - case BRW_CONDITIONAL_GE: - return BRW_CONDITIONAL_LE; - case BRW_CONDITIONAL_L: - return BRW_CONDITIONAL_G; - case BRW_CONDITIONAL_LE: - return BRW_CONDITIONAL_GE; + case ELK_CONDITIONAL_G: + return ELK_CONDITIONAL_L; + case ELK_CONDITIONAL_GE: + return ELK_CONDITIONAL_LE; + case ELK_CONDITIONAL_L: + return ELK_CONDITIONAL_G; + case ELK_CONDITIONAL_LE: + return ELK_CONDITIONAL_GE; default: - return BRW_CONDITIONAL_NONE; + return ELK_CONDITIONAL_NONE; } } @@ -94,12 +94,12 @@ brw_swap_cmod(enum brw_conditional_mod cmod) * scalar register types return zero. */ static unsigned -imm_shift(enum brw_reg_type type, unsigned i) +imm_shift(enum elk_reg_type type, unsigned i) { - assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V && + assert(type != ELK_REGISTER_TYPE_UV && type != ELK_REGISTER_TYPE_V && "Not implemented."); - if (type == BRW_REGISTER_TYPE_VF) + if (type == ELK_REGISTER_TYPE_VF) return 8 * (i & 3); else return 0; @@ -110,7 +110,7 @@ imm_shift(enum brw_reg_type type, unsigned i) * permutation specified as \p swz. */ uint32_t -brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz) +elk_swizzle_immediate(enum elk_reg_type type, uint32_t x, unsigned swz) { if (imm_shift(type, 1)) { const unsigned n = 32 / imm_shift(type, 1); @@ -120,7 +120,7 @@ brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz) /* Shift the specified component all the way to the right and left to * discard any undesired L/MSBs, then shift it right into component i. */ - y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3)) + y |= x >> imm_shift(type, (i & ~3) + ELK_GET_SWZ(swz, i & 3)) << imm_shift(type, ~0u) >> imm_shift(type, ~0u - i); } @@ -132,72 +132,72 @@ brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz) } unsigned -brw_get_default_exec_size(struct brw_codegen *p) +elk_get_default_exec_size(struct elk_codegen *p) { return p->current->exec_size; } unsigned -brw_get_default_group(struct brw_codegen *p) +elk_get_default_group(struct elk_codegen *p) { return p->current->group; } unsigned -brw_get_default_access_mode(struct brw_codegen *p) +elk_get_default_access_mode(struct elk_codegen *p) { return p->current->access_mode; } struct tgl_swsb -brw_get_default_swsb(struct brw_codegen *p) +elk_get_default_swsb(struct elk_codegen *p) { return p->current->swsb; } void -brw_set_default_exec_size(struct brw_codegen *p, unsigned value) +elk_set_default_exec_size(struct elk_codegen *p, unsigned value) { p->current->exec_size = value; } -void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc) +void elk_set_default_predicate_control(struct elk_codegen *p, enum elk_predicate pc) { p->current->predicate = pc; } -void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse) +void elk_set_default_predicate_inverse(struct elk_codegen *p, bool predicate_inverse) { p->current->pred_inv = predicate_inverse; } -void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg) +void elk_set_default_flag_reg(struct elk_codegen *p, int reg, int subreg) { assert(subreg < 2); p->current->flag_subreg = reg * 2 + subreg; } -void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode ) +void elk_set_default_access_mode( struct elk_codegen *p, unsigned access_mode ) { p->current->access_mode = access_mode; } void -brw_set_default_compression_control(struct brw_codegen *p, - enum brw_compression compression_control) +elk_set_default_compression_control(struct elk_codegen *p, + enum elk_compression compression_control) { switch (compression_control) { - case BRW_COMPRESSION_NONE: + case ELK_COMPRESSION_NONE: /* This is the "use the first set of bits of dmask/vmask/arf * according to execsize" option. */ p->current->group = 0; break; - case BRW_COMPRESSION_2NDHALF: + case ELK_COMPRESSION_2NDHALF: /* For SIMD8, this is "use the second set of 8 bits." */ p->current->group = 8; break; - case BRW_COMPRESSION_COMPRESSED: + case ELK_COMPRESSION_COMPRESSED: /* For SIMD16 instruction compression, use the first set of 16 bits * since we don't do SIMD32 dispatch. */ @@ -209,7 +209,7 @@ brw_set_default_compression_control(struct brw_codegen *p, if (p->devinfo->ver <= 6) { p->current->compressed = - (compression_control == BRW_COMPRESSION_COMPRESSED); + (compression_control == ELK_COMPRESSION_COMPRESSED); } } @@ -218,8 +218,8 @@ brw_set_default_compression_control(struct brw_codegen *p, * the currently selected channel enable group untouched. */ void -brw_inst_set_compression(const struct intel_device_info *devinfo, - brw_inst *inst, bool on) +elk_inst_set_compression(const struct intel_device_info *devinfo, + elk_inst *inst, bool on) { if (devinfo->ver >= 6) { /* No-op, the EU will figure out for us whether the instruction needs to @@ -232,15 +232,15 @@ brw_inst_set_compression(const struct intel_device_info *devinfo, * channel group inadvertently. */ if (on) - brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED); - else if (brw_inst_qtr_control(devinfo, inst) - == BRW_COMPRESSION_COMPRESSED) - brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE); + elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_COMPRESSED); + else if (elk_inst_qtr_control(devinfo, inst) + == ELK_COMPRESSION_COMPRESSED) + elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_NONE); } } void -brw_set_default_compression(struct brw_codegen *p, bool on) +elk_set_default_compression(struct elk_codegen *p, bool on) { p->current->compressed = on; } @@ -250,21 +250,21 @@ brw_set_default_compression(struct brw_codegen *p, bool on) * [group, group + exec_size) to the instruction passed as argument. */ void -brw_inst_set_group(const struct intel_device_info *devinfo, - brw_inst *inst, unsigned group) +elk_inst_set_group(const struct intel_device_info *devinfo, + elk_inst *inst, unsigned group) { if (devinfo->ver >= 20) { assert(group % 8 == 0 && group < 32); - brw_inst_set_qtr_control(devinfo, inst, group / 8); + elk_inst_set_qtr_control(devinfo, inst, group / 8); } else if (devinfo->ver >= 7) { assert(group % 4 == 0 && group < 32); - brw_inst_set_qtr_control(devinfo, inst, group / 8); - brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2); + elk_inst_set_qtr_control(devinfo, inst, group / 8); + elk_inst_set_nib_control(devinfo, inst, (group / 4) % 2); } else if (devinfo->ver == 6) { assert(group % 8 == 0 && group < 32); - brw_inst_set_qtr_control(devinfo, inst, group / 8); + elk_inst_set_qtr_control(devinfo, inst, group / 8); } else { assert(group % 8 == 0 && group < 16); @@ -274,46 +274,46 @@ brw_inst_set_group(const struct intel_device_info *devinfo, * enable inadvertently. */ if (group == 8) - brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF); - else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF) - brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE); + elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_2NDHALF); + else if (elk_inst_qtr_control(devinfo, inst) == ELK_COMPRESSION_2NDHALF) + elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_NONE); } } void -brw_set_default_group(struct brw_codegen *p, unsigned group) +elk_set_default_group(struct elk_codegen *p, unsigned group) { p->current->group = group; } -void brw_set_default_mask_control( struct brw_codegen *p, unsigned value ) +void elk_set_default_mask_control( struct elk_codegen *p, unsigned value ) { p->current->mask_control = value; } -void brw_set_default_saturate( struct brw_codegen *p, bool enable ) +void elk_set_default_saturate( struct elk_codegen *p, bool enable ) { p->current->saturate = enable; } -void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value) +void elk_set_default_acc_write_control(struct elk_codegen *p, unsigned value) { p->current->acc_wr_control = value; } -void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value) +void elk_set_default_swsb(struct elk_codegen *p, struct tgl_swsb value) { p->current->swsb = value; } -void brw_push_insn_state( struct brw_codegen *p ) +void elk_push_insn_state( struct elk_codegen *p ) { - assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]); + assert(p->current != &p->stack[ELK_EU_MAX_INSN_STACK-1]); *(p->current + 1) = *p->current; p->current++; } -void brw_pop_insn_state( struct brw_codegen *p ) +void elk_pop_insn_state( struct elk_codegen *p ) { assert(p->current != p->stack); p->current--; @@ -323,8 +323,8 @@ void brw_pop_insn_state( struct brw_codegen *p ) /*********************************************************************** */ void -brw_init_codegen(const struct brw_isa_info *isa, - struct brw_codegen *p, void *mem_ctx) +elk_init_codegen(const struct elk_isa_info *isa, + struct elk_codegen *p, void *mem_ctx) { memset(p, 0, sizeof(*p)); @@ -333,11 +333,11 @@ brw_init_codegen(const struct brw_isa_info *isa, p->automatic_exec_sizes = true; /* * Set the initial instruction store array size to 1024, if found that - * isn't enough, then it will double the store size at brw_next_insn() + * isn't enough, then it will double the store size at elk_next_insn() * until out of memory. */ p->store_size = 1024; - p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size); + p->store = rzalloc_array(mem_ctx, elk_inst, p->store_size); p->nr_insn = 0; p->current = p->stack; memset(p->current, 0, sizeof(p->current[0])); @@ -346,10 +346,10 @@ brw_init_codegen(const struct brw_isa_info *isa, /* Some defaults? */ - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */ - brw_set_default_saturate(p, 0); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_set_default_mask_control(p, ELK_MASK_ENABLE); /* what does this do? */ + elk_set_default_saturate(p, 0); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); /* Set up control flow stack */ p->if_stack_depth = 0; @@ -363,15 +363,15 @@ brw_init_codegen(const struct brw_isa_info *isa, } -const unsigned *brw_get_program( struct brw_codegen *p, +const unsigned *elk_get_program( struct elk_codegen *p, unsigned *sz ) { *sz = p->next_insn_offset; return (const unsigned *)p->store; } -const struct brw_shader_reloc * -brw_get_shader_relocs(struct brw_codegen *p, unsigned *num_relocs) +const struct elk_shader_reloc * +elk_get_shader_relocs(struct elk_codegen *p, unsigned *num_relocs) { *num_relocs = p->num_relocs; return p->relocs; @@ -379,12 +379,12 @@ brw_get_shader_relocs(struct brw_codegen *p, unsigned *num_relocs) DEBUG_GET_ONCE_OPTION(shader_bin_dump_path, "INTEL_SHADER_BIN_DUMP_PATH", NULL); -bool brw_should_dump_shader_bin(void) +bool elk_should_dump_shader_bin(void) { return debug_get_option_shader_bin_dump_path() != NULL; } -void brw_dump_shader_bin(void *assembly, int start_offset, int end_offset, +void elk_dump_shader_bin(void *assembly, int start_offset, int end_offset, const char *identifier) { char *name = ralloc_asprintf(NULL, "%s/%s.bin", @@ -421,7 +421,7 @@ void brw_dump_shader_bin(void *assembly, int start_offset, int end_offset, close(fd); } -bool brw_try_override_assembly(struct brw_codegen *p, int start_offset, +bool elk_try_override_assembly(struct elk_codegen *p, int start_offset, const char *identifier) { const char *read_path = getenv("INTEL_SHADER_ASM_READ_PATH"); @@ -444,12 +444,12 @@ bool brw_try_override_assembly(struct brw_codegen *p, int start_offset, return false; } - p->nr_insn -= (p->next_insn_offset - start_offset) / sizeof(brw_inst); - p->nr_insn += sb.st_size / sizeof(brw_inst); + p->nr_insn -= (p->next_insn_offset - start_offset) / sizeof(elk_inst); + p->nr_insn += sb.st_size / sizeof(elk_inst); p->next_insn_offset = start_offset + sb.st_size; - p->store_size = (start_offset + sb.st_size) / sizeof(brw_inst); - p->store = (brw_inst *)reralloc_size(p->mem_ctx, p->store, p->next_insn_offset); + p->store_size = (start_offset + sb.st_size) / sizeof(elk_inst); + p->store = (elk_inst *)reralloc_size(p->mem_ctx, p->store, p->next_insn_offset); assert(p->store); ssize_t ret = read(fd, (char *)p->store + start_offset, sb.st_size); @@ -459,7 +459,7 @@ bool brw_try_override_assembly(struct brw_codegen *p, int start_offset, } ASSERTED bool valid = - brw_validate_instructions(p->isa, p->store, + elk_validate_instructions(p->isa, p->store, start_offset, p->next_insn_offset, NULL); assert(valid); @@ -467,10 +467,10 @@ bool brw_try_override_assembly(struct brw_codegen *p, int start_offset, return true; } -const struct brw_label * -brw_find_label(const struct brw_label *root, int offset) +const struct elk_label * +elk_find_label(const struct elk_label *root, int offset) { - const struct brw_label *curr = root; + const struct elk_label *curr = root; if (curr != NULL) { @@ -486,11 +486,11 @@ brw_find_label(const struct brw_label *root, int offset) } void -brw_create_label(struct brw_label **labels, int offset, void *mem_ctx) +elk_create_label(struct elk_label **labels, int offset, void *mem_ctx) { if (*labels != NULL) { - struct brw_label *curr = *labels; - struct brw_label *prev; + struct elk_label *curr = *labels; + struct elk_label *prev; do { prev = curr; @@ -501,13 +501,13 @@ brw_create_label(struct brw_label **labels, int offset, void *mem_ctx) curr = curr->next; } while (curr != NULL); - curr = ralloc(mem_ctx, struct brw_label); + curr = ralloc(mem_ctx, struct elk_label); curr->offset = offset; curr->number = prev->number + 1; curr->next = NULL; prev->next = curr; } else { - struct brw_label *root = ralloc(mem_ctx, struct brw_label); + struct elk_label *root = ralloc(mem_ctx, struct elk_label); root->number = 0; root->offset = offset; root->next = NULL; @@ -515,49 +515,49 @@ brw_create_label(struct brw_label **labels, int offset, void *mem_ctx) } } -const struct brw_label * -brw_label_assembly(const struct brw_isa_info *isa, +const struct elk_label * +elk_label_assembly(const struct elk_isa_info *isa, const void *assembly, int start, int end, void *mem_ctx) { const struct intel_device_info *const devinfo = isa->devinfo; - struct brw_label *root_label = NULL; + struct elk_label *root_label = NULL; - int to_bytes_scale = sizeof(brw_inst) / brw_jump_scale(devinfo); + int to_bytes_scale = sizeof(elk_inst) / elk_jump_scale(devinfo); for (int offset = start; offset < end;) { - const brw_inst *inst = (const brw_inst *) ((const char *) assembly + offset); - brw_inst uncompacted; + const elk_inst *inst = (const elk_inst *) ((const char *) assembly + offset); + elk_inst uncompacted; - bool is_compact = brw_inst_cmpt_control(devinfo, inst); + bool is_compact = elk_inst_cmpt_control(devinfo, inst); if (is_compact) { - brw_compact_inst *compacted = (brw_compact_inst *)inst; - brw_uncompact_instruction(isa, &uncompacted, compacted); + elk_compact_inst *compacted = (elk_compact_inst *)inst; + elk_uncompact_instruction(isa, &uncompacted, compacted); inst = &uncompacted; } - if (brw_has_uip(devinfo, brw_inst_opcode(isa, inst))) { + if (elk_has_uip(devinfo, elk_inst_opcode(isa, inst))) { /* Instructions that have UIP also have JIP. */ - brw_create_label(&root_label, - offset + brw_inst_uip(devinfo, inst) * to_bytes_scale, mem_ctx); - brw_create_label(&root_label, - offset + brw_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx); - } else if (brw_has_jip(devinfo, brw_inst_opcode(isa, inst))) { + elk_create_label(&root_label, + offset + elk_inst_uip(devinfo, inst) * to_bytes_scale, mem_ctx); + elk_create_label(&root_label, + offset + elk_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx); + } else if (elk_has_jip(devinfo, elk_inst_opcode(isa, inst))) { int jip; if (devinfo->ver >= 7) { - jip = brw_inst_jip(devinfo, inst); + jip = elk_inst_jip(devinfo, inst); } else { - jip = brw_inst_gfx6_jump_count(devinfo, inst); + jip = elk_inst_gfx6_jump_count(devinfo, inst); } - brw_create_label(&root_label, offset + jip * to_bytes_scale, mem_ctx); + elk_create_label(&root_label, offset + jip * to_bytes_scale, mem_ctx); } if (is_compact) { - offset += sizeof(brw_compact_inst); + offset += sizeof(elk_compact_inst); } else { - offset += sizeof(brw_inst); + offset += sizeof(elk_inst); } } @@ -565,44 +565,44 @@ brw_label_assembly(const struct brw_isa_info *isa, } void -brw_disassemble_with_labels(const struct brw_isa_info *isa, +elk_disassemble_with_labels(const struct elk_isa_info *isa, const void *assembly, int start, int end, FILE *out) { void *mem_ctx = ralloc_context(NULL); - const struct brw_label *root_label = - brw_label_assembly(isa, assembly, start, end, mem_ctx); + const struct elk_label *root_label = + elk_label_assembly(isa, assembly, start, end, mem_ctx); - brw_disassemble(isa, assembly, start, end, root_label, out); + elk_disassemble(isa, assembly, start, end, root_label, out); ralloc_free(mem_ctx); } void -brw_disassemble(const struct brw_isa_info *isa, +elk_disassemble(const struct elk_isa_info *isa, const void *assembly, int start, int end, - const struct brw_label *root_label, FILE *out) + const struct elk_label *root_label, FILE *out) { const struct intel_device_info *devinfo = isa->devinfo; bool dump_hex = INTEL_DEBUG(DEBUG_HEX); for (int offset = start; offset < end;) { - const brw_inst *insn = (const brw_inst *)((char *)assembly + offset); - brw_inst uncompacted; + const elk_inst *insn = (const elk_inst *)((char *)assembly + offset); + elk_inst uncompacted; if (root_label != NULL) { - const struct brw_label *label = brw_find_label(root_label, offset); + const struct elk_label *label = elk_find_label(root_label, offset); if (label != NULL) { fprintf(out, "\nLABEL%d:\n", label->number); } } - bool compacted = brw_inst_cmpt_control(devinfo, insn); + bool compacted = elk_inst_cmpt_control(devinfo, insn); if (0) fprintf(out, "0x%08x: ", offset); if (compacted) { - brw_compact_inst *compacted = (brw_compact_inst *)insn; + elk_compact_inst *compacted = (elk_compact_inst *)insn; if (dump_hex) { unsigned char * insn_ptr = ((unsigned char *)&insn[0]); const unsigned int blank_spaces = 24; @@ -619,7 +619,7 @@ brw_disassemble(const struct brw_isa_info *isa, fprintf(out, "%*c", blank_spaces, ' '); } - brw_uncompact_instruction(isa, &uncompacted, compacted); + elk_uncompact_instruction(isa, &uncompacted, compacted); insn = &uncompacted; } else { if (dump_hex) { @@ -634,130 +634,130 @@ brw_disassemble(const struct brw_isa_info *isa, } } - brw_disassemble_inst(out, isa, insn, compacted, offset, root_label); + elk_disassemble_inst(out, isa, insn, compacted, offset, root_label); if (compacted) { - offset += sizeof(brw_compact_inst); + offset += sizeof(elk_compact_inst); } else { - offset += sizeof(brw_inst); + offset += sizeof(elk_inst); } } } -static const struct opcode_desc opcode_descs[] = { +static const struct elk_opcode_desc opcode_descs[] = { /* IR, HW, name, nsrc, ndst, gfx_vers */ - { BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GFX_ALL }, - { BRW_OPCODE_SYNC, 1, "sync", 1, 0, GFX_GE(GFX12) }, - { BRW_OPCODE_MOV, 1, "mov", 1, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_MOV, 97, "mov", 1, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_SEL, 2, "sel", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_SEL, 98, "sel", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_MOVI, 3, "movi", 2, 1, GFX_GE(GFX45) & GFX_LT(GFX12) }, - { BRW_OPCODE_MOVI, 99, "movi", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_NOT, 4, "not", 1, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_NOT, 100, "not", 1, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_AND, 5, "and", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_AND, 101, "and", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_OR, 6, "or", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_OR, 102, "or", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_XOR, 7, "xor", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_XOR, 103, "xor", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_SHR, 8, "shr", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_SHR, 104, "shr", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_SHL, 9, "shl", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_SHL, 105, "shl", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_DIM, 10, "dim", 1, 1, GFX75 }, - { BRW_OPCODE_SMOV, 10, "smov", 0, 0, GFX_GE(GFX8) & GFX_LT(GFX12) }, - { BRW_OPCODE_SMOV, 106, "smov", 0, 0, GFX_GE(GFX12) }, - { BRW_OPCODE_ASR, 12, "asr", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_ASR, 108, "asr", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_ROR, 14, "ror", 2, 1, GFX11 }, - { BRW_OPCODE_ROR, 110, "ror", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_ROL, 15, "rol", 2, 1, GFX11 }, - { BRW_OPCODE_ROL, 111, "rol", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_CMP, 16, "cmp", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_CMP, 112, "cmp", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_CMPN, 17, "cmpn", 2, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_CMPN, 113, "cmpn", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_CSEL, 18, "csel", 3, 1, GFX_GE(GFX8) & GFX_LT(GFX12) }, - { BRW_OPCODE_CSEL, 114, "csel", 3, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 }, - { BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 }, - { BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) }, - { BRW_OPCODE_BFREV, 119, "bfrev", 1, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) }, - { BRW_OPCODE_BFE, 120, "bfe", 3, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GFX_GE(GFX7) & GFX_LT(GFX12) }, - { BRW_OPCODE_BFI1, 121, "bfi1", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) }, - { BRW_OPCODE_BFI2, 122, "bfi2", 3, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_JMPI, 32, "jmpi", 0, 0, GFX_ALL }, - { BRW_OPCODE_BRD, 33, "brd", 0, 0, GFX_GE(GFX7) }, - { BRW_OPCODE_IF, 34, "if", 0, 0, GFX_ALL }, - { BRW_OPCODE_IFF, 35, "iff", 0, 0, GFX_LE(GFX5) }, - { BRW_OPCODE_BRC, 35, "brc", 0, 0, GFX_GE(GFX7) }, - { BRW_OPCODE_ELSE, 36, "else", 0, 0, GFX_ALL }, - { BRW_OPCODE_ENDIF, 37, "endif", 0, 0, GFX_ALL }, - { BRW_OPCODE_DO, 38, "do", 0, 0, GFX_LE(GFX5) }, - { BRW_OPCODE_CASE, 38, "case", 0, 0, GFX6 }, - { BRW_OPCODE_WHILE, 39, "while", 0, 0, GFX_ALL }, - { BRW_OPCODE_BREAK, 40, "break", 0, 0, GFX_ALL }, - { BRW_OPCODE_CONTINUE, 41, "cont", 0, 0, GFX_ALL }, - { BRW_OPCODE_HALT, 42, "halt", 0, 0, GFX_ALL }, - { BRW_OPCODE_CALLA, 43, "calla", 0, 0, GFX_GE(GFX75) }, - { BRW_OPCODE_MSAVE, 44, "msave", 0, 0, GFX_LE(GFX5) }, - { BRW_OPCODE_CALL, 44, "call", 0, 0, GFX_GE(GFX6) }, - { BRW_OPCODE_MREST, 45, "mrest", 0, 0, GFX_LE(GFX5) }, - { BRW_OPCODE_RET, 45, "ret", 0, 0, GFX_GE(GFX6) }, - { BRW_OPCODE_PUSH, 46, "push", 0, 0, GFX_LE(GFX5) }, - { BRW_OPCODE_FORK, 46, "fork", 0, 0, GFX6 }, - { BRW_OPCODE_GOTO, 46, "goto", 0, 0, GFX_GE(GFX8) }, - { BRW_OPCODE_POP, 47, "pop", 2, 0, GFX_LE(GFX5) }, - { BRW_OPCODE_WAIT, 48, "wait", 0, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_SEND, 49, "send", 1, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_SENDC, 50, "sendc", 1, 1, GFX_LT(GFX12) }, - { BRW_OPCODE_SEND, 49, "send", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_SENDC, 50, "sendc", 2, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_SENDS, 51, "sends", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) }, - { BRW_OPCODE_SENDSC, 52, "sendsc", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) }, - { BRW_OPCODE_MATH, 56, "math", 2, 1, GFX_GE(GFX6) }, - { BRW_OPCODE_ADD, 64, "add", 2, 1, GFX_ALL }, - { BRW_OPCODE_MUL, 65, "mul", 2, 1, GFX_ALL }, - { BRW_OPCODE_AVG, 66, "avg", 2, 1, GFX_ALL }, - { BRW_OPCODE_FRC, 67, "frc", 1, 1, GFX_ALL }, - { BRW_OPCODE_RNDU, 68, "rndu", 1, 1, GFX_ALL }, - { BRW_OPCODE_RNDD, 69, "rndd", 1, 1, GFX_ALL }, - { BRW_OPCODE_RNDE, 70, "rnde", 1, 1, GFX_ALL }, - { BRW_OPCODE_RNDZ, 71, "rndz", 1, 1, GFX_ALL }, - { BRW_OPCODE_MAC, 72, "mac", 2, 1, GFX_ALL }, - { BRW_OPCODE_MACH, 73, "mach", 2, 1, GFX_ALL }, - { BRW_OPCODE_LZD, 74, "lzd", 1, 1, GFX_ALL }, - { BRW_OPCODE_FBH, 75, "fbh", 1, 1, GFX_GE(GFX7) }, - { BRW_OPCODE_FBL, 76, "fbl", 1, 1, GFX_GE(GFX7) }, - { BRW_OPCODE_CBIT, 77, "cbit", 1, 1, GFX_GE(GFX7) }, - { BRW_OPCODE_ADDC, 78, "addc", 2, 1, GFX_GE(GFX7) }, - { BRW_OPCODE_SUBB, 79, "subb", 2, 1, GFX_GE(GFX7) }, - { BRW_OPCODE_SAD2, 80, "sad2", 2, 1, GFX_ALL }, - { BRW_OPCODE_SADA2, 81, "sada2", 2, 1, GFX_ALL }, - { BRW_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) }, - { BRW_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) }, - { BRW_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) }, - { BRW_OPCODE_DP3, 86, "dp3", 2, 1, GFX_LT(GFX11) }, - { BRW_OPCODE_DP2, 87, "dp2", 2, 1, GFX_LT(GFX11) }, - { BRW_OPCODE_DP4A, 88, "dp4a", 3, 1, GFX_GE(GFX12) }, - { BRW_OPCODE_LINE, 89, "line", 2, 1, GFX_LE(GFX10) }, - { BRW_OPCODE_DPAS, 89, "dpas", 3, 1, GFX_GE(GFX125) }, - { BRW_OPCODE_PLN, 90, "pln", 2, 1, GFX_GE(GFX45) & GFX_LE(GFX10) }, - { BRW_OPCODE_MAD, 91, "mad", 3, 1, GFX_GE(GFX6) }, - { BRW_OPCODE_LRP, 92, "lrp", 3, 1, GFX_GE(GFX6) & GFX_LE(GFX10) }, - { BRW_OPCODE_MADM, 93, "madm", 3, 1, GFX_GE(GFX8) }, - { BRW_OPCODE_NENOP, 125, "nenop", 0, 0, GFX45 }, - { BRW_OPCODE_NOP, 126, "nop", 0, 0, GFX_LT(GFX12) }, - { BRW_OPCODE_NOP, 96, "nop", 0, 0, GFX_GE(GFX12) } + { ELK_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GFX_ALL }, + { ELK_OPCODE_SYNC, 1, "sync", 1, 0, GFX_GE(GFX12) }, + { ELK_OPCODE_MOV, 1, "mov", 1, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_MOV, 97, "mov", 1, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_SEL, 2, "sel", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_SEL, 98, "sel", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_MOVI, 3, "movi", 2, 1, GFX_GE(GFX45) & GFX_LT(GFX12) }, + { ELK_OPCODE_MOVI, 99, "movi", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_NOT, 4, "not", 1, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_NOT, 100, "not", 1, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_AND, 5, "and", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_AND, 101, "and", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_OR, 6, "or", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_OR, 102, "or", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_XOR, 7, "xor", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_XOR, 103, "xor", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_SHR, 8, "shr", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_SHR, 104, "shr", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_SHL, 9, "shl", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_SHL, 105, "shl", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_DIM, 10, "dim", 1, 1, GFX75 }, + { ELK_OPCODE_SMOV, 10, "smov", 0, 0, GFX_GE(GFX8) & GFX_LT(GFX12) }, + { ELK_OPCODE_SMOV, 106, "smov", 0, 0, GFX_GE(GFX12) }, + { ELK_OPCODE_ASR, 12, "asr", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_ASR, 108, "asr", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_ROR, 14, "ror", 2, 1, GFX11 }, + { ELK_OPCODE_ROR, 110, "ror", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_ROL, 15, "rol", 2, 1, GFX11 }, + { ELK_OPCODE_ROL, 111, "rol", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_CMP, 16, "cmp", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_CMP, 112, "cmp", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_CMPN, 17, "cmpn", 2, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_CMPN, 113, "cmpn", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_CSEL, 18, "csel", 3, 1, GFX_GE(GFX8) & GFX_LT(GFX12) }, + { ELK_OPCODE_CSEL, 114, "csel", 3, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 }, + { ELK_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 }, + { ELK_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) }, + { ELK_OPCODE_BFREV, 119, "bfrev", 1, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) }, + { ELK_OPCODE_BFE, 120, "bfe", 3, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_BFI1, 25, "bfi1", 2, 1, GFX_GE(GFX7) & GFX_LT(GFX12) }, + { ELK_OPCODE_BFI1, 121, "bfi1", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_BFI2, 26, "bfi2", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) }, + { ELK_OPCODE_BFI2, 122, "bfi2", 3, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_JMPI, 32, "jmpi", 0, 0, GFX_ALL }, + { ELK_OPCODE_BRD, 33, "brd", 0, 0, GFX_GE(GFX7) }, + { ELK_OPCODE_IF, 34, "if", 0, 0, GFX_ALL }, + { ELK_OPCODE_IFF, 35, "iff", 0, 0, GFX_LE(GFX5) }, + { ELK_OPCODE_BRC, 35, "brc", 0, 0, GFX_GE(GFX7) }, + { ELK_OPCODE_ELSE, 36, "else", 0, 0, GFX_ALL }, + { ELK_OPCODE_ENDIF, 37, "endif", 0, 0, GFX_ALL }, + { ELK_OPCODE_DO, 38, "do", 0, 0, GFX_LE(GFX5) }, + { ELK_OPCODE_CASE, 38, "case", 0, 0, GFX6 }, + { ELK_OPCODE_WHILE, 39, "while", 0, 0, GFX_ALL }, + { ELK_OPCODE_BREAK, 40, "break", 0, 0, GFX_ALL }, + { ELK_OPCODE_CONTINUE, 41, "cont", 0, 0, GFX_ALL }, + { ELK_OPCODE_HALT, 42, "halt", 0, 0, GFX_ALL }, + { ELK_OPCODE_CALLA, 43, "calla", 0, 0, GFX_GE(GFX75) }, + { ELK_OPCODE_MSAVE, 44, "msave", 0, 0, GFX_LE(GFX5) }, + { ELK_OPCODE_CALL, 44, "call", 0, 0, GFX_GE(GFX6) }, + { ELK_OPCODE_MREST, 45, "mrest", 0, 0, GFX_LE(GFX5) }, + { ELK_OPCODE_RET, 45, "ret", 0, 0, GFX_GE(GFX6) }, + { ELK_OPCODE_PUSH, 46, "push", 0, 0, GFX_LE(GFX5) }, + { ELK_OPCODE_FORK, 46, "fork", 0, 0, GFX6 }, + { ELK_OPCODE_GOTO, 46, "goto", 0, 0, GFX_GE(GFX8) }, + { ELK_OPCODE_POP, 47, "pop", 2, 0, GFX_LE(GFX5) }, + { ELK_OPCODE_WAIT, 48, "wait", 0, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_SEND, 49, "send", 1, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_SENDC, 50, "sendc", 1, 1, GFX_LT(GFX12) }, + { ELK_OPCODE_SEND, 49, "send", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_SENDC, 50, "sendc", 2, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_SENDS, 51, "sends", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) }, + { ELK_OPCODE_SENDSC, 52, "sendsc", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) }, + { ELK_OPCODE_MATH, 56, "math", 2, 1, GFX_GE(GFX6) }, + { ELK_OPCODE_ADD, 64, "add", 2, 1, GFX_ALL }, + { ELK_OPCODE_MUL, 65, "mul", 2, 1, GFX_ALL }, + { ELK_OPCODE_AVG, 66, "avg", 2, 1, GFX_ALL }, + { ELK_OPCODE_FRC, 67, "frc", 1, 1, GFX_ALL }, + { ELK_OPCODE_RNDU, 68, "rndu", 1, 1, GFX_ALL }, + { ELK_OPCODE_RNDD, 69, "rndd", 1, 1, GFX_ALL }, + { ELK_OPCODE_RNDE, 70, "rnde", 1, 1, GFX_ALL }, + { ELK_OPCODE_RNDZ, 71, "rndz", 1, 1, GFX_ALL }, + { ELK_OPCODE_MAC, 72, "mac", 2, 1, GFX_ALL }, + { ELK_OPCODE_MACH, 73, "mach", 2, 1, GFX_ALL }, + { ELK_OPCODE_LZD, 74, "lzd", 1, 1, GFX_ALL }, + { ELK_OPCODE_FBH, 75, "fbh", 1, 1, GFX_GE(GFX7) }, + { ELK_OPCODE_FBL, 76, "fbl", 1, 1, GFX_GE(GFX7) }, + { ELK_OPCODE_CBIT, 77, "cbit", 1, 1, GFX_GE(GFX7) }, + { ELK_OPCODE_ADDC, 78, "addc", 2, 1, GFX_GE(GFX7) }, + { ELK_OPCODE_SUBB, 79, "subb", 2, 1, GFX_GE(GFX7) }, + { ELK_OPCODE_SAD2, 80, "sad2", 2, 1, GFX_ALL }, + { ELK_OPCODE_SADA2, 81, "sada2", 2, 1, GFX_ALL }, + { ELK_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) }, + { ELK_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) }, + { ELK_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) }, + { ELK_OPCODE_DP3, 86, "dp3", 2, 1, GFX_LT(GFX11) }, + { ELK_OPCODE_DP2, 87, "dp2", 2, 1, GFX_LT(GFX11) }, + { ELK_OPCODE_DP4A, 88, "dp4a", 3, 1, GFX_GE(GFX12) }, + { ELK_OPCODE_LINE, 89, "line", 2, 1, GFX_LE(GFX10) }, + { ELK_OPCODE_DPAS, 89, "dpas", 3, 1, GFX_GE(GFX125) }, + { ELK_OPCODE_PLN, 90, "pln", 2, 1, GFX_GE(GFX45) & GFX_LE(GFX10) }, + { ELK_OPCODE_MAD, 91, "mad", 3, 1, GFX_GE(GFX6) }, + { ELK_OPCODE_LRP, 92, "lrp", 3, 1, GFX_GE(GFX6) & GFX_LE(GFX10) }, + { ELK_OPCODE_MADM, 93, "madm", 3, 1, GFX_GE(GFX8) }, + { ELK_OPCODE_NENOP, 125, "nenop", 0, 0, GFX45 }, + { ELK_OPCODE_NOP, 126, "nop", 0, 0, GFX_LT(GFX12) }, + { ELK_OPCODE_NOP, 96, "nop", 0, 0, GFX_GE(GFX12) } }; void -brw_init_isa_info(struct brw_isa_info *isa, +elk_init_isa_info(struct elk_isa_info *isa, const struct intel_device_info *devinfo) { isa->devinfo = devinfo; @@ -783,8 +783,8 @@ brw_init_isa_info(struct brw_isa_info *isa, * Return the matching opcode_desc for the specified IR opcode and hardware * generation, or NULL if the opcode is not supported by the device. */ -const struct opcode_desc * -brw_opcode_desc(const struct brw_isa_info *isa, enum opcode op) +const struct elk_opcode_desc * +elk_opcode_desc(const struct elk_isa_info *isa, enum elk_opcode op) { return op < ARRAY_SIZE(isa->ir_to_descs) ? isa->ir_to_descs[op] : NULL; } @@ -793,26 +793,26 @@ brw_opcode_desc(const struct brw_isa_info *isa, enum opcode op) * Return the matching opcode_desc for the specified HW opcode and hardware * generation, or NULL if the opcode is not supported by the device. */ -const struct opcode_desc * -brw_opcode_desc_from_hw(const struct brw_isa_info *isa, unsigned hw) +const struct elk_opcode_desc * +elk_opcode_desc_from_hw(const struct elk_isa_info *isa, unsigned hw) { return hw < ARRAY_SIZE(isa->hw_to_descs) ? isa->hw_to_descs[hw] : NULL; } unsigned -brw_num_sources_from_inst(const struct brw_isa_info *isa, - const brw_inst *inst) +elk_num_sources_from_inst(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - const struct opcode_desc *desc = - brw_opcode_desc(isa, brw_inst_opcode(isa, inst)); + const struct elk_opcode_desc *desc = + elk_opcode_desc(isa, elk_inst_opcode(isa, inst)); unsigned math_function; - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) { - math_function = brw_inst_math_function(devinfo, inst); + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_MATH) { + math_function = elk_inst_math_function(devinfo, inst); } else if (devinfo->ver < 6 && - brw_inst_opcode(isa, inst) == BRW_OPCODE_SEND) { - if (brw_inst_sfid(devinfo, inst) == BRW_SFID_MATH) { + elk_inst_opcode(isa, inst) == ELK_OPCODE_SEND) { + if (elk_inst_sfid(devinfo, inst) == ELK_SFID_MATH) { /* src1 must be a descriptor (including the information to determine * that the SEND is doing an extended math operation), but src0 can * actually be null since it serves as the source of the implicit GRF @@ -833,22 +833,22 @@ brw_num_sources_from_inst(const struct brw_isa_info *isa, } switch (math_function) { - case BRW_MATH_FUNCTION_INV: - case BRW_MATH_FUNCTION_LOG: - case BRW_MATH_FUNCTION_EXP: - case BRW_MATH_FUNCTION_SQRT: - case BRW_MATH_FUNCTION_RSQ: - case BRW_MATH_FUNCTION_SIN: - case BRW_MATH_FUNCTION_COS: - case BRW_MATH_FUNCTION_SINCOS: + case ELK_MATH_FUNCTION_INV: + case ELK_MATH_FUNCTION_LOG: + case ELK_MATH_FUNCTION_EXP: + case ELK_MATH_FUNCTION_SQRT: + case ELK_MATH_FUNCTION_RSQ: + case ELK_MATH_FUNCTION_SIN: + case ELK_MATH_FUNCTION_COS: + case ELK_MATH_FUNCTION_SINCOS: case GFX8_MATH_FUNCTION_INVM: case GFX8_MATH_FUNCTION_RSQRTM: return 1; - case BRW_MATH_FUNCTION_FDIV: - case BRW_MATH_FUNCTION_POW: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT: - case BRW_MATH_FUNCTION_INT_DIV_REMAINDER: + case ELK_MATH_FUNCTION_FDIV: + case ELK_MATH_FUNCTION_POW: + case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: + case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT: + case ELK_MATH_FUNCTION_INT_DIV_REMAINDER: return 2; default: unreachable("not reached"); diff --git a/src/intel/compiler/elk/elk_eu.h b/src/intel/compiler/elk/elk_eu.h index fe483910eb0..85331de72a3 100644 --- a/src/intel/compiler/elk/elk_eu.h +++ b/src/intel/compiler/elk/elk_eu.h @@ -47,12 +47,12 @@ extern "C" { #endif -struct disasm_info; +struct elk_disasm_info; -#define BRW_EU_MAX_INSN_STACK 5 +#define ELK_EU_MAX_INSN_STACK 5 -struct brw_insn_state { - /* One of BRW_EXECUTE_* */ +struct elk_insn_state { + /* One of ELK_EXECUTE_* */ unsigned exec_size:3; /* Group in units of channels */ @@ -61,7 +61,7 @@ struct brw_insn_state { /* Compression control on gfx4-5 */ bool compressed:1; - /* One of BRW_MASK_* */ + /* One of ELK_MASK_* */ unsigned mask_control:1; /* Scheduling info for Gfx12+ */ @@ -69,11 +69,11 @@ struct brw_insn_state { bool saturate:1; - /* One of BRW_ALIGN_* */ + /* One of ELK_ALIGN_* */ unsigned access_mode:1; - /* One of BRW_PREDICATE_* */ - enum brw_predicate predicate:4; + /* One of ELK_PREDICATE_* */ + enum elk_predicate predicate:4; bool pred_inv:1; @@ -88,10 +88,10 @@ struct brw_insn_state { * to set various bits on an instruction without having to create temporary * variable and assign the emitted instruction to those. */ -#define brw_last_inst (&p->store[p->nr_insn - 1]) +#define elk_last_inst (&p->store[p->nr_insn - 1]) -struct brw_codegen { - brw_inst *store; +struct elk_codegen { + elk_inst *store; int store_size; unsigned nr_insn; unsigned int next_insn_offset; @@ -100,21 +100,21 @@ struct brw_codegen { /* Allow clients to push/pop instruction state: */ - struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK]; - struct brw_insn_state *current; + struct elk_insn_state stack[ELK_EU_MAX_INSN_STACK]; + struct elk_insn_state *current; /** Whether or not the user wants automatic exec sizes * * If true, codegen will try to automatically infer the exec size of an * instruction from the width of the destination register. If false, it - * will take whatever is set by brw_set_default_exec_size verbatim. + * will take whatever is set by elk_set_default_exec_size verbatim. * - * This is set to true by default in brw_init_codegen. + * This is set to true by default in elk_init_codegen. */ bool automatic_exec_sizes; bool single_program_flow; - const struct brw_isa_info *isa; + const struct elk_isa_info *isa; const struct intel_device_info *devinfo; /* Control flow stacks: @@ -142,88 +142,88 @@ struct brw_codegen { int loop_stack_depth; int loop_stack_array_size; - struct brw_shader_reloc *relocs; + struct elk_shader_reloc *relocs; int num_relocs; int reloc_array_size; }; -struct brw_label { +struct elk_label { int offset; int number; - struct brw_label *next; + struct elk_label *next; }; -void brw_pop_insn_state( struct brw_codegen *p ); -void brw_push_insn_state( struct brw_codegen *p ); -unsigned brw_get_default_exec_size(struct brw_codegen *p); -unsigned brw_get_default_group(struct brw_codegen *p); -unsigned brw_get_default_access_mode(struct brw_codegen *p); -struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p); -void brw_set_default_exec_size(struct brw_codegen *p, unsigned value); -void brw_set_default_mask_control( struct brw_codegen *p, unsigned value ); -void brw_set_default_saturate( struct brw_codegen *p, bool enable ); -void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode ); -void brw_inst_set_compression(const struct intel_device_info *devinfo, - brw_inst *inst, bool on); -void brw_set_default_compression(struct brw_codegen *p, bool on); -void brw_inst_set_group(const struct intel_device_info *devinfo, - brw_inst *inst, unsigned group); -void brw_set_default_group(struct brw_codegen *p, unsigned group); -void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c); -void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc); -void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse); -void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg); -void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value); -void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value); +void elk_pop_insn_state( struct elk_codegen *p ); +void elk_push_insn_state( struct elk_codegen *p ); +unsigned elk_get_default_exec_size(struct elk_codegen *p); +unsigned elk_get_default_group(struct elk_codegen *p); +unsigned elk_get_default_access_mode(struct elk_codegen *p); +struct tgl_swsb elk_get_default_swsb(struct elk_codegen *p); +void elk_set_default_exec_size(struct elk_codegen *p, unsigned value); +void elk_set_default_mask_control( struct elk_codegen *p, unsigned value ); +void elk_set_default_saturate( struct elk_codegen *p, bool enable ); +void elk_set_default_access_mode( struct elk_codegen *p, unsigned access_mode ); +void elk_inst_set_compression(const struct intel_device_info *devinfo, + elk_inst *inst, bool on); +void elk_set_default_compression(struct elk_codegen *p, bool on); +void elk_inst_set_group(const struct intel_device_info *devinfo, + elk_inst *inst, unsigned group); +void elk_set_default_group(struct elk_codegen *p, unsigned group); +void elk_set_default_compression_control(struct elk_codegen *p, enum elk_compression c); +void elk_set_default_predicate_control(struct elk_codegen *p, enum elk_predicate pc); +void elk_set_default_predicate_inverse(struct elk_codegen *p, bool predicate_inverse); +void elk_set_default_flag_reg(struct elk_codegen *p, int reg, int subreg); +void elk_set_default_acc_write_control(struct elk_codegen *p, unsigned value); +void elk_set_default_swsb(struct elk_codegen *p, struct tgl_swsb value); -void brw_init_codegen(const struct brw_isa_info *isa, - struct brw_codegen *p, void *mem_ctx); -bool brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode); -bool brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode); -const struct brw_shader_reloc *brw_get_shader_relocs(struct brw_codegen *p, +void elk_init_codegen(const struct elk_isa_info *isa, + struct elk_codegen *p, void *mem_ctx); +bool elk_has_jip(const struct intel_device_info *devinfo, enum elk_opcode opcode); +bool elk_has_uip(const struct intel_device_info *devinfo, enum elk_opcode opcode); +const struct elk_shader_reloc *elk_get_shader_relocs(struct elk_codegen *p, unsigned *num_relocs); -const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz ); +const unsigned *elk_get_program( struct elk_codegen *p, unsigned *sz ); -bool brw_should_dump_shader_bin(void); -void brw_dump_shader_bin(void *assembly, int start_offset, int end_offset, +bool elk_should_dump_shader_bin(void); +void elk_dump_shader_bin(void *assembly, int start_offset, int end_offset, const char *identifier); -bool brw_try_override_assembly(struct brw_codegen *p, int start_offset, +bool elk_try_override_assembly(struct elk_codegen *p, int start_offset, const char *identifier); -void brw_realign(struct brw_codegen *p, unsigned alignment); -int brw_append_data(struct brw_codegen *p, void *data, +void elk_realign(struct elk_codegen *p, unsigned alignment); +int elk_append_data(struct elk_codegen *p, void *data, unsigned size, unsigned alignment); -brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode); -void brw_add_reloc(struct brw_codegen *p, uint32_t id, - enum brw_shader_reloc_type type, +elk_inst *elk_next_insn(struct elk_codegen *p, unsigned opcode); +void elk_add_reloc(struct elk_codegen *p, uint32_t id, + enum elk_shader_reloc_type type, uint32_t offset, uint32_t delta); -void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest); -void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg); +void elk_set_dest(struct elk_codegen *p, elk_inst *insn, struct elk_reg dest); +void elk_set_src0(struct elk_codegen *p, elk_inst *insn, struct elk_reg reg); -void gfx6_resolve_implied_move(struct brw_codegen *p, - struct brw_reg *src, +void elk_gfx6_resolve_implied_move(struct elk_codegen *p, + struct elk_reg *src, unsigned msg_reg_nr); /* Helpers for regular instructions: */ #define ALU1(OP) \ -brw_inst *brw_##OP(struct brw_codegen *p, \ - struct brw_reg dest, \ - struct brw_reg src0); +elk_inst *elk_##OP(struct elk_codegen *p, \ + struct elk_reg dest, \ + struct elk_reg src0); #define ALU2(OP) \ -brw_inst *brw_##OP(struct brw_codegen *p, \ - struct brw_reg dest, \ - struct brw_reg src0, \ - struct brw_reg src1); +elk_inst *elk_##OP(struct elk_codegen *p, \ + struct elk_reg dest, \ + struct elk_reg src0, \ + struct elk_reg src1); #define ALU3(OP) \ -brw_inst *brw_##OP(struct brw_codegen *p, \ - struct brw_reg dest, \ - struct brw_reg src0, \ - struct brw_reg src1, \ - struct brw_reg src2); +elk_inst *elk_##OP(struct elk_codegen *p, \ + struct elk_reg dest, \ + struct elk_reg src0, \ + struct elk_reg src1, \ + struct elk_reg src2); ALU1(MOV) ALU2(SEL) @@ -290,7 +290,7 @@ reg_unit(const struct intel_device_info *devinfo) * descriptor controls. */ static inline uint32_t -brw_message_desc(const struct intel_device_info *devinfo, +elk_message_desc(const struct intel_device_info *devinfo, unsigned msg_length, unsigned response_length, bool header_present) @@ -308,7 +308,7 @@ brw_message_desc(const struct intel_device_info *devinfo, } static inline unsigned -brw_message_desc_mlen(const struct intel_device_info *devinfo, uint32_t desc) +elk_message_desc_mlen(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 5) return GET_BITS(desc, 28, 25) * reg_unit(devinfo); @@ -317,7 +317,7 @@ brw_message_desc_mlen(const struct intel_device_info *devinfo, uint32_t desc) } static inline unsigned -brw_message_desc_rlen(const struct intel_device_info *devinfo, uint32_t desc) +elk_message_desc_rlen(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 5) return GET_BITS(desc, 24, 20) * reg_unit(devinfo); @@ -326,7 +326,7 @@ brw_message_desc_rlen(const struct intel_device_info *devinfo, uint32_t desc) } static inline bool -brw_message_desc_header_present(ASSERTED +elk_message_desc_header_present(ASSERTED const struct intel_device_info *devinfo, uint32_t desc) { @@ -335,7 +335,7 @@ brw_message_desc_header_present(ASSERTED } static inline unsigned -brw_message_ex_desc(const struct intel_device_info *devinfo, +elk_message_ex_desc(const struct intel_device_info *devinfo, unsigned ex_msg_length) { assert(ex_msg_length % reg_unit(devinfo) == 0); @@ -343,14 +343,14 @@ brw_message_ex_desc(const struct intel_device_info *devinfo, } static inline unsigned -brw_message_ex_desc_ex_mlen(const struct intel_device_info *devinfo, +elk_message_ex_desc_ex_mlen(const struct intel_device_info *devinfo, uint32_t ex_desc) { return GET_BITS(ex_desc, 9, 6) * reg_unit(devinfo); } static inline uint32_t -brw_urb_desc(const struct intel_device_info *devinfo, +elk_urb_desc(const struct intel_device_info *devinfo, unsigned msg_type, bool per_slot_offset_present, bool channel_mask_present, @@ -372,7 +372,7 @@ brw_urb_desc(const struct intel_device_info *devinfo, } static inline uint32_t -brw_urb_desc_msg_type(ASSERTED const struct intel_device_info *devinfo, +elk_urb_desc_msg_type(ASSERTED const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver >= 7); @@ -380,10 +380,10 @@ brw_urb_desc_msg_type(ASSERTED const struct intel_device_info *devinfo, } static inline uint32_t -brw_urb_fence_desc(const struct intel_device_info *devinfo) +elk_urb_fence_desc(const struct intel_device_info *devinfo) { assert(devinfo->has_lsc); - return brw_urb_desc(devinfo, GFX125_URB_OPCODE_FENCE, false, false, 0); + return elk_urb_desc(devinfo, GFX125_URB_OPCODE_FENCE, false, false, 0); } /** @@ -391,7 +391,7 @@ brw_urb_fence_desc(const struct intel_device_info *devinfo) * function controls. */ static inline uint32_t -brw_sampler_desc(const struct intel_device_info *devinfo, +elk_sampler_desc(const struct intel_device_info *devinfo, unsigned binding_table_index, unsigned sampler, unsigned msg_type, @@ -440,7 +440,7 @@ brw_sampler_desc(const struct intel_device_info *devinfo, } static inline unsigned -brw_sampler_desc_binding_table_index(UNUSED +elk_sampler_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { @@ -448,14 +448,14 @@ brw_sampler_desc_binding_table_index(UNUSED } static inline unsigned -brw_sampler_desc_sampler(UNUSED const struct intel_device_info *devinfo, +elk_sampler_desc_sampler(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { return GET_BITS(desc, 11, 8); } static inline unsigned -brw_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) +elk_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 20) return GET_BITS(desc, 31, 31) << 5 | GET_BITS(desc, 16, 12); @@ -468,7 +468,7 @@ brw_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc } static inline unsigned -brw_sampler_desc_simd_mode(const struct intel_device_info *devinfo, +elk_sampler_desc_simd_mode(const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver >= 5); @@ -481,7 +481,7 @@ brw_sampler_desc_simd_mode(const struct intel_device_info *devinfo, } static inline unsigned -brw_sampler_desc_return_format(ASSERTED const struct intel_device_info *devinfo, +elk_sampler_desc_return_format(ASSERTED const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->verx10 == 40 || devinfo->ver >= 8); @@ -495,7 +495,7 @@ brw_sampler_desc_return_format(ASSERTED const struct intel_device_info *devinfo, * Construct a message descriptor for the dataport */ static inline uint32_t -brw_dp_desc(const struct intel_device_info *devinfo, +elk_dp_desc(const struct intel_device_info *devinfo, unsigned binding_table_index, unsigned msg_type, unsigned msg_control) @@ -518,14 +518,14 @@ brw_dp_desc(const struct intel_device_info *devinfo, } static inline unsigned -brw_dp_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo, +elk_dp_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { return GET_BITS(desc, 7, 0); } static inline unsigned -brw_dp_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) +elk_dp_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver >= 6); if (devinfo->ver >= 8) @@ -537,7 +537,7 @@ brw_dp_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) } static inline unsigned -brw_dp_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) +elk_dp_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver >= 6); if (devinfo->ver >= 7) @@ -551,14 +551,14 @@ brw_dp_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) * function controls. */ static inline uint32_t -brw_dp_read_desc(const struct intel_device_info *devinfo, +elk_dp_read_desc(const struct intel_device_info *devinfo, unsigned binding_table_index, unsigned msg_control, unsigned msg_type, unsigned target_cache) { if (devinfo->ver >= 6) - return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control); + return elk_dp_desc(devinfo, binding_table_index, msg_type, msg_control); else if (devinfo->verx10 >= 45) return (SET_BITS(binding_table_index, 7, 0) | SET_BITS(msg_control, 10, 8) | @@ -572,11 +572,11 @@ brw_dp_read_desc(const struct intel_device_info *devinfo, } static inline unsigned -brw_dp_read_desc_msg_type(const struct intel_device_info *devinfo, +elk_dp_read_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 6) - return brw_dp_desc_msg_type(devinfo, desc); + return elk_dp_desc_msg_type(devinfo, desc); else if (devinfo->verx10 >= 45) return GET_BITS(desc, 13, 11); else @@ -584,11 +584,11 @@ brw_dp_read_desc_msg_type(const struct intel_device_info *devinfo, } static inline unsigned -brw_dp_read_desc_msg_control(const struct intel_device_info *devinfo, +elk_dp_read_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 6) - return brw_dp_desc_msg_control(devinfo, desc); + return elk_dp_desc_msg_control(devinfo, desc); else if (devinfo->verx10 >= 45) return GET_BITS(desc, 10, 8); else @@ -600,7 +600,7 @@ brw_dp_read_desc_msg_control(const struct intel_device_info *devinfo, * function controls. */ static inline uint32_t -brw_dp_write_desc(const struct intel_device_info *devinfo, +elk_dp_write_desc(const struct intel_device_info *devinfo, unsigned binding_table_index, unsigned msg_control, unsigned msg_type, @@ -608,7 +608,7 @@ brw_dp_write_desc(const struct intel_device_info *devinfo, { assert(devinfo->ver <= 6 || !send_commit_msg); if (devinfo->ver >= 6) { - return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) | + return elk_dp_desc(devinfo, binding_table_index, msg_type, msg_control) | SET_BITS(send_commit_msg, 17, 17); } else { return (SET_BITS(binding_table_index, 7, 0) | @@ -619,27 +619,27 @@ brw_dp_write_desc(const struct intel_device_info *devinfo, } static inline unsigned -brw_dp_write_desc_msg_type(const struct intel_device_info *devinfo, +elk_dp_write_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 6) - return brw_dp_desc_msg_type(devinfo, desc); + return elk_dp_desc_msg_type(devinfo, desc); else return GET_BITS(desc, 14, 12); } static inline unsigned -brw_dp_write_desc_msg_control(const struct intel_device_info *devinfo, +elk_dp_write_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 6) - return brw_dp_desc_msg_control(devinfo, desc); + return elk_dp_desc_msg_control(devinfo, desc); else return GET_BITS(desc, 11, 8); } static inline bool -brw_dp_write_desc_write_commit(const struct intel_device_info *devinfo, +elk_dp_write_desc_write_commit(const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver <= 6); @@ -654,17 +654,17 @@ brw_dp_write_desc_write_commit(const struct intel_device_info *devinfo, * surface function controls. */ static inline uint32_t -brw_dp_surface_desc(const struct intel_device_info *devinfo, +elk_dp_surface_desc(const struct intel_device_info *devinfo, unsigned msg_type, unsigned msg_control) { assert(devinfo->ver >= 7); /* We'll OR in the binding table index later */ - return brw_dp_desc(devinfo, 0, msg_type, msg_control); + return elk_dp_desc(devinfo, 0, msg_type, msg_control); } static inline uint32_t -brw_dp_untyped_atomic_desc(const struct intel_device_info *devinfo, +elk_dp_untyped_atomic_desc(const struct intel_device_info *devinfo, unsigned exec_size, /**< 0 for SIMD4x2 */ unsigned atomic_op, bool response_expected) @@ -687,11 +687,11 @@ brw_dp_untyped_atomic_desc(const struct intel_device_info *devinfo, SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) | SET_BITS(response_expected, 5, 5); - return brw_dp_surface_desc(devinfo, msg_type, msg_control); + return elk_dp_surface_desc(devinfo, msg_type, msg_control); } static inline uint32_t -brw_dp_untyped_atomic_float_desc(const struct intel_device_info *devinfo, +elk_dp_untyped_atomic_float_desc(const struct intel_device_info *devinfo, unsigned exec_size, unsigned atomic_op, bool response_expected) @@ -707,11 +707,11 @@ brw_dp_untyped_atomic_float_desc(const struct intel_device_info *devinfo, SET_BITS(exec_size <= 8, 4, 4) | SET_BITS(response_expected, 5, 5); - return brw_dp_surface_desc(devinfo, msg_type, msg_control); + return elk_dp_surface_desc(devinfo, msg_type, msg_control); } static inline unsigned -brw_mdc_cmask(unsigned num_channels) +elk_mdc_cmask(unsigned num_channels) { /* See also MDC_CMASK in the SKL PRM Vol 2d. */ return 0xf & (0xf << num_channels); @@ -725,7 +725,7 @@ lsc_cmask(unsigned num_channels) } static inline uint32_t -brw_dp_untyped_surface_rw_desc(const struct intel_device_info *devinfo, +elk_dp_untyped_surface_rw_desc(const struct intel_device_info *devinfo, unsigned exec_size, /**< 0 for SIMD4x2 */ unsigned num_channels, bool write) @@ -757,14 +757,14 @@ brw_dp_untyped_surface_rw_desc(const struct intel_device_info *devinfo, exec_size <= 8 ? 2 : 1; const unsigned msg_control = - SET_BITS(brw_mdc_cmask(num_channels), 3, 0) | + SET_BITS(elk_mdc_cmask(num_channels), 3, 0) | SET_BITS(simd_mode, 5, 4); - return brw_dp_surface_desc(devinfo, msg_type, msg_control); + return elk_dp_surface_desc(devinfo, msg_type, msg_control); } static inline unsigned -brw_mdc_ds(unsigned bit_size) +elk_mdc_ds(unsigned bit_size) { switch (bit_size) { case 8: @@ -779,7 +779,7 @@ brw_mdc_ds(unsigned bit_size) } static inline uint32_t -brw_dp_byte_scattered_rw_desc(const struct intel_device_info *devinfo, +elk_dp_byte_scattered_rw_desc(const struct intel_device_info *devinfo, unsigned exec_size, unsigned bit_size, bool write) @@ -794,13 +794,13 @@ brw_dp_byte_scattered_rw_desc(const struct intel_device_info *devinfo, assert(exec_size > 0); const unsigned msg_control = SET_BITS(exec_size == 16, 0, 0) | - SET_BITS(brw_mdc_ds(bit_size), 3, 2); + SET_BITS(elk_mdc_ds(bit_size), 3, 2); - return brw_dp_surface_desc(devinfo, msg_type, msg_control); + return elk_dp_surface_desc(devinfo, msg_type, msg_control); } static inline uint32_t -brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo, +elk_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo, unsigned exec_size, bool write) { @@ -811,7 +811,7 @@ brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo, if (devinfo->ver >= 6) { msg_type = GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE; } else { - msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE; + msg_type = ELK_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE; } } else { if (devinfo->ver >= 7) { @@ -819,7 +819,7 @@ brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo, } else if (devinfo->verx10 >= 45) { msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; } else { - msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; + msg_type = ELK_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; } } @@ -827,11 +827,11 @@ brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo, SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */ SET_BITS(exec_size == 16, 0, 0); - return brw_dp_surface_desc(devinfo, msg_type, msg_control); + return elk_dp_surface_desc(devinfo, msg_type, msg_control); } static inline uint32_t -brw_dp_oword_block_rw_desc(const struct intel_device_info *devinfo, +elk_dp_oword_block_rw_desc(const struct intel_device_info *devinfo, bool align_16B, unsigned num_dwords, bool write) @@ -845,13 +845,13 @@ brw_dp_oword_block_rw_desc(const struct intel_device_info *devinfo, GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ; const unsigned msg_control = - SET_BITS(BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0); + SET_BITS(ELK_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0); - return brw_dp_surface_desc(devinfo, msg_type, msg_control); + return elk_dp_surface_desc(devinfo, msg_type, msg_control); } static inline uint32_t -brw_dp_a64_untyped_surface_rw_desc(const struct intel_device_info *devinfo, +elk_dp_a64_untyped_surface_rw_desc(const struct intel_device_info *devinfo, unsigned exec_size, /**< 0 for SIMD4x2 */ unsigned num_channels, bool write) @@ -868,15 +868,15 @@ brw_dp_a64_untyped_surface_rw_desc(const struct intel_device_info *devinfo, exec_size <= 8 ? 2 : 1; const unsigned msg_control = - SET_BITS(brw_mdc_cmask(num_channels), 3, 0) | + SET_BITS(elk_mdc_cmask(num_channels), 3, 0) | SET_BITS(simd_mode, 5, 4); - return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, + return elk_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, msg_type, msg_control); } static inline uint32_t -brw_dp_a64_oword_block_rw_desc(const struct intel_device_info *devinfo, +elk_dp_a64_oword_block_rw_desc(const struct intel_device_info *devinfo, bool align_16B, unsigned num_dwords, bool write) @@ -890,9 +890,9 @@ brw_dp_a64_oword_block_rw_desc(const struct intel_device_info *devinfo, unsigned msg_control = SET_BITS(!align_16B, 4, 3) | - SET_BITS(BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0); + SET_BITS(ELK_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0); - return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, + return elk_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, msg_type, msg_control); } @@ -901,7 +901,7 @@ brw_dp_a64_oword_block_rw_desc(const struct intel_device_info *devinfo, * Skylake PRM). */ static inline uint32_t -brw_mdc_a64_ds(unsigned elems) +elk_mdc_a64_ds(unsigned elems) { switch (elems) { case 1: return 0; @@ -914,7 +914,7 @@ brw_mdc_a64_ds(unsigned elems) } static inline uint32_t -brw_dp_a64_byte_scattered_rw_desc(const struct intel_device_info *devinfo, +elk_dp_a64_byte_scattered_rw_desc(const struct intel_device_info *devinfo, unsigned exec_size, /**< 0 for SIMD4x2 */ unsigned bit_size, bool write) @@ -928,15 +928,15 @@ brw_dp_a64_byte_scattered_rw_desc(const struct intel_device_info *devinfo, const unsigned msg_control = SET_BITS(GFX8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) | - SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) | + SET_BITS(elk_mdc_a64_ds(bit_size / 8), 3, 2) | SET_BITS(exec_size == 16, 4, 4); - return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, + return elk_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, msg_type, msg_control); } static inline uint32_t -brw_dp_a64_untyped_atomic_desc(const struct intel_device_info *devinfo, +elk_dp_a64_untyped_atomic_desc(const struct intel_device_info *devinfo, ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */ unsigned bit_size, unsigned atomic_op, @@ -956,12 +956,12 @@ brw_dp_a64_untyped_atomic_desc(const struct intel_device_info *devinfo, SET_BITS(bit_size == 64, 4, 4) | SET_BITS(response_expected, 5, 5); - return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, + return elk_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, msg_type, msg_control); } static inline uint32_t -brw_dp_a64_untyped_atomic_float_desc(const struct intel_device_info *devinfo, +elk_dp_a64_untyped_atomic_float_desc(const struct intel_device_info *devinfo, ASSERTED unsigned exec_size, unsigned bit_size, unsigned atomic_op, @@ -981,12 +981,12 @@ brw_dp_a64_untyped_atomic_float_desc(const struct intel_device_info *devinfo, SET_BITS(atomic_op, 1, 0) | SET_BITS(response_expected, 5, 5); - return brw_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, + return elk_dp_desc(devinfo, GFX8_BTI_STATELESS_NON_COHERENT, msg_type, msg_control); } static inline uint32_t -brw_dp_typed_atomic_desc(const struct intel_device_info *devinfo, +elk_dp_typed_atomic_desc(const struct intel_device_info *devinfo, unsigned exec_size, unsigned exec_group, unsigned atomic_op, @@ -1015,11 +1015,11 @@ brw_dp_typed_atomic_desc(const struct intel_device_info *devinfo, SET_BITS(high_sample_mask, 4, 4) | SET_BITS(response_expected, 5, 5); - return brw_dp_surface_desc(devinfo, msg_type, msg_control); + return elk_dp_surface_desc(devinfo, msg_type, msg_control); } static inline uint32_t -brw_dp_typed_surface_rw_desc(const struct intel_device_info *devinfo, +elk_dp_typed_surface_rw_desc(const struct intel_device_info *devinfo, unsigned exec_size, unsigned exec_group, unsigned num_channels, @@ -1054,7 +1054,7 @@ brw_dp_typed_surface_rw_desc(const struct intel_device_info *devinfo, 1 + ((exec_group / 8) % 2); msg_control = - SET_BITS(brw_mdc_cmask(num_channels), 3, 0) | + SET_BITS(elk_mdc_cmask(num_channels), 3, 0) | SET_BITS(slot_group, 5, 4); } else { /* SIMD4x2 typed surface R/W messages only exist on HSW+ */ @@ -1062,15 +1062,15 @@ brw_dp_typed_surface_rw_desc(const struct intel_device_info *devinfo, const unsigned slot_group = ((exec_group / 8) % 2); msg_control = - SET_BITS(brw_mdc_cmask(num_channels), 3, 0) | + SET_BITS(elk_mdc_cmask(num_channels), 3, 0) | SET_BITS(slot_group, 5, 5); } - return brw_dp_surface_desc(devinfo, msg_type, msg_control); + return elk_dp_surface_desc(devinfo, msg_type, msg_control); } static inline uint32_t -brw_fb_desc(const struct intel_device_info *devinfo, +elk_fb_desc(const struct intel_device_info *devinfo, unsigned binding_table_index, unsigned msg_type, unsigned msg_control) @@ -1090,14 +1090,14 @@ brw_fb_desc(const struct intel_device_info *devinfo, } static inline unsigned -brw_fb_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo, +elk_fb_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { return GET_BITS(desc, 7, 0); } static inline uint32_t -brw_fb_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) +elk_fb_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver >= 6); if (devinfo->ver >= 7) @@ -1107,7 +1107,7 @@ brw_fb_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) } static inline unsigned -brw_fb_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) +elk_fb_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver >= 6); if (devinfo->ver >= 7) @@ -1117,7 +1117,7 @@ brw_fb_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) } static inline uint32_t -brw_fb_read_desc(const struct intel_device_info *devinfo, +elk_fb_read_desc(const struct intel_device_info *devinfo, unsigned binding_table_index, unsigned msg_control, unsigned exec_size, @@ -1126,14 +1126,14 @@ brw_fb_read_desc(const struct intel_device_info *devinfo, assert(devinfo->ver >= 9); assert(exec_size == 8 || exec_size == 16); - return brw_fb_desc(devinfo, binding_table_index, + return elk_fb_desc(devinfo, binding_table_index, GFX9_DATAPORT_RC_RENDER_TARGET_READ, msg_control) | SET_BITS(per_sample, 13, 13) | SET_BITS(exec_size == 8, 8, 8) /* Render Target Message Subtype */; } static inline uint32_t -brw_fb_write_desc(const struct intel_device_info *devinfo, +elk_fb_write_desc(const struct intel_device_info *devinfo, unsigned binding_table_index, unsigned msg_control, bool last_render_target, @@ -1142,12 +1142,12 @@ brw_fb_write_desc(const struct intel_device_info *devinfo, const unsigned msg_type = devinfo->ver >= 6 ? GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE : - BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE; + ELK_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE; assert(devinfo->ver >= 10 || !coarse_write); if (devinfo->ver >= 6) { - return brw_fb_desc(devinfo, binding_table_index, msg_type, msg_control) | + return elk_fb_desc(devinfo, binding_table_index, msg_type, msg_control) | SET_BITS(last_render_target, 12, 12) | SET_BITS(coarse_write, 18, 18); } else { @@ -1159,27 +1159,27 @@ brw_fb_write_desc(const struct intel_device_info *devinfo, } static inline unsigned -brw_fb_write_desc_msg_type(const struct intel_device_info *devinfo, +elk_fb_write_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 6) - return brw_fb_desc_msg_type(devinfo, desc); + return elk_fb_desc_msg_type(devinfo, desc); else return GET_BITS(desc, 14, 12); } static inline unsigned -brw_fb_write_desc_msg_control(const struct intel_device_info *devinfo, +elk_fb_write_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 6) - return brw_fb_desc_msg_control(devinfo, desc); + return elk_fb_desc_msg_control(devinfo, desc); else return GET_BITS(desc, 11, 8); } static inline bool -brw_fb_write_desc_last_render_target(const struct intel_device_info *devinfo, +elk_fb_write_desc_last_render_target(const struct intel_device_info *devinfo, uint32_t desc) { if (devinfo->ver >= 6) @@ -1189,7 +1189,7 @@ brw_fb_write_desc_last_render_target(const struct intel_device_info *devinfo, } static inline bool -brw_fb_write_desc_write_commit(const struct intel_device_info *devinfo, +elk_fb_write_desc_write_commit(const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver <= 6); @@ -1200,7 +1200,7 @@ brw_fb_write_desc_write_commit(const struct intel_device_info *devinfo, } static inline bool -brw_fb_write_desc_coarse_write(const struct intel_device_info *devinfo, +elk_fb_write_desc_coarse_write(const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->ver >= 10); @@ -1208,26 +1208,26 @@ brw_fb_write_desc_coarse_write(const struct intel_device_info *devinfo, } static inline bool -lsc_opcode_has_cmask(enum lsc_opcode opcode) +elk_lsc_opcode_has_cmask(enum elk_lsc_opcode opcode) { return opcode == LSC_OP_LOAD_CMASK || opcode == LSC_OP_STORE_CMASK; } static inline bool -lsc_opcode_has_transpose(enum lsc_opcode opcode) +elk_lsc_opcode_has_transpose(enum elk_lsc_opcode opcode) { return opcode == LSC_OP_LOAD || opcode == LSC_OP_STORE; } static inline bool -lsc_opcode_is_store(enum lsc_opcode opcode) +elk_lsc_opcode_is_store(enum elk_lsc_opcode opcode) { return opcode == LSC_OP_STORE || opcode == LSC_OP_STORE_CMASK; } static inline bool -lsc_opcode_is_atomic(enum lsc_opcode opcode) +elk_lsc_opcode_is_atomic(enum elk_lsc_opcode opcode) { switch (opcode) { case LSC_OP_ATOMIC_INC: @@ -1257,7 +1257,7 @@ lsc_opcode_is_atomic(enum lsc_opcode opcode) } static inline bool -lsc_opcode_is_atomic_float(enum lsc_opcode opcode) +elk_lsc_opcode_is_atomic_float(enum elk_lsc_opcode opcode) { switch (opcode) { case LSC_OP_ATOMIC_FADD: @@ -1275,7 +1275,7 @@ lsc_opcode_is_atomic_float(enum lsc_opcode opcode) static inline unsigned lsc_op_num_data_values(unsigned _op) { - enum lsc_opcode op = (enum lsc_opcode) _op; + enum elk_lsc_opcode op = (enum elk_lsc_opcode) _op; switch (op) { case LSC_OP_ATOMIC_CMPXCHG: @@ -1296,44 +1296,44 @@ lsc_op_num_data_values(unsigned _op) static inline unsigned lsc_op_to_legacy_atomic(unsigned _op) { - enum lsc_opcode op = (enum lsc_opcode) _op; + enum elk_lsc_opcode op = (enum elk_lsc_opcode) _op; switch (op) { case LSC_OP_ATOMIC_INC: - return BRW_AOP_INC; + return ELK_AOP_INC; case LSC_OP_ATOMIC_DEC: - return BRW_AOP_DEC; + return ELK_AOP_DEC; case LSC_OP_ATOMIC_STORE: - return BRW_AOP_MOV; + return ELK_AOP_MOV; case LSC_OP_ATOMIC_ADD: - return BRW_AOP_ADD; + return ELK_AOP_ADD; case LSC_OP_ATOMIC_SUB: - return BRW_AOP_SUB; + return ELK_AOP_SUB; case LSC_OP_ATOMIC_MIN: - return BRW_AOP_IMIN; + return ELK_AOP_IMIN; case LSC_OP_ATOMIC_MAX: - return BRW_AOP_IMAX; + return ELK_AOP_IMAX; case LSC_OP_ATOMIC_UMIN: - return BRW_AOP_UMIN; + return ELK_AOP_UMIN; case LSC_OP_ATOMIC_UMAX: - return BRW_AOP_UMAX; + return ELK_AOP_UMAX; case LSC_OP_ATOMIC_CMPXCHG: - return BRW_AOP_CMPWR; + return ELK_AOP_CMPWR; case LSC_OP_ATOMIC_FADD: - return BRW_AOP_FADD; + return ELK_AOP_FADD; case LSC_OP_ATOMIC_FMIN: - return BRW_AOP_FMIN; + return ELK_AOP_FMIN; case LSC_OP_ATOMIC_FMAX: - return BRW_AOP_FMAX; + return ELK_AOP_FMAX; case LSC_OP_ATOMIC_FCMPXCHG: - return BRW_AOP_FCMPWR; + return ELK_AOP_FCMPWR; case LSC_OP_ATOMIC_AND: - return BRW_AOP_AND; + return ELK_AOP_AND; case LSC_OP_ATOMIC_OR: - return BRW_AOP_OR; + return ELK_AOP_OR; case LSC_OP_ATOMIC_XOR: - return BRW_AOP_XOR; - /* No LSC op maps to BRW_AOP_PREDEC */ + return ELK_AOP_XOR; + /* No LSC op maps to ELK_AOP_PREDEC */ case LSC_OP_ATOMIC_LOAD: case LSC_OP_ATOMIC_FSUB: unreachable("no corresponding legacy atomic operation"); @@ -1416,7 +1416,7 @@ lsc_vect_size(unsigned vect_size) static inline uint32_t lsc_msg_desc_wcmask(UNUSED const struct intel_device_info *devinfo, - enum lsc_opcode opcode, unsigned simd_size, + enum elk_lsc_opcode opcode, unsigned simd_size, enum lsc_addr_surface_type addr_type, enum lsc_addr_size addr_sz, unsigned num_coordinates, enum lsc_data_size data_sz, unsigned num_channels, @@ -1432,7 +1432,7 @@ lsc_msg_desc_wcmask(UNUSED const struct intel_device_info *devinfo, DIV_ROUND_UP(lsc_addr_size_bytes(addr_sz) * num_coordinates * simd_size, reg_unit(devinfo) * REG_SIZE); - assert(!transpose || lsc_opcode_has_transpose(opcode)); + assert(!transpose || elk_lsc_opcode_has_transpose(opcode)); unsigned msg_desc = SET_BITS(opcode, 5, 0) | @@ -1444,7 +1444,7 @@ lsc_msg_desc_wcmask(UNUSED const struct intel_device_info *devinfo, SET_BITS(src0_length, 28, 25) | SET_BITS(addr_type, 30, 29); - if (lsc_opcode_has_cmask(opcode)) + if (elk_lsc_opcode_has_cmask(opcode)) msg_desc |= SET_BITS(cmask ? cmask : lsc_cmask(num_channels), 15, 12); else msg_desc |= SET_BITS(lsc_vect_size(num_channels), 14, 12); @@ -1454,7 +1454,7 @@ lsc_msg_desc_wcmask(UNUSED const struct intel_device_info *devinfo, static inline uint32_t lsc_msg_desc(UNUSED const struct intel_device_info *devinfo, - enum lsc_opcode opcode, unsigned simd_size, + enum elk_lsc_opcode opcode, unsigned simd_size, enum lsc_addr_surface_type addr_type, enum lsc_addr_size addr_sz, unsigned num_coordinates, enum lsc_data_size data_sz, unsigned num_channels, @@ -1465,12 +1465,12 @@ lsc_msg_desc(UNUSED const struct intel_device_info *devinfo, has_dest, 0); } -static inline enum lsc_opcode +static inline enum elk_lsc_opcode lsc_msg_desc_opcode(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->has_lsc); - return (enum lsc_opcode) GET_BITS(desc, 5, 0); + return (enum elk_lsc_opcode) GET_BITS(desc, 5, 0); } static inline enum lsc_addr_size @@ -1494,7 +1494,7 @@ lsc_msg_desc_vect_size(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->has_lsc); - assert(!lsc_opcode_has_cmask(lsc_msg_desc_opcode(devinfo, desc))); + assert(!elk_lsc_opcode_has_cmask(lsc_msg_desc_opcode(devinfo, desc))); return (enum lsc_vect_size) GET_BITS(desc, 14, 12); } @@ -1503,7 +1503,7 @@ lsc_msg_desc_cmask(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { assert(devinfo->has_lsc); - assert(lsc_opcode_has_cmask(lsc_msg_desc_opcode(devinfo, desc))); + assert(elk_lsc_opcode_has_cmask(lsc_msg_desc_opcode(devinfo, desc))); return (enum lsc_cmask) GET_BITS(desc, 15, 12); } @@ -1635,21 +1635,21 @@ lsc_bss_ex_desc_index(const struct intel_device_info *devinfo, } static inline uint32_t -brw_mdc_sm2(unsigned exec_size) +elk_mdc_sm2(unsigned exec_size) { assert(exec_size == 8 || exec_size == 16); return exec_size > 8; } static inline uint32_t -brw_mdc_sm2_exec_size(uint32_t sm2) +elk_mdc_sm2_exec_size(uint32_t sm2) { assert(sm2 <= 1); return 8 << sm2; } static inline uint32_t -brw_btd_spawn_desc(ASSERTED const struct intel_device_info *devinfo, +elk_btd_spawn_desc(ASSERTED const struct intel_device_info *devinfo, unsigned exec_size, unsigned msg_type) { assert(devinfo->has_ray_tracing); @@ -1657,25 +1657,25 @@ brw_btd_spawn_desc(ASSERTED const struct intel_device_info *devinfo, return SET_BITS(0, 19, 19) | /* No header */ SET_BITS(msg_type, 17, 14) | - SET_BITS(brw_mdc_sm2(exec_size), 8, 8); + SET_BITS(elk_mdc_sm2(exec_size), 8, 8); } static inline uint32_t -brw_btd_spawn_msg_type(UNUSED const struct intel_device_info *devinfo, +elk_btd_spawn_msg_type(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { return GET_BITS(desc, 17, 14); } static inline uint32_t -brw_btd_spawn_exec_size(UNUSED const struct intel_device_info *devinfo, +elk_btd_spawn_exec_size(UNUSED const struct intel_device_info *devinfo, uint32_t desc) { - return brw_mdc_sm2_exec_size(GET_BITS(desc, 8, 8)); + return elk_mdc_sm2_exec_size(GET_BITS(desc, 8, 8)); } static inline uint32_t -brw_rt_trace_ray_desc(ASSERTED const struct intel_device_info *devinfo, +elk_rt_trace_ray_desc(ASSERTED const struct intel_device_info *devinfo, unsigned exec_size) { assert(devinfo->has_ray_tracing); @@ -1683,7 +1683,7 @@ brw_rt_trace_ray_desc(ASSERTED const struct intel_device_info *devinfo, return SET_BITS(0, 19, 19) | /* No header */ SET_BITS(0, 17, 14) | /* Message type */ - SET_BITS(brw_mdc_sm2(exec_size), 8, 8); + SET_BITS(elk_mdc_sm2(exec_size), 8, 8); } /** @@ -1691,7 +1691,7 @@ brw_rt_trace_ray_desc(ASSERTED const struct intel_device_info *devinfo, * interpolator function controls. */ static inline uint32_t -brw_pixel_interp_desc(UNUSED const struct intel_device_info *devinfo, +elk_pixel_interp_desc(UNUSED const struct intel_device_info *devinfo, unsigned msg_type, bool noperspective, bool coarse_pixel_rate, @@ -1710,11 +1710,11 @@ brw_pixel_interp_desc(UNUSED const struct intel_device_info *devinfo, SET_BITS(simd_mode, 16, 16)); } -void brw_urb_WRITE(struct brw_codegen *p, - struct brw_reg dest, +void elk_urb_WRITE(struct elk_codegen *p, + struct elk_reg dest, unsigned msg_reg_nr, - struct brw_reg src0, - enum brw_urb_write_flags flags, + struct elk_reg src0, + enum elk_urb_write_flags flags, unsigned msg_length, unsigned response_length, unsigned offset, @@ -1726,46 +1726,46 @@ void brw_urb_WRITE(struct brw_codegen *p, * address register using an OR instruction. */ void -brw_send_indirect_message(struct brw_codegen *p, +elk_send_indirect_message(struct elk_codegen *p, unsigned sfid, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg desc, + struct elk_reg dst, + struct elk_reg payload, + struct elk_reg desc, unsigned desc_imm, bool eot); void -brw_send_indirect_split_message(struct brw_codegen *p, +elk_send_indirect_split_message(struct elk_codegen *p, unsigned sfid, - struct brw_reg dst, - struct brw_reg payload0, - struct brw_reg payload1, - struct brw_reg desc, + struct elk_reg dst, + struct elk_reg payload0, + struct elk_reg payload1, + struct elk_reg desc, unsigned desc_imm, - struct brw_reg ex_desc, + struct elk_reg ex_desc, unsigned ex_desc_imm, bool ex_desc_scratch, bool ex_bso, bool eot); -void brw_ff_sync(struct brw_codegen *p, - struct brw_reg dest, +void elk_ff_sync(struct elk_codegen *p, + struct elk_reg dest, unsigned msg_reg_nr, - struct brw_reg src0, + struct elk_reg src0, bool allocate, unsigned response_length, bool eot); -void brw_svb_write(struct brw_codegen *p, - struct brw_reg dest, +void elk_svb_write(struct elk_codegen *p, + struct elk_reg dest, unsigned msg_reg_nr, - struct brw_reg src0, + struct elk_reg src0, unsigned binding_table_index, bool send_commit_msg); -brw_inst *brw_fb_WRITE(struct brw_codegen *p, - struct brw_reg payload, - struct brw_reg implied_header, +elk_inst *elk_fb_WRITE(struct elk_codegen *p, + struct elk_reg payload, + struct elk_reg implied_header, unsigned msg_control, unsigned binding_table_index, unsigned msg_length, @@ -1774,18 +1774,18 @@ brw_inst *brw_fb_WRITE(struct brw_codegen *p, bool last_render_target, bool header_present); -brw_inst *gfx9_fb_READ(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg payload, +elk_inst *elk_gfx9_fb_READ(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg payload, unsigned binding_table_index, unsigned msg_length, unsigned response_length, bool per_sample); -void brw_SAMPLE(struct brw_codegen *p, - struct brw_reg dest, +void elk_SAMPLE(struct elk_codegen *p, + struct elk_reg dest, unsigned msg_reg_nr, - struct brw_reg src0, + struct elk_reg src0, unsigned binding_table_index, unsigned sampler, unsigned msg_type, @@ -1795,44 +1795,44 @@ void brw_SAMPLE(struct brw_codegen *p, unsigned simd_mode, unsigned return_format); -void brw_adjust_sampler_state_pointer(struct brw_codegen *p, - struct brw_reg header, - struct brw_reg sampler_index); +void elk_adjust_sampler_state_pointer(struct elk_codegen *p, + struct elk_reg header, + struct elk_reg sampler_index); -void gfx4_math(struct brw_codegen *p, - struct brw_reg dest, +void elk_gfx4_math(struct elk_codegen *p, + struct elk_reg dest, unsigned function, unsigned msg_reg_nr, - struct brw_reg src, + struct elk_reg src, unsigned precision ); -void gfx6_math(struct brw_codegen *p, - struct brw_reg dest, +void elk_gfx6_math(struct elk_codegen *p, + struct elk_reg dest, unsigned function, - struct brw_reg src0, - struct brw_reg src1); + struct elk_reg src0, + struct elk_reg src1); -void brw_oword_block_read(struct brw_codegen *p, - struct brw_reg dest, - struct brw_reg mrf, +void elk_oword_block_read(struct elk_codegen *p, + struct elk_reg dest, + struct elk_reg mrf, uint32_t offset, uint32_t bind_table_index); -unsigned brw_scratch_surface_idx(const struct brw_codegen *p); +unsigned elk_scratch_surface_idx(const struct elk_codegen *p); -void brw_oword_block_read_scratch(struct brw_codegen *p, - struct brw_reg dest, - struct brw_reg mrf, +void elk_oword_block_read_scratch(struct elk_codegen *p, + struct elk_reg dest, + struct elk_reg mrf, int num_regs, unsigned offset); -void brw_oword_block_write_scratch(struct brw_codegen *p, - struct brw_reg mrf, +void elk_oword_block_write_scratch(struct elk_codegen *p, + struct elk_reg mrf, int num_regs, unsigned offset); -void gfx7_block_read_scratch(struct brw_codegen *p, - struct brw_reg dest, +void elk_gfx7_block_read_scratch(struct elk_codegen *p, + struct elk_reg dest, int num_regs, unsigned offset); @@ -1844,7 +1844,7 @@ void gfx7_block_read_scratch(struct brw_codegen *p, * instruction. */ static inline unsigned -brw_jump_scale(const struct intel_device_info *devinfo) +elk_jump_scale(const struct intel_device_info *devinfo) { /* Broadwell measures jump targets in bytes. */ if (devinfo->ver >= 8) @@ -1860,214 +1860,214 @@ brw_jump_scale(const struct intel_device_info *devinfo) return 1; } -void brw_barrier(struct brw_codegen *p, struct brw_reg src); +void elk_barrier(struct elk_codegen *p, struct elk_reg src); /* If/else/endif. Works by manipulating the execution flags on each * channel. */ -brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size); -brw_inst *gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, - struct brw_reg src0, struct brw_reg src1); +elk_inst *elk_IF(struct elk_codegen *p, unsigned execute_size); +elk_inst *elk_gfx6_IF(struct elk_codegen *p, enum elk_conditional_mod conditional, + struct elk_reg src0, struct elk_reg src1); -void brw_ELSE(struct brw_codegen *p); -void brw_ENDIF(struct brw_codegen *p); +void elk_ELSE(struct elk_codegen *p); +void elk_ENDIF(struct elk_codegen *p); /* DO/WHILE loops: */ -brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size); +elk_inst *elk_DO(struct elk_codegen *p, unsigned execute_size); -brw_inst *brw_WHILE(struct brw_codegen *p); +elk_inst *elk_WHILE(struct elk_codegen *p); -brw_inst *brw_BREAK(struct brw_codegen *p); -brw_inst *brw_CONT(struct brw_codegen *p); -brw_inst *brw_HALT(struct brw_codegen *p); +elk_inst *elk_BREAK(struct elk_codegen *p); +elk_inst *elk_CONT(struct elk_codegen *p); +elk_inst *elk_HALT(struct elk_codegen *p); /* Forward jumps: */ -void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx); +void elk_land_fwd_jump(struct elk_codegen *p, int jmp_insn_idx); -brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index, +elk_inst *elk_JMPI(struct elk_codegen *p, struct elk_reg index, unsigned predicate_control); -void brw_NOP(struct brw_codegen *p); +void elk_NOP(struct elk_codegen *p); -void brw_WAIT(struct brw_codegen *p); +void elk_WAIT(struct elk_codegen *p); -void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func); +void elk_SYNC(struct elk_codegen *p, enum tgl_sync_function func); /* Special case: there is never a destination, execution size will be * taken from src0: */ -void brw_CMP(struct brw_codegen *p, - struct brw_reg dest, +void elk_CMP(struct elk_codegen *p, + struct elk_reg dest, unsigned conditional, - struct brw_reg src0, - struct brw_reg src1); + struct elk_reg src0, + struct elk_reg src1); -void brw_CMPN(struct brw_codegen *p, - struct brw_reg dest, +void elk_CMPN(struct elk_codegen *p, + struct elk_reg dest, unsigned conditional, - struct brw_reg src0, - struct brw_reg src1); + struct elk_reg src0, + struct elk_reg src1); -brw_inst *brw_DPAS(struct brw_codegen *p, enum gfx12_systolic_depth sdepth, - unsigned rcount, struct brw_reg dest, struct brw_reg src0, - struct brw_reg src1, struct brw_reg src2); +elk_inst *elk_DPAS(struct elk_codegen *p, enum elk_gfx12_systolic_depth sdepth, + unsigned rcount, struct elk_reg dest, struct elk_reg src0, + struct elk_reg src1, struct elk_reg src2); void -brw_untyped_atomic(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg surface, +elk_untyped_atomic(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg payload, + struct elk_reg surface, unsigned atomic_op, unsigned msg_length, bool response_expected, bool header_present); void -brw_untyped_surface_read(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg surface, +elk_untyped_surface_read(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg payload, + struct elk_reg surface, unsigned msg_length, unsigned num_channels); void -brw_untyped_surface_write(struct brw_codegen *p, - struct brw_reg payload, - struct brw_reg surface, +elk_untyped_surface_write(struct elk_codegen *p, + struct elk_reg payload, + struct elk_reg surface, unsigned msg_length, unsigned num_channels, bool header_present); void -brw_memory_fence(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src, - enum opcode send_op, - enum brw_message_target sfid, +elk_memory_fence(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src, + enum elk_opcode send_op, + enum elk_message_target sfid, uint32_t desc, bool commit_enable, unsigned bti); void -brw_pixel_interpolator_query(struct brw_codegen *p, - struct brw_reg dest, - struct brw_reg mrf, +elk_pixel_interpolator_query(struct elk_codegen *p, + struct elk_reg dest, + struct elk_reg mrf, bool noperspective, bool coarse_pixel_rate, unsigned mode, - struct brw_reg data, + struct elk_reg data, unsigned msg_length, unsigned response_length); void -brw_find_live_channel(struct brw_codegen *p, - struct brw_reg dst, +elk_find_live_channel(struct elk_codegen *p, + struct elk_reg dst, bool last); void -brw_broadcast(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg idx); +elk_broadcast(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src, + struct elk_reg idx); void -brw_float_controls_mode(struct brw_codegen *p, +elk_float_controls_mode(struct elk_codegen *p, unsigned mode, unsigned mask); void -brw_update_reloc_imm(const struct brw_isa_info *isa, - brw_inst *inst, +elk_update_reloc_imm(const struct elk_isa_info *isa, + elk_inst *inst, uint32_t value); void -brw_MOV_reloc_imm(struct brw_codegen *p, - struct brw_reg dst, - enum brw_reg_type src_type, +elk_MOV_reloc_imm(struct elk_codegen *p, + struct elk_reg dst, + enum elk_reg_type src_type, uint32_t id); unsigned -brw_num_sources_from_inst(const struct brw_isa_info *isa, - const brw_inst *inst); +elk_num_sources_from_inst(const struct elk_isa_info *isa, + const elk_inst *inst); /*********************************************************************** - * brw_eu_util.c: + * elk_eu_util.c: */ -void brw_copy_indirect_to_indirect(struct brw_codegen *p, - struct brw_indirect dst_ptr, - struct brw_indirect src_ptr, +void elk_copy_indirect_to_indirect(struct elk_codegen *p, + struct elk_indirect dst_ptr, + struct elk_indirect src_ptr, unsigned count); -void brw_copy_from_indirect(struct brw_codegen *p, - struct brw_reg dst, - struct brw_indirect ptr, +void elk_copy_from_indirect(struct elk_codegen *p, + struct elk_reg dst, + struct elk_indirect ptr, unsigned count); -void brw_copy4(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src, +void elk_copy4(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src, unsigned count); -void brw_copy8(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src, +void elk_copy8(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src, unsigned count); -void brw_math_invert( struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src); +void elk_math_invert( struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src); -void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg); +void elk_set_src1(struct elk_codegen *p, elk_inst *insn, struct elk_reg reg); -void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn, +void elk_set_desc_ex(struct elk_codegen *p, elk_inst *insn, unsigned desc, unsigned ex_desc); static inline void -brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc) +elk_set_desc(struct elk_codegen *p, elk_inst *insn, unsigned desc) { - brw_set_desc_ex(p, insn, desc, 0); + elk_set_desc_ex(p, insn, desc, 0); } -void brw_set_uip_jip(struct brw_codegen *p, int start_offset); +void elk_set_uip_jip(struct elk_codegen *p, int start_offset); -enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod); -enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod); +enum elk_conditional_mod elk_negate_cmod(enum elk_conditional_mod cmod); +enum elk_conditional_mod elk_swap_cmod(enum elk_conditional_mod cmod); -/* brw_eu_compact.c */ -void brw_compact_instructions(struct brw_codegen *p, int start_offset, - struct disasm_info *disasm); -void brw_uncompact_instruction(const struct brw_isa_info *isa, - brw_inst *dst, brw_compact_inst *src); -bool brw_try_compact_instruction(const struct brw_isa_info *isa, - brw_compact_inst *dst, const brw_inst *src); +/* elk_eu_compact.c */ +void elk_compact_instructions(struct elk_codegen *p, int start_offset, + struct elk_disasm_info *disasm); +void elk_uncompact_instruction(const struct elk_isa_info *isa, + elk_inst *dst, elk_compact_inst *src); +bool elk_try_compact_instruction(const struct elk_isa_info *isa, + elk_compact_inst *dst, const elk_inst *src); -void brw_debug_compact_uncompact(const struct brw_isa_info *isa, - brw_inst *orig, brw_inst *uncompacted); +void elk_debug_compact_uncompact(const struct elk_isa_info *isa, + elk_inst *orig, elk_inst *uncompacted); -/* brw_eu_validate.c */ -bool brw_validate_instruction(const struct brw_isa_info *isa, - const brw_inst *inst, int offset, +/* elk_eu_validate.c */ +bool elk_validate_instruction(const struct elk_isa_info *isa, + const elk_inst *inst, int offset, unsigned inst_size, - struct disasm_info *disasm); -bool brw_validate_instructions(const struct brw_isa_info *isa, + struct elk_disasm_info *disasm); +bool elk_validate_instructions(const struct elk_isa_info *isa, const void *assembly, int start_offset, int end_offset, - struct disasm_info *disasm); + struct elk_disasm_info *disasm); static inline int next_offset(const struct intel_device_info *devinfo, void *store, int offset) { - brw_inst *insn = (brw_inst *)((char *)store + offset); + elk_inst *insn = (elk_inst *)((char *)store + offset); - if (brw_inst_cmpt_control(devinfo, insn)) + if (elk_inst_cmpt_control(devinfo, insn)) return offset + 8; else return offset + 16; } /** Maximum SEND message length */ -#define BRW_MAX_MSG_LENGTH 15 +#define ELK_MAX_MSG_LENGTH 15 /** First MRF register used by pull loads */ #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13) diff --git a/src/intel/compiler/elk/elk_eu_compact.c b/src/intel/compiler/elk/elk_eu_compact.c index df8ba621aae..57b5f6e3bd3 100644 --- a/src/intel/compiler/elk/elk_eu_compact.c +++ b/src/intel/compiler/elk/elk_eu_compact.c @@ -1299,7 +1299,7 @@ static const uint32_t xe2_3src_subreg_table[32] = { }; struct compaction_state { - const struct brw_isa_info *isa; + const struct elk_isa_info *isa; const uint32_t *control_index_table; const uint32_t *datatype_table; const uint16_t *subreg_table; @@ -1308,56 +1308,56 @@ struct compaction_state { }; static void compaction_state_init(struct compaction_state *c, - const struct brw_isa_info *isa); + const struct elk_isa_info *isa); static bool set_control_index(const struct compaction_state *c, - brw_compact_inst *dst, const brw_inst *src) + elk_compact_inst *dst, const elk_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; uint32_t uncompacted; /* 17b/G45; 19b/IVB+; 21b/TGL+ */ if (devinfo->ver >= 20) { - uncompacted = (brw_inst_bits(src, 95, 92) << 14) | /* 4b */ - (brw_inst_bits(src, 34, 34) << 13) | /* 1b */ - (brw_inst_bits(src, 32, 32) << 12) | /* 1b */ - (brw_inst_bits(src, 31, 31) << 11) | /* 1b */ - (brw_inst_bits(src, 28, 28) << 10) | /* 1b */ - (brw_inst_bits(src, 27, 26) << 8) | /* 2b */ - (brw_inst_bits(src, 25, 24) << 6) | /* 2b */ - (brw_inst_bits(src, 23, 21) << 3) | /* 3b */ - (brw_inst_bits(src, 20, 18)); /* 3b */ + uncompacted = (elk_inst_bits(src, 95, 92) << 14) | /* 4b */ + (elk_inst_bits(src, 34, 34) << 13) | /* 1b */ + (elk_inst_bits(src, 32, 32) << 12) | /* 1b */ + (elk_inst_bits(src, 31, 31) << 11) | /* 1b */ + (elk_inst_bits(src, 28, 28) << 10) | /* 1b */ + (elk_inst_bits(src, 27, 26) << 8) | /* 2b */ + (elk_inst_bits(src, 25, 24) << 6) | /* 2b */ + (elk_inst_bits(src, 23, 21) << 3) | /* 3b */ + (elk_inst_bits(src, 20, 18)); /* 3b */ } else if (devinfo->ver >= 12) { - uncompacted = (brw_inst_bits(src, 95, 92) << 17) | /* 4b */ - (brw_inst_bits(src, 34, 34) << 16) | /* 1b */ - (brw_inst_bits(src, 33, 33) << 15) | /* 1b */ - (brw_inst_bits(src, 32, 32) << 14) | /* 1b */ - (brw_inst_bits(src, 31, 31) << 13) | /* 1b */ - (brw_inst_bits(src, 28, 28) << 12) | /* 1b */ - (brw_inst_bits(src, 27, 24) << 8) | /* 4b */ - (brw_inst_bits(src, 23, 22) << 6) | /* 2b */ - (brw_inst_bits(src, 21, 19) << 3) | /* 3b */ - (brw_inst_bits(src, 18, 16)); /* 3b */ + uncompacted = (elk_inst_bits(src, 95, 92) << 17) | /* 4b */ + (elk_inst_bits(src, 34, 34) << 16) | /* 1b */ + (elk_inst_bits(src, 33, 33) << 15) | /* 1b */ + (elk_inst_bits(src, 32, 32) << 14) | /* 1b */ + (elk_inst_bits(src, 31, 31) << 13) | /* 1b */ + (elk_inst_bits(src, 28, 28) << 12) | /* 1b */ + (elk_inst_bits(src, 27, 24) << 8) | /* 4b */ + (elk_inst_bits(src, 23, 22) << 6) | /* 2b */ + (elk_inst_bits(src, 21, 19) << 3) | /* 3b */ + (elk_inst_bits(src, 18, 16)); /* 3b */ } else if (devinfo->ver >= 8) { - uncompacted = (brw_inst_bits(src, 33, 31) << 16) | /* 3b */ - (brw_inst_bits(src, 23, 12) << 4) | /* 12b */ - (brw_inst_bits(src, 10, 9) << 2) | /* 2b */ - (brw_inst_bits(src, 34, 34) << 1) | /* 1b */ - (brw_inst_bits(src, 8, 8)); /* 1b */ + uncompacted = (elk_inst_bits(src, 33, 31) << 16) | /* 3b */ + (elk_inst_bits(src, 23, 12) << 4) | /* 12b */ + (elk_inst_bits(src, 10, 9) << 2) | /* 2b */ + (elk_inst_bits(src, 34, 34) << 1) | /* 1b */ + (elk_inst_bits(src, 8, 8)); /* 1b */ } else { - uncompacted = (brw_inst_bits(src, 31, 31) << 16) | /* 1b */ - (brw_inst_bits(src, 23, 8)); /* 16b */ + uncompacted = (elk_inst_bits(src, 31, 31) << 16) | /* 1b */ + (elk_inst_bits(src, 23, 8)); /* 16b */ /* On gfx7, the flag register and subregister numbers are integrated into * the control index. */ if (devinfo->ver == 7) - uncompacted |= brw_inst_bits(src, 90, 89) << 17; /* 2b */ + uncompacted |= elk_inst_bits(src, 90, 89) << 17; /* 2b */ } for (int i = 0; i < 32; i++) { if (c->control_index_table[i] == uncompacted) { - brw_compact_inst_set_control_index(devinfo, dst, i); + elk_compact_inst_set_control_index(devinfo, dst, i); return true; } } @@ -1366,41 +1366,41 @@ set_control_index(const struct compaction_state *c, } static bool -set_datatype_index(const struct compaction_state *c, brw_compact_inst *dst, - const brw_inst *src, bool is_immediate) +set_datatype_index(const struct compaction_state *c, elk_compact_inst *dst, + const elk_inst *src, bool is_immediate) { const struct intel_device_info *devinfo = c->isa->devinfo; uint32_t uncompacted; /* 18b/G45+; 21b/BDW+; 20b/TGL+ */ if (devinfo->ver >= 12) { - uncompacted = (brw_inst_bits(src, 91, 88) << 15) | /* 4b */ - (brw_inst_bits(src, 66, 66) << 14) | /* 1b */ - (brw_inst_bits(src, 50, 50) << 13) | /* 1b */ - (brw_inst_bits(src, 49, 48) << 11) | /* 2b */ - (brw_inst_bits(src, 47, 47) << 10) | /* 1b */ - (brw_inst_bits(src, 46, 46) << 9) | /* 1b */ - (brw_inst_bits(src, 43, 40) << 5) | /* 4b */ - (brw_inst_bits(src, 39, 36) << 1) | /* 4b */ - (brw_inst_bits(src, 35, 35)); /* 1b */ + uncompacted = (elk_inst_bits(src, 91, 88) << 15) | /* 4b */ + (elk_inst_bits(src, 66, 66) << 14) | /* 1b */ + (elk_inst_bits(src, 50, 50) << 13) | /* 1b */ + (elk_inst_bits(src, 49, 48) << 11) | /* 2b */ + (elk_inst_bits(src, 47, 47) << 10) | /* 1b */ + (elk_inst_bits(src, 46, 46) << 9) | /* 1b */ + (elk_inst_bits(src, 43, 40) << 5) | /* 4b */ + (elk_inst_bits(src, 39, 36) << 1) | /* 4b */ + (elk_inst_bits(src, 35, 35)); /* 1b */ /* Src1.RegFile overlaps with the immediate, so ignore it if an immediate * is present */ if (!is_immediate) { - uncompacted |= brw_inst_bits(src, 98, 98) << 19; /* 1b */ + uncompacted |= elk_inst_bits(src, 98, 98) << 19; /* 1b */ } } else if (devinfo->ver >= 8) { - uncompacted = (brw_inst_bits(src, 63, 61) << 18) | /* 3b */ - (brw_inst_bits(src, 94, 89) << 12) | /* 6b */ - (brw_inst_bits(src, 46, 35)); /* 12b */ + uncompacted = (elk_inst_bits(src, 63, 61) << 18) | /* 3b */ + (elk_inst_bits(src, 94, 89) << 12) | /* 6b */ + (elk_inst_bits(src, 46, 35)); /* 12b */ } else { - uncompacted = (brw_inst_bits(src, 63, 61) << 15) | /* 3b */ - (brw_inst_bits(src, 46, 32)); /* 15b */ + uncompacted = (elk_inst_bits(src, 63, 61) << 15) | /* 3b */ + (elk_inst_bits(src, 46, 32)); /* 15b */ } for (int i = 0; i < 32; i++) { if (c->datatype_table[i] == uncompacted) { - brw_compact_inst_set_datatype_index(devinfo, dst, i); + elk_compact_inst_set_datatype_index(devinfo, dst, i); return true; } } @@ -1409,8 +1409,8 @@ set_datatype_index(const struct compaction_state *c, brw_compact_inst *dst, } static bool -set_subreg_index(const struct compaction_state *c, brw_compact_inst *dst, - const brw_inst *src, bool is_immediate) +set_subreg_index(const struct compaction_state *c, elk_compact_inst *dst, + const elk_inst *src, bool is_immediate) { const struct intel_device_info *devinfo = c->isa->devinfo; const unsigned table_len = devinfo->ver >= 20 ? @@ -1418,27 +1418,27 @@ set_subreg_index(const struct compaction_state *c, brw_compact_inst *dst, uint16_t uncompacted; /* 15b/G45+; 12b/Xe2+ */ if (devinfo->ver >= 20) { - uncompacted = (brw_inst_bits(src, 33, 33) << 0) | /* 1b */ - (brw_inst_bits(src, 55, 51) << 1) | /* 5b */ - (brw_inst_bits(src, 71, 67) << 6) | /* 5b */ - (brw_inst_bits(src, 87, 87) << 11); /* 1b */ + uncompacted = (elk_inst_bits(src, 33, 33) << 0) | /* 1b */ + (elk_inst_bits(src, 55, 51) << 1) | /* 5b */ + (elk_inst_bits(src, 71, 67) << 6) | /* 5b */ + (elk_inst_bits(src, 87, 87) << 11); /* 1b */ } else if (devinfo->ver >= 12) { - uncompacted = (brw_inst_bits(src, 55, 51) << 0) | /* 5b */ - (brw_inst_bits(src, 71, 67) << 5); /* 5b */ + uncompacted = (elk_inst_bits(src, 55, 51) << 0) | /* 5b */ + (elk_inst_bits(src, 71, 67) << 5); /* 5b */ if (!is_immediate) - uncompacted |= brw_inst_bits(src, 103, 99) << 10; /* 5b */ + uncompacted |= elk_inst_bits(src, 103, 99) << 10; /* 5b */ } else { - uncompacted = (brw_inst_bits(src, 52, 48) << 0) | /* 5b */ - (brw_inst_bits(src, 68, 64) << 5); /* 5b */ + uncompacted = (elk_inst_bits(src, 52, 48) << 0) | /* 5b */ + (elk_inst_bits(src, 68, 64) << 5); /* 5b */ if (!is_immediate) - uncompacted |= brw_inst_bits(src, 100, 96) << 10; /* 5b */ + uncompacted |= elk_inst_bits(src, 100, 96) << 10; /* 5b */ } for (int i = 0; i < table_len; i++) { if (c->subreg_table[i] == uncompacted) { - brw_compact_inst_set_subreg_index(devinfo, dst, i); + elk_compact_inst_set_subreg_index(devinfo, dst, i); return true; } } @@ -1447,8 +1447,8 @@ set_subreg_index(const struct compaction_state *c, brw_compact_inst *dst, } static bool -set_src0_index(const struct compaction_state *c, brw_compact_inst *dst, - const brw_inst *src) +set_src0_index(const struct compaction_state *c, elk_compact_inst *dst, + const elk_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; uint16_t uncompacted; /* 12b/G45+; 11b/Xe2+ */ @@ -1458,20 +1458,20 @@ set_src0_index(const struct compaction_state *c, brw_compact_inst *dst, table_len = (devinfo->ver >= 20 ? ARRAY_SIZE(xe2_src0_index_table) : ARRAY_SIZE(gfx12_src0_index_table)); uncompacted = (devinfo->ver >= 20 ? 0 : - brw_inst_bits(src, 87, 87) << 11) | /* 1b */ - (brw_inst_bits(src, 86, 84) << 8) | /* 3b */ - (brw_inst_bits(src, 83, 81) << 5) | /* 3b */ - (brw_inst_bits(src, 80, 80) << 4) | /* 1b */ - (brw_inst_bits(src, 65, 64) << 2) | /* 2b */ - (brw_inst_bits(src, 45, 44)); /* 2b */ + elk_inst_bits(src, 87, 87) << 11) | /* 1b */ + (elk_inst_bits(src, 86, 84) << 8) | /* 3b */ + (elk_inst_bits(src, 83, 81) << 5) | /* 3b */ + (elk_inst_bits(src, 80, 80) << 4) | /* 1b */ + (elk_inst_bits(src, 65, 64) << 2) | /* 2b */ + (elk_inst_bits(src, 45, 44)); /* 2b */ } else { table_len = ARRAY_SIZE(gfx8_src_index_table); - uncompacted = brw_inst_bits(src, 88, 77); /* 12b */ + uncompacted = elk_inst_bits(src, 88, 77); /* 12b */ } for (int i = 0; i < table_len; i++) { if (c->src0_index_table[i] == uncompacted) { - brw_compact_inst_set_src0_index(devinfo, dst, i); + elk_compact_inst_set_src0_index(devinfo, dst, i); return true; } } @@ -1480,17 +1480,17 @@ set_src0_index(const struct compaction_state *c, brw_compact_inst *dst, } static bool -set_src1_index(const struct compaction_state *c, brw_compact_inst *dst, - const brw_inst *src, bool is_immediate, unsigned imm) +set_src1_index(const struct compaction_state *c, elk_compact_inst *dst, + const elk_inst *src, bool is_immediate, unsigned imm) { const struct intel_device_info *devinfo = c->isa->devinfo; if (is_immediate) { if (devinfo->ver >= 12) { /* src1 index takes the low 4 bits of the 12-bit compacted value */ - brw_compact_inst_set_src1_index(devinfo, dst, imm & 0xf); + elk_compact_inst_set_src1_index(devinfo, dst, imm & 0xf); } else { /* src1 index takes the high 5 bits of the 13-bit compacted value */ - brw_compact_inst_set_src1_index(devinfo, dst, imm >> 8); + elk_compact_inst_set_src1_index(devinfo, dst, imm >> 8); } return true; } else { @@ -1499,27 +1499,27 @@ set_src1_index(const struct compaction_state *c, brw_compact_inst *dst, if (devinfo->ver >= 20) { table_len = ARRAY_SIZE(xe2_src1_index_table); - uncompacted = (brw_inst_bits(src, 121, 120) << 14) | /* 2b */ - (brw_inst_bits(src, 118, 116) << 11) | /* 3b */ - (brw_inst_bits(src, 115, 113) << 8) | /* 3b */ - (brw_inst_bits(src, 112, 112) << 7) | /* 1b */ - (brw_inst_bits(src, 103, 99) << 2) | /* 5b */ - (brw_inst_bits(src, 97, 96)); /* 2b */ + uncompacted = (elk_inst_bits(src, 121, 120) << 14) | /* 2b */ + (elk_inst_bits(src, 118, 116) << 11) | /* 3b */ + (elk_inst_bits(src, 115, 113) << 8) | /* 3b */ + (elk_inst_bits(src, 112, 112) << 7) | /* 1b */ + (elk_inst_bits(src, 103, 99) << 2) | /* 5b */ + (elk_inst_bits(src, 97, 96)); /* 2b */ } else if (devinfo->ver >= 12) { table_len = ARRAY_SIZE(gfx12_src0_index_table); - uncompacted = (brw_inst_bits(src, 121, 120) << 10) | /* 2b */ - (brw_inst_bits(src, 119, 116) << 6) | /* 4b */ - (brw_inst_bits(src, 115, 113) << 3) | /* 3b */ - (brw_inst_bits(src, 112, 112) << 2) | /* 1b */ - (brw_inst_bits(src, 97, 96)); /* 2b */ + uncompacted = (elk_inst_bits(src, 121, 120) << 10) | /* 2b */ + (elk_inst_bits(src, 119, 116) << 6) | /* 4b */ + (elk_inst_bits(src, 115, 113) << 3) | /* 3b */ + (elk_inst_bits(src, 112, 112) << 2) | /* 1b */ + (elk_inst_bits(src, 97, 96)); /* 2b */ } else { table_len = ARRAY_SIZE(gfx8_src_index_table); - uncompacted = brw_inst_bits(src, 120, 109); /* 12b */ + uncompacted = elk_inst_bits(src, 120, 109); /* 12b */ } for (int i = 0; i < table_len; i++) { if (c->src1_index_table[i] == uncompacted) { - brw_compact_inst_set_src1_index(devinfo, dst, i); + elk_compact_inst_set_src1_index(devinfo, dst, i); return true; } } @@ -1530,31 +1530,31 @@ set_src1_index(const struct compaction_state *c, brw_compact_inst *dst, static bool set_3src_control_index(const struct intel_device_info *devinfo, - brw_compact_inst *dst, const brw_inst *src, + elk_compact_inst *dst, const elk_inst *src, bool is_dpas) { assert(devinfo->ver >= 8); if (devinfo->ver >= 20) { - assert(is_dpas || !brw_inst_bits(src, 49, 49)); + assert(is_dpas || !elk_inst_bits(src, 49, 49)); const uint64_t uncompacted = /* 34b/Xe2+ */ - (brw_inst_bits(src, 95, 92) << 30) | /* 4b */ - (brw_inst_bits(src, 90, 88) << 27) | /* 3b */ - (brw_inst_bits(src, 82, 80) << 24) | /* 3b */ - (brw_inst_bits(src, 50, 50) << 23) | /* 1b */ - (brw_inst_bits(src, 49, 48) << 21) | /* 2b */ - (brw_inst_bits(src, 42, 40) << 18) | /* 3b */ - (brw_inst_bits(src, 39, 39) << 17) | /* 1b */ - (brw_inst_bits(src, 38, 36) << 14) | /* 3b */ - (brw_inst_bits(src, 34, 34) << 13) | /* 1b */ - (brw_inst_bits(src, 32, 32) << 12) | /* 1b */ - (brw_inst_bits(src, 31, 31) << 11) | /* 1b */ - (brw_inst_bits(src, 28, 28) << 10) | /* 1b */ - (brw_inst_bits(src, 27, 26) << 8) | /* 2b */ - (brw_inst_bits(src, 25, 24) << 6) | /* 2b */ - (brw_inst_bits(src, 23, 21) << 3) | /* 3b */ - (brw_inst_bits(src, 20, 18)); /* 3b */ + (elk_inst_bits(src, 95, 92) << 30) | /* 4b */ + (elk_inst_bits(src, 90, 88) << 27) | /* 3b */ + (elk_inst_bits(src, 82, 80) << 24) | /* 3b */ + (elk_inst_bits(src, 50, 50) << 23) | /* 1b */ + (elk_inst_bits(src, 49, 48) << 21) | /* 2b */ + (elk_inst_bits(src, 42, 40) << 18) | /* 3b */ + (elk_inst_bits(src, 39, 39) << 17) | /* 1b */ + (elk_inst_bits(src, 38, 36) << 14) | /* 3b */ + (elk_inst_bits(src, 34, 34) << 13) | /* 1b */ + (elk_inst_bits(src, 32, 32) << 12) | /* 1b */ + (elk_inst_bits(src, 31, 31) << 11) | /* 1b */ + (elk_inst_bits(src, 28, 28) << 10) | /* 1b */ + (elk_inst_bits(src, 27, 26) << 8) | /* 2b */ + (elk_inst_bits(src, 25, 24) << 6) | /* 2b */ + (elk_inst_bits(src, 23, 21) << 3) | /* 3b */ + (elk_inst_bits(src, 20, 18)); /* 3b */ /* The bits used to index the tables for 3src and 3src-dpas * are the same, so just need to pick the right one. @@ -1565,77 +1565,77 @@ set_3src_control_index(const struct intel_device_info *devinfo, ARRAY_SIZE(xe2_3src_control_index_table); for (unsigned i = 0; i < size; i++) { if (table[i] == uncompacted) { - brw_compact_inst_set_3src_control_index(devinfo, dst, i); + elk_compact_inst_set_3src_control_index(devinfo, dst, i); return true; } } } else if (devinfo->verx10 >= 125) { uint64_t uncompacted = /* 37b/XeHP+ */ - (brw_inst_bits(src, 95, 92) << 33) | /* 4b */ - (brw_inst_bits(src, 90, 88) << 30) | /* 3b */ - (brw_inst_bits(src, 82, 80) << 27) | /* 3b */ - (brw_inst_bits(src, 50, 50) << 26) | /* 1b */ - (brw_inst_bits(src, 49, 48) << 24) | /* 2b */ - (brw_inst_bits(src, 42, 40) << 21) | /* 3b */ - (brw_inst_bits(src, 39, 39) << 20) | /* 1b */ - (brw_inst_bits(src, 38, 36) << 17) | /* 3b */ - (brw_inst_bits(src, 34, 34) << 16) | /* 1b */ - (brw_inst_bits(src, 33, 33) << 15) | /* 1b */ - (brw_inst_bits(src, 32, 32) << 14) | /* 1b */ - (brw_inst_bits(src, 31, 31) << 13) | /* 1b */ - (brw_inst_bits(src, 28, 28) << 12) | /* 1b */ - (brw_inst_bits(src, 27, 24) << 8) | /* 4b */ - (brw_inst_bits(src, 23, 23) << 7) | /* 1b */ - (brw_inst_bits(src, 22, 22) << 6) | /* 1b */ - (brw_inst_bits(src, 21, 19) << 3) | /* 3b */ - (brw_inst_bits(src, 18, 16)); /* 3b */ + (elk_inst_bits(src, 95, 92) << 33) | /* 4b */ + (elk_inst_bits(src, 90, 88) << 30) | /* 3b */ + (elk_inst_bits(src, 82, 80) << 27) | /* 3b */ + (elk_inst_bits(src, 50, 50) << 26) | /* 1b */ + (elk_inst_bits(src, 49, 48) << 24) | /* 2b */ + (elk_inst_bits(src, 42, 40) << 21) | /* 3b */ + (elk_inst_bits(src, 39, 39) << 20) | /* 1b */ + (elk_inst_bits(src, 38, 36) << 17) | /* 3b */ + (elk_inst_bits(src, 34, 34) << 16) | /* 1b */ + (elk_inst_bits(src, 33, 33) << 15) | /* 1b */ + (elk_inst_bits(src, 32, 32) << 14) | /* 1b */ + (elk_inst_bits(src, 31, 31) << 13) | /* 1b */ + (elk_inst_bits(src, 28, 28) << 12) | /* 1b */ + (elk_inst_bits(src, 27, 24) << 8) | /* 4b */ + (elk_inst_bits(src, 23, 23) << 7) | /* 1b */ + (elk_inst_bits(src, 22, 22) << 6) | /* 1b */ + (elk_inst_bits(src, 21, 19) << 3) | /* 3b */ + (elk_inst_bits(src, 18, 16)); /* 3b */ for (unsigned i = 0; i < ARRAY_SIZE(xehp_3src_control_index_table); i++) { if (xehp_3src_control_index_table[i] == uncompacted) { - brw_compact_inst_set_3src_control_index(devinfo, dst, i); + elk_compact_inst_set_3src_control_index(devinfo, dst, i); return true; } } } else if (devinfo->ver >= 12) { uint64_t uncompacted = /* 36b/TGL+ */ - (brw_inst_bits(src, 95, 92) << 32) | /* 4b */ - (brw_inst_bits(src, 90, 88) << 29) | /* 3b */ - (brw_inst_bits(src, 82, 80) << 26) | /* 3b */ - (brw_inst_bits(src, 50, 50) << 25) | /* 1b */ - (brw_inst_bits(src, 48, 48) << 24) | /* 1b */ - (brw_inst_bits(src, 42, 40) << 21) | /* 3b */ - (brw_inst_bits(src, 39, 39) << 20) | /* 1b */ - (brw_inst_bits(src, 38, 36) << 17) | /* 3b */ - (brw_inst_bits(src, 34, 34) << 16) | /* 1b */ - (brw_inst_bits(src, 33, 33) << 15) | /* 1b */ - (brw_inst_bits(src, 32, 32) << 14) | /* 1b */ - (brw_inst_bits(src, 31, 31) << 13) | /* 1b */ - (brw_inst_bits(src, 28, 28) << 12) | /* 1b */ - (brw_inst_bits(src, 27, 24) << 8) | /* 4b */ - (brw_inst_bits(src, 23, 23) << 7) | /* 1b */ - (brw_inst_bits(src, 22, 22) << 6) | /* 1b */ - (brw_inst_bits(src, 21, 19) << 3) | /* 3b */ - (brw_inst_bits(src, 18, 16)); /* 3b */ + (elk_inst_bits(src, 95, 92) << 32) | /* 4b */ + (elk_inst_bits(src, 90, 88) << 29) | /* 3b */ + (elk_inst_bits(src, 82, 80) << 26) | /* 3b */ + (elk_inst_bits(src, 50, 50) << 25) | /* 1b */ + (elk_inst_bits(src, 48, 48) << 24) | /* 1b */ + (elk_inst_bits(src, 42, 40) << 21) | /* 3b */ + (elk_inst_bits(src, 39, 39) << 20) | /* 1b */ + (elk_inst_bits(src, 38, 36) << 17) | /* 3b */ + (elk_inst_bits(src, 34, 34) << 16) | /* 1b */ + (elk_inst_bits(src, 33, 33) << 15) | /* 1b */ + (elk_inst_bits(src, 32, 32) << 14) | /* 1b */ + (elk_inst_bits(src, 31, 31) << 13) | /* 1b */ + (elk_inst_bits(src, 28, 28) << 12) | /* 1b */ + (elk_inst_bits(src, 27, 24) << 8) | /* 4b */ + (elk_inst_bits(src, 23, 23) << 7) | /* 1b */ + (elk_inst_bits(src, 22, 22) << 6) | /* 1b */ + (elk_inst_bits(src, 21, 19) << 3) | /* 3b */ + (elk_inst_bits(src, 18, 16)); /* 3b */ for (unsigned i = 0; i < ARRAY_SIZE(gfx12_3src_control_index_table); i++) { if (gfx12_3src_control_index_table[i] == uncompacted) { - brw_compact_inst_set_3src_control_index(devinfo, dst, i); + elk_compact_inst_set_3src_control_index(devinfo, dst, i); return true; } } } else { uint32_t uncompacted = /* 24b/BDW; 26b/CHV/SKL+ */ - (brw_inst_bits(src, 34, 32) << 21) | /* 3b */ - (brw_inst_bits(src, 28, 8)); /* 21b */ + (elk_inst_bits(src, 34, 32) << 21) | /* 3b */ + (elk_inst_bits(src, 28, 8)); /* 21b */ if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { uncompacted |= - brw_inst_bits(src, 36, 35) << 24; /* 2b */ + elk_inst_bits(src, 36, 35) << 24; /* 2b */ } for (unsigned i = 0; i < ARRAY_SIZE(gfx8_3src_control_index_table); i++) { if (gfx8_3src_control_index_table[i] == uncompacted) { - brw_compact_inst_set_3src_control_index(devinfo, dst, i); + elk_compact_inst_set_3src_control_index(devinfo, dst, i); return true; } } @@ -1646,28 +1646,28 @@ set_3src_control_index(const struct intel_device_info *devinfo, static bool set_3src_source_index(const struct intel_device_info *devinfo, - brw_compact_inst *dst, const brw_inst *src, + elk_compact_inst *dst, const elk_inst *src, bool is_dpas) { assert(devinfo->ver >= 8); if (devinfo->ver >= 12) { uint32_t uncompacted = /* 21b/TGL+ */ - (brw_inst_bits(src, 114, 114) << 20) | /* 1b */ - (brw_inst_bits(src, 113, 112) << 18) | /* 2b */ - (brw_inst_bits(src, 98, 98) << 17) | /* 1b */ - (brw_inst_bits(src, 97, 96) << 15) | /* 2b */ - (brw_inst_bits(src, 91, 91) << 14) | /* 1b */ - (brw_inst_bits(src, 87, 86) << 12) | /* 2b */ - (brw_inst_bits(src, 85, 84) << 10) | /* 2b */ - (brw_inst_bits(src, 83, 83) << 9) | /* 1b */ - (brw_inst_bits(src, 66, 66) << 8) | /* 1b */ - (brw_inst_bits(src, 65, 64) << 6) | /* 2b */ - (brw_inst_bits(src, 47, 47) << 5) | /* 1b */ - (brw_inst_bits(src, 46, 46) << 4) | /* 1b */ - (brw_inst_bits(src, 45, 44) << 2) | /* 2b */ - (brw_inst_bits(src, 43, 43) << 1) | /* 1b */ - (brw_inst_bits(src, 35, 35)); /* 1b */ + (elk_inst_bits(src, 114, 114) << 20) | /* 1b */ + (elk_inst_bits(src, 113, 112) << 18) | /* 2b */ + (elk_inst_bits(src, 98, 98) << 17) | /* 1b */ + (elk_inst_bits(src, 97, 96) << 15) | /* 2b */ + (elk_inst_bits(src, 91, 91) << 14) | /* 1b */ + (elk_inst_bits(src, 87, 86) << 12) | /* 2b */ + (elk_inst_bits(src, 85, 84) << 10) | /* 2b */ + (elk_inst_bits(src, 83, 83) << 9) | /* 1b */ + (elk_inst_bits(src, 66, 66) << 8) | /* 1b */ + (elk_inst_bits(src, 65, 64) << 6) | /* 2b */ + (elk_inst_bits(src, 47, 47) << 5) | /* 1b */ + (elk_inst_bits(src, 46, 46) << 4) | /* 1b */ + (elk_inst_bits(src, 45, 44) << 2) | /* 2b */ + (elk_inst_bits(src, 43, 43) << 1) | /* 1b */ + (elk_inst_bits(src, 35, 35)); /* 1b */ /* In Xe2, the bits used to index the tables for 3src and 3src-dpas * are the same, so just need to pick the right one. @@ -1685,32 +1685,32 @@ set_3src_source_index(const struct intel_device_info *devinfo, for (unsigned i = 0; i < three_src_source_index_table_len; i++) { if (three_src_source_index_table[i] == uncompacted) { - brw_compact_inst_set_3src_source_index(devinfo, dst, i); + elk_compact_inst_set_3src_source_index(devinfo, dst, i); return true; } } } else { uint64_t uncompacted = /* 46b/BDW; 49b/CHV/SKL+ */ - (brw_inst_bits(src, 83, 83) << 43) | /* 1b */ - (brw_inst_bits(src, 114, 107) << 35) | /* 8b */ - (brw_inst_bits(src, 93, 86) << 27) | /* 8b */ - (brw_inst_bits(src, 72, 65) << 19) | /* 8b */ - (brw_inst_bits(src, 55, 37)); /* 19b */ + (elk_inst_bits(src, 83, 83) << 43) | /* 1b */ + (elk_inst_bits(src, 114, 107) << 35) | /* 8b */ + (elk_inst_bits(src, 93, 86) << 27) | /* 8b */ + (elk_inst_bits(src, 72, 65) << 19) | /* 8b */ + (elk_inst_bits(src, 55, 37)); /* 19b */ if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { uncompacted |= - (brw_inst_bits(src, 126, 125) << 47) | /* 2b */ - (brw_inst_bits(src, 105, 104) << 45) | /* 2b */ - (brw_inst_bits(src, 84, 84) << 44); /* 1b */ + (elk_inst_bits(src, 126, 125) << 47) | /* 2b */ + (elk_inst_bits(src, 105, 104) << 45) | /* 2b */ + (elk_inst_bits(src, 84, 84) << 44); /* 1b */ } else { uncompacted |= - (brw_inst_bits(src, 125, 125) << 45) | /* 1b */ - (brw_inst_bits(src, 104, 104) << 44); /* 1b */ + (elk_inst_bits(src, 125, 125) << 45) | /* 1b */ + (elk_inst_bits(src, 104, 104) << 44); /* 1b */ } for (unsigned i = 0; i < ARRAY_SIZE(gfx8_3src_source_index_table); i++) { if (gfx8_3src_source_index_table[i] == uncompacted) { - brw_compact_inst_set_3src_source_index(devinfo, dst, i); + elk_compact_inst_set_3src_source_index(devinfo, dst, i); return true; } } @@ -1721,15 +1721,15 @@ set_3src_source_index(const struct intel_device_info *devinfo, static bool set_3src_subreg_index(const struct intel_device_info *devinfo, - brw_compact_inst *dst, const brw_inst *src) + elk_compact_inst *dst, const elk_inst *src) { assert(devinfo->ver >= 12); uint32_t uncompacted = /* 20b/TGL+ */ - (brw_inst_bits(src, 119, 115) << 15) | /* 5b */ - (brw_inst_bits(src, 103, 99) << 10) | /* 5b */ - (brw_inst_bits(src, 71, 67) << 5) | /* 5b */ - (brw_inst_bits(src, 55, 51)); /* 5b */ + (elk_inst_bits(src, 119, 115) << 15) | /* 5b */ + (elk_inst_bits(src, 103, 99) << 10) | /* 5b */ + (elk_inst_bits(src, 71, 67) << 5) | /* 5b */ + (elk_inst_bits(src, 55, 51)); /* 5b */ const uint32_t *table = devinfo->ver >= 20 ? xe2_3src_subreg_table : gfx12_3src_subreg_table; @@ -1739,7 +1739,7 @@ set_3src_subreg_index(const struct intel_device_info *devinfo, for (unsigned i = 0; i < len; i++) { if (table[i] == uncompacted) { - brw_compact_inst_set_3src_subreg_index(devinfo, dst, i); + elk_compact_inst_set_3src_subreg_index(devinfo, dst, i); return true; } } @@ -1748,14 +1748,14 @@ set_3src_subreg_index(const struct intel_device_info *devinfo, } static bool -has_unmapped_bits(const struct brw_isa_info *isa, const brw_inst *src) +has_unmapped_bits(const struct elk_isa_info *isa, const elk_inst *src) { const struct intel_device_info *devinfo = isa->devinfo; /* EOT can only be mapped on a send if the src1 is an immediate */ - if ((brw_inst_opcode(isa, src) == BRW_OPCODE_SENDC || - brw_inst_opcode(isa, src) == BRW_OPCODE_SEND) && - brw_inst_eot(devinfo, src)) + if ((elk_inst_opcode(isa, src) == ELK_OPCODE_SENDC || + elk_inst_opcode(isa, src) == ELK_OPCODE_SEND) && + elk_inst_eot(devinfo, src)) return true; /* Check for instruction bits that don't map to any of the fields of the @@ -1768,48 +1768,48 @@ has_unmapped_bits(const struct brw_isa_info *isa, const brw_inst *src) * - UIP[31] (bit 95 on Gfx8) */ if (devinfo->ver >= 12) { - assert(!brw_inst_bits(src, 7, 7)); + assert(!elk_inst_bits(src, 7, 7)); return false; } else if (devinfo->ver >= 8) { - assert(!brw_inst_bits(src, 7, 7)); - return brw_inst_bits(src, 95, 95) || - brw_inst_bits(src, 47, 47) || - brw_inst_bits(src, 11, 11); + assert(!elk_inst_bits(src, 7, 7)); + return elk_inst_bits(src, 95, 95) || + elk_inst_bits(src, 47, 47) || + elk_inst_bits(src, 11, 11); } else { - assert(!brw_inst_bits(src, 7, 7) && - !(devinfo->ver < 7 && brw_inst_bits(src, 90, 90))); - return brw_inst_bits(src, 95, 91) || - brw_inst_bits(src, 47, 47); + assert(!elk_inst_bits(src, 7, 7) && + !(devinfo->ver < 7 && elk_inst_bits(src, 90, 90))); + return elk_inst_bits(src, 95, 91) || + elk_inst_bits(src, 47, 47); } } static bool has_3src_unmapped_bits(const struct intel_device_info *devinfo, - const brw_inst *src, bool is_dpas) + const elk_inst *src, bool is_dpas) { /* Check for three-source instruction bits that don't map to any of the * fields of the compacted instruction. All of them seem to be reserved * bits currently. */ if (devinfo->ver >= 20) { - assert(is_dpas || !brw_inst_bits(src, 49, 49)); - assert(!brw_inst_bits(src, 33, 33)); - assert(!brw_inst_bits(src, 7, 7)); + assert(is_dpas || !elk_inst_bits(src, 49, 49)); + assert(!elk_inst_bits(src, 33, 33)); + assert(!elk_inst_bits(src, 7, 7)); } else if (devinfo->ver >= 12) { - assert(is_dpas || !brw_inst_bits(src, 49, 49)); - assert(!brw_inst_bits(src, 7, 7)); + assert(is_dpas || !elk_inst_bits(src, 49, 49)); + assert(!elk_inst_bits(src, 7, 7)); } else if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { - assert(!brw_inst_bits(src, 127, 127) && - !brw_inst_bits(src, 7, 7)); + assert(!elk_inst_bits(src, 127, 127) && + !elk_inst_bits(src, 7, 7)); } else { assert(devinfo->ver >= 8); - assert(!brw_inst_bits(src, 127, 126) && - !brw_inst_bits(src, 105, 105) && - !brw_inst_bits(src, 84, 84) && - !brw_inst_bits(src, 7, 7)); + assert(!elk_inst_bits(src, 127, 126) && + !elk_inst_bits(src, 105, 105) && + !elk_inst_bits(src, 84, 84) && + !elk_inst_bits(src, 7, 7)); /* Src1Type and Src2Type, used for mixed-precision floating point */ - if (brw_inst_bits(src, 36, 35)) + if (elk_inst_bits(src, 36, 35)) return true; } @@ -1817,20 +1817,20 @@ has_3src_unmapped_bits(const struct intel_device_info *devinfo, } static bool -brw_try_compact_3src_instruction(const struct brw_isa_info *isa, - brw_compact_inst *dst, const brw_inst *src) +elk_try_compact_3src_instruction(const struct elk_isa_info *isa, + elk_compact_inst *dst, const elk_inst *src) { const struct intel_device_info *devinfo = isa->devinfo; assert(devinfo->ver >= 8); - bool is_dpas = brw_inst_opcode(isa, src) == BRW_OPCODE_DPAS; + bool is_dpas = elk_inst_opcode(isa, src) == ELK_OPCODE_DPAS; if (has_3src_unmapped_bits(devinfo, src, is_dpas)) return false; #define compact(field) \ - brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_##field(devinfo, src)) + elk_compact_inst_set_3src_##field(devinfo, dst, elk_inst_3src_##field(devinfo, src)) #define compact_a16(field) \ - brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_a16_##field(devinfo, src)) + elk_compact_inst_set_3src_##field(devinfo, dst, elk_inst_3src_a16_##field(devinfo, src)) compact(hw_opcode); @@ -1864,7 +1864,7 @@ brw_try_compact_3src_instruction(const struct brw_isa_info *isa, compact_a16(src1_subreg_nr); compact_a16(src2_subreg_nr); } - brw_compact_inst_set_3src_cmpt_control(devinfo, dst, true); + elk_compact_inst_set_3src_cmpt_control(devinfo, dst, true); #undef compact #undef compact_a16 @@ -1886,16 +1886,16 @@ brw_try_compact_3src_instruction(const struct brw_isa_info *isa, */ static int compact_immediate(const struct intel_device_info *devinfo, - enum brw_reg_type type, unsigned imm) + enum elk_reg_type type, unsigned imm) { if (devinfo->ver >= 12) { /* 16-bit immediates need to be replicated through the 32-bit immediate * field */ switch (type) { - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_HF: if ((imm >> 16) != (imm & 0xffff)) return -1; break; @@ -1904,45 +1904,45 @@ compact_immediate(const struct intel_device_info *devinfo, } switch (type) { - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: /* We get the high 12-bits as-is; rest must be zero */ if ((imm & 0xfffff) == 0) return (imm >> 20) & 0xfff; break; - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: /* We get the high 12-bits as-is; rest must be zero */ if ((imm & 0xf) == 0) return (imm >> 4) & 0xfff; break; - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_VF: - case BRW_REGISTER_TYPE_UV: - case BRW_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_V: /* We get the low 12-bits as-is; rest must be zero */ if ((imm & 0xfffff000) == 0) return imm & 0xfff; break; - case BRW_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_UW: /* We get the low 12-bits as-is; rest must be zero */ if ((imm & 0xf000) == 0) return imm & 0xfff; break; - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_D: /* We get the low 11-bits as-is; 12th is replicated */ if (((int)imm >> 11) == 0 || ((int)imm >> 11) == -1) return imm & 0xfff; break; - case BRW_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_W: /* We get the low 11-bits as-is; 12th is replicated */ if (((short)imm >> 11) == 0 || ((short)imm >> 11) == -1) return imm & 0xfff; break; - case BRW_REGISTER_TYPE_NF: - case BRW_REGISTER_TYPE_DF: - case BRW_REGISTER_TYPE_Q: - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: return -1; } } else { @@ -1957,35 +1957,35 @@ compact_immediate(const struct intel_device_info *devinfo, static int uncompact_immediate(const struct intel_device_info *devinfo, - enum brw_reg_type type, unsigned compact_imm) + enum elk_reg_type type, unsigned compact_imm) { if (devinfo->ver >= 12) { switch (type) { - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: return compact_imm << 20; - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: return (compact_imm << 20) | (compact_imm << 4); - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_VF: - case BRW_REGISTER_TYPE_UV: - case BRW_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_V: return compact_imm; - case BRW_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_UW: /* Replicate */ return compact_imm << 16 | compact_imm; - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_D: /* Extend the 12th bit into the high 20 bits */ return (int)(compact_imm << 20) >> 20; - case BRW_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_W: /* Extend the 12th bit into the high 4 bits and replicate */ return ((int)(compact_imm << 20) >> 4) | ((unsigned short)((short)(compact_imm << 4) >> 4)); - case BRW_REGISTER_TYPE_NF: - case BRW_REGISTER_TYPE_DF: - case BRW_REGISTER_TYPE_Q: - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: unreachable("not reached"); } } else { @@ -1997,14 +1997,14 @@ uncompact_immediate(const struct intel_device_info *devinfo, } static bool -has_immediate(const struct intel_device_info *devinfo, const brw_inst *inst, - enum brw_reg_type *type) +has_immediate(const struct intel_device_info *devinfo, const elk_inst *inst, + enum elk_reg_type *type) { - if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { - *type = brw_inst_src0_type(devinfo, inst); + if (elk_inst_src0_reg_file(devinfo, inst) == ELK_IMMEDIATE_VALUE) { + *type = elk_inst_src0_type(devinfo, inst); return *type != INVALID_REG_TYPE; - } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { - *type = brw_inst_src1_type(devinfo, inst); + } else if (elk_inst_src1_reg_file(devinfo, inst) == ELK_IMMEDIATE_VALUE) { + *type = elk_inst_src1_type(devinfo, inst); return *type != INVALID_REG_TYPE; } @@ -2015,8 +2015,8 @@ has_immediate(const struct intel_device_info *devinfo, const brw_inst *inst, * Applies some small changes to instruction types to increase chances of * compaction. */ -static brw_inst -precompact(const struct brw_isa_info *isa, brw_inst inst) +static elk_inst +precompact(const struct elk_isa_info *isa, elk_inst inst) { const struct intel_device_info *devinfo = isa->devinfo; @@ -2025,26 +2025,26 @@ precompact(const struct brw_isa_info *isa, brw_inst inst) * sequential elements, so convert to those before compacting. */ if (devinfo->verx10 >= 125) { - if (brw_inst_src0_reg_file(devinfo, &inst) == BRW_GENERAL_REGISTER_FILE && - brw_inst_src0_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 && - brw_inst_src0_vstride(devinfo, &inst) == (brw_inst_src0_width(devinfo, &inst) + 1) && - brw_inst_src0_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) { - brw_inst_set_src0_vstride(devinfo, &inst, BRW_VERTICAL_STRIDE_1); - brw_inst_set_src0_width(devinfo, &inst, BRW_WIDTH_1); - brw_inst_set_src0_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0); + if (elk_inst_src0_reg_file(devinfo, &inst) == ELK_GENERAL_REGISTER_FILE && + elk_inst_src0_vstride(devinfo, &inst) > ELK_VERTICAL_STRIDE_1 && + elk_inst_src0_vstride(devinfo, &inst) == (elk_inst_src0_width(devinfo, &inst) + 1) && + elk_inst_src0_hstride(devinfo, &inst) == ELK_HORIZONTAL_STRIDE_1) { + elk_inst_set_src0_vstride(devinfo, &inst, ELK_VERTICAL_STRIDE_1); + elk_inst_set_src0_width(devinfo, &inst, ELK_WIDTH_1); + elk_inst_set_src0_hstride(devinfo, &inst, ELK_HORIZONTAL_STRIDE_0); } - if (brw_inst_src1_reg_file(devinfo, &inst) == BRW_GENERAL_REGISTER_FILE && - brw_inst_src1_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 && - brw_inst_src1_vstride(devinfo, &inst) == (brw_inst_src1_width(devinfo, &inst) + 1) && - brw_inst_src1_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) { - brw_inst_set_src1_vstride(devinfo, &inst, BRW_VERTICAL_STRIDE_1); - brw_inst_set_src1_width(devinfo, &inst, BRW_WIDTH_1); - brw_inst_set_src1_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0); + if (elk_inst_src1_reg_file(devinfo, &inst) == ELK_GENERAL_REGISTER_FILE && + elk_inst_src1_vstride(devinfo, &inst) > ELK_VERTICAL_STRIDE_1 && + elk_inst_src1_vstride(devinfo, &inst) == (elk_inst_src1_width(devinfo, &inst) + 1) && + elk_inst_src1_hstride(devinfo, &inst) == ELK_HORIZONTAL_STRIDE_1) { + elk_inst_set_src1_vstride(devinfo, &inst, ELK_VERTICAL_STRIDE_1); + elk_inst_set_src1_width(devinfo, &inst, ELK_WIDTH_1); + elk_inst_set_src1_hstride(devinfo, &inst, ELK_HORIZONTAL_STRIDE_0); } } - if (brw_inst_src0_reg_file(devinfo, &inst) != BRW_IMMEDIATE_VALUE) + if (elk_inst_src0_reg_file(devinfo, &inst) != ELK_IMMEDIATE_VALUE) return inst; /* The Bspec's section titled "Non-present Operands" claims that if src0 @@ -2075,12 +2075,12 @@ precompact(const struct brw_isa_info *isa, brw_inst inst) */ if (devinfo->ver >= 6 && !(devinfo->platform == INTEL_PLATFORM_HSW && - brw_inst_opcode(isa, &inst) == BRW_OPCODE_DIM) && + elk_inst_opcode(isa, &inst) == ELK_OPCODE_DIM) && !(devinfo->ver >= 8 && - (brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF || - brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_UQ || - brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_Q))) { - brw_inst_set_src1_reg_hw_type(devinfo, &inst, 0); + (elk_inst_src0_type(devinfo, &inst) == ELK_REGISTER_TYPE_DF || + elk_inst_src0_type(devinfo, &inst) == ELK_REGISTER_TYPE_UQ || + elk_inst_src0_type(devinfo, &inst) == ELK_REGISTER_TYPE_Q))) { + elk_inst_set_src1_reg_hw_type(devinfo, &inst, 0); } /* Compacted instructions only have 12-bits (plus 1 for the other 20) @@ -2098,12 +2098,12 @@ precompact(const struct brw_isa_info *isa, brw_inst inst) * removing the need for this. */ if (devinfo->ver < 12 && - brw_inst_imm_ud(devinfo, &inst) == 0x0 && - brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_F && - brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_F && - brw_inst_dst_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) { - enum brw_reg_file file = brw_inst_src0_reg_file(devinfo, &inst); - brw_inst_set_src0_file_type(devinfo, &inst, file, BRW_REGISTER_TYPE_VF); + elk_inst_imm_ud(devinfo, &inst) == 0x0 && + elk_inst_src0_type(devinfo, &inst) == ELK_REGISTER_TYPE_F && + elk_inst_dst_type(devinfo, &inst) == ELK_REGISTER_TYPE_F && + elk_inst_dst_hstride(devinfo, &inst) == ELK_HORIZONTAL_STRIDE_1) { + enum elk_reg_file file = elk_inst_src0_reg_file(devinfo, &inst); + elk_inst_set_src0_file_type(devinfo, &inst, file, ELK_REGISTER_TYPE_VF); } /* There are no mappings for dst:d | i:d, so if the immediate is suitable @@ -2112,16 +2112,16 @@ precompact(const struct brw_isa_info *isa, brw_inst inst) * FINISHME: Use dst:f | imm:f on Gfx12 */ if (devinfo->ver < 12 && - compact_immediate(devinfo, BRW_REGISTER_TYPE_D, - brw_inst_imm_ud(devinfo, &inst)) != -1 && - brw_inst_cond_modifier(devinfo, &inst) == BRW_CONDITIONAL_NONE && - brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_D && - brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_D) { - enum brw_reg_file src_file = brw_inst_src0_reg_file(devinfo, &inst); - enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, &inst); + compact_immediate(devinfo, ELK_REGISTER_TYPE_D, + elk_inst_imm_ud(devinfo, &inst)) != -1 && + elk_inst_cond_modifier(devinfo, &inst) == ELK_CONDITIONAL_NONE && + elk_inst_src0_type(devinfo, &inst) == ELK_REGISTER_TYPE_D && + elk_inst_dst_type(devinfo, &inst) == ELK_REGISTER_TYPE_D) { + enum elk_reg_file src_file = elk_inst_src0_reg_file(devinfo, &inst); + enum elk_reg_file dst_file = elk_inst_dst_reg_file(devinfo, &inst); - brw_inst_set_src0_file_type(devinfo, &inst, src_file, BRW_REGISTER_TYPE_UD); - brw_inst_set_dst_file_type(devinfo, &inst, dst_file, BRW_REGISTER_TYPE_UD); + elk_inst_set_src0_file_type(devinfo, &inst, src_file, ELK_REGISTER_TYPE_UD); + elk_inst_set_dst_file_type(devinfo, &inst, dst_file, ELK_REGISTER_TYPE_UD); } return inst; @@ -2131,21 +2131,21 @@ precompact(const struct brw_isa_info *isa, brw_inst inst) * Tries to compact instruction src into dst. * * It doesn't modify dst unless src is compactable, which is relied on by - * brw_compact_instructions(). + * elk_compact_instructions(). */ static bool try_compact_instruction(const struct compaction_state *c, - brw_compact_inst *dst, const brw_inst *src) + elk_compact_inst *dst, const elk_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; - brw_compact_inst temp; + elk_compact_inst temp; - assert(brw_inst_cmpt_control(devinfo, src) == 0); + assert(elk_inst_cmpt_control(devinfo, src) == 0); - if (is_3src(c->isa, brw_inst_opcode(c->isa, src))) { + if (elk_is_3src(c->isa, elk_inst_opcode(c->isa, src))) { if (devinfo->ver >= 8) { memset(&temp, 0, sizeof(temp)); - if (brw_try_compact_3src_instruction(c->isa, &temp, src)) { + if (elk_try_compact_3src_instruction(c->isa, &temp, src)) { *dst = temp; return true; } else { @@ -2156,7 +2156,7 @@ try_compact_instruction(const struct compaction_state *c, } } - enum brw_reg_type type; + enum elk_reg_type type; bool is_immediate = has_immediate(devinfo, src, &type); unsigned compacted_imm = 0; @@ -2167,7 +2167,7 @@ try_compact_instruction(const struct compaction_state *c, return false; compacted_imm = compact_immediate(devinfo, type, - brw_inst_imm_ud(devinfo, src)); + elk_inst_imm_ud(devinfo, src)); if (compacted_imm == -1) return false; } @@ -2178,10 +2178,10 @@ try_compact_instruction(const struct compaction_state *c, memset(&temp, 0, sizeof(temp)); #define compact(field) \ - brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src)) + elk_compact_inst_set_##field(devinfo, &temp, elk_inst_##field(devinfo, src)) #define compact_reg(field) \ - brw_compact_inst_set_##field##_reg_nr(devinfo, &temp, \ - brw_inst_##field##_da_reg_nr(devinfo, src)) + elk_compact_inst_set_##field##_reg_nr(devinfo, &temp, \ + elk_inst_##field##_da_reg_nr(devinfo, src)) compact(hw_opcode); compact(debug_control); @@ -2204,7 +2204,7 @@ try_compact_instruction(const struct compaction_state *c, if (is_immediate) { /* src1 reg takes the high 8 bits (of the 12-bit compacted value) */ - brw_compact_inst_set_src1_reg_nr(devinfo, &temp, compacted_imm >> 4); + elk_compact_inst_set_src1_reg_nr(devinfo, &temp, compacted_imm >> 4); } else { compact_reg(src1); } @@ -2225,12 +2225,12 @@ try_compact_instruction(const struct compaction_state *c, if (is_immediate) { /* src1 reg takes the low 8 bits (of the 13-bit compacted value) */ - brw_compact_inst_set_src1_reg_nr(devinfo, &temp, compacted_imm & 0xff); + elk_compact_inst_set_src1_reg_nr(devinfo, &temp, compacted_imm & 0xff); } else { compact_reg(src1); } } - brw_compact_inst_set_cmpt_control(devinfo, &temp, true); + elk_compact_inst_set_cmpt_control(devinfo, &temp, true); #undef compact #undef compact_reg @@ -2241,8 +2241,8 @@ try_compact_instruction(const struct compaction_state *c, } bool -brw_try_compact_instruction(const struct brw_isa_info *isa, - brw_compact_inst *dst, const brw_inst *src) +elk_try_compact_instruction(const struct elk_isa_info *isa, + elk_compact_inst *dst, const elk_inst *src) { struct compaction_state c; compaction_state_init(&c, isa); @@ -2250,244 +2250,244 @@ brw_try_compact_instruction(const struct brw_isa_info *isa, } static void -set_uncompacted_control(const struct compaction_state *c, brw_inst *dst, - brw_compact_inst *src) +set_uncompacted_control(const struct compaction_state *c, elk_inst *dst, + elk_compact_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; uint32_t uncompacted = - c->control_index_table[brw_compact_inst_control_index(devinfo, src)]; + c->control_index_table[elk_compact_inst_control_index(devinfo, src)]; if (devinfo->ver >= 20) { - brw_inst_set_bits(dst, 95, 92, (uncompacted >> 14) & 0xf); - brw_inst_set_bits(dst, 34, 34, (uncompacted >> 13) & 0x1); - brw_inst_set_bits(dst, 32, 32, (uncompacted >> 12) & 0x1); - brw_inst_set_bits(dst, 31, 31, (uncompacted >> 11) & 0x1); - brw_inst_set_bits(dst, 28, 28, (uncompacted >> 10) & 0x1); - brw_inst_set_bits(dst, 27, 26, (uncompacted >> 8) & 0x3); - brw_inst_set_bits(dst, 25, 24, (uncompacted >> 6) & 0x3); - brw_inst_set_bits(dst, 23, 21, (uncompacted >> 3) & 0x7); - brw_inst_set_bits(dst, 20, 18, (uncompacted >> 0) & 0x7); + elk_inst_set_bits(dst, 95, 92, (uncompacted >> 14) & 0xf); + elk_inst_set_bits(dst, 34, 34, (uncompacted >> 13) & 0x1); + elk_inst_set_bits(dst, 32, 32, (uncompacted >> 12) & 0x1); + elk_inst_set_bits(dst, 31, 31, (uncompacted >> 11) & 0x1); + elk_inst_set_bits(dst, 28, 28, (uncompacted >> 10) & 0x1); + elk_inst_set_bits(dst, 27, 26, (uncompacted >> 8) & 0x3); + elk_inst_set_bits(dst, 25, 24, (uncompacted >> 6) & 0x3); + elk_inst_set_bits(dst, 23, 21, (uncompacted >> 3) & 0x7); + elk_inst_set_bits(dst, 20, 18, (uncompacted >> 0) & 0x7); } else if (devinfo->ver >= 12) { - brw_inst_set_bits(dst, 95, 92, (uncompacted >> 17)); - brw_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1); - brw_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1); - brw_inst_set_bits(dst, 32, 32, (uncompacted >> 14) & 0x1); - brw_inst_set_bits(dst, 31, 31, (uncompacted >> 13) & 0x1); - brw_inst_set_bits(dst, 28, 28, (uncompacted >> 12) & 0x1); - brw_inst_set_bits(dst, 27, 24, (uncompacted >> 8) & 0xf); - brw_inst_set_bits(dst, 23, 22, (uncompacted >> 6) & 0x3); - brw_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7); - brw_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7); + elk_inst_set_bits(dst, 95, 92, (uncompacted >> 17)); + elk_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1); + elk_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1); + elk_inst_set_bits(dst, 32, 32, (uncompacted >> 14) & 0x1); + elk_inst_set_bits(dst, 31, 31, (uncompacted >> 13) & 0x1); + elk_inst_set_bits(dst, 28, 28, (uncompacted >> 12) & 0x1); + elk_inst_set_bits(dst, 27, 24, (uncompacted >> 8) & 0xf); + elk_inst_set_bits(dst, 23, 22, (uncompacted >> 6) & 0x3); + elk_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7); + elk_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7); } else if (devinfo->ver >= 8) { - brw_inst_set_bits(dst, 33, 31, (uncompacted >> 16)); - brw_inst_set_bits(dst, 23, 12, (uncompacted >> 4) & 0xfff); - brw_inst_set_bits(dst, 10, 9, (uncompacted >> 2) & 0x3); - brw_inst_set_bits(dst, 34, 34, (uncompacted >> 1) & 0x1); - brw_inst_set_bits(dst, 8, 8, (uncompacted >> 0) & 0x1); + elk_inst_set_bits(dst, 33, 31, (uncompacted >> 16)); + elk_inst_set_bits(dst, 23, 12, (uncompacted >> 4) & 0xfff); + elk_inst_set_bits(dst, 10, 9, (uncompacted >> 2) & 0x3); + elk_inst_set_bits(dst, 34, 34, (uncompacted >> 1) & 0x1); + elk_inst_set_bits(dst, 8, 8, (uncompacted >> 0) & 0x1); } else { - brw_inst_set_bits(dst, 31, 31, (uncompacted >> 16) & 0x1); - brw_inst_set_bits(dst, 23, 8, (uncompacted & 0xffff)); + elk_inst_set_bits(dst, 31, 31, (uncompacted >> 16) & 0x1); + elk_inst_set_bits(dst, 23, 8, (uncompacted & 0xffff)); if (devinfo->ver == 7) - brw_inst_set_bits(dst, 90, 89, uncompacted >> 17); + elk_inst_set_bits(dst, 90, 89, uncompacted >> 17); } } static void -set_uncompacted_datatype(const struct compaction_state *c, brw_inst *dst, - brw_compact_inst *src) +set_uncompacted_datatype(const struct compaction_state *c, elk_inst *dst, + elk_compact_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; uint32_t uncompacted = - c->datatype_table[brw_compact_inst_datatype_index(devinfo, src)]; + c->datatype_table[elk_compact_inst_datatype_index(devinfo, src)]; if (devinfo->ver >= 12) { - brw_inst_set_bits(dst, 98, 98, (uncompacted >> 19)); - brw_inst_set_bits(dst, 91, 88, (uncompacted >> 15) & 0xf); - brw_inst_set_bits(dst, 66, 66, (uncompacted >> 14) & 0x1); - brw_inst_set_bits(dst, 50, 50, (uncompacted >> 13) & 0x1); - brw_inst_set_bits(dst, 49, 48, (uncompacted >> 11) & 0x3); - brw_inst_set_bits(dst, 47, 47, (uncompacted >> 10) & 0x1); - brw_inst_set_bits(dst, 46, 46, (uncompacted >> 9) & 0x1); - brw_inst_set_bits(dst, 43, 40, (uncompacted >> 5) & 0xf); - brw_inst_set_bits(dst, 39, 36, (uncompacted >> 1) & 0xf); - brw_inst_set_bits(dst, 35, 35, (uncompacted >> 0) & 0x1); + elk_inst_set_bits(dst, 98, 98, (uncompacted >> 19)); + elk_inst_set_bits(dst, 91, 88, (uncompacted >> 15) & 0xf); + elk_inst_set_bits(dst, 66, 66, (uncompacted >> 14) & 0x1); + elk_inst_set_bits(dst, 50, 50, (uncompacted >> 13) & 0x1); + elk_inst_set_bits(dst, 49, 48, (uncompacted >> 11) & 0x3); + elk_inst_set_bits(dst, 47, 47, (uncompacted >> 10) & 0x1); + elk_inst_set_bits(dst, 46, 46, (uncompacted >> 9) & 0x1); + elk_inst_set_bits(dst, 43, 40, (uncompacted >> 5) & 0xf); + elk_inst_set_bits(dst, 39, 36, (uncompacted >> 1) & 0xf); + elk_inst_set_bits(dst, 35, 35, (uncompacted >> 0) & 0x1); } else if (devinfo->ver >= 8) { - brw_inst_set_bits(dst, 63, 61, (uncompacted >> 18)); - brw_inst_set_bits(dst, 94, 89, (uncompacted >> 12) & 0x3f); - brw_inst_set_bits(dst, 46, 35, (uncompacted >> 0) & 0xfff); + elk_inst_set_bits(dst, 63, 61, (uncompacted >> 18)); + elk_inst_set_bits(dst, 94, 89, (uncompacted >> 12) & 0x3f); + elk_inst_set_bits(dst, 46, 35, (uncompacted >> 0) & 0xfff); } else { - brw_inst_set_bits(dst, 63, 61, (uncompacted >> 15)); - brw_inst_set_bits(dst, 46, 32, (uncompacted & 0x7fff)); + elk_inst_set_bits(dst, 63, 61, (uncompacted >> 15)); + elk_inst_set_bits(dst, 46, 32, (uncompacted & 0x7fff)); } } static void -set_uncompacted_subreg(const struct compaction_state *c, brw_inst *dst, - brw_compact_inst *src) +set_uncompacted_subreg(const struct compaction_state *c, elk_inst *dst, + elk_compact_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; uint16_t uncompacted = - c->subreg_table[brw_compact_inst_subreg_index(devinfo, src)]; + c->subreg_table[elk_compact_inst_subreg_index(devinfo, src)]; if (devinfo->ver >= 20) { - brw_inst_set_bits(dst, 33, 33, (uncompacted >> 0) & 0x1); - brw_inst_set_bits(dst, 55, 51, (uncompacted >> 1) & 0x1f); - brw_inst_set_bits(dst, 71, 67, (uncompacted >> 6) & 0x1f); - brw_inst_set_bits(dst, 87, 87, (uncompacted >> 11) & 0x1); + elk_inst_set_bits(dst, 33, 33, (uncompacted >> 0) & 0x1); + elk_inst_set_bits(dst, 55, 51, (uncompacted >> 1) & 0x1f); + elk_inst_set_bits(dst, 71, 67, (uncompacted >> 6) & 0x1f); + elk_inst_set_bits(dst, 87, 87, (uncompacted >> 11) & 0x1); } else if (devinfo->ver >= 12) { - brw_inst_set_bits(dst, 103, 99, (uncompacted >> 10)); - brw_inst_set_bits(dst, 71, 67, (uncompacted >> 5) & 0x1f); - brw_inst_set_bits(dst, 55, 51, (uncompacted >> 0) & 0x1f); + elk_inst_set_bits(dst, 103, 99, (uncompacted >> 10)); + elk_inst_set_bits(dst, 71, 67, (uncompacted >> 5) & 0x1f); + elk_inst_set_bits(dst, 55, 51, (uncompacted >> 0) & 0x1f); } else { - brw_inst_set_bits(dst, 100, 96, (uncompacted >> 10)); - brw_inst_set_bits(dst, 68, 64, (uncompacted >> 5) & 0x1f); - brw_inst_set_bits(dst, 52, 48, (uncompacted >> 0) & 0x1f); + elk_inst_set_bits(dst, 100, 96, (uncompacted >> 10)); + elk_inst_set_bits(dst, 68, 64, (uncompacted >> 5) & 0x1f); + elk_inst_set_bits(dst, 52, 48, (uncompacted >> 0) & 0x1f); } } static void -set_uncompacted_src0(const struct compaction_state *c, brw_inst *dst, - brw_compact_inst *src) +set_uncompacted_src0(const struct compaction_state *c, elk_inst *dst, + elk_compact_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; - uint32_t compacted = brw_compact_inst_src0_index(devinfo, src); + uint32_t compacted = elk_compact_inst_src0_index(devinfo, src); uint16_t uncompacted = c->src0_index_table[compacted]; if (devinfo->ver >= 12) { if (devinfo->ver < 20) - brw_inst_set_bits(dst, 87, 87, (uncompacted >> 11) & 0x1); - brw_inst_set_bits(dst, 86, 84, (uncompacted >> 8) & 0x7); - brw_inst_set_bits(dst, 83, 81, (uncompacted >> 5) & 0x7); - brw_inst_set_bits(dst, 80, 80, (uncompacted >> 4) & 0x1); - brw_inst_set_bits(dst, 65, 64, (uncompacted >> 2) & 0x3); - brw_inst_set_bits(dst, 45, 44, (uncompacted >> 0) & 0x3); + elk_inst_set_bits(dst, 87, 87, (uncompacted >> 11) & 0x1); + elk_inst_set_bits(dst, 86, 84, (uncompacted >> 8) & 0x7); + elk_inst_set_bits(dst, 83, 81, (uncompacted >> 5) & 0x7); + elk_inst_set_bits(dst, 80, 80, (uncompacted >> 4) & 0x1); + elk_inst_set_bits(dst, 65, 64, (uncompacted >> 2) & 0x3); + elk_inst_set_bits(dst, 45, 44, (uncompacted >> 0) & 0x3); } else { - brw_inst_set_bits(dst, 88, 77, uncompacted); + elk_inst_set_bits(dst, 88, 77, uncompacted); } } static void -set_uncompacted_src1(const struct compaction_state *c, brw_inst *dst, - brw_compact_inst *src) +set_uncompacted_src1(const struct compaction_state *c, elk_inst *dst, + elk_compact_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; uint16_t uncompacted = - c->src1_index_table[brw_compact_inst_src1_index(devinfo, src)]; + c->src1_index_table[elk_compact_inst_src1_index(devinfo, src)]; if (devinfo->ver >= 20) { - brw_inst_set_bits(dst, 121, 120, (uncompacted >> 14) & 0x3); - brw_inst_set_bits(dst, 118, 116, (uncompacted >> 11) & 0x7); - brw_inst_set_bits(dst, 115, 113, (uncompacted >> 8) & 0x7); - brw_inst_set_bits(dst, 112, 112, (uncompacted >> 7) & 0x1); - brw_inst_set_bits(dst, 103, 99, (uncompacted >> 2) & 0x1f); - brw_inst_set_bits(dst, 97, 96, (uncompacted >> 0) & 0x3); + elk_inst_set_bits(dst, 121, 120, (uncompacted >> 14) & 0x3); + elk_inst_set_bits(dst, 118, 116, (uncompacted >> 11) & 0x7); + elk_inst_set_bits(dst, 115, 113, (uncompacted >> 8) & 0x7); + elk_inst_set_bits(dst, 112, 112, (uncompacted >> 7) & 0x1); + elk_inst_set_bits(dst, 103, 99, (uncompacted >> 2) & 0x1f); + elk_inst_set_bits(dst, 97, 96, (uncompacted >> 0) & 0x3); } else if (devinfo->ver >= 12) { - brw_inst_set_bits(dst, 121, 120, (uncompacted >> 10)); - brw_inst_set_bits(dst, 119, 116, (uncompacted >> 6) & 0xf); - brw_inst_set_bits(dst, 115, 113, (uncompacted >> 3) & 0x7); - brw_inst_set_bits(dst, 112, 112, (uncompacted >> 2) & 0x1); - brw_inst_set_bits(dst, 97, 96, (uncompacted >> 0) & 0x3); + elk_inst_set_bits(dst, 121, 120, (uncompacted >> 10)); + elk_inst_set_bits(dst, 119, 116, (uncompacted >> 6) & 0xf); + elk_inst_set_bits(dst, 115, 113, (uncompacted >> 3) & 0x7); + elk_inst_set_bits(dst, 112, 112, (uncompacted >> 2) & 0x1); + elk_inst_set_bits(dst, 97, 96, (uncompacted >> 0) & 0x3); } else { - brw_inst_set_bits(dst, 120, 109, uncompacted); + elk_inst_set_bits(dst, 120, 109, uncompacted); } } static void set_uncompacted_3src_control_index(const struct compaction_state *c, - brw_inst *dst, brw_compact_inst *src, + elk_inst *dst, elk_compact_inst *src, bool is_dpas) { const struct intel_device_info *devinfo = c->isa->devinfo; assert(devinfo->ver >= 8); if (devinfo->ver >= 20) { - uint64_t compacted = brw_compact_inst_3src_control_index(devinfo, src); + uint64_t compacted = elk_compact_inst_3src_control_index(devinfo, src); uint64_t uncompacted = is_dpas ? xe2_3src_dpas_control_index_table[compacted] : xe2_3src_control_index_table[compacted]; - brw_inst_set_bits(dst, 95, 92, (uncompacted >> 30) & 0xf); - brw_inst_set_bits(dst, 90, 88, (uncompacted >> 27) & 0x7); - brw_inst_set_bits(dst, 82, 80, (uncompacted >> 24) & 0x7); - brw_inst_set_bits(dst, 50, 50, (uncompacted >> 23) & 0x1); - brw_inst_set_bits(dst, 49, 48, (uncompacted >> 21) & 0x3); - brw_inst_set_bits(dst, 42, 40, (uncompacted >> 18) & 0x7); - brw_inst_set_bits(dst, 39, 39, (uncompacted >> 17) & 0x1); - brw_inst_set_bits(dst, 38, 36, (uncompacted >> 14) & 0x7); - brw_inst_set_bits(dst, 34, 34, (uncompacted >> 13) & 0x1); - brw_inst_set_bits(dst, 32, 32, (uncompacted >> 12) & 0x1); - brw_inst_set_bits(dst, 31, 31, (uncompacted >> 11) & 0x1); - brw_inst_set_bits(dst, 28, 28, (uncompacted >> 10) & 0x1); - brw_inst_set_bits(dst, 27, 26, (uncompacted >> 8) & 0x3); - brw_inst_set_bits(dst, 25, 24, (uncompacted >> 6) & 0x3); - brw_inst_set_bits(dst, 23, 21, (uncompacted >> 3) & 0x7); - brw_inst_set_bits(dst, 20, 18, (uncompacted >> 0) & 0x7); + elk_inst_set_bits(dst, 95, 92, (uncompacted >> 30) & 0xf); + elk_inst_set_bits(dst, 90, 88, (uncompacted >> 27) & 0x7); + elk_inst_set_bits(dst, 82, 80, (uncompacted >> 24) & 0x7); + elk_inst_set_bits(dst, 50, 50, (uncompacted >> 23) & 0x1); + elk_inst_set_bits(dst, 49, 48, (uncompacted >> 21) & 0x3); + elk_inst_set_bits(dst, 42, 40, (uncompacted >> 18) & 0x7); + elk_inst_set_bits(dst, 39, 39, (uncompacted >> 17) & 0x1); + elk_inst_set_bits(dst, 38, 36, (uncompacted >> 14) & 0x7); + elk_inst_set_bits(dst, 34, 34, (uncompacted >> 13) & 0x1); + elk_inst_set_bits(dst, 32, 32, (uncompacted >> 12) & 0x1); + elk_inst_set_bits(dst, 31, 31, (uncompacted >> 11) & 0x1); + elk_inst_set_bits(dst, 28, 28, (uncompacted >> 10) & 0x1); + elk_inst_set_bits(dst, 27, 26, (uncompacted >> 8) & 0x3); + elk_inst_set_bits(dst, 25, 24, (uncompacted >> 6) & 0x3); + elk_inst_set_bits(dst, 23, 21, (uncompacted >> 3) & 0x7); + elk_inst_set_bits(dst, 20, 18, (uncompacted >> 0) & 0x7); } else if (devinfo->verx10 >= 125) { - uint64_t compacted = brw_compact_inst_3src_control_index(devinfo, src); + uint64_t compacted = elk_compact_inst_3src_control_index(devinfo, src); uint64_t uncompacted = xehp_3src_control_index_table[compacted]; - brw_inst_set_bits(dst, 95, 92, (uncompacted >> 33)); - brw_inst_set_bits(dst, 90, 88, (uncompacted >> 30) & 0x7); - brw_inst_set_bits(dst, 82, 80, (uncompacted >> 27) & 0x7); - brw_inst_set_bits(dst, 50, 50, (uncompacted >> 26) & 0x1); - brw_inst_set_bits(dst, 49, 48, (uncompacted >> 24) & 0x3); - brw_inst_set_bits(dst, 42, 40, (uncompacted >> 21) & 0x7); - brw_inst_set_bits(dst, 39, 39, (uncompacted >> 20) & 0x1); - brw_inst_set_bits(dst, 38, 36, (uncompacted >> 17) & 0x7); - brw_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1); - brw_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1); - brw_inst_set_bits(dst, 32, 32, (uncompacted >> 14) & 0x1); - brw_inst_set_bits(dst, 31, 31, (uncompacted >> 13) & 0x1); - brw_inst_set_bits(dst, 28, 28, (uncompacted >> 12) & 0x1); - brw_inst_set_bits(dst, 27, 24, (uncompacted >> 8) & 0xf); - brw_inst_set_bits(dst, 23, 23, (uncompacted >> 7) & 0x1); - brw_inst_set_bits(dst, 22, 22, (uncompacted >> 6) & 0x1); - brw_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7); - brw_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7); + elk_inst_set_bits(dst, 95, 92, (uncompacted >> 33)); + elk_inst_set_bits(dst, 90, 88, (uncompacted >> 30) & 0x7); + elk_inst_set_bits(dst, 82, 80, (uncompacted >> 27) & 0x7); + elk_inst_set_bits(dst, 50, 50, (uncompacted >> 26) & 0x1); + elk_inst_set_bits(dst, 49, 48, (uncompacted >> 24) & 0x3); + elk_inst_set_bits(dst, 42, 40, (uncompacted >> 21) & 0x7); + elk_inst_set_bits(dst, 39, 39, (uncompacted >> 20) & 0x1); + elk_inst_set_bits(dst, 38, 36, (uncompacted >> 17) & 0x7); + elk_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1); + elk_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1); + elk_inst_set_bits(dst, 32, 32, (uncompacted >> 14) & 0x1); + elk_inst_set_bits(dst, 31, 31, (uncompacted >> 13) & 0x1); + elk_inst_set_bits(dst, 28, 28, (uncompacted >> 12) & 0x1); + elk_inst_set_bits(dst, 27, 24, (uncompacted >> 8) & 0xf); + elk_inst_set_bits(dst, 23, 23, (uncompacted >> 7) & 0x1); + elk_inst_set_bits(dst, 22, 22, (uncompacted >> 6) & 0x1); + elk_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7); + elk_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7); } else if (devinfo->ver >= 12) { - uint64_t compacted = brw_compact_inst_3src_control_index(devinfo, src); + uint64_t compacted = elk_compact_inst_3src_control_index(devinfo, src); uint64_t uncompacted = gfx12_3src_control_index_table[compacted]; - brw_inst_set_bits(dst, 95, 92, (uncompacted >> 32)); - brw_inst_set_bits(dst, 90, 88, (uncompacted >> 29) & 0x7); - brw_inst_set_bits(dst, 82, 80, (uncompacted >> 26) & 0x7); - brw_inst_set_bits(dst, 50, 50, (uncompacted >> 25) & 0x1); - brw_inst_set_bits(dst, 48, 48, (uncompacted >> 24) & 0x1); - brw_inst_set_bits(dst, 42, 40, (uncompacted >> 21) & 0x7); - brw_inst_set_bits(dst, 39, 39, (uncompacted >> 20) & 0x1); - brw_inst_set_bits(dst, 38, 36, (uncompacted >> 17) & 0x7); - brw_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1); - brw_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1); - brw_inst_set_bits(dst, 32, 32, (uncompacted >> 14) & 0x1); - brw_inst_set_bits(dst, 31, 31, (uncompacted >> 13) & 0x1); - brw_inst_set_bits(dst, 28, 28, (uncompacted >> 12) & 0x1); - brw_inst_set_bits(dst, 27, 24, (uncompacted >> 8) & 0xf); - brw_inst_set_bits(dst, 23, 23, (uncompacted >> 7) & 0x1); - brw_inst_set_bits(dst, 22, 22, (uncompacted >> 6) & 0x1); - brw_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7); - brw_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7); + elk_inst_set_bits(dst, 95, 92, (uncompacted >> 32)); + elk_inst_set_bits(dst, 90, 88, (uncompacted >> 29) & 0x7); + elk_inst_set_bits(dst, 82, 80, (uncompacted >> 26) & 0x7); + elk_inst_set_bits(dst, 50, 50, (uncompacted >> 25) & 0x1); + elk_inst_set_bits(dst, 48, 48, (uncompacted >> 24) & 0x1); + elk_inst_set_bits(dst, 42, 40, (uncompacted >> 21) & 0x7); + elk_inst_set_bits(dst, 39, 39, (uncompacted >> 20) & 0x1); + elk_inst_set_bits(dst, 38, 36, (uncompacted >> 17) & 0x7); + elk_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1); + elk_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1); + elk_inst_set_bits(dst, 32, 32, (uncompacted >> 14) & 0x1); + elk_inst_set_bits(dst, 31, 31, (uncompacted >> 13) & 0x1); + elk_inst_set_bits(dst, 28, 28, (uncompacted >> 12) & 0x1); + elk_inst_set_bits(dst, 27, 24, (uncompacted >> 8) & 0xf); + elk_inst_set_bits(dst, 23, 23, (uncompacted >> 7) & 0x1); + elk_inst_set_bits(dst, 22, 22, (uncompacted >> 6) & 0x1); + elk_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7); + elk_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7); } else { - uint32_t compacted = brw_compact_inst_3src_control_index(devinfo, src); + uint32_t compacted = elk_compact_inst_3src_control_index(devinfo, src); uint32_t uncompacted = gfx8_3src_control_index_table[compacted]; - brw_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7); - brw_inst_set_bits(dst, 28, 8, (uncompacted >> 0) & 0x1fffff); + elk_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7); + elk_inst_set_bits(dst, 28, 8, (uncompacted >> 0) & 0x1fffff); if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) - brw_inst_set_bits(dst, 36, 35, (uncompacted >> 24) & 0x3); + elk_inst_set_bits(dst, 36, 35, (uncompacted >> 24) & 0x3); } } static void set_uncompacted_3src_source_index(const struct intel_device_info *devinfo, - brw_inst *dst, brw_compact_inst *src, + elk_inst *dst, elk_compact_inst *src, bool is_dpas) { assert(devinfo->ver >= 8); - uint32_t compacted = brw_compact_inst_3src_source_index(devinfo, src); + uint32_t compacted = elk_compact_inst_3src_source_index(devinfo, src); if (devinfo->ver >= 12) { const uint32_t *three_src_source_index_table = @@ -2497,68 +2497,68 @@ set_uncompacted_3src_source_index(const struct intel_device_info *devinfo, gfx12_3src_source_index_table; uint32_t uncompacted = three_src_source_index_table[compacted]; - brw_inst_set_bits(dst, 114, 114, (uncompacted >> 20)); - brw_inst_set_bits(dst, 113, 112, (uncompacted >> 18) & 0x3); - brw_inst_set_bits(dst, 98, 98, (uncompacted >> 17) & 0x1); - brw_inst_set_bits(dst, 97, 96, (uncompacted >> 15) & 0x3); - brw_inst_set_bits(dst, 91, 91, (uncompacted >> 14) & 0x1); - brw_inst_set_bits(dst, 87, 86, (uncompacted >> 12) & 0x3); - brw_inst_set_bits(dst, 85, 84, (uncompacted >> 10) & 0x3); - brw_inst_set_bits(dst, 83, 83, (uncompacted >> 9) & 0x1); - brw_inst_set_bits(dst, 66, 66, (uncompacted >> 8) & 0x1); - brw_inst_set_bits(dst, 65, 64, (uncompacted >> 6) & 0x3); - brw_inst_set_bits(dst, 47, 47, (uncompacted >> 5) & 0x1); - brw_inst_set_bits(dst, 46, 46, (uncompacted >> 4) & 0x1); - brw_inst_set_bits(dst, 45, 44, (uncompacted >> 2) & 0x3); - brw_inst_set_bits(dst, 43, 43, (uncompacted >> 1) & 0x1); - brw_inst_set_bits(dst, 35, 35, (uncompacted >> 0) & 0x1); + elk_inst_set_bits(dst, 114, 114, (uncompacted >> 20)); + elk_inst_set_bits(dst, 113, 112, (uncompacted >> 18) & 0x3); + elk_inst_set_bits(dst, 98, 98, (uncompacted >> 17) & 0x1); + elk_inst_set_bits(dst, 97, 96, (uncompacted >> 15) & 0x3); + elk_inst_set_bits(dst, 91, 91, (uncompacted >> 14) & 0x1); + elk_inst_set_bits(dst, 87, 86, (uncompacted >> 12) & 0x3); + elk_inst_set_bits(dst, 85, 84, (uncompacted >> 10) & 0x3); + elk_inst_set_bits(dst, 83, 83, (uncompacted >> 9) & 0x1); + elk_inst_set_bits(dst, 66, 66, (uncompacted >> 8) & 0x1); + elk_inst_set_bits(dst, 65, 64, (uncompacted >> 6) & 0x3); + elk_inst_set_bits(dst, 47, 47, (uncompacted >> 5) & 0x1); + elk_inst_set_bits(dst, 46, 46, (uncompacted >> 4) & 0x1); + elk_inst_set_bits(dst, 45, 44, (uncompacted >> 2) & 0x3); + elk_inst_set_bits(dst, 43, 43, (uncompacted >> 1) & 0x1); + elk_inst_set_bits(dst, 35, 35, (uncompacted >> 0) & 0x1); } else { uint64_t uncompacted = gfx8_3src_source_index_table[compacted]; - brw_inst_set_bits(dst, 83, 83, (uncompacted >> 43) & 0x1); - brw_inst_set_bits(dst, 114, 107, (uncompacted >> 35) & 0xff); - brw_inst_set_bits(dst, 93, 86, (uncompacted >> 27) & 0xff); - brw_inst_set_bits(dst, 72, 65, (uncompacted >> 19) & 0xff); - brw_inst_set_bits(dst, 55, 37, (uncompacted >> 0) & 0x7ffff); + elk_inst_set_bits(dst, 83, 83, (uncompacted >> 43) & 0x1); + elk_inst_set_bits(dst, 114, 107, (uncompacted >> 35) & 0xff); + elk_inst_set_bits(dst, 93, 86, (uncompacted >> 27) & 0xff); + elk_inst_set_bits(dst, 72, 65, (uncompacted >> 19) & 0xff); + elk_inst_set_bits(dst, 55, 37, (uncompacted >> 0) & 0x7ffff); if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { - brw_inst_set_bits(dst, 126, 125, (uncompacted >> 47) & 0x3); - brw_inst_set_bits(dst, 105, 104, (uncompacted >> 45) & 0x3); - brw_inst_set_bits(dst, 84, 84, (uncompacted >> 44) & 0x1); + elk_inst_set_bits(dst, 126, 125, (uncompacted >> 47) & 0x3); + elk_inst_set_bits(dst, 105, 104, (uncompacted >> 45) & 0x3); + elk_inst_set_bits(dst, 84, 84, (uncompacted >> 44) & 0x1); } else { - brw_inst_set_bits(dst, 125, 125, (uncompacted >> 45) & 0x1); - brw_inst_set_bits(dst, 104, 104, (uncompacted >> 44) & 0x1); + elk_inst_set_bits(dst, 125, 125, (uncompacted >> 45) & 0x1); + elk_inst_set_bits(dst, 104, 104, (uncompacted >> 44) & 0x1); } } } static void set_uncompacted_3src_subreg_index(const struct intel_device_info *devinfo, - brw_inst *dst, brw_compact_inst *src) + elk_inst *dst, elk_compact_inst *src) { assert(devinfo->ver >= 12); - uint32_t compacted = brw_compact_inst_3src_subreg_index(devinfo, src); + uint32_t compacted = elk_compact_inst_3src_subreg_index(devinfo, src); uint32_t uncompacted = (devinfo->ver >= 20 ? xe2_3src_subreg_table[compacted]: gfx12_3src_subreg_table[compacted]); - brw_inst_set_bits(dst, 119, 115, (uncompacted >> 15)); - brw_inst_set_bits(dst, 103, 99, (uncompacted >> 10) & 0x1f); - brw_inst_set_bits(dst, 71, 67, (uncompacted >> 5) & 0x1f); - brw_inst_set_bits(dst, 55, 51, (uncompacted >> 0) & 0x1f); + elk_inst_set_bits(dst, 119, 115, (uncompacted >> 15)); + elk_inst_set_bits(dst, 103, 99, (uncompacted >> 10) & 0x1f); + elk_inst_set_bits(dst, 71, 67, (uncompacted >> 5) & 0x1f); + elk_inst_set_bits(dst, 55, 51, (uncompacted >> 0) & 0x1f); } static void -brw_uncompact_3src_instruction(const struct compaction_state *c, - brw_inst *dst, brw_compact_inst *src, bool is_dpas) +elk_uncompact_3src_instruction(const struct compaction_state *c, + elk_inst *dst, elk_compact_inst *src, bool is_dpas) { const struct intel_device_info *devinfo = c->isa->devinfo; assert(devinfo->ver >= 8); #define uncompact(field) \ - brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src)) + elk_inst_set_3src_##field(devinfo, dst, elk_compact_inst_3src_##field(devinfo, src)) #define uncompact_a16(field) \ - brw_inst_set_3src_a16_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src)) + elk_inst_set_3src_a16_##field(devinfo, dst, elk_compact_inst_3src_##field(devinfo, src)) uncompact(hw_opcode); @@ -2590,34 +2590,34 @@ brw_uncompact_3src_instruction(const struct compaction_state *c, uncompact_a16(src1_subreg_nr); uncompact_a16(src2_subreg_nr); } - brw_inst_set_3src_cmpt_control(devinfo, dst, false); + elk_inst_set_3src_cmpt_control(devinfo, dst, false); #undef uncompact #undef uncompact_a16 } static void -uncompact_instruction(const struct compaction_state *c, brw_inst *dst, - brw_compact_inst *src) +uncompact_instruction(const struct compaction_state *c, elk_inst *dst, + elk_compact_inst *src) { const struct intel_device_info *devinfo = c->isa->devinfo; memset(dst, 0, sizeof(*dst)); if (devinfo->ver >= 8) { - const enum opcode opcode = - brw_opcode_decode(c->isa, brw_compact_inst_3src_hw_opcode(devinfo, src)); - if (is_3src(c->isa, opcode)) { - const bool is_dpas = opcode == BRW_OPCODE_DPAS; - brw_uncompact_3src_instruction(c, dst, src, is_dpas); + const enum elk_opcode opcode = + elk_opcode_decode(c->isa, elk_compact_inst_3src_hw_opcode(devinfo, src)); + if (elk_is_3src(c->isa, opcode)) { + const bool is_dpas = opcode == ELK_OPCODE_DPAS; + elk_uncompact_3src_instruction(c, dst, src, is_dpas); return; } } #define uncompact(field) \ - brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src)) + elk_inst_set_##field(devinfo, dst, elk_compact_inst_##field(devinfo, src)) #define uncompact_reg(field) \ - brw_inst_set_##field##_da_reg_nr(devinfo, dst, \ - brw_compact_inst_##field##_reg_nr(devinfo, src)) + elk_inst_set_##field##_da_reg_nr(devinfo, dst, \ + elk_compact_inst_##field##_reg_nr(devinfo, src)) uncompact(hw_opcode); uncompact(debug_control); @@ -2627,11 +2627,11 @@ uncompact_instruction(const struct compaction_state *c, brw_inst *dst, set_uncompacted_subreg(c, dst, src); set_uncompacted_src0(c, dst, src); - enum brw_reg_type type; + enum elk_reg_type type; if (has_immediate(devinfo, dst, &type)) { unsigned imm = uncompact_immediate(devinfo, type, - brw_compact_inst_imm(devinfo, src)); - brw_inst_set_imm_ud(devinfo, dst, imm); + elk_compact_inst_imm(devinfo, src)); + elk_inst_set_imm_ud(devinfo, dst, imm); } else { set_uncompacted_src1(c, dst, src); uncompact_reg(src1); @@ -2656,15 +2656,15 @@ uncompact_instruction(const struct compaction_state *c, brw_inst *dst, uncompact_reg(dst); uncompact_reg(src0); } - brw_inst_set_cmpt_control(devinfo, dst, false); + elk_inst_set_cmpt_control(devinfo, dst, false); #undef uncompact #undef uncompact_reg } void -brw_uncompact_instruction(const struct brw_isa_info *isa, - brw_inst *dst, brw_compact_inst *src) +elk_uncompact_instruction(const struct elk_isa_info *isa, + elk_inst *dst, elk_compact_inst *src) { struct compaction_state c; compaction_state_init(&c, isa); @@ -2672,18 +2672,18 @@ brw_uncompact_instruction(const struct brw_isa_info *isa, } void -brw_debug_compact_uncompact(const struct brw_isa_info *isa, - brw_inst *orig, - brw_inst *uncompacted) +elk_debug_compact_uncompact(const struct elk_isa_info *isa, + elk_inst *orig, + elk_inst *uncompacted) { fprintf(stderr, "Instruction compact/uncompact changed (gen%d):\n", isa->devinfo->ver); fprintf(stderr, " before: "); - brw_disassemble_inst(stderr, isa, orig, true, 0, NULL); + elk_disassemble_inst(stderr, isa, orig, true, 0, NULL); fprintf(stderr, " after: "); - brw_disassemble_inst(stderr, isa, uncompacted, false, 0, NULL); + elk_disassemble_inst(stderr, isa, uncompacted, false, 0, NULL); uint32_t *before_bits = (uint32_t *)orig; uint32_t *after_bits = (uint32_t *)uncompacted; @@ -2709,7 +2709,7 @@ compacted_between(int old_ip, int old_target_ip, int *compacted_counts) } static void -update_uip_jip(const struct brw_isa_info *isa, brw_inst *insn, +update_uip_jip(const struct elk_isa_info *isa, elk_inst *insn, int this_old_ip, int *compacted_counts) { const struct intel_device_info *devinfo = isa->devinfo; @@ -2720,26 +2720,26 @@ update_uip_jip(const struct brw_isa_info *isa, brw_inst *insn, */ int shift = devinfo->ver >= 8 ? 3 : 0; - int32_t jip_compacted = brw_inst_jip(devinfo, insn) >> shift; + int32_t jip_compacted = elk_inst_jip(devinfo, insn) >> shift; jip_compacted -= compacted_between(this_old_ip, this_old_ip + (jip_compacted / 2), compacted_counts); - brw_inst_set_jip(devinfo, insn, jip_compacted << shift); + elk_inst_set_jip(devinfo, insn, jip_compacted << shift); - if (brw_inst_opcode(isa, insn) == BRW_OPCODE_ENDIF || - brw_inst_opcode(isa, insn) == BRW_OPCODE_WHILE || - (brw_inst_opcode(isa, insn) == BRW_OPCODE_ELSE && devinfo->ver <= 7)) + if (elk_inst_opcode(isa, insn) == ELK_OPCODE_ENDIF || + elk_inst_opcode(isa, insn) == ELK_OPCODE_WHILE || + (elk_inst_opcode(isa, insn) == ELK_OPCODE_ELSE && devinfo->ver <= 7)) return; - int32_t uip_compacted = brw_inst_uip(devinfo, insn) >> shift; + int32_t uip_compacted = elk_inst_uip(devinfo, insn) >> shift; uip_compacted -= compacted_between(this_old_ip, this_old_ip + (uip_compacted / 2), compacted_counts); - brw_inst_set_uip(devinfo, insn, uip_compacted << shift); + elk_inst_set_uip(devinfo, insn, uip_compacted << shift); } static void -update_gfx4_jump_count(const struct intel_device_info *devinfo, brw_inst *insn, +update_gfx4_jump_count(const struct intel_device_info *devinfo, elk_inst *insn, int this_old_ip, int *compacted_counts) { assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X); @@ -2750,7 +2750,7 @@ update_gfx4_jump_count(const struct intel_device_info *devinfo, brw_inst *insn, */ int shift = devinfo->platform == INTEL_PLATFORM_G4X ? 1 : 0; - int jump_count_compacted = brw_inst_gfx4_jump_count(devinfo, insn) << shift; + int jump_count_compacted = elk_inst_gfx4_jump_count(devinfo, insn) << shift; int target_old_ip = this_old_ip + (jump_count_compacted / 2); @@ -2758,12 +2758,12 @@ update_gfx4_jump_count(const struct intel_device_info *devinfo, brw_inst *insn, int target_compacted_count = compacted_counts[target_old_ip]; jump_count_compacted -= (target_compacted_count - this_compacted_count); - brw_inst_set_gfx4_jump_count(devinfo, insn, jump_count_compacted >> shift); + elk_inst_set_gfx4_jump_count(devinfo, insn, jump_count_compacted >> shift); } static void compaction_state_init(struct compaction_state *c, - const struct brw_isa_info *isa) + const struct elk_isa_info *isa) { const struct intel_device_info *devinfo = isa->devinfo; @@ -2861,8 +2861,8 @@ compaction_state_init(struct compaction_state *c, } void -brw_compact_instructions(struct brw_codegen *p, int start_offset, - struct disasm_info *disasm) +elk_compact_instructions(struct elk_codegen *p, int start_offset, + struct elk_disasm_info *disasm) { if (INTEL_DEBUG(DEBUG_NO_COMPACTION)) return; @@ -2877,7 +2877,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, * that preceded it. */ unsigned num_compacted_counts = - (p->next_insn_offset - start_offset) / sizeof(brw_inst); + (p->next_insn_offset - start_offset) / sizeof(elk_inst); int *compacted_counts = calloc(1, sizeof(*compacted_counts) * num_compacted_counts); @@ -2885,7 +2885,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, * (in 16-byte units) before compaction. */ unsigned num_old_ip = - (p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) + 1; + (p->next_insn_offset - start_offset) / sizeof(elk_compact_inst) + 1; int *old_ip = calloc(1, sizeof(*old_ip) * num_old_ip); struct compaction_state c; @@ -2894,42 +2894,42 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, int offset = 0; int compacted_count = 0; for (int src_offset = 0; src_offset < p->next_insn_offset - start_offset; - src_offset += sizeof(brw_inst)) { - brw_inst *src = store + src_offset; + src_offset += sizeof(elk_inst)) { + elk_inst *src = store + src_offset; void *dst = store + offset; - old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_inst); - compacted_counts[src_offset / sizeof(brw_inst)] = compacted_count; + old_ip[offset / sizeof(elk_compact_inst)] = src_offset / sizeof(elk_inst); + compacted_counts[src_offset / sizeof(elk_inst)] = compacted_count; - brw_inst inst = precompact(p->isa, *src); - brw_inst saved = inst; + elk_inst inst = precompact(p->isa, *src); + elk_inst saved = inst; if (try_compact_instruction(&c, dst, &inst)) { compacted_count++; if (INTEL_DEBUG(DEBUG_VS | DEBUG_GS | DEBUG_TCS | DEBUG_WM | DEBUG_CS | DEBUG_TES)) { - brw_inst uncompacted; + elk_inst uncompacted; uncompact_instruction(&c, &uncompacted, dst); if (memcmp(&saved, &uncompacted, sizeof(uncompacted))) { - brw_debug_compact_uncompact(p->isa, &saved, &uncompacted); + elk_debug_compact_uncompact(p->isa, &saved, &uncompacted); } } - offset += sizeof(brw_compact_inst); + offset += sizeof(elk_compact_inst); } else { /* All uncompacted instructions need to be aligned on G45. */ - if ((offset & sizeof(brw_compact_inst)) != 0 && + if ((offset & sizeof(elk_compact_inst)) != 0 && devinfo->platform == INTEL_PLATFORM_G4X) { - brw_compact_inst *align = store + offset; + elk_compact_inst *align = store + offset; memset(align, 0, sizeof(*align)); - brw_compact_inst_set_hw_opcode( - devinfo, align, brw_opcode_encode(p->isa, BRW_OPCODE_NENOP)); - brw_compact_inst_set_cmpt_control(devinfo, align, true); - offset += sizeof(brw_compact_inst); + elk_compact_inst_set_hw_opcode( + devinfo, align, elk_opcode_encode(p->isa, ELK_OPCODE_NENOP)); + elk_compact_inst_set_cmpt_control(devinfo, align, true); + offset += sizeof(elk_compact_inst); compacted_count--; - compacted_counts[src_offset / sizeof(brw_inst)] = compacted_count; - old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_inst); + compacted_counts[src_offset / sizeof(elk_inst)] = compacted_count; + old_ip[offset / sizeof(elk_compact_inst)] = src_offset / sizeof(elk_inst); dst = store + offset; } @@ -2938,30 +2938,30 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, * place. */ if (offset != src_offset) { - memmove(dst, src, sizeof(brw_inst)); + memmove(dst, src, sizeof(elk_inst)); } - offset += sizeof(brw_inst); + offset += sizeof(elk_inst); } } /* Add an entry for the ending offset of the program. This greatly * simplifies the linked list walk at the end of the function. */ - old_ip[offset / sizeof(brw_compact_inst)] = - (p->next_insn_offset - start_offset) / sizeof(brw_inst); + old_ip[offset / sizeof(elk_compact_inst)] = + (p->next_insn_offset - start_offset) / sizeof(elk_inst); /* Fix up control flow offsets. */ p->next_insn_offset = start_offset + offset; for (offset = 0; offset < p->next_insn_offset - start_offset; offset = next_offset(devinfo, store, offset)) { - brw_inst *insn = store + offset; - int this_old_ip = old_ip[offset / sizeof(brw_compact_inst)]; + elk_inst *insn = store + offset; + int this_old_ip = old_ip[offset / sizeof(elk_compact_inst)]; int this_compacted_count = compacted_counts[this_old_ip]; - switch (brw_inst_opcode(p->isa, insn)) { - case BRW_OPCODE_BREAK: - case BRW_OPCODE_CONTINUE: - case BRW_OPCODE_HALT: + switch (elk_inst_opcode(p->isa, insn)) { + case ELK_OPCODE_BREAK: + case ELK_OPCODE_CONTINUE: + case ELK_OPCODE_HALT: if (devinfo->ver >= 6) { update_uip_jip(p->isa, insn, this_old_ip, compacted_counts); } else { @@ -2970,61 +2970,61 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, } break; - case BRW_OPCODE_IF: - case BRW_OPCODE_IFF: - case BRW_OPCODE_ELSE: - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_WHILE: + case ELK_OPCODE_IF: + case ELK_OPCODE_IFF: + case ELK_OPCODE_ELSE: + case ELK_OPCODE_ENDIF: + case ELK_OPCODE_WHILE: if (devinfo->ver >= 7) { - if (brw_inst_cmpt_control(devinfo, insn)) { - brw_inst uncompacted; + if (elk_inst_cmpt_control(devinfo, insn)) { + elk_inst uncompacted; uncompact_instruction(&c, &uncompacted, - (brw_compact_inst *)insn); + (elk_compact_inst *)insn); update_uip_jip(p->isa, &uncompacted, this_old_ip, compacted_counts); - bool ret = try_compact_instruction(&c, (brw_compact_inst *)insn, + bool ret = try_compact_instruction(&c, (elk_compact_inst *)insn, &uncompacted); assert(ret); (void)ret; } else { update_uip_jip(p->isa, insn, this_old_ip, compacted_counts); } } else if (devinfo->ver == 6) { - assert(!brw_inst_cmpt_control(devinfo, insn)); + assert(!elk_inst_cmpt_control(devinfo, insn)); /* Jump Count is in units of compacted instructions on Gfx6. */ - int jump_count_compacted = brw_inst_gfx6_jump_count(devinfo, insn); + int jump_count_compacted = elk_inst_gfx6_jump_count(devinfo, insn); int target_old_ip = this_old_ip + (jump_count_compacted / 2); int target_compacted_count = compacted_counts[target_old_ip]; jump_count_compacted -= (target_compacted_count - this_compacted_count); - brw_inst_set_gfx6_jump_count(devinfo, insn, jump_count_compacted); + elk_inst_set_gfx6_jump_count(devinfo, insn, jump_count_compacted); } else { update_gfx4_jump_count(devinfo, insn, this_old_ip, compacted_counts); } break; - case BRW_OPCODE_ADD: + case ELK_OPCODE_ADD: /* Add instructions modifying the IP register use an immediate src1, * and Gens that use this cannot compact instructions with immediate * operands. */ - if (brw_inst_cmpt_control(devinfo, insn)) + if (elk_inst_cmpt_control(devinfo, insn)) break; - if (brw_inst_dst_reg_file(devinfo, insn) == BRW_ARCHITECTURE_REGISTER_FILE && - brw_inst_dst_da_reg_nr(devinfo, insn) == BRW_ARF_IP) { - assert(brw_inst_src1_reg_file(devinfo, insn) == BRW_IMMEDIATE_VALUE); + if (elk_inst_dst_reg_file(devinfo, insn) == ELK_ARCHITECTURE_REGISTER_FILE && + elk_inst_dst_da_reg_nr(devinfo, insn) == ELK_ARF_IP) { + assert(elk_inst_src1_reg_file(devinfo, insn) == ELK_IMMEDIATE_VALUE); int shift = 3; - int jump_compacted = brw_inst_imm_d(devinfo, insn) >> shift; + int jump_compacted = elk_inst_imm_d(devinfo, insn) >> shift; int target_old_ip = this_old_ip + (jump_compacted / 2); int target_compacted_count = compacted_counts[target_old_ip]; jump_compacted -= (target_compacted_count - this_compacted_count); - brw_inst_set_imm_ud(devinfo, insn, jump_compacted << shift); + elk_inst_set_imm_ud(devinfo, insn, jump_compacted << shift); } break; @@ -3038,15 +3038,15 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, * alignment padding, so that the next compression pass (for the FS 8/16 * compile passes) parses correctly. */ - if (p->next_insn_offset & sizeof(brw_compact_inst)) { - brw_compact_inst *align = store + offset; + if (p->next_insn_offset & sizeof(elk_compact_inst)) { + elk_compact_inst *align = store + offset; memset(align, 0, sizeof(*align)); - brw_compact_inst_set_hw_opcode( - devinfo, align, brw_opcode_encode(p->isa, BRW_OPCODE_NOP)); - brw_compact_inst_set_cmpt_control(devinfo, align, true); - p->next_insn_offset += sizeof(brw_compact_inst); + elk_compact_inst_set_hw_opcode( + devinfo, align, elk_opcode_encode(p->isa, ELK_OPCODE_NOP)); + elk_compact_inst_set_cmpt_control(devinfo, align, true); + p->next_insn_offset += sizeof(elk_compact_inst); } - p->nr_insn = p->next_insn_offset / sizeof(brw_inst); + p->nr_insn = p->next_insn_offset / sizeof(elk_inst); for (int i = 0; i < p->num_relocs; i++) { if (p->relocs[i].offset < (uint32_t)start_offset) @@ -3062,10 +3062,10 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, int offset = 0; foreach_list_typed(struct inst_group, group, link, &disasm->group_list) { - while (start_offset + old_ip[offset / sizeof(brw_compact_inst)] * - sizeof(brw_inst) != group->offset) { - assert(start_offset + old_ip[offset / sizeof(brw_compact_inst)] * - sizeof(brw_inst) < group->offset); + while (start_offset + old_ip[offset / sizeof(elk_compact_inst)] * + sizeof(elk_inst) != group->offset) { + assert(start_offset + old_ip[offset / sizeof(elk_compact_inst)] * + sizeof(elk_inst) < group->offset); offset = next_offset(devinfo, store, offset); } diff --git a/src/intel/compiler/elk/elk_eu_defines.h b/src/intel/compiler/elk/elk_eu_defines.h index fb38fdac15b..42e90df9704 100644 --- a/src/intel/compiler/elk/elk_eu_defines.h +++ b/src/intel/compiler/elk/elk_eu_defines.h @@ -64,7 +64,7 @@ #define URB_WRITE_PRIM_START 0x2 #define URB_WRITE_PRIM_TYPE_SHIFT 2 -#define BRW_SPRITE_POINT_ENABLE 16 +#define ELK_SPRITE_POINT_ENABLE 16 # define GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0 # define GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1 @@ -72,21 +72,21 @@ /* Execution Unit (EU) defines */ -#define BRW_ALIGN_1 0 -#define BRW_ALIGN_16 1 +#define ELK_ALIGN_1 0 +#define ELK_ALIGN_16 1 -#define BRW_ADDRESS_DIRECT 0 -#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 +#define ELK_ADDRESS_DIRECT 0 +#define ELK_ADDRESS_REGISTER_INDIRECT_REGISTER 1 -#define BRW_CHANNEL_X 0 -#define BRW_CHANNEL_Y 1 -#define BRW_CHANNEL_Z 2 -#define BRW_CHANNEL_W 3 +#define ELK_CHANNEL_X 0 +#define ELK_CHANNEL_Y 1 +#define ELK_CHANNEL_Z 2 +#define ELK_CHANNEL_W 3 -enum brw_compression { - BRW_COMPRESSION_NONE = 0, - BRW_COMPRESSION_2NDHALF = 1, - BRW_COMPRESSION_COMPRESSED = 2, +enum elk_compression { + ELK_COMPRESSION_NONE = 0, + ELK_COMPRESSION_2NDHALF = 1, + ELK_COMPRESSION_COMPRESSED = 2, }; #define GFX6_COMPRESSION_1Q 0 @@ -96,62 +96,62 @@ enum brw_compression { #define GFX6_COMPRESSION_1H 0 #define GFX6_COMPRESSION_2H 2 -enum ENUM_PACKED brw_conditional_mod { - BRW_CONDITIONAL_NONE = 0, - BRW_CONDITIONAL_Z = 1, - BRW_CONDITIONAL_NZ = 2, - BRW_CONDITIONAL_EQ = 1, /* Z */ - BRW_CONDITIONAL_NEQ = 2, /* NZ */ - BRW_CONDITIONAL_G = 3, - BRW_CONDITIONAL_GE = 4, - BRW_CONDITIONAL_L = 5, - BRW_CONDITIONAL_LE = 6, - BRW_CONDITIONAL_R = 7, /* Gen <= 5 */ - BRW_CONDITIONAL_O = 8, - BRW_CONDITIONAL_U = 9, +enum ENUM_PACKED elk_conditional_mod { + ELK_CONDITIONAL_NONE = 0, + ELK_CONDITIONAL_Z = 1, + ELK_CONDITIONAL_NZ = 2, + ELK_CONDITIONAL_EQ = 1, /* Z */ + ELK_CONDITIONAL_NEQ = 2, /* NZ */ + ELK_CONDITIONAL_G = 3, + ELK_CONDITIONAL_GE = 4, + ELK_CONDITIONAL_L = 5, + ELK_CONDITIONAL_LE = 6, + ELK_CONDITIONAL_R = 7, /* Gen <= 5 */ + ELK_CONDITIONAL_O = 8, + ELK_CONDITIONAL_U = 9, }; -#define BRW_DEBUG_NONE 0 -#define BRW_DEBUG_BREAKPOINT 1 +#define ELK_DEBUG_NONE 0 +#define ELK_DEBUG_BREAKPOINT 1 -#define BRW_DEPENDENCY_NORMAL 0 -#define BRW_DEPENDENCY_NOTCLEARED 1 -#define BRW_DEPENDENCY_NOTCHECKED 2 -#define BRW_DEPENDENCY_DISABLE 3 +#define ELK_DEPENDENCY_NORMAL 0 +#define ELK_DEPENDENCY_NOTCLEARED 1 +#define ELK_DEPENDENCY_NOTCHECKED 2 +#define ELK_DEPENDENCY_DISABLE 3 -enum ENUM_PACKED brw_execution_size { - BRW_EXECUTE_1 = 0, - BRW_EXECUTE_2 = 1, - BRW_EXECUTE_4 = 2, - BRW_EXECUTE_8 = 3, - BRW_EXECUTE_16 = 4, - BRW_EXECUTE_32 = 5, +enum ENUM_PACKED elk_execution_size { + ELK_EXECUTE_1 = 0, + ELK_EXECUTE_2 = 1, + ELK_EXECUTE_4 = 2, + ELK_EXECUTE_8 = 3, + ELK_EXECUTE_16 = 4, + ELK_EXECUTE_32 = 5, }; -enum ENUM_PACKED brw_horizontal_stride { - BRW_HORIZONTAL_STRIDE_0 = 0, - BRW_HORIZONTAL_STRIDE_1 = 1, - BRW_HORIZONTAL_STRIDE_2 = 2, - BRW_HORIZONTAL_STRIDE_4 = 3, +enum ENUM_PACKED elk_horizontal_stride { + ELK_HORIZONTAL_STRIDE_0 = 0, + ELK_HORIZONTAL_STRIDE_1 = 1, + ELK_HORIZONTAL_STRIDE_2 = 2, + ELK_HORIZONTAL_STRIDE_4 = 3, }; enum ENUM_PACKED gfx10_align1_3src_src_horizontal_stride { - BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0, - BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1, - BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2, - BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3, + ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0, + ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1, + ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2, + ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3, }; enum ENUM_PACKED gfx10_align1_3src_dst_horizontal_stride { - BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0, - BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1, + ELK_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0, + ELK_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1, }; -#define BRW_INSTRUCTION_NORMAL 0 -#define BRW_INSTRUCTION_SATURATE 1 +#define ELK_INSTRUCTION_NORMAL 0 +#define ELK_INSTRUCTION_SATURATE 1 -#define BRW_MASK_ENABLE 0 -#define BRW_MASK_DISABLE 1 +#define ELK_MASK_ENABLE 0 +#define ELK_MASK_DISABLE 1 /** @{ * @@ -165,140 +165,140 @@ enum ENUM_PACKED gfx10_align1_3src_dst_horizontal_stride { * This is the default value. It means that a channel's write enable is set * if the per-channel IP is pointing at this instruction. */ -#define BRW_WE_NORMAL 0 +#define ELK_WE_NORMAL 0 /** - * This is used like BRW_MASK_DISABLE, and causes all channels to have + * This is used like ELK_MASK_DISABLE, and causes all channels to have * their write enable set. Note that predication still contributes to * whether the channel actually gets written. */ -#define BRW_WE_ALL 1 +#define ELK_WE_ALL 1 /** @} */ -enum opcode { +enum elk_opcode { /* These are the actual hardware instructions. */ - BRW_OPCODE_ILLEGAL, - BRW_OPCODE_SYNC, - BRW_OPCODE_MOV, - BRW_OPCODE_SEL, - BRW_OPCODE_MOVI, /**< G45+ */ - BRW_OPCODE_NOT, - BRW_OPCODE_AND, - BRW_OPCODE_OR, - BRW_OPCODE_XOR, - BRW_OPCODE_SHR, - BRW_OPCODE_SHL, - BRW_OPCODE_DIM, /**< Gfx7.5 only */ - BRW_OPCODE_SMOV, /**< Gfx8+ */ - BRW_OPCODE_ASR, - BRW_OPCODE_ROR, /**< Gfx11+ */ - BRW_OPCODE_ROL, /**< Gfx11+ */ - BRW_OPCODE_CMP, - BRW_OPCODE_CMPN, - BRW_OPCODE_CSEL, /**< Gfx8+ */ - BRW_OPCODE_F32TO16, /**< Gfx7 only */ - BRW_OPCODE_F16TO32, /**< Gfx7 only */ - BRW_OPCODE_BFREV, /**< Gfx7+ */ - BRW_OPCODE_BFE, /**< Gfx7+ */ - BRW_OPCODE_BFI1, /**< Gfx7+ */ - BRW_OPCODE_BFI2, /**< Gfx7+ */ - BRW_OPCODE_JMPI, - BRW_OPCODE_BRD, /**< Gfx7+ */ - BRW_OPCODE_IF, - BRW_OPCODE_IFF, /**< Pre-Gfx6 */ - BRW_OPCODE_BRC, /**< Gfx7+ */ - BRW_OPCODE_ELSE, - BRW_OPCODE_ENDIF, - BRW_OPCODE_DO, /**< Pre-Gfx6 */ - BRW_OPCODE_CASE, /**< Gfx6 only */ - BRW_OPCODE_WHILE, - BRW_OPCODE_BREAK, - BRW_OPCODE_CONTINUE, - BRW_OPCODE_HALT, - BRW_OPCODE_CALLA, /**< Gfx7.5+ */ - BRW_OPCODE_MSAVE, /**< Pre-Gfx6 */ - BRW_OPCODE_CALL, /**< Gfx6+ */ - BRW_OPCODE_MREST, /**< Pre-Gfx6 */ - BRW_OPCODE_RET, /**< Gfx6+ */ - BRW_OPCODE_PUSH, /**< Pre-Gfx6 */ - BRW_OPCODE_FORK, /**< Gfx6 only */ - BRW_OPCODE_GOTO, /**< Gfx8+ */ - BRW_OPCODE_POP, /**< Pre-Gfx6 */ - BRW_OPCODE_WAIT, - BRW_OPCODE_SEND, - BRW_OPCODE_SENDC, - BRW_OPCODE_SENDS, /**< Gfx9+ */ - BRW_OPCODE_SENDSC, /**< Gfx9+ */ - BRW_OPCODE_MATH, /**< Gfx6+ */ - BRW_OPCODE_ADD, - BRW_OPCODE_MUL, - BRW_OPCODE_AVG, - BRW_OPCODE_FRC, - BRW_OPCODE_RNDU, - BRW_OPCODE_RNDD, - BRW_OPCODE_RNDE, - BRW_OPCODE_RNDZ, - BRW_OPCODE_MAC, - BRW_OPCODE_MACH, - BRW_OPCODE_LZD, - BRW_OPCODE_FBH, /**< Gfx7+ */ - BRW_OPCODE_FBL, /**< Gfx7+ */ - BRW_OPCODE_CBIT, /**< Gfx7+ */ - BRW_OPCODE_ADDC, /**< Gfx7+ */ - BRW_OPCODE_SUBB, /**< Gfx7+ */ - BRW_OPCODE_SAD2, - BRW_OPCODE_SADA2, - BRW_OPCODE_ADD3, /* Gen12+ only */ - BRW_OPCODE_DP4, - BRW_OPCODE_DPH, - BRW_OPCODE_DP3, - BRW_OPCODE_DP2, - BRW_OPCODE_DP4A, /**< Gfx12+ */ - BRW_OPCODE_LINE, - BRW_OPCODE_DPAS, /**< Gfx12.5+ */ - BRW_OPCODE_PLN, /**< G45+ */ - BRW_OPCODE_MAD, /**< Gfx6+ */ - BRW_OPCODE_LRP, /**< Gfx6+ */ - BRW_OPCODE_MADM, /**< Gfx8+ */ - BRW_OPCODE_NENOP, /**< G45 only */ - BRW_OPCODE_NOP, + ELK_OPCODE_ILLEGAL, + ELK_OPCODE_SYNC, + ELK_OPCODE_MOV, + ELK_OPCODE_SEL, + ELK_OPCODE_MOVI, /**< G45+ */ + ELK_OPCODE_NOT, + ELK_OPCODE_AND, + ELK_OPCODE_OR, + ELK_OPCODE_XOR, + ELK_OPCODE_SHR, + ELK_OPCODE_SHL, + ELK_OPCODE_DIM, /**< Gfx7.5 only */ + ELK_OPCODE_SMOV, /**< Gfx8+ */ + ELK_OPCODE_ASR, + ELK_OPCODE_ROR, /**< Gfx11+ */ + ELK_OPCODE_ROL, /**< Gfx11+ */ + ELK_OPCODE_CMP, + ELK_OPCODE_CMPN, + ELK_OPCODE_CSEL, /**< Gfx8+ */ + ELK_OPCODE_F32TO16, /**< Gfx7 only */ + ELK_OPCODE_F16TO32, /**< Gfx7 only */ + ELK_OPCODE_BFREV, /**< Gfx7+ */ + ELK_OPCODE_BFE, /**< Gfx7+ */ + ELK_OPCODE_BFI1, /**< Gfx7+ */ + ELK_OPCODE_BFI2, /**< Gfx7+ */ + ELK_OPCODE_JMPI, + ELK_OPCODE_BRD, /**< Gfx7+ */ + ELK_OPCODE_IF, + ELK_OPCODE_IFF, /**< Pre-Gfx6 */ + ELK_OPCODE_BRC, /**< Gfx7+ */ + ELK_OPCODE_ELSE, + ELK_OPCODE_ENDIF, + ELK_OPCODE_DO, /**< Pre-Gfx6 */ + ELK_OPCODE_CASE, /**< Gfx6 only */ + ELK_OPCODE_WHILE, + ELK_OPCODE_BREAK, + ELK_OPCODE_CONTINUE, + ELK_OPCODE_HALT, + ELK_OPCODE_CALLA, /**< Gfx7.5+ */ + ELK_OPCODE_MSAVE, /**< Pre-Gfx6 */ + ELK_OPCODE_CALL, /**< Gfx6+ */ + ELK_OPCODE_MREST, /**< Pre-Gfx6 */ + ELK_OPCODE_RET, /**< Gfx6+ */ + ELK_OPCODE_PUSH, /**< Pre-Gfx6 */ + ELK_OPCODE_FORK, /**< Gfx6 only */ + ELK_OPCODE_GOTO, /**< Gfx8+ */ + ELK_OPCODE_POP, /**< Pre-Gfx6 */ + ELK_OPCODE_WAIT, + ELK_OPCODE_SEND, + ELK_OPCODE_SENDC, + ELK_OPCODE_SENDS, /**< Gfx9+ */ + ELK_OPCODE_SENDSC, /**< Gfx9+ */ + ELK_OPCODE_MATH, /**< Gfx6+ */ + ELK_OPCODE_ADD, + ELK_OPCODE_MUL, + ELK_OPCODE_AVG, + ELK_OPCODE_FRC, + ELK_OPCODE_RNDU, + ELK_OPCODE_RNDD, + ELK_OPCODE_RNDE, + ELK_OPCODE_RNDZ, + ELK_OPCODE_MAC, + ELK_OPCODE_MACH, + ELK_OPCODE_LZD, + ELK_OPCODE_FBH, /**< Gfx7+ */ + ELK_OPCODE_FBL, /**< Gfx7+ */ + ELK_OPCODE_CBIT, /**< Gfx7+ */ + ELK_OPCODE_ADDC, /**< Gfx7+ */ + ELK_OPCODE_SUBB, /**< Gfx7+ */ + ELK_OPCODE_SAD2, + ELK_OPCODE_SADA2, + ELK_OPCODE_ADD3, /* Gen12+ only */ + ELK_OPCODE_DP4, + ELK_OPCODE_DPH, + ELK_OPCODE_DP3, + ELK_OPCODE_DP2, + ELK_OPCODE_DP4A, /**< Gfx12+ */ + ELK_OPCODE_LINE, + ELK_OPCODE_DPAS, /**< Gfx12.5+ */ + ELK_OPCODE_PLN, /**< G45+ */ + ELK_OPCODE_MAD, /**< Gfx6+ */ + ELK_OPCODE_LRP, /**< Gfx6+ */ + ELK_OPCODE_MADM, /**< Gfx8+ */ + ELK_OPCODE_NENOP, /**< G45 only */ + ELK_OPCODE_NOP, - NUM_BRW_OPCODES, + NUM_ELK_OPCODES, /* These are compiler backend opcodes that get translated into other * instructions. */ - FS_OPCODE_FB_WRITE = NUM_BRW_OPCODES, + ELK_FS_OPCODE_FB_WRITE = NUM_ELK_OPCODES, /** - * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as + * Same as ELK_FS_OPCODE_FB_WRITE but expects its arguments separately as * individual sources instead of as a single payload blob. The * position/ordering of the arguments are defined by the enum * fb_write_logical_srcs. */ - FS_OPCODE_FB_WRITE_LOGICAL, + ELK_FS_OPCODE_FB_WRITE_LOGICAL, - FS_OPCODE_REP_FB_WRITE, + ELK_FS_OPCODE_REP_FB_WRITE, - FS_OPCODE_FB_READ, - FS_OPCODE_FB_READ_LOGICAL, + ELK_FS_OPCODE_FB_READ, + ELK_FS_OPCODE_FB_READ_LOGICAL, - SHADER_OPCODE_RCP, - SHADER_OPCODE_RSQ, - SHADER_OPCODE_SQRT, - SHADER_OPCODE_EXP2, - SHADER_OPCODE_LOG2, - SHADER_OPCODE_POW, - SHADER_OPCODE_INT_QUOTIENT, - SHADER_OPCODE_INT_REMAINDER, - SHADER_OPCODE_SIN, - SHADER_OPCODE_COS, + ELK_SHADER_OPCODE_RCP, + ELK_SHADER_OPCODE_RSQ, + ELK_SHADER_OPCODE_SQRT, + ELK_SHADER_OPCODE_EXP2, + ELK_SHADER_OPCODE_LOG2, + ELK_SHADER_OPCODE_POW, + ELK_SHADER_OPCODE_INT_QUOTIENT, + ELK_SHADER_OPCODE_INT_REMAINDER, + ELK_SHADER_OPCODE_SIN, + ELK_SHADER_OPCODE_COS, /** * A generic "send" opcode. The first two sources are the message * descriptor and extended message descriptor respectively. The third * and optional fourth sources are the message payload */ - SHADER_OPCODE_SEND, + ELK_SHADER_OPCODE_SEND, /** * An "undefined" write which does nothing but indicates to liveness that @@ -306,7 +306,7 @@ enum opcode { * instruction. Used to prevent partial writes from causing issues with * live ranges. */ - SHADER_OPCODE_UNDEF, + ELK_SHADER_OPCODE_UNDEF, /** * Texture sampling opcodes. @@ -316,39 +316,39 @@ enum opcode { * arguments separately as individual sources. The position/ordering of the * arguments are defined by the enum tex_logical_srcs. */ - SHADER_OPCODE_TEX, - SHADER_OPCODE_TEX_LOGICAL, - SHADER_OPCODE_TXD, - SHADER_OPCODE_TXD_LOGICAL, - SHADER_OPCODE_TXF, - SHADER_OPCODE_TXF_LOGICAL, - SHADER_OPCODE_TXF_LZ, - SHADER_OPCODE_TXL, - SHADER_OPCODE_TXL_LOGICAL, - SHADER_OPCODE_TXL_LZ, - SHADER_OPCODE_TXS, - SHADER_OPCODE_TXS_LOGICAL, - FS_OPCODE_TXB, - FS_OPCODE_TXB_LOGICAL, - SHADER_OPCODE_TXF_CMS, - SHADER_OPCODE_TXF_CMS_LOGICAL, - SHADER_OPCODE_TXF_CMS_W, - SHADER_OPCODE_TXF_CMS_W_LOGICAL, - SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL, - SHADER_OPCODE_TXF_UMS, - SHADER_OPCODE_TXF_UMS_LOGICAL, - SHADER_OPCODE_TXF_MCS, - SHADER_OPCODE_TXF_MCS_LOGICAL, - SHADER_OPCODE_LOD, - SHADER_OPCODE_LOD_LOGICAL, - SHADER_OPCODE_TG4, - SHADER_OPCODE_TG4_LOGICAL, - SHADER_OPCODE_TG4_OFFSET, - SHADER_OPCODE_TG4_OFFSET_LOGICAL, - SHADER_OPCODE_SAMPLEINFO, - SHADER_OPCODE_SAMPLEINFO_LOGICAL, + ELK_SHADER_OPCODE_TEX, + ELK_SHADER_OPCODE_TEX_LOGICAL, + ELK_SHADER_OPCODE_TXD, + ELK_SHADER_OPCODE_TXD_LOGICAL, + ELK_SHADER_OPCODE_TXF, + ELK_SHADER_OPCODE_TXF_LOGICAL, + ELK_SHADER_OPCODE_TXF_LZ, + ELK_SHADER_OPCODE_TXL, + ELK_SHADER_OPCODE_TXL_LOGICAL, + ELK_SHADER_OPCODE_TXL_LZ, + ELK_SHADER_OPCODE_TXS, + ELK_SHADER_OPCODE_TXS_LOGICAL, + ELK_FS_OPCODE_TXB, + ELK_FS_OPCODE_TXB_LOGICAL, + ELK_SHADER_OPCODE_TXF_CMS, + ELK_SHADER_OPCODE_TXF_CMS_LOGICAL, + ELK_SHADER_OPCODE_TXF_CMS_W, + ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL, + ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL, + ELK_SHADER_OPCODE_TXF_UMS, + ELK_SHADER_OPCODE_TXF_UMS_LOGICAL, + ELK_SHADER_OPCODE_TXF_MCS, + ELK_SHADER_OPCODE_TXF_MCS_LOGICAL, + ELK_SHADER_OPCODE_LOD, + ELK_SHADER_OPCODE_LOD_LOGICAL, + ELK_SHADER_OPCODE_TG4, + ELK_SHADER_OPCODE_TG4_LOGICAL, + ELK_SHADER_OPCODE_TG4_OFFSET, + ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL, + ELK_SHADER_OPCODE_SAMPLEINFO, + ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL, - SHADER_OPCODE_IMAGE_SIZE_LOGICAL, + ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL, /** * Combines multiple sources of size 1 into a larger virtual GRF. @@ -362,7 +362,7 @@ enum opcode { * but still reserves the first channel of the destination VGRF. This can be * used to reserve space for, say, a message header set up by the generators. */ - SHADER_OPCODE_LOAD_PAYLOAD, + ELK_SHADER_OPCODE_LOAD_PAYLOAD, /** * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this @@ -371,7 +371,7 @@ enum opcode { * occupying the lowest bits and the last source occupying the highest * bits. */ - FS_OPCODE_PACK, + ELK_FS_OPCODE_PACK, /** * Typed and untyped surface access opcodes. @@ -387,15 +387,15 @@ enum opcode { * Source 4: [required] Opcode-specific control immediate, same as source 2 * of the matching non-LOGICAL opcode. */ - VEC4_OPCODE_UNTYPED_ATOMIC, - SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, - VEC4_OPCODE_UNTYPED_SURFACE_READ, - SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, - VEC4_OPCODE_UNTYPED_SURFACE_WRITE, - SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, + ELK_VEC4_OPCODE_UNTYPED_ATOMIC, + ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, + ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ, + ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, + ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE, + ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, - SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, - SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL, + ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, + ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL, /** * Untyped A64 surface access opcodes. @@ -405,21 +405,21 @@ enum opcode { * Source 2: [required] Opcode-specific control immediate, same as source 2 * of the matching non-LOGICAL opcode. */ - SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL, - SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL, - SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL, - SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL, - SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL, - SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, - SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL, - SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, + ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL, + ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL, + ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL, + ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL, + ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL, + ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, + ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL, + ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, - SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, - SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, - SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, + ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, + ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, + ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, - SHADER_OPCODE_RND_MODE, - SHADER_OPCODE_FLOAT_CONTROL_MODE, + ELK_SHADER_OPCODE_RND_MODE, + ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE, /** * Byte scattered write/read opcodes. @@ -428,10 +428,10 @@ enum opcode { * opcode, but instead of taking a single payload blog they expect their * arguments separately as individual sources, like untyped write/read. */ - SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, - SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, - SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, - SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, + ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, + ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, + ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, + ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, /** * Memory fence messages. @@ -444,7 +444,7 @@ enum opcode { * * Vec4 backend only uses Source 0. */ - SHADER_OPCODE_MEMORY_FENCE, + ELK_SHADER_OPCODE_MEMORY_FENCE, /** * Scheduling-only fence. @@ -452,38 +452,38 @@ enum opcode { * Sources can be used to force a stall until the registers in those are * available. This might generate MOVs or SYNC_NOPs (Gfx12+). */ - FS_OPCODE_SCHEDULING_FENCE, + ELK_FS_OPCODE_SCHEDULING_FENCE, - SHADER_OPCODE_GFX4_SCRATCH_READ, - SHADER_OPCODE_GFX4_SCRATCH_WRITE, - SHADER_OPCODE_GFX7_SCRATCH_READ, + ELK_SHADER_OPCODE_GFX4_SCRATCH_READ, + ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE, + ELK_SHADER_OPCODE_GFX7_SCRATCH_READ, - SHADER_OPCODE_SCRATCH_HEADER, + ELK_SHADER_OPCODE_SCRATCH_HEADER, /** * Gfx8+ SIMD8 URB messages. */ - SHADER_OPCODE_URB_READ_LOGICAL, - SHADER_OPCODE_URB_WRITE_LOGICAL, + ELK_SHADER_OPCODE_URB_READ_LOGICAL, + ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, /** * Return the index of the first enabled live channel and assign it to * to the first component of the destination. Frequently used as input * for the BROADCAST pseudo-opcode. */ - SHADER_OPCODE_FIND_LIVE_CHANNEL, + ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, /** * Return the index of the last enabled live channel and assign it to * the first component of the destination. */ - SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL, + ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL, /** * Return the current execution mask in the specified flag subregister. * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register. */ - FS_OPCODE_LOAD_LIVE_CHANNELS, + ELK_FS_OPCODE_LOAD_LIVE_CHANNELS, /** * Pick the channel from its first source register given by the index @@ -495,7 +495,7 @@ enum opcode { * is guaranteed to be updated, which implies that BROADCAST instructions * should usually be marked force_writemask_all. */ - SHADER_OPCODE_BROADCAST, + ELK_SHADER_OPCODE_BROADCAST, /* Pick the channel from its first source register given by the index * specified as second source. @@ -504,84 +504,84 @@ enum opcode { * dynamic index and potentially puts a different value in each output * channel. */ - SHADER_OPCODE_SHUFFLE, + ELK_SHADER_OPCODE_SHUFFLE, /* Select between src0 and src1 based on channel enables. * * This instruction copies src0 into the enabled channels of the * destination and copies src1 into the disabled channels. */ - SHADER_OPCODE_SEL_EXEC, + ELK_SHADER_OPCODE_SEL_EXEC, /* This turns into an align16 mov from src0 to dst with a swizzle * provided as an immediate in src1. */ - SHADER_OPCODE_QUAD_SWIZZLE, + ELK_SHADER_OPCODE_QUAD_SWIZZLE, /* Take every Nth element in src0 and broadcast it to the group of N * channels in which it lives in the destination. The offset within the * cluster is given by src1 and the cluster size is given by src2. */ - SHADER_OPCODE_CLUSTER_BROADCAST, + ELK_SHADER_OPCODE_CLUSTER_BROADCAST, - SHADER_OPCODE_GET_BUFFER_SIZE, + ELK_SHADER_OPCODE_GET_BUFFER_SIZE, - SHADER_OPCODE_INTERLOCK, + ELK_SHADER_OPCODE_INTERLOCK, /** Target for a HALT * * All HALT instructions in a shader must target the same jump point and * that point is denoted by a HALT_TARGET instruction. */ - SHADER_OPCODE_HALT_TARGET, + ELK_SHADER_OPCODE_HALT_TARGET, - VEC4_OPCODE_MOV_BYTES, - VEC4_OPCODE_PACK_BYTES, - VEC4_OPCODE_UNPACK_UNIFORM, - VEC4_OPCODE_DOUBLE_TO_F32, - VEC4_OPCODE_DOUBLE_TO_D32, - VEC4_OPCODE_DOUBLE_TO_U32, - VEC4_OPCODE_TO_DOUBLE, - VEC4_OPCODE_PICK_LOW_32BIT, - VEC4_OPCODE_PICK_HIGH_32BIT, - VEC4_OPCODE_SET_LOW_32BIT, - VEC4_OPCODE_SET_HIGH_32BIT, - VEC4_OPCODE_MOV_FOR_SCRATCH, - VEC4_OPCODE_ZERO_OOB_PUSH_REGS, + ELK_VEC4_OPCODE_MOV_BYTES, + ELK_VEC4_OPCODE_PACK_BYTES, + ELK_VEC4_OPCODE_UNPACK_UNIFORM, + ELK_VEC4_OPCODE_DOUBLE_TO_F32, + ELK_VEC4_OPCODE_DOUBLE_TO_D32, + ELK_VEC4_OPCODE_DOUBLE_TO_U32, + ELK_VEC4_OPCODE_TO_DOUBLE, + ELK_VEC4_OPCODE_PICK_LOW_32BIT, + ELK_VEC4_OPCODE_PICK_HIGH_32BIT, + ELK_VEC4_OPCODE_SET_LOW_32BIT, + ELK_VEC4_OPCODE_SET_HIGH_32BIT, + ELK_VEC4_OPCODE_MOV_FOR_SCRATCH, + ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS, - FS_OPCODE_DDX_COARSE, - FS_OPCODE_DDX_FINE, + ELK_FS_OPCODE_DDX_COARSE, + ELK_FS_OPCODE_DDX_FINE, /** * Compute dFdy(), dFdyCoarse(), or dFdyFine(). */ - FS_OPCODE_DDY_COARSE, - FS_OPCODE_DDY_FINE, - FS_OPCODE_LINTERP, - FS_OPCODE_PIXEL_X, - FS_OPCODE_PIXEL_Y, - FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, - FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4, - FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, - FS_OPCODE_SET_SAMPLE_ID, - FS_OPCODE_PACK_HALF_2x16_SPLIT, - FS_OPCODE_INTERPOLATE_AT_SAMPLE, - FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, - FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, + ELK_FS_OPCODE_DDY_COARSE, + ELK_FS_OPCODE_DDY_FINE, + ELK_FS_OPCODE_LINTERP, + ELK_FS_OPCODE_PIXEL_X, + ELK_FS_OPCODE_PIXEL_Y, + ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, + ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4, + ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, + ELK_FS_OPCODE_SET_SAMPLE_ID, + ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT, + ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE, + ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, + ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, - VEC4_VS_OPCODE_URB_WRITE, - VS_OPCODE_PULL_CONSTANT_LOAD, - VS_OPCODE_PULL_CONSTANT_LOAD_GFX7, + ELK_VEC4_VS_OPCODE_URB_WRITE, + ELK_VS_OPCODE_PULL_CONSTANT_LOAD, + ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7, - VS_OPCODE_UNPACK_FLAGS_SIMD4X2, + ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2, /** * Write geometry shader output data to the URB. * - * Unlike VEC4_VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from + * Unlike ELK_VEC4_VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from * R0 to the first MRF. This allows the geometry shader to override the * "Slot {0,1} Offset" fields in the message header. */ - VEC4_GS_OPCODE_URB_WRITE, + ELK_VEC4_GS_OPCODE_URB_WRITE, /** * Write geometry shader output data to the URB and request a new URB @@ -589,7 +589,7 @@ enum opcode { * * This opcode doesn't do an implied move from R0 to the first MRF. */ - VEC4_GS_OPCODE_URB_WRITE_ALLOCATE, + ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE, /** * Terminate the geometry shader thread by doing an empty URB write. @@ -598,7 +598,7 @@ enum opcode { * allows the geometry shader to override the "GS Number of Output Vertices * for Slot {0,1}" fields in the message header. */ - GS_OPCODE_THREAD_END, + ELK_GS_OPCODE_THREAD_END, /** * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header. @@ -614,7 +614,7 @@ enum opcode { * Note: the hardware will apply this offset *in addition to* the offset in * vec4_instruction::offset. */ - GS_OPCODE_SET_WRITE_OFFSET, + ELK_GS_OPCODE_SET_WRITE_OFFSET, /** * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a @@ -624,27 +624,27 @@ enum opcode { * * - src0.x is the vertex count. The upper 16 bits will be ignored. */ - GS_OPCODE_SET_VERTEX_COUNT, + ELK_GS_OPCODE_SET_VERTEX_COUNT, /** * Set DWORD 2 of dst to the value in src. */ - GS_OPCODE_SET_DWORD_2, + ELK_GS_OPCODE_SET_DWORD_2, /** * Prepare the dst register for storage in the "Channel Mask" fields of a * URB_WRITE message header. * * DWORD 4 of dst is shifted left by 4 bits, so that later, - * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the + * ELK_GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the * final channel mask. * - * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to + * Note: since ELK_GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to * form the final channel mask, DWORDs 0 and 4 of the dst register must not * have any extraneous bits set prior to execution of this opcode (that is, * they should be in the range 0x0 to 0xf). */ - GS_OPCODE_PREPARE_CHANNEL_MASKS, + ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS, /** * Set the "Channel Mask" fields of a URB_WRITE message header. @@ -652,17 +652,17 @@ enum opcode { * - dst is the MRF containing the message header. * * - src.x is the channel mask, as prepared by - * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to + * ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to * form the final channel mask. */ - GS_OPCODE_SET_CHANNEL_MASKS, + ELK_GS_OPCODE_SET_CHANNEL_MASKS, /** * Get the "Instance ID" fields from the payload. * * - dst is the GRF for gl_InvocationID. */ - GS_OPCODE_GET_INSTANCE_ID, + ELK_GS_OPCODE_GET_INSTANCE_ID, /** * Send a FF_SYNC message to allocate initial URB handles (gfx6). @@ -681,7 +681,7 @@ enum opcode { * to include the allocated URB handle so it can then be reused directly as * the header in the URB write operation we are allocating the handle for. */ - GS_OPCODE_FF_SYNC, + ELK_GS_OPCODE_FF_SYNC, /** * Move r0.1 (which holds PrimitiveID information in gfx6) to a separate @@ -689,7 +689,7 @@ enum opcode { * * - dst is the GRF where PrimitiveID information will be moved. */ - GS_OPCODE_SET_PRIMITIVE_ID, + ELK_GS_OPCODE_SET_PRIMITIVE_ID, /** * Write transform feedback data to the SVB by sending a SVB WRITE message. @@ -701,7 +701,7 @@ enum opcode { * * - src1 is the destination register when write commit occurs. */ - GS_OPCODE_SVB_WRITE, + ELK_GS_OPCODE_SVB_WRITE, /** * Set destination index in the SVB write message payload (M0.5). Used @@ -710,7 +710,7 @@ enum opcode { * - dst is the header to save the destination indices for SVB WRITE. * - src is the register that holds the destination indices value. */ - GS_OPCODE_SVB_SET_DST_INDEX, + ELK_GS_OPCODE_SVB_SET_DST_INDEX, /** * Prepare Mx.0 subregister for being used in the FF_SYNC message header. @@ -725,28 +725,28 @@ enum opcode { * - src2 is the value to hold in M0: number of SO vertices to write * and number of SO primitives needed. */ - GS_OPCODE_FF_SYNC_SET_PRIMITIVES, + ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES, /** * Terminate the compute shader. */ - CS_OPCODE_CS_TERMINATE, + ELK_CS_OPCODE_CS_TERMINATE, /** * GLSL barrier() */ - SHADER_OPCODE_BARRIER, + ELK_SHADER_OPCODE_BARRIER, /** * Calculate the high 32-bits of a 32x32 multiply. */ - SHADER_OPCODE_MULH, + ELK_SHADER_OPCODE_MULH, /** Signed subtraction with saturation. */ - SHADER_OPCODE_ISUB_SAT, + ELK_SHADER_OPCODE_ISUB_SAT, /** Unsigned subtraction with saturation. */ - SHADER_OPCODE_USUB_SAT, + ELK_SHADER_OPCODE_USUB_SAT, /** * A MOV that uses VxH indirect addressing. @@ -756,70 +756,70 @@ enum opcode { * Source 2: The length of the region that could be accessed (in bytes, * UD immediate). */ - SHADER_OPCODE_MOV_INDIRECT, + ELK_SHADER_OPCODE_MOV_INDIRECT, /** Fills out a relocatable immediate */ - SHADER_OPCODE_MOV_RELOC_IMM, + ELK_SHADER_OPCODE_MOV_RELOC_IMM, - VEC4_OPCODE_URB_READ, - TCS_OPCODE_GET_INSTANCE_ID, - VEC4_TCS_OPCODE_URB_WRITE, - VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, - VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, - TCS_OPCODE_GET_PRIMITIVE_ID, - TCS_OPCODE_CREATE_BARRIER_HEADER, - TCS_OPCODE_SRC0_010_IS_ZERO, - TCS_OPCODE_RELEASE_INPUT, - TCS_OPCODE_THREAD_END, + ELK_VEC4_OPCODE_URB_READ, + ELK_TCS_OPCODE_GET_INSTANCE_ID, + ELK_VEC4_TCS_OPCODE_URB_WRITE, + ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, + ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, + ELK_TCS_OPCODE_GET_PRIMITIVE_ID, + ELK_TCS_OPCODE_CREATE_BARRIER_HEADER, + ELK_TCS_OPCODE_SRC0_010_IS_ZERO, + ELK_TCS_OPCODE_RELEASE_INPUT, + ELK_TCS_OPCODE_THREAD_END, - TES_OPCODE_GET_PRIMITIVE_ID, - TES_OPCODE_CREATE_INPUT_READ_HEADER, - TES_OPCODE_ADD_INDIRECT_URB_OFFSET, + ELK_TES_OPCODE_GET_PRIMITIVE_ID, + ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER, + ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET, - SHADER_OPCODE_BTD_SPAWN_LOGICAL, - SHADER_OPCODE_BTD_RETIRE_LOGICAL, + ELK_SHADER_OPCODE_BTD_SPAWN_LOGICAL, + ELK_SHADER_OPCODE_BTD_RETIRE_LOGICAL, - SHADER_OPCODE_READ_SR_REG, + ELK_SHADER_OPCODE_READ_SR_REG, - RT_OPCODE_TRACE_RAY_LOGICAL, + ELK_RT_OPCODE_TRACE_RAY_LOGICAL, }; -enum brw_urb_write_flags { - BRW_URB_WRITE_NO_FLAGS = 0, +enum elk_urb_write_flags { + ELK_URB_WRITE_NO_FLAGS = 0, /** * Causes a new URB entry to be allocated, and its address stored in the * destination register (gen < 7). */ - BRW_URB_WRITE_ALLOCATE = 0x1, + ELK_URB_WRITE_ALLOCATE = 0x1, /** * Causes the current URB entry to be deallocated (gen < 7). */ - BRW_URB_WRITE_UNUSED = 0x2, + ELK_URB_WRITE_UNUSED = 0x2, /** * Causes the thread to terminate. */ - BRW_URB_WRITE_EOT = 0x4, + ELK_URB_WRITE_EOT = 0x4, /** * Indicates that the given URB entry is complete, and may be sent further * down the 3D pipeline (gen < 7). */ - BRW_URB_WRITE_COMPLETE = 0x8, + ELK_URB_WRITE_COMPLETE = 0x8, /** * Indicates that an additional offset (which may be different for the two * vec4 slots) is stored in the message header (gen == 7). */ - BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10, + ELK_URB_WRITE_PER_SLOT_OFFSET = 0x10, /** * Indicates that the channel masks in the URB_WRITE message header should * not be overridden to 0xff (gen == 7). */ - BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20, + ELK_URB_WRITE_USE_CHANNEL_MASKS = 0x20, /** * Indicates that the data should be sent to the URB using the @@ -827,20 +827,20 @@ enum brw_urb_write_flags { * causes offsets to be interpreted as multiples of an OWORD instead of an * HWORD, and only allows one OWORD to be written. */ - BRW_URB_WRITE_OWORD = 0x40, + ELK_URB_WRITE_OWORD = 0x40, /** * Convenient combination of flags: end the thread while simultaneously * marking the given URB entry as complete. */ - BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE, + ELK_URB_WRITE_EOT_COMPLETE = ELK_URB_WRITE_EOT | ELK_URB_WRITE_COMPLETE, /** * Convenient combination of flags: mark the given URB entry as complete * and simultaneously allocate a new one. */ - BRW_URB_WRITE_ALLOCATE_COMPLETE = - BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE, + ELK_URB_WRITE_ALLOCATE_COMPLETE = + ELK_URB_WRITE_ALLOCATE | ELK_URB_WRITE_COMPLETE, }; enum fb_write_logical_srcs { @@ -1001,51 +1001,51 @@ enum interpolator_logical_srcs { #ifdef __cplusplus /** - * Allow brw_urb_write_flags enums to be ORed together. + * Allow elk_urb_write_flags enums to be ORed together. */ -inline brw_urb_write_flags -operator|(brw_urb_write_flags x, brw_urb_write_flags y) +inline elk_urb_write_flags +operator|(elk_urb_write_flags x, elk_urb_write_flags y) { - return static_cast(static_cast(x) | + return static_cast(static_cast(x) | static_cast(y)); } #endif -enum ENUM_PACKED brw_predicate { - BRW_PREDICATE_NONE = 0, - BRW_PREDICATE_NORMAL = 1, - BRW_PREDICATE_ALIGN1_ANYV = 2, - BRW_PREDICATE_ALIGN1_ALLV = 3, - BRW_PREDICATE_ALIGN1_ANY2H = 4, - BRW_PREDICATE_ALIGN1_ALL2H = 5, - BRW_PREDICATE_ALIGN1_ANY4H = 6, - BRW_PREDICATE_ALIGN1_ALL4H = 7, - BRW_PREDICATE_ALIGN1_ANY8H = 8, - BRW_PREDICATE_ALIGN1_ALL8H = 9, - BRW_PREDICATE_ALIGN1_ANY16H = 10, - BRW_PREDICATE_ALIGN1_ALL16H = 11, - BRW_PREDICATE_ALIGN1_ANY32H = 12, - BRW_PREDICATE_ALIGN1_ALL32H = 13, - BRW_PREDICATE_ALIGN16_REPLICATE_X = 2, - BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3, - BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4, - BRW_PREDICATE_ALIGN16_REPLICATE_W = 5, - BRW_PREDICATE_ALIGN16_ANY4H = 6, - BRW_PREDICATE_ALIGN16_ALL4H = 7, +enum ENUM_PACKED elk_predicate { + ELK_PREDICATE_NONE = 0, + ELK_PREDICATE_NORMAL = 1, + ELK_PREDICATE_ALIGN1_ANYV = 2, + ELK_PREDICATE_ALIGN1_ALLV = 3, + ELK_PREDICATE_ALIGN1_ANY2H = 4, + ELK_PREDICATE_ALIGN1_ALL2H = 5, + ELK_PREDICATE_ALIGN1_ANY4H = 6, + ELK_PREDICATE_ALIGN1_ALL4H = 7, + ELK_PREDICATE_ALIGN1_ANY8H = 8, + ELK_PREDICATE_ALIGN1_ALL8H = 9, + ELK_PREDICATE_ALIGN1_ANY16H = 10, + ELK_PREDICATE_ALIGN1_ALL16H = 11, + ELK_PREDICATE_ALIGN1_ANY32H = 12, + ELK_PREDICATE_ALIGN1_ALL32H = 13, + ELK_PREDICATE_ALIGN16_REPLICATE_X = 2, + ELK_PREDICATE_ALIGN16_REPLICATE_Y = 3, + ELK_PREDICATE_ALIGN16_REPLICATE_Z = 4, + ELK_PREDICATE_ALIGN16_REPLICATE_W = 5, + ELK_PREDICATE_ALIGN16_ANY4H = 6, + ELK_PREDICATE_ALIGN16_ALL4H = 7, XE2_PREDICATE_ANY = 2, XE2_PREDICATE_ALL = 3 }; -enum ENUM_PACKED brw_reg_file { - BRW_ARCHITECTURE_REGISTER_FILE = 0, - BRW_GENERAL_REGISTER_FILE = 1, - BRW_MESSAGE_REGISTER_FILE = 2, - BRW_IMMEDIATE_VALUE = 3, +enum ENUM_PACKED elk_reg_file { + ELK_ARCHITECTURE_REGISTER_FILE = 0, + ELK_GENERAL_REGISTER_FILE = 1, + ELK_MESSAGE_REGISTER_FILE = 2, + ELK_IMMEDIATE_VALUE = 3, - ARF = BRW_ARCHITECTURE_REGISTER_FILE, - FIXED_GRF = BRW_GENERAL_REGISTER_FILE, - MRF = BRW_MESSAGE_REGISTER_FILE, - IMM = BRW_IMMEDIATE_VALUE, + ARF = ELK_ARCHITECTURE_REGISTER_FILE, + FIXED_GRF = ELK_GENERAL_REGISTER_FILE, + MRF = ELK_MESSAGE_REGISTER_FILE, + IMM = ELK_IMMEDIATE_VALUE, /* These are not hardware values */ VGRF, @@ -1055,9 +1055,9 @@ enum ENUM_PACKED brw_reg_file { }; enum ENUM_PACKED gfx10_align1_3src_reg_file { - BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0, - BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */ - BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */ + ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0, + ELK_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */ + ELK_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */ }; /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction @@ -1066,62 +1066,62 @@ enum ENUM_PACKED gfx10_align1_3src_reg_file { * more fine control their respective types. */ enum ENUM_PACKED gfx10_align1_3src_exec_type { - BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0, - BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1, + ELK_ALIGN1_3SRC_EXEC_TYPE_INT = 0, + ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1, }; -#define BRW_ARF_NULL 0x00 -#define BRW_ARF_ADDRESS 0x10 -#define BRW_ARF_ACCUMULATOR 0x20 -#define BRW_ARF_FLAG 0x30 -#define BRW_ARF_MASK 0x40 -#define BRW_ARF_MASK_STACK 0x50 -#define BRW_ARF_MASK_STACK_DEPTH 0x60 -#define BRW_ARF_STATE 0x70 -#define BRW_ARF_CONTROL 0x80 -#define BRW_ARF_NOTIFICATION_COUNT 0x90 -#define BRW_ARF_IP 0xA0 -#define BRW_ARF_TDR 0xB0 -#define BRW_ARF_TIMESTAMP 0xC0 +#define ELK_ARF_NULL 0x00 +#define ELK_ARF_ADDRESS 0x10 +#define ELK_ARF_ACCUMULATOR 0x20 +#define ELK_ARF_FLAG 0x30 +#define ELK_ARF_MASK 0x40 +#define ELK_ARF_MASK_STACK 0x50 +#define ELK_ARF_MASK_STACK_DEPTH 0x60 +#define ELK_ARF_STATE 0x70 +#define ELK_ARF_CONTROL 0x80 +#define ELK_ARF_NOTIFICATION_COUNT 0x90 +#define ELK_ARF_IP 0xA0 +#define ELK_ARF_TDR 0xB0 +#define ELK_ARF_TIMESTAMP 0xC0 -#define BRW_MRF_COMPR4 (1 << 7) +#define ELK_MRF_COMPR4 (1 << 7) -#define BRW_AMASK 0 -#define BRW_IMASK 1 -#define BRW_LMASK 2 -#define BRW_CMASK 3 +#define ELK_AMASK 0 +#define ELK_IMASK 1 +#define ELK_LMASK 2 +#define ELK_CMASK 3 -#define BRW_THREAD_NORMAL 0 -#define BRW_THREAD_ATOMIC 1 -#define BRW_THREAD_SWITCH 2 +#define ELK_THREAD_NORMAL 0 +#define ELK_THREAD_ATOMIC 1 +#define ELK_THREAD_SWITCH 2 -enum ENUM_PACKED brw_vertical_stride { - BRW_VERTICAL_STRIDE_0 = 0, - BRW_VERTICAL_STRIDE_1 = 1, - BRW_VERTICAL_STRIDE_2 = 2, - BRW_VERTICAL_STRIDE_4 = 3, - BRW_VERTICAL_STRIDE_8 = 4, - BRW_VERTICAL_STRIDE_16 = 5, - BRW_VERTICAL_STRIDE_32 = 6, - BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF, +enum ENUM_PACKED elk_vertical_stride { + ELK_VERTICAL_STRIDE_0 = 0, + ELK_VERTICAL_STRIDE_1 = 1, + ELK_VERTICAL_STRIDE_2 = 2, + ELK_VERTICAL_STRIDE_4 = 3, + ELK_VERTICAL_STRIDE_8 = 4, + ELK_VERTICAL_STRIDE_16 = 5, + ELK_VERTICAL_STRIDE_32 = 6, + ELK_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF, }; enum ENUM_PACKED gfx10_align1_3src_vertical_stride { - BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0, - BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1, - BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1, - BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2, - BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3, + ELK_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0, + ELK_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1, + ELK_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1, + ELK_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2, + ELK_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3, }; -enum ENUM_PACKED brw_width { - BRW_WIDTH_1 = 0, - BRW_WIDTH_2 = 1, - BRW_WIDTH_4 = 2, - BRW_WIDTH_8 = 3, - BRW_WIDTH_16 = 4, +enum ENUM_PACKED elk_width { + ELK_WIDTH_1 = 0, + ELK_WIDTH_2 = 1, + ELK_WIDTH_4 = 2, + ELK_WIDTH_8 = 3, + ELK_WIDTH_16 = 4, }; /** @@ -1142,20 +1142,20 @@ enum tgl_sbid_mode { enum gfx12_sub_byte_precision { - BRW_SUB_BYTE_PRECISION_NONE = 0, + ELK_SUB_BYTE_PRECISION_NONE = 0, /** 4 bits. Signedness determined by base type */ - BRW_SUB_BYTE_PRECISION_4BIT = 1, + ELK_SUB_BYTE_PRECISION_4BIT = 1, /** 2 bits. Signedness determined by base type */ - BRW_SUB_BYTE_PRECISION_2BIT = 2, + ELK_SUB_BYTE_PRECISION_2BIT = 2, }; -enum gfx12_systolic_depth { - BRW_SYSTOLIC_DEPTH_16 = 0, - BRW_SYSTOLIC_DEPTH_2 = 1, - BRW_SYSTOLIC_DEPTH_4 = 2, - BRW_SYSTOLIC_DEPTH_8 = 3, +enum elk_gfx12_systolic_depth { + ELK_SYSTOLIC_DEPTH_16 = 0, + ELK_SYSTOLIC_DEPTH_2 = 1, + ELK_SYSTOLIC_DEPTH_4 = 2, + ELK_SYSTOLIC_DEPTH_8 = 3, }; #ifdef __cplusplus @@ -1412,16 +1412,16 @@ enum tgl_sync_function { * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor" * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs" */ -enum brw_message_target { - BRW_SFID_NULL = 0, - BRW_SFID_MATH = 1, /* Only valid on Gfx4-5 */ - BRW_SFID_SAMPLER = 2, - BRW_SFID_MESSAGE_GATEWAY = 3, - BRW_SFID_DATAPORT_READ = 4, - BRW_SFID_DATAPORT_WRITE = 5, - BRW_SFID_URB = 6, - BRW_SFID_THREAD_SPAWNER = 7, - BRW_SFID_VME = 8, +enum elk_message_target { + ELK_SFID_NULL = 0, + ELK_SFID_MATH = 1, /* Only valid on Gfx4-5 */ + ELK_SFID_SAMPLER = 2, + ELK_SFID_MESSAGE_GATEWAY = 3, + ELK_SFID_DATAPORT_READ = 4, + ELK_SFID_DATAPORT_WRITE = 5, + ELK_SFID_URB = 6, + ELK_SFID_THREAD_SPAWNER = 7, + ELK_SFID_VME = 8, GFX6_SFID_DATAPORT_SAMPLER_CACHE = 4, GFX6_SFID_DATAPORT_RENDER_CACHE = 5, @@ -1439,31 +1439,31 @@ enum brw_message_target { #define GFX7_MESSAGE_TARGET_DP_DATA_CACHE 10 -#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 -#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 -#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 +#define ELK_SAMPLER_RETURN_FORMAT_FLOAT32 0 +#define ELK_SAMPLER_RETURN_FORMAT_UINT32 2 +#define ELK_SAMPLER_RETURN_FORMAT_SINT32 3 #define GFX8_SAMPLER_RETURN_FORMAT_32BITS 0 #define GFX8_SAMPLER_RETURN_FORMAT_16BITS 1 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 -#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 -#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 -#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 -#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 +#define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 +#define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 +#define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 +#define ELK_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 +#define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 +#define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 +#define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 +#define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 +#define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 +#define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 +#define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0 +#define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1 +#define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1 +#define ELK_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 +#define ELK_SAMPLER_MESSAGE_SIMD16_RESINFO 2 +#define ELK_SAMPLER_MESSAGE_SIMD4X2_LD 3 +#define ELK_SAMPLER_MESSAGE_SIMD8_LD 3 +#define ELK_SAMPLER_MESSAGE_SIMD16_LD 3 #define GFX5_SAMPLER_MESSAGE_SAMPLE 0 #define GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS 1 @@ -1492,10 +1492,10 @@ enum brw_message_target { #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31 /* for GFX5 only */ -#define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0 -#define BRW_SAMPLER_SIMD_MODE_SIMD8 1 -#define BRW_SAMPLER_SIMD_MODE_SIMD16 2 -#define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3 +#define ELK_SAMPLER_SIMD_MODE_SIMD4X2 0 +#define ELK_SAMPLER_SIMD_MODE_SIMD8 1 +#define ELK_SAMPLER_SIMD_MODE_SIMD16 2 +#define ELK_SAMPLER_SIMD_MODE_SIMD32_64 3 #define GFX10_SAMPLER_SIMD_MODE_SIMD8H 5 #define GFX10_SAMPLER_SIMD_MODE_SIMD16H 6 @@ -1510,38 +1510,38 @@ enum brw_message_target { #define GFX9_SAMPLER_SIMD_MODE_SIMD8D 0 #define GFX9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22) -#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 -#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 -#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 -#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 -#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 +#define ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 +#define ELK_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 +#define ELK_DATAPORT_OWORD_BLOCK_2_OWORDS 2 +#define ELK_DATAPORT_OWORD_BLOCK_4_OWORDS 3 +#define ELK_DATAPORT_OWORD_BLOCK_8_OWORDS 4 #define GFX12_DATAPORT_OWORD_BLOCK_16_OWORDS 5 -#define BRW_DATAPORT_OWORD_BLOCK_OWORDS(n) \ - ((n) == 1 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ - (n) == 2 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \ - (n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \ - (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \ +#define ELK_DATAPORT_OWORD_BLOCK_OWORDS(n) \ + ((n) == 1 ? ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ + (n) == 2 ? ELK_DATAPORT_OWORD_BLOCK_2_OWORDS : \ + (n) == 4 ? ELK_DATAPORT_OWORD_BLOCK_4_OWORDS : \ + (n) == 8 ? ELK_DATAPORT_OWORD_BLOCK_8_OWORDS : \ (n) == 16 ? GFX12_DATAPORT_OWORD_BLOCK_16_OWORDS : \ (abort(), ~0)) -#define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \ - ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ - (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \ - (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \ - (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \ +#define ELK_DATAPORT_OWORD_BLOCK_DWORDS(n) \ + ((n) == 4 ? ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ + (n) == 8 ? ELK_DATAPORT_OWORD_BLOCK_2_OWORDS : \ + (n) == 16 ? ELK_DATAPORT_OWORD_BLOCK_4_OWORDS : \ + (n) == 32 ? ELK_DATAPORT_OWORD_BLOCK_8_OWORDS : \ (abort(), ~0)) -#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 -#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 +#define ELK_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 +#define ELK_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 -#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 -#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 +#define ELK_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 +#define ELK_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 /* This one stays the same across generations. */ -#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 +#define ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 /* GFX4 */ -#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 -#define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2 -#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 +#define ELK_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 +#define ELK_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2 +#define ELK_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 /* G45, GFX5 */ #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 @@ -1555,23 +1555,23 @@ enum brw_message_target { #define GFX6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5 #define GFX6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 -#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 -#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 -#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 +#define ELK_DATAPORT_READ_TARGET_DATA_CACHE 0 +#define ELK_DATAPORT_READ_TARGET_RENDER_CACHE 1 +#define ELK_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 +#define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 +#define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 +#define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 +#define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 +#define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 -#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 -#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 -#define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2 -#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 -#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 -#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 -#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 +#define ELK_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 +#define ELK_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 +#define ELK_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2 +#define ELK_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 +#define ELK_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 +#define ELK_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 +#define ELK_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 /* GFX6 */ #define GFX6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7 @@ -1663,7 +1663,7 @@ enum brw_message_target { #define GFX8_A64_SCATTERED_SUBTYPE_HWORD 3 /* Dataport special binding table indices: */ -#define BRW_BTI_STATELESS 255 +#define ELK_BTI_STATELESS 255 #define GFX7_BTI_SLM 254 #define HSW_BTI_STATELESS_LOCALLY_COHERENT 255 @@ -1709,60 +1709,60 @@ enum brw_message_target { /* Dataport atomic operations for Untyped Atomic Integer Operation message * (and others). */ -#define BRW_AOP_AND 1 -#define BRW_AOP_OR 2 -#define BRW_AOP_XOR 3 -#define BRW_AOP_MOV 4 -#define BRW_AOP_INC 5 -#define BRW_AOP_DEC 6 -#define BRW_AOP_ADD 7 -#define BRW_AOP_SUB 8 -#define BRW_AOP_REVSUB 9 -#define BRW_AOP_IMAX 10 -#define BRW_AOP_IMIN 11 -#define BRW_AOP_UMAX 12 -#define BRW_AOP_UMIN 13 -#define BRW_AOP_CMPWR 14 -#define BRW_AOP_PREDEC 15 +#define ELK_AOP_AND 1 +#define ELK_AOP_OR 2 +#define ELK_AOP_XOR 3 +#define ELK_AOP_MOV 4 +#define ELK_AOP_INC 5 +#define ELK_AOP_DEC 6 +#define ELK_AOP_ADD 7 +#define ELK_AOP_SUB 8 +#define ELK_AOP_REVSUB 9 +#define ELK_AOP_IMAX 10 +#define ELK_AOP_IMIN 11 +#define ELK_AOP_UMAX 12 +#define ELK_AOP_UMIN 13 +#define ELK_AOP_CMPWR 14 +#define ELK_AOP_PREDEC 15 /* Dataport atomic operations for Untyped Atomic Float Operation message. */ -#define BRW_AOP_FMAX 1 -#define BRW_AOP_FMIN 2 -#define BRW_AOP_FCMPWR 3 -#define BRW_AOP_FADD 4 +#define ELK_AOP_FMAX 1 +#define ELK_AOP_FMIN 2 +#define ELK_AOP_FCMPWR 3 +#define ELK_AOP_FADD 4 -#define BRW_MATH_FUNCTION_INV 1 -#define BRW_MATH_FUNCTION_LOG 2 -#define BRW_MATH_FUNCTION_EXP 3 -#define BRW_MATH_FUNCTION_SQRT 4 -#define BRW_MATH_FUNCTION_RSQ 5 -#define BRW_MATH_FUNCTION_SIN 6 -#define BRW_MATH_FUNCTION_COS 7 -#define BRW_MATH_FUNCTION_SINCOS 8 /* gfx4, gfx5 */ -#define BRW_MATH_FUNCTION_FDIV 9 /* gfx6+ */ -#define BRW_MATH_FUNCTION_POW 10 -#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 -#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 -#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 +#define ELK_MATH_FUNCTION_INV 1 +#define ELK_MATH_FUNCTION_LOG 2 +#define ELK_MATH_FUNCTION_EXP 3 +#define ELK_MATH_FUNCTION_SQRT 4 +#define ELK_MATH_FUNCTION_RSQ 5 +#define ELK_MATH_FUNCTION_SIN 6 +#define ELK_MATH_FUNCTION_COS 7 +#define ELK_MATH_FUNCTION_SINCOS 8 /* gfx4, gfx5 */ +#define ELK_MATH_FUNCTION_FDIV 9 /* gfx6+ */ +#define ELK_MATH_FUNCTION_POW 10 +#define ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 +#define ELK_MATH_FUNCTION_INT_DIV_QUOTIENT 12 +#define ELK_MATH_FUNCTION_INT_DIV_REMAINDER 13 #define GFX8_MATH_FUNCTION_INVM 14 #define GFX8_MATH_FUNCTION_RSQRTM 15 -#define BRW_MATH_INTEGER_UNSIGNED 0 -#define BRW_MATH_INTEGER_SIGNED 1 +#define ELK_MATH_INTEGER_UNSIGNED 0 +#define ELK_MATH_INTEGER_SIGNED 1 -#define BRW_MATH_PRECISION_FULL 0 -#define BRW_MATH_PRECISION_PARTIAL 1 +#define ELK_MATH_PRECISION_FULL 0 +#define ELK_MATH_PRECISION_PARTIAL 1 -#define BRW_MATH_SATURATE_NONE 0 -#define BRW_MATH_SATURATE_SATURATE 1 +#define ELK_MATH_SATURATE_NONE 0 +#define ELK_MATH_SATURATE_SATURATE 1 -#define BRW_MATH_DATA_VECTOR 0 -#define BRW_MATH_DATA_SCALAR 1 +#define ELK_MATH_DATA_VECTOR 0 +#define ELK_MATH_DATA_SCALAR 1 -#define BRW_URB_OPCODE_WRITE_HWORD 0 -#define BRW_URB_OPCODE_WRITE_OWORD 1 -#define BRW_URB_OPCODE_READ_HWORD 2 -#define BRW_URB_OPCODE_READ_OWORD 3 +#define ELK_URB_OPCODE_WRITE_HWORD 0 +#define ELK_URB_OPCODE_WRITE_OWORD 1 +#define ELK_URB_OPCODE_READ_HWORD 2 +#define ELK_URB_OPCODE_READ_OWORD 3 #define GFX7_URB_OPCODE_ATOMIC_MOV 4 #define GFX7_URB_OPCODE_ATOMIC_INC 5 #define GFX8_URB_OPCODE_ATOMIC_ADD 6 @@ -1770,30 +1770,30 @@ enum brw_message_target { #define GFX8_URB_OPCODE_SIMD8_READ 8 #define GFX125_URB_OPCODE_FENCE 9 -#define BRW_URB_SWIZZLE_NONE 0 -#define BRW_URB_SWIZZLE_INTERLEAVE 1 -#define BRW_URB_SWIZZLE_TRANSPOSE 2 +#define ELK_URB_SWIZZLE_NONE 0 +#define ELK_URB_SWIZZLE_INTERLEAVE 1 +#define ELK_URB_SWIZZLE_TRANSPOSE 2 -#define BRW_SCRATCH_SPACE_SIZE_1K 0 -#define BRW_SCRATCH_SPACE_SIZE_2K 1 -#define BRW_SCRATCH_SPACE_SIZE_4K 2 -#define BRW_SCRATCH_SPACE_SIZE_8K 3 -#define BRW_SCRATCH_SPACE_SIZE_16K 4 -#define BRW_SCRATCH_SPACE_SIZE_32K 5 -#define BRW_SCRATCH_SPACE_SIZE_64K 6 -#define BRW_SCRATCH_SPACE_SIZE_128K 7 -#define BRW_SCRATCH_SPACE_SIZE_256K 8 -#define BRW_SCRATCH_SPACE_SIZE_512K 9 -#define BRW_SCRATCH_SPACE_SIZE_1M 10 -#define BRW_SCRATCH_SPACE_SIZE_2M 11 +#define ELK_SCRATCH_SPACE_SIZE_1K 0 +#define ELK_SCRATCH_SPACE_SIZE_2K 1 +#define ELK_SCRATCH_SPACE_SIZE_4K 2 +#define ELK_SCRATCH_SPACE_SIZE_8K 3 +#define ELK_SCRATCH_SPACE_SIZE_16K 4 +#define ELK_SCRATCH_SPACE_SIZE_32K 5 +#define ELK_SCRATCH_SPACE_SIZE_64K 6 +#define ELK_SCRATCH_SPACE_SIZE_128K 7 +#define ELK_SCRATCH_SPACE_SIZE_256K 8 +#define ELK_SCRATCH_SPACE_SIZE_512K 9 +#define ELK_SCRATCH_SPACE_SIZE_1M 10 +#define ELK_SCRATCH_SPACE_SIZE_2M 11 -#define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0 -#define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1 -#define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2 -#define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3 -#define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4 -#define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5 -#define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6 +#define ELK_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0 +#define ELK_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1 +#define ELK_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2 +#define ELK_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3 +#define ELK_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4 +#define ELK_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5 +#define ELK_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6 /* Gfx7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size @@ -1806,8 +1806,8 @@ enum brw_message_target { #define GFX7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64) #define GFX7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64) -#define BRW_GS_EDGE_INDICATOR_0 (1 << 8) -#define BRW_GS_EDGE_INDICATOR_1 (1 << 9) +#define ELK_GS_EDGE_INDICATOR_0 (1 << 8) +#define ELK_GS_EDGE_INDICATOR_1 (1 << 9) /* Gfx6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit * (128 bytes) URB rows and the maximum allowed value is 5 rows. @@ -1830,25 +1830,25 @@ enum brw_message_target { * Skylake PRM, Volume 7 Part 1, "Control Register", page 756 */ -#define BRW_CR0_RND_MODE_MASK 0x30 -#define BRW_CR0_RND_MODE_SHIFT 4 +#define ELK_CR0_RND_MODE_MASK 0x30 +#define ELK_CR0_RND_MODE_SHIFT 4 -enum ENUM_PACKED brw_rnd_mode { - BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */ - BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */ - BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */ - BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */ - BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */ +enum ENUM_PACKED elk_rnd_mode { + ELK_RND_MODE_RTNE = 0, /* Round to Nearest or Even */ + ELK_RND_MODE_RU = 1, /* Round Up, toward +inf */ + ELK_RND_MODE_RD = 2, /* Round Down, toward -inf */ + ELK_RND_MODE_RTZ = 3, /* Round Toward Zero */ + ELK_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */ }; -#define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6) -#define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7) -#define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10) +#define ELK_CR0_FP64_DENORM_PRESERVE (1 << 6) +#define ELK_CR0_FP32_DENORM_PRESERVE (1 << 7) +#define ELK_CR0_FP16_DENORM_PRESERVE (1 << 10) -#define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \ - BRW_CR0_FP32_DENORM_PRESERVE | \ - BRW_CR0_FP16_DENORM_PRESERVE | \ - BRW_CR0_RND_MODE_MASK) +#define ELK_CR0_FP_MODE_MASK (ELK_CR0_FP64_DENORM_PRESERVE | \ + ELK_CR0_FP32_DENORM_PRESERVE | \ + ELK_CR0_FP16_DENORM_PRESERVE | \ + ELK_CR0_RND_MODE_MASK) /* MDC_DS - Data Size Message Descriptor Control Field * Skylake PRM, Volume 2d, page 129 @@ -1868,7 +1868,7 @@ enum ENUM_PACKED brw_rnd_mode { * get to rewrite all our dataport encoding/decoding code. This patch kicks * off the party with all of the new enums. */ -enum lsc_opcode { +enum elk_lsc_opcode { LSC_OP_LOAD = 0, LSC_OP_LOAD_CMASK = 2, LSC_OP_STORE = 4, diff --git a/src/intel/compiler/elk/elk_eu_emit.c b/src/intel/compiler/elk/elk_eu_emit.c index 0549b57048c..289d013d959 100644 --- a/src/intel/compiler/elk/elk_eu_emit.c +++ b/src/intel/compiler/elk/elk_eu_emit.c @@ -43,32 +43,32 @@ * explicit move; it should be called before emitting a SEND instruction. */ void -gfx6_resolve_implied_move(struct brw_codegen *p, - struct brw_reg *src, +elk_gfx6_resolve_implied_move(struct elk_codegen *p, + struct elk_reg *src, unsigned msg_reg_nr) { const struct intel_device_info *devinfo = p->devinfo; if (devinfo->ver < 6) return; - if (src->file == BRW_MESSAGE_REGISTER_FILE) + if (src->file == ELK_MESSAGE_REGISTER_FILE) return; - if (src->file != BRW_ARCHITECTURE_REGISTER_FILE || src->nr != BRW_ARF_NULL) { + if (src->file != ELK_ARCHITECTURE_REGISTER_FILE || src->nr != ELK_ARF_NULL) { assert(devinfo->ver < 12); - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD), - retype(*src, BRW_REGISTER_TYPE_UD)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); + elk_MOV(p, retype(elk_message_reg(msg_reg_nr), ELK_REGISTER_TYPE_UD), + retype(*src, ELK_REGISTER_TYPE_UD)); + elk_pop_insn_state(p); } - *src = brw_message_reg(msg_reg_nr); + *src = elk_message_reg(msg_reg_nr); } static void -gfx7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg) +gfx7_convert_mrf_to_grf(struct elk_codegen *p, struct elk_reg *reg) { /* From the Ivybridge PRM, Volume 4 Part 3, page 218 ("send"): * "The send with EOT should use register space R112-R127 for . This is @@ -79,20 +79,20 @@ gfx7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg) * registers required for messages with EOT. */ const struct intel_device_info *devinfo = p->devinfo; - if (devinfo->ver >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) { - reg->file = BRW_GENERAL_REGISTER_FILE; + if (devinfo->ver >= 7 && reg->file == ELK_MESSAGE_REGISTER_FILE) { + reg->file = ELK_GENERAL_REGISTER_FILE; reg->nr += GFX7_MRF_HACK_START; } } void -brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) +elk_set_dest(struct elk_codegen *p, elk_inst *inst, struct elk_reg dest) { const struct intel_device_info *devinfo = p->devinfo; - if (dest.file == BRW_MESSAGE_REGISTER_FILE) - assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver)); - else if (dest.file == BRW_GENERAL_REGISTER_FILE) + if (dest.file == ELK_MESSAGE_REGISTER_FILE) + assert((dest.nr & ~ELK_MRF_COMPR4) < ELK_MAX_MRF(devinfo->ver)); + else if (dest.file == ELK_GENERAL_REGISTER_FILE) assert(dest.nr < XE2_MAX_GRF); /* The hardware has a restriction where a destination of size Byte with @@ -100,83 +100,83 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) * instruction, the stride must be at least 2, even when the destination * is the NULL register. */ - if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && - dest.nr == BRW_ARF_NULL && + if (dest.file == ELK_ARCHITECTURE_REGISTER_FILE && + dest.nr == ELK_ARF_NULL && type_sz(dest.type) == 1 && - dest.hstride == BRW_HORIZONTAL_STRIDE_1) { - dest.hstride = BRW_HORIZONTAL_STRIDE_2; + dest.hstride == ELK_HORIZONTAL_STRIDE_1) { + dest.hstride = ELK_HORIZONTAL_STRIDE_2; } gfx7_convert_mrf_to_grf(p, &dest); if (devinfo->ver >= 12 && - (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC)) { - assert(dest.file == BRW_GENERAL_REGISTER_FILE || - dest.file == BRW_ARCHITECTURE_REGISTER_FILE); - assert(dest.address_mode == BRW_ADDRESS_DIRECT); + (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SEND || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDC)) { + assert(dest.file == ELK_GENERAL_REGISTER_FILE || + dest.file == ELK_ARCHITECTURE_REGISTER_FILE); + assert(dest.address_mode == ELK_ADDRESS_DIRECT); assert(dest.subnr == 0); - assert(brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1 || - (dest.hstride == BRW_HORIZONTAL_STRIDE_1 && + assert(elk_inst_exec_size(devinfo, inst) == ELK_EXECUTE_1 || + (dest.hstride == ELK_HORIZONTAL_STRIDE_1 && dest.vstride == dest.width + 1)); assert(!dest.negate && !dest.abs); - brw_inst_set_dst_reg_file(devinfo, inst, dest.file); - brw_inst_set_dst_da_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); + elk_inst_set_dst_reg_file(devinfo, inst, dest.file); + elk_inst_set_dst_da_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); - } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC) { + } else if (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDS || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDSC) { assert(devinfo->ver < 12); - assert(dest.file == BRW_GENERAL_REGISTER_FILE || - dest.file == BRW_ARCHITECTURE_REGISTER_FILE); - assert(dest.address_mode == BRW_ADDRESS_DIRECT); + assert(dest.file == ELK_GENERAL_REGISTER_FILE || + dest.file == ELK_ARCHITECTURE_REGISTER_FILE); + assert(dest.address_mode == ELK_ADDRESS_DIRECT); assert(dest.subnr % 16 == 0); - assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1 && + assert(dest.hstride == ELK_HORIZONTAL_STRIDE_1 && dest.vstride == dest.width + 1); assert(!dest.negate && !dest.abs); - brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr); - brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16); - brw_inst_set_send_dst_reg_file(devinfo, inst, dest.file); + elk_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr); + elk_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16); + elk_inst_set_send_dst_reg_file(devinfo, inst, dest.file); } else { - brw_inst_set_dst_file_type(devinfo, inst, dest.file, dest.type); - brw_inst_set_dst_address_mode(devinfo, inst, dest.address_mode); + elk_inst_set_dst_file_type(devinfo, inst, dest.file, dest.type); + elk_inst_set_dst_address_mode(devinfo, inst, dest.address_mode); - if (dest.address_mode == BRW_ADDRESS_DIRECT) { - brw_inst_set_dst_da_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); + if (dest.address_mode == ELK_ADDRESS_DIRECT) { + elk_inst_set_dst_da_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - brw_inst_set_dst_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest)); - if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) - dest.hstride = BRW_HORIZONTAL_STRIDE_1; - brw_inst_set_dst_hstride(devinfo, inst, dest.hstride); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + elk_inst_set_dst_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest)); + if (dest.hstride == ELK_HORIZONTAL_STRIDE_0) + dest.hstride = ELK_HORIZONTAL_STRIDE_1; + elk_inst_set_dst_hstride(devinfo, inst, dest.hstride); } else { - brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16); - brw_inst_set_da16_writemask(devinfo, inst, dest.writemask); - if (dest.file == BRW_GENERAL_REGISTER_FILE || - dest.file == BRW_MESSAGE_REGISTER_FILE) { + elk_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16); + elk_inst_set_da16_writemask(devinfo, inst, dest.writemask); + if (dest.file == ELK_GENERAL_REGISTER_FILE || + dest.file == ELK_MESSAGE_REGISTER_FILE) { assert(dest.writemask != 0); } /* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1: * Although Dst.HorzStride is a don't care for Align16, HW needs * this to be programmed as "01". */ - brw_inst_set_dst_hstride(devinfo, inst, 1); + elk_inst_set_dst_hstride(devinfo, inst, 1); } } else { - brw_inst_set_dst_ia_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest)); + elk_inst_set_dst_ia_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest)); /* These are different sizes in align1 vs align16: */ - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - brw_inst_set_dst_ia1_addr_imm(devinfo, inst, + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + elk_inst_set_dst_ia1_addr_imm(devinfo, inst, dest.indirect_offset); - if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) - dest.hstride = BRW_HORIZONTAL_STRIDE_1; - brw_inst_set_dst_hstride(devinfo, inst, dest.hstride); + if (dest.hstride == ELK_HORIZONTAL_STRIDE_0) + dest.hstride = ELK_HORIZONTAL_STRIDE_1; + elk_inst_set_dst_hstride(devinfo, inst, dest.hstride); } else { - brw_inst_set_dst_ia16_addr_imm(devinfo, inst, + elk_inst_set_dst_ia16_addr_imm(devinfo, inst, dest.indirect_offset); /* even ignored in da16, still need to set as '01' */ - brw_inst_set_dst_hstride(devinfo, inst, 1); + elk_inst_set_dst_hstride(devinfo, inst, 1); } } } @@ -196,134 +196,134 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) */ bool fix_exec_size; if (devinfo->ver >= 6) - fix_exec_size = dest.width < BRW_EXECUTE_4; + fix_exec_size = dest.width < ELK_EXECUTE_4; else - fix_exec_size = dest.width < BRW_EXECUTE_8; + fix_exec_size = dest.width < ELK_EXECUTE_8; if (fix_exec_size) - brw_inst_set_exec_size(devinfo, inst, dest.width); + elk_inst_set_exec_size(devinfo, inst, dest.width); } } void -brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) +elk_set_src0(struct elk_codegen *p, elk_inst *inst, struct elk_reg reg) { const struct intel_device_info *devinfo = p->devinfo; - if (reg.file == BRW_MESSAGE_REGISTER_FILE) - assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver)); - else if (reg.file == BRW_GENERAL_REGISTER_FILE) + if (reg.file == ELK_MESSAGE_REGISTER_FILE) + assert((reg.nr & ~ELK_MRF_COMPR4) < ELK_MAX_MRF(devinfo->ver)); + else if (reg.file == ELK_GENERAL_REGISTER_FILE) assert(reg.nr < XE2_MAX_GRF); gfx7_convert_mrf_to_grf(p, ®); if (devinfo->ver >= 6 && - (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC)) { + (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SEND || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDC || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDS || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDSC)) { /* Any source modifiers or regions will be ignored, since this just * identifies the MRF/GRF to start reading the message contents from. * Check for some likely failures. */ assert(!reg.negate); assert(!reg.abs); - assert(reg.address_mode == BRW_ADDRESS_DIRECT); + assert(reg.address_mode == ELK_ADDRESS_DIRECT); } if (devinfo->ver >= 12 && - (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC)) { - assert(reg.file != BRW_IMMEDIATE_VALUE); - assert(reg.address_mode == BRW_ADDRESS_DIRECT); + (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SEND || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDC)) { + assert(reg.file != ELK_IMMEDIATE_VALUE); + assert(reg.address_mode == ELK_ADDRESS_DIRECT); assert(reg.subnr == 0); assert(has_scalar_region(reg) || - (reg.hstride == BRW_HORIZONTAL_STRIDE_1 && + (reg.hstride == ELK_HORIZONTAL_STRIDE_1 && reg.vstride == reg.width + 1)); assert(!reg.negate && !reg.abs); - brw_inst_set_send_src0_reg_file(devinfo, inst, reg.file); - brw_inst_set_src0_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); + elk_inst_set_send_src0_reg_file(devinfo, inst, reg.file); + elk_inst_set_src0_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); - } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC) { - assert(reg.file == BRW_GENERAL_REGISTER_FILE); - assert(reg.address_mode == BRW_ADDRESS_DIRECT); + } else if (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDS || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDSC) { + assert(reg.file == ELK_GENERAL_REGISTER_FILE); + assert(reg.address_mode == ELK_ADDRESS_DIRECT); assert(reg.subnr % 16 == 0); assert(has_scalar_region(reg) || - (reg.hstride == BRW_HORIZONTAL_STRIDE_1 && + (reg.hstride == ELK_HORIZONTAL_STRIDE_1 && reg.vstride == reg.width + 1)); assert(!reg.negate && !reg.abs); - brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr); - brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16); + elk_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr); + elk_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16); } else { - brw_inst_set_src0_file_type(devinfo, inst, reg.file, reg.type); - brw_inst_set_src0_abs(devinfo, inst, reg.abs); - brw_inst_set_src0_negate(devinfo, inst, reg.negate); - brw_inst_set_src0_address_mode(devinfo, inst, reg.address_mode); + elk_inst_set_src0_file_type(devinfo, inst, reg.file, reg.type); + elk_inst_set_src0_abs(devinfo, inst, reg.abs); + elk_inst_set_src0_negate(devinfo, inst, reg.negate); + elk_inst_set_src0_address_mode(devinfo, inst, reg.address_mode); - if (reg.file == BRW_IMMEDIATE_VALUE) { - if (reg.type == BRW_REGISTER_TYPE_DF || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_DIM) - brw_inst_set_imm_df(devinfo, inst, reg.df); - else if (reg.type == BRW_REGISTER_TYPE_UQ || - reg.type == BRW_REGISTER_TYPE_Q) - brw_inst_set_imm_uq(devinfo, inst, reg.u64); + if (reg.file == ELK_IMMEDIATE_VALUE) { + if (reg.type == ELK_REGISTER_TYPE_DF || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_DIM) + elk_inst_set_imm_df(devinfo, inst, reg.df); + else if (reg.type == ELK_REGISTER_TYPE_UQ || + reg.type == ELK_REGISTER_TYPE_Q) + elk_inst_set_imm_uq(devinfo, inst, reg.u64); else - brw_inst_set_imm_ud(devinfo, inst, reg.ud); + elk_inst_set_imm_ud(devinfo, inst, reg.ud); if (devinfo->ver < 12 && type_sz(reg.type) < 8) { - brw_inst_set_src1_reg_file(devinfo, inst, - BRW_ARCHITECTURE_REGISTER_FILE); - brw_inst_set_src1_reg_hw_type(devinfo, inst, - brw_inst_src0_reg_hw_type(devinfo, inst)); + elk_inst_set_src1_reg_file(devinfo, inst, + ELK_ARCHITECTURE_REGISTER_FILE); + elk_inst_set_src1_reg_hw_type(devinfo, inst, + elk_inst_src0_reg_hw_type(devinfo, inst)); } } else { - if (reg.address_mode == BRW_ADDRESS_DIRECT) { - brw_inst_set_src0_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - brw_inst_set_src0_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); + if (reg.address_mode == ELK_ADDRESS_DIRECT) { + elk_inst_set_src0_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + elk_inst_set_src0_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); } else { - brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16); + elk_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16); } } else { - brw_inst_set_src0_ia_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); + elk_inst_set_src0_ia_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - brw_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.indirect_offset); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + elk_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.indirect_offset); } else { - brw_inst_set_src0_ia16_addr_imm(devinfo, inst, reg.indirect_offset); + elk_inst_set_src0_ia16_addr_imm(devinfo, inst, reg.indirect_offset); } } - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - if (reg.width == BRW_WIDTH_1 && - brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1) { - brw_inst_set_src0_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_0); - brw_inst_set_src0_width(devinfo, inst, BRW_WIDTH_1); - brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + if (reg.width == ELK_WIDTH_1 && + elk_inst_exec_size(devinfo, inst) == ELK_EXECUTE_1) { + elk_inst_set_src0_hstride(devinfo, inst, ELK_HORIZONTAL_STRIDE_0); + elk_inst_set_src0_width(devinfo, inst, ELK_WIDTH_1); + elk_inst_set_src0_vstride(devinfo, inst, ELK_VERTICAL_STRIDE_0); } else { - brw_inst_set_src0_hstride(devinfo, inst, reg.hstride); - brw_inst_set_src0_width(devinfo, inst, reg.width); - brw_inst_set_src0_vstride(devinfo, inst, reg.vstride); + elk_inst_set_src0_hstride(devinfo, inst, reg.hstride); + elk_inst_set_src0_width(devinfo, inst, reg.width); + elk_inst_set_src0_vstride(devinfo, inst, reg.vstride); } } else { - brw_inst_set_src0_da16_swiz_x(devinfo, inst, - BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_X)); - brw_inst_set_src0_da16_swiz_y(devinfo, inst, - BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Y)); - brw_inst_set_src0_da16_swiz_z(devinfo, inst, - BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z)); - brw_inst_set_src0_da16_swiz_w(devinfo, inst, - BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W)); + elk_inst_set_src0_da16_swiz_x(devinfo, inst, + ELK_GET_SWZ(reg.swizzle, ELK_CHANNEL_X)); + elk_inst_set_src0_da16_swiz_y(devinfo, inst, + ELK_GET_SWZ(reg.swizzle, ELK_CHANNEL_Y)); + elk_inst_set_src0_da16_swiz_z(devinfo, inst, + ELK_GET_SWZ(reg.swizzle, ELK_CHANNEL_Z)); + elk_inst_set_src0_da16_swiz_w(devinfo, inst, + ELK_GET_SWZ(reg.swizzle, ELK_CHANNEL_W)); - if (reg.vstride == BRW_VERTICAL_STRIDE_8) { + if (reg.vstride == ELK_VERTICAL_STRIDE_8) { /* This is an oddity of the fact we're using the same * descriptions for registers in align_16 as align_1: */ - brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); + elk_inst_set_src0_vstride(devinfo, inst, ELK_VERTICAL_STRIDE_4); } else if (devinfo->verx10 == 70 && - reg.type == BRW_REGISTER_TYPE_DF && - reg.vstride == BRW_VERTICAL_STRIDE_2) { + reg.type == ELK_REGISTER_TYPE_DF && + reg.vstride == ELK_VERTICAL_STRIDE_2) { /* From SNB PRM: * * "For Align16 access mode, only encodings of 0000 and 0011 @@ -331,9 +331,9 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) * * Presumably the DevSNB behavior applies to IVB as well. */ - brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); + elk_inst_set_src0_vstride(devinfo, inst, ELK_VERTICAL_STRIDE_4); } else { - brw_inst_set_src0_vstride(devinfo, inst, reg.vstride); + elk_inst_set_src0_vstride(devinfo, inst, reg.vstride); } } } @@ -342,95 +342,95 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) void -brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) +elk_set_src1(struct elk_codegen *p, elk_inst *inst, struct elk_reg reg) { const struct intel_device_info *devinfo = p->devinfo; - if (reg.file == BRW_GENERAL_REGISTER_FILE) + if (reg.file == ELK_GENERAL_REGISTER_FILE) assert(reg.nr < XE2_MAX_GRF); - if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC || + if (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDS || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDSC || (devinfo->ver >= 12 && - (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC))) { - assert(reg.file == BRW_GENERAL_REGISTER_FILE || - reg.file == BRW_ARCHITECTURE_REGISTER_FILE); - assert(reg.address_mode == BRW_ADDRESS_DIRECT); + (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SEND || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDC))) { + assert(reg.file == ELK_GENERAL_REGISTER_FILE || + reg.file == ELK_ARCHITECTURE_REGISTER_FILE); + assert(reg.address_mode == ELK_ADDRESS_DIRECT); assert(reg.subnr == 0); assert(has_scalar_region(reg) || - (reg.hstride == BRW_HORIZONTAL_STRIDE_1 && + (reg.hstride == ELK_HORIZONTAL_STRIDE_1 && reg.vstride == reg.width + 1)); assert(!reg.negate && !reg.abs); - brw_inst_set_send_src1_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); - brw_inst_set_send_src1_reg_file(devinfo, inst, reg.file); + elk_inst_set_send_src1_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); + elk_inst_set_send_src1_reg_file(devinfo, inst, reg.file); } else { /* From the IVB PRM Vol. 4, Pt. 3, Section 3.3.3.5: * * "Accumulator registers may be accessed explicitly as src0 * operands only." */ - assert(reg.file != BRW_ARCHITECTURE_REGISTER_FILE || - reg.nr != BRW_ARF_ACCUMULATOR); + assert(reg.file != ELK_ARCHITECTURE_REGISTER_FILE || + reg.nr != ELK_ARF_ACCUMULATOR); gfx7_convert_mrf_to_grf(p, ®); - assert(reg.file != BRW_MESSAGE_REGISTER_FILE); + assert(reg.file != ELK_MESSAGE_REGISTER_FILE); - brw_inst_set_src1_file_type(devinfo, inst, reg.file, reg.type); - brw_inst_set_src1_abs(devinfo, inst, reg.abs); - brw_inst_set_src1_negate(devinfo, inst, reg.negate); + elk_inst_set_src1_file_type(devinfo, inst, reg.file, reg.type); + elk_inst_set_src1_abs(devinfo, inst, reg.abs); + elk_inst_set_src1_negate(devinfo, inst, reg.negate); /* Only src1 can be immediate in two-argument instructions. */ - assert(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE); + assert(elk_inst_src0_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE); - if (reg.file == BRW_IMMEDIATE_VALUE) { + if (reg.file == ELK_IMMEDIATE_VALUE) { /* two-argument instructions can only use 32-bit immediates */ assert(type_sz(reg.type) < 8); - brw_inst_set_imm_ud(devinfo, inst, reg.ud); + elk_inst_set_imm_ud(devinfo, inst, reg.ud); } else { /* This is a hardware restriction, which may or may not be lifted * in the future: */ - assert (reg.address_mode == BRW_ADDRESS_DIRECT); - /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */ + assert (reg.address_mode == ELK_ADDRESS_DIRECT); + /* assert (reg.file == ELK_GENERAL_REGISTER_FILE); */ - brw_inst_set_src1_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - brw_inst_set_src1_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); + elk_inst_set_src1_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + elk_inst_set_src1_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); } else { - brw_inst_set_src1_da16_subreg_nr(devinfo, inst, reg.subnr / 16); + elk_inst_set_src1_da16_subreg_nr(devinfo, inst, reg.subnr / 16); } - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - if (reg.width == BRW_WIDTH_1 && - brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1) { - brw_inst_set_src1_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_0); - brw_inst_set_src1_width(devinfo, inst, BRW_WIDTH_1); - brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + if (reg.width == ELK_WIDTH_1 && + elk_inst_exec_size(devinfo, inst) == ELK_EXECUTE_1) { + elk_inst_set_src1_hstride(devinfo, inst, ELK_HORIZONTAL_STRIDE_0); + elk_inst_set_src1_width(devinfo, inst, ELK_WIDTH_1); + elk_inst_set_src1_vstride(devinfo, inst, ELK_VERTICAL_STRIDE_0); } else { - brw_inst_set_src1_hstride(devinfo, inst, reg.hstride); - brw_inst_set_src1_width(devinfo, inst, reg.width); - brw_inst_set_src1_vstride(devinfo, inst, reg.vstride); + elk_inst_set_src1_hstride(devinfo, inst, reg.hstride); + elk_inst_set_src1_width(devinfo, inst, reg.width); + elk_inst_set_src1_vstride(devinfo, inst, reg.vstride); } } else { - brw_inst_set_src1_da16_swiz_x(devinfo, inst, - BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_X)); - brw_inst_set_src1_da16_swiz_y(devinfo, inst, - BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Y)); - brw_inst_set_src1_da16_swiz_z(devinfo, inst, - BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z)); - brw_inst_set_src1_da16_swiz_w(devinfo, inst, - BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W)); + elk_inst_set_src1_da16_swiz_x(devinfo, inst, + ELK_GET_SWZ(reg.swizzle, ELK_CHANNEL_X)); + elk_inst_set_src1_da16_swiz_y(devinfo, inst, + ELK_GET_SWZ(reg.swizzle, ELK_CHANNEL_Y)); + elk_inst_set_src1_da16_swiz_z(devinfo, inst, + ELK_GET_SWZ(reg.swizzle, ELK_CHANNEL_Z)); + elk_inst_set_src1_da16_swiz_w(devinfo, inst, + ELK_GET_SWZ(reg.swizzle, ELK_CHANNEL_W)); - if (reg.vstride == BRW_VERTICAL_STRIDE_8) { + if (reg.vstride == ELK_VERTICAL_STRIDE_8) { /* This is an oddity of the fact we're using the same * descriptions for registers in align_16 as align_1: */ - brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); + elk_inst_set_src1_vstride(devinfo, inst, ELK_VERTICAL_STRIDE_4); } else if (devinfo->verx10 == 70 && - reg.type == BRW_REGISTER_TYPE_DF && - reg.vstride == BRW_VERTICAL_STRIDE_2) { + reg.type == ELK_REGISTER_TYPE_DF && + reg.vstride == ELK_VERTICAL_STRIDE_2) { /* From SNB PRM: * * "For Align16 access mode, only encodings of 0000 and 0011 @@ -438,9 +438,9 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) * * Presumably the DevSNB behavior applies to IVB as well. */ - brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); + elk_inst_set_src1_vstride(devinfo, inst, ELK_VERTICAL_STRIDE_4); } else { - brw_inst_set_src1_vstride(devinfo, inst, reg.vstride); + elk_inst_set_src1_vstride(devinfo, inst, reg.vstride); } } } @@ -452,22 +452,22 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) * message instruction. */ void -brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst, +elk_set_desc_ex(struct elk_codegen *p, elk_inst *inst, unsigned desc, unsigned ex_desc) { const struct intel_device_info *devinfo = p->devinfo; - assert(brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND || - brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC); + assert(elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SEND || + elk_inst_opcode(p->isa, inst) == ELK_OPCODE_SENDC); if (devinfo->ver < 12) - brw_inst_set_src1_file_type(devinfo, inst, - BRW_IMMEDIATE_VALUE, BRW_REGISTER_TYPE_UD); - brw_inst_set_send_desc(devinfo, inst, desc); + elk_inst_set_src1_file_type(devinfo, inst, + ELK_IMMEDIATE_VALUE, ELK_REGISTER_TYPE_UD); + elk_inst_set_send_desc(devinfo, inst, desc); if (devinfo->ver >= 9) - brw_inst_set_send_ex_desc(devinfo, inst, ex_desc); + elk_inst_set_send_ex_desc(devinfo, inst, ex_desc); } -static void brw_set_math_message( struct brw_codegen *p, - brw_inst *inst, +static void elk_set_math_message( struct elk_codegen *p, + elk_inst *inst, unsigned function, unsigned integer_type, bool low_precision, @@ -479,10 +479,10 @@ static void brw_set_math_message( struct brw_codegen *p, /* Infer message length from the function */ switch (function) { - case BRW_MATH_FUNCTION_POW: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT: - case BRW_MATH_FUNCTION_INT_DIV_REMAINDER: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: + case ELK_MATH_FUNCTION_POW: + case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT: + case ELK_MATH_FUNCTION_INT_DIV_REMAINDER: + case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: msg_length = 2; break; default: @@ -492,8 +492,8 @@ static void brw_set_math_message( struct brw_codegen *p, /* Infer response length from the function */ switch (function) { - case BRW_MATH_FUNCTION_SINCOS: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: + case ELK_MATH_FUNCTION_SINCOS: + case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: response_length = 2; break; default: @@ -501,44 +501,44 @@ static void brw_set_math_message( struct brw_codegen *p, break; } - brw_set_desc(p, inst, brw_message_desc( + elk_set_desc(p, inst, elk_message_desc( devinfo, msg_length, response_length, false)); - brw_inst_set_sfid(devinfo, inst, BRW_SFID_MATH); - brw_inst_set_math_msg_function(devinfo, inst, function); - brw_inst_set_math_msg_signed_int(devinfo, inst, integer_type); - brw_inst_set_math_msg_precision(devinfo, inst, low_precision); - brw_inst_set_math_msg_saturate(devinfo, inst, brw_inst_saturate(devinfo, inst)); - brw_inst_set_math_msg_data_type(devinfo, inst, dataType); - brw_inst_set_saturate(devinfo, inst, 0); + elk_inst_set_sfid(devinfo, inst, ELK_SFID_MATH); + elk_inst_set_math_msg_function(devinfo, inst, function); + elk_inst_set_math_msg_signed_int(devinfo, inst, integer_type); + elk_inst_set_math_msg_precision(devinfo, inst, low_precision); + elk_inst_set_math_msg_saturate(devinfo, inst, elk_inst_saturate(devinfo, inst)); + elk_inst_set_math_msg_data_type(devinfo, inst, dataType); + elk_inst_set_saturate(devinfo, inst, 0); } -static void brw_set_ff_sync_message(struct brw_codegen *p, - brw_inst *insn, +static void elk_set_ff_sync_message(struct elk_codegen *p, + elk_inst *insn, bool allocate, unsigned response_length, bool end_of_thread) { const struct intel_device_info *devinfo = p->devinfo; - brw_set_desc(p, insn, brw_message_desc( + elk_set_desc(p, insn, elk_message_desc( devinfo, 1, response_length, true)); - brw_inst_set_sfid(devinfo, insn, BRW_SFID_URB); - brw_inst_set_eot(devinfo, insn, end_of_thread); - brw_inst_set_urb_opcode(devinfo, insn, 1); /* FF_SYNC */ - brw_inst_set_urb_allocate(devinfo, insn, allocate); + elk_inst_set_sfid(devinfo, insn, ELK_SFID_URB); + elk_inst_set_eot(devinfo, insn, end_of_thread); + elk_inst_set_urb_opcode(devinfo, insn, 1); /* FF_SYNC */ + elk_inst_set_urb_allocate(devinfo, insn, allocate); /* The following fields are not used by FF_SYNC: */ - brw_inst_set_urb_global_offset(devinfo, insn, 0); - brw_inst_set_urb_swizzle_control(devinfo, insn, 0); - brw_inst_set_urb_used(devinfo, insn, 0); - brw_inst_set_urb_complete(devinfo, insn, 0); + elk_inst_set_urb_global_offset(devinfo, insn, 0); + elk_inst_set_urb_swizzle_control(devinfo, insn, 0); + elk_inst_set_urb_used(devinfo, insn, 0); + elk_inst_set_urb_complete(devinfo, insn, 0); } -static void brw_set_urb_message( struct brw_codegen *p, - brw_inst *insn, - enum brw_urb_write_flags flags, +static void elk_set_urb_message( struct elk_codegen *p, + elk_inst *insn, + enum elk_urb_write_flags flags, unsigned msg_length, unsigned response_length, unsigned offset, @@ -546,42 +546,42 @@ static void brw_set_urb_message( struct brw_codegen *p, { const struct intel_device_info *devinfo = p->devinfo; - assert(devinfo->ver < 7 || swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE); - assert(devinfo->ver < 7 || !(flags & BRW_URB_WRITE_ALLOCATE)); - assert(devinfo->ver >= 7 || !(flags & BRW_URB_WRITE_PER_SLOT_OFFSET)); + assert(devinfo->ver < 7 || swizzle_control != ELK_URB_SWIZZLE_TRANSPOSE); + assert(devinfo->ver < 7 || !(flags & ELK_URB_WRITE_ALLOCATE)); + assert(devinfo->ver >= 7 || !(flags & ELK_URB_WRITE_PER_SLOT_OFFSET)); - brw_set_desc(p, insn, brw_message_desc( + elk_set_desc(p, insn, elk_message_desc( devinfo, msg_length, response_length, true)); - brw_inst_set_sfid(devinfo, insn, BRW_SFID_URB); - brw_inst_set_eot(devinfo, insn, !!(flags & BRW_URB_WRITE_EOT)); + elk_inst_set_sfid(devinfo, insn, ELK_SFID_URB); + elk_inst_set_eot(devinfo, insn, !!(flags & ELK_URB_WRITE_EOT)); - if (flags & BRW_URB_WRITE_OWORD) { + if (flags & ELK_URB_WRITE_OWORD) { assert(msg_length == 2); /* header + one OWORD of data */ - brw_inst_set_urb_opcode(devinfo, insn, BRW_URB_OPCODE_WRITE_OWORD); + elk_inst_set_urb_opcode(devinfo, insn, ELK_URB_OPCODE_WRITE_OWORD); } else { - brw_inst_set_urb_opcode(devinfo, insn, BRW_URB_OPCODE_WRITE_HWORD); + elk_inst_set_urb_opcode(devinfo, insn, ELK_URB_OPCODE_WRITE_HWORD); } - brw_inst_set_urb_global_offset(devinfo, insn, offset); - brw_inst_set_urb_swizzle_control(devinfo, insn, swizzle_control); + elk_inst_set_urb_global_offset(devinfo, insn, offset); + elk_inst_set_urb_swizzle_control(devinfo, insn, swizzle_control); if (devinfo->ver < 8) { - brw_inst_set_urb_complete(devinfo, insn, !!(flags & BRW_URB_WRITE_COMPLETE)); + elk_inst_set_urb_complete(devinfo, insn, !!(flags & ELK_URB_WRITE_COMPLETE)); } if (devinfo->ver < 7) { - brw_inst_set_urb_allocate(devinfo, insn, !!(flags & BRW_URB_WRITE_ALLOCATE)); - brw_inst_set_urb_used(devinfo, insn, !(flags & BRW_URB_WRITE_UNUSED)); + elk_inst_set_urb_allocate(devinfo, insn, !!(flags & ELK_URB_WRITE_ALLOCATE)); + elk_inst_set_urb_used(devinfo, insn, !(flags & ELK_URB_WRITE_UNUSED)); } else { - brw_inst_set_urb_per_slot_offset(devinfo, insn, - !!(flags & BRW_URB_WRITE_PER_SLOT_OFFSET)); + elk_inst_set_urb_per_slot_offset(devinfo, insn, + !!(flags & ELK_URB_WRITE_PER_SLOT_OFFSET)); } } static void -gfx7_set_dp_scratch_message(struct brw_codegen *p, - brw_inst *inst, +gfx7_set_dp_scratch_message(struct elk_codegen *p, + elk_inst *inst, bool write, bool dword, bool invalidate_after_read, @@ -597,63 +597,63 @@ gfx7_set_dp_scratch_message(struct brw_codegen *p, const unsigned block_size = (devinfo->ver >= 8 ? util_logbase2(num_regs) : num_regs - 1); - brw_set_desc(p, inst, brw_message_desc( + elk_set_desc(p, inst, elk_message_desc( devinfo, mlen, rlen, header_present)); - brw_inst_set_sfid(devinfo, inst, GFX7_SFID_DATAPORT_DATA_CACHE); - brw_inst_set_dp_category(devinfo, inst, 1); /* Scratch Block Read/Write msgs */ - brw_inst_set_scratch_read_write(devinfo, inst, write); - brw_inst_set_scratch_type(devinfo, inst, dword); - brw_inst_set_scratch_invalidate_after_read(devinfo, inst, invalidate_after_read); - brw_inst_set_scratch_block_size(devinfo, inst, block_size); - brw_inst_set_scratch_addr_offset(devinfo, inst, addr_offset); + elk_inst_set_sfid(devinfo, inst, GFX7_SFID_DATAPORT_DATA_CACHE); + elk_inst_set_dp_category(devinfo, inst, 1); /* Scratch Block Read/Write msgs */ + elk_inst_set_scratch_read_write(devinfo, inst, write); + elk_inst_set_scratch_type(devinfo, inst, dword); + elk_inst_set_scratch_invalidate_after_read(devinfo, inst, invalidate_after_read); + elk_inst_set_scratch_block_size(devinfo, inst, block_size); + elk_inst_set_scratch_addr_offset(devinfo, inst, addr_offset); } static void -brw_inst_set_state(const struct brw_isa_info *isa, - brw_inst *insn, - const struct brw_insn_state *state) +elk_inst_set_state(const struct elk_isa_info *isa, + elk_inst *insn, + const struct elk_insn_state *state) { const struct intel_device_info *devinfo = isa->devinfo; - brw_inst_set_exec_size(devinfo, insn, state->exec_size); - brw_inst_set_group(devinfo, insn, state->group); - brw_inst_set_compression(devinfo, insn, state->compressed); - brw_inst_set_access_mode(devinfo, insn, state->access_mode); - brw_inst_set_mask_control(devinfo, insn, state->mask_control); + elk_inst_set_exec_size(devinfo, insn, state->exec_size); + elk_inst_set_group(devinfo, insn, state->group); + elk_inst_set_compression(devinfo, insn, state->compressed); + elk_inst_set_access_mode(devinfo, insn, state->access_mode); + elk_inst_set_mask_control(devinfo, insn, state->mask_control); if (devinfo->ver >= 12) - brw_inst_set_swsb(devinfo, insn, tgl_swsb_encode(devinfo, state->swsb)); - brw_inst_set_saturate(devinfo, insn, state->saturate); - brw_inst_set_pred_control(devinfo, insn, state->predicate); - brw_inst_set_pred_inv(devinfo, insn, state->pred_inv); + elk_inst_set_swsb(devinfo, insn, tgl_swsb_encode(devinfo, state->swsb)); + elk_inst_set_saturate(devinfo, insn, state->saturate); + elk_inst_set_pred_control(devinfo, insn, state->predicate); + elk_inst_set_pred_inv(devinfo, insn, state->pred_inv); - if (is_3src(isa, brw_inst_opcode(isa, insn)) && - state->access_mode == BRW_ALIGN_16) { - brw_inst_set_3src_a16_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2); + if (elk_is_3src(isa, elk_inst_opcode(isa, insn)) && + state->access_mode == ELK_ALIGN_16) { + elk_inst_set_3src_a16_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2); if (devinfo->ver >= 7) - brw_inst_set_3src_a16_flag_reg_nr(devinfo, insn, state->flag_subreg / 2); + elk_inst_set_3src_a16_flag_reg_nr(devinfo, insn, state->flag_subreg / 2); } else { - brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2); + elk_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2); if (devinfo->ver >= 7) - brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2); + elk_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2); } if (devinfo->ver >= 6 && devinfo->ver < 20) - brw_inst_set_acc_wr_control(devinfo, insn, state->acc_wr_control); + elk_inst_set_acc_wr_control(devinfo, insn, state->acc_wr_control); } -static brw_inst * -brw_append_insns(struct brw_codegen *p, unsigned nr_insn, unsigned alignment) +static elk_inst * +elk_append_insns(struct elk_codegen *p, unsigned nr_insn, unsigned alignment) { - assert(util_is_power_of_two_or_zero(sizeof(brw_inst))); + assert(util_is_power_of_two_or_zero(sizeof(elk_inst))); assert(util_is_power_of_two_or_zero(alignment)); - const unsigned align_insn = MAX2(alignment / sizeof(brw_inst), 1); + const unsigned align_insn = MAX2(alignment / sizeof(elk_inst), 1); const unsigned start_insn = ALIGN(p->nr_insn, align_insn); const unsigned new_nr_insn = start_insn + nr_insn; if (p->store_size < new_nr_insn) { - p->store_size = util_next_power_of_two(new_nr_insn * sizeof(brw_inst)); - p->store = reralloc(p->mem_ctx, p->store, brw_inst, p->store_size); + p->store_size = util_next_power_of_two(new_nr_insn * sizeof(elk_inst)); + p->store = reralloc(p->mem_ctx, p->store, elk_inst, p->store_size); } /* Memset any padding due to alignment to 0. We don't want to be hashing @@ -661,64 +661,64 @@ brw_append_insns(struct brw_codegen *p, unsigned nr_insn, unsigned alignment) */ if (p->nr_insn < start_insn) { memset(&p->store[p->nr_insn], 0, - (start_insn - p->nr_insn) * sizeof(brw_inst)); + (start_insn - p->nr_insn) * sizeof(elk_inst)); } - assert(p->next_insn_offset == p->nr_insn * sizeof(brw_inst)); + assert(p->next_insn_offset == p->nr_insn * sizeof(elk_inst)); p->nr_insn = new_nr_insn; - p->next_insn_offset = new_nr_insn * sizeof(brw_inst); + p->next_insn_offset = new_nr_insn * sizeof(elk_inst); return &p->store[start_insn]; } void -brw_realign(struct brw_codegen *p, unsigned alignment) +elk_realign(struct elk_codegen *p, unsigned alignment) { - brw_append_insns(p, 0, alignment); + elk_append_insns(p, 0, alignment); } int -brw_append_data(struct brw_codegen *p, void *data, +elk_append_data(struct elk_codegen *p, void *data, unsigned size, unsigned alignment) { - unsigned nr_insn = DIV_ROUND_UP(size, sizeof(brw_inst)); - void *dst = brw_append_insns(p, nr_insn, alignment); + unsigned nr_insn = DIV_ROUND_UP(size, sizeof(elk_inst)); + void *dst = elk_append_insns(p, nr_insn, alignment); memcpy(dst, data, size); /* If it's not a whole number of instructions, memset the end */ - if (size < nr_insn * sizeof(brw_inst)) - memset(dst + size, 0, nr_insn * sizeof(brw_inst) - size); + if (size < nr_insn * sizeof(elk_inst)) + memset(dst + size, 0, nr_insn * sizeof(elk_inst) - size); return dst - (void *)p->store; } -#define next_insn brw_next_insn -brw_inst * -brw_next_insn(struct brw_codegen *p, unsigned opcode) +#define next_insn elk_next_insn +elk_inst * +elk_next_insn(struct elk_codegen *p, unsigned opcode) { - brw_inst *insn = brw_append_insns(p, 1, sizeof(brw_inst)); + elk_inst *insn = elk_append_insns(p, 1, sizeof(elk_inst)); memset(insn, 0, sizeof(*insn)); - brw_inst_set_opcode(p->isa, insn, opcode); + elk_inst_set_opcode(p->isa, insn, opcode); /* Apply the default instruction state */ - brw_inst_set_state(p->isa, insn, p->current); + elk_inst_set_state(p->isa, insn, p->current); return insn; } void -brw_add_reloc(struct brw_codegen *p, uint32_t id, - enum brw_shader_reloc_type type, +elk_add_reloc(struct elk_codegen *p, uint32_t id, + enum elk_shader_reloc_type type, uint32_t offset, uint32_t delta) { if (p->num_relocs + 1 > p->reloc_array_size) { p->reloc_array_size = MAX2(16, p->reloc_array_size * 2); p->relocs = reralloc(p->mem_ctx, p->relocs, - struct brw_shader_reloc, p->reloc_array_size); + struct elk_shader_reloc, p->reloc_array_size); } - p->relocs[p->num_relocs++] = (struct brw_shader_reloc) { + p->relocs[p->num_relocs++] = (struct elk_shader_reloc) { .id = id, .type = type, .offset = offset, @@ -726,33 +726,33 @@ brw_add_reloc(struct brw_codegen *p, uint32_t id, }; } -static brw_inst * -brw_alu1(struct brw_codegen *p, unsigned opcode, - struct brw_reg dest, struct brw_reg src) +static elk_inst * +elk_alu1(struct elk_codegen *p, unsigned opcode, + struct elk_reg dest, struct elk_reg src) { - brw_inst *insn = next_insn(p, opcode); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src); + elk_inst *insn = next_insn(p, opcode); + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src); return insn; } -static brw_inst * -brw_alu2(struct brw_codegen *p, unsigned opcode, - struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) +static elk_inst * +elk_alu2(struct elk_codegen *p, unsigned opcode, + struct elk_reg dest, struct elk_reg src0, struct elk_reg src1) { /* 64-bit immediates are only supported on 1-src instructions */ - assert(src0.file != BRW_IMMEDIATE_VALUE || type_sz(src0.type) <= 4); - assert(src1.file != BRW_IMMEDIATE_VALUE || type_sz(src1.type) <= 4); + assert(src0.file != ELK_IMMEDIATE_VALUE || type_sz(src0.type) <= 4); + assert(src1.file != ELK_IMMEDIATE_VALUE || type_sz(src1.type) <= 4); - brw_inst *insn = next_insn(p, opcode); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, src1); + elk_inst *insn = next_insn(p, opcode); + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_src1(p, insn, src1); return insn; } static int -get_3src_subreg_nr(struct brw_reg reg) +get_3src_subreg_nr(struct elk_reg reg) { /* Normally, SubRegNum is in bytes (0..31). However, 3-src instructions * use 32-bit units (components 0..7). Since they only support F/D/UD @@ -763,22 +763,22 @@ get_3src_subreg_nr(struct brw_reg reg) static enum gfx10_align1_3src_vertical_stride to_3src_align1_vstride(const struct intel_device_info *devinfo, - enum brw_vertical_stride vstride) + enum elk_vertical_stride vstride) { switch (vstride) { - case BRW_VERTICAL_STRIDE_0: - return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0; - case BRW_VERTICAL_STRIDE_1: + case ELK_VERTICAL_STRIDE_0: + return ELK_ALIGN1_3SRC_VERTICAL_STRIDE_0; + case ELK_VERTICAL_STRIDE_1: assert(devinfo->ver >= 12); - return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1; - case BRW_VERTICAL_STRIDE_2: + return ELK_ALIGN1_3SRC_VERTICAL_STRIDE_1; + case ELK_VERTICAL_STRIDE_2: assert(devinfo->ver < 12); - return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2; - case BRW_VERTICAL_STRIDE_4: - return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4; - case BRW_VERTICAL_STRIDE_8: - case BRW_VERTICAL_STRIDE_16: - return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8; + return ELK_ALIGN1_3SRC_VERTICAL_STRIDE_2; + case ELK_VERTICAL_STRIDE_4: + return ELK_ALIGN1_3SRC_VERTICAL_STRIDE_4; + case ELK_VERTICAL_STRIDE_8: + case ELK_VERTICAL_STRIDE_16: + return ELK_ALIGN1_3SRC_VERTICAL_STRIDE_8; default: unreachable("invalid vstride"); } @@ -786,204 +786,204 @@ to_3src_align1_vstride(const struct intel_device_info *devinfo, static enum gfx10_align1_3src_src_horizontal_stride -to_3src_align1_hstride(enum brw_horizontal_stride hstride) +to_3src_align1_hstride(enum elk_horizontal_stride hstride) { switch (hstride) { - case BRW_HORIZONTAL_STRIDE_0: - return BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0; - case BRW_HORIZONTAL_STRIDE_1: - return BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1; - case BRW_HORIZONTAL_STRIDE_2: - return BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2; - case BRW_HORIZONTAL_STRIDE_4: - return BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4; + case ELK_HORIZONTAL_STRIDE_0: + return ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0; + case ELK_HORIZONTAL_STRIDE_1: + return ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1; + case ELK_HORIZONTAL_STRIDE_2: + return ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2; + case ELK_HORIZONTAL_STRIDE_4: + return ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4; default: unreachable("invalid hstride"); } } -static brw_inst * -brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, - struct brw_reg src0, struct brw_reg src1, struct brw_reg src2) +static elk_inst * +elk_alu3(struct elk_codegen *p, unsigned opcode, struct elk_reg dest, + struct elk_reg src0, struct elk_reg src1, struct elk_reg src2) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *inst = next_insn(p, opcode); + elk_inst *inst = next_insn(p, opcode); gfx7_convert_mrf_to_grf(p, &dest); assert(dest.nr < XE2_MAX_GRF); if (devinfo->ver >= 10) - assert(!(src0.file == BRW_IMMEDIATE_VALUE && - src2.file == BRW_IMMEDIATE_VALUE)); + assert(!(src0.file == ELK_IMMEDIATE_VALUE && + src2.file == ELK_IMMEDIATE_VALUE)); - assert(src0.file == BRW_IMMEDIATE_VALUE || src0.nr < XE2_MAX_GRF); - assert(src1.file != BRW_IMMEDIATE_VALUE && src1.nr < XE2_MAX_GRF); - assert(src2.file == BRW_IMMEDIATE_VALUE || src2.nr < XE2_MAX_GRF); - assert(dest.address_mode == BRW_ADDRESS_DIRECT); - assert(src0.address_mode == BRW_ADDRESS_DIRECT); - assert(src1.address_mode == BRW_ADDRESS_DIRECT); - assert(src2.address_mode == BRW_ADDRESS_DIRECT); + assert(src0.file == ELK_IMMEDIATE_VALUE || src0.nr < XE2_MAX_GRF); + assert(src1.file != ELK_IMMEDIATE_VALUE && src1.nr < XE2_MAX_GRF); + assert(src2.file == ELK_IMMEDIATE_VALUE || src2.nr < XE2_MAX_GRF); + assert(dest.address_mode == ELK_ADDRESS_DIRECT); + assert(src0.address_mode == ELK_ADDRESS_DIRECT); + assert(src1.address_mode == ELK_ADDRESS_DIRECT); + assert(src2.address_mode == ELK_ADDRESS_DIRECT); - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - assert(dest.file == BRW_GENERAL_REGISTER_FILE || - (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && - dest.nr == BRW_ARF_ACCUMULATOR)); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + assert(dest.file == ELK_GENERAL_REGISTER_FILE || + (dest.file == ELK_ARCHITECTURE_REGISTER_FILE && + dest.nr == ELK_ARF_ACCUMULATOR)); if (devinfo->ver >= 12) { - brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, dest.file); - brw_inst_set_3src_dst_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); + elk_inst_set_3src_a1_dst_reg_file(devinfo, inst, dest.file); + elk_inst_set_3src_dst_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); } else { - if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE) { - brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, - BRW_ALIGN1_3SRC_ACCUMULATOR); - brw_inst_set_3src_dst_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR); + if (dest.file == ELK_ARCHITECTURE_REGISTER_FILE) { + elk_inst_set_3src_a1_dst_reg_file(devinfo, inst, + ELK_ALIGN1_3SRC_ACCUMULATOR); + elk_inst_set_3src_dst_reg_nr(devinfo, inst, ELK_ARF_ACCUMULATOR); } else { - brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, - BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE); - brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr); + elk_inst_set_3src_a1_dst_reg_file(devinfo, inst, + ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE); + elk_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr); } } - brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest) / 8); + elk_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest) / 8); - brw_inst_set_3src_a1_dst_hstride(devinfo, inst, BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1); + elk_inst_set_3src_a1_dst_hstride(devinfo, inst, ELK_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1); - if (brw_reg_type_is_floating_point(dest.type)) { - brw_inst_set_3src_a1_exec_type(devinfo, inst, - BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); + if (elk_reg_type_is_floating_point(dest.type)) { + elk_inst_set_3src_a1_exec_type(devinfo, inst, + ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT); } else { - brw_inst_set_3src_a1_exec_type(devinfo, inst, - BRW_ALIGN1_3SRC_EXEC_TYPE_INT); + elk_inst_set_3src_a1_exec_type(devinfo, inst, + ELK_ALIGN1_3SRC_EXEC_TYPE_INT); } - brw_inst_set_3src_a1_dst_type(devinfo, inst, dest.type); - brw_inst_set_3src_a1_src0_type(devinfo, inst, src0.type); - brw_inst_set_3src_a1_src1_type(devinfo, inst, src1.type); - brw_inst_set_3src_a1_src2_type(devinfo, inst, src2.type); + elk_inst_set_3src_a1_dst_type(devinfo, inst, dest.type); + elk_inst_set_3src_a1_src0_type(devinfo, inst, src0.type); + elk_inst_set_3src_a1_src1_type(devinfo, inst, src1.type); + elk_inst_set_3src_a1_src2_type(devinfo, inst, src2.type); - if (src0.file == BRW_IMMEDIATE_VALUE) { - brw_inst_set_3src_a1_src0_imm(devinfo, inst, src0.ud); + if (src0.file == ELK_IMMEDIATE_VALUE) { + elk_inst_set_3src_a1_src0_imm(devinfo, inst, src0.ud); } else { - brw_inst_set_3src_a1_src0_vstride( + elk_inst_set_3src_a1_src0_vstride( devinfo, inst, to_3src_align1_vstride(devinfo, src0.vstride)); - brw_inst_set_3src_a1_src0_hstride(devinfo, inst, + elk_inst_set_3src_a1_src0_hstride(devinfo, inst, to_3src_align1_hstride(src0.hstride)); - brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, phys_subnr(devinfo, src0)); - if (src0.type == BRW_REGISTER_TYPE_NF) { - brw_inst_set_3src_src0_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR); + elk_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, phys_subnr(devinfo, src0)); + if (src0.type == ELK_REGISTER_TYPE_NF) { + elk_inst_set_3src_src0_reg_nr(devinfo, inst, ELK_ARF_ACCUMULATOR); } else { - brw_inst_set_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0)); + elk_inst_set_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0)); } - brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs); - brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate); + elk_inst_set_3src_src0_abs(devinfo, inst, src0.abs); + elk_inst_set_3src_src0_negate(devinfo, inst, src0.negate); } - brw_inst_set_3src_a1_src1_vstride( + elk_inst_set_3src_a1_src1_vstride( devinfo, inst, to_3src_align1_vstride(devinfo, src1.vstride)); - brw_inst_set_3src_a1_src1_hstride(devinfo, inst, + elk_inst_set_3src_a1_src1_hstride(devinfo, inst, to_3src_align1_hstride(src1.hstride)); - brw_inst_set_3src_a1_src1_subreg_nr(devinfo, inst, phys_subnr(devinfo, src1)); - if (src1.file == BRW_ARCHITECTURE_REGISTER_FILE) { - brw_inst_set_3src_src1_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR); + elk_inst_set_3src_a1_src1_subreg_nr(devinfo, inst, phys_subnr(devinfo, src1)); + if (src1.file == ELK_ARCHITECTURE_REGISTER_FILE) { + elk_inst_set_3src_src1_reg_nr(devinfo, inst, ELK_ARF_ACCUMULATOR); } else { - brw_inst_set_3src_src1_reg_nr(devinfo, inst, phys_nr(devinfo, src1)); + elk_inst_set_3src_src1_reg_nr(devinfo, inst, phys_nr(devinfo, src1)); } - brw_inst_set_3src_src1_abs(devinfo, inst, src1.abs); - brw_inst_set_3src_src1_negate(devinfo, inst, src1.negate); + elk_inst_set_3src_src1_abs(devinfo, inst, src1.abs); + elk_inst_set_3src_src1_negate(devinfo, inst, src1.negate); - if (src2.file == BRW_IMMEDIATE_VALUE) { - brw_inst_set_3src_a1_src2_imm(devinfo, inst, src2.ud); + if (src2.file == ELK_IMMEDIATE_VALUE) { + elk_inst_set_3src_a1_src2_imm(devinfo, inst, src2.ud); } else { - brw_inst_set_3src_a1_src2_hstride(devinfo, inst, + elk_inst_set_3src_a1_src2_hstride(devinfo, inst, to_3src_align1_hstride(src2.hstride)); /* no vstride on src2 */ - brw_inst_set_3src_a1_src2_subreg_nr(devinfo, inst, phys_subnr(devinfo, src2)); - brw_inst_set_3src_src2_reg_nr(devinfo, inst, phys_nr(devinfo, src2)); - brw_inst_set_3src_src2_abs(devinfo, inst, src2.abs); - brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate); + elk_inst_set_3src_a1_src2_subreg_nr(devinfo, inst, phys_subnr(devinfo, src2)); + elk_inst_set_3src_src2_reg_nr(devinfo, inst, phys_nr(devinfo, src2)); + elk_inst_set_3src_src2_abs(devinfo, inst, src2.abs); + elk_inst_set_3src_src2_negate(devinfo, inst, src2.negate); } - assert(src0.file == BRW_GENERAL_REGISTER_FILE || - src0.file == BRW_IMMEDIATE_VALUE || - (src0.file == BRW_ARCHITECTURE_REGISTER_FILE && - src0.type == BRW_REGISTER_TYPE_NF)); - assert(src1.file == BRW_GENERAL_REGISTER_FILE || - (src1.file == BRW_ARCHITECTURE_REGISTER_FILE && - src1.nr == BRW_ARF_ACCUMULATOR)); - assert(src2.file == BRW_GENERAL_REGISTER_FILE || - src2.file == BRW_IMMEDIATE_VALUE); + assert(src0.file == ELK_GENERAL_REGISTER_FILE || + src0.file == ELK_IMMEDIATE_VALUE || + (src0.file == ELK_ARCHITECTURE_REGISTER_FILE && + src0.type == ELK_REGISTER_TYPE_NF)); + assert(src1.file == ELK_GENERAL_REGISTER_FILE || + (src1.file == ELK_ARCHITECTURE_REGISTER_FILE && + src1.nr == ELK_ARF_ACCUMULATOR)); + assert(src2.file == ELK_GENERAL_REGISTER_FILE || + src2.file == ELK_IMMEDIATE_VALUE); if (devinfo->ver >= 12) { - if (src0.file == BRW_IMMEDIATE_VALUE) { - brw_inst_set_3src_a1_src0_is_imm(devinfo, inst, 1); + if (src0.file == ELK_IMMEDIATE_VALUE) { + elk_inst_set_3src_a1_src0_is_imm(devinfo, inst, 1); } else { - brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file); + elk_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file); } - brw_inst_set_3src_a1_src1_reg_file(devinfo, inst, src1.file); + elk_inst_set_3src_a1_src1_reg_file(devinfo, inst, src1.file); - if (src2.file == BRW_IMMEDIATE_VALUE) { - brw_inst_set_3src_a1_src2_is_imm(devinfo, inst, 1); + if (src2.file == ELK_IMMEDIATE_VALUE) { + elk_inst_set_3src_a1_src2_is_imm(devinfo, inst, 1); } else { - brw_inst_set_3src_a1_src2_reg_file(devinfo, inst, src2.file); + elk_inst_set_3src_a1_src2_reg_file(devinfo, inst, src2.file); } } else { - brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, - src0.file == BRW_GENERAL_REGISTER_FILE ? - BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE : - BRW_ALIGN1_3SRC_IMMEDIATE_VALUE); - brw_inst_set_3src_a1_src1_reg_file(devinfo, inst, - src1.file == BRW_GENERAL_REGISTER_FILE ? - BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE : - BRW_ALIGN1_3SRC_ACCUMULATOR); - brw_inst_set_3src_a1_src2_reg_file(devinfo, inst, - src2.file == BRW_GENERAL_REGISTER_FILE ? - BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE : - BRW_ALIGN1_3SRC_IMMEDIATE_VALUE); + elk_inst_set_3src_a1_src0_reg_file(devinfo, inst, + src0.file == ELK_GENERAL_REGISTER_FILE ? + ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE : + ELK_ALIGN1_3SRC_IMMEDIATE_VALUE); + elk_inst_set_3src_a1_src1_reg_file(devinfo, inst, + src1.file == ELK_GENERAL_REGISTER_FILE ? + ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE : + ELK_ALIGN1_3SRC_ACCUMULATOR); + elk_inst_set_3src_a1_src2_reg_file(devinfo, inst, + src2.file == ELK_GENERAL_REGISTER_FILE ? + ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE : + ELK_ALIGN1_3SRC_IMMEDIATE_VALUE); } } else { - assert(dest.file == BRW_GENERAL_REGISTER_FILE || - dest.file == BRW_MESSAGE_REGISTER_FILE); - assert(dest.type == BRW_REGISTER_TYPE_F || - dest.type == BRW_REGISTER_TYPE_DF || - dest.type == BRW_REGISTER_TYPE_D || - dest.type == BRW_REGISTER_TYPE_UD || - (dest.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 8)); + assert(dest.file == ELK_GENERAL_REGISTER_FILE || + dest.file == ELK_MESSAGE_REGISTER_FILE); + assert(dest.type == ELK_REGISTER_TYPE_F || + dest.type == ELK_REGISTER_TYPE_DF || + dest.type == ELK_REGISTER_TYPE_D || + dest.type == ELK_REGISTER_TYPE_UD || + (dest.type == ELK_REGISTER_TYPE_HF && devinfo->ver >= 8)); if (devinfo->ver == 6) { - brw_inst_set_3src_a16_dst_reg_file(devinfo, inst, - dest.file == BRW_MESSAGE_REGISTER_FILE); + elk_inst_set_3src_a16_dst_reg_file(devinfo, inst, + dest.file == ELK_MESSAGE_REGISTER_FILE); } - brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr); - brw_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 4); - brw_inst_set_3src_a16_dst_writemask(devinfo, inst, dest.writemask); + elk_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr); + elk_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 4); + elk_inst_set_3src_a16_dst_writemask(devinfo, inst, dest.writemask); - assert(src0.file == BRW_GENERAL_REGISTER_FILE); - brw_inst_set_3src_a16_src0_swizzle(devinfo, inst, src0.swizzle); - brw_inst_set_3src_a16_src0_subreg_nr(devinfo, inst, get_3src_subreg_nr(src0)); - brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr); - brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs); - brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate); - brw_inst_set_3src_a16_src0_rep_ctrl(devinfo, inst, - src0.vstride == BRW_VERTICAL_STRIDE_0); + assert(src0.file == ELK_GENERAL_REGISTER_FILE); + elk_inst_set_3src_a16_src0_swizzle(devinfo, inst, src0.swizzle); + elk_inst_set_3src_a16_src0_subreg_nr(devinfo, inst, get_3src_subreg_nr(src0)); + elk_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr); + elk_inst_set_3src_src0_abs(devinfo, inst, src0.abs); + elk_inst_set_3src_src0_negate(devinfo, inst, src0.negate); + elk_inst_set_3src_a16_src0_rep_ctrl(devinfo, inst, + src0.vstride == ELK_VERTICAL_STRIDE_0); - assert(src1.file == BRW_GENERAL_REGISTER_FILE); - brw_inst_set_3src_a16_src1_swizzle(devinfo, inst, src1.swizzle); - brw_inst_set_3src_a16_src1_subreg_nr(devinfo, inst, get_3src_subreg_nr(src1)); - brw_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr); - brw_inst_set_3src_src1_abs(devinfo, inst, src1.abs); - brw_inst_set_3src_src1_negate(devinfo, inst, src1.negate); - brw_inst_set_3src_a16_src1_rep_ctrl(devinfo, inst, - src1.vstride == BRW_VERTICAL_STRIDE_0); + assert(src1.file == ELK_GENERAL_REGISTER_FILE); + elk_inst_set_3src_a16_src1_swizzle(devinfo, inst, src1.swizzle); + elk_inst_set_3src_a16_src1_subreg_nr(devinfo, inst, get_3src_subreg_nr(src1)); + elk_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr); + elk_inst_set_3src_src1_abs(devinfo, inst, src1.abs); + elk_inst_set_3src_src1_negate(devinfo, inst, src1.negate); + elk_inst_set_3src_a16_src1_rep_ctrl(devinfo, inst, + src1.vstride == ELK_VERTICAL_STRIDE_0); - assert(src2.file == BRW_GENERAL_REGISTER_FILE); - brw_inst_set_3src_a16_src2_swizzle(devinfo, inst, src2.swizzle); - brw_inst_set_3src_a16_src2_subreg_nr(devinfo, inst, get_3src_subreg_nr(src2)); - brw_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr); - brw_inst_set_3src_src2_abs(devinfo, inst, src2.abs); - brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate); - brw_inst_set_3src_a16_src2_rep_ctrl(devinfo, inst, - src2.vstride == BRW_VERTICAL_STRIDE_0); + assert(src2.file == ELK_GENERAL_REGISTER_FILE); + elk_inst_set_3src_a16_src2_swizzle(devinfo, inst, src2.swizzle); + elk_inst_set_3src_a16_src2_subreg_nr(devinfo, inst, get_3src_subreg_nr(src2)); + elk_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr); + elk_inst_set_3src_src2_abs(devinfo, inst, src2.abs); + elk_inst_set_3src_src2_negate(devinfo, inst, src2.negate); + elk_inst_set_3src_a16_src2_rep_ctrl(devinfo, inst, + src2.vstride == ELK_VERTICAL_STRIDE_0); if (devinfo->ver >= 7) { /* Set both the source and destination types based on dest.type, @@ -992,8 +992,8 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, * may send us mixed D and UD types and want us to ignore that and use * the destination type. */ - brw_inst_set_3src_a16_src_type(devinfo, inst, dest.type); - brw_inst_set_3src_a16_dst_type(devinfo, inst, dest.type); + elk_inst_set_3src_a16_src_type(devinfo, inst, dest.type); + elk_inst_set_3src_a16_dst_type(devinfo, inst, dest.type); /* From the Bspec, 3D Media GPGPU, Instruction fields, srcType: * @@ -1005,68 +1005,68 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, * 0b = :f. Single precision Float (32-bit). * 1b = :hf. Half precision Float (16-bit)." */ - if (src1.type == BRW_REGISTER_TYPE_HF) - brw_inst_set_3src_a16_src1_type(devinfo, inst, 1); + if (src1.type == ELK_REGISTER_TYPE_HF) + elk_inst_set_3src_a16_src1_type(devinfo, inst, 1); - if (src2.type == BRW_REGISTER_TYPE_HF) - brw_inst_set_3src_a16_src2_type(devinfo, inst, 1); + if (src2.type == ELK_REGISTER_TYPE_HF) + elk_inst_set_3src_a16_src2_type(devinfo, inst, 1); } } return inst; } -static brw_inst * -brw_dpas_three_src(struct brw_codegen *p, enum gfx12_systolic_depth opcode, - unsigned sdepth, unsigned rcount, struct brw_reg dest, - struct brw_reg src0, struct brw_reg src1, struct brw_reg src2) +static elk_inst * +elk_dpas_three_src(struct elk_codegen *p, enum elk_gfx12_systolic_depth opcode, + unsigned sdepth, unsigned rcount, struct elk_reg dest, + struct elk_reg src0, struct elk_reg src1, struct elk_reg src2) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *inst = next_insn(p, opcode); + elk_inst *inst = next_insn(p, opcode); - assert(dest.file == BRW_GENERAL_REGISTER_FILE); - brw_inst_set_dpas_3src_dst_reg_file(devinfo, inst, - BRW_GENERAL_REGISTER_FILE); - brw_inst_set_dpas_3src_dst_reg_nr(devinfo, inst, dest.nr); - brw_inst_set_dpas_3src_dst_subreg_nr(devinfo, inst, dest.subnr); + assert(dest.file == ELK_GENERAL_REGISTER_FILE); + elk_inst_set_dpas_3src_dst_reg_file(devinfo, inst, + ELK_GENERAL_REGISTER_FILE); + elk_inst_set_dpas_3src_dst_reg_nr(devinfo, inst, dest.nr); + elk_inst_set_dpas_3src_dst_subreg_nr(devinfo, inst, dest.subnr); - if (brw_reg_type_is_floating_point(dest.type)) { - brw_inst_set_dpas_3src_exec_type(devinfo, inst, - BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); + if (elk_reg_type_is_floating_point(dest.type)) { + elk_inst_set_dpas_3src_exec_type(devinfo, inst, + ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT); } else { - brw_inst_set_dpas_3src_exec_type(devinfo, inst, - BRW_ALIGN1_3SRC_EXEC_TYPE_INT); + elk_inst_set_dpas_3src_exec_type(devinfo, inst, + ELK_ALIGN1_3SRC_EXEC_TYPE_INT); } - brw_inst_set_dpas_3src_sdepth(devinfo, inst, sdepth); - brw_inst_set_dpas_3src_rcount(devinfo, inst, rcount - 1); + elk_inst_set_dpas_3src_sdepth(devinfo, inst, sdepth); + elk_inst_set_dpas_3src_rcount(devinfo, inst, rcount - 1); - brw_inst_set_dpas_3src_dst_type(devinfo, inst, dest.type); - brw_inst_set_dpas_3src_src0_type(devinfo, inst, src0.type); - brw_inst_set_dpas_3src_src1_type(devinfo, inst, src1.type); - brw_inst_set_dpas_3src_src2_type(devinfo, inst, src2.type); + elk_inst_set_dpas_3src_dst_type(devinfo, inst, dest.type); + elk_inst_set_dpas_3src_src0_type(devinfo, inst, src0.type); + elk_inst_set_dpas_3src_src1_type(devinfo, inst, src1.type); + elk_inst_set_dpas_3src_src2_type(devinfo, inst, src2.type); - assert(src0.file == BRW_GENERAL_REGISTER_FILE || - (src0.file == BRW_ARCHITECTURE_REGISTER_FILE && - src0.nr == BRW_ARF_NULL)); + assert(src0.file == ELK_GENERAL_REGISTER_FILE || + (src0.file == ELK_ARCHITECTURE_REGISTER_FILE && + src0.nr == ELK_ARF_NULL)); - brw_inst_set_dpas_3src_src0_reg_file(devinfo, inst, src0.file); - brw_inst_set_dpas_3src_src0_reg_nr(devinfo, inst, src0.nr); - brw_inst_set_dpas_3src_src0_subreg_nr(devinfo, inst, src0.subnr); + elk_inst_set_dpas_3src_src0_reg_file(devinfo, inst, src0.file); + elk_inst_set_dpas_3src_src0_reg_nr(devinfo, inst, src0.nr); + elk_inst_set_dpas_3src_src0_subreg_nr(devinfo, inst, src0.subnr); - assert(src1.file == BRW_GENERAL_REGISTER_FILE); + assert(src1.file == ELK_GENERAL_REGISTER_FILE); - brw_inst_set_dpas_3src_src1_reg_file(devinfo, inst, src1.file); - brw_inst_set_dpas_3src_src1_reg_nr(devinfo, inst, src1.nr); - brw_inst_set_dpas_3src_src1_subreg_nr(devinfo, inst, src1.subnr); - brw_inst_set_dpas_3src_src1_subbyte(devinfo, inst, BRW_SUB_BYTE_PRECISION_NONE); + elk_inst_set_dpas_3src_src1_reg_file(devinfo, inst, src1.file); + elk_inst_set_dpas_3src_src1_reg_nr(devinfo, inst, src1.nr); + elk_inst_set_dpas_3src_src1_subreg_nr(devinfo, inst, src1.subnr); + elk_inst_set_dpas_3src_src1_subbyte(devinfo, inst, ELK_SUB_BYTE_PRECISION_NONE); - assert(src2.file == BRW_GENERAL_REGISTER_FILE); + assert(src2.file == ELK_GENERAL_REGISTER_FILE); - brw_inst_set_dpas_3src_src2_reg_file(devinfo, inst, src2.file); - brw_inst_set_dpas_3src_src2_reg_nr(devinfo, inst, src2.nr); - brw_inst_set_dpas_3src_src2_subreg_nr(devinfo, inst, src2.subnr); - brw_inst_set_dpas_3src_src2_subbyte(devinfo, inst, BRW_SUB_BYTE_PRECISION_NONE); + elk_inst_set_dpas_3src_src2_reg_file(devinfo, inst, src2.file); + elk_inst_set_dpas_3src_src2_reg_nr(devinfo, inst, src2.nr); + elk_inst_set_dpas_3src_src2_subreg_nr(devinfo, inst, src2.subnr); + elk_inst_set_dpas_3src_src2_subbyte(devinfo, inst, ELK_SUB_BYTE_PRECISION_NONE); return inst; } @@ -1075,68 +1075,68 @@ brw_dpas_three_src(struct brw_codegen *p, enum gfx12_systolic_depth opcode, * Convenience routines. */ #define ALU1(OP) \ -brw_inst *brw_##OP(struct brw_codegen *p, \ - struct brw_reg dest, \ - struct brw_reg src0) \ +elk_inst *elk_##OP(struct elk_codegen *p, \ + struct elk_reg dest, \ + struct elk_reg src0) \ { \ - return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \ + return elk_alu1(p, ELK_OPCODE_##OP, dest, src0); \ } #define ALU2(OP) \ -brw_inst *brw_##OP(struct brw_codegen *p, \ - struct brw_reg dest, \ - struct brw_reg src0, \ - struct brw_reg src1) \ +elk_inst *elk_##OP(struct elk_codegen *p, \ + struct elk_reg dest, \ + struct elk_reg src0, \ + struct elk_reg src1) \ { \ - return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \ + return elk_alu2(p, ELK_OPCODE_##OP, dest, src0, src1); \ } #define ALU3(OP) \ -brw_inst *brw_##OP(struct brw_codegen *p, \ - struct brw_reg dest, \ - struct brw_reg src0, \ - struct brw_reg src1, \ - struct brw_reg src2) \ +elk_inst *elk_##OP(struct elk_codegen *p, \ + struct elk_reg dest, \ + struct elk_reg src0, \ + struct elk_reg src1, \ + struct elk_reg src2) \ { \ - if (p->current->access_mode == BRW_ALIGN_16) { \ - if (src0.vstride == BRW_VERTICAL_STRIDE_0) \ - src0.swizzle = BRW_SWIZZLE_XXXX; \ - if (src1.vstride == BRW_VERTICAL_STRIDE_0) \ - src1.swizzle = BRW_SWIZZLE_XXXX; \ - if (src2.vstride == BRW_VERTICAL_STRIDE_0) \ - src2.swizzle = BRW_SWIZZLE_XXXX; \ + if (p->current->access_mode == ELK_ALIGN_16) { \ + if (src0.vstride == ELK_VERTICAL_STRIDE_0) \ + src0.swizzle = ELK_SWIZZLE_XXXX; \ + if (src1.vstride == ELK_VERTICAL_STRIDE_0) \ + src1.swizzle = ELK_SWIZZLE_XXXX; \ + if (src2.vstride == ELK_VERTICAL_STRIDE_0) \ + src2.swizzle = ELK_SWIZZLE_XXXX; \ } \ - return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \ + return elk_alu3(p, ELK_OPCODE_##OP, dest, src0, src1, src2); \ } #define ALU3F(OP) \ -brw_inst *brw_##OP(struct brw_codegen *p, \ - struct brw_reg dest, \ - struct brw_reg src0, \ - struct brw_reg src1, \ - struct brw_reg src2) \ +elk_inst *elk_##OP(struct elk_codegen *p, \ + struct elk_reg dest, \ + struct elk_reg src0, \ + struct elk_reg src1, \ + struct elk_reg src2) \ { \ - assert(dest.type == BRW_REGISTER_TYPE_F || \ - dest.type == BRW_REGISTER_TYPE_DF); \ - if (dest.type == BRW_REGISTER_TYPE_F) { \ - assert(src0.type == BRW_REGISTER_TYPE_F); \ - assert(src1.type == BRW_REGISTER_TYPE_F); \ - assert(src2.type == BRW_REGISTER_TYPE_F); \ - } else if (dest.type == BRW_REGISTER_TYPE_DF) { \ - assert(src0.type == BRW_REGISTER_TYPE_DF); \ - assert(src1.type == BRW_REGISTER_TYPE_DF); \ - assert(src2.type == BRW_REGISTER_TYPE_DF); \ + assert(dest.type == ELK_REGISTER_TYPE_F || \ + dest.type == ELK_REGISTER_TYPE_DF); \ + if (dest.type == ELK_REGISTER_TYPE_F) { \ + assert(src0.type == ELK_REGISTER_TYPE_F); \ + assert(src1.type == ELK_REGISTER_TYPE_F); \ + assert(src2.type == ELK_REGISTER_TYPE_F); \ + } else if (dest.type == ELK_REGISTER_TYPE_DF) { \ + assert(src0.type == ELK_REGISTER_TYPE_DF); \ + assert(src1.type == ELK_REGISTER_TYPE_DF); \ + assert(src2.type == ELK_REGISTER_TYPE_DF); \ } \ \ - if (p->current->access_mode == BRW_ALIGN_16) { \ - if (src0.vstride == BRW_VERTICAL_STRIDE_0) \ - src0.swizzle = BRW_SWIZZLE_XXXX; \ - if (src1.vstride == BRW_VERTICAL_STRIDE_0) \ - src1.swizzle = BRW_SWIZZLE_XXXX; \ - if (src2.vstride == BRW_VERTICAL_STRIDE_0) \ - src2.swizzle = BRW_SWIZZLE_XXXX; \ + if (p->current->access_mode == ELK_ALIGN_16) { \ + if (src0.vstride == ELK_VERTICAL_STRIDE_0) \ + src0.swizzle = ELK_SWIZZLE_XXXX; \ + if (src1.vstride == ELK_VERTICAL_STRIDE_0) \ + src1.swizzle = ELK_SWIZZLE_XXXX; \ + if (src2.vstride == ELK_VERTICAL_STRIDE_0) \ + src2.swizzle = ELK_SWIZZLE_XXXX; \ } \ - return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \ + return elk_alu3(p, ELK_OPCODE_##OP, dest, src0, src1, src2); \ } ALU2(SEL) @@ -1177,8 +1177,8 @@ ALU2(ADDC) ALU2(SUBB) ALU3(ADD3) -brw_inst * -brw_MOV(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0) +elk_inst * +elk_MOV(struct elk_codegen *p, struct elk_reg dest, struct elk_reg src0) { const struct intel_device_info *devinfo = p->devinfo; @@ -1187,132 +1187,132 @@ brw_MOV(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0) * read each element twice. */ if (devinfo->verx10 == 70 && - brw_get_default_access_mode(p) == BRW_ALIGN_1 && - dest.type == BRW_REGISTER_TYPE_DF && - (src0.type == BRW_REGISTER_TYPE_F || - src0.type == BRW_REGISTER_TYPE_D || - src0.type == BRW_REGISTER_TYPE_UD) && + elk_get_default_access_mode(p) == ELK_ALIGN_1 && + dest.type == ELK_REGISTER_TYPE_DF && + (src0.type == ELK_REGISTER_TYPE_F || + src0.type == ELK_REGISTER_TYPE_D || + src0.type == ELK_REGISTER_TYPE_UD) && !has_scalar_region(src0)) { assert(src0.vstride == src0.width + src0.hstride); src0.vstride = src0.hstride; - src0.width = BRW_WIDTH_2; - src0.hstride = BRW_HORIZONTAL_STRIDE_0; + src0.width = ELK_WIDTH_2; + src0.hstride = ELK_HORIZONTAL_STRIDE_0; } - return brw_alu1(p, BRW_OPCODE_MOV, dest, src0); + return elk_alu1(p, ELK_OPCODE_MOV, dest, src0); } -brw_inst * -brw_ADD(struct brw_codegen *p, struct brw_reg dest, - struct brw_reg src0, struct brw_reg src1) +elk_inst * +elk_ADD(struct elk_codegen *p, struct elk_reg dest, + struct elk_reg src0, struct elk_reg src1) { /* 6.2.2: add */ - if (src0.type == BRW_REGISTER_TYPE_F || - (src0.file == BRW_IMMEDIATE_VALUE && - src0.type == BRW_REGISTER_TYPE_VF)) { - assert(src1.type != BRW_REGISTER_TYPE_UD); - assert(src1.type != BRW_REGISTER_TYPE_D); + if (src0.type == ELK_REGISTER_TYPE_F || + (src0.file == ELK_IMMEDIATE_VALUE && + src0.type == ELK_REGISTER_TYPE_VF)) { + assert(src1.type != ELK_REGISTER_TYPE_UD); + assert(src1.type != ELK_REGISTER_TYPE_D); } - if (src1.type == BRW_REGISTER_TYPE_F || - (src1.file == BRW_IMMEDIATE_VALUE && - src1.type == BRW_REGISTER_TYPE_VF)) { - assert(src0.type != BRW_REGISTER_TYPE_UD); - assert(src0.type != BRW_REGISTER_TYPE_D); + if (src1.type == ELK_REGISTER_TYPE_F || + (src1.file == ELK_IMMEDIATE_VALUE && + src1.type == ELK_REGISTER_TYPE_VF)) { + assert(src0.type != ELK_REGISTER_TYPE_UD); + assert(src0.type != ELK_REGISTER_TYPE_D); } - return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1); + return elk_alu2(p, ELK_OPCODE_ADD, dest, src0, src1); } -brw_inst * -brw_AVG(struct brw_codegen *p, struct brw_reg dest, - struct brw_reg src0, struct brw_reg src1) +elk_inst * +elk_AVG(struct elk_codegen *p, struct elk_reg dest, + struct elk_reg src0, struct elk_reg src1) { assert(dest.type == src0.type); assert(src0.type == src1.type); switch (src0.type) { - case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UD: break; default: - unreachable("Bad type for brw_AVG"); + unreachable("Bad type for elk_AVG"); } - return brw_alu2(p, BRW_OPCODE_AVG, dest, src0, src1); + return elk_alu2(p, ELK_OPCODE_AVG, dest, src0, src1); } -brw_inst * -brw_MUL(struct brw_codegen *p, struct brw_reg dest, - struct brw_reg src0, struct brw_reg src1) +elk_inst * +elk_MUL(struct elk_codegen *p, struct elk_reg dest, + struct elk_reg src0, struct elk_reg src1) { /* 6.32.38: mul */ - if (src0.type == BRW_REGISTER_TYPE_D || - src0.type == BRW_REGISTER_TYPE_UD || - src1.type == BRW_REGISTER_TYPE_D || - src1.type == BRW_REGISTER_TYPE_UD) { - assert(dest.type != BRW_REGISTER_TYPE_F); + if (src0.type == ELK_REGISTER_TYPE_D || + src0.type == ELK_REGISTER_TYPE_UD || + src1.type == ELK_REGISTER_TYPE_D || + src1.type == ELK_REGISTER_TYPE_UD) { + assert(dest.type != ELK_REGISTER_TYPE_F); } - if (src0.type == BRW_REGISTER_TYPE_F || - (src0.file == BRW_IMMEDIATE_VALUE && - src0.type == BRW_REGISTER_TYPE_VF)) { - assert(src1.type != BRW_REGISTER_TYPE_UD); - assert(src1.type != BRW_REGISTER_TYPE_D); + if (src0.type == ELK_REGISTER_TYPE_F || + (src0.file == ELK_IMMEDIATE_VALUE && + src0.type == ELK_REGISTER_TYPE_VF)) { + assert(src1.type != ELK_REGISTER_TYPE_UD); + assert(src1.type != ELK_REGISTER_TYPE_D); } - if (src1.type == BRW_REGISTER_TYPE_F || - (src1.file == BRW_IMMEDIATE_VALUE && - src1.type == BRW_REGISTER_TYPE_VF)) { - assert(src0.type != BRW_REGISTER_TYPE_UD); - assert(src0.type != BRW_REGISTER_TYPE_D); + if (src1.type == ELK_REGISTER_TYPE_F || + (src1.file == ELK_IMMEDIATE_VALUE && + src1.type == ELK_REGISTER_TYPE_VF)) { + assert(src0.type != ELK_REGISTER_TYPE_UD); + assert(src0.type != ELK_REGISTER_TYPE_D); } - assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE || - src0.nr != BRW_ARF_ACCUMULATOR); - assert(src1.file != BRW_ARCHITECTURE_REGISTER_FILE || - src1.nr != BRW_ARF_ACCUMULATOR); + assert(src0.file != ELK_ARCHITECTURE_REGISTER_FILE || + src0.nr != ELK_ARF_ACCUMULATOR); + assert(src1.file != ELK_ARCHITECTURE_REGISTER_FILE || + src1.nr != ELK_ARF_ACCUMULATOR); - return brw_alu2(p, BRW_OPCODE_MUL, dest, src0, src1); + return elk_alu2(p, ELK_OPCODE_MUL, dest, src0, src1); } -brw_inst * -brw_LINE(struct brw_codegen *p, struct brw_reg dest, - struct brw_reg src0, struct brw_reg src1) +elk_inst * +elk_LINE(struct elk_codegen *p, struct elk_reg dest, + struct elk_reg src0, struct elk_reg src1) { - src0.vstride = BRW_VERTICAL_STRIDE_0; - src0.width = BRW_WIDTH_1; - src0.hstride = BRW_HORIZONTAL_STRIDE_0; - return brw_alu2(p, BRW_OPCODE_LINE, dest, src0, src1); + src0.vstride = ELK_VERTICAL_STRIDE_0; + src0.width = ELK_WIDTH_1; + src0.hstride = ELK_HORIZONTAL_STRIDE_0; + return elk_alu2(p, ELK_OPCODE_LINE, dest, src0, src1); } -brw_inst * -brw_PLN(struct brw_codegen *p, struct brw_reg dest, - struct brw_reg src0, struct brw_reg src1) +elk_inst * +elk_PLN(struct elk_codegen *p, struct elk_reg dest, + struct elk_reg src0, struct elk_reg src1) { - src0.vstride = BRW_VERTICAL_STRIDE_0; - src0.width = BRW_WIDTH_1; - src0.hstride = BRW_HORIZONTAL_STRIDE_0; - src1.vstride = BRW_VERTICAL_STRIDE_8; - src1.width = BRW_WIDTH_8; - src1.hstride = BRW_HORIZONTAL_STRIDE_1; - return brw_alu2(p, BRW_OPCODE_PLN, dest, src0, src1); + src0.vstride = ELK_VERTICAL_STRIDE_0; + src0.width = ELK_WIDTH_1; + src0.hstride = ELK_HORIZONTAL_STRIDE_0; + src1.vstride = ELK_VERTICAL_STRIDE_8; + src1.width = ELK_WIDTH_8; + src1.hstride = ELK_HORIZONTAL_STRIDE_1; + return elk_alu2(p, ELK_OPCODE_PLN, dest, src0, src1); } -brw_inst * -brw_DPAS(struct brw_codegen *p, enum gfx12_systolic_depth sdepth, - unsigned rcount, struct brw_reg dest, struct brw_reg src0, - struct brw_reg src1, struct brw_reg src2) +elk_inst * +elk_DPAS(struct elk_codegen *p, enum elk_gfx12_systolic_depth sdepth, + unsigned rcount, struct elk_reg dest, struct elk_reg src0, + struct elk_reg src1, struct elk_reg src2) { - return brw_dpas_three_src(p, BRW_OPCODE_DPAS, sdepth, rcount, dest, src0, + return elk_dpas_three_src(p, ELK_OPCODE_DPAS, sdepth, rcount, dest, src0, src1, src2); } -brw_inst * -brw_F32TO16(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src) +elk_inst * +elk_F32TO16(struct elk_codegen *p, struct elk_reg dst, struct elk_reg src) { assert(p->devinfo->ver == 7); @@ -1320,23 +1320,23 @@ brw_F32TO16(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src) * Align1 mode. Gfx7 (only) does zero out the high 16 bits in Align16 * mode as an undocumented feature. */ - if (BRW_ALIGN_16 == brw_get_default_access_mode(p)) { - assert(dst.type == BRW_REGISTER_TYPE_UD); + if (ELK_ALIGN_16 == elk_get_default_access_mode(p)) { + assert(dst.type == ELK_REGISTER_TYPE_UD); } else { - assert(dst.type == BRW_REGISTER_TYPE_W || - dst.type == BRW_REGISTER_TYPE_UW); + assert(dst.type == ELK_REGISTER_TYPE_W || + dst.type == ELK_REGISTER_TYPE_UW); } - return brw_alu1(p, BRW_OPCODE_F32TO16, dst, src); + return elk_alu1(p, ELK_OPCODE_F32TO16, dst, src); } -brw_inst * -brw_F16TO32(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src) +elk_inst * +elk_F16TO32(struct elk_codegen *p, struct elk_reg dst, struct elk_reg src) { assert(p->devinfo->ver == 7); - if (BRW_ALIGN_16 == brw_get_default_access_mode(p)) { - assert(src.type == BRW_REGISTER_TYPE_UD); + if (ELK_ALIGN_16 == elk_get_default_access_mode(p)) { + assert(src.type == ELK_REGISTER_TYPE_UD); } else { /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32: * @@ -1344,49 +1344,49 @@ brw_F16TO32(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src) * type, the source data type must be Word (W). The destination type * must be F (Float). */ - assert(src.type == BRW_REGISTER_TYPE_W || - src.type == BRW_REGISTER_TYPE_UW); + assert(src.type == ELK_REGISTER_TYPE_W || + src.type == ELK_REGISTER_TYPE_UW); } - return brw_alu1(p, BRW_OPCODE_F16TO32, dst, src); + return elk_alu1(p, ELK_OPCODE_F16TO32, dst, src); } -void brw_NOP(struct brw_codegen *p) +void elk_NOP(struct elk_codegen *p) { - brw_inst *insn = next_insn(p, BRW_OPCODE_NOP); + elk_inst *insn = next_insn(p, ELK_OPCODE_NOP); memset(insn, 0, sizeof(*insn)); - brw_inst_set_opcode(p->isa, insn, BRW_OPCODE_NOP); + elk_inst_set_opcode(p->isa, insn, ELK_OPCODE_NOP); } -void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func) +void elk_SYNC(struct elk_codegen *p, enum tgl_sync_function func) { - brw_inst *insn = next_insn(p, BRW_OPCODE_SYNC); - brw_inst_set_cond_modifier(p->devinfo, insn, func); + elk_inst *insn = next_insn(p, ELK_OPCODE_SYNC); + elk_inst_set_cond_modifier(p->devinfo, insn, func); } /*********************************************************************** * Comparisons, if/else/endif */ -brw_inst * -brw_JMPI(struct brw_codegen *p, struct brw_reg index, +elk_inst * +elk_JMPI(struct elk_codegen *p, struct elk_reg index, unsigned predicate_control) { const struct intel_device_info *devinfo = p->devinfo; - struct brw_reg ip = brw_ip_reg(); - brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index); + struct elk_reg ip = elk_ip_reg(); + elk_inst *inst = elk_alu2(p, ELK_OPCODE_JMPI, ip, ip, index); - brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_1); - brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE); - brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE); - brw_inst_set_pred_control(devinfo, inst, predicate_control); + elk_inst_set_exec_size(devinfo, inst, ELK_EXECUTE_1); + elk_inst_set_qtr_control(devinfo, inst, ELK_COMPRESSION_NONE); + elk_inst_set_mask_control(devinfo, inst, ELK_MASK_DISABLE); + elk_inst_set_pred_control(devinfo, inst, predicate_control); return inst; } static void -push_if_stack(struct brw_codegen *p, brw_inst *inst) +push_if_stack(struct elk_codegen *p, elk_inst *inst) { p->if_stack[p->if_stack_depth] = inst - p->store; @@ -1398,15 +1398,15 @@ push_if_stack(struct brw_codegen *p, brw_inst *inst) } } -static brw_inst * -pop_if_stack(struct brw_codegen *p) +static elk_inst * +pop_if_stack(struct elk_codegen *p) { p->if_stack_depth--; return &p->store[p->if_stack[p->if_stack_depth]]; } static void -push_loop_stack(struct brw_codegen *p, brw_inst *inst) +push_loop_stack(struct elk_codegen *p, elk_inst *inst) { if (p->loop_stack_array_size <= (p->loop_stack_depth + 1)) { p->loop_stack_array_size *= 2; @@ -1421,8 +1421,8 @@ push_loop_stack(struct brw_codegen *p, brw_inst *inst) p->if_depth_in_loop[p->loop_stack_depth] = 0; } -static brw_inst * -get_inner_do_insn(struct brw_codegen *p) +static elk_inst * +get_inner_do_insn(struct elk_codegen *p) { return &p->store[p->loop_stack[p->loop_stack_depth - 1]]; } @@ -1440,45 +1440,45 @@ get_inner_do_insn(struct brw_codegen *p) * When the matching 'endif' instruction is reached, the flags are * popped off. If the stack is now empty, normal execution resumes. */ -brw_inst * -brw_IF(struct brw_codegen *p, unsigned execute_size) +elk_inst * +elk_IF(struct elk_codegen *p, unsigned execute_size) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; - insn = next_insn(p, BRW_OPCODE_IF); + insn = next_insn(p, ELK_OPCODE_IF); /* Override the defaults for this instruction: */ if (devinfo->ver < 6) { - brw_set_dest(p, insn, brw_ip_reg()); - brw_set_src0(p, insn, brw_ip_reg()); - brw_set_src1(p, insn, brw_imm_d(0x0)); + elk_set_dest(p, insn, elk_ip_reg()); + elk_set_src0(p, insn, elk_ip_reg()); + elk_set_src1(p, insn, elk_imm_d(0x0)); } else if (devinfo->ver == 6) { - brw_set_dest(p, insn, brw_imm_w(0)); - brw_inst_set_gfx6_jump_count(devinfo, insn, 0); - brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); - brw_set_src1(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); + elk_set_dest(p, insn, elk_imm_w(0)); + elk_inst_set_gfx6_jump_count(devinfo, insn, 0); + elk_set_src0(p, insn, vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_D))); + elk_set_src1(p, insn, vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_D))); } else if (devinfo->ver == 7) { - brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); - brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); - brw_set_src1(p, insn, brw_imm_w(0)); - brw_inst_set_jip(devinfo, insn, 0); - brw_inst_set_uip(devinfo, insn, 0); + elk_set_dest(p, insn, vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_D))); + elk_set_src0(p, insn, vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_D))); + elk_set_src1(p, insn, elk_imm_w(0)); + elk_inst_set_jip(devinfo, insn, 0); + elk_inst_set_uip(devinfo, insn, 0); } else { - brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); + elk_set_dest(p, insn, vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_D))); if (devinfo->ver < 12) - brw_set_src0(p, insn, brw_imm_d(0)); - brw_inst_set_jip(devinfo, insn, 0); - brw_inst_set_uip(devinfo, insn, 0); + elk_set_src0(p, insn, elk_imm_d(0)); + elk_inst_set_jip(devinfo, insn, 0); + elk_inst_set_uip(devinfo, insn, 0); } - brw_inst_set_exec_size(devinfo, insn, execute_size); - brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); - brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NORMAL); - brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE); + elk_inst_set_exec_size(devinfo, insn, execute_size); + elk_inst_set_qtr_control(devinfo, insn, ELK_COMPRESSION_NONE); + elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NORMAL); + elk_inst_set_mask_control(devinfo, insn, ELK_MASK_ENABLE); if (!p->single_program_flow && devinfo->ver < 6) - brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH); + elk_inst_set_thread_control(devinfo, insn, ELK_THREAD_SWITCH); push_if_stack(p, insn); p->if_depth_in_loop[p->loop_stack_depth]++; @@ -1488,24 +1488,24 @@ brw_IF(struct brw_codegen *p, unsigned execute_size) /* This function is only used for gfx6-style IF instructions with an * embedded comparison (conditional modifier). It is not used on gfx7. */ -brw_inst * -gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, - struct brw_reg src0, struct brw_reg src1) +elk_inst * +elk_gfx6_IF(struct elk_codegen *p, enum elk_conditional_mod conditional, + struct elk_reg src0, struct elk_reg src1) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; - insn = next_insn(p, BRW_OPCODE_IF); + insn = next_insn(p, ELK_OPCODE_IF); - brw_set_dest(p, insn, brw_imm_w(0)); - brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p)); - brw_inst_set_gfx6_jump_count(devinfo, insn, 0); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, src1); + elk_set_dest(p, insn, elk_imm_w(0)); + elk_inst_set_exec_size(devinfo, insn, elk_get_default_exec_size(p)); + elk_inst_set_gfx6_jump_count(devinfo, insn, 0); + elk_set_src0(p, insn, src0); + elk_set_src1(p, insn, src1); - assert(brw_inst_qtr_control(devinfo, insn) == BRW_COMPRESSION_NONE); - assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE); - brw_inst_set_cond_modifier(devinfo, insn, conditional); + assert(elk_inst_qtr_control(devinfo, insn) == ELK_COMPRESSION_NONE); + assert(elk_inst_pred_control(devinfo, insn) == ELK_PREDICATE_NONE); + elk_inst_set_cond_modifier(devinfo, insn, conditional); push_if_stack(p, insn); return insn; @@ -1515,18 +1515,18 @@ gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, * In single-program-flow (SPF) mode, convert IF and ELSE into ADDs. */ static void -convert_IF_ELSE_to_ADD(struct brw_codegen *p, - brw_inst *if_inst, brw_inst *else_inst) +convert_IF_ELSE_to_ADD(struct elk_codegen *p, + elk_inst *if_inst, elk_inst *else_inst) { const struct intel_device_info *devinfo = p->devinfo; /* The next instruction (where the ENDIF would be, if it existed) */ - brw_inst *next_inst = &p->store[p->nr_insn]; + elk_inst *next_inst = &p->store[p->nr_insn]; assert(p->single_program_flow); - assert(if_inst != NULL && brw_inst_opcode(p->isa, if_inst) == BRW_OPCODE_IF); - assert(else_inst == NULL || brw_inst_opcode(p->isa, else_inst) == BRW_OPCODE_ELSE); - assert(brw_inst_exec_size(devinfo, if_inst) == BRW_EXECUTE_1); + assert(if_inst != NULL && elk_inst_opcode(p->isa, if_inst) == ELK_OPCODE_IF); + assert(else_inst == NULL || elk_inst_opcode(p->isa, else_inst) == ELK_OPCODE_ELSE); + assert(elk_inst_exec_size(devinfo, if_inst) == ELK_EXECUTE_1); /* Convert IF to an ADD instruction that moves the instruction pointer * to the first instruction of the ELSE block. If there is no ELSE @@ -1536,19 +1536,19 @@ convert_IF_ELSE_to_ADD(struct brw_codegen *p, * stack operations, and if we're currently executing, we just want to * continue normally. */ - brw_inst_set_opcode(p->isa, if_inst, BRW_OPCODE_ADD); - brw_inst_set_pred_inv(devinfo, if_inst, true); + elk_inst_set_opcode(p->isa, if_inst, ELK_OPCODE_ADD); + elk_inst_set_pred_inv(devinfo, if_inst, true); if (else_inst != NULL) { /* Convert ELSE to an ADD instruction that points where the ENDIF * would be. */ - brw_inst_set_opcode(p->isa, else_inst, BRW_OPCODE_ADD); + elk_inst_set_opcode(p->isa, else_inst, ELK_OPCODE_ADD); - brw_inst_set_imm_ud(devinfo, if_inst, (else_inst - if_inst + 1) * 16); - brw_inst_set_imm_ud(devinfo, else_inst, (next_inst - else_inst) * 16); + elk_inst_set_imm_ud(devinfo, if_inst, (else_inst - if_inst + 1) * 16); + elk_inst_set_imm_ud(devinfo, else_inst, (next_inst - else_inst) * 16); } else { - brw_inst_set_imm_ud(devinfo, if_inst, (next_inst - if_inst) * 16); + elk_inst_set_imm_ud(devinfo, if_inst, (next_inst - if_inst) * 16); } } @@ -1556,15 +1556,15 @@ convert_IF_ELSE_to_ADD(struct brw_codegen *p, * Patch IF and ELSE instructions with appropriate jump targets. */ static void -patch_IF_ELSE(struct brw_codegen *p, - brw_inst *if_inst, brw_inst *else_inst, brw_inst *endif_inst) +patch_IF_ELSE(struct elk_codegen *p, + elk_inst *if_inst, elk_inst *else_inst, elk_inst *endif_inst) { const struct intel_device_info *devinfo = p->devinfo; /* We shouldn't be patching IF and ELSE instructions in single program flow * mode when gen < 6, because in single program flow mode on those * platforms, we convert flow control instructions to conditional ADDs that - * operate on IP (see brw_ENDIF). + * operate on IP (see elk_ENDIF). * * However, on Gfx6, writing to IP doesn't work in single program flow mode * (see the SandyBridge PRM, Volume 4 part 2, p79: "When SPF is ON, IP may @@ -1576,14 +1576,14 @@ patch_IF_ELSE(struct brw_codegen *p, if (devinfo->ver < 6) assert(!p->single_program_flow); - assert(if_inst != NULL && brw_inst_opcode(p->isa, if_inst) == BRW_OPCODE_IF); + assert(if_inst != NULL && elk_inst_opcode(p->isa, if_inst) == ELK_OPCODE_IF); assert(endif_inst != NULL); - assert(else_inst == NULL || brw_inst_opcode(p->isa, else_inst) == BRW_OPCODE_ELSE); + assert(else_inst == NULL || elk_inst_opcode(p->isa, else_inst) == ELK_OPCODE_ELSE); - unsigned br = brw_jump_scale(devinfo); + unsigned br = elk_jump_scale(devinfo); - assert(brw_inst_opcode(p->isa, endif_inst) == BRW_OPCODE_ENDIF); - brw_inst_set_exec_size(devinfo, endif_inst, brw_inst_exec_size(devinfo, if_inst)); + assert(elk_inst_opcode(p->isa, endif_inst) == ELK_OPCODE_ENDIF); + elk_inst_set_exec_size(devinfo, endif_inst, elk_inst_exec_size(devinfo, if_inst)); if (else_inst == NULL) { /* Patch IF -> ENDIF */ @@ -1591,47 +1591,47 @@ patch_IF_ELSE(struct brw_codegen *p, /* Turn it into an IFF, which means no mask stack operations for * all-false and jumping past the ENDIF. */ - brw_inst_set_opcode(p->isa, if_inst, BRW_OPCODE_IFF); - brw_inst_set_gfx4_jump_count(devinfo, if_inst, + elk_inst_set_opcode(p->isa, if_inst, ELK_OPCODE_IFF); + elk_inst_set_gfx4_jump_count(devinfo, if_inst, br * (endif_inst - if_inst + 1)); - brw_inst_set_gfx4_pop_count(devinfo, if_inst, 0); + elk_inst_set_gfx4_pop_count(devinfo, if_inst, 0); } else if (devinfo->ver == 6) { /* As of gfx6, there is no IFF and IF must point to the ENDIF. */ - brw_inst_set_gfx6_jump_count(devinfo, if_inst, br*(endif_inst - if_inst)); + elk_inst_set_gfx6_jump_count(devinfo, if_inst, br*(endif_inst - if_inst)); } else { - brw_inst_set_uip(devinfo, if_inst, br * (endif_inst - if_inst)); - brw_inst_set_jip(devinfo, if_inst, br * (endif_inst - if_inst)); + elk_inst_set_uip(devinfo, if_inst, br * (endif_inst - if_inst)); + elk_inst_set_jip(devinfo, if_inst, br * (endif_inst - if_inst)); } } else { - brw_inst_set_exec_size(devinfo, else_inst, brw_inst_exec_size(devinfo, if_inst)); + elk_inst_set_exec_size(devinfo, else_inst, elk_inst_exec_size(devinfo, if_inst)); /* Patch IF -> ELSE */ if (devinfo->ver < 6) { - brw_inst_set_gfx4_jump_count(devinfo, if_inst, + elk_inst_set_gfx4_jump_count(devinfo, if_inst, br * (else_inst - if_inst)); - brw_inst_set_gfx4_pop_count(devinfo, if_inst, 0); + elk_inst_set_gfx4_pop_count(devinfo, if_inst, 0); } else if (devinfo->ver == 6) { - brw_inst_set_gfx6_jump_count(devinfo, if_inst, + elk_inst_set_gfx6_jump_count(devinfo, if_inst, br * (else_inst - if_inst + 1)); } /* Patch ELSE -> ENDIF */ if (devinfo->ver < 6) { - /* BRW_OPCODE_ELSE pre-gfx6 should point just past the + /* ELK_OPCODE_ELSE pre-gfx6 should point just past the * matching ENDIF. */ - brw_inst_set_gfx4_jump_count(devinfo, else_inst, + elk_inst_set_gfx4_jump_count(devinfo, else_inst, br * (endif_inst - else_inst + 1)); - brw_inst_set_gfx4_pop_count(devinfo, else_inst, 1); + elk_inst_set_gfx4_pop_count(devinfo, else_inst, 1); } else if (devinfo->ver == 6) { - /* BRW_OPCODE_ELSE on gfx6 should point to the matching ENDIF. */ - brw_inst_set_gfx6_jump_count(devinfo, else_inst, + /* ELK_OPCODE_ELSE on gfx6 should point to the matching ENDIF. */ + elk_inst_set_gfx6_jump_count(devinfo, else_inst, br * (endif_inst - else_inst)); } else { /* The IF instruction's JIP should point just past the ELSE */ - brw_inst_set_jip(devinfo, if_inst, br * (else_inst - if_inst + 1)); + elk_inst_set_jip(devinfo, if_inst, br * (else_inst - if_inst + 1)); /* The IF instruction's UIP and ELSE's JIP should point to ENDIF */ - brw_inst_set_uip(devinfo, if_inst, br * (endif_inst - if_inst)); + elk_inst_set_uip(devinfo, if_inst, br * (endif_inst - if_inst)); if (devinfo->ver >= 8 && devinfo->ver < 11) { /* Set the ELSE instruction to use branch_ctrl with a join @@ -1643,10 +1643,10 @@ patch_IF_ELSE(struct brw_codegen *p, * Wa_220160235, which could cause the program to continue * running with all channels disabled. */ - brw_inst_set_jip(devinfo, else_inst, br * (endif_inst - else_inst - 1)); - brw_inst_set_branch_control(devinfo, else_inst, true); + elk_inst_set_jip(devinfo, else_inst, br * (endif_inst - else_inst - 1)); + elk_inst_set_branch_control(devinfo, else_inst, true); } else { - brw_inst_set_jip(devinfo, else_inst, br * (endif_inst - else_inst)); + elk_inst_set_jip(devinfo, else_inst, br * (endif_inst - else_inst)); } if (devinfo->ver >= 8) { @@ -1654,66 +1654,66 @@ patch_IF_ELSE(struct brw_codegen *p, * JIP and UIP both should point to ENDIF on those * platforms. */ - brw_inst_set_uip(devinfo, else_inst, br * (endif_inst - else_inst)); + elk_inst_set_uip(devinfo, else_inst, br * (endif_inst - else_inst)); } } } } void -brw_ELSE(struct brw_codegen *p) +elk_ELSE(struct elk_codegen *p) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; - insn = next_insn(p, BRW_OPCODE_ELSE); + insn = next_insn(p, ELK_OPCODE_ELSE); if (devinfo->ver < 6) { - brw_set_dest(p, insn, brw_ip_reg()); - brw_set_src0(p, insn, brw_ip_reg()); - brw_set_src1(p, insn, brw_imm_d(0x0)); + elk_set_dest(p, insn, elk_ip_reg()); + elk_set_src0(p, insn, elk_ip_reg()); + elk_set_src1(p, insn, elk_imm_d(0x0)); } else if (devinfo->ver == 6) { - brw_set_dest(p, insn, brw_imm_w(0)); - brw_inst_set_gfx6_jump_count(devinfo, insn, 0); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + elk_set_dest(p, insn, elk_imm_w(0)); + elk_inst_set_gfx6_jump_count(devinfo, insn, 0); + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); } else if (devinfo->ver == 7) { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, brw_imm_w(0)); - brw_inst_set_jip(devinfo, insn, 0); - brw_inst_set_uip(devinfo, insn, 0); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, elk_imm_w(0)); + elk_inst_set_jip(devinfo, insn, 0); + elk_inst_set_uip(devinfo, insn, 0); } else { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); if (devinfo->ver < 12) - brw_set_src0(p, insn, brw_imm_d(0)); - brw_inst_set_jip(devinfo, insn, 0); - brw_inst_set_uip(devinfo, insn, 0); + elk_set_src0(p, insn, elk_imm_d(0)); + elk_inst_set_jip(devinfo, insn, 0); + elk_inst_set_uip(devinfo, insn, 0); } - brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); - brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE); + elk_inst_set_qtr_control(devinfo, insn, ELK_COMPRESSION_NONE); + elk_inst_set_mask_control(devinfo, insn, ELK_MASK_ENABLE); if (!p->single_program_flow && devinfo->ver < 6) - brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH); + elk_inst_set_thread_control(devinfo, insn, ELK_THREAD_SWITCH); push_if_stack(p, insn); } void -brw_ENDIF(struct brw_codegen *p) +elk_ENDIF(struct elk_codegen *p) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn = NULL; - brw_inst *else_inst = NULL; - brw_inst *if_inst = NULL; - brw_inst *tmp; + elk_inst *insn = NULL; + elk_inst *else_inst = NULL; + elk_inst *if_inst = NULL; + elk_inst *tmp; bool emit_endif = true; assert(p->if_stack_depth > 0); if (devinfo->ver >= 8 && devinfo->ver < 11 && - brw_inst_opcode(p->isa, &p->store[p->if_stack[ - p->if_stack_depth - 1]]) == BRW_OPCODE_ELSE) { + elk_inst_opcode(p->isa, &p->store[p->if_stack[ + p->if_stack_depth - 1]]) == ELK_OPCODE_ELSE) { /* Insert a NOP to be specified as join instruction within the * ELSE block, which is valid for an ELSE instruction with * branch_ctrl on. The ELSE instruction will be set to jump @@ -1722,7 +1722,7 @@ brw_ENDIF(struct brw_codegen *p) * some cases due to Wa_220160235, which could cause the program * to continue running with all channels disabled. */ - brw_NOP(p); + elk_NOP(p); } /* In single program flow mode, we can express IF and ELSE instructions @@ -1746,12 +1746,12 @@ brw_ENDIF(struct brw_codegen *p) * store pointer from an index */ if (emit_endif) - insn = next_insn(p, BRW_OPCODE_ENDIF); + insn = next_insn(p, ELK_OPCODE_ENDIF); /* Pop the IF and (optional) ELSE instructions from the stack */ p->if_depth_in_loop[p->loop_stack_depth]--; tmp = pop_if_stack(p); - if (brw_inst_opcode(p->isa, tmp) == BRW_OPCODE_ELSE) { + if (elk_inst_opcode(p->isa, tmp) == ELK_OPCODE_ELSE) { else_inst = tmp; tmp = pop_if_stack(p); } @@ -1764,115 +1764,115 @@ brw_ENDIF(struct brw_codegen *p) } if (devinfo->ver < 6) { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, brw_imm_d(0x0)); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, elk_imm_d(0x0)); } else if (devinfo->ver == 6) { - brw_set_dest(p, insn, brw_imm_w(0)); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + elk_set_dest(p, insn, elk_imm_w(0)); + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); } else if (devinfo->ver == 7) { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, brw_imm_w(0)); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, elk_imm_w(0)); } else { - brw_set_src0(p, insn, brw_imm_d(0)); + elk_set_src0(p, insn, elk_imm_d(0)); } - brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); - brw_inst_set_mask_control(devinfo, insn, BRW_MASK_ENABLE); + elk_inst_set_qtr_control(devinfo, insn, ELK_COMPRESSION_NONE); + elk_inst_set_mask_control(devinfo, insn, ELK_MASK_ENABLE); if (devinfo->ver < 6) - brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH); + elk_inst_set_thread_control(devinfo, insn, ELK_THREAD_SWITCH); /* Also pop item off the stack in the endif instruction: */ if (devinfo->ver < 6) { - brw_inst_set_gfx4_jump_count(devinfo, insn, 0); - brw_inst_set_gfx4_pop_count(devinfo, insn, 1); + elk_inst_set_gfx4_jump_count(devinfo, insn, 0); + elk_inst_set_gfx4_pop_count(devinfo, insn, 1); } else if (devinfo->ver == 6) { - brw_inst_set_gfx6_jump_count(devinfo, insn, 2); + elk_inst_set_gfx6_jump_count(devinfo, insn, 2); } else { - brw_inst_set_jip(devinfo, insn, 2); + elk_inst_set_jip(devinfo, insn, 2); } patch_IF_ELSE(p, if_inst, else_inst, insn); } -brw_inst * -brw_BREAK(struct brw_codegen *p) +elk_inst * +elk_BREAK(struct elk_codegen *p) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; - insn = next_insn(p, BRW_OPCODE_BREAK); + insn = next_insn(p, ELK_OPCODE_BREAK); if (devinfo->ver >= 8) { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src0(p, insn, brw_imm_d(0x0)); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src0(p, insn, elk_imm_d(0x0)); } else if (devinfo->ver >= 6) { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, brw_imm_d(0x0)); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, elk_imm_d(0x0)); } else { - brw_set_dest(p, insn, brw_ip_reg()); - brw_set_src0(p, insn, brw_ip_reg()); - brw_set_src1(p, insn, brw_imm_d(0x0)); - brw_inst_set_gfx4_pop_count(devinfo, insn, + elk_set_dest(p, insn, elk_ip_reg()); + elk_set_src0(p, insn, elk_ip_reg()); + elk_set_src1(p, insn, elk_imm_d(0x0)); + elk_inst_set_gfx4_pop_count(devinfo, insn, p->if_depth_in_loop[p->loop_stack_depth]); } - brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); - brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p)); + elk_inst_set_qtr_control(devinfo, insn, ELK_COMPRESSION_NONE); + elk_inst_set_exec_size(devinfo, insn, elk_get_default_exec_size(p)); return insn; } -brw_inst * -brw_CONT(struct brw_codegen *p) +elk_inst * +elk_CONT(struct elk_codegen *p) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; - insn = next_insn(p, BRW_OPCODE_CONTINUE); - brw_set_dest(p, insn, brw_ip_reg()); + insn = next_insn(p, ELK_OPCODE_CONTINUE); + elk_set_dest(p, insn, elk_ip_reg()); if (devinfo->ver >= 8) { - brw_set_src0(p, insn, brw_imm_d(0x0)); + elk_set_src0(p, insn, elk_imm_d(0x0)); } else { - brw_set_src0(p, insn, brw_ip_reg()); - brw_set_src1(p, insn, brw_imm_d(0x0)); + elk_set_src0(p, insn, elk_ip_reg()); + elk_set_src1(p, insn, elk_imm_d(0x0)); } if (devinfo->ver < 6) { - brw_inst_set_gfx4_pop_count(devinfo, insn, + elk_inst_set_gfx4_pop_count(devinfo, insn, p->if_depth_in_loop[p->loop_stack_depth]); } - brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); - brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p)); + elk_inst_set_qtr_control(devinfo, insn, ELK_COMPRESSION_NONE); + elk_inst_set_exec_size(devinfo, insn, elk_get_default_exec_size(p)); return insn; } -brw_inst * -brw_HALT(struct brw_codegen *p) +elk_inst * +elk_HALT(struct elk_codegen *p) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; - insn = next_insn(p, BRW_OPCODE_HALT); - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + insn = next_insn(p, ELK_OPCODE_HALT); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); if (devinfo->ver < 6) { /* From the Gfx4 PRM: * * "IP register must be put (for example, by the assembler) at * and locations. */ - brw_set_dest(p, insn, brw_ip_reg()); - brw_set_src0(p, insn, brw_ip_reg()); - brw_set_src1(p, insn, brw_imm_d(0x0)); /* exitcode updated later. */ + elk_set_dest(p, insn, elk_ip_reg()); + elk_set_src0(p, insn, elk_ip_reg()); + elk_set_src1(p, insn, elk_imm_d(0x0)); /* exitcode updated later. */ } else if (devinfo->ver < 8) { - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, brw_imm_d(0x0)); /* UIP and JIP, updated later. */ + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, elk_imm_d(0x0)); /* UIP and JIP, updated later. */ } else if (devinfo->ver < 12) { - brw_set_src0(p, insn, brw_imm_d(0x0)); + elk_set_src0(p, insn, elk_imm_d(0x0)); } - brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); - brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p)); + elk_inst_set_qtr_control(devinfo, insn, ELK_COMPRESSION_NONE); + elk_inst_set_exec_size(devinfo, insn, elk_get_default_exec_size(p)); return insn; } @@ -1892,8 +1892,8 @@ brw_HALT(struct brw_codegen *p) * For gfx6, there's no more mask stack, so no need for DO. WHILE * just points back to the first instruction of the loop. */ -brw_inst * -brw_DO(struct brw_codegen *p, unsigned execute_size) +elk_inst * +elk_DO(struct elk_codegen *p, unsigned execute_size) { const struct intel_device_info *devinfo = p->devinfo; @@ -1901,19 +1901,19 @@ brw_DO(struct brw_codegen *p, unsigned execute_size) push_loop_stack(p, &p->store[p->nr_insn]); return &p->store[p->nr_insn]; } else { - brw_inst *insn = next_insn(p, BRW_OPCODE_DO); + elk_inst *insn = next_insn(p, ELK_OPCODE_DO); push_loop_stack(p, insn); /* Override the defaults for this instruction: */ - brw_set_dest(p, insn, brw_null_reg()); - brw_set_src0(p, insn, brw_null_reg()); - brw_set_src1(p, insn, brw_null_reg()); + elk_set_dest(p, insn, elk_null_reg()); + elk_set_src0(p, insn, elk_null_reg()); + elk_set_src1(p, insn, elk_null_reg()); - brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); - brw_inst_set_exec_size(devinfo, insn, execute_size); - brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE); + elk_inst_set_qtr_control(devinfo, insn, ELK_COMPRESSION_NONE); + elk_inst_set_exec_size(devinfo, insn, execute_size); + elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NONE); return insn; } @@ -1923,16 +1923,16 @@ brw_DO(struct brw_codegen *p, unsigned execute_size) * For pre-gfx6, we patch BREAK/CONT instructions to point at the WHILE * instruction here. * - * For gfx6+, see brw_set_uip_jip(), which doesn't care so much about the loop + * For gfx6+, see elk_set_uip_jip(), which doesn't care so much about the loop * nesting, since it can always just point to the end of the block/current loop. */ static void -brw_patch_break_cont(struct brw_codegen *p, brw_inst *while_inst) +elk_patch_break_cont(struct elk_codegen *p, elk_inst *while_inst) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *do_inst = get_inner_do_insn(p); - brw_inst *inst; - unsigned br = brw_jump_scale(devinfo); + elk_inst *do_inst = get_inner_do_insn(p); + elk_inst *inst; + unsigned br = elk_jump_scale(devinfo); assert(devinfo->ver < 6); @@ -1941,73 +1941,73 @@ brw_patch_break_cont(struct brw_codegen *p, brw_inst *while_inst) * been patched because it's part of a loop inside of the one we're * patching. */ - if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_BREAK && - brw_inst_gfx4_jump_count(devinfo, inst) == 0) { - brw_inst_set_gfx4_jump_count(devinfo, inst, br*((while_inst - inst) + 1)); - } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_CONTINUE && - brw_inst_gfx4_jump_count(devinfo, inst) == 0) { - brw_inst_set_gfx4_jump_count(devinfo, inst, br * (while_inst - inst)); + if (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_BREAK && + elk_inst_gfx4_jump_count(devinfo, inst) == 0) { + elk_inst_set_gfx4_jump_count(devinfo, inst, br*((while_inst - inst) + 1)); + } else if (elk_inst_opcode(p->isa, inst) == ELK_OPCODE_CONTINUE && + elk_inst_gfx4_jump_count(devinfo, inst) == 0) { + elk_inst_set_gfx4_jump_count(devinfo, inst, br * (while_inst - inst)); } } } -brw_inst * -brw_WHILE(struct brw_codegen *p) +elk_inst * +elk_WHILE(struct elk_codegen *p) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn, *do_insn; - unsigned br = brw_jump_scale(devinfo); + elk_inst *insn, *do_insn; + unsigned br = elk_jump_scale(devinfo); if (devinfo->ver >= 6) { - insn = next_insn(p, BRW_OPCODE_WHILE); + insn = next_insn(p, ELK_OPCODE_WHILE); do_insn = get_inner_do_insn(p); if (devinfo->ver >= 8) { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); if (devinfo->ver < 12) - brw_set_src0(p, insn, brw_imm_d(0)); - brw_inst_set_jip(devinfo, insn, br * (do_insn - insn)); + elk_set_src0(p, insn, elk_imm_d(0)); + elk_inst_set_jip(devinfo, insn, br * (do_insn - insn)); } else if (devinfo->ver == 7) { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, brw_imm_w(0)); - brw_inst_set_jip(devinfo, insn, br * (do_insn - insn)); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, elk_imm_w(0)); + elk_inst_set_jip(devinfo, insn, br * (do_insn - insn)); } else { - brw_set_dest(p, insn, brw_imm_w(0)); - brw_inst_set_gfx6_jump_count(devinfo, insn, br * (do_insn - insn)); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + elk_set_dest(p, insn, elk_imm_w(0)); + elk_inst_set_gfx6_jump_count(devinfo, insn, br * (do_insn - insn)); + elk_set_src0(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); + elk_set_src1(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); } - brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p)); + elk_inst_set_exec_size(devinfo, insn, elk_get_default_exec_size(p)); } else { if (p->single_program_flow) { - insn = next_insn(p, BRW_OPCODE_ADD); + insn = next_insn(p, ELK_OPCODE_ADD); do_insn = get_inner_do_insn(p); - brw_set_dest(p, insn, brw_ip_reg()); - brw_set_src0(p, insn, brw_ip_reg()); - brw_set_src1(p, insn, brw_imm_d((do_insn - insn) * 16)); - brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1); + elk_set_dest(p, insn, elk_ip_reg()); + elk_set_src0(p, insn, elk_ip_reg()); + elk_set_src1(p, insn, elk_imm_d((do_insn - insn) * 16)); + elk_inst_set_exec_size(devinfo, insn, ELK_EXECUTE_1); } else { - insn = next_insn(p, BRW_OPCODE_WHILE); + insn = next_insn(p, ELK_OPCODE_WHILE); do_insn = get_inner_do_insn(p); - assert(brw_inst_opcode(p->isa, do_insn) == BRW_OPCODE_DO); + assert(elk_inst_opcode(p->isa, do_insn) == ELK_OPCODE_DO); - brw_set_dest(p, insn, brw_ip_reg()); - brw_set_src0(p, insn, brw_ip_reg()); - brw_set_src1(p, insn, brw_imm_d(0)); + elk_set_dest(p, insn, elk_ip_reg()); + elk_set_src0(p, insn, elk_ip_reg()); + elk_set_src1(p, insn, elk_imm_d(0)); - brw_inst_set_exec_size(devinfo, insn, brw_inst_exec_size(devinfo, do_insn)); - brw_inst_set_gfx4_jump_count(devinfo, insn, br * (do_insn - insn + 1)); - brw_inst_set_gfx4_pop_count(devinfo, insn, 0); + elk_inst_set_exec_size(devinfo, insn, elk_inst_exec_size(devinfo, do_insn)); + elk_inst_set_gfx4_jump_count(devinfo, insn, br * (do_insn - insn + 1)); + elk_inst_set_gfx4_pop_count(devinfo, insn, 0); - brw_patch_break_cont(p, insn); + elk_patch_break_cont(p, insn); } } - brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); + elk_inst_set_qtr_control(devinfo, insn, ELK_COMPRESSION_NONE); p->loop_stack_depth--; @@ -2016,19 +2016,19 @@ brw_WHILE(struct brw_codegen *p) /* FORWARD JUMPS: */ -void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx) +void elk_land_fwd_jump(struct elk_codegen *p, int jmp_insn_idx) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *jmp_insn = &p->store[jmp_insn_idx]; + elk_inst *jmp_insn = &p->store[jmp_insn_idx]; unsigned jmpi = 1; if (devinfo->ver >= 5) jmpi = 2; - assert(brw_inst_opcode(p->isa, jmp_insn) == BRW_OPCODE_JMPI); - assert(brw_inst_src1_reg_file(devinfo, jmp_insn) == BRW_IMMEDIATE_VALUE); + assert(elk_inst_opcode(p->isa, jmp_insn) == ELK_OPCODE_JMPI); + assert(elk_inst_src1_reg_file(devinfo, jmp_insn) == ELK_IMMEDIATE_VALUE); - brw_inst_set_gfx4_jump_count(devinfo, jmp_insn, + elk_inst_set_gfx4_jump_count(devinfo, jmp_insn, jmpi * (p->nr_insn - jmp_insn_idx - 1)); } @@ -2036,19 +2036,19 @@ void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx) * instruction should populate the flag register. It might be simpler * just to use the flag reg for most WM tasks? */ -void brw_CMP(struct brw_codegen *p, - struct brw_reg dest, +void elk_CMP(struct elk_codegen *p, + struct elk_reg dest, unsigned conditional, - struct brw_reg src0, - struct brw_reg src1) + struct elk_reg src0, + struct elk_reg src1) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn = next_insn(p, BRW_OPCODE_CMP); + elk_inst *insn = next_insn(p, ELK_OPCODE_CMP); - brw_inst_set_cond_modifier(devinfo, insn, conditional); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, src1); + elk_inst_set_cond_modifier(devinfo, insn, conditional); + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_src1(p, insn, src1); /* Item WaCMPInstNullDstForcesThreadSwitch in the Haswell Bspec workarounds * page says: @@ -2058,26 +2058,26 @@ void brw_CMP(struct brw_codegen *p, * mentioned on their work-arounds pages. */ if (devinfo->ver == 7) { - if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && - dest.nr == BRW_ARF_NULL) { - brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH); + if (dest.file == ELK_ARCHITECTURE_REGISTER_FILE && + dest.nr == ELK_ARF_NULL) { + elk_inst_set_thread_control(devinfo, insn, ELK_THREAD_SWITCH); } } } -void brw_CMPN(struct brw_codegen *p, - struct brw_reg dest, +void elk_CMPN(struct elk_codegen *p, + struct elk_reg dest, unsigned conditional, - struct brw_reg src0, - struct brw_reg src1) + struct elk_reg src0, + struct elk_reg src1) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn = next_insn(p, BRW_OPCODE_CMPN); + elk_inst *insn = next_insn(p, ELK_OPCODE_CMPN); - brw_inst_set_cond_modifier(devinfo, insn, conditional); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, src1); + elk_inst_set_cond_modifier(devinfo, insn, conditional); + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_src1(p, insn, src1); /* Page 166 of the Ivy Bridge PRM Volume 4 part 3 (Execution Unit ISA) * says: @@ -2088,9 +2088,9 @@ void brw_CMPN(struct brw_codegen *p, * Page 77 of the Haswell PRM Volume 2b contains the same text. */ if (devinfo->ver == 7) { - if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && - dest.nr == BRW_ARF_NULL) { - brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH); + if (dest.file == ELK_ARCHITECTURE_REGISTER_FILE && + dest.nr == ELK_ARF_NULL) { + elk_inst_set_thread_control(devinfo, insn, ELK_THREAD_SWITCH); } } } @@ -2101,20 +2101,20 @@ void brw_CMPN(struct brw_codegen *p, /** Extended math function, float[8]. */ -void gfx4_math(struct brw_codegen *p, - struct brw_reg dest, +void elk_gfx4_math(struct elk_codegen *p, + struct elk_reg dest, unsigned function, unsigned msg_reg_nr, - struct brw_reg src, + struct elk_reg src, unsigned precision ) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); + elk_inst *insn = next_insn(p, ELK_OPCODE_SEND); unsigned data_type; if (has_scalar_region(src)) { - data_type = BRW_MATH_DATA_SCALAR; + data_type = ELK_MATH_DATA_SCALAR; } else { - data_type = BRW_MATH_DATA_VECTOR; + data_type = ELK_MATH_DATA_VECTOR; } assert(devinfo->ver < 6); @@ -2122,46 +2122,46 @@ void gfx4_math(struct brw_codegen *p, /* Example code doesn't set predicate_control for send * instructions. */ - brw_inst_set_pred_control(devinfo, insn, 0); - brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr); + elk_inst_set_pred_control(devinfo, insn, 0); + elk_inst_set_base_mrf(devinfo, insn, msg_reg_nr); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src); - brw_set_math_message(p, + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src); + elk_set_math_message(p, insn, function, - src.type == BRW_REGISTER_TYPE_D, + src.type == ELK_REGISTER_TYPE_D, precision, data_type); } -void gfx6_math(struct brw_codegen *p, - struct brw_reg dest, +void elk_gfx6_math(struct elk_codegen *p, + struct elk_reg dest, unsigned function, - struct brw_reg src0, - struct brw_reg src1) + struct elk_reg src0, + struct elk_reg src1) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn = next_insn(p, BRW_OPCODE_MATH); + elk_inst *insn = next_insn(p, ELK_OPCODE_MATH); assert(devinfo->ver >= 6); - assert(dest.file == BRW_GENERAL_REGISTER_FILE || - (devinfo->ver >= 7 && dest.file == BRW_MESSAGE_REGISTER_FILE)); + assert(dest.file == ELK_GENERAL_REGISTER_FILE || + (devinfo->ver >= 7 && dest.file == ELK_MESSAGE_REGISTER_FILE)); - assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1); + assert(dest.hstride == ELK_HORIZONTAL_STRIDE_1); if (devinfo->ver == 6) { - assert(src0.hstride == BRW_HORIZONTAL_STRIDE_1); - assert(src1.hstride == BRW_HORIZONTAL_STRIDE_1); + assert(src0.hstride == ELK_HORIZONTAL_STRIDE_1); + assert(src1.hstride == ELK_HORIZONTAL_STRIDE_1); } - if (function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT || - function == BRW_MATH_FUNCTION_INT_DIV_REMAINDER || - function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) { - assert(src0.type != BRW_REGISTER_TYPE_F); - assert(src1.type != BRW_REGISTER_TYPE_F); - assert(src1.file == BRW_GENERAL_REGISTER_FILE || - (devinfo->ver >= 8 && src1.file == BRW_IMMEDIATE_VALUE)); + if (function == ELK_MATH_FUNCTION_INT_DIV_QUOTIENT || + function == ELK_MATH_FUNCTION_INT_DIV_REMAINDER || + function == ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) { + assert(src0.type != ELK_REGISTER_TYPE_F); + assert(src1.type != ELK_REGISTER_TYPE_F); + assert(src1.file == ELK_GENERAL_REGISTER_FILE || + (devinfo->ver >= 8 && src1.file == ELK_IMMEDIATE_VALUE)); /* From BSpec 6647/47428 "[Instruction] Extended Math Function": * INT DIV function does not support source modifiers. */ @@ -2170,10 +2170,10 @@ void gfx6_math(struct brw_codegen *p, assert(!src1.negate); assert(!src1.abs); } else { - assert(src0.type == BRW_REGISTER_TYPE_F || - (src0.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9)); - assert(src1.type == BRW_REGISTER_TYPE_F || - (src1.type == BRW_REGISTER_TYPE_HF && devinfo->ver >= 9)); + assert(src0.type == ELK_REGISTER_TYPE_F || + (src0.type == ELK_REGISTER_TYPE_HF && devinfo->ver >= 9)); + assert(src1.type == ELK_REGISTER_TYPE_F || + (src1.type == ELK_REGISTER_TYPE_HF && devinfo->ver >= 9)); } /* Source modifiers are ignored for extended math instructions on Gfx6. */ @@ -2184,11 +2184,11 @@ void gfx6_math(struct brw_codegen *p, assert(!src1.abs); } - brw_inst_set_math_function(devinfo, insn, function); + elk_inst_set_math_function(devinfo, insn, function); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, src1); + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_src1(p, insn, src1); } /** @@ -2196,13 +2196,13 @@ void gfx6_math(struct brw_codegen *p, * stateless dataport messages. */ unsigned -brw_scratch_surface_idx(const struct brw_codegen *p) +elk_scratch_surface_idx(const struct elk_codegen *p) { /* The scratch space is thread-local so IA coherency is unnecessary. */ if (p->devinfo->ver >= 8) return GFX8_BTI_STATELESS_NON_COHERENT; else - return BRW_BTI_STATELESS; + return ELK_BTI_STATELESS; } /** @@ -2212,8 +2212,8 @@ brw_scratch_surface_idx(const struct brw_codegen *p) * The offset must be aligned to oword size (16 bytes). Used for * register spilling. */ -void brw_oword_block_write_scratch(struct brw_codegen *p, - struct brw_reg mrf, +void elk_oword_block_write_scratch(struct elk_codegen *p, + struct elk_reg mrf, int num_regs, unsigned offset) { @@ -2221,14 +2221,14 @@ void brw_oword_block_write_scratch(struct brw_codegen *p, const unsigned target_cache = (devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE : devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE : - BRW_SFID_DATAPORT_WRITE); - const struct tgl_swsb swsb = brw_get_default_swsb(p); + ELK_SFID_DATAPORT_WRITE); + const struct tgl_swsb swsb = elk_get_default_swsb(p); uint32_t msg_type; if (devinfo->ver >= 6) offset /= 16; - mrf = retype(mrf, BRW_REGISTER_TYPE_UD); + mrf = retype(mrf, ELK_REGISTER_TYPE_UD); const unsigned mlen = 1 + num_regs; @@ -2238,43 +2238,43 @@ void brw_oword_block_write_scratch(struct brw_codegen *p, * reg. */ { - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); - brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + elk_MOV(p, mrf, retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); /* set message header global offset field (reg 0, element 2) */ - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, - retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_MOV(p, + retype(elk_vec1_reg(ELK_MESSAGE_REGISTER_FILE, mrf.nr, - 2), BRW_REGISTER_TYPE_UD), - brw_imm_ud(offset)); + 2), ELK_REGISTER_TYPE_UD), + elk_imm_ud(offset)); - brw_pop_insn_state(p); - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + elk_pop_insn_state(p); + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); } { - struct brw_reg dest; - brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); + struct elk_reg dest; + elk_inst *insn = next_insn(p, ELK_OPCODE_SEND); int send_commit_msg; - struct brw_reg src_header = retype(brw_vec8_grf(0, 0), - BRW_REGISTER_TYPE_UW); + struct elk_reg src_header = retype(elk_vec8_grf(0, 0), + ELK_REGISTER_TYPE_UW); - brw_inst_set_sfid(devinfo, insn, target_cache); - brw_inst_set_compression(devinfo, insn, false); + elk_inst_set_sfid(devinfo, insn, target_cache); + elk_inst_set_compression(devinfo, insn, false); - if (brw_inst_exec_size(devinfo, insn) >= 16) + if (elk_inst_exec_size(devinfo, insn) >= 16) src_header = vec16(src_header); - assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE); + assert(elk_inst_pred_control(devinfo, insn) == ELK_PREDICATE_NONE); if (devinfo->ver < 6) - brw_inst_set_base_mrf(devinfo, insn, mrf.nr); + elk_inst_set_base_mrf(devinfo, insn, mrf.nr); /* Until gfx6, writes followed by reads from the same location * are not guaranteed to be ordered unless write_commit is set. @@ -2287,29 +2287,29 @@ void brw_oword_block_write_scratch(struct brw_codegen *p, * spilling within a thread. */ if (devinfo->ver >= 6) { - dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW); + dest = retype(vec16(elk_null_reg()), ELK_REGISTER_TYPE_UW); send_commit_msg = 0; } else { dest = src_header; send_commit_msg = 1; } - brw_set_dest(p, insn, dest); + elk_set_dest(p, insn, dest); if (devinfo->ver >= 6) { - brw_set_src0(p, insn, mrf); + elk_set_src0(p, insn, mrf); } else { - brw_set_src0(p, insn, brw_null_reg()); + elk_set_src0(p, insn, elk_null_reg()); } if (devinfo->ver >= 6) msg_type = GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE; else - msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE; + msg_type = ELK_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE; - brw_set_desc(p, insn, - brw_message_desc(devinfo, mlen, send_commit_msg, true) | - brw_dp_write_desc(devinfo, brw_scratch_surface_idx(p), - BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_regs * 8), + elk_set_desc(p, insn, + elk_message_desc(devinfo, mlen, send_commit_msg, true) | + elk_dp_write_desc(devinfo, elk_scratch_surface_idx(p), + ELK_DATAPORT_OWORD_BLOCK_DWORDS(num_regs * 8), msg_type, send_commit_msg)); } } @@ -2323,14 +2323,14 @@ void brw_oword_block_write_scratch(struct brw_codegen *p, * spilling. */ void -brw_oword_block_read_scratch(struct brw_codegen *p, - struct brw_reg dest, - struct brw_reg mrf, +elk_oword_block_read_scratch(struct elk_codegen *p, + struct elk_reg dest, + struct elk_reg mrf, int num_regs, unsigned offset) { const struct intel_device_info *devinfo = p->devinfo; - const struct tgl_swsb swsb = brw_get_default_swsb(p); + const struct tgl_swsb swsb = elk_get_default_swsb(p); if (devinfo->ver >= 6) offset /= 16; @@ -2343,75 +2343,75 @@ brw_oword_block_read_scratch(struct brw_codegen *p, * the MRF registers and source for the final FB write are both fixed * and may overlap. */ - mrf = retype(dest, BRW_REGISTER_TYPE_UD); + mrf = retype(dest, ELK_REGISTER_TYPE_UD); } else { - mrf = retype(mrf, BRW_REGISTER_TYPE_UD); + mrf = retype(mrf, ELK_REGISTER_TYPE_UD); } - dest = retype(dest, BRW_REGISTER_TYPE_UW); + dest = retype(dest, ELK_REGISTER_TYPE_UW); const unsigned rlen = num_regs; const unsigned target_cache = (devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE : devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE : - BRW_SFID_DATAPORT_READ); + ELK_SFID_DATAPORT_READ); { - brw_push_insn_state(p); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); - brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + elk_MOV(p, mrf, retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); /* set message header global offset field (reg 0, element 2) */ - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, get_element_ud(mrf, 2), brw_imm_ud(offset)); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_MOV(p, get_element_ud(mrf, 2), elk_imm_ud(offset)); - brw_pop_insn_state(p); - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + elk_pop_insn_state(p); + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); } { - brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); + elk_inst *insn = next_insn(p, ELK_OPCODE_SEND); - brw_inst_set_sfid(devinfo, insn, target_cache); - assert(brw_inst_pred_control(devinfo, insn) == 0); - brw_inst_set_compression(devinfo, insn, false); + elk_inst_set_sfid(devinfo, insn, target_cache); + assert(elk_inst_pred_control(devinfo, insn) == 0); + elk_inst_set_compression(devinfo, insn, false); - brw_set_dest(p, insn, dest); /* UW? */ + elk_set_dest(p, insn, dest); /* UW? */ if (devinfo->ver >= 6) { - brw_set_src0(p, insn, mrf); + elk_set_src0(p, insn, mrf); } else { - brw_set_src0(p, insn, brw_null_reg()); - brw_inst_set_base_mrf(devinfo, insn, mrf.nr); + elk_set_src0(p, insn, elk_null_reg()); + elk_inst_set_base_mrf(devinfo, insn, mrf.nr); } - brw_set_desc(p, insn, - brw_message_desc(devinfo, 1, rlen, true) | - brw_dp_read_desc(devinfo, brw_scratch_surface_idx(p), - BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_regs * 8), - BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, - BRW_DATAPORT_READ_TARGET_RENDER_CACHE)); + elk_set_desc(p, insn, + elk_message_desc(devinfo, 1, rlen, true) | + elk_dp_read_desc(devinfo, elk_scratch_surface_idx(p), + ELK_DATAPORT_OWORD_BLOCK_DWORDS(num_regs * 8), + ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, + ELK_DATAPORT_READ_TARGET_RENDER_CACHE)); } } void -gfx7_block_read_scratch(struct brw_codegen *p, - struct brw_reg dest, +elk_gfx7_block_read_scratch(struct elk_codegen *p, + struct elk_reg dest, int num_regs, unsigned offset) { - brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); - assert(brw_inst_pred_control(p->devinfo, insn) == BRW_PREDICATE_NONE); + elk_inst *insn = next_insn(p, ELK_OPCODE_SEND); + assert(elk_inst_pred_control(p->devinfo, insn) == ELK_PREDICATE_NONE); - brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UW)); + elk_set_dest(p, insn, retype(dest, ELK_REGISTER_TYPE_UW)); /* The HW requires that the header is present; this is to get the g0.5 * scratch offset. */ - brw_set_src0(p, insn, brw_vec8_grf(0, 0)); + elk_set_src0(p, insn, elk_vec8_grf(0, 0)); /* According to the docs, offset is "A 12-bit HWord offset into the memory * Immediate Memory buffer as specified by binding table 0xFF." An HWORD @@ -2436,77 +2436,77 @@ gfx7_block_read_scratch(struct brw_codegen *p, * Location (in buffer) should be a multiple of 16. * Used for fetching shader constants. */ -void brw_oword_block_read(struct brw_codegen *p, - struct brw_reg dest, - struct brw_reg mrf, +void elk_oword_block_read(struct elk_codegen *p, + struct elk_reg dest, + struct elk_reg mrf, uint32_t offset, uint32_t bind_table_index) { const struct intel_device_info *devinfo = p->devinfo; const unsigned target_cache = (devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_CONSTANT_CACHE : - BRW_SFID_DATAPORT_READ); - const unsigned exec_size = 1 << brw_get_default_exec_size(p); - const struct tgl_swsb swsb = brw_get_default_swsb(p); + ELK_SFID_DATAPORT_READ); + const unsigned exec_size = 1 << elk_get_default_exec_size(p); + const struct tgl_swsb swsb = elk_get_default_swsb(p); /* On newer hardware, offset is in units of owords. */ if (devinfo->ver >= 6) offset /= 16; - mrf = retype(mrf, BRW_REGISTER_TYPE_UD); + mrf = retype(mrf, ELK_REGISTER_TYPE_UD); - brw_push_insn_state(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); - brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_MOV(p, mrf, retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); /* set message header global offset field (reg 0, element 2) */ - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, - retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_MOV(p, + retype(elk_vec1_reg(ELK_MESSAGE_REGISTER_FILE, mrf.nr, - 2), BRW_REGISTER_TYPE_UD), - brw_imm_ud(offset)); - brw_pop_insn_state(p); + 2), ELK_REGISTER_TYPE_UD), + elk_imm_ud(offset)); + elk_pop_insn_state(p); - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); - brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); + elk_inst *insn = next_insn(p, ELK_OPCODE_SEND); - brw_inst_set_sfid(devinfo, insn, target_cache); + elk_inst_set_sfid(devinfo, insn, target_cache); /* cast dest to a uword[8] vector */ - dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW); + dest = retype(vec8(dest), ELK_REGISTER_TYPE_UW); - brw_set_dest(p, insn, dest); + elk_set_dest(p, insn, dest); if (devinfo->ver >= 6) { - brw_set_src0(p, insn, mrf); + elk_set_src0(p, insn, mrf); } else { - brw_set_src0(p, insn, brw_null_reg()); - brw_inst_set_base_mrf(devinfo, insn, mrf.nr); + elk_set_src0(p, insn, elk_null_reg()); + elk_inst_set_base_mrf(devinfo, insn, mrf.nr); } - brw_set_desc(p, insn, - brw_message_desc(devinfo, 1, DIV_ROUND_UP(exec_size, 8), true) | - brw_dp_read_desc(devinfo, bind_table_index, - BRW_DATAPORT_OWORD_BLOCK_DWORDS(exec_size), - BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, - BRW_DATAPORT_READ_TARGET_DATA_CACHE)); + elk_set_desc(p, insn, + elk_message_desc(devinfo, 1, DIV_ROUND_UP(exec_size, 8), true) | + elk_dp_read_desc(devinfo, bind_table_index, + ELK_DATAPORT_OWORD_BLOCK_DWORDS(exec_size), + ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, + ELK_DATAPORT_READ_TARGET_DATA_CACHE)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } -brw_inst * -brw_fb_WRITE(struct brw_codegen *p, - struct brw_reg payload, - struct brw_reg implied_header, +elk_inst * +elk_fb_WRITE(struct elk_codegen *p, + struct elk_reg payload, + struct elk_reg implied_header, unsigned msg_control, unsigned binding_table_index, unsigned msg_length, @@ -2518,49 +2518,49 @@ brw_fb_WRITE(struct brw_codegen *p, const struct intel_device_info *devinfo = p->devinfo; const unsigned target_cache = (devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE : - BRW_SFID_DATAPORT_WRITE); - brw_inst *insn; - struct brw_reg dest, src0; + ELK_SFID_DATAPORT_WRITE); + elk_inst *insn; + struct elk_reg dest, src0; - if (brw_get_default_exec_size(p) >= BRW_EXECUTE_16) - dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW); + if (elk_get_default_exec_size(p) >= ELK_EXECUTE_16) + dest = retype(vec16(elk_null_reg()), ELK_REGISTER_TYPE_UW); else - dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW); + dest = retype(vec8(elk_null_reg()), ELK_REGISTER_TYPE_UW); if (devinfo->ver >= 6) { - insn = next_insn(p, BRW_OPCODE_SENDC); + insn = next_insn(p, ELK_OPCODE_SENDC); } else { - insn = next_insn(p, BRW_OPCODE_SEND); + insn = next_insn(p, ELK_OPCODE_SEND); } - brw_inst_set_sfid(devinfo, insn, target_cache); - brw_inst_set_compression(devinfo, insn, false); + elk_inst_set_sfid(devinfo, insn, target_cache); + elk_inst_set_compression(devinfo, insn, false); if (devinfo->ver >= 6) { /* headerless version, just submit color payload */ src0 = payload; } else { - assert(payload.file == BRW_MESSAGE_REGISTER_FILE); - brw_inst_set_base_mrf(devinfo, insn, payload.nr); + assert(payload.file == ELK_MESSAGE_REGISTER_FILE); + elk_inst_set_base_mrf(devinfo, insn, payload.nr); src0 = implied_header; } - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_desc(p, insn, - brw_message_desc(devinfo, msg_length, response_length, + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_desc(p, insn, + elk_message_desc(devinfo, msg_length, response_length, header_present) | - brw_fb_write_desc(devinfo, binding_table_index, msg_control, + elk_fb_write_desc(devinfo, binding_table_index, msg_control, last_render_target, false /* coarse_write */)); - brw_inst_set_eot(devinfo, insn, eot); + elk_inst_set_eot(devinfo, insn, eot); return insn; } -brw_inst * -gfx9_fb_READ(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg payload, +elk_inst * +elk_gfx9_fb_READ(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg payload, unsigned binding_table_index, unsigned msg_length, unsigned response_length, @@ -2568,17 +2568,17 @@ gfx9_fb_READ(struct brw_codegen *p, { const struct intel_device_info *devinfo = p->devinfo; assert(devinfo->ver >= 9); - brw_inst *insn = next_insn(p, BRW_OPCODE_SENDC); + elk_inst *insn = next_insn(p, ELK_OPCODE_SENDC); - brw_inst_set_sfid(devinfo, insn, GFX6_SFID_DATAPORT_RENDER_CACHE); - brw_set_dest(p, insn, dst); - brw_set_src0(p, insn, payload); - brw_set_desc( + elk_inst_set_sfid(devinfo, insn, GFX6_SFID_DATAPORT_RENDER_CACHE); + elk_set_dest(p, insn, dst); + elk_set_src0(p, insn, payload); + elk_set_desc( p, insn, - brw_message_desc(devinfo, msg_length, response_length, true) | - brw_fb_read_desc(devinfo, binding_table_index, 0 /* msg_control */, - 1 << brw_get_default_exec_size(p), per_sample)); - brw_inst_set_rt_slot_group(devinfo, insn, brw_get_default_group(p) / 16); + elk_message_desc(devinfo, msg_length, response_length, true) | + elk_fb_read_desc(devinfo, binding_table_index, 0 /* msg_control */, + 1 << elk_get_default_exec_size(p), per_sample)); + elk_inst_set_rt_slot_group(devinfo, insn, elk_get_default_group(p) / 16); return insn; } @@ -2588,10 +2588,10 @@ gfx9_fb_READ(struct brw_codegen *p, * Note: the msg_type plus msg_length values determine exactly what kind * of sampling operation is performed. See volume 4, page 161 of docs. */ -void brw_SAMPLE(struct brw_codegen *p, - struct brw_reg dest, +void elk_SAMPLE(struct elk_codegen *p, + struct elk_reg dest, unsigned msg_reg_nr, - struct brw_reg src0, + struct elk_reg src0, unsigned binding_table_index, unsigned sampler, unsigned msg_type, @@ -2602,14 +2602,14 @@ void brw_SAMPLE(struct brw_codegen *p, unsigned return_format) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; if (msg_reg_nr != -1) - gfx6_resolve_implied_move(p, &src0, msg_reg_nr); + elk_gfx6_resolve_implied_move(p, &src0, msg_reg_nr); - insn = next_insn(p, BRW_OPCODE_SEND); - brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER); - brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE); /* XXX */ + insn = next_insn(p, ELK_OPCODE_SEND); + elk_inst_set_sfid(devinfo, insn, ELK_SFID_SAMPLER); + elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NONE); /* XXX */ /* From the 965 PRM (volume 4, part 1, section 14.2.41): * @@ -2621,28 +2621,28 @@ void brw_SAMPLE(struct brw_codegen *p, * No similar wording is found in later PRMs, but there are examples * utilizing send with SecHalf. More importantly, SIMD8 sampler messages * are allowed in SIMD16 mode and they could not work without SecHalf. For - * these reasons, we allow BRW_COMPRESSION_2NDHALF here. + * these reasons, we allow ELK_COMPRESSION_2NDHALF here. */ - brw_inst_set_compression(devinfo, insn, false); + elk_inst_set_compression(devinfo, insn, false); if (devinfo->ver < 6) - brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr); + elk_inst_set_base_mrf(devinfo, insn, msg_reg_nr); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_desc(p, insn, - brw_message_desc(devinfo, msg_length, response_length, + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_desc(p, insn, + elk_message_desc(devinfo, msg_length, response_length, header_present) | - brw_sampler_desc(devinfo, binding_table_index, sampler, + elk_sampler_desc(devinfo, binding_table_index, sampler, msg_type, simd_mode, return_format)); } /* Adjust the message header's sampler state pointer to * select the correct group of 16 samplers. */ -void brw_adjust_sampler_state_pointer(struct brw_codegen *p, - struct brw_reg header, - struct brw_reg sampler_index) +void elk_adjust_sampler_state_pointer(struct elk_codegen *p, + struct elk_reg header, + struct elk_reg sampler_index) { /* The "Sampler Index" field can only store values between 0 and 15. * However, we can add an offset to the "Sampler State Pointer" @@ -2655,16 +2655,16 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p, const struct intel_device_info *devinfo = p->devinfo; - if (sampler_index.file == BRW_IMMEDIATE_VALUE) { + if (sampler_index.file == ELK_IMMEDIATE_VALUE) { const int sampler_state_size = 16; /* 16 bytes */ uint32_t sampler = sampler_index.ud; if (sampler >= 16) { assert(devinfo->verx10 >= 75); - brw_ADD(p, + elk_ADD(p, get_element_ud(header, 3), - get_element_ud(brw_vec8_grf(0, 0), 3), - brw_imm_ud(16 * (sampler / 16) * sampler_state_size)); + get_element_ud(elk_vec8_grf(0, 0), 3), + elk_imm_ud(16 * (sampler / 16) * sampler_state_size)); } } else { /* Non-const sampler array indexing case */ @@ -2672,17 +2672,17 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p, return; } - struct brw_reg temp = get_element_ud(header, 3); + struct elk_reg temp = get_element_ud(header, 3); - brw_push_insn_state(p); - brw_AND(p, temp, get_element_ud(sampler_index, 0), brw_imm_ud(0x0f0)); - brw_set_default_swsb(p, tgl_swsb_regdist(1)); - brw_SHL(p, temp, temp, brw_imm_ud(4)); - brw_ADD(p, + elk_push_insn_state(p); + elk_AND(p, temp, get_element_ud(sampler_index, 0), elk_imm_ud(0x0f0)); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_SHL(p, temp, temp, elk_imm_ud(4)); + elk_ADD(p, get_element_ud(header, 3), - get_element_ud(brw_vec8_grf(0, 0), 3), + get_element_ud(elk_vec8_grf(0, 0), 3), temp); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } } @@ -2690,46 +2690,46 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p, * using bitmasks and macros for this, in the old style. Or perhaps * just having the caller instantiate the fields in dword3 itself. */ -void brw_urb_WRITE(struct brw_codegen *p, - struct brw_reg dest, +void elk_urb_WRITE(struct elk_codegen *p, + struct elk_reg dest, unsigned msg_reg_nr, - struct brw_reg src0, - enum brw_urb_write_flags flags, + struct elk_reg src0, + enum elk_urb_write_flags flags, unsigned msg_length, unsigned response_length, unsigned offset, unsigned swizzle) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; - gfx6_resolve_implied_move(p, &src0, msg_reg_nr); + elk_gfx6_resolve_implied_move(p, &src0, msg_reg_nr); - if (devinfo->ver >= 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) { + if (devinfo->ver >= 7 && !(flags & ELK_URB_WRITE_USE_CHANNEL_MASKS)) { /* Enable Channel Masks in the URB_WRITE_HWORD message header */ - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5), - BRW_REGISTER_TYPE_UD), - retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), - brw_imm_ud(0xff00)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_OR(p, retype(elk_vec1_reg(ELK_MESSAGE_REGISTER_FILE, msg_reg_nr, 5), + ELK_REGISTER_TYPE_UD), + retype(elk_vec1_grf(0, 5), ELK_REGISTER_TYPE_UD), + elk_imm_ud(0xff00)); + elk_pop_insn_state(p); } - insn = next_insn(p, BRW_OPCODE_SEND); + insn = next_insn(p, ELK_OPCODE_SEND); - assert(msg_length < BRW_MAX_MRF(devinfo->ver)); + assert(msg_length < ELK_MAX_MRF(devinfo->ver)); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, brw_imm_d(0)); + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_src1(p, insn, elk_imm_d(0)); if (devinfo->ver < 6) - brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr); + elk_inst_set_base_mrf(devinfo, insn, msg_reg_nr); - brw_set_urb_message(p, + elk_set_urb_message(p, insn, flags, msg_length, @@ -2739,108 +2739,108 @@ void brw_urb_WRITE(struct brw_codegen *p, } void -brw_send_indirect_message(struct brw_codegen *p, +elk_send_indirect_message(struct elk_codegen *p, unsigned sfid, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg desc, + struct elk_reg dst, + struct elk_reg payload, + struct elk_reg desc, unsigned desc_imm, bool eot) { const struct intel_device_info *devinfo = p->devinfo; - struct brw_inst *send; + struct elk_inst *send; - dst = retype(dst, BRW_REGISTER_TYPE_UW); + dst = retype(dst, ELK_REGISTER_TYPE_UW); - assert(desc.type == BRW_REGISTER_TYPE_UD); + assert(desc.type == ELK_REGISTER_TYPE_UD); - if (desc.file == BRW_IMMEDIATE_VALUE) { - send = next_insn(p, BRW_OPCODE_SEND); - brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD)); - brw_set_desc(p, send, desc.ud | desc_imm); + if (desc.file == ELK_IMMEDIATE_VALUE) { + send = next_insn(p, ELK_OPCODE_SEND); + elk_set_src0(p, send, retype(payload, ELK_REGISTER_TYPE_UD)); + elk_set_desc(p, send, desc.ud | desc_imm); } else { - const struct tgl_swsb swsb = brw_get_default_swsb(p); - struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD); + const struct tgl_swsb swsb = elk_get_default_swsb(p); + struct elk_reg addr = retype(elk_address_reg(0), ELK_REGISTER_TYPE_UD); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); /* Load the indirect descriptor to an address register using OR so the * caller can specify additional descriptor bits with the desc_imm * immediate. */ - brw_OR(p, addr, desc, brw_imm_ud(desc_imm)); + elk_OR(p, addr, desc, elk_imm_ud(desc_imm)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); - send = next_insn(p, BRW_OPCODE_SEND); - brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD)); + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + send = next_insn(p, ELK_OPCODE_SEND); + elk_set_src0(p, send, retype(payload, ELK_REGISTER_TYPE_UD)); if (devinfo->ver >= 12) - brw_inst_set_send_sel_reg32_desc(devinfo, send, true); + elk_inst_set_send_sel_reg32_desc(devinfo, send, true); else - brw_set_src1(p, send, addr); + elk_set_src1(p, send, addr); } - brw_set_dest(p, send, dst); - brw_inst_set_sfid(devinfo, send, sfid); - brw_inst_set_eot(devinfo, send, eot); + elk_set_dest(p, send, dst); + elk_inst_set_sfid(devinfo, send, sfid); + elk_inst_set_eot(devinfo, send, eot); } void -brw_send_indirect_split_message(struct brw_codegen *p, +elk_send_indirect_split_message(struct elk_codegen *p, unsigned sfid, - struct brw_reg dst, - struct brw_reg payload0, - struct brw_reg payload1, - struct brw_reg desc, + struct elk_reg dst, + struct elk_reg payload0, + struct elk_reg payload1, + struct elk_reg desc, unsigned desc_imm, - struct brw_reg ex_desc, + struct elk_reg ex_desc, unsigned ex_desc_imm, bool ex_desc_scratch, bool ex_bso, bool eot) { const struct intel_device_info *devinfo = p->devinfo; - struct brw_inst *send; + struct elk_inst *send; - dst = retype(dst, BRW_REGISTER_TYPE_UW); + dst = retype(dst, ELK_REGISTER_TYPE_UW); - assert(desc.type == BRW_REGISTER_TYPE_UD); + assert(desc.type == ELK_REGISTER_TYPE_UD); - if (desc.file == BRW_IMMEDIATE_VALUE) { + if (desc.file == ELK_IMMEDIATE_VALUE) { desc.ud |= desc_imm; } else { - const struct tgl_swsb swsb = brw_get_default_swsb(p); - struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD); + const struct tgl_swsb swsb = elk_get_default_swsb(p); + struct elk_reg addr = retype(elk_address_reg(0), ELK_REGISTER_TYPE_UD); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); /* Load the indirect descriptor to an address register using OR so the * caller can specify additional descriptor bits with the desc_imm * immediate. */ - brw_OR(p, addr, desc, brw_imm_ud(desc_imm)); + elk_OR(p, addr, desc, elk_imm_ud(desc_imm)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); desc = addr; - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); } - if (ex_desc.file == BRW_IMMEDIATE_VALUE && + if (ex_desc.file == ELK_IMMEDIATE_VALUE && !ex_desc_scratch && (devinfo->ver >= 12 || ((ex_desc.ud | ex_desc_imm) & INTEL_MASK(15, 12)) == 0)) { @@ -2852,16 +2852,16 @@ brw_send_indirect_split_message(struct brw_codegen *p, assert(!ex_bso); ex_desc.ud |= ex_desc_imm; } else { - const struct tgl_swsb swsb = brw_get_default_swsb(p); - struct brw_reg addr = retype(brw_address_reg(2), BRW_REGISTER_TYPE_UD); + const struct tgl_swsb swsb = elk_get_default_swsb(p); + struct elk_reg addr = retype(elk_address_reg(2), ELK_REGISTER_TYPE_UD); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); /* Load the indirect extended descriptor to an address register using OR * so the caller can specify additional descriptor bits with the @@ -2880,50 +2880,50 @@ brw_send_indirect_split_message(struct brw_codegen *p, * the extended descriptor. */ assert(devinfo->verx10 >= 125); - brw_AND(p, addr, - retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(31, 10))); - brw_OR(p, addr, addr, brw_imm_ud(imm_part)); - } else if (ex_desc.file == BRW_IMMEDIATE_VALUE) { + elk_AND(p, addr, + retype(elk_vec1_grf(0, 5), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(31, 10))); + elk_OR(p, addr, addr, elk_imm_ud(imm_part)); + } else if (ex_desc.file == ELK_IMMEDIATE_VALUE) { /* ex_desc bits 15:12 don't exist in the instruction encoding prior * to Gfx12, so we may have fallen back to an indirect extended * descriptor. */ - brw_MOV(p, addr, brw_imm_ud(ex_desc.ud | imm_part)); + elk_MOV(p, addr, elk_imm_ud(ex_desc.ud | imm_part)); } else { - brw_OR(p, addr, ex_desc, brw_imm_ud(imm_part)); + elk_OR(p, addr, ex_desc, elk_imm_ud(imm_part)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); ex_desc = addr; - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); } - send = next_insn(p, devinfo->ver >= 12 ? BRW_OPCODE_SEND : BRW_OPCODE_SENDS); - brw_set_dest(p, send, dst); - brw_set_src0(p, send, retype(payload0, BRW_REGISTER_TYPE_UD)); - brw_set_src1(p, send, retype(payload1, BRW_REGISTER_TYPE_UD)); + send = next_insn(p, devinfo->ver >= 12 ? ELK_OPCODE_SEND : ELK_OPCODE_SENDS); + elk_set_dest(p, send, dst); + elk_set_src0(p, send, retype(payload0, ELK_REGISTER_TYPE_UD)); + elk_set_src1(p, send, retype(payload1, ELK_REGISTER_TYPE_UD)); - if (desc.file == BRW_IMMEDIATE_VALUE) { - brw_inst_set_send_sel_reg32_desc(devinfo, send, 0); - brw_inst_set_send_desc(devinfo, send, desc.ud); + if (desc.file == ELK_IMMEDIATE_VALUE) { + elk_inst_set_send_sel_reg32_desc(devinfo, send, 0); + elk_inst_set_send_desc(devinfo, send, desc.ud); } else { - assert(desc.file == BRW_ARCHITECTURE_REGISTER_FILE); - assert(desc.nr == BRW_ARF_ADDRESS); + assert(desc.file == ELK_ARCHITECTURE_REGISTER_FILE); + assert(desc.nr == ELK_ARF_ADDRESS); assert(desc.subnr == 0); - brw_inst_set_send_sel_reg32_desc(devinfo, send, 1); + elk_inst_set_send_sel_reg32_desc(devinfo, send, 1); } - if (ex_desc.file == BRW_IMMEDIATE_VALUE) { - brw_inst_set_send_sel_reg32_ex_desc(devinfo, send, 0); - brw_inst_set_sends_ex_desc(devinfo, send, ex_desc.ud); + if (ex_desc.file == ELK_IMMEDIATE_VALUE) { + elk_inst_set_send_sel_reg32_ex_desc(devinfo, send, 0); + elk_inst_set_sends_ex_desc(devinfo, send, ex_desc.ud); } else { - assert(ex_desc.file == BRW_ARCHITECTURE_REGISTER_FILE); - assert(ex_desc.nr == BRW_ARF_ADDRESS); + assert(ex_desc.file == ELK_ARCHITECTURE_REGISTER_FILE); + assert(ex_desc.nr == ELK_ARF_ADDRESS); assert((ex_desc.subnr & 0x3) == 0); - brw_inst_set_send_sel_reg32_ex_desc(devinfo, send, 1); - brw_inst_set_send_ex_desc_ia_subreg_nr(devinfo, send, phys_subnr(devinfo, ex_desc) >> 2); + elk_inst_set_send_sel_reg32_ex_desc(devinfo, send, 1); + elk_inst_set_send_ex_desc_ia_subreg_nr(devinfo, send, phys_subnr(devinfo, ex_desc) >> 2); } if (ex_bso) { @@ -2933,64 +2933,64 @@ brw_send_indirect_split_message(struct brw_codegen *p, * BSpec 56890 */ if (devinfo->ver < 20 || sfid != GFX12_SFID_UGM) - brw_inst_set_send_ex_bso(devinfo, send, true); - brw_inst_set_send_src1_len(devinfo, send, GET_BITS(ex_desc_imm, 10, 6)); + elk_inst_set_send_ex_bso(devinfo, send, true); + elk_inst_set_send_src1_len(devinfo, send, GET_BITS(ex_desc_imm, 10, 6)); } - brw_inst_set_sfid(devinfo, send, sfid); - brw_inst_set_eot(devinfo, send, eot); + elk_inst_set_sfid(devinfo, send, sfid); + elk_inst_set_eot(devinfo, send, eot); } static void -brw_send_indirect_surface_message(struct brw_codegen *p, +elk_send_indirect_surface_message(struct elk_codegen *p, unsigned sfid, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg surface, + struct elk_reg dst, + struct elk_reg payload, + struct elk_reg surface, unsigned desc_imm) { - if (surface.file != BRW_IMMEDIATE_VALUE) { - const struct tgl_swsb swsb = brw_get_default_swsb(p); - struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD); + if (surface.file != ELK_IMMEDIATE_VALUE) { + const struct tgl_swsb swsb = elk_get_default_swsb(p); + struct elk_reg addr = retype(elk_address_reg(0), ELK_REGISTER_TYPE_UD); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); /* Mask out invalid bits from the surface index to avoid hangs e.g. when * some surface array is accessed out of bounds. */ - brw_AND(p, addr, - suboffset(vec1(retype(surface, BRW_REGISTER_TYPE_UD)), - BRW_GET_SWZ(surface.swizzle, 0)), - brw_imm_ud(0xff)); + elk_AND(p, addr, + suboffset(vec1(retype(surface, ELK_REGISTER_TYPE_UD)), + ELK_GET_SWZ(surface.swizzle, 0)), + elk_imm_ud(0xff)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); surface = addr; - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); } - brw_send_indirect_message(p, sfid, dst, payload, surface, desc_imm, false); + elk_send_indirect_message(p, sfid, dst, payload, surface, desc_imm, false); } static bool while_jumps_before_offset(const struct intel_device_info *devinfo, - brw_inst *insn, int while_offset, int start_offset) + elk_inst *insn, int while_offset, int start_offset) { - int scale = 16 / brw_jump_scale(devinfo); - int jip = devinfo->ver == 6 ? brw_inst_gfx6_jump_count(devinfo, insn) - : brw_inst_jip(devinfo, insn); + int scale = 16 / elk_jump_scale(devinfo); + int jip = devinfo->ver == 6 ? elk_inst_gfx6_jump_count(devinfo, insn) + : elk_inst_jip(devinfo, insn); assert(jip < 0); return while_offset + jip * scale <= start_offset; } static int -brw_find_next_block_end(struct brw_codegen *p, int start_offset) +elk_find_next_block_end(struct elk_codegen *p, int start_offset) { int offset; void *store = p->store; @@ -3001,26 +3001,26 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset) for (offset = next_offset(devinfo, store, start_offset); offset < p->next_insn_offset; offset = next_offset(devinfo, store, offset)) { - brw_inst *insn = store + offset; + elk_inst *insn = store + offset; - switch (brw_inst_opcode(p->isa, insn)) { - case BRW_OPCODE_IF: + switch (elk_inst_opcode(p->isa, insn)) { + case ELK_OPCODE_IF: depth++; break; - case BRW_OPCODE_ENDIF: + case ELK_OPCODE_ENDIF: if (depth == 0) return offset; depth--; break; - case BRW_OPCODE_WHILE: + case ELK_OPCODE_WHILE: /* If the while doesn't jump before our instruction, it's the end * of a sibling do...while loop. Ignore it. */ if (!while_jumps_before_offset(devinfo, insn, offset, start_offset)) continue; FALLTHROUGH; - case BRW_OPCODE_ELSE: - case BRW_OPCODE_HALT: + case ELK_OPCODE_ELSE: + case ELK_OPCODE_HALT: if (depth == 0) return offset; break; @@ -3037,7 +3037,7 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset) * instruction. */ static int -brw_find_loop_end(struct brw_codegen *p, int start_offset) +elk_find_loop_end(struct elk_codegen *p, int start_offset) { const struct intel_device_info *devinfo = p->devinfo; int offset; @@ -3051,9 +3051,9 @@ brw_find_loop_end(struct brw_codegen *p, int start_offset) for (offset = next_offset(devinfo, store, start_offset); offset < p->next_insn_offset; offset = next_offset(devinfo, store, offset)) { - brw_inst *insn = store + offset; + elk_inst *insn = store + offset; - if (brw_inst_opcode(p->isa, insn) == BRW_OPCODE_WHILE) { + if (elk_inst_opcode(p->isa, insn) == ELK_OPCODE_WHILE) { if (while_jumps_before_offset(devinfo, insn, offset, start_offset)) return offset; } @@ -3066,11 +3066,11 @@ brw_find_loop_end(struct brw_codegen *p, int start_offset) * BREAK, CONT, and HALT instructions to their correct locations. */ void -brw_set_uip_jip(struct brw_codegen *p, int start_offset) +elk_set_uip_jip(struct elk_codegen *p, int start_offset) { const struct intel_device_info *devinfo = p->devinfo; int offset; - int br = brw_jump_scale(devinfo); + int br = elk_jump_scale(devinfo); int scale = 16 / br; void *store = p->store; @@ -3078,45 +3078,45 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset) return; for (offset = start_offset; offset < p->next_insn_offset; offset += 16) { - brw_inst *insn = store + offset; - assert(brw_inst_cmpt_control(devinfo, insn) == 0); + elk_inst *insn = store + offset; + assert(elk_inst_cmpt_control(devinfo, insn) == 0); - switch (brw_inst_opcode(p->isa, insn)) { - case BRW_OPCODE_BREAK: { - int block_end_offset = brw_find_next_block_end(p, offset); + switch (elk_inst_opcode(p->isa, insn)) { + case ELK_OPCODE_BREAK: { + int block_end_offset = elk_find_next_block_end(p, offset); assert(block_end_offset != 0); - brw_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale); + elk_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale); /* Gfx7 UIP points to WHILE; Gfx6 points just after it */ - brw_inst_set_uip(devinfo, insn, - (brw_find_loop_end(p, offset) - offset + + elk_inst_set_uip(devinfo, insn, + (elk_find_loop_end(p, offset) - offset + (devinfo->ver == 6 ? 16 : 0)) / scale); break; } - case BRW_OPCODE_CONTINUE: { - int block_end_offset = brw_find_next_block_end(p, offset); + case ELK_OPCODE_CONTINUE: { + int block_end_offset = elk_find_next_block_end(p, offset); assert(block_end_offset != 0); - brw_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale); - brw_inst_set_uip(devinfo, insn, - (brw_find_loop_end(p, offset) - offset) / scale); + elk_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale); + elk_inst_set_uip(devinfo, insn, + (elk_find_loop_end(p, offset) - offset) / scale); - assert(brw_inst_uip(devinfo, insn) != 0); - assert(brw_inst_jip(devinfo, insn) != 0); + assert(elk_inst_uip(devinfo, insn) != 0); + assert(elk_inst_jip(devinfo, insn) != 0); break; } - case BRW_OPCODE_ENDIF: { - int block_end_offset = brw_find_next_block_end(p, offset); + case ELK_OPCODE_ENDIF: { + int block_end_offset = elk_find_next_block_end(p, offset); int32_t jump = (block_end_offset == 0) ? 1 * br : (block_end_offset - offset) / scale; if (devinfo->ver >= 7) - brw_inst_set_jip(devinfo, insn, jump); + elk_inst_set_jip(devinfo, insn, jump); else - brw_inst_set_gfx6_jump_count(devinfo, insn, jump); + elk_inst_set_gfx6_jump_count(devinfo, insn, jump); break; } - case BRW_OPCODE_HALT: { + case ELK_OPCODE_HALT: { /* From the Sandy Bridge PRM (volume 4, part 2, section 8.3.19): * * "In case of the halt instruction not inside any conditional @@ -3128,14 +3128,14 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset) * The uip will have already been set by whoever set up the * instruction. */ - int block_end_offset = brw_find_next_block_end(p, offset); + int block_end_offset = elk_find_next_block_end(p, offset); if (block_end_offset == 0) { - brw_inst_set_jip(devinfo, insn, brw_inst_uip(devinfo, insn)); + elk_inst_set_jip(devinfo, insn, elk_inst_uip(devinfo, insn)); } else { - brw_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale); + elk_inst_set_jip(devinfo, insn, (block_end_offset - offset) / scale); } - assert(brw_inst_uip(devinfo, insn) != 0); - assert(brw_inst_jip(devinfo, insn) != 0); + assert(elk_inst_uip(devinfo, insn) != 0); + assert(elk_inst_jip(devinfo, insn) != 0); break; } @@ -3145,28 +3145,28 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset) } } -void brw_ff_sync(struct brw_codegen *p, - struct brw_reg dest, +void elk_ff_sync(struct elk_codegen *p, + struct elk_reg dest, unsigned msg_reg_nr, - struct brw_reg src0, + struct elk_reg src0, bool allocate, unsigned response_length, bool eot) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *insn; + elk_inst *insn; - gfx6_resolve_implied_move(p, &src0, msg_reg_nr); + elk_gfx6_resolve_implied_move(p, &src0, msg_reg_nr); - insn = next_insn(p, BRW_OPCODE_SEND); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_src1(p, insn, brw_imm_d(0)); + insn = next_insn(p, ELK_OPCODE_SEND); + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_src1(p, insn, elk_imm_d(0)); if (devinfo->ver < 6) - brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr); + elk_inst_set_base_mrf(devinfo, insn, msg_reg_nr); - brw_set_ff_sync_message(p, + elk_set_ff_sync_message(p, insn, allocate, response_length, @@ -3185,34 +3185,34 @@ void brw_ff_sync(struct brw_codegen *p, * writes are complete by sending the final write as a committed write." */ void -brw_svb_write(struct brw_codegen *p, - struct brw_reg dest, +elk_svb_write(struct elk_codegen *p, + struct elk_reg dest, unsigned msg_reg_nr, - struct brw_reg src0, + struct elk_reg src0, unsigned binding_table_index, bool send_commit_msg) { const struct intel_device_info *devinfo = p->devinfo; assert(devinfo->ver == 6); const unsigned target_cache = GFX6_SFID_DATAPORT_RENDER_CACHE; - brw_inst *insn; + elk_inst *insn; - gfx6_resolve_implied_move(p, &src0, msg_reg_nr); + elk_gfx6_resolve_implied_move(p, &src0, msg_reg_nr); - insn = next_insn(p, BRW_OPCODE_SEND); - brw_inst_set_sfid(devinfo, insn, target_cache); - brw_set_dest(p, insn, dest); - brw_set_src0(p, insn, src0); - brw_set_desc(p, insn, - brw_message_desc(devinfo, 1, send_commit_msg, true) | - brw_dp_write_desc(devinfo, binding_table_index, + insn = next_insn(p, ELK_OPCODE_SEND); + elk_inst_set_sfid(devinfo, insn, target_cache); + elk_set_dest(p, insn, dest); + elk_set_src0(p, insn, src0); + elk_set_desc(p, insn, + elk_message_desc(devinfo, 1, send_commit_msg, true) | + elk_dp_write_desc(devinfo, binding_table_index, 0, /* msg_control: ignored */ GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE, send_commit_msg)); /* send_commit_msg */ } static unsigned -brw_surface_payload_size(unsigned num_channels, +elk_surface_payload_size(unsigned num_channels, unsigned exec_size /**< 0 for SIMD4x2 */) { if (exec_size == 0) @@ -3224,10 +3224,10 @@ brw_surface_payload_size(unsigned num_channels, } void -brw_untyped_atomic(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg surface, +elk_untyped_atomic(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg payload, + struct elk_reg surface, unsigned atomic_op, unsigned msg_length, bool response_expected, @@ -3237,16 +3237,16 @@ brw_untyped_atomic(struct brw_codegen *p, const unsigned sfid = (devinfo->verx10 >= 75 ? HSW_SFID_DATAPORT_DATA_CACHE_1 : GFX7_SFID_DATAPORT_DATA_CACHE); - const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1; + const bool align1 = elk_get_default_access_mode(p) == ELK_ALIGN_1; /* SIMD4x2 untyped atomic instructions only exist on HSW+ */ const bool has_simd4x2 = devinfo->verx10 >= 75; - const unsigned exec_size = align1 ? 1 << brw_get_default_exec_size(p) : + const unsigned exec_size = align1 ? 1 << elk_get_default_exec_size(p) : has_simd4x2 ? 0 : 8; const unsigned response_length = - brw_surface_payload_size(response_expected, exec_size); + elk_surface_payload_size(response_expected, exec_size); const unsigned desc = - brw_message_desc(devinfo, msg_length, response_length, header_present) | - brw_dp_untyped_atomic_desc(devinfo, exec_size, atomic_op, + elk_message_desc(devinfo, msg_length, response_length, header_present) | + elk_dp_untyped_atomic_desc(devinfo, exec_size, atomic_op, response_expected); /* Mask out unused components -- This is especially important in Align16 * mode on generations that don't have native support for SIMD4x2 atomics, @@ -3256,15 +3256,15 @@ brw_untyped_atomic(struct brw_codegen *p, */ const unsigned mask = align1 ? WRITEMASK_XYZW : WRITEMASK_X; - brw_send_indirect_surface_message(p, sfid, brw_writemask(dst, mask), + elk_send_indirect_surface_message(p, sfid, elk_writemask(dst, mask), payload, surface, desc); } void -brw_untyped_surface_read(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg surface, +elk_untyped_surface_read(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg payload, + struct elk_reg surface, unsigned msg_length, unsigned num_channels) { @@ -3272,21 +3272,21 @@ brw_untyped_surface_read(struct brw_codegen *p, const unsigned sfid = (devinfo->verx10 >= 75 ? HSW_SFID_DATAPORT_DATA_CACHE_1 : GFX7_SFID_DATAPORT_DATA_CACHE); - const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1; - const unsigned exec_size = align1 ? 1 << brw_get_default_exec_size(p) : 0; + const bool align1 = elk_get_default_access_mode(p) == ELK_ALIGN_1; + const unsigned exec_size = align1 ? 1 << elk_get_default_exec_size(p) : 0; const unsigned response_length = - brw_surface_payload_size(num_channels, exec_size); + elk_surface_payload_size(num_channels, exec_size); const unsigned desc = - brw_message_desc(devinfo, msg_length, response_length, false) | - brw_dp_untyped_surface_rw_desc(devinfo, exec_size, num_channels, false); + elk_message_desc(devinfo, msg_length, response_length, false) | + elk_dp_untyped_surface_rw_desc(devinfo, exec_size, num_channels, false); - brw_send_indirect_surface_message(p, sfid, dst, payload, surface, desc); + elk_send_indirect_surface_message(p, sfid, dst, payload, surface, desc); } void -brw_untyped_surface_write(struct brw_codegen *p, - struct brw_reg payload, - struct brw_reg surface, +elk_untyped_surface_write(struct elk_codegen *p, + struct elk_reg payload, + struct elk_reg surface, unsigned msg_length, unsigned num_channels, bool header_present) @@ -3295,68 +3295,68 @@ brw_untyped_surface_write(struct brw_codegen *p, const unsigned sfid = (devinfo->verx10 >= 75 ? HSW_SFID_DATAPORT_DATA_CACHE_1 : GFX7_SFID_DATAPORT_DATA_CACHE); - const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1; + const bool align1 = elk_get_default_access_mode(p) == ELK_ALIGN_1; /* SIMD4x2 untyped surface write instructions only exist on HSW+ */ const bool has_simd4x2 = devinfo->verx10 >= 75; - const unsigned exec_size = align1 ? 1 << brw_get_default_exec_size(p) : + const unsigned exec_size = align1 ? 1 << elk_get_default_exec_size(p) : has_simd4x2 ? 0 : 8; const unsigned desc = - brw_message_desc(devinfo, msg_length, 0, header_present) | - brw_dp_untyped_surface_rw_desc(devinfo, exec_size, num_channels, true); - /* Mask out unused components -- See comment in brw_untyped_atomic(). */ + elk_message_desc(devinfo, msg_length, 0, header_present) | + elk_dp_untyped_surface_rw_desc(devinfo, exec_size, num_channels, true); + /* Mask out unused components -- See comment in elk_untyped_atomic(). */ const unsigned mask = !has_simd4x2 && !align1 ? WRITEMASK_X : WRITEMASK_XYZW; - brw_send_indirect_surface_message(p, sfid, brw_writemask(brw_null_reg(), mask), + elk_send_indirect_surface_message(p, sfid, elk_writemask(elk_null_reg(), mask), payload, surface, desc); } static void -brw_set_memory_fence_message(struct brw_codegen *p, - struct brw_inst *insn, - enum brw_message_target sfid, +elk_set_memory_fence_message(struct elk_codegen *p, + struct elk_inst *insn, + enum elk_message_target sfid, bool commit_enable, unsigned bti) { const struct intel_device_info *devinfo = p->devinfo; - brw_set_desc(p, insn, brw_message_desc( + elk_set_desc(p, insn, elk_message_desc( devinfo, 1, (commit_enable ? 1 : 0), true)); - brw_inst_set_sfid(devinfo, insn, sfid); + elk_inst_set_sfid(devinfo, insn, sfid); switch (sfid) { case GFX6_SFID_DATAPORT_RENDER_CACHE: - brw_inst_set_dp_msg_type(devinfo, insn, GFX7_DATAPORT_RC_MEMORY_FENCE); + elk_inst_set_dp_msg_type(devinfo, insn, GFX7_DATAPORT_RC_MEMORY_FENCE); break; case GFX7_SFID_DATAPORT_DATA_CACHE: - brw_inst_set_dp_msg_type(devinfo, insn, GFX7_DATAPORT_DC_MEMORY_FENCE); + elk_inst_set_dp_msg_type(devinfo, insn, GFX7_DATAPORT_DC_MEMORY_FENCE); break; default: unreachable("Not reached"); } if (commit_enable) - brw_inst_set_dp_msg_control(devinfo, insn, 1 << 5); + elk_inst_set_dp_msg_control(devinfo, insn, 1 << 5); assert(devinfo->ver >= 11 || bti == 0); - brw_inst_set_binding_table_index(devinfo, insn, bti); + elk_inst_set_binding_table_index(devinfo, insn, bti); } static void -gfx12_set_memory_fence_message(struct brw_codegen *p, - struct brw_inst *insn, - enum brw_message_target sfid, +gfx12_set_memory_fence_message(struct elk_codegen *p, + struct elk_inst *insn, + enum elk_message_target sfid, uint32_t desc) { const unsigned mlen = 1 * reg_unit(p->devinfo); /* g0 header */ /* Completion signaled by write to register. No data returned. */ const unsigned rlen = 1 * reg_unit(p->devinfo); - brw_inst_set_sfid(p->devinfo, insn, sfid); + elk_inst_set_sfid(p->devinfo, insn, sfid); - if (sfid == BRW_SFID_URB && p->devinfo->ver < 20) { - brw_set_desc(p, insn, brw_urb_fence_desc(p->devinfo) | - brw_message_desc(p->devinfo, mlen, rlen, true)); + if (sfid == ELK_SFID_URB && p->devinfo->ver < 20) { + elk_set_desc(p, insn, elk_urb_fence_desc(p->devinfo) | + elk_message_desc(p->devinfo, mlen, rlen, true)); } else { enum lsc_fence_scope scope = lsc_fence_msg_desc_scope(p->devinfo, desc); enum lsc_flush_type flush_type = lsc_fence_msg_desc_flush_type(p->devinfo, desc); @@ -3383,54 +3383,54 @@ gfx12_set_memory_fence_message(struct brw_codegen *p, flush_type = LSC_FLUSH_TYPE_NONE_6; } - brw_set_desc(p, insn, lsc_fence_msg_desc(p->devinfo, scope, + elk_set_desc(p, insn, lsc_fence_msg_desc(p->devinfo, scope, flush_type, false) | - brw_message_desc(p->devinfo, mlen, rlen, false)); + elk_message_desc(p->devinfo, mlen, rlen, false)); } } void -brw_memory_fence(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src, - enum opcode send_op, - enum brw_message_target sfid, +elk_memory_fence(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src, + enum elk_opcode send_op, + enum elk_message_target sfid, uint32_t desc, bool commit_enable, unsigned bti) { const struct intel_device_info *devinfo = p->devinfo; - dst = retype(vec1(dst), BRW_REGISTER_TYPE_UW); - src = retype(vec1(src), BRW_REGISTER_TYPE_UD); + dst = retype(vec1(dst), ELK_REGISTER_TYPE_UW); + src = retype(vec1(src), ELK_REGISTER_TYPE_UD); /* Set dst as destination for dependency tracking, the MEMORY_FENCE * message doesn't write anything back. */ - struct brw_inst *insn = next_insn(p, send_op); - brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); - brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1); - brw_set_dest(p, insn, dst); - brw_set_src0(p, insn, src); + struct elk_inst *insn = next_insn(p, send_op); + elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE); + elk_inst_set_exec_size(devinfo, insn, ELK_EXECUTE_1); + elk_set_dest(p, insn, dst); + elk_set_src0(p, insn, src); /* All DG2 hardware requires LSC for fence messages, even A-step */ if (devinfo->has_lsc) gfx12_set_memory_fence_message(p, insn, sfid, desc); else - brw_set_memory_fence_message(p, insn, sfid, commit_enable, bti); + elk_set_memory_fence_message(p, insn, sfid, commit_enable, bti); } void -brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst, bool last) +elk_find_live_channel(struct elk_codegen *p, struct elk_reg dst, bool last) { const struct intel_device_info *devinfo = p->devinfo; - const unsigned exec_size = 1 << brw_get_default_exec_size(p); - const unsigned qtr_control = brw_get_default_group(p) / 8; - brw_inst *inst; + const unsigned exec_size = 1 << elk_get_default_exec_size(p); + const unsigned qtr_control = elk_get_default_group(p) / 8; + elk_inst *inst; assert(devinfo->ver == 7); - brw_push_insn_state(p); + elk_push_insn_state(p); /* The flag register is only used on Gfx7 in align1 mode, so avoid setting * unnecessary bits in the instruction words, get the information we need @@ -3438,15 +3438,15 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst, bool last) * compacted. */ const unsigned flag_subreg = p->current->flag_subreg; - brw_set_default_flag_reg(p, 0, 0); + elk_set_default_flag_reg(p, 0, 0); - if (brw_get_default_access_mode(p) == BRW_ALIGN_1) { - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + if (elk_get_default_access_mode(p) == ELK_ALIGN_1) { + elk_set_default_mask_control(p, ELK_MASK_DISABLE); - const struct brw_reg flag = brw_flag_subreg(flag_subreg); + const struct elk_reg flag = elk_flag_subreg(flag_subreg); - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_MOV(p, retype(flag, BRW_REGISTER_TYPE_UD), brw_imm_ud(0)); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_MOV(p, retype(flag, ELK_REGISTER_TYPE_UD), elk_imm_ud(0)); /* Run enough instructions returning zero with execution masking and * a conditional modifier enabled in order to get the full execution @@ -3457,66 +3457,66 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst, bool last) */ const unsigned lower_size = MIN2(16, exec_size); for (unsigned i = 0; i < exec_size / lower_size; i++) { - inst = brw_MOV(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW), - brw_imm_uw(0)); - brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE); - brw_inst_set_group(devinfo, inst, lower_size * i + 8 * qtr_control); - brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z); - brw_inst_set_exec_size(devinfo, inst, cvt(lower_size) - 1); - brw_inst_set_flag_reg_nr(devinfo, inst, flag_subreg / 2); - brw_inst_set_flag_subreg_nr(devinfo, inst, flag_subreg % 2); + inst = elk_MOV(p, retype(elk_null_reg(), ELK_REGISTER_TYPE_UW), + elk_imm_uw(0)); + elk_inst_set_mask_control(devinfo, inst, ELK_MASK_ENABLE); + elk_inst_set_group(devinfo, inst, lower_size * i + 8 * qtr_control); + elk_inst_set_cond_modifier(devinfo, inst, ELK_CONDITIONAL_Z); + elk_inst_set_exec_size(devinfo, inst, cvt(lower_size) - 1); + elk_inst_set_flag_reg_nr(devinfo, inst, flag_subreg / 2); + elk_inst_set_flag_subreg_nr(devinfo, inst, flag_subreg % 2); } /* Find the first bit set in the exec_size-wide portion of the flag * register that was updated by the last sequence of MOV * instructions. */ - const enum brw_reg_type type = brw_int_type(exec_size / 8, false); - brw_set_default_exec_size(p, BRW_EXECUTE_1); + const enum elk_reg_type type = elk_int_type(exec_size / 8, false); + elk_set_default_exec_size(p, ELK_EXECUTE_1); if (!last) { - inst = brw_FBL(p, vec1(dst), byte_offset(retype(flag, type), qtr_control)); + inst = elk_FBL(p, vec1(dst), byte_offset(retype(flag, type), qtr_control)); } else { - inst = brw_LZD(p, vec1(dst), byte_offset(retype(flag, type), qtr_control)); - struct brw_reg neg = vec1(dst); + inst = elk_LZD(p, vec1(dst), byte_offset(retype(flag, type), qtr_control)); + struct elk_reg neg = vec1(dst); neg.negate = true; - inst = brw_ADD(p, vec1(dst), neg, brw_imm_uw(31)); + inst = elk_ADD(p, vec1(dst), neg, elk_imm_uw(31)); } } else { - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); /* Overwrite the destination without and with execution masking to * find out which of the channels is active. */ - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_4); - brw_MOV(p, brw_writemask(vec4(dst), WRITEMASK_X), - brw_imm_ud(1)); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_4); + elk_MOV(p, elk_writemask(vec4(dst), WRITEMASK_X), + elk_imm_ud(1)); - inst = brw_MOV(p, brw_writemask(vec4(dst), WRITEMASK_X), - brw_imm_ud(0)); - brw_pop_insn_state(p); - brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE); + inst = elk_MOV(p, elk_writemask(vec4(dst), WRITEMASK_X), + elk_imm_ud(0)); + elk_pop_insn_state(p); + elk_inst_set_mask_control(devinfo, inst, ELK_MASK_ENABLE); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } void -brw_broadcast(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg idx) +elk_broadcast(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src, + struct elk_reg idx) { const struct intel_device_info *devinfo = p->devinfo; - const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1; - brw_inst *inst; + const bool align1 = elk_get_default_access_mode(p) == ELK_ALIGN_1; + elk_inst *inst; - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_exec_size(p, align1 ? BRW_EXECUTE_1 : BRW_EXECUTE_4); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_exec_size(p, align1 ? ELK_EXECUTE_1 : ELK_EXECUTE_4); - assert(src.file == BRW_GENERAL_REGISTER_FILE && - src.address_mode == BRW_ADDRESS_DIRECT); + assert(src.file == ELK_GENERAL_REGISTER_FILE && + src.address_mode == ELK_ADDRESS_DIRECT); assert(!src.abs && !src.negate); /* Gen12.5 adds the following region restriction: @@ -3528,27 +3528,27 @@ brw_broadcast(struct brw_codegen *p, * unsigned integer type. */ assert(src.type == dst.type); - src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8, - BRW_REGISTER_TYPE_UD); + src.type = dst.type = elk_reg_type_from_bit_size(type_sz(src.type) * 8, + ELK_REGISTER_TYPE_UD); if ((src.vstride == 0 && (src.hstride == 0 || !align1)) || - idx.file == BRW_IMMEDIATE_VALUE) { + idx.file == ELK_IMMEDIATE_VALUE) { /* Trivial, the source is already uniform or the index is a constant. * We will typically not get here if the optimizer is doing its job, but * asserting would be mean. */ - const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0; + const unsigned i = idx.file == ELK_IMMEDIATE_VALUE ? idx.ud : 0; src = align1 ? stride(suboffset(src, i), 0, 1, 0) : stride(suboffset(src, 4 * i), 0, 4, 1); if (type_sz(src.type) > 4 && !devinfo->has_64bit_int) { - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), - subscript(src, BRW_REGISTER_TYPE_D, 0)); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1), - subscript(src, BRW_REGISTER_TYPE_D, 1)); + elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 0), + subscript(src, ELK_REGISTER_TYPE_D, 0)); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 1), + subscript(src, ELK_REGISTER_TYPE_D, 1)); } else { - brw_MOV(p, dst, src); + elk_MOV(p, dst, src); } } else { /* From the Haswell PRM section "Register Region Restrictions": @@ -3566,21 +3566,21 @@ brw_broadcast(struct brw_codegen *p, assert(src.subnr == 0); if (align1) { - const struct brw_reg addr = - retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD); + const struct elk_reg addr = + retype(elk_address_reg(0), ELK_REGISTER_TYPE_UD); unsigned offset = src.nr * REG_SIZE + src.subnr; /* Limit in bytes of the signed indirect addressing immediate. */ const unsigned limit = 512; - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); /* Take into account the component size and horizontal stride. */ assert(src.vstride == src.hstride + src.width); - brw_SHL(p, addr, vec1(idx), - brw_imm_ud(util_logbase2(type_sz(src.type)) + + elk_SHL(p, addr, vec1(idx), + elk_imm_ud(util_logbase2(type_sz(src.type)) + src.hstride - 1)); /* We can only address up to limit bytes using the indirect @@ -3588,14 +3588,14 @@ brw_broadcast(struct brw_codegen *p, * register is above this limit. */ if (offset >= limit) { - brw_set_default_swsb(p, tgl_swsb_regdist(1)); - brw_ADD(p, addr, addr, brw_imm_ud(offset - offset % limit)); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_ADD(p, addr, addr, elk_imm_ud(offset - offset % limit)); offset = offset % limit; } - brw_pop_insn_state(p); + elk_pop_insn_state(p); - brw_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); /* Use indirect addressing to fetch the specified component. */ if (type_sz(src.type) > 4 && @@ -3613,38 +3613,38 @@ brw_broadcast(struct brw_codegen *p, * offset in the indirect here to handle adding 4 bytes to the * offset and avoid the extra ADD to the register file. */ - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), - retype(brw_vec1_indirect(addr.subnr, offset), - BRW_REGISTER_TYPE_D)); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1), - retype(brw_vec1_indirect(addr.subnr, offset + 4), - BRW_REGISTER_TYPE_D)); + elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 0), + retype(elk_vec1_indirect(addr.subnr, offset), + ELK_REGISTER_TYPE_D)); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 1), + retype(elk_vec1_indirect(addr.subnr, offset + 4), + ELK_REGISTER_TYPE_D)); } else { - brw_MOV(p, dst, - retype(brw_vec1_indirect(addr.subnr, offset), src.type)); + elk_MOV(p, dst, + retype(elk_vec1_indirect(addr.subnr, offset), src.type)); } } else { /* In SIMD4x2 mode the index can be either zero or one, replicate it * to all bits of a flag register, */ - inst = brw_MOV(p, - brw_null_reg(), - stride(brw_swizzle(idx, BRW_SWIZZLE_XXXX), 4, 4, 1)); - brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NONE); - brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_NZ); - brw_inst_set_flag_reg_nr(devinfo, inst, 1); + inst = elk_MOV(p, + elk_null_reg(), + stride(elk_swizzle(idx, ELK_SWIZZLE_XXXX), 4, 4, 1)); + elk_inst_set_pred_control(devinfo, inst, ELK_PREDICATE_NONE); + elk_inst_set_cond_modifier(devinfo, inst, ELK_CONDITIONAL_NZ); + elk_inst_set_flag_reg_nr(devinfo, inst, 1); /* and use predicated SEL to pick the right channel. */ - inst = brw_SEL(p, dst, + inst = elk_SEL(p, dst, stride(suboffset(src, 4), 4, 4, 1), stride(src, 4, 4, 1)); - brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NORMAL); - brw_inst_set_flag_reg_nr(devinfo, inst, 1); + elk_inst_set_pred_control(devinfo, inst, ELK_PREDICATE_NORMAL); + elk_inst_set_flag_reg_nr(devinfo, inst, 1); } } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } @@ -3652,28 +3652,28 @@ brw_broadcast(struct brw_codegen *p, * Emit the SEND message for a barrier */ void -brw_barrier(struct brw_codegen *p, struct brw_reg src) +elk_barrier(struct elk_codegen *p, struct elk_reg src) { const struct intel_device_info *devinfo = p->devinfo; - struct brw_inst *inst; + struct elk_inst *inst; assert(devinfo->ver >= 7); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - inst = next_insn(p, BRW_OPCODE_SEND); - brw_set_dest(p, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW)); - brw_set_src0(p, inst, src); - brw_set_src1(p, inst, brw_null_reg()); - brw_set_desc(p, inst, brw_message_desc(devinfo, + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + inst = next_insn(p, ELK_OPCODE_SEND); + elk_set_dest(p, inst, retype(elk_null_reg(), ELK_REGISTER_TYPE_UW)); + elk_set_src0(p, inst, src); + elk_set_src1(p, inst, elk_null_reg()); + elk_set_desc(p, inst, elk_message_desc(devinfo, 1 * reg_unit(devinfo), 0, false)); - brw_inst_set_sfid(devinfo, inst, BRW_SFID_MESSAGE_GATEWAY); - brw_inst_set_gateway_subfuncid(devinfo, inst, - BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG); + elk_inst_set_sfid(devinfo, inst, ELK_SFID_MESSAGE_GATEWAY); + elk_inst_set_gateway_subfuncid(devinfo, inst, + ELK_MESSAGE_GATEWAY_SFID_BARRIER_MSG); - brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE); - brw_pop_insn_state(p); + elk_inst_set_mask_control(devinfo, inst, ELK_MASK_DISABLE); + elk_pop_insn_state(p); } @@ -3681,27 +3681,27 @@ brw_barrier(struct brw_codegen *p, struct brw_reg src) * Emit the wait instruction for a barrier */ void -brw_WAIT(struct brw_codegen *p) +elk_WAIT(struct elk_codegen *p) { const struct intel_device_info *devinfo = p->devinfo; - struct brw_inst *insn; + struct elk_inst *insn; - struct brw_reg src = brw_notification_reg(); + struct elk_reg src = elk_notification_reg(); - insn = next_insn(p, BRW_OPCODE_WAIT); - brw_set_dest(p, insn, src); - brw_set_src0(p, insn, src); - brw_set_src1(p, insn, brw_null_reg()); + insn = next_insn(p, ELK_OPCODE_WAIT); + elk_set_dest(p, insn, src); + elk_set_src0(p, insn, src); + elk_set_src1(p, insn, elk_null_reg()); - brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1); - brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); + elk_inst_set_exec_size(devinfo, insn, ELK_EXECUTE_1); + elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE); } void -brw_float_controls_mode(struct brw_codegen *p, +elk_float_controls_mode(struct elk_codegen *p, unsigned mode, unsigned mask) { - assert(p->current->mask_control == BRW_MASK_DISABLE); + assert(p->current->mask_control == ELK_MASK_DISABLE); /* From the Skylake PRM, Volume 7, page 760: * "Implementation Restriction on Register Access: When the control @@ -3712,41 +3712,41 @@ brw_float_controls_mode(struct brw_codegen *p, * * On Gfx12+ this is implemented in terms of SWSB annotations instead. */ - brw_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); - brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0), - brw_imm_ud(~mask)); - brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1); + elk_inst *inst = elk_AND(p, elk_cr0_reg(0), elk_cr0_reg(0), + elk_imm_ud(~mask)); + elk_inst_set_exec_size(p->devinfo, inst, ELK_EXECUTE_1); if (p->devinfo->ver < 12) - brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH); + elk_inst_set_thread_control(p->devinfo, inst, ELK_THREAD_SWITCH); if (mode) { - brw_inst *inst_or = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0), - brw_imm_ud(mode)); - brw_inst_set_exec_size(p->devinfo, inst_or, BRW_EXECUTE_1); + elk_inst *inst_or = elk_OR(p, elk_cr0_reg(0), elk_cr0_reg(0), + elk_imm_ud(mode)); + elk_inst_set_exec_size(p->devinfo, inst_or, ELK_EXECUTE_1); if (p->devinfo->ver < 12) - brw_inst_set_thread_control(p->devinfo, inst_or, BRW_THREAD_SWITCH); + elk_inst_set_thread_control(p->devinfo, inst_or, ELK_THREAD_SWITCH); } if (p->devinfo->ver >= 12) - brw_SYNC(p, TGL_SYNC_NOP); + elk_SYNC(p, TGL_SYNC_NOP); } void -brw_update_reloc_imm(const struct brw_isa_info *isa, - brw_inst *inst, +elk_update_reloc_imm(const struct elk_isa_info *isa, + elk_inst *inst, uint32_t value) { const struct intel_device_info *devinfo = isa->devinfo; /* Sanity check that the instruction is a MOV of an immediate */ - assert(brw_inst_opcode(isa, inst) == BRW_OPCODE_MOV); - assert(brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE); + assert(elk_inst_opcode(isa, inst) == ELK_OPCODE_MOV); + assert(elk_inst_src0_reg_file(devinfo, inst) == ELK_IMMEDIATE_VALUE); /* If it was compacted, we can't safely rewrite */ - assert(brw_inst_cmpt_control(devinfo, inst) == 0); + assert(elk_inst_cmpt_control(devinfo, inst) == 0); - brw_inst_set_imm_ud(devinfo, inst, value); + elk_inst_set_imm_ud(devinfo, inst, value); } /* A default value for constants that will be patched at run-time. @@ -3755,16 +3755,16 @@ brw_update_reloc_imm(const struct brw_isa_info *isa, #define DEFAULT_PATCH_IMM 0x4a7cc037 void -brw_MOV_reloc_imm(struct brw_codegen *p, - struct brw_reg dst, - enum brw_reg_type src_type, +elk_MOV_reloc_imm(struct elk_codegen *p, + struct elk_reg dst, + enum elk_reg_type src_type, uint32_t id) { assert(type_sz(src_type) == 4); assert(type_sz(dst.type) == 4); - brw_add_reloc(p, id, BRW_SHADER_RELOC_TYPE_MOV_IMM, + elk_add_reloc(p, id, ELK_SHADER_RELOC_TYPE_MOV_IMM, p->next_insn_offset, 0); - brw_MOV(p, dst, retype(brw_imm_ud(DEFAULT_PATCH_IMM), src_type)); + elk_MOV(p, dst, retype(elk_imm_ud(DEFAULT_PATCH_IMM), src_type)); } diff --git a/src/intel/compiler/elk/elk_eu_util.c b/src/intel/compiler/elk/elk_eu_util.c index 42f32bb0eb0..a1ec336f365 100644 --- a/src/intel/compiler/elk/elk_eu_util.c +++ b/src/intel/compiler/elk/elk_eu_util.c @@ -34,23 +34,23 @@ #include "elk_eu.h" -void brw_math_invert( struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src) +void elk_math_invert( struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src) { - gfx4_math(p, + elk_gfx4_math(p, dst, - BRW_MATH_FUNCTION_INV, + ELK_MATH_FUNCTION_INV, 0, src, - BRW_MATH_PRECISION_FULL); + ELK_MATH_PRECISION_FULL); } -void brw_copy4(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src, +void elk_copy4(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src, unsigned count) { unsigned i; @@ -61,15 +61,15 @@ void brw_copy4(struct brw_codegen *p, for (i = 0; i < count; i++) { unsigned delta = i*32; - brw_MOV(p, byte_offset(dst, delta), byte_offset(src, delta)); - brw_MOV(p, byte_offset(dst, delta+16), byte_offset(src, delta+16)); + elk_MOV(p, byte_offset(dst, delta), byte_offset(src, delta)); + elk_MOV(p, byte_offset(dst, delta+16), byte_offset(src, delta+16)); } } -void brw_copy8(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src, +void elk_copy8(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src, unsigned count) { unsigned i; @@ -80,14 +80,14 @@ void brw_copy8(struct brw_codegen *p, for (i = 0; i < count; i++) { unsigned delta = i*32; - brw_MOV(p, byte_offset(dst, delta), byte_offset(src, delta)); + elk_MOV(p, byte_offset(dst, delta), byte_offset(src, delta)); } } -void brw_copy_indirect_to_indirect(struct brw_codegen *p, - struct brw_indirect dst_ptr, - struct brw_indirect src_ptr, +void elk_copy_indirect_to_indirect(struct elk_codegen *p, + struct elk_indirect dst_ptr, + struct elk_indirect src_ptr, unsigned count) { unsigned i; @@ -95,15 +95,15 @@ void brw_copy_indirect_to_indirect(struct brw_codegen *p, for (i = 0; i < count; i++) { unsigned delta = i*32; - brw_MOV(p, deref_4f(dst_ptr, delta), deref_4f(src_ptr, delta)); - brw_MOV(p, deref_4f(dst_ptr, delta+16), deref_4f(src_ptr, delta+16)); + elk_MOV(p, deref_4f(dst_ptr, delta), deref_4f(src_ptr, delta)); + elk_MOV(p, deref_4f(dst_ptr, delta+16), deref_4f(src_ptr, delta+16)); } } -void brw_copy_from_indirect(struct brw_codegen *p, - struct brw_reg dst, - struct brw_indirect ptr, +void elk_copy_from_indirect(struct elk_codegen *p, + struct elk_reg dst, + struct elk_indirect ptr, unsigned count) { unsigned i; @@ -113,7 +113,7 @@ void brw_copy_from_indirect(struct brw_codegen *p, for (i = 0; i < count; i++) { unsigned delta = i*32; - brw_MOV(p, byte_offset(dst, delta), deref_4f(ptr, delta)); - brw_MOV(p, byte_offset(dst, delta+16), deref_4f(ptr, delta+16)); + elk_MOV(p, byte_offset(dst, delta), deref_4f(ptr, delta)); + elk_MOV(p, byte_offset(dst, delta+16), deref_4f(ptr, delta+16)); } } diff --git a/src/intel/compiler/elk/elk_eu_validate.c b/src/intel/compiler/elk/elk_eu_validate.c index f03ee00d1af..23157a0320a 100644 --- a/src/intel/compiler/elk/elk_eu_validate.c +++ b/src/intel/compiler/elk/elk_eu_validate.c @@ -91,13 +91,13 @@ contains(const struct string haystack, const struct string needle) #define WIDTH(width) (1 << (width)) static bool -inst_is_send(const struct brw_isa_info *isa, const brw_inst *inst) +inst_is_send(const struct elk_isa_info *isa, const elk_inst *inst) { - switch (brw_inst_opcode(isa, inst)) { - case BRW_OPCODE_SEND: - case BRW_OPCODE_SENDC: - case BRW_OPCODE_SENDS: - case BRW_OPCODE_SENDSC: + switch (elk_inst_opcode(isa, inst)) { + case ELK_OPCODE_SEND: + case ELK_OPCODE_SENDC: + case ELK_OPCODE_SENDS: + case ELK_OPCODE_SENDSC: return true; default: return false; @@ -105,16 +105,16 @@ inst_is_send(const struct brw_isa_info *isa, const brw_inst *inst) } static bool -inst_is_split_send(const struct brw_isa_info *isa, const brw_inst *inst) +inst_is_split_send(const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; if (devinfo->ver >= 12) { return inst_is_send(isa, inst); } else { - switch (brw_inst_opcode(isa, inst)) { - case BRW_OPCODE_SENDS: - case BRW_OPCODE_SENDSC: + switch (elk_inst_opcode(isa, inst)) { + case ELK_OPCODE_SENDS: + case ELK_OPCODE_SENDSC: return true; default: return false; @@ -126,117 +126,117 @@ static unsigned signed_type(unsigned type) { switch (type) { - case BRW_REGISTER_TYPE_UD: return BRW_REGISTER_TYPE_D; - case BRW_REGISTER_TYPE_UW: return BRW_REGISTER_TYPE_W; - case BRW_REGISTER_TYPE_UB: return BRW_REGISTER_TYPE_B; - case BRW_REGISTER_TYPE_UQ: return BRW_REGISTER_TYPE_Q; + case ELK_REGISTER_TYPE_UD: return ELK_REGISTER_TYPE_D; + case ELK_REGISTER_TYPE_UW: return ELK_REGISTER_TYPE_W; + case ELK_REGISTER_TYPE_UB: return ELK_REGISTER_TYPE_B; + case ELK_REGISTER_TYPE_UQ: return ELK_REGISTER_TYPE_Q; default: return type; } } -static enum brw_reg_type -inst_dst_type(const struct brw_isa_info *isa, const brw_inst *inst) +static enum elk_reg_type +inst_dst_type(const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; return (devinfo->ver < 12 || !inst_is_send(isa, inst)) ? - brw_inst_dst_type(devinfo, inst) : BRW_REGISTER_TYPE_D; + elk_inst_dst_type(devinfo, inst) : ELK_REGISTER_TYPE_D; } static bool -inst_is_raw_move(const struct brw_isa_info *isa, const brw_inst *inst) +inst_is_raw_move(const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; unsigned dst_type = signed_type(inst_dst_type(isa, inst)); - unsigned src_type = signed_type(brw_inst_src0_type(devinfo, inst)); + unsigned src_type = signed_type(elk_inst_src0_type(devinfo, inst)); - if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { + if (elk_inst_src0_reg_file(devinfo, inst) == ELK_IMMEDIATE_VALUE) { /* FIXME: not strictly true */ - if (brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_VF || - brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UV || - brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_V) { + if (elk_inst_src0_type(devinfo, inst) == ELK_REGISTER_TYPE_VF || + elk_inst_src0_type(devinfo, inst) == ELK_REGISTER_TYPE_UV || + elk_inst_src0_type(devinfo, inst) == ELK_REGISTER_TYPE_V) { return false; } - } else if (brw_inst_src0_negate(devinfo, inst) || - brw_inst_src0_abs(devinfo, inst)) { + } else if (elk_inst_src0_negate(devinfo, inst) || + elk_inst_src0_abs(devinfo, inst)) { return false; } - return brw_inst_opcode(isa, inst) == BRW_OPCODE_MOV && - brw_inst_saturate(devinfo, inst) == 0 && + return elk_inst_opcode(isa, inst) == ELK_OPCODE_MOV && + elk_inst_saturate(devinfo, inst) == 0 && dst_type == src_type; } static bool -dst_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) +dst_is_null(const struct intel_device_info *devinfo, const elk_inst *inst) { - return brw_inst_dst_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && - brw_inst_dst_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; + return elk_inst_dst_reg_file(devinfo, inst) == ELK_ARCHITECTURE_REGISTER_FILE && + elk_inst_dst_da_reg_nr(devinfo, inst) == ELK_ARF_NULL; } static bool -src0_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) +src0_is_null(const struct intel_device_info *devinfo, const elk_inst *inst) { - return brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT && - brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && - brw_inst_src0_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; + return elk_inst_src0_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT && + elk_inst_src0_reg_file(devinfo, inst) == ELK_ARCHITECTURE_REGISTER_FILE && + elk_inst_src0_da_reg_nr(devinfo, inst) == ELK_ARF_NULL; } static bool -src1_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) +src1_is_null(const struct intel_device_info *devinfo, const elk_inst *inst) { - return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && - brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL; + return elk_inst_src1_reg_file(devinfo, inst) == ELK_ARCHITECTURE_REGISTER_FILE && + elk_inst_src1_da_reg_nr(devinfo, inst) == ELK_ARF_NULL; } static bool -src0_is_acc(const struct intel_device_info *devinfo, const brw_inst *inst) +src0_is_acc(const struct intel_device_info *devinfo, const elk_inst *inst) { - return brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && - (brw_inst_src0_da_reg_nr(devinfo, inst) & 0xF0) == BRW_ARF_ACCUMULATOR; + return elk_inst_src0_reg_file(devinfo, inst) == ELK_ARCHITECTURE_REGISTER_FILE && + (elk_inst_src0_da_reg_nr(devinfo, inst) & 0xF0) == ELK_ARF_ACCUMULATOR; } static bool -src1_is_acc(const struct intel_device_info *devinfo, const brw_inst *inst) +src1_is_acc(const struct intel_device_info *devinfo, const elk_inst *inst) { - return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && - (brw_inst_src1_da_reg_nr(devinfo, inst) & 0xF0) == BRW_ARF_ACCUMULATOR; + return elk_inst_src1_reg_file(devinfo, inst) == ELK_ARCHITECTURE_REGISTER_FILE && + (elk_inst_src1_da_reg_nr(devinfo, inst) & 0xF0) == ELK_ARF_ACCUMULATOR; } static bool src0_has_scalar_region(const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { - return brw_inst_src0_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 && - brw_inst_src0_width(devinfo, inst) == BRW_WIDTH_1 && - brw_inst_src0_hstride(devinfo, inst) == BRW_HORIZONTAL_STRIDE_0; + return elk_inst_src0_vstride(devinfo, inst) == ELK_VERTICAL_STRIDE_0 && + elk_inst_src0_width(devinfo, inst) == ELK_WIDTH_1 && + elk_inst_src0_hstride(devinfo, inst) == ELK_HORIZONTAL_STRIDE_0; } static bool src1_has_scalar_region(const struct intel_device_info *devinfo, - const brw_inst *inst) + const elk_inst *inst) { - return brw_inst_src1_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 && - brw_inst_src1_width(devinfo, inst) == BRW_WIDTH_1 && - brw_inst_src1_hstride(devinfo, inst) == BRW_HORIZONTAL_STRIDE_0; + return elk_inst_src1_vstride(devinfo, inst) == ELK_VERTICAL_STRIDE_0 && + elk_inst_src1_width(devinfo, inst) == ELK_WIDTH_1 && + elk_inst_src1_hstride(devinfo, inst) == ELK_HORIZONTAL_STRIDE_0; } static struct string -invalid_values(const struct brw_isa_info *isa, const brw_inst *inst) +invalid_values(const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - unsigned num_sources = brw_num_sources_from_inst(isa, inst); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); struct string error_msg = { .str = NULL, .len = 0 }; - switch ((enum brw_execution_size) brw_inst_exec_size(devinfo, inst)) { - case BRW_EXECUTE_1: - case BRW_EXECUTE_2: - case BRW_EXECUTE_4: - case BRW_EXECUTE_8: - case BRW_EXECUTE_16: - case BRW_EXECUTE_32: + switch ((enum elk_execution_size) elk_inst_exec_size(devinfo, inst)) { + case ELK_EXECUTE_1: + case ELK_EXECUTE_2: + case ELK_EXECUTE_4: + case ELK_EXECUTE_8: + case ELK_EXECUTE_16: + case ELK_EXECUTE_32: break; default: ERROR("invalid execution size"); @@ -247,9 +247,9 @@ invalid_values(const struct brw_isa_info *isa, const brw_inst *inst) return error_msg; if (devinfo->ver >= 12) { - unsigned group_size = 1 << brw_inst_exec_size(devinfo, inst); - unsigned qtr_ctrl = brw_inst_qtr_control(devinfo, inst); - unsigned nib_ctrl = brw_inst_nib_control(devinfo, inst); + unsigned group_size = 1 << elk_inst_exec_size(devinfo, inst); + unsigned qtr_ctrl = elk_inst_qtr_control(devinfo, inst); + unsigned nib_ctrl = elk_inst_nib_control(devinfo, inst); unsigned chan_off = (qtr_ctrl * 2 + nib_ctrl) << 2; ERROR_IF(chan_off % group_size != 0, @@ -267,11 +267,11 @@ invalid_values(const struct brw_isa_info *isa, const brw_inst *inst) */ } else { if (devinfo->ver > 6) { - ERROR_IF(brw_inst_dst_reg_file(devinfo, inst) == MRF || + ERROR_IF(elk_inst_dst_reg_file(devinfo, inst) == MRF || (num_sources > 0 && - brw_inst_src0_reg_file(devinfo, inst) == MRF) || + elk_inst_src0_reg_file(devinfo, inst) == MRF) || (num_sources > 1 && - brw_inst_src1_reg_file(devinfo, inst) == MRF), + elk_inst_src1_reg_file(devinfo, inst) == MRF), "invalid register file encoding"); } } @@ -280,27 +280,27 @@ invalid_values(const struct brw_isa_info *isa, const brw_inst *inst) return error_msg; if (num_sources == 3) { - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { if (devinfo->ver >= 10) { - ERROR_IF(brw_inst_3src_a1_dst_type (devinfo, inst) == INVALID_REG_TYPE || - brw_inst_3src_a1_src0_type(devinfo, inst) == INVALID_REG_TYPE || - brw_inst_3src_a1_src1_type(devinfo, inst) == INVALID_REG_TYPE || - brw_inst_3src_a1_src2_type(devinfo, inst) == INVALID_REG_TYPE, + ERROR_IF(elk_inst_3src_a1_dst_type (devinfo, inst) == INVALID_REG_TYPE || + elk_inst_3src_a1_src0_type(devinfo, inst) == INVALID_REG_TYPE || + elk_inst_3src_a1_src1_type(devinfo, inst) == INVALID_REG_TYPE || + elk_inst_3src_a1_src2_type(devinfo, inst) == INVALID_REG_TYPE, "invalid register type encoding"); } else { ERROR("Align1 mode not allowed on Gen < 10"); } } else { - ERROR_IF(brw_inst_3src_a16_dst_type(devinfo, inst) == INVALID_REG_TYPE || - brw_inst_3src_a16_src_type(devinfo, inst) == INVALID_REG_TYPE, + ERROR_IF(elk_inst_3src_a16_dst_type(devinfo, inst) == INVALID_REG_TYPE || + elk_inst_3src_a16_src_type(devinfo, inst) == INVALID_REG_TYPE, "invalid register type encoding"); } } else { - ERROR_IF(brw_inst_dst_type (devinfo, inst) == INVALID_REG_TYPE || + ERROR_IF(elk_inst_dst_type (devinfo, inst) == INVALID_REG_TYPE || (num_sources > 0 && - brw_inst_src0_type(devinfo, inst) == INVALID_REG_TYPE) || + elk_inst_src0_type(devinfo, inst) == INVALID_REG_TYPE) || (num_sources > 1 && - brw_inst_src1_type(devinfo, inst) == INVALID_REG_TYPE), + elk_inst_src1_type(devinfo, inst) == INVALID_REG_TYPE), "invalid register type encoding"); } @@ -308,11 +308,11 @@ invalid_values(const struct brw_isa_info *isa, const brw_inst *inst) } static struct string -sources_not_null(const struct brw_isa_info *isa, - const brw_inst *inst) +sources_not_null(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - unsigned num_sources = brw_num_sources_from_inst(isa, inst); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); struct string error_msg = { .str = NULL, .len = 0 }; /* Nothing to test. 3-src instructions can only have GRF sources, and @@ -327,7 +327,7 @@ sources_not_null(const struct brw_isa_info *isa, if (inst_is_split_send(isa, inst)) return (struct string){}; - if (num_sources >= 1 && brw_inst_opcode(isa, inst) != BRW_OPCODE_SYNC) + if (num_sources >= 1 && elk_inst_opcode(isa, inst) != ELK_OPCODE_SYNC) ERROR_IF(src0_is_null(devinfo, inst), "src0 is null"); if (num_sources == 2) @@ -337,79 +337,79 @@ sources_not_null(const struct brw_isa_info *isa, } static struct string -alignment_supported(const struct brw_isa_info *isa, - const brw_inst *inst) +alignment_supported(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; struct string error_msg = { .str = NULL, .len = 0 }; - ERROR_IF(devinfo->ver >= 11 && brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16, + ERROR_IF(devinfo->ver >= 11 && elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_16, "Align16 not supported"); return error_msg; } static bool -inst_uses_src_acc(const struct brw_isa_info *isa, - const brw_inst *inst) +inst_uses_src_acc(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; /* Check instructions that use implicit accumulator sources */ - switch (brw_inst_opcode(isa, inst)) { - case BRW_OPCODE_MAC: - case BRW_OPCODE_MACH: - case BRW_OPCODE_SADA2: + switch (elk_inst_opcode(isa, inst)) { + case ELK_OPCODE_MAC: + case ELK_OPCODE_MACH: + case ELK_OPCODE_SADA2: return true; default: break; } /* FIXME: support 3-src instructions */ - unsigned num_sources = brw_num_sources_from_inst(isa, inst); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); assert(num_sources < 3); return src0_is_acc(devinfo, inst) || (num_sources > 1 && src1_is_acc(devinfo, inst)); } static struct string -send_restrictions(const struct brw_isa_info *isa, - const brw_inst *inst) +send_restrictions(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; struct string error_msg = { .str = NULL, .len = 0 }; if (inst_is_split_send(isa, inst)) { - ERROR_IF(brw_inst_send_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && - brw_inst_send_src1_reg_nr(devinfo, inst) != BRW_ARF_NULL, + ERROR_IF(elk_inst_send_src1_reg_file(devinfo, inst) == ELK_ARCHITECTURE_REGISTER_FILE && + elk_inst_send_src1_reg_nr(devinfo, inst) != ELK_ARF_NULL, "src1 of split send must be a GRF or NULL"); - ERROR_IF(brw_inst_eot(devinfo, inst) && - brw_inst_src0_da_reg_nr(devinfo, inst) < 112, + ERROR_IF(elk_inst_eot(devinfo, inst) && + elk_inst_src0_da_reg_nr(devinfo, inst) < 112, "send with EOT must use g112-g127"); - ERROR_IF(brw_inst_eot(devinfo, inst) && - brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE && - brw_inst_send_src1_reg_nr(devinfo, inst) < 112, + ERROR_IF(elk_inst_eot(devinfo, inst) && + elk_inst_send_src1_reg_file(devinfo, inst) == ELK_GENERAL_REGISTER_FILE && + elk_inst_send_src1_reg_nr(devinfo, inst) < 112, "send with EOT must use g112-g127"); - if (brw_inst_send_src0_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE && - brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE) { + if (elk_inst_send_src0_reg_file(devinfo, inst) == ELK_GENERAL_REGISTER_FILE && + elk_inst_send_src1_reg_file(devinfo, inst) == ELK_GENERAL_REGISTER_FILE) { /* Assume minimums if we don't know */ unsigned mlen = 1; - if (!brw_inst_send_sel_reg32_desc(devinfo, inst)) { - const uint32_t desc = brw_inst_send_desc(devinfo, inst); - mlen = brw_message_desc_mlen(devinfo, desc) / reg_unit(devinfo); + if (!elk_inst_send_sel_reg32_desc(devinfo, inst)) { + const uint32_t desc = elk_inst_send_desc(devinfo, inst); + mlen = elk_message_desc_mlen(devinfo, desc) / reg_unit(devinfo); } unsigned ex_mlen = 1; - if (!brw_inst_send_sel_reg32_ex_desc(devinfo, inst)) { - const uint32_t ex_desc = brw_inst_sends_ex_desc(devinfo, inst); - ex_mlen = brw_message_ex_desc_ex_mlen(devinfo, ex_desc) / + if (!elk_inst_send_sel_reg32_ex_desc(devinfo, inst)) { + const uint32_t ex_desc = elk_inst_sends_ex_desc(devinfo, inst); + ex_mlen = elk_message_ex_desc_ex_mlen(devinfo, ex_desc) / reg_unit(devinfo); } - const unsigned src0_reg_nr = brw_inst_src0_da_reg_nr(devinfo, inst); - const unsigned src1_reg_nr = brw_inst_send_src1_reg_nr(devinfo, inst); + const unsigned src0_reg_nr = elk_inst_src0_da_reg_nr(devinfo, inst); + const unsigned src1_reg_nr = elk_inst_send_src1_reg_nr(devinfo, inst); ERROR_IF((src0_reg_nr <= src1_reg_nr && src1_reg_nr < src0_reg_nr + mlen) || (src1_reg_nr <= src0_reg_nr && @@ -417,24 +417,24 @@ send_restrictions(const struct brw_isa_info *isa, "split send payloads must not overlap"); } } else if (inst_is_send(isa, inst)) { - ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT, + ERROR_IF(elk_inst_src0_address_mode(devinfo, inst) != ELK_ADDRESS_DIRECT, "send must use direct addressing"); if (devinfo->ver >= 7) { - ERROR_IF(brw_inst_send_src0_reg_file(devinfo, inst) != BRW_GENERAL_REGISTER_FILE, + ERROR_IF(elk_inst_send_src0_reg_file(devinfo, inst) != ELK_GENERAL_REGISTER_FILE, "send from non-GRF"); - ERROR_IF(brw_inst_eot(devinfo, inst) && - brw_inst_src0_da_reg_nr(devinfo, inst) < 112, + ERROR_IF(elk_inst_eot(devinfo, inst) && + elk_inst_src0_da_reg_nr(devinfo, inst) < 112, "send with EOT must use g112-g127"); } if (devinfo->ver >= 8) { ERROR_IF(!dst_is_null(devinfo, inst) && - (brw_inst_dst_da_reg_nr(devinfo, inst) + - brw_inst_rlen(devinfo, inst) > 127) && - (brw_inst_src0_da_reg_nr(devinfo, inst) + - brw_inst_mlen(devinfo, inst) > - brw_inst_dst_da_reg_nr(devinfo, inst)), + (elk_inst_dst_da_reg_nr(devinfo, inst) + + elk_inst_rlen(devinfo, inst) > 127) && + (elk_inst_src0_da_reg_nr(devinfo, inst) + + elk_inst_mlen(devinfo, inst) > + elk_inst_dst_da_reg_nr(devinfo, inst)), "r127 must not be used for return address when there is " "a src and dest overlap"); } @@ -444,10 +444,10 @@ send_restrictions(const struct brw_isa_info *isa, } static bool -is_unsupported_inst(const struct brw_isa_info *isa, - const brw_inst *inst) +is_unsupported_inst(const struct elk_isa_info *isa, + const elk_inst *inst) { - return brw_inst_opcode(isa, inst) == BRW_OPCODE_ILLEGAL; + return elk_inst_opcode(isa, inst) == ELK_OPCODE_ILLEGAL; } /** @@ -455,40 +455,40 @@ is_unsupported_inst(const struct brw_isa_info *isa, * operation mode */ static inline bool -types_are_mixed_float(enum brw_reg_type t0, enum brw_reg_type t1) +types_are_mixed_float(enum elk_reg_type t0, enum elk_reg_type t1) { - return (t0 == BRW_REGISTER_TYPE_F && t1 == BRW_REGISTER_TYPE_HF) || - (t1 == BRW_REGISTER_TYPE_F && t0 == BRW_REGISTER_TYPE_HF); + return (t0 == ELK_REGISTER_TYPE_F && t1 == ELK_REGISTER_TYPE_HF) || + (t1 == ELK_REGISTER_TYPE_F && t0 == ELK_REGISTER_TYPE_HF); } -static enum brw_reg_type -execution_type_for_type(enum brw_reg_type type) +static enum elk_reg_type +execution_type_for_type(enum elk_reg_type type) { switch (type) { - case BRW_REGISTER_TYPE_NF: - case BRW_REGISTER_TYPE_DF: - case BRW_REGISTER_TYPE_F: - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_HF: return type; - case BRW_REGISTER_TYPE_VF: - return BRW_REGISTER_TYPE_F; + case ELK_REGISTER_TYPE_VF: + return ELK_REGISTER_TYPE_F; - case BRW_REGISTER_TYPE_Q: - case BRW_REGISTER_TYPE_UQ: - return BRW_REGISTER_TYPE_Q; + case ELK_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UQ: + return ELK_REGISTER_TYPE_Q; - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UD: - return BRW_REGISTER_TYPE_D; + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UD: + return ELK_REGISTER_TYPE_D; - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_V: - case BRW_REGISTER_TYPE_UV: - return BRW_REGISTER_TYPE_W; + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UV: + return ELK_REGISTER_TYPE_W; } unreachable("not reached"); } @@ -496,63 +496,63 @@ execution_type_for_type(enum brw_reg_type type) /** * Returns the execution type of an instruction \p inst */ -static enum brw_reg_type -execution_type(const struct brw_isa_info *isa, const brw_inst *inst) +static enum elk_reg_type +execution_type(const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - unsigned num_sources = brw_num_sources_from_inst(isa, inst); - enum brw_reg_type src0_exec_type, src1_exec_type; + unsigned num_sources = elk_num_sources_from_inst(isa, inst); + enum elk_reg_type src0_exec_type, src1_exec_type; /* Execution data type is independent of destination data type, except in * mixed F/HF instructions. */ - enum brw_reg_type dst_exec_type = inst_dst_type(isa, inst); + enum elk_reg_type dst_exec_type = inst_dst_type(isa, inst); - src0_exec_type = execution_type_for_type(brw_inst_src0_type(devinfo, inst)); + src0_exec_type = execution_type_for_type(elk_inst_src0_type(devinfo, inst)); if (num_sources == 1) { - if (src0_exec_type == BRW_REGISTER_TYPE_HF) + if (src0_exec_type == ELK_REGISTER_TYPE_HF) return dst_exec_type; return src0_exec_type; } - src1_exec_type = execution_type_for_type(brw_inst_src1_type(devinfo, inst)); + src1_exec_type = execution_type_for_type(elk_inst_src1_type(devinfo, inst)); if (types_are_mixed_float(src0_exec_type, src1_exec_type) || types_are_mixed_float(src0_exec_type, dst_exec_type) || types_are_mixed_float(src1_exec_type, dst_exec_type)) { - return BRW_REGISTER_TYPE_F; + return ELK_REGISTER_TYPE_F; } if (src0_exec_type == src1_exec_type) return src0_exec_type; - if (src0_exec_type == BRW_REGISTER_TYPE_NF || - src1_exec_type == BRW_REGISTER_TYPE_NF) - return BRW_REGISTER_TYPE_NF; + if (src0_exec_type == ELK_REGISTER_TYPE_NF || + src1_exec_type == ELK_REGISTER_TYPE_NF) + return ELK_REGISTER_TYPE_NF; /* Mixed operand types where one is float is float on Gen < 6 * (and not allowed on later platforms) */ if (devinfo->ver < 6 && - (src0_exec_type == BRW_REGISTER_TYPE_F || - src1_exec_type == BRW_REGISTER_TYPE_F)) - return BRW_REGISTER_TYPE_F; + (src0_exec_type == ELK_REGISTER_TYPE_F || + src1_exec_type == ELK_REGISTER_TYPE_F)) + return ELK_REGISTER_TYPE_F; - if (src0_exec_type == BRW_REGISTER_TYPE_Q || - src1_exec_type == BRW_REGISTER_TYPE_Q) - return BRW_REGISTER_TYPE_Q; + if (src0_exec_type == ELK_REGISTER_TYPE_Q || + src1_exec_type == ELK_REGISTER_TYPE_Q) + return ELK_REGISTER_TYPE_Q; - if (src0_exec_type == BRW_REGISTER_TYPE_D || - src1_exec_type == BRW_REGISTER_TYPE_D) - return BRW_REGISTER_TYPE_D; + if (src0_exec_type == ELK_REGISTER_TYPE_D || + src1_exec_type == ELK_REGISTER_TYPE_D) + return ELK_REGISTER_TYPE_D; - if (src0_exec_type == BRW_REGISTER_TYPE_W || - src1_exec_type == BRW_REGISTER_TYPE_W) - return BRW_REGISTER_TYPE_W; + if (src0_exec_type == ELK_REGISTER_TYPE_W || + src1_exec_type == ELK_REGISTER_TYPE_W) + return ELK_REGISTER_TYPE_W; - if (src0_exec_type == BRW_REGISTER_TYPE_DF || - src1_exec_type == BRW_REGISTER_TYPE_DF) - return BRW_REGISTER_TYPE_DF; + if (src0_exec_type == ELK_REGISTER_TYPE_DF || + src1_exec_type == ELK_REGISTER_TYPE_DF) + return ELK_REGISTER_TYPE_DF; unreachable("not reached"); } @@ -595,24 +595,24 @@ is_linear(unsigned vstride, unsigned width, unsigned hstride) * to/from half-float. */ static bool -is_half_float_conversion(const struct brw_isa_info *isa, - const brw_inst *inst) +is_half_float_conversion(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst); + enum elk_reg_type dst_type = elk_inst_dst_type(devinfo, inst); - unsigned num_sources = brw_num_sources_from_inst(isa, inst); - enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); + enum elk_reg_type src0_type = elk_inst_src0_type(devinfo, inst); if (dst_type != src0_type && - (dst_type == BRW_REGISTER_TYPE_HF || src0_type == BRW_REGISTER_TYPE_HF)) { + (dst_type == ELK_REGISTER_TYPE_HF || src0_type == ELK_REGISTER_TYPE_HF)) { return true; } else if (num_sources > 1) { - enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst); + enum elk_reg_type src1_type = elk_inst_src1_type(devinfo, inst); return dst_type != src1_type && - (dst_type == BRW_REGISTER_TYPE_HF || - src1_type == BRW_REGISTER_TYPE_HF); + (dst_type == ELK_REGISTER_TYPE_HF || + src1_type == ELK_REGISTER_TYPE_HF); } return false; @@ -622,7 +622,7 @@ is_half_float_conversion(const struct brw_isa_info *isa, * Returns whether an instruction is using mixed float operation mode */ static bool -is_mixed_float(const struct brw_isa_info *isa, const brw_inst *inst) +is_mixed_float(const struct elk_isa_info *isa, const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; @@ -632,22 +632,22 @@ is_mixed_float(const struct brw_isa_info *isa, const brw_inst *inst) if (inst_is_send(isa, inst)) return false; - unsigned opcode = brw_inst_opcode(isa, inst); - const struct opcode_desc *desc = brw_opcode_desc(isa, opcode); + unsigned opcode = elk_inst_opcode(isa, inst); + const struct elk_opcode_desc *desc = elk_opcode_desc(isa, opcode); if (desc->ndst == 0) return false; /* FIXME: support 3-src instructions */ - unsigned num_sources = brw_num_sources_from_inst(isa, inst); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); assert(num_sources < 3); - enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst); - enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst); + enum elk_reg_type dst_type = elk_inst_dst_type(devinfo, inst); + enum elk_reg_type src0_type = elk_inst_src0_type(devinfo, inst); if (num_sources == 1) return types_are_mixed_float(src0_type, dst_type); - enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst); + enum elk_reg_type src1_type = elk_inst_src1_type(devinfo, inst); return types_are_mixed_float(src0_type, src1_type) || types_are_mixed_float(src0_type, dst_type) || @@ -659,21 +659,21 @@ is_mixed_float(const struct brw_isa_info *isa, const brw_inst *inst) * to/from byte. */ static bool -is_byte_conversion(const struct brw_isa_info *isa, - const brw_inst *inst) +is_byte_conversion(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst); + enum elk_reg_type dst_type = elk_inst_dst_type(devinfo, inst); - unsigned num_sources = brw_num_sources_from_inst(isa, inst); - enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); + enum elk_reg_type src0_type = elk_inst_src0_type(devinfo, inst); if (dst_type != src0_type && (type_sz(dst_type) == 1 || type_sz(src0_type) == 1)) { return true; } else if (num_sources > 1) { - enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst); + enum elk_reg_type src1_type = elk_inst_src1_type(devinfo, inst); return dst_type != src1_type && (type_sz(dst_type) == 1 || type_sz(src1_type) == 1); } @@ -686,15 +686,15 @@ is_byte_conversion(const struct brw_isa_info *isa, * in the "Register Region Restrictions" section. */ static struct string -general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, - const brw_inst *inst) +general_restrictions_based_on_operand_types(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - const struct opcode_desc *desc = - brw_opcode_desc(isa, brw_inst_opcode(isa, inst)); - unsigned num_sources = brw_num_sources_from_inst(isa, inst); - unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst); + const struct elk_opcode_desc *desc = + elk_opcode_desc(isa, elk_inst_opcode(isa, inst)); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); + unsigned exec_size = 1 << elk_inst_exec_size(devinfo, inst); struct string error_msg = { .str = NULL, .len = 0 }; if (inst_is_send(isa, inst)) @@ -704,66 +704,66 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, /* A register type of B or UB for DPAS actually means 4 bytes packed into * a D or UD, so it is allowed. */ - if (num_sources == 3 && brw_inst_opcode(isa, inst) != BRW_OPCODE_DPAS) { - ERROR_IF(brw_reg_type_to_size(brw_inst_3src_a1_src1_type(devinfo, inst)) == 1 || - brw_reg_type_to_size(brw_inst_3src_a1_src2_type(devinfo, inst)) == 1, + if (num_sources == 3 && elk_inst_opcode(isa, inst) != ELK_OPCODE_DPAS) { + ERROR_IF(elk_reg_type_to_size(elk_inst_3src_a1_src1_type(devinfo, inst)) == 1 || + elk_reg_type_to_size(elk_inst_3src_a1_src2_type(devinfo, inst)) == 1, "Byte data type is not supported for src1/2 register regioning. This includes " "byte broadcast as well."); } if (num_sources == 2) { - ERROR_IF(brw_reg_type_to_size(brw_inst_src1_type(devinfo, inst)) == 1, + ERROR_IF(elk_reg_type_to_size(elk_inst_src1_type(devinfo, inst)) == 1, "Byte data type is not supported for src1 register regioning. This includes " "byte broadcast as well."); } } - enum brw_reg_type dst_type; + enum elk_reg_type dst_type; if (num_sources == 3) { - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) - dst_type = brw_inst_3src_a1_dst_type(devinfo, inst); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) + dst_type = elk_inst_3src_a1_dst_type(devinfo, inst); else - dst_type = brw_inst_3src_a16_dst_type(devinfo, inst); + dst_type = elk_inst_3src_a16_dst_type(devinfo, inst); } else { dst_type = inst_dst_type(isa, inst); } - ERROR_IF(dst_type == BRW_REGISTER_TYPE_DF && + ERROR_IF(dst_type == ELK_REGISTER_TYPE_DF && !devinfo->has_64bit_float, "64-bit float destination, but platform does not support it"); - ERROR_IF((dst_type == BRW_REGISTER_TYPE_Q || - dst_type == BRW_REGISTER_TYPE_UQ) && + ERROR_IF((dst_type == ELK_REGISTER_TYPE_Q || + dst_type == ELK_REGISTER_TYPE_UQ) && !devinfo->has_64bit_int, "64-bit int destination, but platform does not support it"); for (unsigned s = 0; s < num_sources; s++) { - enum brw_reg_type src_type; + enum elk_reg_type src_type; if (num_sources == 3) { - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { switch (s) { - case 0: src_type = brw_inst_3src_a1_src0_type(devinfo, inst); break; - case 1: src_type = brw_inst_3src_a1_src1_type(devinfo, inst); break; - case 2: src_type = brw_inst_3src_a1_src2_type(devinfo, inst); break; + case 0: src_type = elk_inst_3src_a1_src0_type(devinfo, inst); break; + case 1: src_type = elk_inst_3src_a1_src1_type(devinfo, inst); break; + case 2: src_type = elk_inst_3src_a1_src2_type(devinfo, inst); break; default: unreachable("invalid src"); } } else { - src_type = brw_inst_3src_a16_src_type(devinfo, inst); + src_type = elk_inst_3src_a16_src_type(devinfo, inst); } } else { switch (s) { - case 0: src_type = brw_inst_src0_type(devinfo, inst); break; - case 1: src_type = brw_inst_src1_type(devinfo, inst); break; + case 0: src_type = elk_inst_src0_type(devinfo, inst); break; + case 1: src_type = elk_inst_src1_type(devinfo, inst); break; default: unreachable("invalid src"); } } - ERROR_IF(src_type == BRW_REGISTER_TYPE_DF && + ERROR_IF(src_type == ELK_REGISTER_TYPE_DF && !devinfo->has_64bit_float, "64-bit float source, but platform does not support it"); - ERROR_IF((src_type == BRW_REGISTER_TYPE_Q || - src_type == BRW_REGISTER_TYPE_UQ) && + ERROR_IF((src_type == ELK_REGISTER_TYPE_Q || + src_type == ELK_REGISTER_TYPE_UQ) && !devinfo->has_64bit_int, "64-bit int source, but platform does not support it"); } @@ -792,10 +792,10 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, * In fact, checking it would weaken testing of the other rules. */ - unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst)); + unsigned dst_stride = STRIDE(elk_inst_dst_hstride(devinfo, inst)); bool dst_type_is_byte = - inst_dst_type(isa, inst) == BRW_REGISTER_TYPE_B || - inst_dst_type(isa, inst) == BRW_REGISTER_TYPE_UB; + inst_dst_type(isa, inst) == ELK_REGISTER_TYPE_B || + inst_dst_type(isa, inst) == ELK_REGISTER_TYPE_UB; if (dst_type_is_byte) { if (is_packed(exec_size * dst_stride, exec_size, dst_stride)) { @@ -806,8 +806,8 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, } unsigned exec_type = execution_type(isa, inst); - unsigned exec_type_size = brw_reg_type_to_size(exec_type); - unsigned dst_type_size = brw_reg_type_to_size(dst_type); + unsigned exec_type_size = elk_reg_type_to_size(exec_type); + unsigned dst_type_size = elk_reg_type_to_size(dst_type); /* On IVB/BYT, region parameters and execution size for DF are in terms of * 32-bit elements, so they are doubled. For evaluating the validity of an @@ -827,9 +827,9 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, * validate this more generally, since there is the possibility * of implicit conversions from other instructions. */ - enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst); - enum brw_reg_type src1_type = num_sources > 1 ? - brw_inst_src1_type(devinfo, inst) : 0; + enum elk_reg_type src0_type = elk_inst_src0_type(devinfo, inst); + enum elk_reg_type src1_type = num_sources > 1 ? + elk_inst_src1_type(devinfo, inst) : 0; ERROR_IF(type_sz(dst_type) == 1 && (type_sz(src0_type) == 8 || @@ -855,17 +855,17 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, * of implicit conversions from other instructions, such us implicit * conversion from integer to HF with the ADD instruction in SKL+. */ - enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst); - enum brw_reg_type src1_type = num_sources > 1 ? - brw_inst_src1_type(devinfo, inst) : 0; - ERROR_IF(dst_type == BRW_REGISTER_TYPE_HF && + enum elk_reg_type src0_type = elk_inst_src0_type(devinfo, inst); + enum elk_reg_type src1_type = num_sources > 1 ? + elk_inst_src1_type(devinfo, inst) : 0; + ERROR_IF(dst_type == ELK_REGISTER_TYPE_HF && (type_sz(src0_type) == 8 || (num_sources > 1 && type_sz(src1_type) == 8)), "There are no direct conversions between 64-bit types and HF"); ERROR_IF(type_sz(dst_type) == 8 && - (src0_type == BRW_REGISTER_TYPE_HF || - (num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)), + (src0_type == ELK_REGISTER_TYPE_HF || + (num_sources > 1 && src1_type == ELK_REGISTER_TYPE_HF)), "There are no direct conversions between 64-bit types and HF"); /* From the BDW+ PRM: @@ -898,25 +898,25 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, * requires packed destinations, so these restrictions can't possibly * apply to Align16 mode. */ - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - if ((dst_type == BRW_REGISTER_TYPE_HF && - (brw_reg_type_is_integer(src0_type) || - (num_sources > 1 && brw_reg_type_is_integer(src1_type)))) || - (brw_reg_type_is_integer(dst_type) && - (src0_type == BRW_REGISTER_TYPE_HF || - (num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)))) { + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { + if ((dst_type == ELK_REGISTER_TYPE_HF && + (elk_reg_type_is_integer(src0_type) || + (num_sources > 1 && elk_reg_type_is_integer(src1_type)))) || + (elk_reg_type_is_integer(dst_type) && + (src0_type == ELK_REGISTER_TYPE_HF || + (num_sources > 1 && src1_type == ELK_REGISTER_TYPE_HF)))) { ERROR_IF(dst_stride * dst_type_size != 4, "Conversions between integer and half-float must be " "strided by a DWord on the destination"); - unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); + unsigned subreg = elk_inst_dst_da1_subreg_nr(devinfo, inst); ERROR_IF(subreg % 4 != 0, "Conversions between integer and half-float must be " "aligned to a DWord on the destination"); } else if ((devinfo->platform == INTEL_PLATFORM_CHV || devinfo->ver >= 9) && - dst_type == BRW_REGISTER_TYPE_HF) { - unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); + dst_type == ELK_REGISTER_TYPE_HF) { + unsigned subreg = elk_inst_dst_da1_subreg_nr(devinfo, inst); ERROR_IF(dst_stride != 2 && !(is_mixed_float(isa, inst) && dst_stride == 1 && subreg % 16 == 0), @@ -943,10 +943,10 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, "of the execution data type to the destination type"); } - unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); + unsigned subreg = elk_inst_dst_da1_subreg_nr(devinfo, inst); - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && - brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1 && + elk_inst_dst_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) { /* The i965 PRM says: * * Implementation Restriction: The relaxed alignment rule for byte @@ -974,15 +974,15 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, * in the "Register Region Restrictions" section. */ static struct string -general_restrictions_on_region_parameters(const struct brw_isa_info *isa, - const brw_inst *inst) +general_restrictions_on_region_parameters(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - const struct opcode_desc *desc = - brw_opcode_desc(isa, brw_inst_opcode(isa, inst)); - unsigned num_sources = brw_num_sources_from_inst(isa, inst); - unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst); + const struct elk_opcode_desc *desc = + elk_opcode_desc(isa, elk_inst_opcode(isa, inst)); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); + unsigned exec_size = 1 << elk_inst_exec_size(devinfo, inst); struct string error_msg = { .str = NULL, .len = 0 }; if (num_sources == 3) @@ -994,37 +994,37 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa, if (inst_is_split_send(isa, inst)) return (struct string){}; - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16) { + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_16) { if (desc->ndst != 0 && !dst_is_null(devinfo, inst)) - ERROR_IF(brw_inst_dst_hstride(devinfo, inst) != BRW_HORIZONTAL_STRIDE_1, + ERROR_IF(elk_inst_dst_hstride(devinfo, inst) != ELK_HORIZONTAL_STRIDE_1, "Destination Horizontal Stride must be 1"); if (num_sources >= 1) { if (devinfo->verx10 >= 75) { - ERROR_IF(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && - brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && - brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 && - brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, + ERROR_IF(elk_inst_src0_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE && + elk_inst_src0_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_0 && + elk_inst_src0_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_2 && + elk_inst_src0_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_4, "In Align16 mode, only VertStride of 0, 2, or 4 is allowed"); } else { - ERROR_IF(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && - brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && - brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, + ERROR_IF(elk_inst_src0_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE && + elk_inst_src0_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_0 && + elk_inst_src0_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_4, "In Align16 mode, only VertStride of 0 or 4 is allowed"); } } if (num_sources == 2) { if (devinfo->verx10 >= 75) { - ERROR_IF(brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && - brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && - brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 && - brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, + ERROR_IF(elk_inst_src1_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE && + elk_inst_src1_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_0 && + elk_inst_src1_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_2 && + elk_inst_src1_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_4, "In Align16 mode, only VertStride of 0, 2, or 4 is allowed"); } else { - ERROR_IF(brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && - brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && - brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, + ERROR_IF(elk_inst_src1_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE && + elk_inst_src1_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_0 && + elk_inst_src1_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_4, "In Align16 mode, only VertStride of 0 or 4 is allowed"); } } @@ -1034,19 +1034,19 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa, for (unsigned i = 0; i < num_sources; i++) { unsigned vstride, width, hstride, element_size, subreg; - enum brw_reg_type type; + enum elk_reg_type type; #define DO_SRC(n) \ - if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \ - BRW_IMMEDIATE_VALUE) \ + if (elk_inst_src ## n ## _reg_file(devinfo, inst) == \ + ELK_IMMEDIATE_VALUE) \ continue; \ \ - vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \ - width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \ - hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \ - type = brw_inst_src ## n ## _type(devinfo, inst); \ - element_size = brw_reg_type_to_size(type); \ - subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst) + vstride = STRIDE(elk_inst_src ## n ## _vstride(devinfo, inst)); \ + width = WIDTH(elk_inst_src ## n ## _width(devinfo, inst)); \ + hstride = STRIDE(elk_inst_src ## n ## _hstride(devinfo, inst)); \ + type = elk_inst_src ## n ## _type(devinfo, inst); \ + element_size = elk_reg_type_to_size(type); \ + subreg = elk_inst_src ## n ## _da1_subreg_nr(devinfo, inst) if (i == 0) { DO_SRC(0); @@ -1127,7 +1127,7 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa, /* Dst.HorzStride must not be 0. */ if (desc->ndst != 0 && !dst_is_null(devinfo, inst)) { - ERROR_IF(brw_inst_dst_hstride(devinfo, inst) == BRW_HORIZONTAL_STRIDE_0, + ERROR_IF(elk_inst_dst_hstride(devinfo, inst) == ELK_HORIZONTAL_STRIDE_0, "Destination Horizontal Stride must not be 0"); } @@ -1135,30 +1135,30 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa, } static struct string -special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, - const brw_inst *inst) +special_restrictions_for_mixed_float_mode(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; struct string error_msg = { .str = NULL, .len = 0 }; - const unsigned opcode = brw_inst_opcode(isa, inst); - const unsigned num_sources = brw_num_sources_from_inst(isa, inst); + const unsigned opcode = elk_inst_opcode(isa, inst); + const unsigned num_sources = elk_num_sources_from_inst(isa, inst); if (num_sources >= 3) return error_msg; if (!is_mixed_float(isa, inst)) return error_msg; - unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst); - bool is_align16 = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16; + unsigned exec_size = 1 << elk_inst_exec_size(devinfo, inst); + bool is_align16 = elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_16; - enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst); - enum brw_reg_type src1_type = num_sources > 1 ? - brw_inst_src1_type(devinfo, inst) : 0; - enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst); + enum elk_reg_type src0_type = elk_inst_src0_type(devinfo, inst); + enum elk_reg_type src1_type = num_sources > 1 ? + elk_inst_src1_type(devinfo, inst) : 0; + enum elk_reg_type dst_type = elk_inst_dst_type(devinfo, inst); - unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst)); + unsigned dst_stride = STRIDE(elk_inst_dst_hstride(devinfo, inst)); bool dst_is_packed = is_packed(exec_size * dst_stride, exec_size, dst_stride); /* From the SKL PRM, Special Restrictions for Handling Mixed Mode @@ -1167,9 +1167,9 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * "Indirect addressing on source is not supported when source and * destination data types are mixed float." */ - ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT || + ERROR_IF(elk_inst_src0_address_mode(devinfo, inst) != ELK_ADDRESS_DIRECT || (num_sources > 1 && - brw_inst_src1_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT), + elk_inst_src1_address_mode(devinfo, inst) != ELK_ADDRESS_DIRECT), "Indirect addressing on source is not supported when source and " "destination data types are mixed float"); @@ -1179,7 +1179,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * "No SIMD16 in mixed mode when destination is f32. Instruction * execution size must be no more than 8." */ - ERROR_IF(exec_size > 8 && dst_type == BRW_REGISTER_TYPE_F, + ERROR_IF(exec_size > 8 && dst_type == ELK_REGISTER_TYPE_F, "Mixed float mode with 32-bit float destination is limited " "to SIMD8"); @@ -1195,11 +1195,11 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * it means that vertical stride must always be 4, since 0 and 2 would * lead to replicated data, and any other value is disallowed in Align16. */ - ERROR_IF(brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, + ERROR_IF(elk_inst_src0_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_4, "Align16 mixed float mode assumes packed data (vstride must be 4"); ERROR_IF(num_sources >= 2 && - brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, + elk_inst_src1_vstride(devinfo, inst) != ELK_VERTICAL_STRIDE_4, "Align16 mixed float mode assumes packed data (vstride must be 4"); /* From the SKL PRM, Special Restrictions for Handling Mixed Mode @@ -1254,7 +1254,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * Align1 and Align16." */ ERROR_IF(exec_size > 8 && dst_is_packed && - dst_type == BRW_REGISTER_TYPE_HF, + dst_type == ELK_REGISTER_TYPE_HF, "Align1 mixed float mode is limited to SIMD8 when destination " "is packed half-float"); @@ -1264,19 +1264,19 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * "Math operations for mixed mode: * - In Align1, f16 inputs need to be strided" */ - if (opcode == BRW_OPCODE_MATH) { - if (src0_type == BRW_REGISTER_TYPE_HF) { - ERROR_IF(STRIDE(brw_inst_src0_hstride(devinfo, inst)) <= 1, + if (opcode == ELK_OPCODE_MATH) { + if (src0_type == ELK_REGISTER_TYPE_HF) { + ERROR_IF(STRIDE(elk_inst_src0_hstride(devinfo, inst)) <= 1, "Align1 mixed mode math needs strided half-float inputs"); } - if (num_sources >= 2 && src1_type == BRW_REGISTER_TYPE_HF) { - ERROR_IF(STRIDE(brw_inst_src1_hstride(devinfo, inst)) <= 1, + if (num_sources >= 2 && src1_type == ELK_REGISTER_TYPE_HF) { + ERROR_IF(STRIDE(elk_inst_src1_hstride(devinfo, inst)) <= 1, "Align1 mixed mode math needs strided half-float inputs"); } } - if (dst_type == BRW_REGISTER_TYPE_HF && dst_stride == 1) { + if (dst_type == ELK_REGISTER_TYPE_HF && dst_stride == 1) { /* From the SKL PRM, Special Restrictions for Handling Mixed Mode * Float Operations: * @@ -1289,10 +1289,10 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * aligned data means that execution size is limited to 8. */ unsigned subreg; - if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) - subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); + if (elk_inst_dst_address_mode(devinfo, inst) == ELK_ADDRESS_DIRECT) + subreg = elk_inst_dst_da1_subreg_nr(devinfo, inst); else - subreg = brw_inst_dst_ia_subreg_nr(devinfo, inst); + subreg = elk_inst_dst_ia_subreg_nr(devinfo, inst); ERROR_IF(subreg % 16 != 0, "Align1 mixed mode packed half-float output must be " "oword aligned"); @@ -1311,9 +1311,9 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * so we only need to check this for Align1. */ if (src0_is_acc(devinfo, inst) && - (src0_type == BRW_REGISTER_TYPE_F || - src0_type == BRW_REGISTER_TYPE_HF)) { - ERROR_IF(brw_inst_src0_da1_subreg_nr(devinfo, inst) != 0, + (src0_type == ELK_REGISTER_TYPE_F || + src0_type == ELK_REGISTER_TYPE_HF)) { + ERROR_IF(elk_inst_src0_da1_subreg_nr(devinfo, inst) != 0, "Mixed float mode requires register-aligned accumulator " "source reads when destination is packed half-float"); @@ -1321,9 +1321,9 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, if (num_sources > 1 && src1_is_acc(devinfo, inst) && - (src1_type == BRW_REGISTER_TYPE_F || - src1_type == BRW_REGISTER_TYPE_HF)) { - ERROR_IF(brw_inst_src1_da1_subreg_nr(devinfo, inst) != 0, + (src1_type == ELK_REGISTER_TYPE_F || + src1_type == ELK_REGISTER_TYPE_HF)) { + ERROR_IF(elk_inst_src1_da1_subreg_nr(devinfo, inst) != 0, "Mixed float mode requires register-aligned accumulator " "source reads when destination is packed half-float"); } @@ -1341,7 +1341,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, * or its link to the implication described after it, so we only * validate the explicit implication, which is clearly described. */ - if (dst_type == BRW_REGISTER_TYPE_HF && + if (dst_type == ELK_REGISTER_TYPE_HF && inst_uses_src_acc(isa, inst)) { ERROR_IF(dst_stride != 2, "Mixed float mode with implicit/explicit accumulator " @@ -1418,21 +1418,21 @@ registers_read(const uint64_t access_mask[static 32]) * Region Restrictions" section. */ static struct string -region_alignment_rules(const struct brw_isa_info *isa, - const brw_inst *inst) +region_alignment_rules(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - const struct opcode_desc *desc = - brw_opcode_desc(isa, brw_inst_opcode(isa, inst)); - unsigned num_sources = brw_num_sources_from_inst(isa, inst); - unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst); + const struct elk_opcode_desc *desc = + elk_opcode_desc(isa, elk_inst_opcode(isa, inst)); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); + unsigned exec_size = 1 << elk_inst_exec_size(devinfo, inst); uint64_t dst_access_mask[32], src0_access_mask[32], src1_access_mask[32]; struct string error_msg = { .str = NULL, .len = 0 }; if (num_sources == 3) return (struct string){}; - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16) + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_16) return (struct string){}; if (inst_is_send(isa, inst)) @@ -1444,27 +1444,27 @@ region_alignment_rules(const struct brw_isa_info *isa, for (unsigned i = 0; i < num_sources; i++) { unsigned vstride, width, hstride, element_size, subreg; - enum brw_reg_type type; + enum elk_reg_type type; /* In Direct Addressing mode, a source cannot span more than 2 adjacent * GRF registers. */ #define DO_SRC(n) \ - if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \ - BRW_ADDRESS_DIRECT) \ + if (elk_inst_src ## n ## _address_mode(devinfo, inst) != \ + ELK_ADDRESS_DIRECT) \ continue; \ \ - if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \ - BRW_IMMEDIATE_VALUE) \ + if (elk_inst_src ## n ## _reg_file(devinfo, inst) == \ + ELK_IMMEDIATE_VALUE) \ continue; \ \ - vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \ - width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \ - hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \ - type = brw_inst_src ## n ## _type(devinfo, inst); \ - element_size = brw_reg_type_to_size(type); \ - subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \ + vstride = STRIDE(elk_inst_src ## n ## _vstride(devinfo, inst)); \ + width = WIDTH(elk_inst_src ## n ## _width(devinfo, inst)); \ + hstride = STRIDE(elk_inst_src ## n ## _hstride(devinfo, inst)); \ + type = elk_inst_src ## n ## _type(devinfo, inst); \ + element_size = elk_reg_type_to_size(type); \ + subreg = elk_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \ align1_access_mask(src ## n ## _access_mask, \ exec_size, element_size, subreg, \ vstride, width, hstride) @@ -1489,10 +1489,10 @@ region_alignment_rules(const struct brw_isa_info *isa, if (desc->ndst == 0 || dst_is_null(devinfo, inst)) return error_msg; - unsigned stride = STRIDE(brw_inst_dst_hstride(devinfo, inst)); - enum brw_reg_type dst_type = inst_dst_type(isa, inst); - unsigned element_size = brw_reg_type_to_size(dst_type); - unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); + unsigned stride = STRIDE(elk_inst_dst_hstride(devinfo, inst)); + enum elk_reg_type dst_type = inst_dst_type(isa, inst); + unsigned element_size = elk_reg_type_to_size(dst_type); + unsigned subreg = elk_inst_dst_da1_subreg_nr(devinfo, inst); unsigned offset = ((exec_size - 1) * stride * element_size) + subreg; ERROR_IF(offset >= 64 * reg_unit(devinfo), "A destination cannot span more than 2 adjacent GRF registers"); @@ -1576,7 +1576,7 @@ region_alignment_rules(const struct brw_isa_info *isa, * SKL. */ if (devinfo->ver <= 8 || - brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) { + elk_inst_opcode(isa, inst) == ELK_OPCODE_MATH) { /* Nothing explicitly states that on Gen < 8 elements must be evenly * split between two destination registers in the two exceptional @@ -1647,7 +1647,7 @@ region_alignment_rules(const struct brw_isa_info *isa, } \ \ unsigned offset_0 = \ - brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \ + elk_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \ unsigned offset_1 = offset_0; \ \ for (unsigned i = 0; i < exec_size; i++) { \ @@ -1688,8 +1688,8 @@ region_alignment_rules(const struct brw_isa_info *isa, * destination must be an integer DWord, the hardware allows at least a * float destination type as well. We emit such instructions from * - * fs_visitor::emit_interpolation_setup_gfx6 - * fs_visitor::emit_fragcoord_interpolation + * elk_fs_visitor::emit_interpolation_setup_gfx6 + * elk_fs_visitor::emit_fragcoord_interpolation * * and have for years with no ill effects. * @@ -1707,21 +1707,21 @@ region_alignment_rules(const struct brw_isa_info *isa, * for src1. */ if (devinfo->ver <= 7 && dst_regs == 2) { - enum brw_reg_type dst_type = inst_dst_type(isa, inst); + enum elk_reg_type dst_type = inst_dst_type(isa, inst); bool dst_is_packed_dword = is_packed(exec_size * stride, exec_size, stride) && - brw_reg_type_to_size(dst_type) == 4; + elk_reg_type_to_size(dst_type) == 4; for (unsigned i = 0; i < num_sources; i++) { #define DO_SRC(n) \ unsigned vstride, width, hstride; \ - vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \ - width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \ - hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \ + vstride = STRIDE(elk_inst_src ## n ## _vstride(devinfo, inst)); \ + width = WIDTH(elk_inst_src ## n ## _width(devinfo, inst)); \ + hstride = STRIDE(elk_inst_src ## n ## _hstride(devinfo, inst)); \ bool src ## n ## _is_packed_word = \ n != 1 && is_packed(vstride, width, hstride) && \ - (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \ - brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \ + (elk_inst_src ## n ## _type(devinfo, inst) == ELK_REGISTER_TYPE_W || \ + elk_inst_src ## n ## _type(devinfo, inst) == ELK_REGISTER_TYPE_UW); \ \ ERROR_IF(src ## n ## _regs == 1 && \ !src ## n ## _has_scalar_region(devinfo, inst) && \ @@ -1743,12 +1743,12 @@ region_alignment_rules(const struct brw_isa_info *isa, } static struct string -vector_immediate_restrictions(const struct brw_isa_info *isa, - const brw_inst *inst) +vector_immediate_restrictions(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - unsigned num_sources = brw_num_sources_from_inst(isa, inst); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); struct string error_msg = { .str = NULL, .len = 0 }; if (num_sources == 3 || num_sources == 0 || @@ -1756,19 +1756,19 @@ vector_immediate_restrictions(const struct brw_isa_info *isa, return (struct string){}; unsigned file = num_sources == 1 ? - brw_inst_src0_reg_file(devinfo, inst) : - brw_inst_src1_reg_file(devinfo, inst); - if (file != BRW_IMMEDIATE_VALUE) + elk_inst_src0_reg_file(devinfo, inst) : + elk_inst_src1_reg_file(devinfo, inst); + if (file != ELK_IMMEDIATE_VALUE) return (struct string){}; - enum brw_reg_type dst_type = inst_dst_type(isa, inst); - unsigned dst_type_size = brw_reg_type_to_size(dst_type); - unsigned dst_subreg = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 ? - brw_inst_dst_da1_subreg_nr(devinfo, inst) : 0; - unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst)); - enum brw_reg_type type = num_sources == 1 ? - brw_inst_src0_type(devinfo, inst) : - brw_inst_src1_type(devinfo, inst); + enum elk_reg_type dst_type = inst_dst_type(isa, inst); + unsigned dst_type_size = elk_reg_type_to_size(dst_type); + unsigned dst_subreg = elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1 ? + elk_inst_dst_da1_subreg_nr(devinfo, inst) : 0; + unsigned dst_stride = STRIDE(elk_inst_dst_hstride(devinfo, inst)); + enum elk_reg_type type = num_sources == 1 ? + elk_inst_src0_type(devinfo, inst) : + elk_inst_src1_type(devinfo, inst); /* The PRMs say: * @@ -1782,14 +1782,14 @@ vector_immediate_restrictions(const struct brw_isa_info *isa, * applies. */ switch (type) { - case BRW_REGISTER_TYPE_V: - case BRW_REGISTER_TYPE_UV: - case BRW_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_VF: ERROR_IF(dst_subreg % (128 / 8) != 0, "Destination must be 128-bit aligned in order to use immediate " "vector types"); - if (type == BRW_REGISTER_TYPE_VF) { + if (type == ELK_REGISTER_TYPE_VF) { ERROR_IF(dst_type_size * dst_stride != 4, "Destination must have stride equivalent to dword in order " "to use the VF type"); @@ -1808,12 +1808,12 @@ vector_immediate_restrictions(const struct brw_isa_info *isa, static struct string special_requirements_for_handling_double_precision_data_types( - const struct brw_isa_info *isa, - const brw_inst *inst) + const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - unsigned num_sources = brw_num_sources_from_inst(isa, inst); + unsigned num_sources = elk_num_sources_from_inst(isa, inst); struct string error_msg = { .str = NULL, .len = 0 }; if (num_sources == 3 || num_sources == 0) @@ -1823,24 +1823,24 @@ special_requirements_for_handling_double_precision_data_types( if (inst_is_split_send(isa, inst)) return (struct string){}; - enum brw_reg_type exec_type = execution_type(isa, inst); - unsigned exec_type_size = brw_reg_type_to_size(exec_type); + enum elk_reg_type exec_type = execution_type(isa, inst); + unsigned exec_type_size = elk_reg_type_to_size(exec_type); - enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, inst); - enum brw_reg_type dst_type = inst_dst_type(isa, inst); - unsigned dst_type_size = brw_reg_type_to_size(dst_type); - unsigned dst_hstride = STRIDE(brw_inst_dst_hstride(devinfo, inst)); - unsigned dst_reg = brw_inst_dst_da_reg_nr(devinfo, inst); - unsigned dst_subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); - unsigned dst_address_mode = brw_inst_dst_address_mode(devinfo, inst); + enum elk_reg_file dst_file = elk_inst_dst_reg_file(devinfo, inst); + enum elk_reg_type dst_type = inst_dst_type(isa, inst); + unsigned dst_type_size = elk_reg_type_to_size(dst_type); + unsigned dst_hstride = STRIDE(elk_inst_dst_hstride(devinfo, inst)); + unsigned dst_reg = elk_inst_dst_da_reg_nr(devinfo, inst); + unsigned dst_subreg = elk_inst_dst_da1_subreg_nr(devinfo, inst); + unsigned dst_address_mode = elk_inst_dst_address_mode(devinfo, inst); bool is_integer_dword_multiply = devinfo->ver >= 8 && - brw_inst_opcode(isa, inst) == BRW_OPCODE_MUL && - (brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_D || - brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UD) && - (brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_D || - brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_UD); + elk_inst_opcode(isa, inst) == ELK_OPCODE_MUL && + (elk_inst_src0_type(devinfo, inst) == ELK_REGISTER_TYPE_D || + elk_inst_src0_type(devinfo, inst) == ELK_REGISTER_TYPE_UD) && + (elk_inst_src1_type(devinfo, inst) == ELK_REGISTER_TYPE_D || + elk_inst_src1_type(devinfo, inst) == ELK_REGISTER_TYPE_UD); const bool is_double_precision = dst_type_size == 8 || exec_type_size == 8 || is_integer_dword_multiply; @@ -1848,24 +1848,24 @@ special_requirements_for_handling_double_precision_data_types( for (unsigned i = 0; i < num_sources; i++) { unsigned vstride, width, hstride, type_size, reg, subreg, address_mode; bool is_scalar_region; - enum brw_reg_file file; - enum brw_reg_type type; + enum elk_reg_file file; + enum elk_reg_type type; #define DO_SRC(n) \ - if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \ - BRW_IMMEDIATE_VALUE) \ + if (elk_inst_src ## n ## _reg_file(devinfo, inst) == \ + ELK_IMMEDIATE_VALUE) \ continue; \ \ is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \ - vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \ - width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \ - hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \ - file = brw_inst_src ## n ## _reg_file(devinfo, inst); \ - type = brw_inst_src ## n ## _type(devinfo, inst); \ - type_size = brw_reg_type_to_size(type); \ - reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \ - subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \ - address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst) + vstride = STRIDE(elk_inst_src ## n ## _vstride(devinfo, inst)); \ + width = WIDTH(elk_inst_src ## n ## _width(devinfo, inst)); \ + hstride = STRIDE(elk_inst_src ## n ## _hstride(devinfo, inst)); \ + file = elk_inst_src ## n ## _reg_file(devinfo, inst); \ + type = elk_inst_src ## n ## _type(devinfo, inst); \ + type_size = elk_reg_type_to_size(type); \ + reg = elk_inst_src ## n ## _da_reg_nr(devinfo, inst); \ + subreg = elk_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \ + address_mode = elk_inst_src ## n ## _address_mode(devinfo, inst) if (i == 0) { DO_SRC(0); @@ -1891,7 +1891,7 @@ special_requirements_for_handling_double_precision_data_types( * We assume that the restriction applies to GLK as well. */ if (is_double_precision && - brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && + elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1 && (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) { ERROR_IF(!is_scalar_region && (src_stride % 8 != 0 || @@ -1918,8 +1918,8 @@ special_requirements_for_handling_double_precision_data_types( */ if (is_double_precision && (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) { - ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == address_mode || - BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == dst_address_mode, + ERROR_IF(ELK_ADDRESS_REGISTER_INDIRECT_REGISTER == address_mode || + ELK_ADDRESS_REGISTER_INDIRECT_REGISTER == dst_address_mode, "Indirect addressing is not allowed when the execution type " "is 64-bit"); } @@ -1936,12 +1936,12 @@ special_requirements_for_handling_double_precision_data_types( if (is_double_precision && (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) { - ERROR_IF(brw_inst_opcode(isa, inst) == BRW_OPCODE_MAC || - brw_inst_acc_wr_control(devinfo, inst) || - (BRW_ARCHITECTURE_REGISTER_FILE == file && - reg != BRW_ARF_NULL) || - (BRW_ARCHITECTURE_REGISTER_FILE == dst_file && - dst_reg != BRW_ARF_NULL), + ERROR_IF(elk_inst_opcode(isa, inst) == ELK_OPCODE_MAC || + elk_inst_acc_wr_control(devinfo, inst) || + (ELK_ARCHITECTURE_REGISTER_FILE == file && + reg != ELK_ARF_NULL) || + (ELK_ARCHITECTURE_REGISTER_FILE == dst_file && + dst_reg != ELK_ARF_NULL), "Architecture registers cannot be used when the execution " "type is 64-bit"); } @@ -1966,10 +1966,10 @@ special_requirements_for_handling_double_precision_data_types( * used." */ if (devinfo->verx10 >= 125 && - (brw_reg_type_is_floating_point(dst_type) || + (elk_reg_type_is_floating_point(dst_type) || is_double_precision)) { ERROR_IF(!is_scalar_region && - BRW_ADDRESS_REGISTER_INDIRECT_REGISTER != address_mode && + ELK_ADDRESS_REGISTER_INDIRECT_REGISTER != address_mode && (!is_linear(vstride, width, hstride) || src_stride != dst_stride || subreg != dst_subreg), @@ -1978,10 +1978,10 @@ special_requirements_for_handling_double_precision_data_types( "source and destination are not supported except for " "broadcast of a scalar."); - ERROR_IF((address_mode == BRW_ADDRESS_DIRECT && file == BRW_ARCHITECTURE_REGISTER_FILE && - reg != BRW_ARF_NULL && !(reg >= BRW_ARF_ACCUMULATOR && reg < BRW_ARF_FLAG)) || - (dst_file == BRW_ARCHITECTURE_REGISTER_FILE && - dst_reg != BRW_ARF_NULL && dst_reg != BRW_ARF_ACCUMULATOR), + ERROR_IF((address_mode == ELK_ADDRESS_DIRECT && file == ELK_ARCHITECTURE_REGISTER_FILE && + reg != ELK_ARF_NULL && !(reg >= ELK_ARF_ACCUMULATOR && reg < ELK_ARF_FLAG)) || + (dst_file == ELK_ARCHITECTURE_REGISTER_FILE && + dst_reg != ELK_ARF_NULL && dst_reg != ELK_ARF_ACCUMULATOR), "Explicit ARF registers except null and accumulator must not " "be used."); } @@ -1992,9 +1992,9 @@ special_requirements_for_handling_double_precision_data_types( * Quad-Word data must not be used." */ if (devinfo->verx10 >= 125 && - (brw_reg_type_is_floating_point(type) || type_sz(type) == 8)) { - ERROR_IF(address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER && - vstride == BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, + (elk_reg_type_is_floating_point(type) || type_sz(type) == 8)) { + ERROR_IF(address_mode == ELK_ADDRESS_REGISTER_INDIRECT_REGISTER && + vstride == ELK_VERTICAL_STRIDE_ONE_DIMENSIONAL, "Vx1 and VxH indirect addressing for Float, Half-Float, " "Double-Float and Quad-Word data must not be used"); } @@ -2008,16 +2008,16 @@ special_requirements_for_handling_double_precision_data_types( * We assume that the restriction applies to all Gfx8+ parts. */ if (is_double_precision && devinfo->ver >= 8) { - enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst); - enum brw_reg_type src1_type = - num_sources > 1 ? brw_inst_src1_type(devinfo, inst) : src0_type; - unsigned src0_type_size = brw_reg_type_to_size(src0_type); - unsigned src1_type_size = brw_reg_type_to_size(src1_type); + enum elk_reg_type src0_type = elk_inst_src0_type(devinfo, inst); + enum elk_reg_type src1_type = + num_sources > 1 ? elk_inst_src1_type(devinfo, inst) : src0_type; + unsigned src0_type_size = elk_reg_type_to_size(src0_type); + unsigned src1_type_size = elk_reg_type_to_size(src1_type); - ERROR_IF(brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16 && + ERROR_IF(elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_16 && dst_type_size == 8 && (src0_type_size != 8 || src1_type_size != 8) && - brw_inst_exec_size(devinfo, inst) > BRW_EXECUTE_2, + elk_inst_exec_size(devinfo, inst) > ELK_EXECUTE_2, "In Align16 exec size cannot exceed 2 with a QWord destination " "and a non-QWord source"); } @@ -2031,8 +2031,8 @@ special_requirements_for_handling_double_precision_data_types( */ if (is_double_precision && (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) { - ERROR_IF(brw_inst_no_dd_check(devinfo, inst) || - brw_inst_no_dd_clear(devinfo, inst), + ERROR_IF(elk_inst_no_dd_check(devinfo, inst) || + elk_inst_no_dd_clear(devinfo, inst), "DepCtrl is not allowed when the execution type is 64-bit"); } @@ -2040,8 +2040,8 @@ special_requirements_for_handling_double_precision_data_types( } static struct string -instruction_restrictions(const struct brw_isa_info *isa, - const brw_inst *inst) +instruction_restrictions(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; struct string error_msg = { .str = NULL, .len = 0 }; @@ -2052,25 +2052,25 @@ instruction_restrictions(const struct brw_isa_info *isa, * is not supported." */ if (devinfo->ver >= 12 && - brw_inst_opcode(isa, inst) == BRW_OPCODE_MUL) { - enum brw_reg_type exec_type = execution_type(isa, inst); - const bool src0_valid = type_sz(brw_inst_src0_type(devinfo, inst)) == 4 || - brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE || - !(brw_inst_src0_negate(devinfo, inst) || - brw_inst_src0_abs(devinfo, inst)); - const bool src1_valid = type_sz(brw_inst_src1_type(devinfo, inst)) == 4 || - brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE || - !(brw_inst_src1_negate(devinfo, inst) || - brw_inst_src1_abs(devinfo, inst)); + elk_inst_opcode(isa, inst) == ELK_OPCODE_MUL) { + enum elk_reg_type exec_type = execution_type(isa, inst); + const bool src0_valid = type_sz(elk_inst_src0_type(devinfo, inst)) == 4 || + elk_inst_src0_reg_file(devinfo, inst) == ELK_IMMEDIATE_VALUE || + !(elk_inst_src0_negate(devinfo, inst) || + elk_inst_src0_abs(devinfo, inst)); + const bool src1_valid = type_sz(elk_inst_src1_type(devinfo, inst)) == 4 || + elk_inst_src1_reg_file(devinfo, inst) == ELK_IMMEDIATE_VALUE || + !(elk_inst_src1_negate(devinfo, inst) || + elk_inst_src1_abs(devinfo, inst)); - ERROR_IF(!brw_reg_type_is_floating_point(exec_type) && + ERROR_IF(!elk_reg_type_is_floating_point(exec_type) && type_sz(exec_type) == 4 && !(src0_valid && src1_valid), "When multiplying a DW and any lower precision integer, source " "modifier is not supported."); } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_CMP || - brw_inst_opcode(isa, inst) == BRW_OPCODE_CMPN) { + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_CMP || + elk_inst_opcode(isa, inst) == ELK_OPCODE_CMPN) { if (devinfo->ver <= 7) { /* Page 166 of the Ivy Bridge PRM Volume 4 part 3 (Execution Unit * ISA) says: @@ -2086,8 +2086,8 @@ instruction_restrictions(const struct brw_isa_info *isa, * For the cmp and cmpn instructions, remove the accumulator * restrictions. */ - ERROR_IF(brw_inst_dst_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && - brw_inst_dst_da_reg_nr(devinfo, inst) != BRW_ARF_NULL, + ERROR_IF(elk_inst_dst_reg_file(devinfo, inst) == ELK_ARCHITECTURE_REGISTER_FILE && + elk_inst_dst_da_reg_nr(devinfo, inst) != ELK_ARF_NULL, "Accumulator cannot be destination, implicit or explicit."); } @@ -2101,32 +2101,32 @@ instruction_restrictions(const struct brw_isa_info *isa, */ if (devinfo->ver == 7) { ERROR_IF(dst_is_null(devinfo, inst) && - brw_inst_thread_control(devinfo, inst) != BRW_THREAD_SWITCH, + elk_inst_thread_control(devinfo, inst) != ELK_THREAD_SWITCH, "If the destination is the null register, the {Switch} " "instruction option must be used."); } - ERROR_IF(brw_inst_cond_modifier(devinfo, inst) == BRW_CONDITIONAL_NONE, + ERROR_IF(elk_inst_cond_modifier(devinfo, inst) == ELK_CONDITIONAL_NONE, "CMP (or CMPN) must have a condition."); } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_SEL) { + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_SEL) { if (devinfo->ver < 6) { - ERROR_IF(brw_inst_cond_modifier(devinfo, inst) != BRW_CONDITIONAL_NONE, + ERROR_IF(elk_inst_cond_modifier(devinfo, inst) != ELK_CONDITIONAL_NONE, "SEL must not have a condition modifier"); - ERROR_IF(brw_inst_pred_control(devinfo, inst) == BRW_PREDICATE_NONE, + ERROR_IF(elk_inst_pred_control(devinfo, inst) == ELK_PREDICATE_NONE, "SEL must be predicated"); } else { - ERROR_IF((brw_inst_cond_modifier(devinfo, inst) != BRW_CONDITIONAL_NONE) == - (brw_inst_pred_control(devinfo, inst) != BRW_PREDICATE_NONE), + ERROR_IF((elk_inst_cond_modifier(devinfo, inst) != ELK_CONDITIONAL_NONE) == + (elk_inst_pred_control(devinfo, inst) != ELK_PREDICATE_NONE), "SEL must either be predicated or have a condition modifiers"); } } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_MUL) { - const enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst); - const enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst); - const enum brw_reg_type dst_type = inst_dst_type(isa, inst); + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_MUL) { + const enum elk_reg_type src0_type = elk_inst_src0_type(devinfo, inst); + const enum elk_reg_type src1_type = elk_inst_src1_type(devinfo, inst); + const enum elk_reg_type dst_type = inst_dst_type(isa, inst); if (devinfo->ver == 6) { /* Page 223 of the Sandybridge PRM volume 4 part 2 says: @@ -2136,7 +2136,7 @@ instruction_restrictions(const struct brw_isa_info *isa, * * This text appears only in the Sandybridge PRMw. */ - ERROR_IF(brw_reg_type_is_integer(src0_type) && + ERROR_IF(elk_reg_type_is_integer(src0_type) && type_sz(src0_type) == 4 && type_sz(src1_type) < 4, "When multiplying a DW and any lower precision integer, the " "DW operand must be src1."); @@ -2149,7 +2149,7 @@ instruction_restrictions(const struct brw_isa_info *isa, * Ivy Bridge, Haswell, Skylake, and Ice Lake PRMs contain the same * text. */ - ERROR_IF(brw_reg_type_is_integer(src1_type) && + ERROR_IF(elk_reg_type_is_integer(src1_type) && type_sz(src0_type) < 4 && type_sz(src1_type) == 4, "When multiplying a DW and any lower precision integer, the " "DW operand must be src0."); @@ -2176,9 +2176,9 @@ instruction_restrictions(const struct brw_isa_info *isa, * The Skylake and Ice Lake PRMs contain the same text. */ ERROR_IF((src0_is_acc(devinfo, inst) && - brw_reg_type_is_integer(src0_type)) || + elk_reg_type_is_integer(src0_type)) || (src1_is_acc(devinfo, inst) && - brw_reg_type_is_integer(src1_type)), + elk_reg_type_is_integer(src1_type)), "Integer source operands cannot be accumulators."); } @@ -2194,11 +2194,11 @@ instruction_restrictions(const struct brw_isa_info *isa, * allow mixed source types at all, but that restriction should be * handled elsewhere. */ - ERROR_IF(execution_type(isa, inst) == BRW_REGISTER_TYPE_F && - (src0_type == BRW_REGISTER_TYPE_UD || - src0_type == BRW_REGISTER_TYPE_D || - src1_type == BRW_REGISTER_TYPE_UD || - src1_type == BRW_REGISTER_TYPE_D), + ERROR_IF(execution_type(isa, inst) == ELK_REGISTER_TYPE_F && + (src0_type == ELK_REGISTER_TYPE_UD || + src0_type == ELK_REGISTER_TYPE_D || + src1_type == ELK_REGISTER_TYPE_UD || + src1_type == ELK_REGISTER_TYPE_D), "Dword integer source is not allowed for this instruction in" "float execution mode."); } @@ -2215,11 +2215,11 @@ instruction_restrictions(const struct brw_isa_info *isa, * Later GPUs do not allow mixed source and destination types at all, * but that restriction should be handled elsewhere. */ - ERROR_IF(dst_type == BRW_REGISTER_TYPE_F && - (src0_type == BRW_REGISTER_TYPE_UD || - src0_type == BRW_REGISTER_TYPE_D || - src1_type == BRW_REGISTER_TYPE_UD || - src1_type == BRW_REGISTER_TYPE_D), + ERROR_IF(dst_type == ELK_REGISTER_TYPE_F && + (src0_type == ELK_REGISTER_TYPE_UD || + src0_type == ELK_REGISTER_TYPE_D || + src1_type == ELK_REGISTER_TYPE_UD || + src1_type == ELK_REGISTER_TYPE_D), "Float destination type not allowed with DWord source type."); } @@ -2232,12 +2232,12 @@ instruction_restrictions(const struct brw_isa_info *isa, * This text also appears in the Cherry Trail / Braswell PRM, but it * does not appear in any other PRM. */ - ERROR_IF((src0_type == BRW_REGISTER_TYPE_UD || - src0_type == BRW_REGISTER_TYPE_D) && - (src1_type == BRW_REGISTER_TYPE_UD || - src1_type == BRW_REGISTER_TYPE_D) && - brw_inst_dst_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE && - brw_inst_dst_da_reg_nr(devinfo, inst) != BRW_ARF_NULL, + ERROR_IF((src0_type == ELK_REGISTER_TYPE_UD || + src0_type == ELK_REGISTER_TYPE_D) && + (src1_type == ELK_REGISTER_TYPE_UD || + src1_type == ELK_REGISTER_TYPE_D) && + elk_inst_dst_reg_file(devinfo, inst) == ELK_ARCHITECTURE_REGISTER_FILE && + elk_inst_dst_da_reg_nr(devinfo, inst) != ELK_ARF_NULL, "When multiplying DW x DW, the dst cannot be accumulator."); } @@ -2259,34 +2259,34 @@ instruction_restrictions(const struct brw_isa_info *isa, * be used." I have interpreted it as the latter primarily because that * is the more restrictive interpretation. */ - ERROR_IF((src0_type == BRW_REGISTER_TYPE_UD || - src0_type == BRW_REGISTER_TYPE_D || - src1_type == BRW_REGISTER_TYPE_UD || - src1_type == BRW_REGISTER_TYPE_D) && - (dst_type == BRW_REGISTER_TYPE_UD || - dst_type == BRW_REGISTER_TYPE_D || - dst_type == BRW_REGISTER_TYPE_UW || - dst_type == BRW_REGISTER_TYPE_W) && - (brw_inst_saturate(devinfo, inst) != 0 || - brw_inst_cond_modifier(devinfo, inst) != BRW_CONDITIONAL_NONE), + ERROR_IF((src0_type == ELK_REGISTER_TYPE_UD || + src0_type == ELK_REGISTER_TYPE_D || + src1_type == ELK_REGISTER_TYPE_UD || + src1_type == ELK_REGISTER_TYPE_D) && + (dst_type == ELK_REGISTER_TYPE_UD || + dst_type == ELK_REGISTER_TYPE_D || + dst_type == ELK_REGISTER_TYPE_UW || + dst_type == ELK_REGISTER_TYPE_W) && + (elk_inst_saturate(devinfo, inst) != 0 || + elk_inst_cond_modifier(devinfo, inst) != ELK_CONDITIONAL_NONE), "Neither Saturate nor conditional modifier allowed with DW " "integer multiply."); } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) { - unsigned math_function = brw_inst_math_function(devinfo, inst); + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_MATH) { + unsigned math_function = elk_inst_math_function(devinfo, inst); switch (math_function) { - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT: - case BRW_MATH_FUNCTION_INT_DIV_REMAINDER: { + case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER: + case ELK_MATH_FUNCTION_INT_DIV_QUOTIENT: + case ELK_MATH_FUNCTION_INT_DIV_REMAINDER: { /* Page 442 of the Broadwell PRM Volume 2a "Extended Math Function" says: * INT DIV function does not support source modifiers. * Bspec 6647 extends it back to Ivy Bridge. */ - bool src0_valid = !brw_inst_src0_negate(devinfo, inst) && - !brw_inst_src0_abs(devinfo, inst); - bool src1_valid = !brw_inst_src1_negate(devinfo, inst) && - !brw_inst_src1_abs(devinfo, inst); + bool src0_valid = !elk_inst_src0_negate(devinfo, inst) && + !elk_inst_src0_abs(devinfo, inst); + bool src1_valid = !elk_inst_src1_negate(devinfo, inst) && + !elk_inst_src1_abs(devinfo, inst); ERROR_IF(!src0_valid || !src1_valid, "INT DIV function does not support source modifiers."); break; @@ -2296,7 +2296,7 @@ instruction_restrictions(const struct brw_isa_info *isa, } } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_DP4A) { + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_DP4A) { /* Page 396 (page 412 of the PDF) of the DG1 PRM volume 2a says: * * Only one of src0 or src1 operand may be an the (sic) accumulator @@ -2308,61 +2308,61 @@ instruction_restrictions(const struct brw_isa_info *isa, } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_ADD3) { - const enum brw_reg_type dst_type = inst_dst_type(isa, inst); + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_ADD3) { + const enum elk_reg_type dst_type = inst_dst_type(isa, inst); - ERROR_IF(dst_type != BRW_REGISTER_TYPE_D && - dst_type != BRW_REGISTER_TYPE_UD && - dst_type != BRW_REGISTER_TYPE_W && - dst_type != BRW_REGISTER_TYPE_UW, + ERROR_IF(dst_type != ELK_REGISTER_TYPE_D && + dst_type != ELK_REGISTER_TYPE_UD && + dst_type != ELK_REGISTER_TYPE_W && + dst_type != ELK_REGISTER_TYPE_UW, "Destination must be integer D, UD, W, or UW type."); for (unsigned i = 0; i < 3; i++) { - enum brw_reg_type src_type; + enum elk_reg_type src_type; switch (i) { - case 0: src_type = brw_inst_3src_a1_src0_type(devinfo, inst); break; - case 1: src_type = brw_inst_3src_a1_src1_type(devinfo, inst); break; - case 2: src_type = brw_inst_3src_a1_src2_type(devinfo, inst); break; + case 0: src_type = elk_inst_3src_a1_src0_type(devinfo, inst); break; + case 1: src_type = elk_inst_3src_a1_src1_type(devinfo, inst); break; + case 2: src_type = elk_inst_3src_a1_src2_type(devinfo, inst); break; default: unreachable("invalid src"); } - ERROR_IF(src_type != BRW_REGISTER_TYPE_D && - src_type != BRW_REGISTER_TYPE_UD && - src_type != BRW_REGISTER_TYPE_W && - src_type != BRW_REGISTER_TYPE_UW, + ERROR_IF(src_type != ELK_REGISTER_TYPE_D && + src_type != ELK_REGISTER_TYPE_UD && + src_type != ELK_REGISTER_TYPE_W && + src_type != ELK_REGISTER_TYPE_UW, "Source must be integer D, UD, W, or UW type."); if (i == 0) { - if (brw_inst_3src_a1_src0_is_imm(devinfo, inst)) { - ERROR_IF(src_type != BRW_REGISTER_TYPE_W && - src_type != BRW_REGISTER_TYPE_UW, + if (elk_inst_3src_a1_src0_is_imm(devinfo, inst)) { + ERROR_IF(src_type != ELK_REGISTER_TYPE_W && + src_type != ELK_REGISTER_TYPE_UW, "Immediate source must be integer W or UW type."); } } else if (i == 2) { - if (brw_inst_3src_a1_src2_is_imm(devinfo, inst)) { - ERROR_IF(src_type != BRW_REGISTER_TYPE_W && - src_type != BRW_REGISTER_TYPE_UW, + if (elk_inst_3src_a1_src2_is_imm(devinfo, inst)) { + ERROR_IF(src_type != ELK_REGISTER_TYPE_W && + src_type != ELK_REGISTER_TYPE_UW, "Immediate source must be integer W or UW type."); } } } } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_OR || - brw_inst_opcode(isa, inst) == BRW_OPCODE_AND || - brw_inst_opcode(isa, inst) == BRW_OPCODE_XOR || - brw_inst_opcode(isa, inst) == BRW_OPCODE_NOT) { + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_OR || + elk_inst_opcode(isa, inst) == ELK_OPCODE_AND || + elk_inst_opcode(isa, inst) == ELK_OPCODE_XOR || + elk_inst_opcode(isa, inst) == ELK_OPCODE_NOT) { if (devinfo->ver >= 8) { /* While the behavior of the negate source modifier is defined as * logical not, the behavior of abs source modifier is not * defined. Disallow it to be safe. */ - ERROR_IF(brw_inst_src0_abs(devinfo, inst), + ERROR_IF(elk_inst_src0_abs(devinfo, inst), "Behavior of abs source modifier in logic ops is undefined."); - ERROR_IF(brw_inst_opcode(isa, inst) != BRW_OPCODE_NOT && - brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && - brw_inst_src1_abs(devinfo, inst), + ERROR_IF(elk_inst_opcode(isa, inst) != ELK_OPCODE_NOT && + elk_inst_src1_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE && + elk_inst_src1_abs(devinfo, inst), "Behavior of abs source modifier in logic ops is undefined."); /* Page 479 (page 495 of the PDF) of the Broadwell PRM volume 2a says: @@ -2371,13 +2371,13 @@ instruction_restrictions(const struct brw_isa_info *isa, * * The same text also appears for OR, NOT, and XOR instructions. */ - ERROR_IF((brw_inst_src0_abs(devinfo, inst) || - brw_inst_src0_negate(devinfo, inst)) && + ERROR_IF((elk_inst_src0_abs(devinfo, inst) || + elk_inst_src0_negate(devinfo, inst)) && src0_is_acc(devinfo, inst), "Source modifier is not allowed if source is an accumulator."); - ERROR_IF(brw_num_sources_from_inst(isa, inst) > 1 && - (brw_inst_src1_abs(devinfo, inst) || - brw_inst_src1_negate(devinfo, inst)) && + ERROR_IF(elk_num_sources_from_inst(isa, inst) > 1 && + (elk_inst_src1_abs(devinfo, inst) || + elk_inst_src1_negate(devinfo, inst)) && src1_is_acc(devinfo, inst), "Source modifier is not allowed if source is an accumulator."); } @@ -2389,49 +2389,49 @@ instruction_restrictions(const struct brw_isa_info *isa, * * The same text also appears for OR, NOT, and XOR instructions. * - * Per the comment around nir_op_imod in brw_fs_nir.cpp, we have + * Per the comment around nir_op_imod in elk_fs_nir.cpp, we have * determined this to not be true. The only conditions that seem * absolutely sketchy are O, R, and U. Some OpenGL shaders from Doom * 2016 have been observed to generate and.g and operate correctly. */ - const enum brw_conditional_mod cmod = - brw_inst_cond_modifier(devinfo, inst); - ERROR_IF(cmod == BRW_CONDITIONAL_O || - cmod == BRW_CONDITIONAL_R || - cmod == BRW_CONDITIONAL_U, + const enum elk_conditional_mod cmod = + elk_inst_cond_modifier(devinfo, inst); + ERROR_IF(cmod == ELK_CONDITIONAL_O || + cmod == ELK_CONDITIONAL_R || + cmod == ELK_CONDITIONAL_U, "O, R, and U conditional modifiers should not be used."); } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_BFI2) { - ERROR_IF(brw_inst_cond_modifier(devinfo, inst) != BRW_CONDITIONAL_NONE, + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_BFI2) { + ERROR_IF(elk_inst_cond_modifier(devinfo, inst) != ELK_CONDITIONAL_NONE, "BFI2 cannot have conditional modifier"); - ERROR_IF(brw_inst_saturate(devinfo, inst), + ERROR_IF(elk_inst_saturate(devinfo, inst), "BFI2 cannot have saturate modifier"); - enum brw_reg_type dst_type; + enum elk_reg_type dst_type; - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) - dst_type = brw_inst_3src_a1_dst_type(devinfo, inst); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) + dst_type = elk_inst_3src_a1_dst_type(devinfo, inst); else - dst_type = brw_inst_3src_a16_dst_type(devinfo, inst); + dst_type = elk_inst_3src_a16_dst_type(devinfo, inst); - ERROR_IF(dst_type != BRW_REGISTER_TYPE_D && - dst_type != BRW_REGISTER_TYPE_UD, + ERROR_IF(dst_type != ELK_REGISTER_TYPE_D && + dst_type != ELK_REGISTER_TYPE_UD, "BFI2 destination type must be D or UD"); for (unsigned s = 0; s < 3; s++) { - enum brw_reg_type src_type; + enum elk_reg_type src_type; - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { switch (s) { - case 0: src_type = brw_inst_3src_a1_src0_type(devinfo, inst); break; - case 1: src_type = brw_inst_3src_a1_src1_type(devinfo, inst); break; - case 2: src_type = brw_inst_3src_a1_src2_type(devinfo, inst); break; + case 0: src_type = elk_inst_3src_a1_src0_type(devinfo, inst); break; + case 1: src_type = elk_inst_3src_a1_src1_type(devinfo, inst); break; + case 2: src_type = elk_inst_3src_a1_src2_type(devinfo, inst); break; default: unreachable("invalid src"); } } else { - src_type = brw_inst_3src_a16_src_type(devinfo, inst); + src_type = elk_inst_3src_a16_src_type(devinfo, inst); } ERROR_IF(src_type != dst_type, @@ -2439,48 +2439,48 @@ instruction_restrictions(const struct brw_isa_info *isa, } } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_CSEL) { - ERROR_IF(brw_inst_pred_control(devinfo, inst) != BRW_PREDICATE_NONE, + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_CSEL) { + ERROR_IF(elk_inst_pred_control(devinfo, inst) != ELK_PREDICATE_NONE, "CSEL cannot be predicated"); /* CSEL is CMP and SEL fused into one. The condition modifier, which * does not actually modify the flags, controls the built-in comparison. */ - ERROR_IF(brw_inst_cond_modifier(devinfo, inst) == BRW_CONDITIONAL_NONE, + ERROR_IF(elk_inst_cond_modifier(devinfo, inst) == ELK_CONDITIONAL_NONE, "CSEL must have a condition."); - enum brw_reg_type dst_type; + enum elk_reg_type dst_type; - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) - dst_type = brw_inst_3src_a1_dst_type(devinfo, inst); + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) + dst_type = elk_inst_3src_a1_dst_type(devinfo, inst); else - dst_type = brw_inst_3src_a16_dst_type(devinfo, inst); + dst_type = elk_inst_3src_a16_dst_type(devinfo, inst); if (devinfo->ver < 8) { ERROR_IF(devinfo->ver < 8, "CSEL not supported before Gfx8"); } else if (devinfo->ver <= 9) { - ERROR_IF(dst_type != BRW_REGISTER_TYPE_F, + ERROR_IF(dst_type != ELK_REGISTER_TYPE_F, "CSEL destination type must be F"); } else { - ERROR_IF(dst_type != BRW_REGISTER_TYPE_F && - dst_type != BRW_REGISTER_TYPE_HF && - dst_type != BRW_REGISTER_TYPE_D && - dst_type != BRW_REGISTER_TYPE_W, + ERROR_IF(dst_type != ELK_REGISTER_TYPE_F && + dst_type != ELK_REGISTER_TYPE_HF && + dst_type != ELK_REGISTER_TYPE_D && + dst_type != ELK_REGISTER_TYPE_W, "CSEL destination type must be F, HF, D, or W"); } for (unsigned s = 0; s < 3; s++) { - enum brw_reg_type src_type; + enum elk_reg_type src_type; - if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { + if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) { switch (s) { - case 0: src_type = brw_inst_3src_a1_src0_type(devinfo, inst); break; - case 1: src_type = brw_inst_3src_a1_src1_type(devinfo, inst); break; - case 2: src_type = brw_inst_3src_a1_src2_type(devinfo, inst); break; + case 0: src_type = elk_inst_3src_a1_src0_type(devinfo, inst); break; + case 1: src_type = elk_inst_3src_a1_src1_type(devinfo, inst); break; + case 2: src_type = elk_inst_3src_a1_src2_type(devinfo, inst); break; default: unreachable("invalid src"); } } else { - src_type = brw_inst_3src_a16_src_type(devinfo, inst); + src_type = elk_inst_3src_a16_src_type(devinfo, inst); } ERROR_IF(src_type != dst_type, @@ -2488,68 +2488,68 @@ instruction_restrictions(const struct brw_isa_info *isa, } } - if (brw_inst_opcode(isa, inst) == BRW_OPCODE_DPAS) { - ERROR_IF(brw_inst_dpas_3src_sdepth(devinfo, inst) != BRW_SYSTOLIC_DEPTH_8, + if (elk_inst_opcode(isa, inst) == ELK_OPCODE_DPAS) { + ERROR_IF(elk_inst_dpas_3src_sdepth(devinfo, inst) != ELK_SYSTOLIC_DEPTH_8, "Systolic depth must be 8."); const unsigned sdepth = 8; - const enum brw_reg_type dst_type = - brw_inst_dpas_3src_dst_type(devinfo, inst); - const enum brw_reg_type src0_type = - brw_inst_dpas_3src_src0_type(devinfo, inst); - const enum brw_reg_type src1_type = - brw_inst_dpas_3src_src1_type(devinfo, inst); - const enum brw_reg_type src2_type = - brw_inst_dpas_3src_src2_type(devinfo, inst); + const enum elk_reg_type dst_type = + elk_inst_dpas_3src_dst_type(devinfo, inst); + const enum elk_reg_type src0_type = + elk_inst_dpas_3src_src0_type(devinfo, inst); + const enum elk_reg_type src1_type = + elk_inst_dpas_3src_src1_type(devinfo, inst); + const enum elk_reg_type src2_type = + elk_inst_dpas_3src_src2_type(devinfo, inst); const enum gfx12_sub_byte_precision src1_sub_byte = - brw_inst_dpas_3src_src1_subbyte(devinfo, inst); + elk_inst_dpas_3src_src1_subbyte(devinfo, inst); - if (src1_type != BRW_REGISTER_TYPE_B && src1_type != BRW_REGISTER_TYPE_UB) { - ERROR_IF(src1_sub_byte != BRW_SUB_BYTE_PRECISION_NONE, + if (src1_type != ELK_REGISTER_TYPE_B && src1_type != ELK_REGISTER_TYPE_UB) { + ERROR_IF(src1_sub_byte != ELK_SUB_BYTE_PRECISION_NONE, "Sub-byte precision must be None for source type larger than Byte."); } else { - ERROR_IF(src1_sub_byte != BRW_SUB_BYTE_PRECISION_NONE && - src1_sub_byte != BRW_SUB_BYTE_PRECISION_4BIT && - src1_sub_byte != BRW_SUB_BYTE_PRECISION_2BIT, + ERROR_IF(src1_sub_byte != ELK_SUB_BYTE_PRECISION_NONE && + src1_sub_byte != ELK_SUB_BYTE_PRECISION_4BIT && + src1_sub_byte != ELK_SUB_BYTE_PRECISION_2BIT, "Invalid sub-byte precision."); } const enum gfx12_sub_byte_precision src2_sub_byte = - brw_inst_dpas_3src_src2_subbyte(devinfo, inst); + elk_inst_dpas_3src_src2_subbyte(devinfo, inst); - if (src2_type != BRW_REGISTER_TYPE_B && src2_type != BRW_REGISTER_TYPE_UB) { - ERROR_IF(src2_sub_byte != BRW_SUB_BYTE_PRECISION_NONE, + if (src2_type != ELK_REGISTER_TYPE_B && src2_type != ELK_REGISTER_TYPE_UB) { + ERROR_IF(src2_sub_byte != ELK_SUB_BYTE_PRECISION_NONE, "Sub-byte precision must be None."); } else { - ERROR_IF(src2_sub_byte != BRW_SUB_BYTE_PRECISION_NONE && - src2_sub_byte != BRW_SUB_BYTE_PRECISION_4BIT && - src2_sub_byte != BRW_SUB_BYTE_PRECISION_2BIT, + ERROR_IF(src2_sub_byte != ELK_SUB_BYTE_PRECISION_NONE && + src2_sub_byte != ELK_SUB_BYTE_PRECISION_4BIT && + src2_sub_byte != ELK_SUB_BYTE_PRECISION_2BIT, "Invalid sub-byte precision."); } const unsigned src1_bits_per_element = - (8 * brw_reg_type_to_size(src1_type)) >> - brw_inst_dpas_3src_src1_subbyte(devinfo, inst); + (8 * elk_reg_type_to_size(src1_type)) >> + elk_inst_dpas_3src_src1_subbyte(devinfo, inst); const unsigned src2_bits_per_element = - (8 * brw_reg_type_to_size(src2_type)) >> - brw_inst_dpas_3src_src2_subbyte(devinfo, inst); + (8 * elk_reg_type_to_size(src2_type)) >> + elk_inst_dpas_3src_src2_subbyte(devinfo, inst); /* The MAX2(1, ...) is just to prevent possible division by 0 later. */ const unsigned ops_per_chan = MAX2(1, 32 / MAX2(src1_bits_per_element, src2_bits_per_element)); - ERROR_IF(brw_inst_exec_size(devinfo, inst) != BRW_EXECUTE_8, + ERROR_IF(elk_inst_exec_size(devinfo, inst) != ELK_EXECUTE_8, "DPAS execution size must be 8."); const unsigned exec_size = 8; - const unsigned dst_subnr = brw_inst_dpas_3src_dst_subreg_nr(devinfo, inst); - const unsigned src0_subnr = brw_inst_dpas_3src_src0_subreg_nr(devinfo, inst); - const unsigned src1_subnr = brw_inst_dpas_3src_src1_subreg_nr(devinfo, inst); - const unsigned src2_subnr = brw_inst_dpas_3src_src2_subreg_nr(devinfo, inst); + const unsigned dst_subnr = elk_inst_dpas_3src_dst_subreg_nr(devinfo, inst); + const unsigned src0_subnr = elk_inst_dpas_3src_src0_subreg_nr(devinfo, inst); + const unsigned src1_subnr = elk_inst_dpas_3src_src1_subreg_nr(devinfo, inst); + const unsigned src2_subnr = elk_inst_dpas_3src_src2_subreg_nr(devinfo, inst); /* Until HF is supported as dst type, this is effectively subnr == 0. */ ERROR_IF(dst_subnr % exec_size != 0, @@ -2582,7 +2582,7 @@ instruction_restrictions(const struct brw_isa_info *isa, ERROR_IF((src2_subnr * type_sz(src2_type) * src2_bits_per_element) / 8 >= REG_SIZE, "Src2 subregister specifies next register."); - if (brw_inst_3src_atomic_control(devinfo, inst)) { + if (elk_inst_3src_atomic_control(devinfo, inst)) { /* FINISHME: When we start emitting DPAS with Atomic set, figure out * a way to validate it. Also add a test in test_eu_validate.cpp. */ @@ -2591,34 +2591,34 @@ instruction_restrictions(const struct brw_isa_info *isa, "DPAS instruction."); } - if (brw_inst_dpas_3src_exec_type(devinfo, inst) == - BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT) { - ERROR_IF(dst_type != BRW_REGISTER_TYPE_F, + if (elk_inst_dpas_3src_exec_type(devinfo, inst) == + ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT) { + ERROR_IF(dst_type != ELK_REGISTER_TYPE_F, "DPAS destination type must be F."); - ERROR_IF(src0_type != BRW_REGISTER_TYPE_F, + ERROR_IF(src0_type != ELK_REGISTER_TYPE_F, "DPAS src0 type must be F."); - ERROR_IF(src1_type != BRW_REGISTER_TYPE_HF, + ERROR_IF(src1_type != ELK_REGISTER_TYPE_HF, "DPAS src1 type must be HF."); - ERROR_IF(src2_type != BRW_REGISTER_TYPE_HF, + ERROR_IF(src2_type != ELK_REGISTER_TYPE_HF, "DPAS src2 type must be HF."); } else { - ERROR_IF(dst_type != BRW_REGISTER_TYPE_D && - dst_type != BRW_REGISTER_TYPE_UD, + ERROR_IF(dst_type != ELK_REGISTER_TYPE_D && + dst_type != ELK_REGISTER_TYPE_UD, "DPAS destination type must be D or UD."); - ERROR_IF(src0_type != BRW_REGISTER_TYPE_D && - src0_type != BRW_REGISTER_TYPE_UD, + ERROR_IF(src0_type != ELK_REGISTER_TYPE_D && + src0_type != ELK_REGISTER_TYPE_UD, "DPAS src0 type must be D or UD."); - ERROR_IF(src1_type != BRW_REGISTER_TYPE_B && - src1_type != BRW_REGISTER_TYPE_UB, + ERROR_IF(src1_type != ELK_REGISTER_TYPE_B && + src1_type != ELK_REGISTER_TYPE_UB, "DPAS src1 base type must be B or UB."); - ERROR_IF(src2_type != BRW_REGISTER_TYPE_B && - src2_type != BRW_REGISTER_TYPE_UB, + ERROR_IF(src2_type != ELK_REGISTER_TYPE_B && + src2_type != ELK_REGISTER_TYPE_UB, "DPAS src2 base type must be B or UB."); - if (brw_reg_type_is_unsigned_integer(dst_type)) { - ERROR_IF(!brw_reg_type_is_unsigned_integer(src0_type) || - !brw_reg_type_is_unsigned_integer(src1_type) || - !brw_reg_type_is_unsigned_integer(src2_type), + if (elk_reg_type_is_unsigned_integer(dst_type)) { + ERROR_IF(!elk_reg_type_is_unsigned_integer(src0_type) || + !elk_reg_type_is_unsigned_integer(src1_type) || + !elk_reg_type_is_unsigned_integer(src2_type), "If any source datatype is signed, destination datatype " "must be signed."); } @@ -2628,7 +2628,7 @@ instruction_restrictions(const struct brw_isa_info *isa, * yet enforced here: * * - General Accumulator registers access is not supported. This is - * currently enforced in brw_dpas_three_src (brw_eu_emit.c). + * currently enforced in elk_dpas_three_src (elk_eu_emit.c). * * - Given any combination of datatypes in the sources of a DPAS * instructions, the boundaries of a register should not be crossed. @@ -2639,28 +2639,28 @@ instruction_restrictions(const struct brw_isa_info *isa, } static struct string -send_descriptor_restrictions(const struct brw_isa_info *isa, - const brw_inst *inst) +send_descriptor_restrictions(const struct elk_isa_info *isa, + const elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; struct string error_msg = { .str = NULL, .len = 0 }; if (inst_is_split_send(isa, inst)) { /* We can only validate immediate descriptors */ - if (brw_inst_send_sel_reg32_desc(devinfo, inst)) + if (elk_inst_send_sel_reg32_desc(devinfo, inst)) return error_msg; } else if (inst_is_send(isa, inst)) { /* We can only validate immediate descriptors */ - if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) + if (elk_inst_src1_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE) return error_msg; } else { return error_msg; } - const uint32_t desc = brw_inst_send_desc(devinfo, inst); + const uint32_t desc = elk_inst_send_desc(devinfo, inst); - switch (brw_inst_sfid(devinfo, inst)) { - case BRW_SFID_URB: + switch (elk_inst_sfid(devinfo, inst)) { + case ELK_SFID_URB: if (devinfo->ver < 20) break; FALLTHROUGH; @@ -2669,9 +2669,9 @@ send_descriptor_restrictions(const struct brw_isa_info *isa, case GFX12_SFID_UGM: ERROR_IF(!devinfo->has_lsc, "Platform does not support LSC"); - ERROR_IF(lsc_opcode_has_transpose(lsc_msg_desc_opcode(devinfo, desc)) && + ERROR_IF(elk_lsc_opcode_has_transpose(lsc_msg_desc_opcode(devinfo, desc)) && lsc_msg_desc_transpose(devinfo, desc) && - brw_inst_exec_size(devinfo, inst) != BRW_EXECUTE_1, + elk_inst_exec_size(devinfo, inst) != ELK_EXECUTE_1, "Transposed vectors are restricted to Exec_Mask = 1."); break; @@ -2679,28 +2679,28 @@ send_descriptor_restrictions(const struct brw_isa_info *isa, break; } - if (brw_inst_sfid(devinfo, inst) == BRW_SFID_URB && devinfo->ver < 20) { + if (elk_inst_sfid(devinfo, inst) == ELK_SFID_URB && devinfo->ver < 20) { /* Gfx4 doesn't have a "header present" bit in the SEND message. */ - ERROR_IF(devinfo->ver > 4 && !brw_inst_header_present(devinfo, inst), + ERROR_IF(devinfo->ver > 4 && !elk_inst_header_present(devinfo, inst), "Header must be present for all URB messages."); - switch (brw_inst_urb_opcode(devinfo, inst)) { - case BRW_URB_OPCODE_WRITE_HWORD: + switch (elk_inst_urb_opcode(devinfo, inst)) { + case ELK_URB_OPCODE_WRITE_HWORD: break; /* case FF_SYNC: */ - case BRW_URB_OPCODE_WRITE_OWORD: + case ELK_URB_OPCODE_WRITE_OWORD: /* Gfx5 / Gfx6 FF_SYNC message and Gfx7+ URB_WRITE_OWORD have the * same opcode value. */ if (devinfo->ver == 5 || devinfo->ver == 6) { - ERROR_IF(brw_inst_urb_global_offset(devinfo, inst) != 0, + ERROR_IF(elk_inst_urb_global_offset(devinfo, inst) != 0, "FF_SYNC global offset must be zero."); - ERROR_IF(brw_inst_urb_swizzle_control(devinfo, inst) != 0, + ERROR_IF(elk_inst_urb_swizzle_control(devinfo, inst) != 0, "FF_SYNC swizzle control must be zero."); - ERROR_IF(brw_inst_urb_used(devinfo, inst) != 0, + ERROR_IF(elk_inst_urb_used(devinfo, inst) != 0, "FF_SYNC used must be zero."); - ERROR_IF(brw_inst_urb_complete(devinfo, inst) != 0, + ERROR_IF(elk_inst_urb_complete(devinfo, inst) != 0, "FF_SYNC complete must be zero."); /* Volume 4 part 2 of the Sandybridge PRM (page 28) says: @@ -2709,7 +2709,7 @@ send_descriptor_restrictions(const struct brw_isa_info *isa, * indicated on the ‘send’ instruction if the thread requires * response data and/or synchronization. */ - ERROR_IF((unsigned)brw_inst_rlen(devinfo, inst) > 1, + ERROR_IF((unsigned)elk_inst_rlen(devinfo, inst) > 1, "FF_SYNC read length must be 0 or 1."); } else { ERROR_IF(devinfo->ver < 7, @@ -2717,8 +2717,8 @@ send_descriptor_restrictions(const struct brw_isa_info *isa, } break; - case BRW_URB_OPCODE_READ_HWORD: - case BRW_URB_OPCODE_READ_OWORD: + case ELK_URB_OPCODE_READ_HWORD: + case ELK_URB_OPCODE_READ_OWORD: ERROR_IF(devinfo->ver < 7, "URB read messages only valid on gfx >= 7"); break; @@ -2736,7 +2736,7 @@ send_descriptor_restrictions(const struct brw_isa_info *isa, break; case GFX8_URB_OPCODE_SIMD8_READ: - ERROR_IF(brw_inst_rlen(devinfo, inst) == 0, + ERROR_IF(elk_inst_rlen(devinfo, inst) == 0, "URB SIMD8 read message must read some data."); FALLTHROUGH; @@ -2760,10 +2760,10 @@ send_descriptor_restrictions(const struct brw_isa_info *isa, } bool -brw_validate_instruction(const struct brw_isa_info *isa, - const brw_inst *inst, int offset, +elk_validate_instruction(const struct elk_isa_info *isa, + const elk_inst *inst, int offset, unsigned inst_size, - struct disasm_info *disasm) + struct elk_disasm_info *disasm) { struct string error_msg = { .str = NULL, .len = 0 }; @@ -2788,7 +2788,7 @@ brw_validate_instruction(const struct brw_isa_info *isa, } if (error_msg.str && disasm) { - disasm_insert_error(disasm, offset, inst_size, error_msg.str); + elk_disasm_insert_error(disasm, offset, inst_size, error_msg.str); } free(error_msg.str); @@ -2796,27 +2796,27 @@ brw_validate_instruction(const struct brw_isa_info *isa, } bool -brw_validate_instructions(const struct brw_isa_info *isa, +elk_validate_instructions(const struct elk_isa_info *isa, const void *assembly, int start_offset, int end_offset, - struct disasm_info *disasm) + struct elk_disasm_info *disasm) { const struct intel_device_info *devinfo = isa->devinfo; bool valid = true; for (int src_offset = start_offset; src_offset < end_offset;) { - const brw_inst *inst = assembly + src_offset; - bool is_compact = brw_inst_cmpt_control(devinfo, inst); - unsigned inst_size = is_compact ? sizeof(brw_compact_inst) - : sizeof(brw_inst); - brw_inst uncompacted; + const elk_inst *inst = assembly + src_offset; + bool is_compact = elk_inst_cmpt_control(devinfo, inst); + unsigned inst_size = is_compact ? sizeof(elk_compact_inst) + : sizeof(elk_inst); + elk_inst uncompacted; if (is_compact) { - brw_compact_inst *compacted = (void *)inst; - brw_uncompact_instruction(isa, &uncompacted, compacted); + elk_compact_inst *compacted = (void *)inst; + elk_uncompact_instruction(isa, &uncompacted, compacted); inst = &uncompacted; } - bool v = brw_validate_instruction(isa, inst, src_offset, + bool v = elk_validate_instruction(isa, inst, src_offset, inst_size, disasm); valid = valid && v; diff --git a/src/intel/compiler/elk/elk_fs.cpp b/src/intel/compiler/elk/elk_fs.cpp index 5a90adf2f0b..0298995cbc9 100644 --- a/src/intel/compiler/elk/elk_fs.cpp +++ b/src/intel/compiler/elk/elk_fs.cpp @@ -49,16 +49,16 @@ using namespace elk; -static unsigned get_lowered_simd_width(const fs_visitor *shader, - const fs_inst *inst); +static unsigned get_lowered_simd_width(const elk_fs_visitor *shader, + const elk_fs_inst *inst); void -fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg *src, unsigned sources) +elk_fs_inst::init(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst, + const elk_fs_reg *src, unsigned sources) { memset((void*)this, 0, sizeof(*this)); - this->src = new fs_reg[MAX2(sources, 3)]; + this->src = new elk_fs_reg[MAX2(sources, 3)]; for (unsigned i = 0; i < sources; i++) this->src[i] = src[i]; @@ -72,7 +72,7 @@ fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, assert(this->exec_size != 0); - this->conditional_mod = BRW_CONDITIONAL_NONE; + this->conditional_mod = ELK_CONDITIONAL_NONE; /* This will be the case for almost all instructions. */ switch (dst.file) { @@ -94,68 +94,68 @@ fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, this->writes_accumulator = false; } -fs_inst::fs_inst() +elk_fs_inst::elk_fs_inst() { - init(BRW_OPCODE_NOP, 8, dst, NULL, 0); + init(ELK_OPCODE_NOP, 8, dst, NULL, 0); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size) +elk_fs_inst::elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size) { init(opcode, exec_size, reg_undef, NULL, 0); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst) +elk_fs_inst::elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst) { init(opcode, exec_size, dst, NULL, 0); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0) +elk_fs_inst::elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst, + const elk_fs_reg &src0) { - const fs_reg src[1] = { src0 }; + const elk_fs_reg src[1] = { src0 }; init(opcode, exec_size, dst, src, 1); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0, const fs_reg &src1) +elk_fs_inst::elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst, + const elk_fs_reg &src0, const elk_fs_reg &src1) { - const fs_reg src[2] = { src0, src1 }; + const elk_fs_reg src[2] = { src0, src1 }; init(opcode, exec_size, dst, src, 2); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0, const fs_reg &src1, const fs_reg &src2) +elk_fs_inst::elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst, + const elk_fs_reg &src0, const elk_fs_reg &src1, const elk_fs_reg &src2) { - const fs_reg src[3] = { src0, src1, src2 }; + const elk_fs_reg src[3] = { src0, src1, src2 }; init(opcode, exec_size, dst, src, 3); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst, - const fs_reg src[], unsigned sources) +elk_fs_inst::elk_fs_inst(enum elk_opcode opcode, uint8_t exec_width, const elk_fs_reg &dst, + const elk_fs_reg src[], unsigned sources) { init(opcode, exec_width, dst, src, sources); } -fs_inst::fs_inst(const fs_inst &that) +elk_fs_inst::elk_fs_inst(const elk_fs_inst &that) { memcpy((void*)this, &that, sizeof(that)); - this->src = new fs_reg[MAX2(that.sources, 3)]; + this->src = new elk_fs_reg[MAX2(that.sources, 3)]; for (unsigned i = 0; i < that.sources; i++) this->src[i] = that.src[i]; } -fs_inst::~fs_inst() +elk_fs_inst::~elk_fs_inst() { delete[] this->src; } void -fs_inst::resize_sources(uint8_t num_sources) +elk_fs_inst::resize_sources(uint8_t num_sources) { if (this->sources != num_sources) { - fs_reg *src = new fs_reg[MAX2(num_sources, 3)]; + elk_fs_reg *src = new elk_fs_reg[MAX2(num_sources, 3)]; for (unsigned i = 0; i < MIN2(this->sources, num_sources); ++i) src[i] = this->src[i]; @@ -167,11 +167,11 @@ fs_inst::resize_sources(uint8_t num_sources) } void -fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld, - const fs_reg &dst, - const fs_reg &surface, - const fs_reg &surface_handle, - const fs_reg &varying_offset, +elk_fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld, + const elk_fs_reg &dst, + const elk_fs_reg &surface, + const elk_fs_reg &surface_handle, + const elk_fs_reg &varying_offset, uint32_t const_offset, uint8_t alignment, unsigned components) @@ -182,8 +182,8 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld, * be any component of a vector, and then we load 4 contiguous * components starting from that. TODO: Support loading fewer than 4. */ - fs_reg total_offset = vgrf(glsl_uint_type()); - bld.ADD(total_offset, varying_offset, brw_imm_ud(const_offset)); + elk_fs_reg total_offset = vgrf(glsl_uint_type()); + bld.ADD(total_offset, varying_offset, elk_imm_ud(const_offset)); /* The pull load message will load a vec4 (16 bytes). If we are loading * a double this means we are only loading 2 elements worth of data. @@ -191,19 +191,19 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld, * so other parts of the driver don't get confused about the size of the * result. */ - fs_reg vec4_result = bld.vgrf(BRW_REGISTER_TYPE_F, 4); + elk_fs_reg vec4_result = bld.vgrf(ELK_REGISTER_TYPE_F, 4); - fs_reg srcs[PULL_VARYING_CONSTANT_SRCS]; + elk_fs_reg srcs[PULL_VARYING_CONSTANT_SRCS]; srcs[PULL_VARYING_CONSTANT_SRC_SURFACE] = surface; srcs[PULL_VARYING_CONSTANT_SRC_SURFACE_HANDLE] = surface_handle; srcs[PULL_VARYING_CONSTANT_SRC_OFFSET] = total_offset; - srcs[PULL_VARYING_CONSTANT_SRC_ALIGNMENT] = brw_imm_ud(alignment); + srcs[PULL_VARYING_CONSTANT_SRC_ALIGNMENT] = elk_imm_ud(alignment); - fs_inst *inst = bld.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, + elk_fs_inst *inst = bld.emit(ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, vec4_result, srcs, PULL_VARYING_CONSTANT_SRCS); inst->size_written = 4 * vec4_result.component_size(inst->exec_size); - shuffle_from_32bit_read(bld, dst, vec4_result, 0, components); + elk_shuffle_from_32bit_read(bld, dst, vec4_result, 0, components); } /** @@ -211,7 +211,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld, * handling. */ void -fs_visitor::DEP_RESOLVE_MOV(const fs_builder &bld, int grf) +elk_fs_visitor::DEP_RESOLVE_MOV(const fs_builder &bld, int grf) { /* The caller always wants uncompressed to emit the minimal extra * dependencies, and to avoid having to deal with aligning its regs to 2. @@ -219,25 +219,25 @@ fs_visitor::DEP_RESOLVE_MOV(const fs_builder &bld, int grf) const fs_builder ubld = bld.annotate("send dependency resolve") .quarter(0); - ubld.MOV(ubld.null_reg_f(), fs_reg(VGRF, grf, BRW_REGISTER_TYPE_F)); + ubld.MOV(ubld.null_reg_f(), elk_fs_reg(VGRF, grf, ELK_REGISTER_TYPE_F)); } bool -fs_inst::is_send_from_grf() const +elk_fs_inst::is_send_from_grf() const { switch (opcode) { - case SHADER_OPCODE_SEND: - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: - case SHADER_OPCODE_INTERLOCK: - case SHADER_OPCODE_MEMORY_FENCE: - case SHADER_OPCODE_BARRIER: + case ELK_SHADER_OPCODE_SEND: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_SHADER_OPCODE_INTERLOCK: + case ELK_SHADER_OPCODE_MEMORY_FENCE: + case ELK_SHADER_OPCODE_BARRIER: return true; - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: return src[1].file == VGRF; - case FS_OPCODE_FB_WRITE: - case FS_OPCODE_FB_READ: + case ELK_FS_OPCODE_FB_WRITE: + case ELK_FS_OPCODE_FB_READ: return src[0].file == VGRF; default: return false; @@ -245,42 +245,42 @@ fs_inst::is_send_from_grf() const } bool -fs_inst::is_control_source(unsigned arg) const +elk_fs_inst::is_control_source(unsigned arg) const { switch (opcode) { - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: return arg == 0; - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_SHUFFLE: - case SHADER_OPCODE_QUAD_SWIZZLE: - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: return arg == 1; - case SHADER_OPCODE_MOV_INDIRECT: - case SHADER_OPCODE_CLUSTER_BROADCAST: - case SHADER_OPCODE_TEX: - case FS_OPCODE_TXB: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_LZ: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_UMS: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXL_LZ: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_LOD: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: + case ELK_SHADER_OPCODE_TEX: + case ELK_FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_UMS: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL_LZ: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_SAMPLEINFO: return arg == 1 || arg == 2; - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: return arg == 0 || arg == 1; default: @@ -289,39 +289,39 @@ fs_inst::is_control_source(unsigned arg) const } bool -fs_inst::is_payload(unsigned arg) const +elk_fs_inst::is_payload(unsigned arg) const { switch (opcode) { - case FS_OPCODE_FB_WRITE: - case FS_OPCODE_FB_READ: - case VEC4_OPCODE_UNTYPED_ATOMIC: - case VEC4_OPCODE_UNTYPED_SURFACE_READ: - case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - case SHADER_OPCODE_INTERLOCK: - case SHADER_OPCODE_MEMORY_FENCE: - case SHADER_OPCODE_BARRIER: - case SHADER_OPCODE_TEX: - case FS_OPCODE_TXB: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_LZ: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_UMS: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXL_LZ: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_LOD: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_SAMPLEINFO: + case ELK_FS_OPCODE_FB_WRITE: + case ELK_FS_OPCODE_FB_READ: + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_SHADER_OPCODE_INTERLOCK: + case ELK_SHADER_OPCODE_MEMORY_FENCE: + case ELK_SHADER_OPCODE_BARRIER: + case ELK_SHADER_OPCODE_TEX: + case ELK_FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_UMS: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL_LZ: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_SAMPLEINFO: return arg == 0; - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: return arg == 2 || arg == 3; default: @@ -351,19 +351,19 @@ fs_inst::is_payload(unsigned arg) const * GRF sources and the destination. */ bool -fs_inst::has_source_and_destination_hazard() const +elk_fs_inst::has_source_and_destination_hazard() const { switch (opcode) { - case FS_OPCODE_PACK_HALF_2x16_SPLIT: + case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT: /* Multiple partial writes to the destination */ return true; - case SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_SHUFFLE: /* This instruction returns an arbitrary channel from the source and * gets split into smaller instructions in the generator. It's possible * that one of the instructions will read from a channel corresponding * to an earlier instruction. */ - case SHADER_OPCODE_SEL_EXEC: + case ELK_SHADER_OPCODE_SEL_EXEC: /* This is implemented as * * mov(16) g4<1>D 0D { align1 WE_all 1H }; @@ -373,25 +373,25 @@ fs_inst::has_source_and_destination_hazard() const * may stomp all over it. */ return true; - case SHADER_OPCODE_QUAD_SWIZZLE: + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: switch (src[1].ud) { - case BRW_SWIZZLE_XXXX: - case BRW_SWIZZLE_YYYY: - case BRW_SWIZZLE_ZZZZ: - case BRW_SWIZZLE_WWWW: - case BRW_SWIZZLE_XXZZ: - case BRW_SWIZZLE_YYWW: - case BRW_SWIZZLE_XYXY: - case BRW_SWIZZLE_ZWZW: + case ELK_SWIZZLE_XXXX: + case ELK_SWIZZLE_YYYY: + case ELK_SWIZZLE_ZZZZ: + case ELK_SWIZZLE_WWWW: + case ELK_SWIZZLE_XXZZ: + case ELK_SWIZZLE_YYWW: + case ELK_SWIZZLE_XYXY: + case ELK_SWIZZLE_ZWZW: /* These can be implemented as a single Align1 region on all * platforms, so there's never a hazard between source and - * destination. C.f. fs_generator::generate_quad_swizzle(). + * destination. C.f. elk_fs_generator::generate_quad_swizzle(). */ return false; default: return !is_uniform(src[0]); } - case BRW_OPCODE_DPAS: + case ELK_OPCODE_DPAS: /* This is overly conservative. The actual hazard is more complicated to * describe. When the repeat count is N, the single instruction behaves * like N instructions with a repeat count of one, but the destination @@ -431,10 +431,10 @@ fs_inst::has_source_and_destination_hazard() const if (exec_size == 16) { for (int i = 0; i < sources; i++) { if (src[i].file == VGRF && (src[i].stride == 0 || - src[i].type == BRW_REGISTER_TYPE_UW || - src[i].type == BRW_REGISTER_TYPE_W || - src[i].type == BRW_REGISTER_TYPE_UB || - src[i].type == BRW_REGISTER_TYPE_B)) { + src[i].type == ELK_REGISTER_TYPE_UW || + src[i].type == ELK_REGISTER_TYPE_W || + src[i].type == ELK_REGISTER_TYPE_UB || + src[i].type == ELK_REGISTER_TYPE_B)) { return true; } } @@ -444,7 +444,7 @@ fs_inst::has_source_and_destination_hazard() const } bool -fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const +elk_fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const { if (devinfo->ver == 6 && is_math()) return false; @@ -457,29 +457,29 @@ fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const * "When multiplying a DW and any lower precision integer, source modifier * is not supported." */ - if (devinfo->ver >= 12 && (opcode == BRW_OPCODE_MUL || - opcode == BRW_OPCODE_MAD)) { - const brw_reg_type exec_type = get_exec_type(this); - const unsigned min_type_sz = opcode == BRW_OPCODE_MAD ? + if (devinfo->ver >= 12 && (opcode == ELK_OPCODE_MUL || + opcode == ELK_OPCODE_MAD)) { + const elk_reg_type exec_type = get_exec_type(this); + const unsigned min_type_sz = opcode == ELK_OPCODE_MAD ? MIN2(type_sz(src[1].type), type_sz(src[2].type)) : MIN2(type_sz(src[0].type), type_sz(src[1].type)); - if (brw_reg_type_is_integer(exec_type) && + if (elk_reg_type_is_integer(exec_type) && type_sz(exec_type) >= 4 && type_sz(exec_type) != min_type_sz) return false; } - if (!backend_instruction::can_do_source_mods()) + if (!elk_backend_instruction::can_do_source_mods()) return false; return true; } bool -fs_inst::can_do_cmod() +elk_fs_inst::can_do_cmod() { - if (!backend_instruction::can_do_cmod()) + if (!elk_backend_instruction::can_do_cmod()) return false; /* The accumulator result appears to get used for the conditional modifier @@ -488,7 +488,7 @@ fs_inst::can_do_cmod() * equality with a 32-bit value. See piglit fs-op-neg-uvec4. */ for (unsigned i = 0; i < sources; i++) { - if (brw_reg_type_is_unsigned_integer(src[i].type) && src[i].negate) + if (elk_reg_type_is_unsigned_integer(src[i].type) && src[i].negate) return false; } @@ -496,66 +496,66 @@ fs_inst::can_do_cmod() } bool -fs_inst::can_change_types() const +elk_fs_inst::can_change_types() const { return dst.type == src[0].type && !src[0].abs && !src[0].negate && !saturate && src[0].file != ATTR && - (opcode == BRW_OPCODE_MOV || - (opcode == BRW_OPCODE_SEL && + (opcode == ELK_OPCODE_MOV || + (opcode == ELK_OPCODE_SEL && dst.type == src[1].type && - predicate != BRW_PREDICATE_NONE && + predicate != ELK_PREDICATE_NONE && !src[1].abs && !src[1].negate && src[1].file != ATTR)); } void -fs_reg::init() +elk_fs_reg::init() { memset((void*)this, 0, sizeof(*this)); - type = BRW_REGISTER_TYPE_UD; + type = ELK_REGISTER_TYPE_UD; stride = 1; } /** Generic unset register constructor. */ -fs_reg::fs_reg() +elk_fs_reg::elk_fs_reg() { init(); this->file = BAD_FILE; } -fs_reg::fs_reg(struct ::brw_reg reg) : - backend_reg(reg) +elk_fs_reg::elk_fs_reg(struct ::elk_reg reg) : + elk_backend_reg(reg) { this->offset = 0; this->stride = 1; if (this->file == IMM && - (this->type != BRW_REGISTER_TYPE_V && - this->type != BRW_REGISTER_TYPE_UV && - this->type != BRW_REGISTER_TYPE_VF)) { + (this->type != ELK_REGISTER_TYPE_V && + this->type != ELK_REGISTER_TYPE_UV && + this->type != ELK_REGISTER_TYPE_VF)) { this->stride = 0; } } bool -fs_reg::equals(const fs_reg &r) const +elk_fs_reg::equals(const elk_fs_reg &r) const { - return (this->backend_reg::equals(r) && + return (this->elk_backend_reg::equals(r) && stride == r.stride); } bool -fs_reg::negative_equals(const fs_reg &r) const +elk_fs_reg::negative_equals(const elk_fs_reg &r) const { - return (this->backend_reg::negative_equals(r) && + return (this->elk_backend_reg::negative_equals(r) && stride == r.stride); } bool -fs_reg::is_contiguous() const +elk_fs_reg::is_contiguous() const { switch (file) { case ARF: case FIXED_GRF: - return hstride == BRW_HORIZONTAL_STRIDE_1 && + return hstride == ELK_HORIZONTAL_STRIDE_1 && vstride == width + hstride; case MRF: case VGRF: @@ -571,7 +571,7 @@ fs_reg::is_contiguous() const } unsigned -fs_reg::component_size(unsigned width) const +elk_fs_reg::component_size(unsigned width) const { if (file == ARF || file == FIXED_GRF) { const unsigned w = MIN2(width, 1u << this->width); @@ -586,7 +586,7 @@ fs_reg::component_size(unsigned width) const } void -fs_visitor::vfail(const char *format, va_list va) +elk_fs_visitor::vfail(const char *format, va_list va) { char *msg; @@ -607,7 +607,7 @@ fs_visitor::vfail(const char *format, va_list va) } void -fs_visitor::fail(const char *format, ...) +elk_fs_visitor::fail(const char *format, ...) { va_list va; @@ -628,13 +628,13 @@ fs_visitor::fail(const char *format, ...) * this just calls fail(). */ void -fs_visitor::limit_dispatch_width(unsigned n, const char *msg) +elk_fs_visitor::limit_dispatch_width(unsigned n, const char *msg) { if (dispatch_width > n) { fail("%s", msg); } else { max_dispatch_width = MIN2(max_dispatch_width, n); - brw_shader_perf_log(compiler, log_data, + elk_shader_perf_log(compiler, log_data, "Shader dispatch width limited to SIMD%d: %s\n", n, msg); } @@ -649,26 +649,26 @@ fs_visitor::limit_dispatch_width(unsigned n, const char *msg) * it. */ bool -fs_inst::is_partial_write() const +elk_fs_inst::is_partial_write() const { if (this->predicate && !this->predicate_trivial && - this->opcode != BRW_OPCODE_SEL) + this->opcode != ELK_OPCODE_SEL) return true; if (this->dst.offset % REG_SIZE != 0) return true; /* SEND instructions always write whole registers */ - if (this->opcode == SHADER_OPCODE_SEND) + if (this->opcode == ELK_SHADER_OPCODE_SEND) return false; /* Special case UNDEF since a lot of places in the backend do things like this : * * fs_builder ubld = bld.exec_all().group(1, 0); - * fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD); + * elk_fs_reg tmp = ubld.vgrf(ELK_REGISTER_TYPE_UD); * ubld.UNDEF(tmp); <- partial write, even if the whole register is concerned */ - if (this->opcode == SHADER_OPCODE_UNDEF) { + if (this->opcode == ELK_SHADER_OPCODE_UNDEF) { assert(this->dst.is_contiguous()); return this->size_written < 32; } @@ -678,28 +678,28 @@ fs_inst::is_partial_write() const } unsigned -fs_inst::components_read(unsigned i) const +elk_fs_inst::components_read(unsigned i) const { /* Return zero if the source is not present. */ if (src[i].file == BAD_FILE) return 0; switch (opcode) { - case FS_OPCODE_LINTERP: + case ELK_FS_OPCODE_LINTERP: if (i == 0) return 2; else return 1; - case FS_OPCODE_PIXEL_X: - case FS_OPCODE_PIXEL_Y: + case ELK_FS_OPCODE_PIXEL_X: + case ELK_FS_OPCODE_PIXEL_Y: assert(i < 2); if (i == 0) return 2; else return 1; - case FS_OPCODE_FB_WRITE_LOGICAL: + case ELK_FS_OPCODE_FB_WRITE_LOGICAL: assert(src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM); /* First/second FB write color. */ if (i < 2) @@ -707,22 +707,22 @@ fs_inst::components_read(unsigned i) const else return 1; - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_UMS_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case ELK_SHADER_OPCODE_TEX_LOGICAL: + case ELK_SHADER_OPCODE_TXD_LOGICAL: + case ELK_SHADER_OPCODE_TXF_LOGICAL: + case ELK_SHADER_OPCODE_TXL_LOGICAL: + case ELK_SHADER_OPCODE_TXS_LOGICAL: + case ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case ELK_FS_OPCODE_TXB_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: + case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL: + case ELK_SHADER_OPCODE_LOD_LOGICAL: + case ELK_SHADER_OPCODE_TG4_LOGICAL: + case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL: + case ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL: assert(src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM && src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM && src[TEX_LOGICAL_SRC_RESIDENCY].file == IMM); @@ -731,24 +731,24 @@ fs_inst::components_read(unsigned i) const return src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud; /* Texture derivatives. */ else if ((i == TEX_LOGICAL_SRC_LOD || i == TEX_LOGICAL_SRC_LOD2) && - opcode == SHADER_OPCODE_TXD_LOGICAL) + opcode == ELK_SHADER_OPCODE_TXD_LOGICAL) return src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud; /* Texture offset. */ else if (i == TEX_LOGICAL_SRC_TG4_OFFSET) return 2; /* MCS */ else if (i == TEX_LOGICAL_SRC_MCS) { - if (opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL) + if (opcode == ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL) return 2; - else if (opcode == SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) + else if (opcode == ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) return 4; else return 1; } else return 1; - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM); /* Surface coordinates. */ if (i == SURFACE_LOGICAL_SRC_ADDRESS) @@ -759,8 +759,8 @@ fs_inst::components_read(unsigned i) const else return 1; - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM && src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM); /* Surface coordinates. */ @@ -772,13 +772,13 @@ fs_inst::components_read(unsigned i) const else return 1; - case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: - case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: - case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: assert(src[A64_LOGICAL_ARG].file == IMM); return 1; - case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: assert(src[A64_LOGICAL_ARG].file == IMM); if (i == A64_LOGICAL_SRC) { /* data to write */ const unsigned comps = src[A64_LOGICAL_ARG].ud / exec_size; @@ -788,11 +788,11 @@ fs_inst::components_read(unsigned i) const return 1; } - case SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: assert(src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM); return 1; - case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL: assert(src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM); if (i == SURFACE_LOGICAL_SRC_DATA) { const unsigned comps = src[SURFACE_LOGICAL_SRC_IMM_ARG].ud / exec_size; @@ -802,17 +802,17 @@ fs_inst::components_read(unsigned i) const return 1; } - case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: assert(src[A64_LOGICAL_ARG].file == IMM); return i == A64_LOGICAL_SRC ? src[A64_LOGICAL_ARG].ud : 1; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: assert(src[A64_LOGICAL_ARG].file == IMM); return i == A64_LOGICAL_SRC ? lsc_op_num_data_values(src[A64_LOGICAL_ARG].ud) : 1; - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: /* Scattered logical opcodes use the following params: * src[0] Surface coordinates * src[1] Surface operation source (ignored for reads) @@ -824,14 +824,14 @@ fs_inst::components_read(unsigned i) const src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM); return i == SURFACE_LOGICAL_SRC_DATA ? 0 : 1; - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM && src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM); return 1; - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: { + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: { assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM && src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM); const unsigned op = src[SURFACE_LOGICAL_SRC_IMM_ARG].ud; @@ -844,10 +844,10 @@ fs_inst::components_read(unsigned i) const else return 1; } - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: return (i == 0 ? 2 : 1); - case SHADER_OPCODE_URB_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_URB_WRITE_LOGICAL: assert(src[URB_LOGICAL_SRC_COMPONENTS].file == IMM); if (i == URB_LOGICAL_SRC_DATA) @@ -855,7 +855,7 @@ fs_inst::components_read(unsigned i) const else return 1; - case BRW_OPCODE_DPAS: + case ELK_OPCODE_DPAS: unreachable("Do not use components_read() for DPAS."); default: @@ -864,10 +864,10 @@ fs_inst::components_read(unsigned i) const } unsigned -fs_inst::size_read(int arg) const +elk_fs_inst::size_read(int arg) const { switch (opcode) { - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: if (arg == 2) { return mlen * REG_SIZE; } else if (arg == 3) { @@ -875,8 +875,8 @@ fs_inst::size_read(int arg) const } break; - case FS_OPCODE_FB_WRITE: - case FS_OPCODE_REP_FB_WRITE: + case ELK_FS_OPCODE_FB_WRITE: + case ELK_FS_OPCODE_REP_FB_WRITE: if (arg == 0) { if (base_mrf >= 0) return src[0].file == BAD_FILE ? 0 : 2 * REG_SIZE; @@ -885,43 +885,43 @@ fs_inst::size_read(int arg) const } break; - case FS_OPCODE_FB_READ: - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_FB_READ: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: if (arg == 0) return mlen * REG_SIZE; break; - case FS_OPCODE_SET_SAMPLE_ID: + case ELK_FS_OPCODE_SET_SAMPLE_ID: if (arg == 1) return 1; break; - case FS_OPCODE_LINTERP: + case ELK_FS_OPCODE_LINTERP: if (arg == 1) return 16; break; - case SHADER_OPCODE_LOAD_PAYLOAD: + case ELK_SHADER_OPCODE_LOAD_PAYLOAD: if (arg < this->header_size) - return retype(src[arg], BRW_REGISTER_TYPE_UD).component_size(8); + return retype(src[arg], ELK_REGISTER_TYPE_UD).component_size(8); break; - case CS_OPCODE_CS_TERMINATE: - case SHADER_OPCODE_BARRIER: + case ELK_CS_OPCODE_CS_TERMINATE: + case ELK_SHADER_OPCODE_BARRIER: return REG_SIZE; - case SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_MOV_INDIRECT: if (arg == 0) { assert(src[2].file == IMM); return src[2].ud; } break; - case BRW_OPCODE_DPAS: + case ELK_OPCODE_DPAS: switch (arg) { case 0: - if (src[0].type == BRW_REGISTER_TYPE_HF) { + if (src[0].type == ELK_REGISTER_TYPE_HF) { return rcount * REG_SIZE / 2; } else { return rcount * REG_SIZE; @@ -938,22 +938,22 @@ fs_inst::size_read(int arg) const } break; - case SHADER_OPCODE_TEX: - case FS_OPCODE_TXB: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_LZ: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_UMS: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXL_LZ: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_LOD: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_TEX: + case ELK_FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_UMS: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL_LZ: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_SAMPLEINFO: if (arg == 0 && src[0].file == VGRF) return mlen * REG_SIZE; break; @@ -980,24 +980,24 @@ fs_inst::size_read(int arg) const namespace { unsigned - predicate_width(const intel_device_info *devinfo, brw_predicate predicate) + predicate_width(const intel_device_info *devinfo, elk_predicate predicate) { if (devinfo->ver >= 20) { return 1; } else { switch (predicate) { - case BRW_PREDICATE_NONE: return 1; - case BRW_PREDICATE_NORMAL: return 1; - case BRW_PREDICATE_ALIGN1_ANY2H: return 2; - case BRW_PREDICATE_ALIGN1_ALL2H: return 2; - case BRW_PREDICATE_ALIGN1_ANY4H: return 4; - case BRW_PREDICATE_ALIGN1_ALL4H: return 4; - case BRW_PREDICATE_ALIGN1_ANY8H: return 8; - case BRW_PREDICATE_ALIGN1_ALL8H: return 8; - case BRW_PREDICATE_ALIGN1_ANY16H: return 16; - case BRW_PREDICATE_ALIGN1_ALL16H: return 16; - case BRW_PREDICATE_ALIGN1_ANY32H: return 32; - case BRW_PREDICATE_ALIGN1_ALL32H: return 32; + case ELK_PREDICATE_NONE: return 1; + case ELK_PREDICATE_NORMAL: return 1; + case ELK_PREDICATE_ALIGN1_ANY2H: return 2; + case ELK_PREDICATE_ALIGN1_ALL2H: return 2; + case ELK_PREDICATE_ALIGN1_ANY4H: return 4; + case ELK_PREDICATE_ALIGN1_ALL4H: return 4; + case ELK_PREDICATE_ALIGN1_ANY8H: return 8; + case ELK_PREDICATE_ALIGN1_ALL8H: return 8; + case ELK_PREDICATE_ALIGN1_ANY16H: return 16; + case ELK_PREDICATE_ALIGN1_ALL16H: return 16; + case ELK_PREDICATE_ALIGN1_ANY32H: return 32; + case ELK_PREDICATE_ALIGN1_ALL32H: return 32; default: unreachable("Unsupported predicate"); } } @@ -1008,7 +1008,7 @@ namespace { * subregister number of the instruction. */ unsigned - flag_mask(const fs_inst *inst, unsigned width) + flag_mask(const elk_fs_inst *inst, unsigned width) { assert(util_is_power_of_two_nonzero(width)); const unsigned start = (inst->flag_subreg * 16 + inst->group) & @@ -1024,10 +1024,10 @@ namespace { } unsigned - flag_mask(const fs_reg &r, unsigned sz) + flag_mask(const elk_fs_reg &r, unsigned sz) { if (r.file == ARF) { - const unsigned start = (r.nr - BRW_ARF_FLAG) * 4 + r.subnr; + const unsigned start = (r.nr - ELK_ARF_FLAG) * 4 + r.subnr; const unsigned end = start + sz; return bit_mask(end) & ~bit_mask(start); } else { @@ -1037,10 +1037,10 @@ namespace { } unsigned -fs_inst::flags_read(const intel_device_info *devinfo) const +elk_fs_inst::flags_read(const intel_device_info *devinfo) const { - if (devinfo->ver < 20 && (predicate == BRW_PREDICATE_ALIGN1_ANYV || - predicate == BRW_PREDICATE_ALIGN1_ALLV)) { + if (devinfo->ver < 20 && (predicate == ELK_PREDICATE_ALIGN1_ANYV || + predicate == ELK_PREDICATE_ALIGN1_ALLV)) { /* The vertical predication modes combine corresponding bits from * f0.0 and f1.0 on Gfx7+, and f0.0 and f0.1 on older hardware. */ @@ -1058,21 +1058,21 @@ fs_inst::flags_read(const intel_device_info *devinfo) const } unsigned -fs_inst::flags_written(const intel_device_info *devinfo) const +elk_fs_inst::flags_written(const intel_device_info *devinfo) const { /* On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented * using a separate cmpn and sel instruction. This lowering occurs in * fs_vistor::lower_minmax which is called very, very late. */ - if ((conditional_mod && ((opcode != BRW_OPCODE_SEL || devinfo->ver <= 5) && - opcode != BRW_OPCODE_CSEL && - opcode != BRW_OPCODE_IF && - opcode != BRW_OPCODE_WHILE)) || - opcode == FS_OPCODE_FB_WRITE) { + if ((conditional_mod && ((opcode != ELK_OPCODE_SEL || devinfo->ver <= 5) && + opcode != ELK_OPCODE_CSEL && + opcode != ELK_OPCODE_IF && + opcode != ELK_OPCODE_WHILE)) || + opcode == ELK_FS_OPCODE_FB_WRITE) { return flag_mask(this, 1); - } else if (opcode == SHADER_OPCODE_FIND_LIVE_CHANNEL || - opcode == SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL || - opcode == FS_OPCODE_LOAD_LIVE_CHANNELS) { + } else if (opcode == ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL || + opcode == ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL || + opcode == ELK_FS_OPCODE_LOAD_LIVE_CHANNELS) { return flag_mask(this, 32); } else { return flag_mask(dst, size_written); @@ -1086,7 +1086,7 @@ fs_inst::flags_written(const intel_device_info *devinfo) const * instruction -- the FS opcodes often generate MOVs in addition. */ unsigned -fs_inst::implied_mrf_writes() const +elk_fs_inst::implied_mrf_writes() const { if (mlen == 0) return 0; @@ -1095,40 +1095,40 @@ fs_inst::implied_mrf_writes() const return 0; switch (opcode) { - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: return 1 * exec_size / 8; - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: return 2 * exec_size / 8; - case SHADER_OPCODE_TEX: - case FS_OPCODE_TXB: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_LOD: - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_TEX: + case ELK_FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_SAMPLEINFO: return 1; - case FS_OPCODE_FB_WRITE: - case FS_OPCODE_REP_FB_WRITE: + case ELK_FS_OPCODE_FB_WRITE: + case ELK_FS_OPCODE_REP_FB_WRITE: return src[0].file == BAD_FILE ? 0 : 2; - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: - case SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: return 1; - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: return mlen; - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: return mlen; default: unreachable("not reached"); @@ -1136,20 +1136,20 @@ fs_inst::implied_mrf_writes() const } bool -fs_inst::has_sampler_residency() const +elk_fs_inst::has_sampler_residency() const { switch (opcode) { - case SHADER_OPCODE_TEX_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: + case ELK_SHADER_OPCODE_TEX_LOGICAL: + case ELK_FS_OPCODE_TXB_LOGICAL: + case ELK_SHADER_OPCODE_TXL_LOGICAL: + case ELK_SHADER_OPCODE_TXD_LOGICAL: + case ELK_SHADER_OPCODE_TXF_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL: + case ELK_SHADER_OPCODE_TXS_LOGICAL: + case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL: + case ELK_SHADER_OPCODE_TG4_LOGICAL: assert(src[TEX_LOGICAL_SRC_RESIDENCY].file == IMM); return src[TEX_LOGICAL_SRC_RESIDENCY].ud != 0; default: @@ -1157,25 +1157,25 @@ fs_inst::has_sampler_residency() const } } -fs_reg -fs_visitor::vgrf(const glsl_type *const type) +elk_fs_reg +elk_fs_visitor::vgrf(const glsl_type *const type) { int reg_width = dispatch_width / 8; - return fs_reg(VGRF, + return elk_fs_reg(VGRF, alloc.allocate(glsl_count_dword_slots(type, false) * reg_width), - brw_type_for_base_type(type)); + elk_type_for_base_type(type)); } -fs_reg::fs_reg(enum brw_reg_file file, unsigned nr) +elk_fs_reg::elk_fs_reg(enum elk_reg_file file, unsigned nr) { init(); this->file = file; this->nr = nr; - this->type = BRW_REGISTER_TYPE_F; + this->type = ELK_REGISTER_TYPE_F; this->stride = (file == UNIFORM ? 0 : 1); } -fs_reg::fs_reg(enum brw_reg_file file, unsigned nr, enum brw_reg_type type) +elk_fs_reg::elk_fs_reg(enum elk_reg_file file, unsigned nr, enum elk_reg_type type) { init(); this->file = file; @@ -1188,14 +1188,14 @@ fs_reg::fs_reg(enum brw_reg_file file, unsigned nr, enum brw_reg_type type) * This brings in those uniform definitions */ void -fs_visitor::import_uniforms(fs_visitor *v) +elk_fs_visitor::import_uniforms(elk_fs_visitor *v) { this->push_constant_loc = v->push_constant_loc; this->uniforms = v->uniforms; } -enum brw_barycentric_mode -brw_barycentric_mode(nir_intrinsic_instr *intr) +enum elk_barycentric_mode +elk_barycentric_mode(nir_intrinsic_instr *intr) { const glsl_interp_mode mode = (enum glsl_interp_mode) nir_intrinsic_interp_mode(intr); @@ -1207,14 +1207,14 @@ brw_barycentric_mode(nir_intrinsic_instr *intr) switch (intr->intrinsic) { case nir_intrinsic_load_barycentric_pixel: case nir_intrinsic_load_barycentric_at_offset: - bary = BRW_BARYCENTRIC_PERSPECTIVE_PIXEL; + bary = ELK_BARYCENTRIC_PERSPECTIVE_PIXEL; break; case nir_intrinsic_load_barycentric_centroid: - bary = BRW_BARYCENTRIC_PERSPECTIVE_CENTROID; + bary = ELK_BARYCENTRIC_PERSPECTIVE_CENTROID; break; case nir_intrinsic_load_barycentric_sample: case nir_intrinsic_load_barycentric_at_sample: - bary = BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE; + bary = ELK_BARYCENTRIC_PERSPECTIVE_SAMPLE; break; default: unreachable("invalid intrinsic"); @@ -1223,18 +1223,18 @@ brw_barycentric_mode(nir_intrinsic_instr *intr) if (mode == INTERP_MODE_NOPERSPECTIVE) bary += 3; - return (enum brw_barycentric_mode) bary; + return (enum elk_barycentric_mode) bary; } /** * Turn one of the two CENTROID barycentric modes into PIXEL mode. */ -static enum brw_barycentric_mode -centroid_to_pixel(enum brw_barycentric_mode bary) +static enum elk_barycentric_mode +centroid_to_pixel(enum elk_barycentric_mode bary) { - assert(bary == BRW_BARYCENTRIC_PERSPECTIVE_CENTROID || - bary == BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID); - return (enum brw_barycentric_mode) ((unsigned) bary - 1); + assert(bary == ELK_BARYCENTRIC_PERSPECTIVE_CENTROID || + bary == ELK_BARYCENTRIC_NONPERSPECTIVE_CENTROID); + return (enum elk_barycentric_mode) ((unsigned) bary - 1); } /** @@ -1244,10 +1244,10 @@ centroid_to_pixel(enum brw_barycentric_mode bary) * Return true if successful or false if a separate EOT write is needed. */ bool -fs_visitor::mark_last_urb_write_with_eot() +elk_fs_visitor::mark_last_urb_write_with_eot() { - foreach_in_list_reverse(fs_inst, prev, &this->instructions) { - if (prev->opcode == SHADER_OPCODE_URB_WRITE_LOGICAL) { + foreach_in_list_reverse(elk_fs_inst, prev, &this->instructions) { + if (prev->opcode == ELK_SHADER_OPCODE_URB_WRITE_LOGICAL) { prev->eot = true; /* Delete now dead instructions. */ @@ -1266,18 +1266,18 @@ fs_visitor::mark_last_urb_write_with_eot() } void -fs_visitor::emit_gs_thread_end() +elk_fs_visitor::emit_gs_thread_end() { assert(stage == MESA_SHADER_GEOMETRY); - struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); + struct elk_gs_prog_data *gs_prog_data = elk_gs_prog_data(prog_data); if (gs_compile->control_data_header_size_bits > 0) { emit_gs_control_data_bits(this->final_gs_vertex_count); } const fs_builder abld = fs_builder(this).at_end().annotate("thread end"); - fs_inst *inst; + elk_fs_inst *inst; if (gs_prog_data->static_vertex_count != -1) { /* Try and tag the last URB write with EOT instead of emitting a whole @@ -1286,17 +1286,17 @@ fs_visitor::emit_gs_thread_end() if (mark_last_urb_write_with_eot()) return; - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = gs_payload().urb_handles; - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(0); - inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + srcs[URB_LOGICAL_SRC_COMPONENTS] = elk_imm_ud(0); + inst = abld.emit(ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); } else { - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = gs_payload().urb_handles; srcs[URB_LOGICAL_SRC_DATA] = this->final_gs_vertex_count; - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(1); - inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + srcs[URB_LOGICAL_SRC_COMPONENTS] = elk_imm_ud(1); + inst = abld.emit(ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); } inst->eot = true; @@ -1304,7 +1304,7 @@ fs_visitor::emit_gs_thread_end() } void -fs_visitor::assign_curb_setup() +elk_fs_visitor::assign_curb_setup() { unsigned uniform_push_length = DIV_ROUND_UP(stage_prog_data->nr_params, 8); @@ -1320,7 +1320,7 @@ fs_visitor::assign_curb_setup() uint64_t used = 0; bool is_compute = gl_shader_stage_is_compute(stage); - if (is_compute && brw_cs_prog_data(prog_data)->uses_inline_data) { + if (is_compute && elk_cs_prog_data(prog_data)->uses_inline_data) { /* With COMPUTE_WALKER, we can push up to one register worth of data via * the inline data parameter in the COMPUTE_WALKER command itself. * @@ -1336,10 +1336,10 @@ fs_visitor::assign_curb_setup() /* The base offset for our push data is passed in as R0.0[31:6]. We have * to mask off the bottom 6 bits. */ - fs_reg base_addr = ubld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg base_addr = ubld.vgrf(ELK_REGISTER_TYPE_UD); ubld.AND(base_addr, - retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(31, 6))); + retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(31, 6))); /* On Gfx12-HP we load constants at the start of the program using A32 * stateless messages. @@ -1350,19 +1350,19 @@ fs_visitor::assign_curb_setup() assert(num_regs > 0); num_regs = 1 << util_logbase2(num_regs); - fs_reg addr = ubld.vgrf(BRW_REGISTER_TYPE_UD); - ubld.ADD(addr, base_addr, brw_imm_ud(i * REG_SIZE)); + elk_fs_reg addr = ubld.vgrf(ELK_REGISTER_TYPE_UD); + ubld.ADD(addr, base_addr, elk_imm_ud(i * REG_SIZE)); - fs_reg srcs[4] = { - brw_imm_ud(0), /* desc */ - brw_imm_ud(0), /* ex_desc */ + elk_fs_reg srcs[4] = { + elk_imm_ud(0), /* desc */ + elk_imm_ud(0), /* ex_desc */ addr, /* payload */ - fs_reg(), /* payload2 */ + elk_fs_reg(), /* payload2 */ }; - fs_reg dest = retype(brw_vec8_grf(payload().num_regs + i, 0), - BRW_REGISTER_TYPE_UD); - fs_inst *send = ubld.emit(SHADER_OPCODE_SEND, dest, srcs, 4); + elk_fs_reg dest = retype(elk_vec8_grf(payload().num_regs + i, 0), + ELK_REGISTER_TYPE_UD); + elk_fs_inst *send = ubld.emit(ELK_SHADER_OPCODE_SEND, dest, srcs, 4); send->sfid = GFX12_SFID_UGM; send->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, @@ -1388,7 +1388,7 @@ fs_visitor::assign_curb_setup() } /* Map the offsets in the UNIFORM file to fixed HW regs. */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == UNIFORM) { int uniform_nr = inst->src[i].nr + inst->src[i].offset / 4; @@ -1411,15 +1411,15 @@ fs_visitor::assign_curb_setup() assert(constant_nr / 8 < 64); used |= BITFIELD64_BIT(constant_nr / 8); - struct brw_reg brw_reg = brw_vec1_grf(payload().num_regs + + struct elk_reg elk_reg = elk_vec1_grf(payload().num_regs + constant_nr / 8, constant_nr % 8); - brw_reg.abs = inst->src[i].abs; - brw_reg.negate = inst->src[i].negate; + elk_reg.abs = inst->src[i].abs; + elk_reg.negate = inst->src[i].negate; assert(inst->src[i].stride == 0); inst->src[i] = byte_offset( - retype(brw_reg, inst->src[i].type), + retype(elk_reg, inst->src[i].type), inst->src[i].offset % 4); } } @@ -1432,28 +1432,28 @@ fs_visitor::assign_curb_setup() /* push_reg_mask_param is in 32-bit units */ unsigned mask_param = stage_prog_data->push_reg_mask_param; - struct brw_reg mask = brw_vec1_grf(payload().num_regs + mask_param / 8, + struct elk_reg mask = elk_vec1_grf(payload().num_regs + mask_param / 8, mask_param % 8); - fs_reg b32; + elk_fs_reg b32; for (unsigned i = 0; i < 64; i++) { if (i % 16 == 0 && (want_zero & BITFIELD64_RANGE(i, 16))) { - fs_reg shifted = ubld.vgrf(BRW_REGISTER_TYPE_W, 2); + elk_fs_reg shifted = ubld.vgrf(ELK_REGISTER_TYPE_W, 2); ubld.SHL(horiz_offset(shifted, 8), - byte_offset(retype(mask, BRW_REGISTER_TYPE_W), i / 8), - brw_imm_v(0x01234567)); - ubld.SHL(shifted, horiz_offset(shifted, 8), brw_imm_w(8)); + byte_offset(retype(mask, ELK_REGISTER_TYPE_W), i / 8), + elk_imm_v(0x01234567)); + ubld.SHL(shifted, horiz_offset(shifted, 8), elk_imm_w(8)); fs_builder ubld16 = ubld.group(16, 0); - b32 = ubld16.vgrf(BRW_REGISTER_TYPE_D); - ubld16.group(16, 0).ASR(b32, shifted, brw_imm_w(15)); + b32 = ubld16.vgrf(ELK_REGISTER_TYPE_D); + ubld16.group(16, 0).ASR(b32, shifted, elk_imm_w(15)); } if (want_zero & BITFIELD64_BIT(i)) { assert(i < prog_data->curb_read_length); - struct brw_reg push_reg = - retype(brw_vec8_grf(payload().num_regs + i, 0), - BRW_REGISTER_TYPE_D); + struct elk_reg push_reg = + retype(elk_vec8_grf(payload().num_regs + i, 0), + ELK_REGISTER_TYPE_D); ubld.AND(push_reg, push_reg, component(b32, i % 16)); } @@ -1473,7 +1473,7 @@ fs_visitor::assign_curb_setup() * on each upload. */ void -brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data) +elk_compute_urb_setup_index(struct elk_wm_prog_data *wm_prog_data) { /* Make sure uint8_t is sufficient */ STATIC_ASSERT(VARYING_SLOT_MAX <= 0xff); @@ -1488,8 +1488,8 @@ brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data) static void calculate_urb_setup(const struct intel_device_info *devinfo, - const struct brw_wm_prog_key *key, - struct brw_wm_prog_data *prog_data, + const struct elk_wm_prog_key *key, + struct elk_wm_prog_data *prog_data, const nir_shader *nir) { memset(prog_data->urb_setup, -1, sizeof(prog_data->urb_setup)); @@ -1507,7 +1507,7 @@ calculate_urb_setup(const struct intel_device_info *devinfo, uint64_t vue_header_bits = VARYING_BIT_PSIZ | VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT; - uint64_t unique_fs_attrs = inputs_read & BRW_FS_VARYING_INPUT_MASK; + uint64_t unique_fs_attrs = inputs_read & ELK_FS_VARYING_INPUT_MASK; /* VUE header fields all live in the same URB slot, so we pass them * as a single FS input attribute. We want to only count them once. @@ -1541,7 +1541,7 @@ calculate_urb_setup(const struct intel_device_info *devinfo, } for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) { - if (inputs_read & BRW_FS_VARYING_INPUT_MASK & ~vue_header_bits & + if (inputs_read & ELK_FS_VARYING_INPUT_MASK & ~vue_header_bits & BITFIELD64_BIT(i)) { prog_data->urb_setup[i] = urb_next++; } @@ -1558,20 +1558,20 @@ calculate_urb_setup(const struct intel_device_info *devinfo, * Replication). */ struct intel_vue_map prev_stage_vue_map; - brw_compute_vue_map(devinfo, &prev_stage_vue_map, + elk_compute_vue_map(devinfo, &prev_stage_vue_map, key->input_slots_valid, nir->info.separate_shader, 1); int first_slot = - brw_compute_first_urb_slot_required(inputs_read, + elk_compute_first_urb_slot_required(inputs_read, &prev_stage_vue_map); assert(prev_stage_vue_map.num_slots <= first_slot + 32); for (int slot = first_slot; slot < prev_stage_vue_map.num_slots; slot++) { int varying = prev_stage_vue_map.slot_to_varying[slot]; - if (varying != BRW_VARYING_SLOT_PAD && - (inputs_read & BRW_FS_VARYING_INPUT_MASK & + if (varying != ELK_VARYING_SLOT_PAD && + (inputs_read & ELK_FS_VARYING_INPUT_MASK & BITFIELD64_BIT(varying))) { prog_data->urb_setup[varying] = slot - first_slot; } @@ -1611,30 +1611,30 @@ calculate_urb_setup(const struct intel_device_info *devinfo, prog_data->num_varying_inputs = urb_next - prog_data->num_per_primitive_inputs; prog_data->inputs = inputs_read; - brw_compute_urb_setup_index(prog_data); + elk_compute_urb_setup_index(prog_data); } void -fs_visitor::assign_urb_setup() +elk_fs_visitor::assign_urb_setup() { assert(stage == MESA_SHADER_FRAGMENT); - struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); + struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data); int urb_start = payload().num_regs + prog_data->base.curb_read_length; /* Offset all the urb_setup[] index by the actual position of the * setup regs, now that the location of the constants has been chosen. */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == ATTR) { - /* ATTR fs_reg::nr in the FS is in units of logical scalar + /* ATTR elk_fs_reg::nr in the FS is in units of logical scalar * inputs each of which consumes 16B on Gfx4-Gfx12. In * single polygon mode this leads to the following layout * of the vertex setup plane parameters in the ATTR * register file: * - * fs_reg::nr Input Comp0 Comp1 Comp2 Comp3 + * elk_fs_reg::nr Input Comp0 Comp1 Comp2 Comp3 * 0 Attr0.x a1-a0 a2-a0 N/A a0 * 1 Attr0.y a1-a0 a2-a0 N/A a0 * 2 Attr0.z a1-a0 a2-a0 N/A a0 @@ -1647,7 +1647,7 @@ fs_visitor::assign_urb_setup() * different plane parameters, so each parameter above is * represented as a dispatch_width-wide vector: * - * fs_reg::nr fs_reg::offset Input Comp0 ... CompN + * elk_fs_reg::nr elk_fs_reg::offset Input Comp0 ... CompN * 0 0 Attr0.x a1[0]-a0[0] ... a1[N]-a0[N] * 0 4 * dispatch_width Attr0.x a2[0]-a0[0] ... a2[N]-a0[N] * 0 8 * dispatch_width Attr0.x N/A ... N/A @@ -1681,7 +1681,7 @@ fs_visitor::assign_urb_setup() * in bytes. */ const unsigned chan_sz = 4; - struct brw_reg reg; + struct elk_reg reg; assert(max_polygons > 0); /* Calculate the base register on the thread payload of @@ -1712,7 +1712,7 @@ fs_visitor::assign_urb_setup() const unsigned delta = idx % 5 * 12 + inst->src[i].offset / (param_width * chan_sz) * chan_sz + inst->src[i].offset % chan_sz; - reg = byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type), + reg = byte_offset(retype(elk_vec8_grf(grf, 0), inst->src[i].type), delta); } else { /* Earlier platforms and per-primitive block pack 2 logical @@ -1723,7 +1723,7 @@ fs_visitor::assign_urb_setup() const unsigned delta = (idx % 2) * (REG_SIZE / 2) + inst->src[i].offset / (param_width * chan_sz) * chan_sz + inst->src[i].offset % chan_sz; - reg = byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type), + reg = byte_offset(retype(elk_vec8_grf(grf, 0), inst->src[i].type), delta); } @@ -1796,7 +1796,7 @@ fs_visitor::assign_urb_setup() } void -fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst) +elk_fs_visitor::convert_attr_sources_to_hw_regs(elk_fs_inst *inst) { for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == ATTR) { @@ -1805,7 +1805,7 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst) prog_data->curb_read_length + inst->src[i].offset / REG_SIZE; - /* As explained at brw_reg_from_fs_reg, From the Haswell PRM: + /* As explained at elk_reg_from_fs_reg, From the Haswell PRM: * * VertStride must be used to cross GRF register boundaries. This * rule implies that elements within a 'Width' cannot cross GRF @@ -1823,8 +1823,8 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst) (total_size <= REG_SIZE) ? inst->exec_size : inst->exec_size / 2; unsigned width = inst->src[i].stride == 0 ? 1 : exec_size; - struct brw_reg reg = - stride(byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type), + struct elk_reg reg = + stride(byte_offset(retype(elk_vec8_grf(grf, 0), inst->src[i].type), inst->src[i].offset % REG_SIZE), exec_size * inst->src[i].stride, width, inst->src[i].stride); @@ -1837,9 +1837,9 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst) } void -fs_visitor::assign_vs_urb_setup() +elk_fs_visitor::assign_vs_urb_setup() { - struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(prog_data); + struct elk_vs_prog_data *vs_prog_data = elk_vs_prog_data(prog_data); assert(stage == MESA_SHADER_VERTEX); @@ -1849,48 +1849,48 @@ fs_visitor::assign_vs_urb_setup() assert(vs_prog_data->base.urb_read_length <= 15); /* Rewrite all ATTR file references to the hw grf that they land in. */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { convert_attr_sources_to_hw_regs(inst); } } void -fs_visitor::assign_tcs_urb_setup() +elk_fs_visitor::assign_tcs_urb_setup() { assert(stage == MESA_SHADER_TESS_CTRL); /* Rewrite all ATTR file references to HW_REGs. */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { convert_attr_sources_to_hw_regs(inst); } } void -fs_visitor::assign_tes_urb_setup() +elk_fs_visitor::assign_tes_urb_setup() { assert(stage == MESA_SHADER_TESS_EVAL); - struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data); + struct elk_vue_prog_data *vue_prog_data = elk_vue_prog_data(prog_data); first_non_payload_grf += 8 * vue_prog_data->urb_read_length; /* Rewrite all ATTR file references to HW_REGs. */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { convert_attr_sources_to_hw_regs(inst); } } void -fs_visitor::assign_gs_urb_setup() +elk_fs_visitor::assign_gs_urb_setup() { assert(stage == MESA_SHADER_GEOMETRY); - struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data); + struct elk_vue_prog_data *vue_prog_data = elk_vue_prog_data(prog_data); first_non_payload_grf += 8 * vue_prog_data->urb_read_length * nir->info.gs.vertices_in; - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { /* Rewrite all ATTR file references to GRFs. */ convert_attr_sources_to_hw_regs(inst); } @@ -1911,7 +1911,7 @@ fs_visitor::assign_gs_urb_setup() * elimination and coalescing. */ bool -fs_visitor::split_virtual_grfs() +elk_fs_visitor::split_virtual_grfs() { /* Compact the register file so we eliminate dead vgrfs. This * only defines split points for live registers, so if we have @@ -1939,7 +1939,7 @@ fs_visitor::split_virtual_grfs() memset(split_points, 0, reg_count * sizeof(*split_points)); /* Mark all used registers as fully splittable */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { if (inst->dst.file == VGRF) { unsigned reg = vgrf_to_reg[inst->dst.nr]; for (unsigned j = 1; j < this->alloc.sizes[inst->dst.nr]; j++) @@ -1955,9 +1955,9 @@ fs_visitor::split_virtual_grfs() } } - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { /* We fix up undef instructions later */ - if (inst->opcode == SHADER_OPCODE_UNDEF) { + if (inst->opcode == ELK_SHADER_OPCODE_UNDEF) { assert(inst->dst.file == VGRF); continue; } @@ -2027,8 +2027,8 @@ fs_visitor::split_virtual_grfs() goto cleanup; } - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { - if (inst->opcode == SHADER_OPCODE_UNDEF) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { + if (inst->opcode == ELK_SHADER_OPCODE_UNDEF) { assert(inst->dst.file == VGRF); if (vgrf_has_split[inst->dst.nr]) { const fs_builder ibld(this, block, inst); @@ -2037,9 +2037,9 @@ fs_visitor::split_virtual_grfs() unsigned size_written = 0; while (size_written < inst->size_written) { reg = vgrf_to_reg[inst->dst.nr] + reg_offset + size_written / REG_SIZE; - fs_inst *undef = + elk_fs_inst *undef = ibld.UNDEF( - byte_offset(fs_reg(VGRF, new_virtual_grf[reg], inst->dst.type), + byte_offset(elk_fs_reg(VGRF, new_virtual_grf[reg], inst->dst.type), new_reg_offset[reg] * REG_SIZE)); undef->size_written = MIN2(inst->size_written - size_written, undef->size_written); @@ -2106,14 +2106,14 @@ cleanup: * overhead. */ bool -fs_visitor::compact_virtual_grfs() +elk_fs_visitor::compact_virtual_grfs() { bool progress = false; int *remap_table = new int[this->alloc.count]; memset(remap_table, -1, this->alloc.count * sizeof(int)); /* Mark which virtual GRFs are used. */ - foreach_block_and_inst(block, const fs_inst, inst, cfg) { + foreach_block_and_inst(block, const elk_fs_inst, inst, cfg) { if (inst->dst.file == VGRF) remap_table[inst->dst.nr] = 0; @@ -2142,7 +2142,7 @@ fs_visitor::compact_virtual_grfs() this->alloc.count = new_index; /* Patch all the instructions to use the newly renumbered registers */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { if (inst->dst.file == VGRF) inst->dst.nr = remap_table[inst->dst.nr]; @@ -2172,8 +2172,8 @@ fs_visitor::compact_virtual_grfs() } int -brw_get_subgroup_id_param_index(const intel_device_info *devinfo, - const brw_stage_prog_data *prog_data) +elk_get_subgroup_id_param_index(const intel_device_info *devinfo, + const elk_stage_prog_data *prog_data) { if (prog_data->nr_params == 0) return -1; @@ -2183,7 +2183,7 @@ brw_get_subgroup_id_param_index(const intel_device_info *devinfo, /* The local thread id is always the last parameter in the list */ uint32_t last_param = prog_data->param[prog_data->nr_params - 1]; - if (last_param == BRW_PARAM_BUILTIN_SUBGROUP_ID) + if (last_param == ELK_PARAM_BUILTIN_SUBGROUP_ID) return prog_data->nr_params - 1; return -1; @@ -2199,7 +2199,7 @@ brw_get_subgroup_id_param_index(const intel_device_info *devinfo, * update the program to load them. */ void -fs_visitor::assign_constant_locations() +elk_fs_visitor::assign_constant_locations() { /* Only the first compile gets to decide on locations. */ if (push_constant_loc) @@ -2216,12 +2216,12 @@ fs_visitor::assign_constant_locations() * Only allow 16 registers (128 uniform components) as push constants. * * If changing this value, note the limitation about total_regs in - * brw_curbe.c/crocus_state.c + * elk_curbe.c/crocus_state.c */ const unsigned max_push_length = compiler->devinfo->ver < 6 ? 16 : 64; unsigned push_length = DIV_ROUND_UP(stage_prog_data->nr_params, 8); for (int i = 0; i < 4; i++) { - struct brw_ubo_range *range = &prog_data->ubo_ranges[i]; + struct elk_ubo_range *range = &prog_data->ubo_ranges[i]; if (push_length + range->length > max_push_length) range->length = max_push_length - push_length; @@ -2232,7 +2232,7 @@ fs_visitor::assign_constant_locations() } bool -fs_visitor::get_pull_locs(const fs_reg &src, +elk_fs_visitor::get_pull_locs(const elk_fs_reg &src, unsigned *out_surf_index, unsigned *out_pull_index) { @@ -2241,7 +2241,7 @@ fs_visitor::get_pull_locs(const fs_reg &src, if (src.nr < UBO_START) return false; - const struct brw_ubo_range *range = + const struct elk_ubo_range *range = &prog_data->ubo_ranges[src.nr - UBO_START]; /* If this access is in our (reduced) range, use the push data. */ @@ -2261,12 +2261,12 @@ fs_visitor::get_pull_locs(const fs_reg &src, * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs. */ bool -fs_visitor::lower_constant_loads() +elk_fs_visitor::lower_constant_loads() { unsigned index, pull_index; bool progress = false; - foreach_block_and_inst_safe (block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe (block, elk_fs_inst, inst, cfg) { /* Set up the annotation tracking for new generated instructions. */ const fs_builder ibld(this, block, inst); @@ -2275,7 +2275,7 @@ fs_visitor::lower_constant_loads() continue; /* We'll handle this case later */ - if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT && i == 0) + if (inst->opcode == ELK_SHADER_OPCODE_MOV_INDIRECT && i == 0) continue; if (!get_pull_locs(inst->src[i], &index, &pull_index)) @@ -2285,16 +2285,16 @@ fs_visitor::lower_constant_loads() const unsigned block_sz = 64; /* Fetch one cacheline at a time. */ const fs_builder ubld = ibld.exec_all().group(block_sz / 4, 0); - const fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_UD); + const elk_fs_reg dst = ubld.vgrf(ELK_REGISTER_TYPE_UD); const unsigned base = pull_index * 4; - fs_reg srcs[PULL_UNIFORM_CONSTANT_SRCS]; - srcs[PULL_UNIFORM_CONSTANT_SRC_SURFACE] = brw_imm_ud(index); - srcs[PULL_UNIFORM_CONSTANT_SRC_OFFSET] = brw_imm_ud(base & ~(block_sz - 1)); - srcs[PULL_UNIFORM_CONSTANT_SRC_SIZE] = brw_imm_ud(block_sz); + elk_fs_reg srcs[PULL_UNIFORM_CONSTANT_SRCS]; + srcs[PULL_UNIFORM_CONSTANT_SRC_SURFACE] = elk_imm_ud(index); + srcs[PULL_UNIFORM_CONSTANT_SRC_OFFSET] = elk_imm_ud(base & ~(block_sz - 1)); + srcs[PULL_UNIFORM_CONSTANT_SRC_SIZE] = elk_imm_ud(block_sz); - ubld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, dst, + ubld.emit(ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, dst, srcs, PULL_UNIFORM_CONSTANT_SRCS); /* Rewrite the instruction to use the temporary VGRF. */ @@ -2306,15 +2306,15 @@ fs_visitor::lower_constant_loads() progress = true; } - if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT && + if (inst->opcode == ELK_SHADER_OPCODE_MOV_INDIRECT && inst->src[0].file == UNIFORM) { if (!get_pull_locs(inst->src[0], &index, &pull_index)) continue; VARYING_PULL_CONSTANT_LOAD(ibld, inst->dst, - brw_imm_ud(index), - fs_reg() /* surface_handle */, + elk_imm_ud(index), + elk_fs_reg() /* surface_handle */, inst->src[1], pull_index * 4, 4, 1); inst->remove(block); @@ -2328,27 +2328,27 @@ fs_visitor::lower_constant_loads() } static uint64_t -src_as_uint(const fs_reg &src) +src_as_uint(const elk_fs_reg &src) { assert(src.file == IMM); switch (src.type) { - case BRW_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_W: return (uint64_t)(int16_t)(src.ud & 0xffff); - case BRW_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_UW: return (uint64_t)(uint16_t)(src.ud & 0xffff); - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_D: return (uint64_t)src.d; - case BRW_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_UD: return (uint64_t)src.ud; - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_Q: return src.d64; - case BRW_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_UQ: return src.u64; default: @@ -2356,27 +2356,27 @@ src_as_uint(const fs_reg &src) } } -static fs_reg -brw_imm_for_type(uint64_t value, enum brw_reg_type type) +static elk_fs_reg +elk_imm_for_type(uint64_t value, enum elk_reg_type type) { switch (type) { - case BRW_REGISTER_TYPE_W: - return brw_imm_w(value); + case ELK_REGISTER_TYPE_W: + return elk_imm_w(value); - case BRW_REGISTER_TYPE_UW: - return brw_imm_uw(value); + case ELK_REGISTER_TYPE_UW: + return elk_imm_uw(value); - case BRW_REGISTER_TYPE_D: - return brw_imm_d(value); + case ELK_REGISTER_TYPE_D: + return elk_imm_d(value); - case BRW_REGISTER_TYPE_UD: - return brw_imm_ud(value); + case ELK_REGISTER_TYPE_UD: + return elk_imm_ud(value); - case BRW_REGISTER_TYPE_Q: - return brw_imm_d(value); + case ELK_REGISTER_TYPE_Q: + return elk_imm_d(value); - case BRW_REGISTER_TYPE_UQ: - return brw_imm_uq(value); + case ELK_REGISTER_TYPE_UQ: + return elk_imm_uq(value); default: unreachable("Invalid integer type."); @@ -2384,15 +2384,15 @@ brw_imm_for_type(uint64_t value, enum brw_reg_type type) } bool -fs_visitor::opt_algebraic() +elk_fs_visitor::opt_algebraic() { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { switch (inst->opcode) { - case BRW_OPCODE_MOV: + case ELK_OPCODE_MOV: if (!devinfo->has_64bit_float && - inst->dst.type == BRW_REGISTER_TYPE_DF) { + inst->dst.type == ELK_REGISTER_TYPE_DF) { assert(inst->dst.type == inst->src[0].type); assert(!inst->saturate); assert(!inst->src[0].abs); @@ -2402,18 +2402,18 @@ fs_visitor::opt_algebraic() if (!inst->is_partial_write()) ibld.emit_undef_for_dst(inst); - ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_F, 1), - subscript(inst->src[0], BRW_REGISTER_TYPE_F, 1)); - ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_F, 0), - subscript(inst->src[0], BRW_REGISTER_TYPE_F, 0)); + ibld.MOV(subscript(inst->dst, ELK_REGISTER_TYPE_F, 1), + subscript(inst->src[0], ELK_REGISTER_TYPE_F, 1)); + ibld.MOV(subscript(inst->dst, ELK_REGISTER_TYPE_F, 0), + subscript(inst->src[0], ELK_REGISTER_TYPE_F, 0)); inst->remove(block); progress = true; } if (!devinfo->has_64bit_int && - (inst->dst.type == BRW_REGISTER_TYPE_UQ || - inst->dst.type == BRW_REGISTER_TYPE_Q)) { + (inst->dst.type == ELK_REGISTER_TYPE_UQ || + inst->dst.type == ELK_REGISTER_TYPE_Q)) { assert(inst->dst.type == inst->src[0].type); assert(!inst->saturate); assert(!inst->src[0].abs); @@ -2423,17 +2423,17 @@ fs_visitor::opt_algebraic() if (!inst->is_partial_write()) ibld.emit_undef_for_dst(inst); - ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1), - subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1)); - ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0)); + ibld.MOV(subscript(inst->dst, ELK_REGISTER_TYPE_UD, 1), + subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 1)); + ibld.MOV(subscript(inst->dst, ELK_REGISTER_TYPE_UD, 0), + subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 0)); inst->remove(block); progress = true; } - if ((inst->conditional_mod == BRW_CONDITIONAL_Z || - inst->conditional_mod == BRW_CONDITIONAL_NZ) && + if ((inst->conditional_mod == ELK_CONDITIONAL_Z || + inst->conditional_mod == ELK_CONDITIONAL_NZ) && inst->dst.is_null() && (inst->src[0].abs || inst->src[0].negate)) { inst->src[0].abs = false; @@ -2454,23 +2454,23 @@ fs_visitor::opt_algebraic() * Other mixed-size-but-same-base-type cases may also be possible. */ if (inst->dst.type != inst->src[0].type && - inst->dst.type != BRW_REGISTER_TYPE_DF && - inst->src[0].type != BRW_REGISTER_TYPE_F) + inst->dst.type != ELK_REGISTER_TYPE_DF && + inst->src[0].type != ELK_REGISTER_TYPE_F) assert(!"unimplemented: saturate mixed types"); - if (brw_saturate_immediate(inst->src[0].type, - &inst->src[0].as_brw_reg())) { + if (elk_saturate_immediate(inst->src[0].type, + &inst->src[0].as_elk_reg())) { inst->saturate = false; progress = true; } } break; - case BRW_OPCODE_MUL: + case ELK_OPCODE_MUL: if (inst->src[1].file != IMM) continue; - if (brw_reg_type_is_floating_point(inst->src[1].type)) + if (elk_reg_type_is_floating_point(inst->src[1].type)) break; /* From the BDW PRM, Vol 2a, "mul - Multiply": @@ -2490,15 +2490,15 @@ fs_visitor::opt_algebraic() * we might use the full accumulator in the MUL/MACH macro, we * shouldn't replace such MULs with MOVs. */ - if ((brw_reg_type_to_size(inst->src[0].type) == 4 || - brw_reg_type_to_size(inst->src[1].type) == 4) && + if ((elk_reg_type_to_size(inst->src[0].type) == 4 || + elk_reg_type_to_size(inst->src[1].type) == 4) && (inst->dst.is_accumulator() || inst->writes_accumulator_implicitly(devinfo))) break; /* a * 1.0 = a */ if (inst->src[1].is_one()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; inst->src[1] = reg_undef; progress = true; @@ -2507,7 +2507,7 @@ fs_visitor::opt_algebraic() /* a * -1.0 = -a */ if (inst->src[1].is_negative_one()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; inst->src[0].negate = !inst->src[0].negate; inst->src[1] = reg_undef; @@ -2516,13 +2516,13 @@ fs_visitor::opt_algebraic() } break; - case BRW_OPCODE_ADD: + case ELK_OPCODE_ADD: if (inst->src[1].file != IMM) continue; - if (brw_reg_type_is_integer(inst->src[1].type) && + if (elk_reg_type_is_integer(inst->src[1].type) && inst->src[1].is_zero()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; inst->src[1] = reg_undef; progress = true; @@ -2530,8 +2530,8 @@ fs_visitor::opt_algebraic() } if (inst->src[0].file == IMM) { - assert(inst->src[0].type == BRW_REGISTER_TYPE_F); - inst->opcode = BRW_OPCODE_MOV; + assert(inst->src[0].type == ELK_REGISTER_TYPE_F); + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; inst->src[0].f += inst->src[1].f; inst->src[1] = reg_undef; @@ -2540,14 +2540,14 @@ fs_visitor::opt_algebraic() } break; - case BRW_OPCODE_AND: + case ELK_OPCODE_AND: if (inst->src[0].file == IMM && inst->src[1].file == IMM) { const uint64_t src0 = src_as_uint(inst->src[0]); const uint64_t src1 = src_as_uint(inst->src[1]); - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; - inst->src[0] = brw_imm_for_type(src0 & src1, inst->dst.type); + inst->src[0] = elk_imm_for_type(src0 & src1, inst->dst.type); inst->src[1] = reg_undef; progress = true; break; @@ -2555,14 +2555,14 @@ fs_visitor::opt_algebraic() break; - case BRW_OPCODE_OR: + case ELK_OPCODE_OR: if (inst->src[0].file == IMM && inst->src[1].file == IMM) { const uint64_t src0 = src_as_uint(inst->src[0]); const uint64_t src1 = src_as_uint(inst->src[1]); - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; - inst->src[0] = brw_imm_for_type(src0 | src1, inst->dst.type); + inst->src[0] = elk_imm_for_type(src0 | src1, inst->dst.type); inst->src[1] = reg_undef; progress = true; break; @@ -2575,11 +2575,11 @@ fs_visitor::opt_algebraic() * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV. */ if (inst->src[0].negate) { - inst->opcode = BRW_OPCODE_NOT; + inst->opcode = ELK_OPCODE_NOT; inst->sources = 1; inst->src[0].negate = false; } else { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; } inst->src[1] = reg_undef; @@ -2587,9 +2587,9 @@ fs_visitor::opt_algebraic() break; } break; - case BRW_OPCODE_CMP: - if ((inst->conditional_mod == BRW_CONDITIONAL_Z || - inst->conditional_mod == BRW_CONDITIONAL_NZ) && + case ELK_OPCODE_CMP: + if ((inst->conditional_mod == ELK_CONDITIONAL_Z || + inst->conditional_mod == ELK_CONDITIONAL_NZ) && inst->src[1].is_zero() && (inst->src[0].abs || inst->src[0].negate)) { inst->src[0].abs = false; @@ -2598,12 +2598,12 @@ fs_visitor::opt_algebraic() break; } break; - case BRW_OPCODE_SEL: + case ELK_OPCODE_SEL: if (!devinfo->has_64bit_float && !devinfo->has_64bit_int && - (inst->dst.type == BRW_REGISTER_TYPE_DF || - inst->dst.type == BRW_REGISTER_TYPE_UQ || - inst->dst.type == BRW_REGISTER_TYPE_Q)) { + (inst->dst.type == ELK_REGISTER_TYPE_DF || + inst->dst.type == ELK_REGISTER_TYPE_UQ || + inst->dst.type == ELK_REGISTER_TYPE_Q)) { assert(inst->dst.type == inst->src[0].type); assert(!inst->saturate); assert(!inst->src[0].abs && !inst->src[0].negate); @@ -2614,35 +2614,35 @@ fs_visitor::opt_algebraic() ibld.emit_undef_for_dst(inst); set_predicate(inst->predicate, - ibld.SEL(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0))); + ibld.SEL(subscript(inst->dst, ELK_REGISTER_TYPE_UD, 0), + subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 0), + subscript(inst->src[1], ELK_REGISTER_TYPE_UD, 0))); set_predicate(inst->predicate, - ibld.SEL(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1), - subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1), - subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 1))); + ibld.SEL(subscript(inst->dst, ELK_REGISTER_TYPE_UD, 1), + subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 1), + subscript(inst->src[1], ELK_REGISTER_TYPE_UD, 1))); inst->remove(block); progress = true; } if (inst->src[0].equals(inst->src[1])) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; inst->src[1] = reg_undef; - inst->predicate = BRW_PREDICATE_NONE; + inst->predicate = ELK_PREDICATE_NONE; inst->predicate_inverse = false; progress = true; } else if (inst->saturate && inst->src[1].file == IMM) { switch (inst->conditional_mod) { - case BRW_CONDITIONAL_LE: - case BRW_CONDITIONAL_L: + case ELK_CONDITIONAL_LE: + case ELK_CONDITIONAL_L: switch (inst->src[1].type) { - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: if (inst->src[1].f >= 1.0f) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; inst->src[1] = reg_undef; - inst->conditional_mod = BRW_CONDITIONAL_NONE; + inst->conditional_mod = ELK_CONDITIONAL_NONE; progress = true; } break; @@ -2650,15 +2650,15 @@ fs_visitor::opt_algebraic() break; } break; - case BRW_CONDITIONAL_GE: - case BRW_CONDITIONAL_G: + case ELK_CONDITIONAL_GE: + case ELK_CONDITIONAL_G: switch (inst->src[1].type) { - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: if (inst->src[1].f <= 0.0f) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; inst->src[1] = reg_undef; - inst->conditional_mod = BRW_CONDITIONAL_NONE; + inst->conditional_mod = ELK_CONDITIONAL_NONE; progress = true; } break; @@ -2670,49 +2670,49 @@ fs_visitor::opt_algebraic() } } break; - case BRW_OPCODE_MAD: - if (inst->src[0].type != BRW_REGISTER_TYPE_F || - inst->src[1].type != BRW_REGISTER_TYPE_F || - inst->src[2].type != BRW_REGISTER_TYPE_F) + case ELK_OPCODE_MAD: + if (inst->src[0].type != ELK_REGISTER_TYPE_F || + inst->src[1].type != ELK_REGISTER_TYPE_F || + inst->src[2].type != ELK_REGISTER_TYPE_F) break; if (inst->src[1].is_one()) { - inst->opcode = BRW_OPCODE_ADD; + inst->opcode = ELK_OPCODE_ADD; inst->sources = 2; inst->src[1] = inst->src[2]; inst->src[2] = reg_undef; progress = true; } else if (inst->src[2].is_one()) { - inst->opcode = BRW_OPCODE_ADD; + inst->opcode = ELK_OPCODE_ADD; inst->sources = 2; inst->src[2] = reg_undef; progress = true; } break; - case BRW_OPCODE_SHL: + case ELK_OPCODE_SHL: if (inst->src[0].file == IMM && inst->src[1].file == IMM) { /* It's not currently possible to generate this, and this constant * folding does not handle it. */ assert(!inst->saturate); - fs_reg result; + elk_fs_reg result; switch (type_sz(inst->src[0].type)) { case 2: - result = brw_imm_uw(0x0ffff & (inst->src[0].ud << (inst->src[1].ud & 0x1f))); + result = elk_imm_uw(0x0ffff & (inst->src[0].ud << (inst->src[1].ud & 0x1f))); break; case 4: - result = brw_imm_ud(inst->src[0].ud << (inst->src[1].ud & 0x1f)); + result = elk_imm_ud(inst->src[0].ud << (inst->src[1].ud & 0x1f)); break; case 8: - result = brw_imm_uq(inst->src[0].u64 << (inst->src[1].ud & 0x3f)); + result = elk_imm_uq(inst->src[0].u64 << (inst->src[1].ud & 0x3f)); break; default: /* Just in case a future platform re-enables B or UB types. */ unreachable("Invalid source size."); } - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->src[0] = retype(result, inst->dst.type); inst->src[1] = reg_undef; inst->sources = 1; @@ -2721,14 +2721,14 @@ fs_visitor::opt_algebraic() } break; - case SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_BROADCAST: if (is_uniform(inst->src[0])) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; inst->force_writemask_all = true; progress = true; } else if (inst->src[1].file == IMM) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; /* It's possible that the selected component will be too large and * overflow the register. This can happen if someone does a * readInvocation() from GLSL or SPIR-V and provides an OOB @@ -2746,13 +2746,13 @@ fs_visitor::opt_algebraic() } break; - case SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_SHUFFLE: if (is_uniform(inst->src[0])) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->sources = 1; progress = true; } else if (inst->src[1].file == IMM) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->src[0] = component(inst->src[0], inst->src[1].ud); inst->sources = 1; @@ -2772,7 +2772,7 @@ fs_visitor::opt_algebraic() */ if (progress && inst->sources == 2 && inst->is_commutative()) { if (inst->src[0].file == IMM) { - fs_reg tmp = inst->src[1]; + elk_fs_reg tmp = inst->src[1]; inst->src[1] = inst->src[0]; inst->src[0] = tmp; } @@ -2787,9 +2787,9 @@ fs_visitor::opt_algebraic() } static unsigned -load_payload_sources_read_for_size(fs_inst *lp, unsigned size_read) +load_payload_sources_read_for_size(elk_fs_inst *lp, unsigned size_read) { - assert(lp->opcode == SHADER_OPCODE_LOAD_PAYLOAD); + assert(lp->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD); assert(size_read >= lp->header_size * REG_SIZE); unsigned i; @@ -2811,16 +2811,16 @@ load_payload_sources_read_for_size(fs_inst *lp, unsigned size_read) * set up the zero value. */ bool -fs_visitor::opt_zero_samples() +elk_fs_visitor::opt_zero_samples() { /* Implementation supports only SENDs, so applicable to Gfx7+ only. */ assert(devinfo->ver >= 7); bool progress = false; - foreach_block_and_inst(block, fs_inst, send, cfg) { - if (send->opcode != SHADER_OPCODE_SEND || - send->sfid != BRW_SFID_SAMPLER) + foreach_block_and_inst(block, elk_fs_inst, send, cfg) { + if (send->opcode != ELK_SHADER_OPCODE_SEND || + send->sfid != ELK_SFID_SAMPLER) continue; /* Wa_14012688258: @@ -2835,9 +2835,9 @@ fs_visitor::opt_zero_samples() if (send->ex_mlen > 0) continue; - fs_inst *lp = (fs_inst *) send->prev; + elk_fs_inst *lp = (elk_fs_inst *) send->prev; - if (lp->is_head_sentinel() || lp->opcode != SHADER_OPCODE_LOAD_PAYLOAD) + if (lp->is_head_sentinel() || lp->opcode != ELK_SHADER_OPCODE_LOAD_PAYLOAD) continue; /* How much of the payload are actually read by this SEND. */ @@ -2889,24 +2889,24 @@ fs_visitor::opt_zero_samples() * payload concatenation altogether. */ bool -fs_visitor::opt_split_sends() +elk_fs_visitor::opt_split_sends() { if (devinfo->ver < 9) return false; bool progress = false; - foreach_block_and_inst(block, fs_inst, send, cfg) { - if (send->opcode != SHADER_OPCODE_SEND || + foreach_block_and_inst(block, elk_fs_inst, send, cfg) { + if (send->opcode != ELK_SHADER_OPCODE_SEND || send->mlen <= reg_unit(devinfo) || send->ex_mlen > 0) continue; assert(send->src[2].file == VGRF); /* Currently don't split sends that reuse a previously used payload. */ - fs_inst *lp = (fs_inst *) send->prev; + elk_fs_inst *lp = (elk_fs_inst *) send->prev; - if (lp->is_head_sentinel() || lp->opcode != SHADER_OPCODE_LOAD_PAYLOAD) + if (lp->is_head_sentinel() || lp->opcode != ELK_SHADER_OPCODE_LOAD_PAYLOAD) continue; if (lp->dst.file != send->src[2].file || lp->dst.nr != send->src[2].nr) @@ -2938,15 +2938,15 @@ fs_visitor::opt_split_sends() continue; const fs_builder ibld(this, block, lp); - fs_inst *lp1 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[0], mid, lp->header_size); - fs_inst *lp2 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[mid], end - mid, 0); + elk_fs_inst *lp1 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[0], mid, lp->header_size); + elk_fs_inst *lp2 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[mid], end - mid, 0); assert(lp1->size_written % REG_SIZE == 0); assert(lp2->size_written % REG_SIZE == 0); assert((lp1->size_written + lp2->size_written) / REG_SIZE == send->mlen); - lp1->dst = fs_reg(VGRF, alloc.allocate(lp1->size_written / REG_SIZE), lp1->dst.type); - lp2->dst = fs_reg(VGRF, alloc.allocate(lp2->size_written / REG_SIZE), lp2->dst.type); + lp1->dst = elk_fs_reg(VGRF, alloc.allocate(lp1->size_written / REG_SIZE), lp1->dst.type); + lp2->dst = elk_fs_reg(VGRF, alloc.allocate(lp2->size_written / REG_SIZE), lp2->dst.type); send->resize_sources(4); send->src[2] = lp1->dst; @@ -2973,18 +2973,18 @@ fs_visitor::opt_split_sends() * halt-target */ bool -fs_visitor::opt_redundant_halt() +elk_fs_visitor::opt_redundant_halt() { bool progress = false; unsigned halt_count = 0; - fs_inst *halt_target = NULL; - bblock_t *halt_target_block = NULL; - foreach_block_and_inst(block, fs_inst, inst, cfg) { - if (inst->opcode == BRW_OPCODE_HALT) + elk_fs_inst *halt_target = NULL; + elk_bblock_t *halt_target_block = NULL; + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { + if (inst->opcode == ELK_OPCODE_HALT) halt_count++; - if (inst->opcode == SHADER_OPCODE_HALT_TARGET) { + if (inst->opcode == ELK_SHADER_OPCODE_HALT_TARGET) { halt_target = inst; halt_target_block = block; break; @@ -2997,9 +2997,9 @@ fs_visitor::opt_redundant_halt() } /* Delete any HALTs immediately before the halt target. */ - for (fs_inst *prev = (fs_inst *) halt_target->prev; - !prev->is_head_sentinel() && prev->opcode == BRW_OPCODE_HALT; - prev = (fs_inst *) halt_target->prev) { + for (elk_fs_inst *prev = (elk_fs_inst *) halt_target->prev; + !prev->is_head_sentinel() && prev->opcode == ELK_OPCODE_HALT; + prev = (elk_fs_inst *) halt_target->prev) { prev->remove(halt_target_block); halt_count--; progress = true; @@ -3022,7 +3022,7 @@ fs_visitor::opt_redundant_halt() * spanning \p ds bytes. */ static inline unsigned -mask_relative_to(const fs_reg &r, const fs_reg &s, unsigned ds) +mask_relative_to(const elk_fs_reg &r, const elk_fs_reg &s, unsigned ds) { const int rel_offset = reg_offset(s) - reg_offset(r); const int shift = rel_offset / REG_SIZE; @@ -3033,7 +3033,7 @@ mask_relative_to(const fs_reg &r, const fs_reg &s, unsigned ds) } bool -fs_visitor::compute_to_mrf() +elk_fs_visitor::compute_to_mrf() { bool progress = false; int next_ip = 0; @@ -3044,11 +3044,11 @@ fs_visitor::compute_to_mrf() const fs_live_variables &live = live_analysis.require(); - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { int ip = next_ip; next_ip++; - if (inst->opcode != BRW_OPCODE_MOV || + if (inst->opcode != ELK_OPCODE_MOV || inst->is_partial_write() || inst->dst.file != MRF || inst->src[0].file != VGRF || inst->dst.type != inst->src[0].type || @@ -3070,7 +3070,7 @@ fs_visitor::compute_to_mrf() */ unsigned regs_left = (1 << regs_read(inst, 0)) - 1; - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) { if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) { /* Found the last thing to write our reg we want to turn @@ -3142,7 +3142,7 @@ fs_visitor::compute_to_mrf() } if (scan_inst->mlen > 0 && scan_inst->base_mrf != -1 && - regions_overlap(fs_reg(MRF, scan_inst->base_mrf), scan_inst->mlen * REG_SIZE, + regions_overlap(elk_fs_reg(MRF, scan_inst->base_mrf), scan_inst->mlen * REG_SIZE, inst->dst, inst->size_written)) { /* Found a SEND instruction, which means that there are * live values in MRFs from base_mrf to base_mrf + @@ -3161,7 +3161,7 @@ fs_visitor::compute_to_mrf() */ regs_left = (1 << regs_read(inst, 0)) - 1; - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) { if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) { /* Clear the bits for any registers this instruction overwrites. */ @@ -3171,7 +3171,7 @@ fs_visitor::compute_to_mrf() const unsigned rel_offset = reg_offset(scan_inst->dst) - reg_offset(inst->src[0]); - if (inst->dst.nr & BRW_MRF_COMPR4) { + if (inst->dst.nr & ELK_MRF_COMPR4) { /* Apply the same address transformation done by the hardware * for COMPR4 MRF writes. */ @@ -3182,7 +3182,7 @@ fs_visitor::compute_to_mrf() * compressed. */ if (scan_inst->size_written < 2 * REG_SIZE) - scan_inst->dst.nr &= ~BRW_MRF_COMPR4; + scan_inst->dst.nr &= ~ELK_MRF_COMPR4; } else { /* Calculate the MRF number the result of this instruction is @@ -3216,12 +3216,12 @@ fs_visitor::compute_to_mrf() * analysis. */ bool -fs_visitor::eliminate_find_live_channel() +elk_fs_visitor::eliminate_find_live_channel() { bool progress = false; unsigned depth = 0; - if (!brw_stage_has_packed_dispatch(devinfo, stage, max_polygons, + if (!elk_stage_has_packed_dispatch(devinfo, stage, max_polygons, stage_prog_data)) { /* The optimization below assumes that channel zero is live on thread * dispatch, which may not be the case if the fixed function dispatches @@ -3230,28 +3230,28 @@ fs_visitor::eliminate_find_live_channel() return false; } - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { switch (inst->opcode) { - case BRW_OPCODE_IF: - case BRW_OPCODE_DO: + case ELK_OPCODE_IF: + case ELK_OPCODE_DO: depth++; break; - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_WHILE: + case ELK_OPCODE_ENDIF: + case ELK_OPCODE_WHILE: depth--; break; - case BRW_OPCODE_HALT: + case ELK_OPCODE_HALT: /* This can potentially make control flow non-uniform until the end * of the program. */ goto out; - case SHADER_OPCODE_FIND_LIVE_CHANNEL: + case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL: if (depth == 0) { - inst->opcode = BRW_OPCODE_MOV; - inst->src[0] = brw_imm_ud(0u); + inst->opcode = ELK_OPCODE_MOV; + inst->src[0] = elk_imm_ud(0u); inst->sources = 1; inst->force_writemask_all = true; progress = true; @@ -3271,32 +3271,32 @@ out: } /** - * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE - * instructions to FS_OPCODE_REP_FB_WRITE. + * Once we've generated code, try to convert normal ELK_FS_OPCODE_FB_WRITE + * instructions to ELK_FS_OPCODE_REP_FB_WRITE. */ void -fs_visitor::emit_repclear_shader() +elk_fs_visitor::emit_repclear_shader() { - brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; - fs_inst *write = NULL; + elk_wm_prog_key *key = (elk_wm_prog_key*) this->key; + elk_fs_inst *write = NULL; assert(uniforms == 0); assume(key->nr_color_regions > 0); - fs_reg color_output, header; + elk_fs_reg color_output, header; if (devinfo->ver >= 7) { - color_output = retype(brw_vec4_grf(127, 0), BRW_REGISTER_TYPE_UD); - header = retype(brw_vec8_grf(125, 0), BRW_REGISTER_TYPE_UD); + color_output = retype(elk_vec4_grf(127, 0), ELK_REGISTER_TYPE_UD); + header = retype(elk_vec8_grf(125, 0), ELK_REGISTER_TYPE_UD); } else { - color_output = retype(brw_vec4_reg(MRF, 2, 0), BRW_REGISTER_TYPE_UD); - header = retype(brw_vec8_reg(MRF, 0, 0), BRW_REGISTER_TYPE_UD); + color_output = retype(elk_vec4_reg(MRF, 2, 0), ELK_REGISTER_TYPE_UD); + header = retype(elk_vec8_reg(MRF, 0, 0), ELK_REGISTER_TYPE_UD); } /* We pass the clear color as a flat input. Copy it to the output. */ - fs_reg color_input = - brw_reg(BRW_GENERAL_REGISTER_FILE, 2, 3, 0, 0, BRW_REGISTER_TYPE_UD, - BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4, - BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); + elk_fs_reg color_input = + elk_reg(ELK_GENERAL_REGISTER_FILE, 2, 3, 0, 0, ELK_REGISTER_TYPE_UD, + ELK_VERTICAL_STRIDE_8, ELK_WIDTH_2, ELK_HORIZONTAL_STRIDE_4, + ELK_SWIZZLE_XYZW, WRITEMASK_XYZW); const fs_builder bld = fs_builder(this).at_end(); bld.exec_all().group(4, 0).MOV(color_output, color_input); @@ -3304,27 +3304,27 @@ fs_visitor::emit_repclear_shader() if (key->nr_color_regions > 1) { /* Copy g0..g1 as the message header */ bld.exec_all().group(16, 0) - .MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + .MOV(header, retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); } for (int i = 0; i < key->nr_color_regions; ++i) { if (i > 0) - bld.exec_all().group(1, 0).MOV(component(header, 2), brw_imm_ud(i)); + bld.exec_all().group(1, 0).MOV(component(header, 2), elk_imm_ud(i)); if (devinfo->ver >= 7) { - write = bld.emit(SHADER_OPCODE_SEND); + write = bld.emit(ELK_SHADER_OPCODE_SEND); write->resize_sources(3); write->sfid = GFX6_SFID_DATAPORT_RENDER_CACHE; - write->src[0] = brw_imm_ud(0); - write->src[1] = brw_imm_ud(0); + write->src[0] = elk_imm_ud(0); + write->src[1] = elk_imm_ud(0); write->src[2] = i == 0 ? color_output : header; write->check_tdr = true; write->send_has_side_effects = true; - write->desc = brw_fb_write_desc(devinfo, i, - BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED, + write->desc = elk_fb_write_desc(devinfo, i, + ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED, i == key->nr_color_regions - 1, false); } else { - write = bld.emit(FS_OPCODE_REP_FB_WRITE); + write = bld.emit(ELK_FS_OPCODE_REP_FB_WRITE); write->target = i; write->base_mrf = i == 0 ? color_output.nr : header.nr; } @@ -3346,9 +3346,9 @@ fs_visitor::emit_repclear_shader() * removing the later ones. */ bool -fs_visitor::remove_duplicate_mrf_writes() +elk_fs_visitor::remove_duplicate_mrf_writes() { - fs_inst *last_mrf_move[BRW_MAX_MRF(devinfo->ver)]; + elk_fs_inst *last_mrf_move[ELK_MAX_MRF(devinfo->ver)]; bool progress = false; /* Need to update the MRF tracking for compressed instructions. */ @@ -3357,15 +3357,15 @@ fs_visitor::remove_duplicate_mrf_writes() memset(last_mrf_move, 0, sizeof(last_mrf_move)); - foreach_block_and_inst_safe (block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe (block, elk_fs_inst, inst, cfg) { if (inst->is_control_flow()) { memset(last_mrf_move, 0, sizeof(last_mrf_move)); } - if (inst->opcode == BRW_OPCODE_MOV && + if (inst->opcode == ELK_OPCODE_MOV && inst->dst.file == MRF) { - fs_inst *prev_inst = last_mrf_move[inst->dst.nr]; - if (prev_inst && prev_inst->opcode == BRW_OPCODE_MOV && + elk_fs_inst *prev_inst = last_mrf_move[inst->dst.nr]; + if (prev_inst && prev_inst->opcode == ELK_OPCODE_MOV && inst->dst.equals(prev_inst->dst) && inst->src[0].equals(prev_inst->src[0]) && inst->saturate == prev_inst->saturate && @@ -3402,7 +3402,7 @@ fs_visitor::remove_duplicate_mrf_writes() } } - if (inst->opcode == BRW_OPCODE_MOV && + if (inst->opcode == ELK_OPCODE_MOV && inst->dst.file == MRF && inst->src[0].file != ARF && !inst->is_partial_write()) { @@ -3425,30 +3425,30 @@ fs_visitor::remove_duplicate_mrf_writes() * mode once is enough for the full vector/matrix */ bool -fs_visitor::remove_extra_rounding_modes() +elk_fs_visitor::remove_extra_rounding_modes() { bool progress = false; unsigned execution_mode = this->nir->info.float_controls_execution_mode; - brw_rnd_mode base_mode = BRW_RND_MODE_UNSPECIFIED; + elk_rnd_mode base_mode = ELK_RND_MODE_UNSPECIFIED; if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64) & execution_mode) - base_mode = BRW_RND_MODE_RTNE; + base_mode = ELK_RND_MODE_RTNE; if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64) & execution_mode) - base_mode = BRW_RND_MODE_RTZ; + base_mode = ELK_RND_MODE_RTZ; foreach_block (block, cfg) { - brw_rnd_mode prev_mode = base_mode; + elk_rnd_mode prev_mode = base_mode; - foreach_inst_in_block_safe (fs_inst, inst, block) { - if (inst->opcode == SHADER_OPCODE_RND_MODE) { - assert(inst->src[0].file == BRW_IMMEDIATE_VALUE); - const brw_rnd_mode mode = (brw_rnd_mode) inst->src[0].d; + foreach_inst_in_block_safe (elk_fs_inst, inst, block) { + if (inst->opcode == ELK_SHADER_OPCODE_RND_MODE) { + assert(inst->src[0].file == ELK_IMMEDIATE_VALUE); + const elk_rnd_mode mode = (elk_rnd_mode) inst->src[0].d; if (mode == prev_mode) { inst->remove(block); progress = true; @@ -3466,7 +3466,7 @@ fs_visitor::remove_extra_rounding_modes() } static void -clear_deps_for_inst_src(fs_inst *inst, bool *deps, int first_grf, int grf_len) +clear_deps_for_inst_src(elk_fs_inst *inst, bool *deps, int first_grf, int grf_len) { /* Clear the flag for registers that actually got read (as expected). */ for (int i = 0; i < inst->sources; i++) { @@ -3503,12 +3503,12 @@ clear_deps_for_inst_src(fs_inst *inst, bool *deps, int first_grf, int grf_len) * same time that both consider ‘r3’ as the target of their final writes. */ void -fs_visitor::insert_gfx4_pre_send_dependency_workarounds(bblock_t *block, - fs_inst *inst) +elk_fs_visitor::insert_gfx4_pre_send_dependency_workarounds(elk_bblock_t *block, + elk_fs_inst *inst) { int write_len = regs_written(inst); int first_write_grf = inst->dst.nr; - bool needs_dep[BRW_MAX_MRF(devinfo->ver)]; + bool needs_dep[ELK_MAX_MRF(devinfo->ver)]; assert(write_len < (int)sizeof(needs_dep) - 1); memset(needs_dep, false, sizeof(needs_dep)); @@ -3521,7 +3521,7 @@ fs_visitor::insert_gfx4_pre_send_dependency_workarounds(bblock_t *block, * we assume that there are no outstanding dependencies on entry to the * program. */ - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) { /* If we hit control flow, assume that there *are* outstanding * dependencies, and force their cleanup before our instruction. */ @@ -3575,11 +3575,11 @@ fs_visitor::insert_gfx4_pre_send_dependency_workarounds(bblock_t *block, * instruction with a different destination register. */ void -fs_visitor::insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_inst *inst) +elk_fs_visitor::insert_gfx4_post_send_dependency_workarounds(elk_bblock_t *block, elk_fs_inst *inst) { int write_len = regs_written(inst); unsigned first_write_grf = inst->dst.nr; - bool needs_dep[BRW_MAX_MRF(devinfo->ver)]; + bool needs_dep[ELK_MAX_MRF(devinfo->ver)]; assert(write_len < (int)sizeof(needs_dep) - 1); memset(needs_dep, false, sizeof(needs_dep)); @@ -3587,7 +3587,7 @@ fs_visitor::insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_ins /* Walk forwards looking for writes to registers we're writing which aren't * read before being written. */ - foreach_inst_in_block_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_starting_from(elk_fs_inst, scan_inst, inst) { /* If we hit control flow, force resolve all remaining dependencies. */ if (block->end() == scan_inst && block->num != cfg->num_blocks - 1) { for (int i = 0; i < write_len; i++) { @@ -3625,14 +3625,14 @@ fs_visitor::insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_ins } void -fs_visitor::insert_gfx4_send_dependency_workarounds() +elk_fs_visitor::insert_gfx4_send_dependency_workarounds() { if (devinfo->ver != 4 || devinfo->platform == INTEL_PLATFORM_G4X) return; bool progress = false; - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { if (inst->mlen != 0 && inst->dst.file == VGRF) { insert_gfx4_pre_send_dependency_workarounds(block, inst); insert_gfx4_post_send_dependency_workarounds(block, inst); @@ -3645,21 +3645,21 @@ fs_visitor::insert_gfx4_send_dependency_workarounds() } bool -fs_visitor::lower_load_payload() +elk_fs_visitor::lower_load_payload() { bool progress = false; - foreach_block_and_inst_safe (block, fs_inst, inst, cfg) { - if (inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) + foreach_block_and_inst_safe (block, elk_fs_inst, inst, cfg) { + if (inst->opcode != ELK_SHADER_OPCODE_LOAD_PAYLOAD) continue; assert(inst->dst.file == MRF || inst->dst.file == VGRF); assert(inst->saturate == false); - fs_reg dst = inst->dst; + elk_fs_reg dst = inst->dst; /* Get rid of COMPR4. We'll add it back in if we need it */ if (dst.file == MRF) - dst.nr = dst.nr & ~BRW_MRF_COMPR4; + dst.nr = dst.nr & ~ELK_MRF_COMPR4; const fs_builder ibld(this, block, inst); const fs_builder ubld = ibld.exec_all(); @@ -3674,14 +3674,14 @@ fs_visitor::lower_load_payload() 2 : 1; if (inst->src[i].file != BAD_FILE) - ubld.group(8 * n, 0).MOV(retype(dst, BRW_REGISTER_TYPE_UD), - retype(inst->src[i], BRW_REGISTER_TYPE_UD)); + ubld.group(8 * n, 0).MOV(retype(dst, ELK_REGISTER_TYPE_UD), + retype(inst->src[i], ELK_REGISTER_TYPE_UD)); dst = byte_offset(dst, n * REG_SIZE); i += n; } - if (inst->dst.file == MRF && (inst->dst.nr & BRW_MRF_COMPR4) && + if (inst->dst.file == MRF && (inst->dst.nr & ELK_MRF_COMPR4) && inst->exec_size > 8) { /* In this case, the payload portion of the LOAD_PAYLOAD isn't * a straightforward copy. Instead, the result of the @@ -3704,12 +3704,12 @@ fs_visitor::lower_load_payload() for (uint8_t i = inst->header_size; i < inst->header_size + 4; i++) { if (inst->src[i].file != BAD_FILE) { if (devinfo->has_compr4) { - fs_reg compr4_dst = retype(dst, inst->src[i].type); - compr4_dst.nr |= BRW_MRF_COMPR4; + elk_fs_reg compr4_dst = retype(dst, inst->src[i].type); + compr4_dst.nr |= ELK_MRF_COMPR4; ibld.MOV(compr4_dst, inst->src[i]); } else { /* Platform doesn't have COMPR4. We have to fake it */ - fs_reg mov_dst = retype(dst, inst->src[i].type); + elk_fs_reg mov_dst = retype(dst, inst->src[i].type); ibld.quarter(0).MOV(mov_dst, quarter(inst->src[i], 0)); mov_dst.nr += 4; ibld.quarter(1).MOV(mov_dst, quarter(inst->src[i], 1)); @@ -3883,7 +3883,7 @@ factor_uint32(uint32_t x, unsigned *result_a, unsigned *result_b) } void -fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block) +elk_fs_visitor::lower_mul_dword_inst(elk_fs_inst *inst, elk_bblock_t *block) { const fs_builder ibld(this, block, inst); @@ -3902,13 +3902,13 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block) */ const bool ud = (inst->src[1].d >= 0); if (devinfo->ver < 7) { - fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type); + elk_fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type); ibld.MOV(imm, inst->src[1]); ibld.MUL(inst->dst, imm, inst->src[0]); } else { ibld.MUL(inst->dst, inst->src[0], - ud ? brw_imm_uw(inst->src[1].ud) - : brw_imm_w(inst->src[1].d)); + ud ? elk_imm_uw(inst->src[1].ud) + : elk_imm_w(inst->src[1].d)); } } else { /* Gen < 8 (and some Gfx8+ low-power parts like Cherryview) cannot @@ -3957,14 +3957,14 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block) */ bool needs_mov = false; - fs_reg orig_dst = inst->dst; + elk_fs_reg orig_dst = inst->dst; /* Get a new VGRF for the "low" 32x16-bit multiplication result if * reusing the original destination is impossible due to hardware * restrictions, source/destination overlap, or it being the null * register. */ - fs_reg low = inst->dst; + elk_fs_reg low = inst->dst; if (orig_dst.is_null() || orig_dst.file == MRF || regions_overlap(inst->dst, inst->size_written, inst->src[0], inst->size_read(0)) || @@ -3972,12 +3972,12 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block) inst->src[1], inst->size_read(1)) || inst->dst.stride >= 4) { needs_mov = true; - low = fs_reg(VGRF, alloc.allocate(regs_written(inst)), + low = elk_fs_reg(VGRF, alloc.allocate(regs_written(inst)), inst->dst.type); } /* Get a new VGRF but keep the same stride as inst->dst */ - fs_reg high(VGRF, alloc.allocate(regs_written(inst)), inst->dst.type); + elk_fs_reg high(VGRF, alloc.allocate(regs_written(inst)), inst->dst.type); high.stride = inst->dst.stride; high.offset = inst->dst.offset % REG_SIZE; @@ -4019,38 +4019,38 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block) factor_uint32(inst->src[1].ud, &a, &b); if (a != 0) { - ibld.MUL(low, inst->src[0], brw_imm_uw(a)); - ibld.MUL(low, low, brw_imm_uw(b)); + ibld.MUL(low, inst->src[0], elk_imm_uw(a)); + ibld.MUL(low, low, elk_imm_uw(b)); do_addition = false; } } if (do_addition) { ibld.MUL(low, inst->src[0], - brw_imm_uw(inst->src[1].ud & 0xffff)); + elk_imm_uw(inst->src[1].ud & 0xffff)); ibld.MUL(high, inst->src[0], - brw_imm_uw(inst->src[1].ud >> 16)); + elk_imm_uw(inst->src[1].ud >> 16)); } } else { ibld.MUL(low, inst->src[0], - subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 0)); + subscript(inst->src[1], ELK_REGISTER_TYPE_UW, 0)); ibld.MUL(high, inst->src[0], - subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 1)); + subscript(inst->src[1], ELK_REGISTER_TYPE_UW, 1)); } } else { if (inst->src[0].abs) lower_src_modifiers(this, block, inst, 0); - ibld.MUL(low, subscript(inst->src[0], BRW_REGISTER_TYPE_UW, 0), + ibld.MUL(low, subscript(inst->src[0], ELK_REGISTER_TYPE_UW, 0), inst->src[1]); - ibld.MUL(high, subscript(inst->src[0], BRW_REGISTER_TYPE_UW, 1), + ibld.MUL(high, subscript(inst->src[0], ELK_REGISTER_TYPE_UW, 1), inst->src[1]); } if (do_addition) { - ibld.ADD(subscript(low, BRW_REGISTER_TYPE_UW, 1), - subscript(low, BRW_REGISTER_TYPE_UW, 1), - subscript(high, BRW_REGISTER_TYPE_UW, 0)); + ibld.ADD(subscript(low, ELK_REGISTER_TYPE_UW, 1), + subscript(low, ELK_REGISTER_TYPE_UW, 1), + subscript(high, ELK_REGISTER_TYPE_UW, 0)); } if (needs_mov || inst->conditional_mod) @@ -4059,7 +4059,7 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block) } void -fs_visitor::lower_mul_qword_inst(fs_inst *inst, bblock_t *block) +elk_fs_visitor::lower_mul_qword_inst(elk_fs_inst *inst, elk_bblock_t *block) { const fs_builder ibld(this, block, inst); @@ -4076,58 +4076,58 @@ fs_visitor::lower_mul_qword_inst(fs_inst *inst, bblock_t *block) unsigned int q_regs = regs_written(inst); unsigned int d_regs = (q_regs + 1) / 2; - fs_reg bd(VGRF, alloc.allocate(q_regs), BRW_REGISTER_TYPE_UQ); - fs_reg ad(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD); - fs_reg bc(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD); + elk_fs_reg bd(VGRF, alloc.allocate(q_regs), ELK_REGISTER_TYPE_UQ); + elk_fs_reg ad(VGRF, alloc.allocate(d_regs), ELK_REGISTER_TYPE_UD); + elk_fs_reg bc(VGRF, alloc.allocate(d_regs), ELK_REGISTER_TYPE_UD); /* Here we need the full 64 bit result for 32b * 32b. */ if (devinfo->has_integer_dword_mul) { - ibld.MUL(bd, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0)); + ibld.MUL(bd, subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 0), + subscript(inst->src[1], ELK_REGISTER_TYPE_UD, 0)); } else { - fs_reg bd_high(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD); - fs_reg bd_low(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD); + elk_fs_reg bd_high(VGRF, alloc.allocate(d_regs), ELK_REGISTER_TYPE_UD); + elk_fs_reg bd_low(VGRF, alloc.allocate(d_regs), ELK_REGISTER_TYPE_UD); const unsigned acc_width = reg_unit(devinfo) * 8; - fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_REGISTER_TYPE_UD), + elk_fs_reg acc = suboffset(retype(elk_acc_reg(inst->exec_size), ELK_REGISTER_TYPE_UD), inst->group % acc_width); - fs_inst *mul = ibld.MUL(acc, - subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[1], BRW_REGISTER_TYPE_UW, 0)); + elk_fs_inst *mul = ibld.MUL(acc, + subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 0), + subscript(inst->src[1], ELK_REGISTER_TYPE_UW, 0)); mul->writes_accumulator = true; - ibld.MACH(bd_high, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0)); + ibld.MACH(bd_high, subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 0), + subscript(inst->src[1], ELK_REGISTER_TYPE_UD, 0)); ibld.MOV(bd_low, acc); ibld.UNDEF(bd); - ibld.MOV(subscript(bd, BRW_REGISTER_TYPE_UD, 0), bd_low); - ibld.MOV(subscript(bd, BRW_REGISTER_TYPE_UD, 1), bd_high); + ibld.MOV(subscript(bd, ELK_REGISTER_TYPE_UD, 0), bd_low); + ibld.MOV(subscript(bd, ELK_REGISTER_TYPE_UD, 1), bd_high); } - ibld.MUL(ad, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1), - subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0)); - ibld.MUL(bc, subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 1)); + ibld.MUL(ad, subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 1), + subscript(inst->src[1], ELK_REGISTER_TYPE_UD, 0)); + ibld.MUL(bc, subscript(inst->src[0], ELK_REGISTER_TYPE_UD, 0), + subscript(inst->src[1], ELK_REGISTER_TYPE_UD, 1)); ibld.ADD(ad, ad, bc); - ibld.ADD(subscript(bd, BRW_REGISTER_TYPE_UD, 1), - subscript(bd, BRW_REGISTER_TYPE_UD, 1), ad); + ibld.ADD(subscript(bd, ELK_REGISTER_TYPE_UD, 1), + subscript(bd, ELK_REGISTER_TYPE_UD, 1), ad); if (devinfo->has_64bit_int) { ibld.MOV(inst->dst, bd); } else { if (!inst->is_partial_write()) ibld.emit_undef_for_dst(inst); - ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0), - subscript(bd, BRW_REGISTER_TYPE_UD, 0)); - ibld.MOV(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1), - subscript(bd, BRW_REGISTER_TYPE_UD, 1)); + ibld.MOV(subscript(inst->dst, ELK_REGISTER_TYPE_UD, 0), + subscript(bd, ELK_REGISTER_TYPE_UD, 0)); + ibld.MOV(subscript(inst->dst, ELK_REGISTER_TYPE_UD, 1), + subscript(bd, ELK_REGISTER_TYPE_UD, 1)); } } void -fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block) +elk_fs_visitor::lower_mulh_inst(elk_fs_inst *inst, elk_bblock_t *block) { const fs_builder ibld(this, block, inst); @@ -4146,10 +4146,10 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block) /* Should have been lowered to 8-wide. */ assert(inst->exec_size <= get_lowered_simd_width(this, inst)); const unsigned acc_width = reg_unit(devinfo) * 8; - const fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), inst->dst.type), + const elk_fs_reg acc = suboffset(retype(elk_acc_reg(inst->exec_size), inst->dst.type), inst->group % acc_width); - fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]); - fs_inst *mach = ibld.MACH(inst->dst, inst->src[0], inst->src[1]); + elk_fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]); + elk_fs_inst *mach = ibld.MACH(inst->dst, inst->src[0], inst->src[1]); if (devinfo->ver >= 8) { /* Until Gfx8, integer multiplies read 32-bits from one source, @@ -4160,13 +4160,13 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block) * multiply, but in order to do a 64-bit multiply we can simulate * the previous behavior and then use a MACH instruction. */ - assert(mul->src[1].type == BRW_REGISTER_TYPE_D || - mul->src[1].type == BRW_REGISTER_TYPE_UD); - mul->src[1].type = BRW_REGISTER_TYPE_UW; + assert(mul->src[1].type == ELK_REGISTER_TYPE_D || + mul->src[1].type == ELK_REGISTER_TYPE_UD); + mul->src[1].type = ELK_REGISTER_TYPE_UW; mul->src[1].stride *= 2; if (mul->src[1].file == IMM) { - mul->src[1] = brw_imm_uw(mul->src[1].ud); + mul->src[1] = elk_imm_uw(mul->src[1].ud); } } else if (devinfo->verx10 == 70 && inst->group > 0) { @@ -4194,12 +4194,12 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block) } bool -fs_visitor::lower_integer_multiplication() +elk_fs_visitor::lower_integer_multiplication() { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { - if (inst->opcode == BRW_OPCODE_MUL) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { + if (inst->opcode == ELK_OPCODE_MUL) { /* If the instruction is already in a form that does not need lowering, * return early. */ @@ -4211,25 +4211,25 @@ fs_visitor::lower_integer_multiplication() continue; } - if ((inst->dst.type == BRW_REGISTER_TYPE_Q || - inst->dst.type == BRW_REGISTER_TYPE_UQ) && - (inst->src[0].type == BRW_REGISTER_TYPE_Q || - inst->src[0].type == BRW_REGISTER_TYPE_UQ) && - (inst->src[1].type == BRW_REGISTER_TYPE_Q || - inst->src[1].type == BRW_REGISTER_TYPE_UQ)) { + if ((inst->dst.type == ELK_REGISTER_TYPE_Q || + inst->dst.type == ELK_REGISTER_TYPE_UQ) && + (inst->src[0].type == ELK_REGISTER_TYPE_Q || + inst->src[0].type == ELK_REGISTER_TYPE_UQ) && + (inst->src[1].type == ELK_REGISTER_TYPE_Q || + inst->src[1].type == ELK_REGISTER_TYPE_UQ)) { lower_mul_qword_inst(inst, block); inst->remove(block); progress = true; } else if (!inst->dst.is_accumulator() && - (inst->dst.type == BRW_REGISTER_TYPE_D || - inst->dst.type == BRW_REGISTER_TYPE_UD) && + (inst->dst.type == ELK_REGISTER_TYPE_D || + inst->dst.type == ELK_REGISTER_TYPE_UD) && (!devinfo->has_integer_dword_mul || devinfo->verx10 >= 125)) { lower_mul_dword_inst(inst, block); inst->remove(block); progress = true; } - } else if (inst->opcode == SHADER_OPCODE_MULH) { + } else if (inst->opcode == ELK_SHADER_OPCODE_MULH) { lower_mulh_inst(inst, block); inst->remove(block); progress = true; @@ -4244,23 +4244,23 @@ fs_visitor::lower_integer_multiplication() } bool -fs_visitor::lower_minmax() +elk_fs_visitor::lower_minmax() { assert(devinfo->ver < 6); bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { const fs_builder ibld(this, block, inst); - if (inst->opcode == BRW_OPCODE_SEL && - inst->predicate == BRW_PREDICATE_NONE) { + if (inst->opcode == ELK_OPCODE_SEL && + inst->predicate == ELK_PREDICATE_NONE) { /* If src1 is an immediate value that is not NaN, then it can't be * NaN. In that case, emit CMP because it is much better for cmod * propagation. Likewise if src1 is not float. Gfx4 and Gfx5 don't * support HF or DF, so it is not necessary to check for those. */ - if (inst->src[1].type != BRW_REGISTER_TYPE_F || + if (inst->src[1].type != ELK_REGISTER_TYPE_F || (inst->src[1].file == IMM && !isnan(inst->src[1].f))) { ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1], inst->conditional_mod); @@ -4268,8 +4268,8 @@ fs_visitor::lower_minmax() ibld.CMPN(ibld.null_reg_d(), inst->src[0], inst->src[1], inst->conditional_mod); } - inst->predicate = BRW_PREDICATE_NORMAL; - inst->conditional_mod = BRW_CONDITIONAL_NONE; + inst->predicate = ELK_PREDICATE_NORMAL; + inst->conditional_mod = ELK_CONDITIONAL_NONE; progress = true; } @@ -4282,15 +4282,15 @@ fs_visitor::lower_minmax() } bool -fs_visitor::lower_sub_sat() +elk_fs_visitor::lower_sub_sat() { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { const fs_builder ibld(this, block, inst); - if (inst->opcode == SHADER_OPCODE_USUB_SAT || - inst->opcode == SHADER_OPCODE_ISUB_SAT) { + if (inst->opcode == ELK_SHADER_OPCODE_USUB_SAT || + inst->opcode == ELK_SHADER_OPCODE_ISUB_SAT) { /* The fundamental problem is the hardware performs source negation * at the bit width of the source. If the source is 0x80000000D, the * negation is 0x80000000D. As a result, subtractSaturate(0, @@ -4318,24 +4318,24 @@ fs_visitor::lower_sub_sat() * same situations as #1 above. It is further limited by only * allowing UD sources. */ - if (inst->exec_size == 8 && inst->src[0].type != BRW_REGISTER_TYPE_Q && - inst->src[0].type != BRW_REGISTER_TYPE_UQ) { - fs_reg acc(ARF, BRW_ARF_ACCUMULATOR, inst->src[1].type); + if (inst->exec_size == 8 && inst->src[0].type != ELK_REGISTER_TYPE_Q && + inst->src[0].type != ELK_REGISTER_TYPE_UQ) { + elk_fs_reg acc(ARF, ELK_ARF_ACCUMULATOR, inst->src[1].type); ibld.MOV(acc, inst->src[1]); - fs_inst *add = ibld.ADD(inst->dst, acc, inst->src[0]); + elk_fs_inst *add = ibld.ADD(inst->dst, acc, inst->src[0]); add->saturate = true; add->src[0].negate = true; - } else if (inst->opcode == SHADER_OPCODE_ISUB_SAT) { + } else if (inst->opcode == ELK_SHADER_OPCODE_ISUB_SAT) { /* tmp = src1 >> 1; * dst = add.sat(add.sat(src0, -tmp), -(src1 - tmp)); */ - fs_reg tmp1 = ibld.vgrf(inst->src[0].type); - fs_reg tmp2 = ibld.vgrf(inst->src[0].type); - fs_reg tmp3 = ibld.vgrf(inst->src[0].type); - fs_inst *add; + elk_fs_reg tmp1 = ibld.vgrf(inst->src[0].type); + elk_fs_reg tmp2 = ibld.vgrf(inst->src[0].type); + elk_fs_reg tmp3 = ibld.vgrf(inst->src[0].type); + elk_fs_inst *add; - ibld.SHR(tmp1, inst->src[1], brw_imm_d(1)); + ibld.SHR(tmp1, inst->src[1], elk_imm_d(1)); add = ibld.ADD(tmp2, inst->src[1], tmp1); add->src[1].negate = true; @@ -4350,13 +4350,13 @@ fs_visitor::lower_sub_sat() } else { /* a > b ? a - b : 0 */ ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1], - BRW_CONDITIONAL_G); + ELK_CONDITIONAL_G); - fs_inst *add = ibld.ADD(inst->dst, inst->src[0], inst->src[1]); + elk_fs_inst *add = ibld.ADD(inst->dst, inst->src[0], inst->src[1]); add->src[1].negate = !add->src[1].negate; - ibld.SEL(inst->dst, inst->dst, brw_imm_ud(0)) - ->predicate = BRW_PREDICATE_NORMAL; + ibld.SEL(inst->dst, inst->dst, elk_imm_ud(0)) + ->predicate = ELK_PREDICATE_NORMAL; } inst->remove(block); @@ -4376,49 +4376,49 @@ fs_visitor::lower_sub_sat() * thread payload, \p bld is required to have a dispatch_width() not greater * than 16 for fragment shaders. */ -fs_reg -brw_sample_mask_reg(const fs_builder &bld) +elk_fs_reg +elk_sample_mask_reg(const fs_builder &bld) { - const fs_visitor &s = *bld.shader; + const elk_fs_visitor &s = *bld.shader; if (s.stage != MESA_SHADER_FRAGMENT) { - return brw_imm_ud(0xffffffff); - } else if (brw_wm_prog_data(s.stage_prog_data)->uses_kill) { + return elk_imm_ud(0xffffffff); + } else if (elk_wm_prog_data(s.stage_prog_data)->uses_kill) { assert(bld.dispatch_width() <= 16); - return brw_flag_subreg(sample_mask_flag_subreg(s) + bld.group() / 16); + return elk_flag_subreg(sample_mask_flag_subreg(s) + bld.group() / 16); } else { assert(s.devinfo->ver >= 6 && bld.dispatch_width() <= 16); assert(s.devinfo->ver < 20); - return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7), - BRW_REGISTER_TYPE_UW); + return retype(elk_vec1_grf((bld.group() >= 16 ? 2 : 1), 7), + ELK_REGISTER_TYPE_UW); } } uint32_t -brw_fb_write_msg_control(const fs_inst *inst, - const struct brw_wm_prog_data *prog_data) +elk_fb_write_msg_control(const elk_fs_inst *inst, + const struct elk_wm_prog_data *prog_data) { uint32_t mctl; - if (inst->opcode == FS_OPCODE_REP_FB_WRITE) { + if (inst->opcode == ELK_FS_OPCODE_REP_FB_WRITE) { assert(inst->group == 0 && inst->exec_size == 16); - mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED; + mctl = ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED; } else if (prog_data->dual_src_blend) { assert(inst->exec_size == 8); if (inst->group % 16 == 0) - mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01; + mctl = ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01; else if (inst->group % 16 == 8) - mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23; + mctl = ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23; else unreachable("Invalid dual-source FB write instruction group"); } else { assert(inst->group == 0 || (inst->group == 16 && inst->exec_size == 16)); if (inst->exec_size == 16) - mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE; + mctl = ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE; else if (inst->exec_size == 8) - mctl = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; + mctl = ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; else unreachable("Invalid FB write execution size"); } @@ -4430,56 +4430,56 @@ brw_fb_write_msg_control(const fs_inst *inst, * Predicate the specified instruction on the sample mask. */ void -brw_emit_predicate_on_sample_mask(const fs_builder &bld, fs_inst *inst) +elk_emit_predicate_on_sample_mask(const fs_builder &bld, elk_fs_inst *inst) { assert(bld.shader->stage == MESA_SHADER_FRAGMENT && bld.group() == inst->group && bld.dispatch_width() == inst->exec_size); - const fs_visitor &s = *bld.shader; - const fs_reg sample_mask = brw_sample_mask_reg(bld); + const elk_fs_visitor &s = *bld.shader; + const elk_fs_reg sample_mask = elk_sample_mask_reg(bld); const unsigned subreg = sample_mask_flag_subreg(s); - if (brw_wm_prog_data(s.stage_prog_data)->uses_kill) { + if (elk_wm_prog_data(s.stage_prog_data)->uses_kill) { assert(sample_mask.file == ARF && - sample_mask.nr == brw_flag_subreg(subreg).nr && - sample_mask.subnr == brw_flag_subreg( + sample_mask.nr == elk_flag_subreg(subreg).nr && + sample_mask.subnr == elk_flag_subreg( subreg + inst->group / 16).subnr); } else { bld.group(1, 0).exec_all() - .MOV(brw_flag_subreg(subreg + inst->group / 16), sample_mask); + .MOV(elk_flag_subreg(subreg + inst->group / 16), sample_mask); } if (inst->predicate) { - assert(inst->predicate == BRW_PREDICATE_NORMAL); + assert(inst->predicate == ELK_PREDICATE_NORMAL); assert(!inst->predicate_inverse); assert(inst->flag_subreg == 0); assert(s.devinfo->ver < 20); /* Combine the sample mask with the existing predicate by using a * vertical predication mode. */ - inst->predicate = BRW_PREDICATE_ALIGN1_ALLV; + inst->predicate = ELK_PREDICATE_ALIGN1_ALLV; } else { inst->flag_subreg = subreg; - inst->predicate = BRW_PREDICATE_NORMAL; + inst->predicate = ELK_PREDICATE_NORMAL; inst->predicate_inverse = false; } } static bool -is_mixed_float_with_fp32_dst(const fs_inst *inst) +is_mixed_float_with_fp32_dst(const elk_fs_inst *inst) { /* This opcode sometimes uses :W type on the source even if the operand is * a :HF, because in gfx7 there is no support for :HF, and thus it uses :W. */ - if (inst->opcode == BRW_OPCODE_F16TO32) + if (inst->opcode == ELK_OPCODE_F16TO32) return true; - if (inst->dst.type != BRW_REGISTER_TYPE_F) + if (inst->dst.type != ELK_REGISTER_TYPE_F) return false; for (int i = 0; i < inst->sources; i++) { - if (inst->src[i].type == BRW_REGISTER_TYPE_HF) + if (inst->src[i].type == ELK_REGISTER_TYPE_HF) return true; } @@ -4487,22 +4487,22 @@ is_mixed_float_with_fp32_dst(const fs_inst *inst) } static bool -is_mixed_float_with_packed_fp16_dst(const fs_inst *inst) +is_mixed_float_with_packed_fp16_dst(const elk_fs_inst *inst) { /* This opcode sometimes uses :W type on the destination even if the * destination is a :HF, because in gfx7 there is no support for :HF, and * thus it uses :W. */ - if (inst->opcode == BRW_OPCODE_F32TO16 && + if (inst->opcode == ELK_OPCODE_F32TO16 && inst->dst.stride == 1) return true; - if (inst->dst.type != BRW_REGISTER_TYPE_HF || + if (inst->dst.type != ELK_REGISTER_TYPE_HF || inst->dst.stride != 1) return false; for (int i = 0; i < inst->sources; i++) { - if (inst->src[i].type == BRW_REGISTER_TYPE_F) + if (inst->src[i].type == ELK_REGISTER_TYPE_F) return true; } @@ -4524,10 +4524,10 @@ is_mixed_float_with_packed_fp16_dst(const fs_inst *inst) * excessively restrictive. */ static unsigned -get_fpu_lowered_simd_width(const fs_visitor *shader, - const fs_inst *inst) +get_fpu_lowered_simd_width(const elk_fs_visitor *shader, + const elk_fs_inst *inst) { - const struct brw_compiler *compiler = shader->compiler; + const struct elk_compiler *compiler = shader->compiler; const struct intel_device_info *devinfo = compiler->devinfo; /* Maximum execution size representable in the instruction controls. */ @@ -4654,7 +4654,7 @@ get_fpu_lowered_simd_width(const fs_visitor *shader, * "Ternary instruction with condition modifiers must not use SIMD32." */ if (inst->conditional_mod && (devinfo->ver < 8 || - (inst->is_3src(compiler) && devinfo->ver < 12))) + (inst->elk_is_3src(compiler) && devinfo->ver < 12))) max_width = MIN2(max_width, 16); /* From the IVB PRMs (applies to other devices that don't have the @@ -4662,7 +4662,7 @@ get_fpu_lowered_simd_width(const fs_visitor *shader, * "In Align16 access mode, SIMD16 is not allowed for DW operations and * SIMD8 is not allowed for DF operations." */ - if (inst->is_3src(compiler) && !devinfo->supports_simd16_3src) + if (inst->elk_is_3src(compiler) && !devinfo->supports_simd16_3src) max_width = MIN2(max_width, inst->exec_size / reg_count); /* Pre-Gfx8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is @@ -4754,13 +4754,13 @@ get_fpu_lowered_simd_width(const fs_visitor *shader, */ static unsigned get_sampler_lowered_simd_width(const struct intel_device_info *devinfo, - const fs_inst *inst) + const elk_fs_inst *inst) { /* If we have a min_lod parameter on anything other than a simple sample * message, it will push it over 5 arguments and we have to fall back to * SIMD8. */ - if (inst->opcode != SHADER_OPCODE_TEX && + if (inst->opcode != ELK_SHADER_OPCODE_TEX && inst->components_read(TEX_LOGICAL_SRC_MIN_LOD)) return devinfo->ver < 20 ? 8 : 16; @@ -4773,16 +4773,16 @@ get_sampler_lowered_simd_width(const struct intel_device_info *devinfo, const unsigned req_coord_components = (devinfo->ver >= 7 || !inst->components_read(TEX_LOGICAL_SRC_COORDINATE)) ? 0 : - (devinfo->ver >= 5 && inst->opcode != SHADER_OPCODE_TXF_LOGICAL && - inst->opcode != SHADER_OPCODE_TXF_CMS_LOGICAL) ? 4 : + (devinfo->ver >= 5 && inst->opcode != ELK_SHADER_OPCODE_TXF_LOGICAL && + inst->opcode != ELK_SHADER_OPCODE_TXF_CMS_LOGICAL) ? 4 : 3; /* On Gfx9+ the LOD argument is for free if we're able to use the LZ * variant of the TXL or TXF message. */ const bool implicit_lod = devinfo->ver >= 9 && - (inst->opcode == SHADER_OPCODE_TXL || - inst->opcode == SHADER_OPCODE_TXF) && + (inst->opcode == ELK_SHADER_OPCODE_TXL || + inst->opcode == ELK_SHADER_OPCODE_TXF) && inst->src[TEX_LOGICAL_SRC_LOD].is_zero(); /* Calculate the total number of argument components that need to be passed @@ -4795,7 +4795,7 @@ get_sampler_lowered_simd_width(const struct intel_device_info *devinfo, (implicit_lod ? 0 : inst->components_read(TEX_LOGICAL_SRC_LOD)) + inst->components_read(TEX_LOGICAL_SRC_LOD2) + inst->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX) + - (inst->opcode == SHADER_OPCODE_TG4_OFFSET_LOGICAL ? + (inst->opcode == ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL ? inst->components_read(TEX_LOGICAL_SRC_TG4_OFFSET) : 0) + inst->components_read(TEX_LOGICAL_SRC_MCS); @@ -4812,57 +4812,57 @@ get_sampler_lowered_simd_width(const struct intel_device_info *devinfo, /** * Get the closest native SIMD width supported by the hardware for instruction * \p inst. The instruction will be left untouched by - * fs_visitor::lower_simd_width() if the returned value is equal to the + * elk_fs_visitor::lower_simd_width() if the returned value is equal to the * original execution size. */ static unsigned -get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) +get_lowered_simd_width(const elk_fs_visitor *shader, const elk_fs_inst *inst) { - const struct brw_compiler *compiler = shader->compiler; + const struct elk_compiler *compiler = shader->compiler; const struct intel_device_info *devinfo = compiler->devinfo; switch (inst->opcode) { - case BRW_OPCODE_DP4A: - case BRW_OPCODE_MOV: - case BRW_OPCODE_SEL: - case BRW_OPCODE_NOT: - case BRW_OPCODE_AND: - case BRW_OPCODE_OR: - case BRW_OPCODE_XOR: - case BRW_OPCODE_SHR: - case BRW_OPCODE_SHL: - case BRW_OPCODE_ASR: - case BRW_OPCODE_ROR: - case BRW_OPCODE_ROL: - case BRW_OPCODE_CMPN: - case BRW_OPCODE_CSEL: - case BRW_OPCODE_F32TO16: - case BRW_OPCODE_F16TO32: - case BRW_OPCODE_BFREV: - case BRW_OPCODE_BFE: - case BRW_OPCODE_ADD: - case BRW_OPCODE_MUL: - case BRW_OPCODE_AVG: - case BRW_OPCODE_FRC: - case BRW_OPCODE_RNDU: - case BRW_OPCODE_RNDD: - case BRW_OPCODE_RNDE: - case BRW_OPCODE_RNDZ: - case BRW_OPCODE_LZD: - case BRW_OPCODE_FBH: - case BRW_OPCODE_FBL: - case BRW_OPCODE_CBIT: - case BRW_OPCODE_SAD2: - case BRW_OPCODE_MAD: - case BRW_OPCODE_LRP: - case BRW_OPCODE_ADD3: - case FS_OPCODE_PACK: - case SHADER_OPCODE_SEL_EXEC: - case SHADER_OPCODE_CLUSTER_BROADCAST: - case SHADER_OPCODE_MOV_RELOC_IMM: + case ELK_OPCODE_DP4A: + case ELK_OPCODE_MOV: + case ELK_OPCODE_SEL: + case ELK_OPCODE_NOT: + case ELK_OPCODE_AND: + case ELK_OPCODE_OR: + case ELK_OPCODE_XOR: + case ELK_OPCODE_SHR: + case ELK_OPCODE_SHL: + case ELK_OPCODE_ASR: + case ELK_OPCODE_ROR: + case ELK_OPCODE_ROL: + case ELK_OPCODE_CMPN: + case ELK_OPCODE_CSEL: + case ELK_OPCODE_F32TO16: + case ELK_OPCODE_F16TO32: + case ELK_OPCODE_BFREV: + case ELK_OPCODE_BFE: + case ELK_OPCODE_ADD: + case ELK_OPCODE_MUL: + case ELK_OPCODE_AVG: + case ELK_OPCODE_FRC: + case ELK_OPCODE_RNDU: + case ELK_OPCODE_RNDD: + case ELK_OPCODE_RNDE: + case ELK_OPCODE_RNDZ: + case ELK_OPCODE_LZD: + case ELK_OPCODE_FBH: + case ELK_OPCODE_FBL: + case ELK_OPCODE_CBIT: + case ELK_OPCODE_SAD2: + case ELK_OPCODE_MAD: + case ELK_OPCODE_LRP: + case ELK_OPCODE_ADD3: + case ELK_FS_OPCODE_PACK: + case ELK_SHADER_OPCODE_SEL_EXEC: + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: + case ELK_SHADER_OPCODE_MOV_RELOC_IMM: return get_fpu_lowered_simd_width(shader, inst); - case BRW_OPCODE_CMP: { + case ELK_OPCODE_CMP: { /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that * when the destination is a GRF the dependency-clear bit on the flag * register is cleared early. @@ -4878,8 +4878,8 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) !inst->dst.is_null() ? 8 : ~0); return MIN2(max_width, get_fpu_lowered_simd_width(shader, inst)); } - case BRW_OPCODE_BFI1: - case BRW_OPCODE_BFI2: + case ELK_OPCODE_BFI1: + case ELK_OPCODE_BFI2: /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we * should * "Force BFI instructions to be executed always in SIMD8." @@ -4887,56 +4887,56 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) return MIN2(devinfo->platform == INTEL_PLATFORM_HSW ? 8 : ~0u, get_fpu_lowered_simd_width(shader, inst)); - case BRW_OPCODE_IF: + case ELK_OPCODE_IF: assert(inst->src[0].file == BAD_FILE || inst->exec_size <= 16); return inst->exec_size; - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: { + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: { /* Unary extended math instructions are limited to SIMD8 on Gfx4 and * Gfx6. Extended Math Function is limited to SIMD8 with half-float. */ if (devinfo->ver == 6 || devinfo->verx10 == 40) return MIN2(8, inst->exec_size); - if (inst->dst.type == BRW_REGISTER_TYPE_HF) + if (inst->dst.type == ELK_REGISTER_TYPE_HF) return MIN2(8, inst->exec_size); return MIN2(16, inst->exec_size); } - case SHADER_OPCODE_POW: { + case ELK_SHADER_OPCODE_POW: { /* SIMD16 is only allowed on Gfx7+. Extended Math Function is limited * to SIMD8 with half-float */ if (devinfo->ver < 7) return MIN2(8, inst->exec_size); - if (inst->dst.type == BRW_REGISTER_TYPE_HF) + if (inst->dst.type == ELK_REGISTER_TYPE_HF) return MIN2(8, inst->exec_size); return MIN2(16, inst->exec_size); } - case SHADER_OPCODE_USUB_SAT: - case SHADER_OPCODE_ISUB_SAT: + case ELK_SHADER_OPCODE_USUB_SAT: + case ELK_SHADER_OPCODE_ISUB_SAT: return get_fpu_lowered_simd_width(shader, inst); - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: /* Integer division is limited to SIMD8 on all generations. */ return MIN2(8, inst->exec_size); - case FS_OPCODE_LINTERP: - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: - case FS_OPCODE_PACK_HALF_2x16_SPLIT: - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_FS_OPCODE_LINTERP: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: return MIN2(16, inst->exec_size); - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch * message used to implement varying pull constant loads, so expand it * to SIMD16. An alternative with longer message payload length but @@ -4945,10 +4945,10 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) */ return (devinfo->ver == 4 ? 16 : MIN2(16, inst->exec_size)); - case FS_OPCODE_DDX_COARSE: - case FS_OPCODE_DDX_FINE: - case FS_OPCODE_DDY_COARSE: - case FS_OPCODE_DDY_FINE: + case ELK_FS_OPCODE_DDX_COARSE: + case ELK_FS_OPCODE_DDX_FINE: + case ELK_FS_OPCODE_DDY_COARSE: + case ELK_FS_OPCODE_DDY_FINE: /* The implementation of this virtual opcode may require emitting * compressed Align16 instructions, which are severely limited on some * generations. @@ -4977,7 +4977,7 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) (devinfo->verx10 == 70) ? MIN2(8, inst->exec_size) : MIN2(16, inst->exec_size)); - case SHADER_OPCODE_MULH: + case ELK_SHADER_OPCODE_MULH: /* MULH is lowered to the MUL/MACH sequence using the accumulator, which * is 8-wide on Gfx7+. */ @@ -4985,7 +4985,7 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) devinfo->ver >= 7 ? 8 : get_fpu_lowered_simd_width(shader, inst)); - case FS_OPCODE_FB_WRITE_LOGICAL: + case ELK_FS_OPCODE_FB_WRITE_LOGICAL: /* Gfx6 doesn't support SIMD16 depth writes but we cannot handle them * here. */ @@ -4996,34 +4996,34 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) return (inst->src[FB_WRITE_LOGICAL_SRC_COLOR1].file != BAD_FILE ? 8 : MIN2(16, inst->exec_size)); - case FS_OPCODE_FB_READ_LOGICAL: + case ELK_FS_OPCODE_FB_READ_LOGICAL: return MIN2(16, inst->exec_size); - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXF_CMS_LOGICAL: - case SHADER_OPCODE_TXF_UMS_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: + case ELK_SHADER_OPCODE_TEX_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL: + case ELK_SHADER_OPCODE_LOD_LOGICAL: + case ELK_SHADER_OPCODE_TG4_LOGICAL: + case ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL: + case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL: return get_sampler_lowered_simd_width(devinfo, inst); /* On gfx12 parameters are fixed to 16-bit values and therefore they all * always fit regardless of the execution size. */ - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: return MIN2(16, inst->exec_size); - case SHADER_OPCODE_TXD_LOGICAL: + case ELK_SHADER_OPCODE_TXD_LOGICAL: /* TXD is unsupported in SIMD16 mode previous to Xe2. SIMD32 is still * unsuppported on Xe2. */ return devinfo->ver < 20 ? 8 : 16; - case SHADER_OPCODE_TXL_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: + case ELK_SHADER_OPCODE_TXL_LOGICAL: + case ELK_FS_OPCODE_TXB_LOGICAL: /* Only one execution size is representable pre-ILK depending on whether * the shadow reference argument is present. */ @@ -5032,8 +5032,8 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) else return get_sampler_lowered_simd_width(devinfo, inst); - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_LOGICAL: + case ELK_SHADER_OPCODE_TXS_LOGICAL: /* Gfx4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD * messages. Use SIMD16 instead. */ @@ -5042,48 +5042,48 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) else return get_sampler_lowered_simd_width(devinfo, inst); - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: return 8; - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: return MIN2(16, inst->exec_size); - case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: - case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: return devinfo->ver <= 8 ? 8 : MIN2(16, inst->exec_size); - case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: - case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: - case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: assert(inst->exec_size <= 16); return inst->exec_size; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: return devinfo->has_lsc ? MIN2(16, inst->exec_size) : 8; - case SHADER_OPCODE_URB_READ_LOGICAL: - case SHADER_OPCODE_URB_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_URB_READ_LOGICAL: + case ELK_SHADER_OPCODE_URB_WRITE_LOGICAL: return MIN2(devinfo->ver < 20 ? 8 : 16, inst->exec_size); - case SHADER_OPCODE_QUAD_SWIZZLE: { + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: { const unsigned swiz = inst->src[1].ud; return (is_uniform(inst->src[0]) ? get_fpu_lowered_simd_width(shader, inst) : devinfo->ver < 11 && type_sz(inst->src[0].type) == 4 ? 8 : - swiz == BRW_SWIZZLE_XYXY || swiz == BRW_SWIZZLE_ZWZW ? 4 : + swiz == ELK_SWIZZLE_XYXY || swiz == ELK_SWIZZLE_ZWZW ? 4 : get_fpu_lowered_simd_width(shader, inst)); } - case SHADER_OPCODE_MOV_INDIRECT: { + case ELK_SHADER_OPCODE_MOV_INDIRECT: { /* From IVB and HSW PRMs: * * "2.When the destination requires two registers and the sources are @@ -5100,7 +5100,7 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) inst->exec_size); } - case SHADER_OPCODE_LOAD_PAYLOAD: { + case ELK_SHADER_OPCODE_LOAD_PAYLOAD: { const unsigned reg_count = DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE); @@ -5130,7 +5130,7 @@ get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) * of the lowered instruction. */ static inline bool -needs_src_copy(const fs_builder &lbld, const fs_inst *inst, unsigned i) +needs_src_copy(const fs_builder &lbld, const elk_fs_inst *inst, unsigned i) { return !(is_periodic(inst->src[i], lbld.dispatch_width()) || (inst->components_read(i) == 1 && @@ -5144,13 +5144,13 @@ needs_src_copy(const fs_builder &lbld, const fs_inst *inst, unsigned i) * lbld.group() from the i-th source region of instruction \p inst and return * it as result in packed form. */ -static fs_reg -emit_unzip(const fs_builder &lbld, fs_inst *inst, unsigned i) +static elk_fs_reg +emit_unzip(const fs_builder &lbld, elk_fs_inst *inst, unsigned i) { assert(lbld.group() >= inst->group); /* Specified channel group from the source region. */ - const fs_reg src = horiz_offset(inst->src[i], lbld.group() - inst->group); + const elk_fs_reg src = horiz_offset(inst->src[i], lbld.group() - inst->group); if (needs_src_copy(lbld, inst, i)) { /* Builder of the right width to perform the copy avoiding uninitialized @@ -5159,7 +5159,7 @@ emit_unzip(const fs_builder &lbld, fs_inst *inst, unsigned i) */ const fs_builder cbld = lbld.group(MIN2(lbld.dispatch_width(), inst->exec_size), 0); - const fs_reg tmp = lbld.vgrf(inst->src[i].type, inst->components_read(i)); + const elk_fs_reg tmp = lbld.vgrf(inst->src[i].type, inst->components_read(i)); for (unsigned k = 0; k < inst->components_read(i); ++k) cbld.MOV(offset(tmp, lbld, k), offset(src, inst->exec_size, k)); @@ -5187,7 +5187,7 @@ emit_unzip(const fs_builder &lbld, fs_inst *inst, unsigned i) * destination region. */ static inline bool -needs_dst_copy(const fs_builder &lbld, const fs_inst *inst) +needs_dst_copy(const fs_builder &lbld, const elk_fs_inst *inst) { if (inst->dst.is_null()) return false; @@ -5236,9 +5236,9 @@ needs_dst_copy(const fs_builder &lbld, const fs_inst *inst) * inserted using \p lbld_before and any copy instructions required for * zipping up the destination of \p inst will be inserted using \p lbld_after. */ -static fs_reg +static elk_fs_reg emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after, - fs_inst *inst) + elk_fs_inst *inst) { assert(lbld_before.dispatch_width() == lbld_after.dispatch_width()); assert(lbld_before.group() == lbld_after.group()); @@ -5247,7 +5247,7 @@ emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after, const struct intel_device_info *devinfo = lbld_before.shader->devinfo; /* Specified channel group from the destination region. */ - const fs_reg dst = horiz_offset(inst->dst, lbld_after.group() - inst->group); + const elk_fs_reg dst = horiz_offset(inst->dst, lbld_after.group() - inst->group); if (!needs_dst_copy(lbld_after, inst)) { /* No need to allocate a temporary for the lowered instruction, just @@ -5262,7 +5262,7 @@ emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after, const unsigned dst_size = (inst->size_written - residency_size) / inst->dst.component_size(inst->exec_size); - const fs_reg tmp = lbld_after.vgrf(inst->dst.type, + const elk_fs_reg tmp = lbld_after.vgrf(inst->dst.type, dst_size + inst->has_sampler_residency()); if (inst->predicate) { @@ -5299,14 +5299,14 @@ emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after, * SIMD16 16 bit values. */ const fs_builder rbld = gbld_after.exec_all().group(1, 0); - fs_reg local_res_reg = component( + elk_fs_reg local_res_reg = component( retype(offset(tmp, lbld_before, dst_size), - BRW_REGISTER_TYPE_UW), 0); - fs_reg final_res_reg = + ELK_REGISTER_TYPE_UW), 0); + elk_fs_reg final_res_reg = retype(byte_offset(inst->dst, inst->size_written - residency_size + gbld_after.group() / 8), - BRW_REGISTER_TYPE_UW); + ELK_REGISTER_TYPE_UW); rbld.MOV(final_res_reg, local_res_reg); } @@ -5314,11 +5314,11 @@ emit_zip(const fs_builder &lbld_before, const fs_builder &lbld_after, } bool -fs_visitor::lower_simd_width() +elk_fs_visitor::lower_simd_width() { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { const unsigned lower_width = get_lowered_simd_width(this, inst); if (lower_width != inst->exec_size) { @@ -5398,7 +5398,7 @@ fs_visitor::lower_simd_width() * If the EOT flag was set throw it away except for the last * instruction to avoid killing the thread prematurely. */ - fs_inst split_inst = *inst; + elk_fs_inst split_inst = *inst; split_inst.exec_size = lower_width; split_inst.eot = inst->eot && i == int(n - 1); @@ -5448,7 +5448,7 @@ fs_visitor::lower_simd_width() * component layout. */ bool -fs_visitor::lower_barycentrics() +elk_fs_visitor::lower_barycentrics() { const bool has_interleaved_layout = devinfo->has_pln || (devinfo->ver >= 7 && devinfo->ver < 20); @@ -5457,7 +5457,7 @@ fs_visitor::lower_barycentrics() if (stage != MESA_SHADER_FRAGMENT || !has_interleaved_layout) return false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { if (inst->exec_size < 16) continue; @@ -5465,10 +5465,10 @@ fs_visitor::lower_barycentrics() const fs_builder ubld = ibld.exec_all().group(8, 0); switch (inst->opcode) { - case FS_OPCODE_LINTERP : { + case ELK_FS_OPCODE_LINTERP : { assert(inst->exec_size == 16); - const fs_reg tmp = ibld.vgrf(inst->src[0].type, 2); - fs_reg srcs[4]; + const elk_fs_reg tmp = ibld.vgrf(inst->src[0].type, 2); + elk_fs_reg srcs[4]; for (unsigned i = 0; i < ARRAY_SIZE(srcs); i++) srcs[i] = horiz_offset(offset(inst->src[0], ibld, i % 2), @@ -5480,15 +5480,15 @@ fs_visitor::lower_barycentrics() progress = true; break; } - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: { + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: { assert(inst->exec_size == 16); - const fs_reg tmp = ibld.vgrf(inst->dst.type, 2); + const elk_fs_reg tmp = ibld.vgrf(inst->dst.type, 2); for (unsigned i = 0; i < 2; i++) { for (unsigned g = 0; g < inst->exec_size / 8; g++) { - fs_inst *mov = ibld.at(block, inst->next).group(8, g) + elk_fs_inst *mov = ibld.at(block, inst->next).group(8, g) .MOV(horiz_offset(offset(inst->dst, ibld, i), 8 * g), offset(tmp, ubld, 2 * g + i)); @@ -5518,20 +5518,20 @@ fs_visitor::lower_barycentrics() * swizzles of the source, specified as \p swz0 and \p swz1. */ static bool -lower_derivative(fs_visitor *v, bblock_t *block, fs_inst *inst, +lower_derivative(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst, unsigned swz0, unsigned swz1) { const fs_builder ubld = fs_builder(v, block, inst).exec_all(); - const fs_reg tmp0 = ubld.vgrf(inst->src[0].type); - const fs_reg tmp1 = ubld.vgrf(inst->src[0].type); + const elk_fs_reg tmp0 = ubld.vgrf(inst->src[0].type); + const elk_fs_reg tmp1 = ubld.vgrf(inst->src[0].type); - ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp0, inst->src[0], brw_imm_ud(swz0)); - ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp1, inst->src[0], brw_imm_ud(swz1)); + ubld.emit(ELK_SHADER_OPCODE_QUAD_SWIZZLE, tmp0, inst->src[0], elk_imm_ud(swz0)); + ubld.emit(ELK_SHADER_OPCODE_QUAD_SWIZZLE, tmp1, inst->src[0], elk_imm_ud(swz1)); inst->resize_sources(2); inst->src[0] = negate(tmp0); inst->src[1] = tmp1; - inst->opcode = BRW_OPCODE_ADD; + inst->opcode = ELK_OPCODE_ADD; return true; } @@ -5541,29 +5541,29 @@ lower_derivative(fs_visitor *v, bblock_t *block, fs_inst *inst, * them efficiently (i.e. XeHP). */ bool -fs_visitor::lower_derivatives() +elk_fs_visitor::lower_derivatives() { bool progress = false; if (devinfo->verx10 < 125) return false; - foreach_block_and_inst(block, fs_inst, inst, cfg) { - if (inst->opcode == FS_OPCODE_DDX_COARSE) + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { + if (inst->opcode == ELK_FS_OPCODE_DDX_COARSE) progress |= lower_derivative(this, block, inst, - BRW_SWIZZLE_XXXX, BRW_SWIZZLE_YYYY); + ELK_SWIZZLE_XXXX, ELK_SWIZZLE_YYYY); - else if (inst->opcode == FS_OPCODE_DDX_FINE) + else if (inst->opcode == ELK_FS_OPCODE_DDX_FINE) progress |= lower_derivative(this, block, inst, - BRW_SWIZZLE_XXZZ, BRW_SWIZZLE_YYWW); + ELK_SWIZZLE_XXZZ, ELK_SWIZZLE_YYWW); - else if (inst->opcode == FS_OPCODE_DDY_COARSE) + else if (inst->opcode == ELK_FS_OPCODE_DDY_COARSE) progress |= lower_derivative(this, block, inst, - BRW_SWIZZLE_XXXX, BRW_SWIZZLE_ZZZZ); + ELK_SWIZZLE_XXXX, ELK_SWIZZLE_ZZZZ); - else if (inst->opcode == FS_OPCODE_DDY_FINE) + else if (inst->opcode == ELK_FS_OPCODE_DDY_FINE) progress |= lower_derivative(this, block, inst, - BRW_SWIZZLE_XYXY, BRW_SWIZZLE_ZWZW); + ELK_SWIZZLE_XYXY, ELK_SWIZZLE_ZWZW); } if (progress) @@ -5573,7 +5573,7 @@ fs_visitor::lower_derivatives() } bool -fs_visitor::lower_find_live_channel() +elk_fs_visitor::lower_find_live_channel() { bool progress = false; @@ -5581,18 +5581,18 @@ fs_visitor::lower_find_live_channel() return false; bool packed_dispatch = - brw_stage_has_packed_dispatch(devinfo, stage, max_polygons, + elk_stage_has_packed_dispatch(devinfo, stage, max_polygons, stage_prog_data); bool vmask = stage == MESA_SHADER_FRAGMENT && - brw_wm_prog_data(stage_prog_data)->uses_vmask; + elk_wm_prog_data(stage_prog_data)->uses_vmask; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { - if (inst->opcode != SHADER_OPCODE_FIND_LIVE_CHANNEL && - inst->opcode != SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL) + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { + if (inst->opcode != ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL && + inst->opcode != ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL) continue; - bool first = inst->opcode == SHADER_OPCODE_FIND_LIVE_CHANNEL; + bool first = inst->opcode == ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL; /* Getting the first active channel index is easy on Gfx8: Just find * the first bit set in the execution mask. The register exists on @@ -5600,7 +5600,7 @@ fs_visitor::lower_find_live_channel() * instruction has execution masking disabled, so it's kind of * useless there. */ - fs_reg exec_mask(retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD)); + elk_fs_reg exec_mask(retype(elk_mask_reg(0), ELK_REGISTER_TYPE_UD)); const fs_builder ibld(this, block, inst); if (!inst->is_partial_write()) @@ -5616,16 +5616,16 @@ fs_visitor::lower_find_live_channel() * will appear at the front of the mask. */ if (!(first && packed_dispatch)) { - fs_reg mask = ubld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg mask = ubld.vgrf(ELK_REGISTER_TYPE_UD); ubld.UNDEF(mask); - ubld.emit(SHADER_OPCODE_READ_SR_REG, mask, brw_imm_ud(vmask ? 3 : 2)); + ubld.emit(ELK_SHADER_OPCODE_READ_SR_REG, mask, elk_imm_ud(vmask ? 3 : 2)); /* Quarter control has the effect of magically shifting the value of * ce0 so you'll get the first/last active channel relative to the * specified quarter control as result. */ if (inst->group > 0) - ubld.SHR(mask, mask, brw_imm_ud(ALIGN(inst->group, 8))); + ubld.SHR(mask, mask, elk_imm_ud(ALIGN(inst->group, 8))); ubld.AND(mask, exec_mask, mask); exec_mask = mask; @@ -5634,10 +5634,10 @@ fs_visitor::lower_find_live_channel() if (first) { ubld.FBL(inst->dst, exec_mask); } else { - fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 1); + elk_fs_reg tmp = ubld.vgrf(ELK_REGISTER_TYPE_UD, 1); ubld.UNDEF(tmp); ubld.LZD(tmp, exec_mask); - ubld.ADD(inst->dst, negate(tmp), brw_imm_uw(31)); + ubld.ADD(inst->dst, negate(tmp), elk_imm_uw(31)); } inst->remove(block); @@ -5651,13 +5651,13 @@ fs_visitor::lower_find_live_channel() } void -fs_visitor::dump_instructions_to_file(FILE *file) const +elk_fs_visitor::dump_instructions_to_file(FILE *file) const { if (cfg) { const register_pressure &rp = regpressure_analysis.require(); unsigned ip = 0, max_pressure = 0; unsigned cf_count = 0; - foreach_block_and_inst(block, backend_instruction, inst, cfg) { + foreach_block_and_inst(block, elk_backend_instruction, inst, cfg) { if (inst->is_control_flow_end()) cf_count -= 1; @@ -5674,7 +5674,7 @@ fs_visitor::dump_instructions_to_file(FILE *file) const fprintf(file, "Maximum %3d registers live at once.\n", max_pressure); } else { int ip = 0; - foreach_in_list(backend_instruction, inst, &instructions) { + foreach_in_list(elk_backend_instruction, inst, &instructions) { fprintf(file, "%4d: ", ip++); dump_instruction(inst, file); } @@ -5682,9 +5682,9 @@ fs_visitor::dump_instructions_to_file(FILE *file) const } void -fs_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *file) const +elk_fs_visitor::dump_instruction_to_file(const elk_backend_instruction *be_inst, FILE *file) const { - const fs_inst *inst = (const fs_inst *)be_inst; + const elk_fs_inst *inst = (const elk_fs_inst *)be_inst; if (inst->predicate) { fprintf(file, "(%cf%d.%d) ", @@ -5693,16 +5693,16 @@ fs_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *f inst->flag_subreg % 2); } - fprintf(file, "%s", brw_instruction_name(&compiler->isa, inst->opcode)); + fprintf(file, "%s", elk_instruction_name(&compiler->isa, inst->opcode)); if (inst->saturate) fprintf(file, ".sat"); if (inst->conditional_mod) { - fprintf(file, "%s", conditional_modifier[inst->conditional_mod]); + fprintf(file, "%s", elk_conditional_modifier[inst->conditional_mod]); if (!inst->predicate && - (devinfo->ver < 5 || (inst->opcode != BRW_OPCODE_SEL && - inst->opcode != BRW_OPCODE_CSEL && - inst->opcode != BRW_OPCODE_IF && - inst->opcode != BRW_OPCODE_WHILE))) { + (devinfo->ver < 5 || (inst->opcode != ELK_OPCODE_SEL && + inst->opcode != ELK_OPCODE_CSEL && + inst->opcode != ELK_OPCODE_IF && + inst->opcode != ELK_OPCODE_WHILE))) { fprintf(file, ".f%d.%d", inst->flag_subreg / 2, inst->flag_subreg % 2); } @@ -5742,16 +5742,16 @@ fs_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *f break; case ARF: switch (inst->dst.nr) { - case BRW_ARF_NULL: + case ELK_ARF_NULL: fprintf(file, "null"); break; - case BRW_ARF_ADDRESS: + case ELK_ARF_ADDRESS: fprintf(file, "a0.%d", inst->dst.subnr); break; - case BRW_ARF_ACCUMULATOR: + case ELK_ARF_ACCUMULATOR: fprintf(file, "acc%d", inst->dst.subnr); break; - case BRW_ARF_FLAG: + case ELK_ARF_FLAG: fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr); break; default: @@ -5773,7 +5773,7 @@ fs_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *f if (inst->dst.stride != 1) fprintf(file, "<%u>", inst->dst.stride); - fprintf(file, ":%s, ", brw_reg_type_to_letters(inst->dst.type)); + fprintf(file, ":%s, ", elk_reg_type_to_letters(inst->dst.type)); for (int i = 0; i < inst->sources; i++) { if (inst->src[i].negate) @@ -5801,40 +5801,40 @@ fs_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *f break; case IMM: switch (inst->src[i].type) { - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: fprintf(file, "%-ghf", _mesa_half_to_float(inst->src[i].ud & 0xffff)); break; - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: fprintf(file, "%-gf", inst->src[i].f); break; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: fprintf(file, "%fdf", inst->src[i].df); break; - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_D: fprintf(file, "%dd", inst->src[i].d); break; - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_UD: fprintf(file, "%uu", inst->src[i].ud); break; - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_Q: fprintf(file, "%" PRId64 "q", inst->src[i].d64); break; - case BRW_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_UQ: fprintf(file, "%" PRIu64 "uq", inst->src[i].u64); break; - case BRW_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_VF: fprintf(file, "[%-gF, %-gF, %-gF, %-gF]", - brw_vf_to_float((inst->src[i].ud >> 0) & 0xff), - brw_vf_to_float((inst->src[i].ud >> 8) & 0xff), - brw_vf_to_float((inst->src[i].ud >> 16) & 0xff), - brw_vf_to_float((inst->src[i].ud >> 24) & 0xff)); + elk_vf_to_float((inst->src[i].ud >> 0) & 0xff), + elk_vf_to_float((inst->src[i].ud >> 8) & 0xff), + elk_vf_to_float((inst->src[i].ud >> 16) & 0xff), + elk_vf_to_float((inst->src[i].ud >> 24) & 0xff)); break; - case BRW_REGISTER_TYPE_V: - case BRW_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UV: fprintf(file, "%08x%s", inst->src[i].ud, - inst->src[i].type == BRW_REGISTER_TYPE_V ? "V" : "UV"); + inst->src[i].type == ELK_REGISTER_TYPE_V ? "V" : "UV"); break; default: fprintf(file, "???"); @@ -5843,16 +5843,16 @@ fs_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *f break; case ARF: switch (inst->src[i].nr) { - case BRW_ARF_NULL: + case ELK_ARF_NULL: fprintf(file, "null"); break; - case BRW_ARF_ADDRESS: + case ELK_ARF_ADDRESS: fprintf(file, "a0.%d", inst->src[i].subnr); break; - case BRW_ARF_ACCUMULATOR: + case ELK_ARF_ACCUMULATOR: fprintf(file, "acc%d", inst->src[i].subnr); break; - case BRW_ARF_FLAG: + case ELK_ARF_FLAG: fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr); break; default: @@ -5884,7 +5884,7 @@ fs_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *f if (stride != 1) fprintf(file, "<%u>", stride); - fprintf(file, ":%s", brw_reg_type_to_letters(inst->src[i].type)); + fprintf(file, ":%s", elk_reg_type_to_letters(inst->src[i].type)); } if (i < inst->sources - 1 && inst->src[i + 1].file != BAD_FILE) @@ -5902,7 +5902,7 @@ fs_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *f fprintf(file, "\n"); } -elk::register_pressure::register_pressure(const fs_visitor *v) +elk::register_pressure::register_pressure(const elk_fs_visitor *v) { const fs_live_variables &live = v->live_analysis.require(); const unsigned num_instructions = v->cfg->num_blocks ? @@ -5934,19 +5934,19 @@ elk::register_pressure::~register_pressure() } void -fs_visitor::invalidate_analysis(elk::analysis_dependency_class c) +elk_fs_visitor::invalidate_analysis(elk::analysis_dependency_class c) { - backend_shader::invalidate_analysis(c); + elk_backend_shader::invalidate_analysis(c); live_analysis.invalidate(c); regpressure_analysis.invalidate(c); } void -fs_visitor::debug_optimizer(const nir_shader *nir, +elk_fs_visitor::debug_optimizer(const nir_shader *nir, const char *pass_name, int iteration, int pass_num) const { - if (!brw_should_print_shader(nir, DEBUG_OPTIMIZER)) + if (!elk_should_print_shader(nir, DEBUG_OPTIMIZER)) return; char *filename; @@ -5961,7 +5961,7 @@ fs_visitor::debug_optimizer(const nir_shader *nir, } void -fs_visitor::optimize() +elk_fs_visitor::optimize() { debug_optimizer(nir, "start", 0, 0); @@ -6012,11 +6012,11 @@ fs_visitor::optimize() OPT(opt_algebraic); OPT(opt_cse); OPT(opt_copy_propagation); - OPT(opt_predicated_break, this); + OPT(elk_opt_predicated_break, this); OPT(opt_cmod_propagation); OPT(dead_code_eliminate); OPT(opt_peephole_sel); - OPT(dead_control_flow_eliminate, this); + OPT(elk_dead_control_flow_eliminate, this); OPT(opt_saturate_propagation); OPT(register_coalesce); OPT(compute_to_mrf); @@ -6133,22 +6133,22 @@ fs_visitor::optimize() * just adds a new vgrf for the second payload and copies it over. */ bool -fs_visitor::fixup_sends_duplicate_payload() +elk_fs_visitor::fixup_sends_duplicate_payload() { bool progress = false; - foreach_block_and_inst_safe (block, fs_inst, inst, cfg) { - if (inst->opcode == SHADER_OPCODE_SEND && inst->ex_mlen > 0 && + foreach_block_and_inst_safe (block, elk_fs_inst, inst, cfg) { + if (inst->opcode == ELK_SHADER_OPCODE_SEND && inst->ex_mlen > 0 && regions_overlap(inst->src[2], inst->mlen * REG_SIZE, inst->src[3], inst->ex_mlen * REG_SIZE)) { - fs_reg tmp = fs_reg(VGRF, alloc.allocate(inst->ex_mlen), - BRW_REGISTER_TYPE_UD); + elk_fs_reg tmp = elk_fs_reg(VGRF, alloc.allocate(inst->ex_mlen), + ELK_REGISTER_TYPE_UD); /* Sadly, we've lost all notion of channels and bit sizes at this * point. Just WE_all it. */ const fs_builder ibld = fs_builder(this, block, inst).exec_all().group(16, 0); - fs_reg copy_src = retype(inst->src[3], BRW_REGISTER_TYPE_UD); - fs_reg copy_dst = tmp; + elk_fs_reg copy_src = retype(inst->src[3], ELK_REGISTER_TYPE_UD); + elk_fs_reg copy_dst = tmp; for (unsigned i = 0; i < inst->ex_mlen; i += 2) { if (inst->ex_mlen == i + 1) { /* Only one register left; do SIMD8 */ @@ -6175,13 +6175,13 @@ fs_visitor::fixup_sends_duplicate_payload() * ARF NULL is not allowed. Fix that up by allocating a temporary GRF. */ void -fs_visitor::fixup_3src_null_dest() +elk_fs_visitor::fixup_3src_null_dest() { bool progress = false; - foreach_block_and_inst_safe (block, fs_inst, inst, cfg) { - if (inst->is_3src(compiler) && inst->dst.is_null()) { - inst->dst = fs_reg(VGRF, alloc.allocate(dispatch_width / 8), + foreach_block_and_inst_safe (block, elk_fs_inst, inst, cfg) { + if (inst->elk_is_3src(compiler) && inst->dst.is_null()) { + inst->dst = elk_fs_reg(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type); progress = true; } @@ -6193,7 +6193,7 @@ fs_visitor::fixup_3src_null_dest() } static bool -needs_dummy_fence(const intel_device_info *devinfo, fs_inst *inst) +needs_dummy_fence(const intel_device_info *devinfo, elk_fs_inst *inst) { /* This workaround is about making sure that any instruction writing * through UGM has completed before we hit EOT. @@ -6204,8 +6204,8 @@ needs_dummy_fence(const intel_device_info *devinfo, fs_inst *inst) /* Any UGM, non-Scratch-surface Stores (not including Atomic) messages, * where the L1-cache override is NOT among {WB, WS, WT} */ - enum lsc_opcode opcode = lsc_msg_desc_opcode(devinfo, inst->desc); - if (lsc_opcode_is_store(opcode)) { + enum elk_lsc_opcode opcode = lsc_msg_desc_opcode(devinfo, inst->desc); + if (elk_lsc_opcode_is_store(opcode)) { switch (lsc_msg_desc_cache_ctrl(devinfo, inst->desc)) { case LSC_CACHE_STORE_L1STATE_L3MOCS: case LSC_CACHE_STORE_L1WB_L3WB: @@ -6221,7 +6221,7 @@ needs_dummy_fence(const intel_device_info *devinfo, fs_inst *inst) } /* Any UGM Atomic message WITHOUT return value */ - if (lsc_opcode_is_atomic(opcode) && inst->dst.file == BAD_FILE) + if (elk_lsc_opcode_is_atomic(opcode) && inst->dst.file == BAD_FILE) return true; return false; @@ -6233,12 +6233,12 @@ needs_dummy_fence(const intel_device_info *devinfo, fs_inst *inst) * Make sure this happens by introducing a dummy mov instruction. */ void -fs_visitor::emit_dummy_mov_instruction() +elk_fs_visitor::emit_dummy_mov_instruction() { if (!intel_needs_workaround(devinfo, 14015360517)) return; - struct backend_instruction *first_inst = + struct elk_backend_instruction *first_inst = cfg->first_block()->start(); /* We can skip the WA if first instruction is marked with @@ -6250,8 +6250,8 @@ fs_visitor::emit_dummy_mov_instruction() /* Insert dummy mov as first instruction. */ const fs_builder ubld = - fs_builder(this, cfg->first_block(), (fs_inst *)first_inst).exec_all().group(8, 0); - ubld.MOV(ubld.null_reg_ud(), brw_imm_ud(0u)); + fs_builder(this, cfg->first_block(), (elk_fs_inst *)first_inst).exec_all().group(8, 0); + ubld.MOV(ubld.null_reg_ud(), elk_imm_ud(0u)); invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES); } @@ -6265,7 +6265,7 @@ fs_visitor::emit_dummy_mov_instruction() * We probably need a better criteria in needs_dummy_fence(). */ void -fs_visitor::emit_dummy_memory_fence_before_eot() +elk_fs_visitor::emit_dummy_memory_fence_before_eot() { bool progress = false; bool has_ugm_write_or_atomic = false; @@ -6273,7 +6273,7 @@ fs_visitor::emit_dummy_memory_fence_before_eot() if (!intel_needs_workaround(devinfo, 22013689345)) return; - foreach_block_and_inst_safe (block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe (block, elk_fs_inst, inst, cfg) { if (!inst->eot) { if (needs_dummy_fence(devinfo, inst)) has_ugm_write_or_atomic = true; @@ -6286,15 +6286,15 @@ fs_visitor::emit_dummy_memory_fence_before_eot() const fs_builder ibld(this, block, inst); const fs_builder ubld = ibld.exec_all().group(1, 0); - fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_UD); - fs_inst *dummy_fence = ubld.emit(SHADER_OPCODE_MEMORY_FENCE, - dst, brw_vec8_grf(0, 0), - /* commit enable */ brw_imm_ud(1), - /* bti */ brw_imm_ud(0)); + elk_fs_reg dst = ubld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_inst *dummy_fence = ubld.emit(ELK_SHADER_OPCODE_MEMORY_FENCE, + dst, elk_vec8_grf(0, 0), + /* commit enable */ elk_imm_ud(1), + /* bti */ elk_imm_ud(0)); dummy_fence->sfid = GFX12_SFID_UGM; dummy_fence->desc = lsc_fence_msg_desc(devinfo, LSC_FENCE_TILE, LSC_FLUSH_TYPE_NONE_6, false); - ubld.emit(FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(), dst); + ubld.emit(ELK_FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(), dst); progress = true; /* TODO: remove this break if we ever have shader with multiple EOT. */ break; @@ -6310,14 +6310,14 @@ fs_visitor::emit_dummy_memory_fence_before_eot() * Find the first instruction in the program that might start a region of * divergent control flow due to a HALT jump. There is no * find_halt_control_flow_region_end(), the region of divergence extends until - * the only SHADER_OPCODE_HALT_TARGET in the program. + * the only ELK_SHADER_OPCODE_HALT_TARGET in the program. */ -static const fs_inst * -find_halt_control_flow_region_start(const fs_visitor *v) +static const elk_fs_inst * +find_halt_control_flow_region_start(const elk_fs_visitor *v) { - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { - if (inst->opcode == BRW_OPCODE_HALT || - inst->opcode == SHADER_OPCODE_HALT_TARGET) + foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) { + if (inst->opcode == ELK_OPCODE_HALT || + inst->opcode == ELK_SHADER_OPCODE_HALT_TARGET) return inst; } @@ -6337,15 +6337,15 @@ find_halt_control_flow_region_start(const fs_visitor *v) * all channels of the program are disabled. */ bool -fs_visitor::fixup_nomask_control_flow() +elk_fs_visitor::fixup_nomask_control_flow() { if (devinfo->ver != 12) return false; - const brw_predicate pred = dispatch_width > 16 ? BRW_PREDICATE_ALIGN1_ANY32H : - dispatch_width > 8 ? BRW_PREDICATE_ALIGN1_ANY16H : - BRW_PREDICATE_ALIGN1_ANY8H; - const fs_inst *halt_start = find_halt_control_flow_region_start(this); + const elk_predicate pred = dispatch_width > 16 ? ELK_PREDICATE_ALIGN1_ANY32H : + dispatch_width > 8 ? ELK_PREDICATE_ALIGN1_ANY16H : + ELK_PREDICATE_ALIGN1_ANY8H; + const elk_fs_inst *halt_start = find_halt_control_flow_region_start(this); unsigned depth = 0; bool progress = false; @@ -6359,14 +6359,14 @@ fs_visitor::fixup_nomask_control_flow() .flag_liveout[0]; STATIC_ASSERT(ARRAY_SIZE(live_vars.block_data[0].flag_liveout) == 1); - foreach_inst_in_block_reverse_safe(fs_inst, inst, block) { + foreach_inst_in_block_reverse_safe(elk_fs_inst, inst, block) { if (!inst->predicate && inst->exec_size >= 8) flag_liveout &= ~inst->flags_written(devinfo); switch (inst->opcode) { - case BRW_OPCODE_DO: - case BRW_OPCODE_IF: - /* Note that this doesn't handle BRW_OPCODE_HALT since only + case ELK_OPCODE_DO: + case ELK_OPCODE_IF: + /* Note that this doesn't handle ELK_OPCODE_HALT since only * the first one in the program closes the region of divergent * control flow due to any HALT instructions -- Instead this is * handled with the halt_start check below. @@ -6374,9 +6374,9 @@ fs_visitor::fixup_nomask_control_flow() depth--; break; - case BRW_OPCODE_WHILE: - case BRW_OPCODE_ENDIF: - case SHADER_OPCODE_HALT_TARGET: + case ELK_OPCODE_WHILE: + case ELK_OPCODE_ENDIF: + case ELK_SHADER_OPCODE_HALT_TARGET: depth++; break; @@ -6389,7 +6389,7 @@ fs_visitor::fixup_nomask_control_flow() * The main concern is NoMask SEND instructions where the message * descriptor or header depends on data generated by live * invocations of the shader (RESINFO and - * FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD with a dynamically + * ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD with a dynamically * computed surface index seem to be the only examples right now * where this could easily lead to GPU hangs). Unfortunately we * have no straightforward way to detect that currently, so just @@ -6410,22 +6410,22 @@ fs_visitor::fixup_nomask_control_flow() */ const fs_builder ubld = fs_builder(this, block, inst) .exec_all().group(dispatch_width, 0); - const fs_reg flag = retype(brw_flag_reg(0, 0), - BRW_REGISTER_TYPE_UD); + const elk_fs_reg flag = retype(elk_flag_reg(0, 0), + ELK_REGISTER_TYPE_UD); /* Due to the lack of flag register allocation we need to save * and restore the flag register if it's live. */ const bool save_flag = flag_liveout & flag_mask(flag, dispatch_width / 8); - const fs_reg tmp = ubld.group(8, 0).vgrf(flag.type); + const elk_fs_reg tmp = ubld.group(8, 0).vgrf(flag.type); if (save_flag) { ubld.group(8, 0).UNDEF(tmp); ubld.group(1, 0).MOV(tmp, flag); } - ubld.emit(FS_OPCODE_LOAD_LIVE_CHANNELS); + ubld.emit(ELK_FS_OPCODE_LOAD_LIVE_CHANNELS); set_predicate(pred, inst); inst->flag_subreg = 0; @@ -6453,29 +6453,29 @@ fs_visitor::fixup_nomask_control_flow() } uint32_t -fs_visitor::compute_max_register_pressure() +elk_fs_visitor::compute_max_register_pressure() { const register_pressure &rp = regpressure_analysis.require(); uint32_t ip = 0, max_pressure = 0; - foreach_block_and_inst(block, backend_instruction, inst, cfg) { + foreach_block_and_inst(block, elk_backend_instruction, inst, cfg) { max_pressure = MAX2(max_pressure, rp.regs_live_at_ip[ip]); ip++; } return max_pressure; } -static fs_inst ** -save_instruction_order(const struct cfg_t *cfg) +static elk_fs_inst ** +save_instruction_order(const struct elk_cfg_t *cfg) { /* Before we schedule anything, stash off the instruction order as an array - * of fs_inst *. This way, we can reset it between scheduling passes to + * of elk_fs_inst *. This way, we can reset it between scheduling passes to * prevent dependencies between the different scheduling modes. */ int num_insts = cfg->last_block()->end_ip + 1; - fs_inst **inst_arr = new fs_inst * [num_insts]; + elk_fs_inst **inst_arr = new elk_fs_inst * [num_insts]; int ip = 0; - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { assert(ip >= block->start_ip && ip <= block->end_ip); inst_arr[ip++] = inst; } @@ -6485,7 +6485,7 @@ save_instruction_order(const struct cfg_t *cfg) } static void -restore_instruction_order(struct cfg_t *cfg, fs_inst **inst_arr) +restore_instruction_order(struct elk_cfg_t *cfg, elk_fs_inst **inst_arr) { ASSERTED int num_insts = cfg->last_block()->end_ip + 1; @@ -6501,7 +6501,7 @@ restore_instruction_order(struct cfg_t *cfg, fs_inst **inst_arr) } void -fs_visitor::allocate_registers(bool allow_spilling) +elk_fs_visitor::allocate_registers(bool allow_spilling) { bool allocated; @@ -6533,14 +6533,14 @@ fs_visitor::allocate_registers(bool allow_spilling) bool spill_all = allow_spilling && INTEL_DEBUG(DEBUG_SPILL_FS); /* Before we schedule anything, stash off the instruction order as an array - * of fs_inst *. This way, we can reset it between scheduling passes to + * of elk_fs_inst *. This way, we can reset it between scheduling passes to * prevent dependencies between the different scheduling modes. */ - fs_inst **orig_order = save_instruction_order(cfg); - fs_inst **best_pressure_order = NULL; + elk_fs_inst **orig_order = save_instruction_order(cfg); + elk_fs_inst **best_pressure_order = NULL; void *scheduler_ctx = ralloc_context(NULL); - fs_instruction_scheduler *sched = prepare_scheduler(scheduler_ctx); + elk_fs_instruction_scheduler *sched = prepare_scheduler(scheduler_ctx); /* Try each scheduling heuristic to see if it can successfully register * allocate without spilling. They should be ordered by decreasing @@ -6607,7 +6607,7 @@ fs_visitor::allocate_registers(bool allow_spilling) fail("Failure to register allocate. Reduce number of " "live scalar values to avoid this."); } else if (spilled_any_registers) { - brw_shader_perf_log(compiler, log_data, + elk_shader_perf_log(compiler, log_data, "%s shader triggered register spilling. " "Try reducing the number of live scalar " "values to improve performance.\n", @@ -6634,7 +6634,7 @@ fs_visitor::allocate_registers(bool allow_spilling) * case of bindless shaders with return parts, this will also take the * max of all parts. */ - prog_data->total_scratch = MAX2(brw_get_scratch_size(last_scratch), + prog_data->total_scratch = MAX2(elk_get_scratch_size(last_scratch), prog_data->total_scratch); if (gl_shader_stage_is_compute(stage)) { @@ -6670,13 +6670,13 @@ fs_visitor::allocate_registers(bool allow_spilling) } bool -fs_visitor::run_vs() +elk_fs_visitor::run_vs() { assert(stage == MESA_SHADER_VERTEX); - payload_ = new vs_thread_payload(*this); + payload_ = new elk_vs_thread_payload(*this); - nir_to_brw(this); + nir_to_elk(this); if (failed) return false; @@ -6702,10 +6702,10 @@ fs_visitor::run_vs() } void -fs_visitor::set_tcs_invocation_id() +elk_fs_visitor::set_tcs_invocation_id() { - struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data); - struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base; + struct elk_tcs_prog_data *tcs_prog_data = elk_tcs_prog_data(prog_data); + struct elk_vue_prog_data *vue_prog_data = &tcs_prog_data->base; const fs_builder bld = fs_builder(this).at_end(); const unsigned instance_id_mask = @@ -6720,36 +6720,36 @@ fs_visitor::set_tcs_invocation_id() * * 22:16 on gfx11+ * * 23:17 otherwise */ - fs_reg t = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.AND(t, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)), - brw_imm_ud(instance_id_mask)); + elk_fs_reg t = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.AND(t, elk_fs_reg(retype(elk_vec1_grf(0, 2), ELK_REGISTER_TYPE_UD)), + elk_imm_ud(instance_id_mask)); - invocation_id = bld.vgrf(BRW_REGISTER_TYPE_UD); + invocation_id = bld.vgrf(ELK_REGISTER_TYPE_UD); if (vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH) { /* gl_InvocationID is just the thread number */ - bld.SHR(invocation_id, t, brw_imm_ud(instance_id_shift)); + bld.SHR(invocation_id, t, elk_imm_ud(instance_id_shift)); return; } assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH); - fs_reg channels_uw = bld.vgrf(BRW_REGISTER_TYPE_UW); - fs_reg channels_ud = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.MOV(channels_uw, fs_reg(brw_imm_uv(0x76543210))); + elk_fs_reg channels_uw = bld.vgrf(ELK_REGISTER_TYPE_UW); + elk_fs_reg channels_ud = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.MOV(channels_uw, elk_fs_reg(elk_imm_uv(0x76543210))); bld.MOV(channels_ud, channels_uw); if (tcs_prog_data->instances == 1) { invocation_id = channels_ud; } else { - fs_reg instance_times_8 = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.SHR(instance_times_8, t, brw_imm_ud(instance_id_shift - 3)); + elk_fs_reg instance_times_8 = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.SHR(instance_times_8, t, elk_imm_ud(instance_id_shift - 3)); bld.ADD(invocation_id, instance_times_8, channels_ud); } } void -fs_visitor::emit_tcs_thread_end() +elk_fs_visitor::emit_tcs_thread_end() { /* Try and tag the last URB write with EOT instead of emitting a whole * separate write just to finish the thread. There isn't guaranteed to @@ -6765,28 +6765,28 @@ fs_visitor::emit_tcs_thread_end() * algorithm to set it optimally). On other platforms, we simply write * zero to a reserved/MBZ patch header DWord which has no consequence. */ - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = tcs_payload().patch_urb_output; - srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(WRITEMASK_X << 16); - srcs[URB_LOGICAL_SRC_DATA] = brw_imm_ud(0); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(1); - fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, + srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = elk_imm_ud(WRITEMASK_X << 16); + srcs[URB_LOGICAL_SRC_DATA] = elk_imm_ud(0); + srcs[URB_LOGICAL_SRC_COMPONENTS] = elk_imm_ud(1); + elk_fs_inst *inst = bld.emit(ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->eot = true; } bool -fs_visitor::run_tcs() +elk_fs_visitor::run_tcs() { assert(stage == MESA_SHADER_TESS_CTRL); - struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data); + struct elk_vue_prog_data *vue_prog_data = elk_vue_prog_data(prog_data); const fs_builder bld = fs_builder(this).at_end(); assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH || vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH); - payload_ = new tcs_thread_payload(*this); + payload_ = new elk_tcs_thread_payload(*this); /* Initialize gl_InvocationID */ set_tcs_invocation_id(); @@ -6798,14 +6798,14 @@ fs_visitor::run_tcs() /* Fix the disptach mask */ if (fix_dispatch_mask) { bld.CMP(bld.null_reg_ud(), invocation_id, - brw_imm_ud(nir->info.tess.tcs_vertices_out), BRW_CONDITIONAL_L); - bld.IF(BRW_PREDICATE_NORMAL); + elk_imm_ud(nir->info.tess.tcs_vertices_out), ELK_CONDITIONAL_L); + bld.IF(ELK_PREDICATE_NORMAL); } - nir_to_brw(this); + nir_to_elk(this); if (fix_dispatch_mask) { - bld.emit(BRW_OPCODE_ENDIF); + bld.emit(ELK_OPCODE_ENDIF); } emit_tcs_thread_end(); @@ -6832,13 +6832,13 @@ fs_visitor::run_tcs() } bool -fs_visitor::run_tes() +elk_fs_visitor::run_tes() { assert(stage == MESA_SHADER_TESS_EVAL); - payload_ = new tes_thread_payload(*this); + payload_ = new elk_tes_thread_payload(*this); - nir_to_brw(this); + nir_to_elk(this); if (failed) return false; @@ -6864,11 +6864,11 @@ fs_visitor::run_tes() } bool -fs_visitor::run_gs() +elk_fs_visitor::run_gs() { assert(stage == MESA_SHADER_GEOMETRY); - payload_ = new gs_thread_payload(*this); + payload_ = new elk_gs_thread_payload(*this); this->final_gs_vertex_count = vgrf(glsl_uint_type()); @@ -6883,11 +6883,11 @@ fs_visitor::run_gs() if (gs_compile->control_data_header_size_bits <= 32) { const fs_builder bld = fs_builder(this).at_end(); const fs_builder abld = bld.annotate("initialize control data bits"); - abld.MOV(this->control_data_bits, brw_imm_ud(0u)); + abld.MOV(this->control_data_bits, elk_imm_ud(0u)); } } - nir_to_brw(this); + nir_to_elk(this); emit_gs_thread_end(); @@ -6925,7 +6925,7 @@ fs_visitor::run_gs() * overhead. */ static void -gfx9_ps_header_only_workaround(struct brw_wm_prog_data *wm_prog_data) +gfx9_ps_header_only_workaround(struct elk_wm_prog_data *wm_prog_data) { if (wm_prog_data->num_varying_inputs) return; @@ -6936,19 +6936,19 @@ gfx9_ps_header_only_workaround(struct brw_wm_prog_data *wm_prog_data) wm_prog_data->urb_setup[VARYING_SLOT_LAYER] = 0; wm_prog_data->num_varying_inputs = 1; - brw_compute_urb_setup_index(wm_prog_data); + elk_compute_urb_setup_index(wm_prog_data); } bool -fs_visitor::run_fs(bool allow_spilling, bool do_rep_send) +elk_fs_visitor::run_fs(bool allow_spilling, bool do_rep_send) { - struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data); - brw_wm_prog_key *wm_key = (brw_wm_prog_key *) this->key; + struct elk_wm_prog_data *wm_prog_data = elk_wm_prog_data(this->prog_data); + elk_wm_prog_key *wm_key = (elk_wm_prog_key *) this->key; const fs_builder bld = fs_builder(this).at_end(); assert(stage == MESA_SHADER_FRAGMENT); - payload_ = new fs_thread_payload(*this, source_depth_to_render_target, + payload_ = new elk_fs_thread_payload(*this, source_depth_to_render_target, runtime_check_aads_emit); if (do_rep_send) { @@ -6975,20 +6975,20 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send) * stored in R0.15/R1.15 on gfx20+ and in R1.7/R2.7 on * gfx6+. */ - const fs_reg dispatch_mask = + const elk_fs_reg dispatch_mask = devinfo->ver >= 20 ? xe2_vec1_grf(i, 15) : - devinfo->ver >= 6 ? brw_vec1_grf(i + 1, 7) : - brw_vec1_grf(0, 0); + devinfo->ver >= 6 ? elk_vec1_grf(i + 1, 7) : + elk_vec1_grf(0, 0); bld.exec_all().group(1, 0) - .MOV(brw_sample_mask_reg(bld.group(lower_width, i)), - retype(dispatch_mask, BRW_REGISTER_TYPE_UW)); + .MOV(elk_sample_mask_reg(bld.group(lower_width, i)), + retype(dispatch_mask, ELK_REGISTER_TYPE_UW)); } } if (nir->info.writes_memory) wm_prog_data->has_side_effects = true; - nir_to_brw(this); + nir_to_elk(this); if (failed) return false; @@ -7022,22 +7022,22 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send) } bool -fs_visitor::run_cs(bool allow_spilling) +elk_fs_visitor::run_cs(bool allow_spilling) { assert(gl_shader_stage_is_compute(stage)); assert(devinfo->ver >= 7); const fs_builder bld = fs_builder(this).at_end(); - payload_ = new cs_thread_payload(*this); + payload_ = new elk_cs_thread_payload(*this); if (devinfo->platform == INTEL_PLATFORM_HSW && prog_data->total_shared > 0) { /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */ const fs_builder abld = bld.exec_all().group(1, 0); - abld.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW), - suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW), 1)); + abld.MOV(retype(elk_sr0_reg(1), ELK_REGISTER_TYPE_UW), + suboffset(retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_UW), 1)); } - nir_to_brw(this); + nir_to_elk(this); if (failed) return false; @@ -7081,14 +7081,14 @@ is_used_in_not_interp_frag_coord(nir_def *def) /** * Return a bitfield where bit n is set if barycentric interpolation mode n - * (see enum brw_barycentric_mode) is needed by the fragment shader. + * (see enum elk_barycentric_mode) is needed by the fragment shader. * * We examine the load_barycentric intrinsics rather than looking at input * variables so that we catch interpolateAtCentroid() messages too, which - * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up. + * also need the ELK_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up. */ static unsigned -brw_compute_barycentric_interp_modes(const struct intel_device_info *devinfo, +elk_compute_barycentric_interp_modes(const struct intel_device_info *devinfo, const nir_shader *shader) { unsigned barycentric_interp_modes = 0; @@ -7116,8 +7116,8 @@ brw_compute_barycentric_interp_modes(const struct intel_device_info *devinfo, continue; nir_intrinsic_op bary_op = intrin->intrinsic; - enum brw_barycentric_mode bary = - brw_barycentric_mode(intrin); + enum elk_barycentric_mode bary = + elk_barycentric_mode(intrin); barycentric_interp_modes |= 1 << bary; @@ -7132,7 +7132,7 @@ brw_compute_barycentric_interp_modes(const struct intel_device_info *devinfo, } static void -brw_compute_flat_inputs(struct brw_wm_prog_data *prog_data, +elk_compute_flat_inputs(struct elk_wm_prog_data *prog_data, const nir_shader *shader) { prog_data->flat_inputs = 0; @@ -7162,11 +7162,11 @@ computed_depth_mode(const nir_shader *shader) switch (shader->info.fs.depth_layout) { case FRAG_DEPTH_LAYOUT_NONE: case FRAG_DEPTH_LAYOUT_ANY: - return BRW_PSCDEPTH_ON; + return ELK_PSCDEPTH_ON; case FRAG_DEPTH_LAYOUT_GREATER: - return BRW_PSCDEPTH_ON_GE; + return ELK_PSCDEPTH_ON_GE; case FRAG_DEPTH_LAYOUT_LESS: - return BRW_PSCDEPTH_ON_LE; + return ELK_PSCDEPTH_ON_LE; case FRAG_DEPTH_LAYOUT_UNCHANGED: /* We initially set this to OFF, but having the shader write the * depth means we allocate register space in the SEND message. The @@ -7178,10 +7178,10 @@ computed_depth_mode(const nir_shader *shader) * (unchanged/equal). * */ - return BRW_PSCDEPTH_ON_LE; + return ELK_PSCDEPTH_ON_LE; } } - return BRW_PSCDEPTH_OFF; + return ELK_PSCDEPTH_OFF; } /** @@ -7200,7 +7200,7 @@ computed_depth_mode(const nir_shader *shader) * This should be replaced by global value numbering someday. */ bool -brw_nir_move_interpolation_to_top(nir_shader *nir) +elk_nir_move_interpolation_to_top(nir_shader *nir) { bool progress = false; @@ -7255,10 +7255,10 @@ brw_nir_move_interpolation_to_top(nir_shader *nir) } static void -brw_nir_populate_wm_prog_data(nir_shader *shader, +elk_nir_populate_wm_prog_data(nir_shader *shader, const struct intel_device_info *devinfo, - const struct brw_wm_prog_key *key, - struct brw_wm_prog_data *prog_data) + const struct elk_wm_prog_key *key, + struct elk_wm_prog_data *prog_data) { /* key->alpha_test_func means simulating alpha testing via discards, * so the shader definitely kills pixels. @@ -7278,12 +7278,12 @@ brw_nir_populate_wm_prog_data(nir_shader *shader, shader->info.fs.uses_sample_shading || shader->info.outputs_read; - assert(key->multisample_fbo != BRW_NEVER || - key->persample_interp == BRW_NEVER); + assert(key->multisample_fbo != ELK_NEVER || + key->persample_interp == ELK_NEVER); prog_data->persample_dispatch = key->persample_interp; if (prog_data->sample_shading) - prog_data->persample_dispatch = BRW_ALWAYS; + prog_data->persample_dispatch = ELK_ALWAYS; /* We can only persample dispatch if we have a multisample FBO */ prog_data->persample_dispatch = MIN2(prog_data->persample_dispatch, @@ -7294,8 +7294,8 @@ brw_nir_populate_wm_prog_data(nir_shader *shader, * to definitively tell whether alpha_to_coverage is on or off. */ prog_data->alpha_to_coverage = key->alpha_to_coverage; - assert(prog_data->alpha_to_coverage != BRW_SOMETIMES || - prog_data->persample_dispatch == BRW_SOMETIMES); + assert(prog_data->alpha_to_coverage != ELK_SOMETIMES || + prog_data->persample_dispatch == ELK_SOMETIMES); if (devinfo->ver >= 6) { prog_data->uses_sample_mask = @@ -7311,7 +7311,7 @@ brw_nir_populate_wm_prog_data(nir_shader *shader, * persample dispatch, we hard-code it to 0.5. */ prog_data->uses_pos_offset = - prog_data->persample_dispatch != BRW_NEVER && + prog_data->persample_dispatch != ELK_NEVER && (BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) || BITSET_TEST(shader->info.system_values_read, @@ -7325,7 +7325,7 @@ brw_nir_populate_wm_prog_data(nir_shader *shader, prog_data->inner_coverage = shader->info.fs.inner_coverage; prog_data->barycentric_interp_modes = - brw_compute_barycentric_interp_modes(devinfo, shader); + elk_compute_barycentric_interp_modes(devinfo, shader); /* From the BDW PRM documentation for 3DSTATE_WM: * @@ -7335,33 +7335,33 @@ brw_nir_populate_wm_prog_data(nir_shader *shader, * So cleanup any potentially set sample barycentric mode when not in per * sample dispatch. */ - if (prog_data->persample_dispatch == BRW_NEVER) { + if (prog_data->persample_dispatch == ELK_NEVER) { prog_data->barycentric_interp_modes &= - ~BITFIELD_BIT(BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE); + ~BITFIELD_BIT(ELK_BARYCENTRIC_PERSPECTIVE_SAMPLE); } prog_data->uses_nonperspective_interp_modes |= (prog_data->barycentric_interp_modes & - BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) != 0; + ELK_BARYCENTRIC_NONPERSPECTIVE_BITS) != 0; /* The current VK_EXT_graphics_pipeline_library specification requires * coarse to specified at compile time. But per sample interpolation can be * dynamic. So we should never be in a situation where coarse & - * persample_interp are both respectively true & BRW_ALWAYS. + * persample_interp are both respectively true & ELK_ALWAYS. * * Coarse will dynamically turned off when persample_interp is active. */ - assert(!key->coarse_pixel || key->persample_interp != BRW_ALWAYS); + assert(!key->coarse_pixel || key->persample_interp != ELK_ALWAYS); prog_data->coarse_pixel_dispatch = - brw_sometimes_invert(prog_data->persample_dispatch); + elk_sometimes_invert(prog_data->persample_dispatch); if (!key->coarse_pixel || prog_data->uses_omask || prog_data->sample_shading || prog_data->uses_sample_mask || - (prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF) || + (prog_data->computed_depth_mode != ELK_PSCDEPTH_OFF) || prog_data->computed_stencil) { - prog_data->coarse_pixel_dispatch = BRW_NEVER; + prog_data->coarse_pixel_dispatch = ELK_NEVER; } /* ICL PRMs, Volume 9: Render Engine, Shared Functions Pixel Interpolater, @@ -7391,7 +7391,7 @@ brw_nir_populate_wm_prog_data(nir_shader *shader, * interpolater message at sample. */ if (intel_nir_pulls_at_sample(shader)) - prog_data->coarse_pixel_dispatch = BRW_NEVER; + prog_data->coarse_pixel_dispatch = ELK_NEVER; /* We choose to always enable VMask prior to XeHP, as it would cause * us to lose out on the eliminate_find_live_channel() optimization. @@ -7399,19 +7399,19 @@ brw_nir_populate_wm_prog_data(nir_shader *shader, prog_data->uses_vmask = devinfo->verx10 < 125 || shader->info.fs.needs_quad_helper_invocations || shader->info.uses_wide_subgroup_intrinsics || - prog_data->coarse_pixel_dispatch != BRW_NEVER; + prog_data->coarse_pixel_dispatch != ELK_NEVER; prog_data->uses_src_w = BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD); prog_data->uses_src_depth = BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) && - prog_data->coarse_pixel_dispatch != BRW_ALWAYS; + prog_data->coarse_pixel_dispatch != ELK_ALWAYS; prog_data->uses_depth_w_coefficients = BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) && - prog_data->coarse_pixel_dispatch != BRW_NEVER; + prog_data->coarse_pixel_dispatch != ELK_NEVER; calculate_urb_setup(devinfo, key, prog_data, shader); - brw_compute_flat_inputs(prog_data, shader); + elk_compute_flat_inputs(prog_data, shader); } /** @@ -7420,21 +7420,21 @@ brw_nir_populate_wm_prog_data(nir_shader *shader, * granularity. The unit states wanted these block counts. */ static inline int -brw_register_blocks(int reg_count) +elk_register_blocks(int reg_count) { return ALIGN(reg_count, 16) / 16 - 1; } const unsigned * -brw_compile_fs(const struct brw_compiler *compiler, - struct brw_compile_fs_params *params) +elk_compile_fs(const struct elk_compiler *compiler, + struct elk_compile_fs_params *params) { struct nir_shader *nir = params->base.nir; - const struct brw_wm_prog_key *key = params->key; - struct brw_wm_prog_data *prog_data = params->prog_data; + const struct elk_wm_prog_key *key = params->key; + struct elk_wm_prog_data *prog_data = params->prog_data; bool allow_spilling = params->allow_spilling; const bool debug_enabled = - brw_should_print_shader(nir, params->base.debug_flag ? + elk_should_print_shader(nir, params->base.debug_flag ? params->base.debug_flag : DEBUG_WM); prog_data->base.stage = MESA_SHADER_FRAGMENT; @@ -7444,40 +7444,40 @@ brw_compile_fs(const struct brw_compiler *compiler, const struct intel_device_info *devinfo = compiler->devinfo; const unsigned max_subgroup_size = compiler->devinfo->ver >= 6 ? 32 : 16; - brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size); - brw_nir_lower_fs_inputs(nir, devinfo, key); - brw_nir_lower_fs_outputs(nir); + elk_nir_apply_key(nir, compiler, &key->base, max_subgroup_size); + elk_nir_lower_fs_inputs(nir, devinfo, key); + elk_nir_lower_fs_outputs(nir); if (devinfo->ver < 6) - brw_setup_vue_interpolation(params->vue_map, nir, prog_data); + elk_setup_vue_interpolation(params->vue_map, nir, prog_data); /* From the SKL PRM, Volume 7, "Alpha Coverage": * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in * hardware, regardless of the state setting for this feature." */ - if (devinfo->ver > 6 && key->alpha_to_coverage != BRW_NEVER) { + if (devinfo->ver > 6 && key->alpha_to_coverage != ELK_NEVER) { /* Run constant fold optimization in order to get the correct source * offset to determine render target 0 store instruction in * emit_alpha_to_coverage pass. */ NIR_PASS(_, nir, nir_opt_constant_folding); - NIR_PASS(_, nir, brw_nir_lower_alpha_to_coverage, key, prog_data); + NIR_PASS(_, nir, elk_nir_lower_alpha_to_coverage, key, prog_data); } - NIR_PASS(_, nir, brw_nir_move_interpolation_to_top); - brw_postprocess_nir(nir, compiler, debug_enabled, + NIR_PASS(_, nir, elk_nir_move_interpolation_to_top); + elk_postprocess_nir(nir, compiler, debug_enabled, key->base.robust_flags); - brw_nir_populate_wm_prog_data(nir, compiler->devinfo, key, prog_data); + elk_nir_populate_wm_prog_data(nir, compiler->devinfo, key, prog_data); - std::unique_ptr v8, v16, v32, vmulti; - cfg_t *simd8_cfg = NULL, *simd16_cfg = NULL, *simd32_cfg = NULL, + std::unique_ptr v8, v16, v32, vmulti; + elk_cfg_t *simd8_cfg = NULL, *simd16_cfg = NULL, *simd32_cfg = NULL, *multi_cfg = NULL; float throughput = 0; bool has_spilled = false; if (devinfo->ver < 20) { - v8 = std::make_unique(compiler, ¶ms->base, key, + v8 = std::make_unique(compiler, ¶ms->base, key, prog_data, nir, 8, 1, params->base.stats != NULL, debug_enabled); @@ -7491,7 +7491,7 @@ brw_compile_fs(const struct brw_compiler *compiler, assert(v8->payload().num_regs % reg_unit(devinfo) == 0); prog_data->base.dispatch_grf_start_reg = v8->payload().num_regs / reg_unit(devinfo); - prog_data->reg_blocks_8 = brw_register_blocks(v8->grf_used); + prog_data->reg_blocks_8 = elk_register_blocks(v8->grf_used); const performance &perf = v8->performance_analysis.require(); throughput = MAX2(throughput, perf.throughput); has_spilled = v8->spilled_any_registers; @@ -7525,14 +7525,14 @@ brw_compile_fs(const struct brw_compiler *compiler, (!v8 || v8->max_dispatch_width >= 16) && (INTEL_SIMD(FS, 16) || params->use_rep_send)) { /* Try a SIMD16 compile */ - v16 = std::make_unique(compiler, ¶ms->base, key, + v16 = std::make_unique(compiler, ¶ms->base, key, prog_data, nir, 16, 1, params->base.stats != NULL, debug_enabled); if (v8) v16->import_uniforms(v8.get()); if (!v16->run_fs(allow_spilling, params->use_rep_send)) { - brw_shader_perf_log(compiler, params->base.log_data, + elk_shader_perf_log(compiler, params->base.log_data, "SIMD16 shader failed to compile: %s\n", v16->fail_msg); } else { @@ -7541,7 +7541,7 @@ brw_compile_fs(const struct brw_compiler *compiler, assert(v16->payload().num_regs % reg_unit(devinfo) == 0); prog_data->dispatch_grf_start_reg_16 = v16->payload().num_regs / reg_unit(devinfo); - prog_data->reg_blocks_16 = brw_register_blocks(v16->grf_used); + prog_data->reg_blocks_16 = elk_register_blocks(v16->grf_used); const performance &perf = v16->performance_analysis.require(); throughput = MAX2(throughput, perf.throughput); has_spilled = v16->spilled_any_registers; @@ -7558,7 +7558,7 @@ brw_compile_fs(const struct brw_compiler *compiler, devinfo->ver >= 6 && !simd16_failed && INTEL_SIMD(FS, 32)) { /* Try a SIMD32 compile */ - v32 = std::make_unique(compiler, ¶ms->base, key, + v32 = std::make_unique(compiler, ¶ms->base, key, prog_data, nir, 32, 1, params->base.stats != NULL, debug_enabled); @@ -7568,14 +7568,14 @@ brw_compile_fs(const struct brw_compiler *compiler, v32->import_uniforms(v16.get()); if (!v32->run_fs(allow_spilling, false)) { - brw_shader_perf_log(compiler, params->base.log_data, + elk_shader_perf_log(compiler, params->base.log_data, "SIMD32 shader failed to compile: %s\n", v32->fail_msg); } else { const performance &perf = v32->performance_analysis.require(); if (!INTEL_DEBUG(DEBUG_DO32) && throughput >= perf.throughput) { - brw_shader_perf_log(compiler, params->base.log_data, + elk_shader_perf_log(compiler, params->base.log_data, "SIMD32 shader inefficient\n"); } else { simd32_cfg = v32->cfg; @@ -7583,7 +7583,7 @@ brw_compile_fs(const struct brw_compiler *compiler, assert(v32->payload().num_regs % reg_unit(devinfo) == 0); prog_data->dispatch_grf_start_reg_32 = v32->payload().num_regs / reg_unit(devinfo); - prog_data->reg_blocks_32 = brw_register_blocks(v32->grf_used); + prog_data->reg_blocks_32 = elk_register_blocks(v32->grf_used); throughput = MAX2(throughput, perf.throughput); } } @@ -7591,7 +7591,7 @@ brw_compile_fs(const struct brw_compiler *compiler, if (devinfo->ver >= 12 && !has_spilled && params->max_polygons >= 2 && !key->coarse_pixel) { - fs_visitor *vbase = v8 ? v8.get() : v16 ? v16.get() : v32.get(); + elk_fs_visitor *vbase = v8 ? v8.get() : v16 ? v16.get() : v32.get(); assert(vbase); if (devinfo->ver >= 20 && @@ -7600,13 +7600,13 @@ brw_compile_fs(const struct brw_compiler *compiler, 4 * prog_data->num_varying_inputs <= MAX_VARYING && INTEL_SIMD(FS, 4X8)) { /* Try a quad-SIMD8 compile */ - vmulti = std::make_unique(compiler, ¶ms->base, key, + vmulti = std::make_unique(compiler, ¶ms->base, key, prog_data, nir, 32, 4, params->base.stats != NULL, debug_enabled); vmulti->import_uniforms(vbase); if (!vmulti->run_fs(false, params->use_rep_send)) { - brw_shader_perf_log(compiler, params->base.log_data, + elk_shader_perf_log(compiler, params->base.log_data, "Quad-SIMD8 shader failed to compile: %s\n", vmulti->fail_msg); } else { @@ -7620,13 +7620,13 @@ brw_compile_fs(const struct brw_compiler *compiler, 2 * prog_data->num_varying_inputs <= MAX_VARYING && INTEL_SIMD(FS, 2X16)) { /* Try a dual-SIMD16 compile */ - vmulti = std::make_unique(compiler, ¶ms->base, key, + vmulti = std::make_unique(compiler, ¶ms->base, key, prog_data, nir, 32, 2, params->base.stats != NULL, debug_enabled); vmulti->import_uniforms(vbase); if (!vmulti->run_fs(false, params->use_rep_send)) { - brw_shader_perf_log(compiler, params->base.log_data, + elk_shader_perf_log(compiler, params->base.log_data, "Dual-SIMD16 shader failed to compile: %s\n", vmulti->fail_msg); } else { @@ -7639,13 +7639,13 @@ brw_compile_fs(const struct brw_compiler *compiler, 2 * prog_data->num_varying_inputs <= MAX_VARYING && INTEL_SIMD(FS, 2X8)) { /* Try a dual-SIMD8 compile */ - vmulti = std::make_unique(compiler, ¶ms->base, key, + vmulti = std::make_unique(compiler, ¶ms->base, key, prog_data, nir, 16, 2, params->base.stats != NULL, debug_enabled); vmulti->import_uniforms(vbase); if (!vmulti->run_fs(allow_spilling, params->use_rep_send)) { - brw_shader_perf_log(compiler, params->base.log_data, + elk_shader_perf_log(compiler, params->base.log_data, "Dual-SIMD8 shader failed to compile: %s\n", vmulti->fail_msg); } else { @@ -7657,7 +7657,7 @@ brw_compile_fs(const struct brw_compiler *compiler, assert(vmulti->payload().num_regs % reg_unit(devinfo) == 0); prog_data->base.dispatch_grf_start_reg = vmulti->payload().num_regs / reg_unit(devinfo); - prog_data->reg_blocks_8 = brw_register_blocks(vmulti->grf_used); + prog_data->reg_blocks_8 = elk_register_blocks(vmulti->grf_used); } } @@ -7679,7 +7679,7 @@ brw_compile_fs(const struct brw_compiler *compiler, /* If computed depth is enabled SNB only allows SIMD8. */ if (compiler->devinfo->ver == 6 && - prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF) + prog_data->computed_depth_mode != ELK_PSCDEPTH_OFF) assert(simd16_cfg == NULL && simd32_cfg == NULL); if (compiler->devinfo->ver <= 5 && !simd8_cfg) { @@ -7695,7 +7695,7 @@ brw_compile_fs(const struct brw_compiler *compiler, } } - fs_generator g(compiler, ¶ms->base, &prog_data->base, + elk_fs_generator g(compiler, ¶ms->base, &prog_data->base, v8 && v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT); if (unlikely(debug_enabled)) { @@ -7706,7 +7706,7 @@ brw_compile_fs(const struct brw_compiler *compiler, nir->info.name)); } - struct brw_compile_stats *stats = params->base.stats; + struct elk_compile_stats *stats = params->base.stats; uint32_t max_dispatch_width = 0; if (multi_cfg) { @@ -7744,7 +7744,7 @@ brw_compile_fs(const struct brw_compiler *compiler, max_dispatch_width = 32; } - for (struct brw_compile_stats *s = params->base.stats; s != NULL && s != stats; s++) + for (struct elk_compile_stats *s = params->base.stats; s != NULL && s != stats; s++) s->max_dispatch_width = max_dispatch_width; g.add_const_data(nir->constant_data, nir->constant_data_size); @@ -7752,7 +7752,7 @@ brw_compile_fs(const struct brw_compiler *compiler, } unsigned -brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data, +elk_cs_push_const_total_size(const struct elk_cs_prog_data *cs_prog_data, unsigned threads) { assert(cs_prog_data->push.per_thread.size % REG_SIZE == 0); @@ -7762,7 +7762,7 @@ brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data, } static void -fill_push_const_block_info(struct brw_push_const_block *block, unsigned dwords) +fill_push_const_block_info(struct elk_push_const_block *block, unsigned dwords) { block->dwords = dwords; block->regs = DIV_ROUND_UP(dwords, 8); @@ -7771,10 +7771,10 @@ fill_push_const_block_info(struct brw_push_const_block *block, unsigned dwords) static void cs_fill_push_const_info(const struct intel_device_info *devinfo, - struct brw_cs_prog_data *cs_prog_data) + struct elk_cs_prog_data *cs_prog_data) { - const struct brw_stage_prog_data *prog_data = &cs_prog_data->base; - int subgroup_id_index = brw_get_subgroup_id_param_index(devinfo, prog_data); + const struct elk_stage_prog_data *prog_data = &cs_prog_data->base; + int subgroup_id_index = elk_get_subgroup_id_param_index(devinfo, prog_data); bool cross_thread_supported = devinfo->verx10 >= 75; /* The thread ID should be stored in the last param dword */ @@ -7850,22 +7850,22 @@ lower_simd(nir_builder *b, nir_instr *instr, void *options) } bool -brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width) +elk_nir_lower_simd(nir_shader *nir, unsigned dispatch_width) { return nir_shader_lower_instructions(nir, filter_simd, lower_simd, (void *)(uintptr_t)dispatch_width); } const unsigned * -brw_compile_cs(const struct brw_compiler *compiler, - struct brw_compile_cs_params *params) +elk_compile_cs(const struct elk_compiler *compiler, + struct elk_compile_cs_params *params) { const nir_shader *nir = params->base.nir; - const struct brw_cs_prog_key *key = params->key; - struct brw_cs_prog_data *prog_data = params->prog_data; + const struct elk_cs_prog_key *key = params->key; + struct elk_cs_prog_data *prog_data = params->prog_data; const bool debug_enabled = - brw_should_print_shader(nir, params->base.debug_flag ? + elk_should_print_shader(nir, params->base.debug_flag ? params->base.debug_flag : DEBUG_CS); prog_data->base.stage = MESA_SHADER_COMPUTE; @@ -7879,41 +7879,41 @@ brw_compile_cs(const struct brw_compiler *compiler, prog_data->local_size[2] = nir->info.workgroup_size[2]; } - brw_simd_selection_state simd_state{ + elk_simd_selection_state simd_state{ .devinfo = compiler->devinfo, .prog_data = prog_data, - .required_width = brw_required_dispatch_width(&nir->info), + .required_width = elk_required_dispatch_width(&nir->info), }; - std::unique_ptr v[3]; + std::unique_ptr v[3]; for (unsigned simd = 0; simd < 3; simd++) { - if (!brw_simd_should_compile(simd_state, simd)) + if (!elk_simd_should_compile(simd_state, simd)) continue; const unsigned dispatch_width = 8u << simd; nir_shader *shader = nir_shader_clone(params->base.mem_ctx, nir); - brw_nir_apply_key(shader, compiler, &key->base, + elk_nir_apply_key(shader, compiler, &key->base, dispatch_width); - NIR_PASS(_, shader, brw_nir_lower_simd, dispatch_width); + NIR_PASS(_, shader, elk_nir_lower_simd, dispatch_width); /* Clean up after the local index and ID calculations. */ NIR_PASS(_, shader, nir_opt_constant_folding); NIR_PASS(_, shader, nir_opt_dce); - brw_postprocess_nir(shader, compiler, debug_enabled, + elk_postprocess_nir(shader, compiler, debug_enabled, key->base.robust_flags); - v[simd] = std::make_unique(compiler, ¶ms->base, + v[simd] = std::make_unique(compiler, ¶ms->base, &key->base, &prog_data->base, shader, dispatch_width, params->base.stats != NULL, debug_enabled); - const int first = brw_simd_first_compiled(simd_state); + const int first = elk_simd_first_compiled(simd_state); if (first >= 0) v[simd]->import_uniforms(v[first].get()); @@ -7922,18 +7922,18 @@ brw_compile_cs(const struct brw_compiler *compiler, if (v[simd]->run_cs(allow_spilling)) { cs_fill_push_const_info(compiler->devinfo, prog_data); - brw_simd_mark_compiled(simd_state, simd, v[simd]->spilled_any_registers); + elk_simd_mark_compiled(simd_state, simd, v[simd]->spilled_any_registers); } else { simd_state.error[simd] = ralloc_strdup(params->base.mem_ctx, v[simd]->fail_msg); if (simd > 0) { - brw_shader_perf_log(compiler, params->base.log_data, + elk_shader_perf_log(compiler, params->base.log_data, "SIMD%u shader failed to compile: %s\n", dispatch_width, v[simd]->fail_msg); } } } - const int selected_simd = brw_simd_select(simd_state); + const int selected_simd = elk_simd_select(simd_state); if (selected_simd < 0) { params->base.error_str = ralloc_asprintf(params->base.mem_ctx, @@ -7945,12 +7945,12 @@ brw_compile_cs(const struct brw_compiler *compiler, } assert(selected_simd < 3); - fs_visitor *selected = v[selected_simd].get(); + elk_fs_visitor *selected = v[selected_simd].get(); if (!nir->info.workgroup_size_variable) prog_data->prog_mask = 1 << selected_simd; - fs_generator g(compiler, ¶ms->base, &prog_data->base, + elk_fs_generator g(compiler, ¶ms->base, &prog_data->base, selected->runtime_check_aads_emit, MESA_SHADER_COMPUTE); if (unlikely(debug_enabled)) { char *name = ralloc_asprintf(params->base.mem_ctx, @@ -7963,7 +7963,7 @@ brw_compile_cs(const struct brw_compiler *compiler, uint32_t max_dispatch_width = 8u << (util_last_bit(prog_data->prog_mask) - 1); - struct brw_compile_stats *stats = params->base.stats; + struct elk_compile_stats *stats = params->base.stats; for (unsigned simd = 0; simd < 3; simd++) { if (prog_data->prog_mask & (1u << simd)) { assert(v[simd]); @@ -7983,8 +7983,8 @@ brw_compile_cs(const struct brw_compiler *compiler, } struct intel_cs_dispatch_info -brw_cs_get_dispatch_info(const struct intel_device_info *devinfo, - const struct brw_cs_prog_data *prog_data, +elk_cs_get_dispatch_info(const struct intel_device_info *devinfo, + const struct elk_cs_prog_data *prog_data, const unsigned *override_local_size) { struct intel_cs_dispatch_info info = {}; @@ -7993,7 +7993,7 @@ brw_cs_get_dispatch_info(const struct intel_device_info *devinfo, override_local_size ? override_local_size : prog_data->local_size; - const int simd = brw_simd_select_for_workgroup_size(devinfo, prog_data, sizes); + const int simd = elk_simd_select_for_workgroup_size(devinfo, prog_data, sizes); assert(simd >= 0 && simd < 3); info.group_size = sizes[0] * sizes[1] * sizes[2]; @@ -8010,7 +8010,7 @@ brw_cs_get_dispatch_info(const struct intel_device_info *devinfo, } uint64_t -brw_bsr(const struct intel_device_info *devinfo, +elk_bsr(const struct intel_device_info *devinfo, uint32_t offset, uint8_t simd_size, uint8_t local_arg_offset) { assert(offset % 64 == 0); @@ -8024,69 +8024,69 @@ brw_bsr(const struct intel_device_info *devinfo, /** * Test the dispatch mask packing assumptions of - * brw_stage_has_packed_dispatch(). Call this from e.g. the top of - * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is + * elk_stage_has_packed_dispatch(). Call this from e.g. the top of + * elk_fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is * executed with an unexpected dispatch mask. */ static UNUSED void -brw_fs_test_dispatch_packing(const fs_builder &bld) +elk_fs_test_dispatch_packing(const fs_builder &bld) { - const fs_visitor *shader = static_cast(bld.shader); + const elk_fs_visitor *shader = static_cast(bld.shader); const gl_shader_stage stage = shader->stage; const bool uses_vmask = stage == MESA_SHADER_FRAGMENT && - brw_wm_prog_data(shader->stage_prog_data)->uses_vmask; + elk_wm_prog_data(shader->stage_prog_data)->uses_vmask; - if (brw_stage_has_packed_dispatch(shader->devinfo, stage, + if (elk_stage_has_packed_dispatch(shader->devinfo, stage, shader->max_polygons, shader->stage_prog_data)) { const fs_builder ubld = bld.exec_all().group(1, 0); - const fs_reg tmp = component(bld.vgrf(BRW_REGISTER_TYPE_UD), 0); - const fs_reg mask = uses_vmask ? brw_vmask_reg() : brw_dmask_reg(); + const elk_fs_reg tmp = component(bld.vgrf(ELK_REGISTER_TYPE_UD), 0); + const elk_fs_reg mask = uses_vmask ? elk_vmask_reg() : elk_dmask_reg(); - ubld.ADD(tmp, mask, brw_imm_ud(1)); + ubld.ADD(tmp, mask, elk_imm_ud(1)); ubld.AND(tmp, mask, tmp); /* This will loop forever if the dispatch mask doesn't have the expected * form '2^n-1', in which case tmp will be non-zero. */ - bld.emit(BRW_OPCODE_DO); - bld.CMP(bld.null_reg_ud(), tmp, brw_imm_ud(0), BRW_CONDITIONAL_NZ); - set_predicate(BRW_PREDICATE_NORMAL, bld.emit(BRW_OPCODE_WHILE)); + bld.emit(ELK_OPCODE_DO); + bld.CMP(bld.null_reg_ud(), tmp, elk_imm_ud(0), ELK_CONDITIONAL_NZ); + set_predicate(ELK_PREDICATE_NORMAL, bld.emit(ELK_OPCODE_WHILE)); } } unsigned -fs_visitor::workgroup_size() const +elk_fs_visitor::workgroup_size() const { assert(gl_shader_stage_uses_workgroup(stage)); - const struct brw_cs_prog_data *cs = brw_cs_prog_data(prog_data); + const struct elk_cs_prog_data *cs = elk_cs_prog_data(prog_data); return cs->local_size[0] * cs->local_size[1] * cs->local_size[2]; } -bool brw_should_print_shader(const nir_shader *shader, uint64_t debug_flag) +bool elk_should_print_shader(const nir_shader *shader, uint64_t debug_flag) { return INTEL_DEBUG(debug_flag) && (!shader->info.internal || NIR_DEBUG(PRINT_INTERNAL)); } namespace elk { - fs_reg + elk_fs_reg fetch_payload_reg(const elk::fs_builder &bld, uint8_t regs[2], - brw_reg_type type, unsigned n) + elk_reg_type type, unsigned n) { if (!regs[0]) - return fs_reg(); + return elk_fs_reg(); if (bld.dispatch_width() > 16) { - const fs_reg tmp = bld.vgrf(type, n); + const elk_fs_reg tmp = bld.vgrf(type, n); const elk::fs_builder hbld = bld.exec_all().group(16, 0); const unsigned m = bld.dispatch_width() / hbld.dispatch_width(); - fs_reg *const components = new fs_reg[m * n]; + elk_fs_reg *const components = new elk_fs_reg[m * n]; for (unsigned c = 0; c < n; c++) { for (unsigned g = 0; g < m; g++) components[c * m + g] = - offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c); + offset(retype(elk_vec8_grf(regs[g], 0), type), hbld, c); } hbld.LOAD_PAYLOAD(tmp, components, m * n, 0); @@ -8095,26 +8095,26 @@ namespace elk { return tmp; } else { - return fs_reg(retype(brw_vec8_grf(regs[0], 0), type)); + return elk_fs_reg(retype(elk_vec8_grf(regs[0], 0), type)); } } - fs_reg + elk_fs_reg fetch_barycentric_reg(const elk::fs_builder &bld, uint8_t regs[2]) { if (!regs[0]) - return fs_reg(); + return elk_fs_reg(); else if (bld.shader->devinfo->ver >= 20) - return fetch_payload_reg(bld, regs, BRW_REGISTER_TYPE_F, 2); + return fetch_payload_reg(bld, regs, ELK_REGISTER_TYPE_F, 2); - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, 2); + const elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_F, 2); const elk::fs_builder hbld = bld.exec_all().group(8, 0); const unsigned m = bld.dispatch_width() / hbld.dispatch_width(); - fs_reg *const components = new fs_reg[2 * m]; + elk_fs_reg *const components = new elk_fs_reg[2 * m]; for (unsigned c = 0; c < 2; c++) { for (unsigned g = 0; g < m; g++) - components[c * m + g] = offset(brw_vec8_grf(regs[g / 2], 0), + components[c * m + g] = offset(elk_vec8_grf(regs[g / 2], 0), hbld, c + 2 * (g % 2)); } @@ -8126,12 +8126,12 @@ namespace elk { void check_dynamic_msaa_flag(const fs_builder &bld, - const struct brw_wm_prog_data *wm_prog_data, + const struct elk_wm_prog_data *wm_prog_data, enum intel_msaa_flags flag) { - fs_inst *inst = bld.AND(bld.null_reg_ud(), + elk_fs_inst *inst = bld.AND(bld.null_reg_ud(), dynamic_msaa_flags(wm_prog_data), - brw_imm_ud(flag)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; + elk_imm_ud(flag)); + inst->conditional_mod = ELK_CONDITIONAL_NZ; } } diff --git a/src/intel/compiler/elk/elk_fs.h b/src/intel/compiler/elk/elk_fs.h index 32034a0f4e7..4a17f868862 100644 --- a/src/intel/compiler/elk/elk_fs.h +++ b/src/intel/compiler/elk/elk_fs.h @@ -34,12 +34,12 @@ #include "elk_ir_performance.h" #include "compiler/nir/nir.h" -struct bblock_t; +struct elk_bblock_t; namespace { struct acp_entry; } -class fs_visitor; +class elk_fs_visitor; namespace elk { /** @@ -47,7 +47,7 @@ namespace elk { * are live at any point of the program in GRF units. */ struct register_pressure { - register_pressure(const fs_visitor *v); + register_pressure(const elk_fs_visitor *v); ~register_pressure(); analysis_dependency_class @@ -59,7 +59,7 @@ namespace elk { } bool - validate(const fs_visitor *) const + validate(const elk_fs_visitor *) const { /* FINISHME */ return true; @@ -69,7 +69,7 @@ namespace elk { }; } -struct brw_gs_compile; +struct elk_gs_compile; namespace elk { class fs_builder; @@ -84,50 +84,50 @@ struct shader_stats { }; /** Register numbers for thread payload fields. */ -struct thread_payload { +struct elk_elk_thread_payload { /** The number of thread payload registers the hardware will supply. */ uint8_t num_regs; - virtual ~thread_payload() = default; + virtual ~elk_elk_thread_payload() = default; protected: - thread_payload() : num_regs() {} + elk_elk_thread_payload() : num_regs() {} }; -struct vs_thread_payload : public thread_payload { - vs_thread_payload(const fs_visitor &v); +struct elk_vs_thread_payload : public elk_elk_thread_payload { + elk_vs_thread_payload(const elk_fs_visitor &v); - fs_reg urb_handles; + elk_fs_reg urb_handles; }; -struct tcs_thread_payload : public thread_payload { - tcs_thread_payload(const fs_visitor &v); +struct elk_tcs_thread_payload : public elk_elk_thread_payload { + elk_tcs_thread_payload(const elk_fs_visitor &v); - fs_reg patch_urb_output; - fs_reg primitive_id; - fs_reg icp_handle_start; + elk_fs_reg patch_urb_output; + elk_fs_reg primitive_id; + elk_fs_reg icp_handle_start; }; -struct tes_thread_payload : public thread_payload { - tes_thread_payload(const fs_visitor &v); +struct elk_tes_thread_payload : public elk_elk_thread_payload { + elk_tes_thread_payload(const elk_fs_visitor &v); - fs_reg patch_urb_input; - fs_reg primitive_id; - fs_reg coords[3]; - fs_reg urb_output; + elk_fs_reg patch_urb_input; + elk_fs_reg primitive_id; + elk_fs_reg coords[3]; + elk_fs_reg urb_output; }; -struct gs_thread_payload : public thread_payload { - gs_thread_payload(fs_visitor &v); +struct elk_gs_thread_payload : public elk_elk_thread_payload { + elk_gs_thread_payload(elk_fs_visitor &v); - fs_reg urb_handles; - fs_reg primitive_id; - fs_reg instance_id; - fs_reg icp_handle_start; + elk_fs_reg urb_handles; + elk_fs_reg primitive_id; + elk_fs_reg instance_id; + elk_fs_reg icp_handle_start; }; -struct fs_thread_payload : public thread_payload { - fs_thread_payload(const fs_visitor &v, +struct elk_fs_thread_payload : public elk_elk_thread_payload { + elk_fs_thread_payload(const elk_fs_visitor &v, bool &source_depth_to_render_target, bool &runtime_check_aads_emit); @@ -139,65 +139,65 @@ struct fs_thread_payload : public thread_payload { uint8_t sample_pos_reg[2]; uint8_t sample_mask_in_reg[2]; uint8_t depth_w_coef_reg; - uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2]; + uint8_t barycentric_coord_reg[ELK_BARYCENTRIC_MODE_COUNT][2]; }; -struct cs_thread_payload : public thread_payload { - cs_thread_payload(const fs_visitor &v); +struct elk_cs_thread_payload : public elk_elk_thread_payload { + elk_cs_thread_payload(const elk_fs_visitor &v); - void load_subgroup_id(const elk::fs_builder &bld, fs_reg &dest) const; + void load_subgroup_id(const elk::fs_builder &bld, elk_fs_reg &dest) const; - fs_reg local_invocation_id[3]; + elk_fs_reg local_invocation_id[3]; protected: - fs_reg subgroup_id_; + elk_fs_reg subgroup_id_; }; -class fs_instruction_scheduler; +class elk_fs_instruction_scheduler; /** * The fragment shader front-end. * * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR. */ -class fs_visitor : public backend_shader +class elk_fs_visitor : public elk_backend_shader { public: - fs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const brw_base_prog_key *key, - struct brw_stage_prog_data *prog_data, + elk_fs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const elk_base_prog_key *key, + struct elk_stage_prog_data *prog_data, const nir_shader *shader, unsigned dispatch_width, bool needs_register_pressure, bool debug_enabled); - fs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const brw_wm_prog_key *key, - struct brw_wm_prog_data *prog_data, + elk_fs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const elk_wm_prog_key *key, + struct elk_wm_prog_data *prog_data, const nir_shader *shader, unsigned dispatch_width, unsigned num_polygons, bool needs_register_pressure, bool debug_enabled); - fs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - struct brw_gs_compile *gs_compile, - struct brw_gs_prog_data *prog_data, + elk_fs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + struct elk_gs_compile *gs_compile, + struct elk_gs_prog_data *prog_data, const nir_shader *shader, bool needs_register_pressure, bool debug_enabled); void init(); - ~fs_visitor(); + ~elk_fs_visitor(); - fs_reg vgrf(const glsl_type *const type); - void import_uniforms(fs_visitor *v); + elk_fs_reg vgrf(const glsl_type *const type); + void import_uniforms(elk_fs_visitor *v); void VARYING_PULL_CONSTANT_LOAD(const elk::fs_builder &bld, - const fs_reg &dst, - const fs_reg &surface, - const fs_reg &surface_handle, - const fs_reg &varying_offset, + const elk_fs_reg &dst, + const elk_fs_reg &surface, + const elk_fs_reg &surface_handle, + const elk_fs_reg &varying_offset, uint32_t const_offset, uint8_t alignment, unsigned components); @@ -219,7 +219,7 @@ public: bool fixup_nomask_control_flow(); void assign_curb_setup(); void assign_urb_setup(); - void convert_attr_sources_to_hw_regs(fs_inst *inst); + void convert_attr_sources_to_hw_regs(elk_fs_inst *inst); void assign_vs_urb_setup(); void assign_tcs_urb_setup(); void assign_tes_urb_setup(); @@ -231,7 +231,7 @@ public: bool split_virtual_grfs(); bool compact_virtual_grfs(); void assign_constant_locations(); - bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index, + bool get_pull_locs(const elk_fs_reg &src, unsigned *out_surf_index, unsigned *out_pull_index); bool lower_constant_loads(); virtual void invalidate_analysis(elk::analysis_dependency_class c); @@ -245,7 +245,7 @@ public: bool opt_algebraic(); bool opt_redundant_halt(); bool opt_cse(); - bool opt_cse_local(const elk::fs_live_variables &live, bblock_t *block, int &ip); + bool opt_cse_local(const elk::fs_live_variables &live, elk_bblock_t *block, int &ip); bool opt_copy_propagation(); bool opt_bank_conflicts(); @@ -257,16 +257,16 @@ public: bool remove_duplicate_mrf_writes(); bool remove_extra_rounding_modes(); - fs_instruction_scheduler *prepare_scheduler(void *mem_ctx); - void schedule_instructions_pre_ra(fs_instruction_scheduler *sched, + elk_fs_instruction_scheduler *prepare_scheduler(void *mem_ctx); + void schedule_instructions_pre_ra(elk_fs_instruction_scheduler *sched, instruction_scheduler_mode mode); void schedule_instructions_post_ra(); void insert_gfx4_send_dependency_workarounds(); - void insert_gfx4_pre_send_dependency_workarounds(bblock_t *block, - fs_inst *inst); - void insert_gfx4_post_send_dependency_workarounds(bblock_t *block, - fs_inst *inst); + void insert_gfx4_pre_send_dependency_workarounds(elk_bblock_t *block, + elk_fs_inst *inst); + void insert_gfx4_post_send_dependency_workarounds(elk_bblock_t *block, + elk_fs_inst *inst); void vfail(const char *msg, va_list args); void fail(const char *msg, ...); void limit_dispatch_width(unsigned n, const char *msg); @@ -296,37 +296,37 @@ public: void set_tcs_invocation_id(); void emit_alpha_test(); - fs_inst *emit_single_fb_write(const elk::fs_builder &bld, - fs_reg color1, fs_reg color2, - fs_reg src0_alpha, unsigned components); + elk_fs_inst *emit_single_fb_write(const elk::fs_builder &bld, + elk_fs_reg color1, elk_fs_reg color2, + elk_fs_reg src0_alpha, unsigned components); void do_emit_fb_writes(int nr_color_regions, bool replicate_alpha); void emit_fb_writes(); - void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg()); - void emit_gs_control_data_bits(const fs_reg &vertex_count); + void emit_urb_writes(const elk_fs_reg &gs_vertex_count = elk_fs_reg()); + void emit_gs_control_data_bits(const elk_fs_reg &vertex_count); void emit_gs_thread_end(); bool mark_last_urb_write_with_eot(); void emit_tcs_thread_end(); void emit_urb_fence(); void emit_cs_terminate(); - fs_reg interp_reg(const elk::fs_builder &bld, unsigned location, + elk_fs_reg interp_reg(const elk::fs_builder &bld, unsigned location, unsigned channel, unsigned comp); - fs_reg per_primitive_reg(const elk::fs_builder &bld, + elk_fs_reg per_primitive_reg(const elk::fs_builder &bld, int location, unsigned comp); - virtual void dump_instruction_to_file(const backend_instruction *inst, FILE *file) const; + virtual void dump_instruction_to_file(const elk_backend_instruction *inst, FILE *file) const; virtual void dump_instructions_to_file(FILE *file) const; - const brw_base_prog_key *const key; - const struct brw_sampler_prog_key_data *key_tex; + const elk_base_prog_key *const key; + const struct elk_sampler_prog_key_data *key_tex; - struct brw_gs_compile *gs_compile; + struct elk_gs_compile *gs_compile; - struct brw_stage_prog_data *prog_data; + struct elk_stage_prog_data *prog_data; - brw_analysis live_analysis; - brw_analysis regpressure_analysis; - brw_analysis performance_analysis; + elk_analysis live_analysis; + elk_analysis regpressure_analysis; + elk_analysis performance_analysis; /** Number of uniform variable components visited. */ unsigned uniforms; @@ -340,66 +340,66 @@ public: */ int *push_constant_loc; - fs_reg frag_depth; - fs_reg frag_stencil; - fs_reg sample_mask; - fs_reg outputs[VARYING_SLOT_MAX]; - fs_reg dual_src_output; + elk_fs_reg frag_depth; + elk_fs_reg frag_stencil; + elk_fs_reg sample_mask; + elk_fs_reg outputs[VARYING_SLOT_MAX]; + elk_fs_reg dual_src_output; int first_non_payload_grf; - /** Either BRW_MAX_GRF or GFX7_MRF_HACK_START */ + /** Either ELK_MAX_GRF or GFX7_MRF_HACK_START */ unsigned max_grf; bool failed; char *fail_msg; - thread_payload *payload_; + elk_elk_thread_payload *payload_; - thread_payload &payload() { + elk_elk_thread_payload &payload() { return *this->payload_; } - vs_thread_payload &vs_payload() { + elk_vs_thread_payload &vs_payload() { assert(stage == MESA_SHADER_VERTEX); - return *static_cast(this->payload_); + return *static_cast(this->payload_); } - tcs_thread_payload &tcs_payload() { + elk_tcs_thread_payload &tcs_payload() { assert(stage == MESA_SHADER_TESS_CTRL); - return *static_cast(this->payload_); + return *static_cast(this->payload_); } - tes_thread_payload &tes_payload() { + elk_tes_thread_payload &tes_payload() { assert(stage == MESA_SHADER_TESS_EVAL); - return *static_cast(this->payload_); + return *static_cast(this->payload_); } - gs_thread_payload &gs_payload() { + elk_gs_thread_payload &gs_payload() { assert(stage == MESA_SHADER_GEOMETRY); - return *static_cast(this->payload_); + return *static_cast(this->payload_); } - fs_thread_payload &fs_payload() { + elk_fs_thread_payload &fs_payload() { assert(stage == MESA_SHADER_FRAGMENT); - return *static_cast(this->payload_); + return *static_cast(this->payload_); }; - cs_thread_payload &cs_payload() { + elk_cs_thread_payload &cs_payload() { assert(gl_shader_stage_uses_workgroup(stage)); - return *static_cast(this->payload_); + return *static_cast(this->payload_); } bool source_depth_to_render_target; bool runtime_check_aads_emit; - fs_reg pixel_x; - fs_reg pixel_y; - fs_reg pixel_z; - fs_reg wpos_w; - fs_reg pixel_w; - fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT]; - fs_reg final_gs_vertex_count; - fs_reg control_data_bits; - fs_reg invocation_id; + elk_fs_reg pixel_x; + elk_fs_reg pixel_y; + elk_fs_reg pixel_z; + elk_fs_reg wpos_w; + elk_fs_reg pixel_w; + elk_fs_reg delta_xy[ELK_BARYCENTRIC_MODE_COUNT]; + elk_fs_reg final_gs_vertex_count; + elk_fs_reg control_data_bits; + elk_fs_reg invocation_id; unsigned grf_used; bool spilled_any_registers; @@ -414,9 +414,9 @@ public: struct shader_stats shader_stats; - void lower_mul_dword_inst(fs_inst *inst, bblock_t *block); - void lower_mul_qword_inst(fs_inst *inst, bblock_t *block); - void lower_mulh_inst(fs_inst *inst, bblock_t *block); + void lower_mul_dword_inst(elk_fs_inst *inst, elk_bblock_t *block); + void lower_mul_qword_inst(elk_fs_inst *inst, elk_bblock_t *block); + void lower_mulh_inst(elk_fs_inst *inst, elk_bblock_t *block); unsigned workgroup_size() const; @@ -432,7 +432,7 @@ public: * limits the dispatch width to SIMD16 for fragment shaders that use discard. */ static inline unsigned -sample_mask_flag_subreg(const fs_visitor &s) +sample_mask_flag_subreg(const elk_fs_visitor &s) { assert(s.stage == MESA_SHADER_FRAGMENT); return s.devinfo->ver >= 7 ? 2 : 1; @@ -443,91 +443,91 @@ sample_mask_flag_subreg(const fs_visitor &s) * * Translates FS IR to actual i965 assembly code. */ -class fs_generator +class elk_fs_generator { public: - fs_generator(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - struct brw_stage_prog_data *prog_data, + elk_fs_generator(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + struct elk_stage_prog_data *prog_data, bool runtime_check_aads_emit, gl_shader_stage stage); - ~fs_generator(); + ~elk_fs_generator(); void enable_debug(const char *shader_name); - int generate_code(const cfg_t *cfg, int dispatch_width, + int generate_code(const elk_cfg_t *cfg, int dispatch_width, struct shader_stats shader_stats, const elk::performance &perf, - struct brw_compile_stats *stats, + struct elk_compile_stats *stats, unsigned max_polygons = 0); void add_const_data(void *data, unsigned size); const unsigned *get_assembly(); private: - void fire_fb_write(fs_inst *inst, - struct brw_reg payload, - struct brw_reg implied_header, + void fire_fb_write(elk_fs_inst *inst, + struct elk_reg payload, + struct elk_reg implied_header, GLuint nr); - void generate_send(fs_inst *inst, - struct brw_reg dst, - struct brw_reg desc, - struct brw_reg ex_desc, - struct brw_reg payload, - struct brw_reg payload2); - void generate_fb_write(fs_inst *inst, struct brw_reg payload); - void generate_fb_read(fs_inst *inst, struct brw_reg dst, - struct brw_reg payload); - void generate_cs_terminate(fs_inst *inst, struct brw_reg payload); - void generate_barrier(fs_inst *inst, struct brw_reg src); - bool generate_linterp(fs_inst *inst, struct brw_reg dst, - struct brw_reg *src); - void generate_tex(fs_inst *inst, struct brw_reg dst, - struct brw_reg surface_index, - struct brw_reg sampler_index); - void generate_ddx(const fs_inst *inst, - struct brw_reg dst, struct brw_reg src); - void generate_ddy(const fs_inst *inst, - struct brw_reg dst, struct brw_reg src); - void generate_scratch_write(fs_inst *inst, struct brw_reg src); - void generate_scratch_read(fs_inst *inst, struct brw_reg dst); - void generate_scratch_read_gfx7(fs_inst *inst, struct brw_reg dst); - void generate_scratch_header(fs_inst *inst, struct brw_reg dst); - void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst, - struct brw_reg index, - struct brw_reg offset); - void generate_varying_pull_constant_load_gfx4(fs_inst *inst, - struct brw_reg dst, - struct brw_reg index); + void generate_send(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg desc, + struct elk_reg ex_desc, + struct elk_reg payload, + struct elk_reg payload2); + void generate_fb_write(elk_fs_inst *inst, struct elk_reg payload); + void generate_fb_read(elk_fs_inst *inst, struct elk_reg dst, + struct elk_reg payload); + void generate_cs_terminate(elk_fs_inst *inst, struct elk_reg payload); + void generate_barrier(elk_fs_inst *inst, struct elk_reg src); + bool generate_linterp(elk_fs_inst *inst, struct elk_reg dst, + struct elk_reg *src); + void generate_tex(elk_fs_inst *inst, struct elk_reg dst, + struct elk_reg surface_index, + struct elk_reg sampler_index); + void generate_ddx(const elk_fs_inst *inst, + struct elk_reg dst, struct elk_reg src); + void generate_ddy(const elk_fs_inst *inst, + struct elk_reg dst, struct elk_reg src); + void generate_scratch_write(elk_fs_inst *inst, struct elk_reg src); + void generate_scratch_read(elk_fs_inst *inst, struct elk_reg dst); + void generate_scratch_read_gfx7(elk_fs_inst *inst, struct elk_reg dst); + void generate_scratch_header(elk_fs_inst *inst, struct elk_reg dst); + void generate_uniform_pull_constant_load(elk_fs_inst *inst, struct elk_reg dst, + struct elk_reg index, + struct elk_reg offset); + void generate_varying_pull_constant_load_gfx4(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg index); - void generate_set_sample_id(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1); + void generate_set_sample_id(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg src0, + struct elk_reg src1); - void generate_halt(fs_inst *inst); + void generate_halt(elk_fs_inst *inst); - void generate_mov_indirect(fs_inst *inst, - struct brw_reg dst, - struct brw_reg reg, - struct brw_reg indirect_byte_offset); + void generate_mov_indirect(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg reg, + struct elk_reg indirect_byte_offset); - void generate_shuffle(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg idx); + void generate_shuffle(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg src, + struct elk_reg idx); - void generate_quad_swizzle(const fs_inst *inst, - struct brw_reg dst, struct brw_reg src, + void generate_quad_swizzle(const elk_fs_inst *inst, + struct elk_reg dst, struct elk_reg src, unsigned swiz); bool patch_halt_jumps(); - const struct brw_compiler *compiler; - const struct brw_compile_params *params; + const struct elk_compiler *compiler; + const struct elk_compile_params *params; const struct intel_device_info *devinfo; - struct brw_codegen *p; - struct brw_stage_prog_data * const prog_data; + struct elk_codegen *p; + struct elk_stage_prog_data * const prog_data; unsigned dispatch_width; /**< 8, 16 or 32 */ @@ -540,62 +540,62 @@ private: }; namespace elk { - fs_reg + elk_fs_reg fetch_payload_reg(const elk::fs_builder &bld, uint8_t regs[2], - brw_reg_type type = BRW_REGISTER_TYPE_F, + elk_reg_type type = ELK_REGISTER_TYPE_F, unsigned n = 1); - fs_reg + elk_fs_reg fetch_barycentric_reg(const elk::fs_builder &bld, uint8_t regs[2]); - inline fs_reg - dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data) + inline elk_fs_reg + dynamic_msaa_flags(const struct elk_wm_prog_data *wm_prog_data) { - return fs_reg(UNIFORM, wm_prog_data->msaa_flags_param, - BRW_REGISTER_TYPE_UD); + return elk_fs_reg(UNIFORM, wm_prog_data->msaa_flags_param, + ELK_REGISTER_TYPE_UD); } void check_dynamic_msaa_flag(const fs_builder &bld, - const struct brw_wm_prog_data *wm_prog_data, + const struct elk_wm_prog_data *wm_prog_data, enum intel_msaa_flags flag); bool - lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i); + lower_src_modifiers(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst, unsigned i); } -void shuffle_from_32bit_read(const elk::fs_builder &bld, - const fs_reg &dst, - const fs_reg &src, +void elk_shuffle_from_32bit_read(const elk::fs_builder &bld, + const elk_fs_reg &dst, + const elk_fs_reg &src, uint32_t first_component, uint32_t components); -fs_reg setup_imm_df(const elk::fs_builder &bld, +elk_fs_reg elk_setup_imm_df(const elk::fs_builder &bld, double v); -fs_reg setup_imm_b(const elk::fs_builder &bld, +elk_fs_reg elk_setup_imm_b(const elk::fs_builder &bld, int8_t v); -fs_reg setup_imm_ub(const elk::fs_builder &bld, +elk_fs_reg elk_setup_imm_ub(const elk::fs_builder &bld, uint8_t v); -enum brw_barycentric_mode brw_barycentric_mode(nir_intrinsic_instr *intr); +enum elk_barycentric_mode elk_barycentric_mode(nir_intrinsic_instr *intr); -uint32_t brw_fb_write_msg_control(const fs_inst *inst, - const struct brw_wm_prog_data *prog_data); +uint32_t elk_fb_write_msg_control(const elk_fs_inst *inst, + const struct elk_wm_prog_data *prog_data); -void brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data); +void elk_compute_urb_setup_index(struct elk_wm_prog_data *wm_prog_data); -bool brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width); +bool elk_nir_lower_simd(nir_shader *nir, unsigned dispatch_width); -fs_reg brw_sample_mask_reg(const elk::fs_builder &bld); -void brw_emit_predicate_on_sample_mask(const elk::fs_builder &bld, fs_inst *inst); +elk_fs_reg elk_sample_mask_reg(const elk::fs_builder &bld); +void elk_emit_predicate_on_sample_mask(const elk::fs_builder &bld, elk_fs_inst *inst); -int brw_get_subgroup_id_param_index(const intel_device_info *devinfo, - const brw_stage_prog_data *prog_data); +int elk_get_subgroup_id_param_index(const intel_device_info *devinfo, + const elk_stage_prog_data *prog_data); -bool brw_lower_dpas(fs_visitor &v); +bool elk_lower_dpas(elk_fs_visitor &v); -void nir_to_brw(fs_visitor *s); +void nir_to_elk(elk_fs_visitor *s); #endif /* ELK_FS_H */ diff --git a/src/intel/compiler/elk/elk_fs_bank_conflicts.cpp b/src/intel/compiler/elk/elk_fs_bank_conflicts.cpp index c539dd66da5..f10a2c3fdb1 100644 --- a/src/intel/compiler/elk/elk_fs_bank_conflicts.cpp +++ b/src/intel/compiler/elk/elk_fs_bank_conflicts.cpp @@ -480,7 +480,7 @@ namespace { * possibly incur bank conflicts. */ bool - is_grf(const fs_reg &r) + is_grf(const elk_fs_reg &r) { return r.file == VGRF || r.file == FIXED_GRF; } @@ -492,7 +492,7 @@ namespace { * allocation or whether it was part of a VGRF allocation. */ unsigned - reg_of(const fs_reg &r) + reg_of(const elk_fs_reg &r) { assert(is_grf(r)); if (r.file == VGRF) @@ -507,11 +507,11 @@ namespace { * the program. */ partitioning - shader_reg_partitioning(const fs_visitor *v) + shader_reg_partitioning(const elk_fs_visitor *v) { - partitioning p(BRW_MAX_GRF); + partitioning p(ELK_MAX_GRF); - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) { if (is_grf(inst->dst)) p.require_contiguous(reg_of(inst->dst), regs_written(inst)); @@ -529,7 +529,7 @@ namespace { * original location to avoid violating hardware or software assumptions. */ bool * - shader_reg_constraints(const fs_visitor *v, const partitioning &p) + shader_reg_constraints(const elk_fs_visitor *v, const partitioning &p) { bool *constrained = new bool[p.num_atoms()](); @@ -552,7 +552,7 @@ namespace { if (v->devinfo->ver >= 8) constrained[p.atom_of_reg(127)] = true; - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) { /* Assume that anything referenced via fixed GRFs is baked into the * hardware's fixed-function logic and may be unsafe to move around. * Also take into account the source GRF restrictions of EOT @@ -572,7 +572,7 @@ namespace { * barycentrics allow the PLN instruction to be used. */ if (v->devinfo->has_pln && v->devinfo->ver <= 6 && - inst->opcode == FS_OPCODE_LINTERP) + inst->opcode == ELK_FS_OPCODE_LINTERP) constrained[p.atom_of_reg(reg_of(inst->src[0]))] = true; /* The location of the Gfx7 MRF hack registers is hard-coded in the @@ -598,7 +598,7 @@ namespace { */ bool is_conflict_optimized_out(const intel_device_info *devinfo, - const fs_inst *inst) + const elk_fs_inst *inst) { return devinfo->ver >= 9 && ((is_grf(inst->src[0]) && (reg_of(inst->src[0]) == reg_of(inst->src[1]) || @@ -627,7 +627,7 @@ namespace { * helpful than not optimizing at all. */ weight_vector_type * - shader_conflict_weight_matrix(const fs_visitor *v, const partitioning &p) + shader_conflict_weight_matrix(const elk_fs_visitor *v, const partitioning &p) { weight_vector_type *conflicts = new weight_vector_type[p.num_atoms()]; for (unsigned r = 0; r < p.num_atoms(); r++) @@ -638,14 +638,14 @@ namespace { */ unsigned block_scale = 1; - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { - if (inst->opcode == BRW_OPCODE_DO) { + foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) { + if (inst->opcode == ELK_OPCODE_DO) { block_scale *= 10; - } else if (inst->opcode == BRW_OPCODE_WHILE) { + } else if (inst->opcode == ELK_OPCODE_WHILE) { block_scale /= 10; - } else if (inst->is_3src(v->compiler) && + } else if (inst->elk_is_3src(v->compiler) && is_grf(inst->src[1]) && is_grf(inst->src[2])) { const unsigned r = p.atom_of_reg(reg_of(inst->src[1])); const unsigned s = p.atom_of_reg(reg_of(inst->src[2])); @@ -892,8 +892,8 @@ namespace { * Apply the GRF atom permutation given by \p map to register \p r and * return the result. */ - fs_reg - transform(const partitioning &p, const permutation &map, fs_reg r) + elk_fs_reg + transform(const partitioning &p, const permutation &map, elk_fs_reg r) { if (r.file == VGRF) { const unsigned reg = reg_of(r); @@ -907,7 +907,7 @@ namespace { } bool -fs_visitor::opt_bank_conflicts() +elk_fs_visitor::opt_bank_conflicts() { assert(grf_used || !"Must be called after register allocation"); @@ -927,7 +927,7 @@ fs_visitor::opt_bank_conflicts() optimize_reg_permutation(p, constrained, conflicts, identity_reg_permutation(p)); - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { inst->dst = transform(p, map, inst->dst); for (int i = 0; i < inst->sources; i++) @@ -946,9 +946,9 @@ fs_visitor::opt_bank_conflicts() * we don't know which bank each VGRF is going to end up aligned to. */ bool -has_bank_conflict(const struct brw_isa_info *isa, const fs_inst *inst) +elk_has_bank_conflict(const struct elk_isa_info *isa, const elk_fs_inst *inst) { - return is_3src(isa, inst->opcode) && + return elk_is_3src(isa, inst->opcode) && is_grf(inst->src[1]) && is_grf(inst->src[2]) && bank_of(reg_of(inst->src[1])) == bank_of(reg_of(inst->src[2])) && !is_conflict_optimized_out(isa->devinfo, inst); diff --git a/src/intel/compiler/elk/elk_fs_builder.h b/src/intel/compiler/elk/elk_fs_builder.h index bbaaab5d0d8..a457d6d6a63 100644 --- a/src/intel/compiler/elk/elk_fs_builder.h +++ b/src/intel/compiler/elk/elk_fs_builder.h @@ -42,19 +42,19 @@ namespace elk { class fs_builder { public: /** Type used in this IR to represent a source of an instruction. */ - typedef fs_reg src_reg; + typedef elk_fs_reg src_reg; /** Type used in this IR to represent the destination of an instruction. */ - typedef fs_reg dst_reg; + typedef elk_fs_reg dst_reg; /** Type used in this IR to represent an instruction. */ - typedef fs_inst instruction; + typedef elk_fs_inst instruction; /** * Construct an fs_builder that inserts instructions into \p shader. * \p dispatch_width gives the native execution width of the program. */ - fs_builder(fs_visitor *shader, + fs_builder(elk_fs_visitor *shader, unsigned dispatch_width) : shader(shader), block(NULL), cursor(NULL), _dispatch_width(dispatch_width), @@ -64,7 +64,7 @@ namespace elk { { } - explicit fs_builder(fs_visitor *s) : fs_builder(s, s->dispatch_width) {} + explicit fs_builder(elk_fs_visitor *s) : fs_builder(s, s->dispatch_width) {} /** * Construct an fs_builder that inserts instructions into \p shader @@ -72,7 +72,7 @@ namespace elk { * execution controls and debug annotation are initialized from the * instruction passed as argument. */ - fs_builder(fs_visitor *shader, bblock_t *block, fs_inst *inst) : + fs_builder(elk_fs_visitor *shader, elk_bblock_t *block, elk_fs_inst *inst) : shader(shader), block(block), cursor(inst), _dispatch_width(inst->exec_size), _group(inst->group), @@ -88,7 +88,7 @@ namespace elk { * from this. */ fs_builder - at(bblock_t *block, exec_node *cursor) const + at(elk_bblock_t *block, exec_node *cursor) const { fs_builder bld = *this; bld.block = block; @@ -200,7 +200,7 @@ namespace elk { * component in this IR). */ dst_reg - vgrf(enum brw_reg_type type, unsigned n = 1) const + vgrf(enum elk_reg_type type, unsigned n = 1) const { const unsigned unit = reg_unit(shader->devinfo); assert(dispatch_width() <= 32); @@ -220,13 +220,13 @@ namespace elk { dst_reg null_reg_f() const { - return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_F)); + return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_F)); } dst_reg null_reg_df() const { - return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF)); + return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_DF)); } /** @@ -235,7 +235,7 @@ namespace elk { dst_reg null_reg_d() const { - return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); } /** @@ -244,7 +244,7 @@ namespace elk { dst_reg null_reg_ud() const { - return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); + return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD)); } /** @@ -260,7 +260,7 @@ namespace elk { * Create and insert a nullary control instruction into the program. */ instruction * - emit(enum opcode opcode) const + emit(enum elk_opcode opcode) const { return emit(instruction(opcode, dispatch_width())); } @@ -269,7 +269,7 @@ namespace elk { * Create and insert a nullary instruction into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst) const + emit(enum elk_opcode opcode, const dst_reg &dst) const { return emit(instruction(opcode, dispatch_width(), dst)); } @@ -278,16 +278,16 @@ namespace elk { * Create and insert a unary instruction into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const + emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0) const { switch (opcode) { - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: return emit(instruction(opcode, dispatch_width(), dst, fix_math_operand(src0))); @@ -300,13 +300,13 @@ namespace elk { * Create and insert a binary instruction into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, + emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1) const { switch (opcode) { - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: return emit(instruction(opcode, dispatch_width(), dst, fix_math_operand(src0), fix_math_operand(src1))); @@ -322,14 +322,14 @@ namespace elk { * Create and insert a ternary instruction into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, + emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) const { switch (opcode) { - case BRW_OPCODE_BFE: - case BRW_OPCODE_BFI2: - case BRW_OPCODE_MAD: - case BRW_OPCODE_LRP: + case ELK_OPCODE_BFE: + case ELK_OPCODE_BFI2: + case ELK_OPCODE_MAD: + case ELK_OPCODE_LRP: return emit(instruction(opcode, dispatch_width(), dst, fix_3src_operand(src0), fix_3src_operand(src1), @@ -346,7 +346,7 @@ namespace elk { * into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst, const src_reg srcs[], + emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg srcs[], unsigned n) const { /* Use the emit() methods for specific operand counts to ensure that @@ -392,9 +392,9 @@ namespace elk { */ instruction * emit_minmax(const dst_reg &dst, const src_reg &src0, - const src_reg &src1, brw_conditional_mod mod) const + const src_reg &src1, elk_conditional_mod mod) const { - assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L); + assert(mod == ELK_CONDITIONAL_GE || mod == ELK_CONDITIONAL_L); /* In some cases we can't have bytes as operand for src1, so use the * same type for both operand. @@ -417,11 +417,11 @@ namespace elk { * should go back to scalar destinations here. */ const fs_builder ubld = exec_all(); - const dst_reg chan_index = vgrf(BRW_REGISTER_TYPE_UD); + const dst_reg chan_index = vgrf(ELK_REGISTER_TYPE_UD); const dst_reg dst = vgrf(src.type); - ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index); - ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0)); + ubld.emit(ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index); + ubld.emit(ELK_SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0)); return src_reg(component(dst, 0)); } @@ -442,7 +442,7 @@ namespace elk { } void - emit_scan_step(enum opcode opcode, brw_conditional_mod mod, + emit_scan_step(enum elk_opcode opcode, elk_conditional_mod mod, const dst_reg &tmp, unsigned left_offset, unsigned left_stride, unsigned right_offset, unsigned right_stride) const @@ -450,31 +450,31 @@ namespace elk { dst_reg left, right; left = horiz_stride(horiz_offset(tmp, left_offset), left_stride); right = horiz_stride(horiz_offset(tmp, right_offset), right_stride); - if ((tmp.type == BRW_REGISTER_TYPE_Q || - tmp.type == BRW_REGISTER_TYPE_UQ) && + if ((tmp.type == ELK_REGISTER_TYPE_Q || + tmp.type == ELK_REGISTER_TYPE_UQ) && !shader->devinfo->has_64bit_int) { switch (opcode) { - case BRW_OPCODE_MUL: + case ELK_OPCODE_MUL: /* This will get lowered by integer MUL lowering */ set_condmod(mod, emit(opcode, right, left, right)); break; - case BRW_OPCODE_SEL: { + case ELK_OPCODE_SEL: { /* In order for the comparisons to work out right, we need our * comparisons to be strict. */ - assert(mod == BRW_CONDITIONAL_L || mod == BRW_CONDITIONAL_GE); - if (mod == BRW_CONDITIONAL_GE) - mod = BRW_CONDITIONAL_G; + assert(mod == ELK_CONDITIONAL_L || mod == ELK_CONDITIONAL_GE); + if (mod == ELK_CONDITIONAL_GE) + mod = ELK_CONDITIONAL_G; /* We treat the bottom 32 bits as unsigned regardless of * whether or not the integer as a whole is signed. */ - dst_reg right_low = subscript(right, BRW_REGISTER_TYPE_UD, 0); - dst_reg left_low = subscript(left, BRW_REGISTER_TYPE_UD, 0); + dst_reg right_low = subscript(right, ELK_REGISTER_TYPE_UD, 0); + dst_reg left_low = subscript(left, ELK_REGISTER_TYPE_UD, 0); /* The upper bits get the same sign as the 64-bit type */ - brw_reg_type type32 = brw_reg_type_from_bit_size(32, tmp.type); + elk_reg_type type32 = elk_reg_type_from_bit_size(32, tmp.type); dst_reg right_high = subscript(right, type32, 1); dst_reg left_high = subscript(left, type32, 1); @@ -482,20 +482,20 @@ namespace elk { * * l_hi < r_hi || (l_hi == r_hi && l_low < r_low) */ - CMP(null_reg_ud(), retype(left_low, BRW_REGISTER_TYPE_UD), - retype(right_low, BRW_REGISTER_TYPE_UD), mod); - set_predicate(BRW_PREDICATE_NORMAL, + CMP(null_reg_ud(), retype(left_low, ELK_REGISTER_TYPE_UD), + retype(right_low, ELK_REGISTER_TYPE_UD), mod); + set_predicate(ELK_PREDICATE_NORMAL, CMP(null_reg_ud(), left_high, right_high, - BRW_CONDITIONAL_EQ)); - set_predicate_inv(BRW_PREDICATE_NORMAL, true, + ELK_CONDITIONAL_EQ)); + set_predicate_inv(ELK_PREDICATE_NORMAL, true, CMP(null_reg_ud(), left_high, right_high, mod)); /* We could use selects here or we could use predicated MOVs * because the destination and second source (if it were a SEL) * are the same. */ - set_predicate(BRW_PREDICATE_NORMAL, MOV(right_low, left_low)); - set_predicate(BRW_PREDICATE_NORMAL, MOV(right_high, left_high)); + set_predicate(ELK_PREDICATE_NORMAL, MOV(right_low, left_low)); + set_predicate(ELK_PREDICATE_NORMAL, MOV(right_high, left_high)); break; } @@ -508,8 +508,8 @@ namespace elk { } void - emit_scan(enum opcode opcode, const dst_reg &tmp, - unsigned cluster_size, brw_conditional_mod mod) const + emit_scan(enum elk_opcode opcode, const dst_reg &tmp, + unsigned cluster_size, elk_conditional_mod mod) const { assert(dispatch_width() >= 8); @@ -574,8 +574,8 @@ namespace elk { emit_undef_for_dst(const instruction *old_inst) const { assert(old_inst->dst.file == VGRF); - instruction *inst = emit(SHADER_OPCODE_UNDEF, - retype(old_inst->dst, BRW_REGISTER_TYPE_UD)); + instruction *inst = emit(ELK_SHADER_OPCODE_UNDEF, + retype(old_inst->dst, ELK_REGISTER_TYPE_UD)); inst->size_written = old_inst->size_written; return inst; @@ -589,21 +589,21 @@ namespace elk { instruction * \ op(const dst_reg &dst, const src_reg &src0) const \ { \ - return emit(BRW_OPCODE_##op, dst, src0); \ + return emit(ELK_OPCODE_##op, dst, src0); \ } #define ALU2(op) \ instruction * \ op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \ { \ - return emit(BRW_OPCODE_##op, dst, src0, src1); \ + return emit(ELK_OPCODE_##op, dst, src0, src1); \ } #define ALU2_ACC(op) \ instruction * \ op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \ { \ - instruction *inst = emit(BRW_OPCODE_##op, dst, src0, src1); \ + instruction *inst = emit(ELK_OPCODE_##op, dst, src0, src1); \ inst->writes_accumulator = true; \ return inst; \ } @@ -613,7 +613,7 @@ namespace elk { op(const dst_reg &dst, const src_reg &src0, const src_reg &src1, \ const src_reg &src2) const \ { \ - return emit(BRW_OPCODE_##op, dst, src0, src1, src2); \ + return emit(ELK_OPCODE_##op, dst, src0, src1, src2); \ } ALU2(ADD) @@ -668,30 +668,30 @@ namespace elk { instruction * F32TO16(const dst_reg &dst, const src_reg &src) const { - assert(dst.type == BRW_REGISTER_TYPE_HF); - assert(src.type == BRW_REGISTER_TYPE_F); + assert(dst.type == ELK_REGISTER_TYPE_HF); + assert(src.type == ELK_REGISTER_TYPE_F); if (shader->devinfo->ver >= 8) { return MOV(dst, src); } else { assert(shader->devinfo->ver == 7); - return emit(BRW_OPCODE_F32TO16, - retype(dst, BRW_REGISTER_TYPE_W), src); + return emit(ELK_OPCODE_F32TO16, + retype(dst, ELK_REGISTER_TYPE_W), src); } } instruction * F16TO32(const dst_reg &dst, const src_reg &src) const { - assert(dst.type == BRW_REGISTER_TYPE_F); - assert(src.type == BRW_REGISTER_TYPE_HF); + assert(dst.type == ELK_REGISTER_TYPE_F); + assert(src.type == ELK_REGISTER_TYPE_HF); if (shader->devinfo->ver >= 8) { return MOV(dst, src); } else { assert(shader->devinfo->ver == 7); - return emit(BRW_OPCODE_F16TO32, - dst, retype(src, BRW_REGISTER_TYPE_W)); + return emit(ELK_OPCODE_F16TO32, + dst, retype(src, ELK_REGISTER_TYPE_W)); } } /** @} */ @@ -703,7 +703,7 @@ namespace elk { */ instruction * CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, - brw_conditional_mod condition) const + elk_conditional_mod condition) const { /* Take the instruction: * @@ -718,7 +718,7 @@ namespace elk { * instruction. */ return set_condmod(condition, - emit(BRW_OPCODE_CMP, retype(dst, src0.type), + emit(ELK_OPCODE_CMP, retype(dst, src0.type), fix_unsigned_negate(src0), fix_unsigned_negate(src1))); } @@ -728,7 +728,7 @@ namespace elk { */ instruction * CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, - brw_conditional_mod condition) const + elk_conditional_mod condition) const { /* Take the instruction: * @@ -743,7 +743,7 @@ namespace elk { * instruction. */ return set_condmod(condition, - emit(BRW_OPCODE_CMPN, retype(dst, src0.type), + emit(ELK_OPCODE_CMPN, retype(dst, src0.type), fix_unsigned_negate(src0), fix_unsigned_negate(src1))); } @@ -752,9 +752,9 @@ namespace elk { * Gfx4 predicated IF. */ instruction * - IF(brw_predicate predicate) const + IF(elk_predicate predicate) const { - return set_predicate(predicate, emit(BRW_OPCODE_IF)); + return set_predicate(predicate, emit(ELK_OPCODE_IF)); } /** @@ -762,19 +762,19 @@ namespace elk { */ instruction * CSEL(const dst_reg &dst, const src_reg &src0, const src_reg &src1, - const src_reg &src2, brw_conditional_mod condition) const + const src_reg &src2, elk_conditional_mod condition) const { /* CSEL only operates on floats, so we can't do integer =/> * comparisons. Zero/non-zero (== and !=) comparisons almost work. * 0x80000000 fails because it is -0.0, and -0.0 == 0.0. */ - assert(src2.type == BRW_REGISTER_TYPE_F); + assert(src2.type == ELK_REGISTER_TYPE_F); return set_condmod(condition, - emit(BRW_OPCODE_CSEL, - retype(dst, BRW_REGISTER_TYPE_F), - retype(src0, BRW_REGISTER_TYPE_F), - retype(src1, BRW_REGISTER_TYPE_F), + emit(ELK_OPCODE_CSEL, + retype(dst, ELK_REGISTER_TYPE_F), + retype(src0, ELK_REGISTER_TYPE_F), + retype(src1, ELK_REGISTER_TYPE_F), src2)); } @@ -789,7 +789,7 @@ namespace elk { /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so * we need to reorder the operands. */ - return emit(BRW_OPCODE_LRP, dst, a, y, x); + return emit(ELK_OPCODE_LRP, dst, a, y, x); } else { /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */ @@ -798,7 +798,7 @@ namespace elk { const dst_reg x_times_one_minus_a = vgrf(dst.type); MUL(y_times_a, y, a); - ADD(one_minus_a, negate(a), brw_imm_f(1.0f)); + ADD(one_minus_a, negate(a), elk_imm_f(1.0f)); MUL(x_times_one_minus_a, x, src_reg(one_minus_a)); return ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a)); } @@ -811,7 +811,7 @@ namespace elk { LOAD_PAYLOAD(const dst_reg &dst, const src_reg *src, unsigned sources, unsigned header_size) const { - instruction *inst = emit(SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources); + instruction *inst = emit(ELK_SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources); inst->header_size = header_size; inst->size_written = header_size * REG_SIZE; for (unsigned i = header_size; i < sources; i++) { @@ -827,8 +827,8 @@ namespace elk { { assert(dst.file == VGRF); assert(dst.offset % REG_SIZE == 0); - instruction *inst = emit(SHADER_OPCODE_UNDEF, - retype(dst, BRW_REGISTER_TYPE_UD)); + instruction *inst = emit(ELK_SHADER_OPCODE_UNDEF, + retype(dst, ELK_REGISTER_TYPE_UD)); inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE - dst.offset; return inst; @@ -842,11 +842,11 @@ namespace elk { assert(sdepth == 8); assert(rcount == 1 || rcount == 2 || rcount == 4 || rcount == 8); - instruction *inst = emit(BRW_OPCODE_DPAS, dst, src0, src1, src2); + instruction *inst = emit(ELK_OPCODE_DPAS, dst, src0, src1, src2); inst->sdepth = sdepth; inst->rcount = rcount; - if (dst.type == BRW_REGISTER_TYPE_HF) { + if (dst.type == ELK_REGISTER_TYPE_HF) { inst->size_written = rcount * REG_SIZE / 2; } else { inst->size_written = rcount * REG_SIZE; @@ -855,26 +855,26 @@ namespace elk { return inst; } - fs_visitor *shader; + elk_fs_visitor *shader; - fs_inst *BREAK() { return emit(BRW_OPCODE_BREAK); } - fs_inst *DO() { return emit(BRW_OPCODE_DO); } - fs_inst *ENDIF() { return emit(BRW_OPCODE_ENDIF); } - fs_inst *NOP() { return emit(BRW_OPCODE_NOP); } - fs_inst *WHILE() { return emit(BRW_OPCODE_WHILE); } - fs_inst *CONTINUE() { return emit(BRW_OPCODE_CONTINUE); } + elk_fs_inst *BREAK() { return emit(ELK_OPCODE_BREAK); } + elk_fs_inst *DO() { return emit(ELK_OPCODE_DO); } + elk_fs_inst *ENDIF() { return emit(ELK_OPCODE_ENDIF); } + elk_fs_inst *NOP() { return emit(ELK_OPCODE_NOP); } + elk_fs_inst *WHILE() { return emit(ELK_OPCODE_WHILE); } + elk_fs_inst *CONTINUE() { return emit(ELK_OPCODE_CONTINUE); } private: /** * Workaround for negation of UD registers. See comment in - * fs_generator::generate_code() for more details. + * elk_fs_generator::generate_code() for more details. */ src_reg fix_unsigned_negate(const src_reg &src) const { - if (src.type == BRW_REGISTER_TYPE_UD && + if (src.type == ELK_REGISTER_TYPE_UD && src.negate) { - dst_reg temp = vgrf(BRW_REGISTER_TYPE_UD); + dst_reg temp = vgrf(ELK_REGISTER_TYPE_UD); MOV(temp, src); return src_reg(temp); } else { @@ -892,9 +892,9 @@ namespace elk { switch (src.file) { case FIXED_GRF: /* FINISHME: Could handle scalar region, other stride=1 regions */ - if (src.vstride != BRW_VERTICAL_STRIDE_8 || - src.width != BRW_WIDTH_8 || - src.hstride != BRW_HORIZONTAL_STRIDE_1) + if (src.vstride != ELK_VERTICAL_STRIDE_8 || + src.width != ELK_WIDTH_8 || + src.hstride != ELK_HORIZONTAL_STRIDE_1) break; FALLTHROUGH; case ATTR: @@ -941,7 +941,7 @@ namespace elk { } } - bblock_t *block; + elk_bblock_t *block; exec_node *cursor; unsigned _dispatch_width; @@ -956,8 +956,8 @@ namespace elk { }; } -static inline fs_reg -offset(const fs_reg ®, const elk::fs_builder &bld, unsigned delta) +static inline elk_fs_reg +offset(const elk_fs_reg ®, const elk::fs_builder &bld, unsigned delta) { return offset(reg, bld.dispatch_width(), delta); } diff --git a/src/intel/compiler/elk/elk_fs_cmod_propagation.cpp b/src/intel/compiler/elk/elk_fs_cmod_propagation.cpp index deab933acd8..57a25141ebf 100644 --- a/src/intel/compiler/elk/elk_fs_cmod_propagation.cpp +++ b/src/intel/compiler/elk/elk_fs_cmod_propagation.cpp @@ -51,14 +51,14 @@ using namespace elk; static bool -cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block, - fs_inst *inst) +cmod_propagate_cmp_to_add(const intel_device_info *devinfo, elk_bblock_t *block, + elk_fs_inst *inst) { bool read_flag = false; const unsigned flags_written = inst->flags_written(devinfo); - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { - if (scan_inst->opcode == BRW_OPCODE_ADD && + foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) { + if (scan_inst->opcode == ELK_OPCODE_ADD && !scan_inst->is_partial_write() && scan_inst->exec_size == inst->exec_size) { bool negate; @@ -119,20 +119,20 @@ cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block, * (sat(x) > 0) == (x > 0) --- false * (sat(x) <= 0) == (x <= 0) --- true */ - const enum brw_conditional_mod cond = - negate ? brw_swap_cmod(inst->conditional_mod) + const enum elk_conditional_mod cond = + negate ? elk_swap_cmod(inst->conditional_mod) : inst->conditional_mod; if (scan_inst->saturate && - (brw_reg_type_is_floating_point(scan_inst->dst.type) || - brw_reg_type_is_unsigned_integer(scan_inst->dst.type)) && - (cond != BRW_CONDITIONAL_G && - cond != BRW_CONDITIONAL_LE)) + (elk_reg_type_is_floating_point(scan_inst->dst.type) || + elk_reg_type_is_unsigned_integer(scan_inst->dst.type)) && + (cond != ELK_CONDITIONAL_G && + cond != ELK_CONDITIONAL_LE)) goto not_match; /* Otherwise, try propagating the conditional. */ if (scan_inst->can_do_cmod() && - ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) || + ((!read_flag && scan_inst->conditional_mod == ELK_CONDITIONAL_NONE) || scan_inst->conditional_mod == cond)) { scan_inst->conditional_mod = cond; scan_inst->flag_subreg = inst->flag_subreg; @@ -167,21 +167,21 @@ cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block, * or.z.f0(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD */ static bool -cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block, - fs_inst *inst) +cmod_propagate_not(const intel_device_info *devinfo, elk_bblock_t *block, + elk_fs_inst *inst) { - const enum brw_conditional_mod cond = brw_negate_cmod(inst->conditional_mod); + const enum elk_conditional_mod cond = elk_negate_cmod(inst->conditional_mod); bool read_flag = false; const unsigned flags_written = inst->flags_written(devinfo); - if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ) + if (cond != ELK_CONDITIONAL_Z && cond != ELK_CONDITIONAL_NZ) return false; - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) { if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) { - if (scan_inst->opcode != BRW_OPCODE_OR && - scan_inst->opcode != BRW_OPCODE_AND) + if (scan_inst->opcode != ELK_OPCODE_OR && + scan_inst->opcode != ELK_OPCODE_AND) break; if (scan_inst->is_partial_write() || @@ -201,7 +201,7 @@ cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block, break; if (scan_inst->can_do_cmod() && - ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) || + ((!read_flag && scan_inst->conditional_mod == ELK_CONDITIONAL_NONE) || scan_inst->conditional_mod == cond)) { scan_inst->conditional_mod = cond; scan_inst->flag_subreg = inst->flag_subreg; @@ -222,19 +222,19 @@ cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block, } static bool -opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) +opt_cmod_propagation_local(const intel_device_info *devinfo, elk_bblock_t *block) { bool progress = false; UNUSED int ip = block->end_ip + 1; - foreach_inst_in_block_reverse_safe(fs_inst, inst, block) { + foreach_inst_in_block_reverse_safe(elk_fs_inst, inst, block) { ip--; - if ((inst->opcode != BRW_OPCODE_AND && - inst->opcode != BRW_OPCODE_CMP && - inst->opcode != BRW_OPCODE_MOV && - inst->opcode != BRW_OPCODE_NOT) || - inst->predicate != BRW_PREDICATE_NONE || + if ((inst->opcode != ELK_OPCODE_AND && + inst->opcode != ELK_OPCODE_CMP && + inst->opcode != ELK_OPCODE_MOV && + inst->opcode != ELK_OPCODE_NOT) || + inst->predicate != ELK_PREDICATE_NONE || !inst->dst.is_null() || (inst->src[0].file != VGRF && inst->src[0].file != ATTR && inst->src[0].file != UNIFORM)) @@ -244,19 +244,19 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) * with a value other than zero. */ if (inst->src[0].abs && - (inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero())) + (inst->opcode != ELK_OPCODE_CMP || inst->src[1].is_zero())) continue; /* Only an AND.NZ can be propagated. Many AND.Z instructions are - * generated (for ir_unop_not in fs_visitor::emit_bool_to_cond_code). + * generated (for ir_unop_not in elk_fs_visitor::emit_bool_to_cond_code). * Propagating those would require inverting the condition on the CMP. * This changes both the flag value and the register destination of the * CMP. That result may be used elsewhere, so we can't change its value * on a whim. */ - if (inst->opcode == BRW_OPCODE_AND && + if (inst->opcode == ELK_OPCODE_AND && !(inst->src[1].is_one() && - inst->conditional_mod == BRW_CONDITIONAL_NZ && + inst->conditional_mod == ELK_CONDITIONAL_NZ && !inst->src[0].negate)) continue; @@ -269,22 +269,22 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) * int(0x80000000) - 4 overflows and results in 0x7ffffffc. that's not * less than zero, so the flags get set differently than for (a < b). */ - if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) { - if (brw_reg_type_is_floating_point(inst->src[0].type) && + if (inst->opcode == ELK_OPCODE_CMP && !inst->src[1].is_zero()) { + if (elk_reg_type_is_floating_point(inst->src[0].type) && cmod_propagate_cmp_to_add(devinfo, block, inst)) progress = true; continue; } - if (inst->opcode == BRW_OPCODE_NOT) { + if (inst->opcode == ELK_OPCODE_NOT) { progress = cmod_propagate_not(devinfo, block, inst) || progress; continue; } bool read_flag = false; const unsigned flags_written = inst->flags_written(devinfo); - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) { if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) { /* If the scan instruction writes a different flag register than @@ -308,9 +308,9 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) break; /* CMP's result is the same regardless of dest type. */ - if (inst->conditional_mod == BRW_CONDITIONAL_NZ && - scan_inst->opcode == BRW_OPCODE_CMP && - brw_reg_type_is_integer(inst->dst.type)) { + if (inst->conditional_mod == ELK_CONDITIONAL_NZ && + scan_inst->opcode == ELK_OPCODE_CMP && + elk_reg_type_is_integer(inst->dst.type)) { inst->remove(block, true); progress = true; break; @@ -319,11 +319,11 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) /* If the AND wasn't handled by the previous case, it isn't safe * to remove it. */ - if (inst->opcode == BRW_OPCODE_AND) + if (inst->opcode == ELK_OPCODE_AND) break; - if (inst->opcode == BRW_OPCODE_MOV) { - if (brw_reg_type_is_floating_point(scan_inst->dst.type)) { + if (inst->opcode == ELK_OPCODE_MOV) { + if (elk_reg_type_is_floating_point(scan_inst->dst.type)) { /* If the destination type of scan_inst is floating-point, * then: * @@ -338,7 +338,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) if (scan_inst->dst.type != inst->src[0].type) break; - if (!brw_reg_type_is_floating_point(inst->dst.type)) + if (!elk_reg_type_is_floating_point(inst->dst.type)) break; if (type_sz(scan_inst->dst.type) > type_sz(inst->dst.type)) @@ -359,18 +359,18 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) * (of any size) or integer with a size at least as large * as the destination of inst and the same signedness. */ - if (!brw_reg_type_is_integer(inst->src[0].type) || + if (!elk_reg_type_is_integer(inst->src[0].type) || type_sz(scan_inst->dst.type) != type_sz(inst->src[0].type)) break; - if (brw_reg_type_is_integer(inst->dst.type)) { + if (elk_reg_type_is_integer(inst->dst.type)) { if (type_sz(inst->dst.type) < type_sz(scan_inst->dst.type)) break; - if (inst->conditional_mod != BRW_CONDITIONAL_Z && - inst->conditional_mod != BRW_CONDITIONAL_NZ && - brw_reg_type_is_unsigned_integer(inst->dst.type) != - brw_reg_type_is_unsigned_integer(scan_inst->dst.type)) + if (inst->conditional_mod != ELK_CONDITIONAL_Z && + inst->conditional_mod != ELK_CONDITIONAL_NZ && + elk_reg_type_is_unsigned_integer(inst->dst.type) != + elk_reg_type_is_unsigned_integer(scan_inst->dst.type)) break; } } @@ -379,8 +379,8 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) * different. */ if (scan_inst->dst.type != inst->src[0].type && - inst->conditional_mod != BRW_CONDITIONAL_Z && - inst->conditional_mod != BRW_CONDITIONAL_NZ) + inst->conditional_mod != ELK_CONDITIONAL_Z && + inst->conditional_mod != ELK_CONDITIONAL_NZ) break; /* Comparisons operate differently for ints and floats */ @@ -391,8 +391,8 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) if (type_sz(scan_inst->dst.type) != type_sz(inst->dst.type)) break; - if (brw_reg_type_is_floating_point(scan_inst->dst.type) != - brw_reg_type_is_floating_point(inst->dst.type)) + if (elk_reg_type_is_floating_point(scan_inst->dst.type) != + elk_reg_type_is_floating_point(inst->dst.type)) break; } } @@ -440,12 +440,12 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) */ if (!inst->src[0].negate && scan_inst->flags_written(devinfo)) { - if (scan_inst->opcode == BRW_OPCODE_CMP) { - if ((inst->conditional_mod == BRW_CONDITIONAL_NZ) || - (inst->conditional_mod == BRW_CONDITIONAL_G && - inst->src[0].type == BRW_REGISTER_TYPE_UD) || - (inst->conditional_mod == BRW_CONDITIONAL_L && - inst->src[0].type == BRW_REGISTER_TYPE_D)) { + if (scan_inst->opcode == ELK_OPCODE_CMP) { + if ((inst->conditional_mod == ELK_CONDITIONAL_NZ) || + (inst->conditional_mod == ELK_CONDITIONAL_G && + inst->src[0].type == ELK_REGISTER_TYPE_UD) || + (inst->conditional_mod == ELK_CONDITIONAL_L && + inst->src[0].type == ELK_REGISTER_TYPE_D)) { inst->remove(block, true); progress = true; break; @@ -456,7 +456,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) * destination. On all other platforms sel.cond will not * write the flags, so execution will not get to this point. */ - if (scan_inst->opcode == BRW_OPCODE_SEL) { + if (scan_inst->opcode == ELK_OPCODE_SEL) { assert(devinfo->ver <= 5); } else { inst->remove(block, true); @@ -481,8 +481,8 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) * different results because they are evaluated based on different * inputs. */ - if (scan_inst->opcode == BRW_OPCODE_CMP || - scan_inst->opcode == BRW_OPCODE_CMPN) + if (scan_inst->opcode == ELK_OPCODE_CMP || + scan_inst->opcode == ELK_OPCODE_CMPN) break; /* From the Sky Lake PRM, Vol 2a, "Multiply": @@ -498,12 +498,12 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) * * We just disallow cmod propagation on all integer multiplies. */ - if (!brw_reg_type_is_floating_point(scan_inst->dst.type) && - scan_inst->opcode == BRW_OPCODE_MUL) + if (!elk_reg_type_is_floating_point(scan_inst->dst.type) && + scan_inst->opcode == ELK_OPCODE_MUL) break; - enum brw_conditional_mod cond = - inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod) + enum elk_conditional_mod cond = + inst->src[0].negate ? elk_swap_cmod(inst->conditional_mod) : inst->conditional_mod; /* From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags": @@ -525,7 +525,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) /* Otherwise, try propagating the conditional. */ if (scan_inst->can_do_cmod() && - ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) || + ((!read_flag && scan_inst->conditional_mod == ELK_CONDITIONAL_NONE) || scan_inst->conditional_mod == cond)) { scan_inst->conditional_mod = cond; scan_inst->flag_subreg = inst->flag_subreg; @@ -550,7 +550,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) } bool -fs_visitor::opt_cmod_propagation() +elk_fs_visitor::opt_cmod_propagation() { bool progress = false; diff --git a/src/intel/compiler/elk/elk_fs_combine_constants.cpp b/src/intel/compiler/elk/elk_fs_combine_constants.cpp index a221dd7d9fe..b455989cbb7 100644 --- a/src/intel/compiler/elk/elk_fs_combine_constants.cpp +++ b/src/intel/compiler/elk/elk_fs_combine_constants.cpp @@ -62,7 +62,7 @@ struct value { /** * Which source of instr is this value? * - * \note This field is not actually used by \c brw_combine_constants, but + * \note This field is not actually used by \c elk_combine_constants, but * it is generally very useful to callers. */ uint8_t src; @@ -107,10 +107,10 @@ struct value { /** * \name UtilCombineConstantsPrivate - * Private data used only by brw_combine_constants + * Private data used only by elk_combine_constants * * Any data stored in these fields will be overwritten by the call to - * \c brw_combine_constants. No assumptions should be made about the + * \c elk_combine_constants. No assumptions should be made about the * state of these fields after that function returns. */ /**@{*/ @@ -156,7 +156,7 @@ struct combine_constants_value { }; struct combine_constants_user { - /** Index into the array of values passed to brw_combine_constants. */ + /** Index into the array of values passed to elk_combine_constants. */ unsigned index; /** @@ -757,7 +757,7 @@ combine_constants_greedy(struct value *candidates, unsigned num_candidates) } static combine_constants_result * -brw_combine_constants(struct value *candidates, unsigned num_candidates) +elk_combine_constants(struct value *candidates, unsigned num_candidates) { preprocess_candidates(candidates, num_candidates); @@ -768,12 +768,12 @@ brw_combine_constants(struct value *candidates, unsigned num_candidates) * replaced with a GRF source. */ static bool -could_coissue(const struct intel_device_info *devinfo, const fs_inst *inst) +could_coissue(const struct intel_device_info *devinfo, const elk_fs_inst *inst) { - assert(inst->opcode == BRW_OPCODE_MOV || - inst->opcode == BRW_OPCODE_CMP || - inst->opcode == BRW_OPCODE_ADD || - inst->opcode == BRW_OPCODE_MUL); + assert(inst->opcode == ELK_OPCODE_MOV || + inst->opcode == ELK_OPCODE_CMP || + inst->opcode == ELK_OPCODE_ADD || + inst->opcode == ELK_OPCODE_MUL); if (devinfo->ver != 7) return false; @@ -784,19 +784,19 @@ could_coissue(const struct intel_device_info *devinfo, const fs_inst *inst) * (based on the source types), so we take the conservative choice of * only promoting when both destination and source are float. */ - return inst->dst.type == BRW_REGISTER_TYPE_F && - inst->src[0].type == BRW_REGISTER_TYPE_F; + return inst->dst.type == ELK_REGISTER_TYPE_F && + inst->src[0].type == ELK_REGISTER_TYPE_F; } /** - * Box for storing fs_inst and some other necessary data + * Box for storing elk_fs_inst and some other necessary data * * \sa box_instruction */ struct fs_inst_box { - fs_inst *inst; + elk_fs_inst *inst; unsigned ip; - bblock_t *block; + elk_bblock_t *block; bool must_promote; }; @@ -804,18 +804,18 @@ struct fs_inst_box { struct reg_link { DECLARE_RALLOC_CXX_OPERATORS(reg_link) - reg_link(fs_inst *inst, unsigned src, bool negate, enum interpreted_type type) + reg_link(elk_fs_inst *inst, unsigned src, bool negate, enum interpreted_type type) : inst(inst), src(src), negate(negate), type(type) {} struct exec_node link; - fs_inst *inst; + elk_fs_inst *inst; uint8_t src; bool negate; enum interpreted_type type; }; static struct exec_node * -link(void *mem_ctx, fs_inst *inst, unsigned src, bool negate, +link(void *mem_ctx, elk_fs_inst *inst, unsigned src, bool negate, enum interpreted_type type) { reg_link *l = new(mem_ctx) reg_link(inst, src, negate, type); @@ -827,13 +827,13 @@ link(void *mem_ctx, fs_inst *inst, unsigned src, bool negate, */ struct imm { /** The common ancestor of all blocks using this immediate value. */ - bblock_t *block; + elk_bblock_t *block; /** * The instruction generating the immediate value, if all uses are contained * within a single basic block. Otherwise, NULL. */ - fs_inst *inst; + elk_fs_inst *inst; /** * A list of fs_regs that refer to this immediate. If we promote it, we'll @@ -908,8 +908,8 @@ new_value(struct table *table, void *mem_ctx) * \returns the index into the dynamic array of boxes for the instruction. */ static unsigned -box_instruction(struct table *table, void *mem_ctx, fs_inst *inst, - unsigned ip, bblock_t *block, bool must_promote) +box_instruction(struct table *table, void *mem_ctx, elk_fs_inst *inst, + unsigned ip, elk_bblock_t *block, bool must_promote) { /* It is common for box_instruction to be called consecutively for each * source of an instruction. As a result, the most common case for finding @@ -967,16 +967,16 @@ compare(const void *_a, const void *_b) return a->first_use_ip - b->first_use_ip; } -static struct brw_reg +static struct elk_reg build_imm_reg_for_copy(struct imm *imm) { switch (imm->size) { case 8: - return brw_imm_d(imm->d64); + return elk_imm_d(imm->d64); case 4: - return brw_imm_d(imm->d); + return elk_imm_d(imm->d); case 2: - return brw_imm_w(imm->w); + return elk_imm_w(imm->w); default: unreachable("not implemented"); } @@ -1030,22 +1030,22 @@ representable_as_uw(unsigned ud, uint16_t *uw) } static bool -supports_src_as_imm(const struct intel_device_info *devinfo, const fs_inst *inst) +supports_src_as_imm(const struct intel_device_info *devinfo, const elk_fs_inst *inst) { if (devinfo->ver < 12) return false; switch (inst->opcode) { - case BRW_OPCODE_ADD3: + case ELK_OPCODE_ADD3: /* ADD3 only exists on Gfx12.5+. */ return true; - case BRW_OPCODE_MAD: + case ELK_OPCODE_MAD: /* Integer types can always mix sizes. Floating point types can mix * sizes on Gfx12. On Gfx12.5, floating point sources must all be HF or * all be F. */ - return devinfo->verx10 < 125 || inst->src[0].type != BRW_REGISTER_TYPE_F; + return devinfo->verx10 < 125 || inst->src[0].type != ELK_REGISTER_TYPE_F; default: return false; @@ -1053,7 +1053,7 @@ supports_src_as_imm(const struct intel_device_info *devinfo, const fs_inst *inst } static bool -can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst, +can_promote_src_as_imm(const struct intel_device_info *devinfo, elk_fs_inst *inst, unsigned src_idx) { bool can_promote = false; @@ -1073,33 +1073,33 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst, * since HF/F mixed mode has been removed from the hardware. */ switch (inst->src[src_idx].type) { - case BRW_REGISTER_TYPE_F: { + case ELK_REGISTER_TYPE_F: { uint16_t hf; if (representable_as_hf(inst->src[src_idx].f, &hf)) { - inst->src[src_idx] = retype(brw_imm_uw(hf), BRW_REGISTER_TYPE_HF); + inst->src[src_idx] = retype(elk_imm_uw(hf), ELK_REGISTER_TYPE_HF); can_promote = true; } break; } - case BRW_REGISTER_TYPE_D: { + case ELK_REGISTER_TYPE_D: { int16_t w; if (representable_as_w(inst->src[src_idx].d, &w)) { - inst->src[src_idx] = brw_imm_w(w); + inst->src[src_idx] = elk_imm_w(w); can_promote = true; } break; } - case BRW_REGISTER_TYPE_UD: { + case ELK_REGISTER_TYPE_UD: { uint16_t uw; if (representable_as_uw(inst->src[src_idx].ud, &uw)) { - inst->src[src_idx] = brw_imm_uw(uw); + inst->src[src_idx] = elk_imm_uw(uw); can_promote = true; } break; } - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_HF: can_promote = true; break; default: @@ -1110,11 +1110,11 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst, } static void -add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip, +add_candidate_immediate(struct table *table, elk_fs_inst *inst, unsigned ip, unsigned i, bool must_promote, bool allow_one_constant, - bblock_t *block, + elk_bblock_t *block, const struct intel_device_info *devinfo, void *const_ctx) { @@ -1134,32 +1134,32 @@ add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip, * allow negations on a right shift if the source type is already signed. */ v->no_negations = !inst->can_do_source_mods(devinfo) || - ((inst->opcode == BRW_OPCODE_SHR || - inst->opcode == BRW_OPCODE_ASR) && - brw_reg_type_is_unsigned_integer(inst->src[i].type)); + ((inst->opcode == ELK_OPCODE_SHR || + inst->opcode == ELK_OPCODE_ASR) && + elk_reg_type_is_unsigned_integer(inst->src[i].type)); switch (inst->src[i].type) { - case BRW_REGISTER_TYPE_DF: - case BRW_REGISTER_TYPE_NF: - case BRW_REGISTER_TYPE_F: - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_HF: v->type = float_only; break; - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_Q: - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_W: v->type = integer_only; break; - case BRW_REGISTER_TYPE_VF: - case BRW_REGISTER_TYPE_UV: - case BRW_REGISTER_TYPE_V: - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_B: default: unreachable("not reached"); } @@ -1168,8 +1168,8 @@ add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip, * that has no conditional modifier, no source modifiers, and no saturate * modifer. */ - if (inst->opcode == BRW_OPCODE_SEL && - inst->conditional_mod == BRW_CONDITIONAL_NONE && + if (inst->opcode == ELK_OPCODE_SEL && + inst->conditional_mod == ELK_CONDITIONAL_NONE && !inst->src[0].negate && !inst->src[0].abs && !inst->src[1].negate && !inst->src[1].abs && !inst->saturate) { @@ -1190,7 +1190,7 @@ struct register_allocation { uint16_t avail; }; -static fs_reg +static elk_fs_reg allocate_slots(struct register_allocation *regs, unsigned num_regs, unsigned bytes, unsigned align_bytes, elk::simple_allocator &alloc) @@ -1212,7 +1212,7 @@ allocate_slots(struct register_allocation *regs, unsigned num_regs, regs[i].avail &= ~(mask << j); - fs_reg reg(VGRF, regs[i].nr); + elk_fs_reg reg(VGRF, regs[i].nr); reg.offset = j * 2; return reg; @@ -1246,7 +1246,7 @@ deallocate_slots(struct register_allocation *regs, unsigned num_regs, } static void -parcel_out_registers(struct imm *imm, unsigned len, const bblock_t *cur_block, +parcel_out_registers(struct imm *imm, unsigned len, const elk_bblock_t *cur_block, struct register_allocation *regs, unsigned num_regs, elk::simple_allocator &alloc, unsigned ver) { @@ -1283,7 +1283,7 @@ parcel_out_registers(struct imm *imm, unsigned len, const bblock_t *cur_block, */ const unsigned width = ver == 8 && imm[i].is_half_float ? 2 : 1; - const fs_reg reg = allocate_slots(regs, num_regs, + const elk_fs_reg reg = allocate_slots(regs, num_regs, imm[i].size * width, get_alignment_for_imm(&imm[i]), alloc); @@ -1305,7 +1305,7 @@ parcel_out_registers(struct imm *imm, unsigned len, const bblock_t *cur_block, } bool -fs_visitor::opt_combine_constants() +elk_fs_visitor::opt_combine_constants() { void *const_ctx = ralloc_context(NULL); @@ -1332,15 +1332,15 @@ fs_visitor::opt_combine_constants() * constant is used by coissueable instructions or instructions that cannot * take immediate arguments. */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { ip++; switch (inst->opcode) { - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: - case SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_POW: if (inst->src[0].file == IMM) { - assert(inst->opcode != SHADER_OPCODE_POW); + assert(inst->opcode != ELK_SHADER_OPCODE_POW); add_candidate_immediate(&table, inst, ip, 0, true, false, block, devinfo, const_ctx); @@ -1353,8 +1353,8 @@ fs_visitor::opt_combine_constants() break; - case BRW_OPCODE_ADD3: - case BRW_OPCODE_MAD: { + case ELK_OPCODE_ADD3: + case ELK_OPCODE_MAD: { for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file != IMM) continue; @@ -1369,9 +1369,9 @@ fs_visitor::opt_combine_constants() break; } - case BRW_OPCODE_BFE: - case BRW_OPCODE_BFI2: - case BRW_OPCODE_LRP: + case ELK_OPCODE_BFE: + case ELK_OPCODE_BFI2: + case ELK_OPCODE_LRP: for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file != IMM) continue; @@ -1382,16 +1382,16 @@ fs_visitor::opt_combine_constants() break; - case BRW_OPCODE_SEL: + case ELK_OPCODE_SEL: if (inst->src[0].file == IMM) { /* It is possible to have src0 be immediate but src1 not be * immediate for the non-commutative conditional modifiers (e.g., * G). */ - if (inst->conditional_mod == BRW_CONDITIONAL_NONE || + if (inst->conditional_mod == ELK_CONDITIONAL_NONE || /* Only GE and L are commutative. */ - inst->conditional_mod == BRW_CONDITIONAL_GE || - inst->conditional_mod == BRW_CONDITIONAL_L) { + inst->conditional_mod == ELK_CONDITIONAL_GE || + inst->conditional_mod == ELK_CONDITIONAL_L) { assert(inst->src[1].file == IMM); add_candidate_immediate(&table, inst, ip, 0, true, true, block, @@ -1405,28 +1405,28 @@ fs_visitor::opt_combine_constants() } break; - case BRW_OPCODE_ASR: - case BRW_OPCODE_BFI1: - case BRW_OPCODE_ROL: - case BRW_OPCODE_ROR: - case BRW_OPCODE_SHL: - case BRW_OPCODE_SHR: + case ELK_OPCODE_ASR: + case ELK_OPCODE_BFI1: + case ELK_OPCODE_ROL: + case ELK_OPCODE_ROR: + case ELK_OPCODE_SHL: + case ELK_OPCODE_SHR: if (inst->src[0].file == IMM) { add_candidate_immediate(&table, inst, ip, 0, true, false, block, devinfo, const_ctx); } break; - case BRW_OPCODE_MOV: + case ELK_OPCODE_MOV: if (could_coissue(devinfo, inst) && inst->src[0].file == IMM) { add_candidate_immediate(&table, inst, ip, 0, false, false, block, devinfo, const_ctx); } break; - case BRW_OPCODE_CMP: - case BRW_OPCODE_ADD: - case BRW_OPCODE_MUL: + case ELK_OPCODE_CMP: + case ELK_OPCODE_ADD: + case ELK_OPCODE_MUL: assert(inst->src[0].file != IMM); if (could_coissue(devinfo, inst) && inst->src[1].file == IMM) { @@ -1446,7 +1446,7 @@ fs_visitor::opt_combine_constants() } combine_constants_result *result = - brw_combine_constants(table.values, table.num_values); + elk_combine_constants(table.values, table.num_values); table.imm = ralloc_array(const_ctx, struct imm, result->num_values_to_emit); table.len = 0; @@ -1499,7 +1499,7 @@ fs_visitor::opt_combine_constants() imm->last_use_ip = ib->ip; imm->used_in_single_block = true; } else { - bblock_t *intersection = idom.intersect(ib->block, + elk_bblock_t *intersection = idom.intersect(ib->block, imm->block); if (ib->block != imm->block) @@ -1531,7 +1531,7 @@ fs_visitor::opt_combine_constants() imm->block = intersection; } - if (ib->inst->src[src].type == BRW_REGISTER_TYPE_HF) + if (ib->inst->src[src].type == ELK_REGISTER_TYPE_HF) imm->is_half_float = true; } @@ -1567,7 +1567,7 @@ fs_visitor::opt_combine_constants() free(regs); } else { - fs_reg reg(VGRF, alloc.allocate(1)); + elk_fs_reg reg(VGRF, alloc.allocate(1)); reg.stride = 0; for (int i = 0; i < table.len; i++) { @@ -1602,17 +1602,17 @@ fs_visitor::opt_combine_constants() * or after the last non-control flow instruction of the common ancestor. */ exec_node *n; - bblock_t *insert_block; + elk_bblock_t *insert_block; if (imm->inst != nullptr) { n = imm->inst; insert_block = imm->block; } else { - if (imm->block->start()->opcode == BRW_OPCODE_DO) { + if (imm->block->start()->opcode == ELK_OPCODE_DO) { /* DO blocks are weird. They can contain only the single DO * instruction. As a result, MOV instructions cannot be added to * the DO block. */ - bblock_t *next_block = imm->block->next(); + elk_bblock_t *next_block = imm->block->next(); if (next_block->starts_with_control_flow()) { /* This is the difficult case. This occurs for code like * @@ -1663,7 +1663,7 @@ fs_visitor::opt_combine_constants() const uint32_t width = devinfo->ver == 8 && imm->is_half_float ? 2 : 1; const fs_builder ibld = fs_builder(this, width).at(insert_block, n).exec_all(); - fs_reg reg(VGRF, imm->nr); + elk_fs_reg reg(VGRF, imm->nr); reg.offset = imm->subreg_offset; reg.stride = 0; @@ -1673,7 +1673,7 @@ fs_visitor::opt_combine_constants() */ assert(reg.offset == ALIGN(reg.offset, get_alignment_for_imm(imm))); - struct brw_reg imm_reg = build_imm_reg_for_copy(imm); + struct elk_reg imm_reg = build_imm_reg_for_copy(imm); /* Ensure we have enough space in the register to copy the immediate */ assert(reg.offset + type_sz(imm_reg.type) * width <= REG_SIZE); @@ -1685,70 +1685,70 @@ fs_visitor::opt_combine_constants() /* Rewrite the immediate sources to refer to the new GRFs. */ for (int i = 0; i < table.len; i++) { foreach_list_typed(reg_link, link, link, table.imm[i].uses) { - fs_reg *reg = &link->inst->src[link->src]; + elk_fs_reg *reg = &link->inst->src[link->src]; - if (link->inst->opcode == BRW_OPCODE_SEL) { + if (link->inst->opcode == ELK_OPCODE_SEL) { if (link->type == either_type) { /* Do not change the register type. */ } else if (link->type == integer_only) { - reg->type = brw_int_type(type_sz(reg->type), true); + reg->type = elk_int_type(type_sz(reg->type), true); } else { assert(link->type == float_only); switch (type_sz(reg->type)) { case 2: - reg->type = BRW_REGISTER_TYPE_HF; + reg->type = ELK_REGISTER_TYPE_HF; break; case 4: - reg->type = BRW_REGISTER_TYPE_F; + reg->type = ELK_REGISTER_TYPE_F; break; case 8: - reg->type = BRW_REGISTER_TYPE_DF; + reg->type = ELK_REGISTER_TYPE_DF; break; default: unreachable("Bad type size"); } } - } else if ((link->inst->opcode == BRW_OPCODE_SHL || - link->inst->opcode == BRW_OPCODE_ASR) && + } else if ((link->inst->opcode == ELK_OPCODE_SHL || + link->inst->opcode == ELK_OPCODE_ASR) && link->negate) { - reg->type = brw_int_type(type_sz(reg->type), true); + reg->type = elk_int_type(type_sz(reg->type), true); } #ifdef DEBUG switch (reg->type) { - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: assert((isnan(reg->df) && isnan(table.imm[i].df)) || (fabs(reg->df) == fabs(table.imm[i].df))); break; - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: assert((isnan(reg->f) && isnan(table.imm[i].f)) || (fabsf(reg->f) == fabsf(table.imm[i].f))); break; - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: assert((isnan(_mesa_half_to_float(reg->d & 0xffffu)) && isnan(_mesa_half_to_float(table.imm[i].w))) || (fabsf(_mesa_half_to_float(reg->d & 0xffffu)) == fabsf(_mesa_half_to_float(table.imm[i].w)))); break; - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_Q: assert(abs(reg->d64) == abs(table.imm[i].d64)); break; - case BRW_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_UQ: assert(!link->negate); assert(reg->d64 == table.imm[i].d64); break; - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_D: assert(abs(reg->d) == abs(table.imm[i].d)); break; - case BRW_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_UD: assert(!link->negate); assert(reg->d == table.imm[i].d); break; - case BRW_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_W: assert(abs((int16_t) (reg->d & 0xffff)) == table.imm[i].w); break; - case BRW_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_UW: assert(!link->negate); assert((reg->ud & 0xffffu) == (uint16_t) table.imm[i].w); break; @@ -1773,9 +1773,9 @@ fs_visitor::opt_combine_constants() * so the other source (and destination) must be changed to match. */ for (unsigned i = 0; i < table.num_boxes; i++) { - fs_inst *inst = table.boxes[i].inst; + elk_fs_inst *inst = table.boxes[i].inst; - if (inst->opcode != BRW_OPCODE_SEL) + if (inst->opcode != ELK_OPCODE_SEL) continue; /* If both sources have negation, the types had better be the same! */ @@ -1799,18 +1799,18 @@ fs_visitor::opt_combine_constants() continue; assert(inst->src[1].file != IMM); - assert(inst->conditional_mod == BRW_CONDITIONAL_NONE || - inst->conditional_mod == BRW_CONDITIONAL_GE || - inst->conditional_mod == BRW_CONDITIONAL_L); + assert(inst->conditional_mod == ELK_CONDITIONAL_NONE || + inst->conditional_mod == ELK_CONDITIONAL_GE || + inst->conditional_mod == ELK_CONDITIONAL_L); - fs_reg temp = inst->src[0]; + elk_fs_reg temp = inst->src[0]; inst->src[0] = inst->src[1]; inst->src[1] = temp; /* If this was predicated, flipping operands means we also need to flip * the predicate. */ - if (inst->conditional_mod == BRW_CONDITIONAL_NONE) + if (inst->conditional_mod == ELK_CONDITIONAL_NONE) inst->predicate_inverse = !inst->predicate_inverse; } @@ -1835,7 +1835,7 @@ fs_visitor::opt_combine_constants() if (rebuild_cfg) { /* When the CFG is initially built, the instructions are removed from - * the list of instructions stored in fs_visitor -- the same exec_node + * the list of instructions stored in elk_fs_visitor -- the same exec_node * is used for membership in that list and in a block list. So we need * to pull them back before rebuilding the CFG. */ diff --git a/src/intel/compiler/elk/elk_fs_copy_propagation.cpp b/src/intel/compiler/elk/elk_fs_copy_propagation.cpp index d1f8656cb32..2d6206cbbd2 100644 --- a/src/intel/compiler/elk/elk_fs_copy_propagation.cpp +++ b/src/intel/compiler/elk/elk_fs_copy_propagation.cpp @@ -46,12 +46,12 @@ namespace { /* avoid conflict with opt_copy_propagation_elements */ struct acp_entry { struct rb_node by_dst; struct rb_node by_src; - fs_reg dst; - fs_reg src; + elk_fs_reg dst; + elk_fs_reg src; unsigned global_idx; unsigned size_written; unsigned size_read; - enum opcode opcode; + enum elk_opcode opcode; bool is_partial_write; bool force_writemask_all; }; @@ -265,7 +265,7 @@ struct block_data { class fs_copy_prop_dataflow { public: - fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg, + fs_copy_prop_dataflow(linear_ctx *lin_ctx, elk_cfg_t *cfg, const fs_live_variables &live, struct acp *out_acp); @@ -274,7 +274,7 @@ public: void dump_block_data() const UNUSED; - cfg_t *cfg; + elk_cfg_t *cfg; const fs_live_variables &live; acp_entry **acp; @@ -285,7 +285,7 @@ public: }; } /* anonymous namespace */ -fs_copy_prop_dataflow::fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg, +fs_copy_prop_dataflow::fs_copy_prop_dataflow(linear_ctx *lin_ctx, elk_cfg_t *cfg, const fs_live_variables &live, struct acp *out_acp) : cfg(cfg), live(live) @@ -338,7 +338,7 @@ fs_copy_prop_dataflow::fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg, * Like reg_offset, but register must be VGRF or FIXED_GRF. */ static inline unsigned -grf_reg_offset(const fs_reg &r) +grf_reg_offset(const elk_fs_reg &r) { return (r.file == VGRF ? 0 : r.nr) * REG_SIZE + r.offset + @@ -349,7 +349,7 @@ grf_reg_offset(const fs_reg &r) * Like regions_overlap, but register must be VGRF or FIXED_GRF. */ static inline bool -grf_regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds) +grf_regions_overlap(const elk_fs_reg &r, unsigned dr, const elk_fs_reg &s, unsigned ds) { return reg_space(r) == reg_space(s) && !(grf_reg_offset(r) + dr <= grf_reg_offset(s) || @@ -374,7 +374,7 @@ fs_copy_prop_dataflow::setup_initial_values() acp_table.add(acp[i]); foreach_block (block, cfg) { - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(elk_fs_inst, inst, block) { if (inst->dst.file != VGRF && inst->dst.file != FIXED_GRF) continue; @@ -463,8 +463,8 @@ fs_copy_prop_dataflow::run() * parent blocks, it's live coming in to this block. */ bd[block->num].livein[i] = ~0u; - foreach_list_typed(bblock_link, parent_link, link, &block->parents) { - bblock_t *parent = parent_link->block; + foreach_list_typed(elk_bblock_link, parent_link, link, &block->parents) { + elk_bblock_t *parent = parent_link->block; /* Consider ACP entries with a known-undefined destination to * be available from the parent. This is valid because we're * free to set the undefined variable equal to the source of @@ -521,8 +521,8 @@ fs_copy_prop_dataflow::run() * inconsistent execution masking, the start of this block * is reachable by such an overwrite as well. */ - foreach_list_typed(bblock_link, parent_link, link, &block->parents) { - bblock_t *parent = parent_link->block; + foreach_list_typed(elk_bblock_link, parent_link, link, &block->parents) { + elk_bblock_t *parent = parent_link->block; bd[block->num].exec_mismatch[i] |= (bd[parent->num].exec_mismatch[i] & bd[parent->num].reachin[i]); } @@ -546,8 +546,8 @@ fs_copy_prop_dataflow::dump_block_data() const foreach_block (block, cfg) { fprintf(stderr, "Block %d [%d, %d] (parents ", block->num, block->start_ip, block->end_ip); - foreach_list_typed(bblock_link, link, link, &block->parents) { - bblock_t *parent = link->block; + foreach_list_typed(elk_bblock_link, link, link, &block->parents) { + elk_bblock_t *parent = link->block; fprintf(stderr, "%d ", parent->num); } fprintf(stderr, "):\n"); @@ -568,18 +568,18 @@ fs_copy_prop_dataflow::dump_block_data() const } static bool -is_logic_op(enum opcode opcode) +is_logic_op(enum elk_opcode opcode) { - return (opcode == BRW_OPCODE_AND || - opcode == BRW_OPCODE_OR || - opcode == BRW_OPCODE_XOR || - opcode == BRW_OPCODE_NOT); + return (opcode == ELK_OPCODE_AND || + opcode == ELK_OPCODE_OR || + opcode == ELK_OPCODE_XOR || + opcode == ELK_OPCODE_NOT); } static bool -can_take_stride(fs_inst *inst, brw_reg_type dst_type, +can_take_stride(elk_fs_inst *inst, elk_reg_type dst_type, unsigned arg, unsigned stride, - const struct brw_compiler *compiler) + const struct elk_compiler *compiler) { const struct intel_device_info *devinfo = compiler->devinfo; @@ -606,7 +606,7 @@ can_take_stride(fs_inst *inst, brw_reg_type dst_type, * This is applicable to 32b datatypes and 16b datatype. 64b datatypes * cannot use the replicate control. */ - if (inst->is_3src(compiler)) { + if (inst->elk_is_3src(compiler)) { if (type_sz(inst->src[arg].type) > 4) return stride == 1; else @@ -643,14 +643,14 @@ can_take_stride(fs_inst *inst, brw_reg_type dst_type, } static bool -instruction_requires_packed_data(fs_inst *inst) +instruction_requires_packed_data(elk_fs_inst *inst) { switch (inst->opcode) { - case FS_OPCODE_DDX_FINE: - case FS_OPCODE_DDX_COARSE: - case FS_OPCODE_DDY_FINE: - case FS_OPCODE_DDY_COARSE: - case SHADER_OPCODE_QUAD_SWIZZLE: + case ELK_FS_OPCODE_DDX_FINE: + case ELK_FS_OPCODE_DDX_COARSE: + case ELK_FS_OPCODE_DDY_FINE: + case ELK_FS_OPCODE_DDY_COARSE: + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: return true; default: return false; @@ -658,7 +658,7 @@ instruction_requires_packed_data(fs_inst *inst) } static bool -try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, +try_copy_propagate(const elk_compiler *compiler, elk_fs_inst *inst, acp_entry *entry, int arg, const elk::simple_allocator &alloc, uint8_t max_polygons) @@ -685,7 +685,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, * optimization loop. Avoid this by detecting LOAD_PAYLOAD copies from CSE * temporaries which should match is_coalescing_payload(). */ - if (entry->opcode == SHADER_OPCODE_LOAD_PAYLOAD && + if (entry->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD && (is_coalescing_payload(alloc, inst) || is_multi_copy_payload(inst))) return false; @@ -714,7 +714,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, * We need to pin both split SEND sources in g112-g126/127, so only * allow this if the registers aren't too large. */ - if (inst->opcode == SHADER_OPCODE_SEND && entry->src.file == VGRF) { + if (inst->opcode == ELK_SHADER_OPCODE_SEND && entry->src.file == VGRF) { int other_src = arg == 2 ? 3 : 2; unsigned other_size = inst->src[other_src].file == VGRF ? alloc.sizes[inst->src[other_src].nr] : @@ -731,15 +731,15 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, */ if (devinfo->has_pln && devinfo->ver <= 6 && entry->src.file == FIXED_GRF && (entry->src.nr & 1) && - inst->opcode == FS_OPCODE_LINTERP && arg == 0) + inst->opcode == ELK_FS_OPCODE_LINTERP && arg == 0) return false; /* we can't generally copy-propagate UD negations because we * can end up accessing the resulting values as signed integers * instead. See also resolve_ud_negate() and comment in - * fs_generator::generate_code. + * elk_fs_generator::generate_code. */ - if (entry->src.type == BRW_REGISTER_TYPE_UD && + if (entry->src.type == ELK_REGISTER_TYPE_UD && entry->src.negate) return false; @@ -757,7 +757,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, } if (has_source_modifiers && - inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE) + inst->opcode == ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE) return false; /* Some instructions implemented in the generator backend, such as @@ -769,7 +769,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, if (instruction_requires_packed_data(inst) && entry_stride != 1) return false; - const brw_reg_type dst_type = (has_source_modifiers && + const elk_reg_type dst_type = (has_source_modifiers && entry->dst.type != inst->src[arg].type) ? entry->dst.type : inst->dst.type; @@ -810,7 +810,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, if (entry->src.file == ATTR && max_polygons > 1 && (has_dst_aligned_region_restriction(devinfo, inst, dst_type) || instruction_requires_packed_data(inst) || - (inst->is_3src(compiler) && arg == 2) || + (inst->elk_is_3src(compiler) && arg == 2) || entry->dst.type != inst->src[arg].type)) return false; @@ -833,7 +833,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, */ if ((type_sz(entry->dst.type) < type_sz(inst->src[arg].type) || entry->is_partial_write) && - inst->opcode != BRW_OPCODE_MOV) { + inst->opcode != ELK_OPCODE_MOV) { return false; } @@ -900,7 +900,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, inst->src[arg].stride = 1; /* Hopefully no Align16 around here... */ - assert(entry->src.swizzle == BRW_SWIZZLE_XYZW); + assert(entry->src.swizzle == ELK_SWIZZLE_XYZW); inst->src[arg].swizzle = entry->src.swizzle; } else { inst->src[arg].stride *= entry->src.stride; @@ -909,7 +909,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, /* Compute the first component of the copy that the instruction is * reading, and the base byte offset within that component. */ - assert((entry->dst.offset % REG_SIZE == 0 || inst->opcode == BRW_OPCODE_MOV) && + assert((entry->dst.offset % REG_SIZE == 0 || inst->opcode == ELK_OPCODE_MOV) && entry->dst.stride == 1); const unsigned component = rel_offset / type_sz(entry->dst.type); const unsigned suboffset = rel_offset % type_sz(entry->dst.type); @@ -943,7 +943,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, static bool -try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, +try_constant_propagate(const elk_compiler *compiler, elk_fs_inst *inst, acp_entry *entry, int arg) { const struct intel_device_info *devinfo = compiler->devinfo; @@ -973,7 +973,7 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, if (type_sz(inst->src[arg].type) > type_sz(entry->dst.type)) return false; - fs_reg val = entry->src; + elk_fs_reg val = entry->src; /* If the size of the use type is smaller than the size of the entry, * clamp the value to the range of the use type. This enables constant @@ -1003,27 +1003,27 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, if (inst->src[arg].abs) { if ((devinfo->ver >= 8 && is_logic_op(inst->opcode)) || - !brw_abs_immediate(val.type, &val.as_brw_reg())) { + !elk_abs_immediate(val.type, &val.as_elk_reg())) { return false; } } if (inst->src[arg].negate) { if ((devinfo->ver >= 8 && is_logic_op(inst->opcode)) || - !brw_negate_immediate(val.type, &val.as_brw_reg())) { + !elk_negate_immediate(val.type, &val.as_elk_reg())) { return false; } } switch (inst->opcode) { - case BRW_OPCODE_MOV: - case SHADER_OPCODE_LOAD_PAYLOAD: - case FS_OPCODE_PACK: + case ELK_OPCODE_MOV: + case ELK_SHADER_OPCODE_LOAD_PAYLOAD: + case ELK_FS_OPCODE_PACK: inst->src[arg] = val; progress = true; break; - case SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_POW: /* Allow constant propagation into src1 (except on Gen 6 which * doesn't support scalar source math), and let constant combining * promote the constant on Gen < 8. @@ -1037,19 +1037,19 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, } break; - case BRW_OPCODE_SUBB: + case ELK_OPCODE_SUBB: if (arg == 1) { inst->src[arg] = val; progress = true; } break; - case BRW_OPCODE_MACH: - case BRW_OPCODE_MUL: - case SHADER_OPCODE_MULH: - case BRW_OPCODE_ADD: - case BRW_OPCODE_XOR: - case BRW_OPCODE_ADDC: + case ELK_OPCODE_MACH: + case ELK_OPCODE_MUL: + case ELK_SHADER_OPCODE_MULH: + case ELK_OPCODE_ADD: + case ELK_OPCODE_XOR: + case ELK_OPCODE_ADDC: if (arg == 1) { inst->src[arg] = val; progress = true; @@ -1076,7 +1076,7 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, * When multiplying a DW and any lower precision integer, the * DW operand must on src0. */ - if (inst->opcode == BRW_OPCODE_MUL && + if (inst->opcode == ELK_OPCODE_MUL && type_sz(inst->src[1].type) < 4 && type_sz(val.type) == 4) break; @@ -1092,11 +1092,11 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, * Integer MUL with a non-accumulator destination will be lowered * by lower_integer_multiplication(), so don't restrict it. */ - if (((inst->opcode == BRW_OPCODE_MUL && + if (((inst->opcode == ELK_OPCODE_MUL && inst->dst.is_accumulator()) || - inst->opcode == BRW_OPCODE_MACH) && - (inst->src[1].type == BRW_REGISTER_TYPE_D || - inst->src[1].type == BRW_REGISTER_TYPE_UD)) + inst->opcode == ELK_OPCODE_MACH) && + (inst->src[1].type == ELK_REGISTER_TYPE_D || + inst->src[1].type == ELK_REGISTER_TYPE_UD)) break; inst->src[0] = inst->src[1]; inst->src[1] = val; @@ -1104,16 +1104,16 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, } break; - case BRW_OPCODE_ADD3: + case ELK_OPCODE_ADD3: /* add3 can have a single imm16 source. Proceed if the source type is * already W or UW or the value can be coerced to one of those types. */ - if (val.type == BRW_REGISTER_TYPE_W || val.type == BRW_REGISTER_TYPE_UW) + if (val.type == ELK_REGISTER_TYPE_W || val.type == ELK_REGISTER_TYPE_UW) ; /* Nothing to do. */ else if (val.ud <= 0xffff) - val = brw_imm_uw(val.ud); + val = elk_imm_uw(val.ud); else if (val.d >= -0x8000 && val.d <= 0x7fff) - val = brw_imm_w(val.d); + val = elk_imm_w(val.d); else break; @@ -1128,16 +1128,16 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, break; - case BRW_OPCODE_CMP: - case BRW_OPCODE_IF: + case ELK_OPCODE_CMP: + case ELK_OPCODE_IF: if (arg == 1) { inst->src[arg] = val; progress = true; } else if (arg == 0 && inst->src[1].file != IMM) { - enum brw_conditional_mod new_cmod; + enum elk_conditional_mod new_cmod; - new_cmod = brw_swap_cmod(inst->conditional_mod); - if (new_cmod != BRW_CONDITIONAL_NONE) { + new_cmod = elk_swap_cmod(inst->conditional_mod); + if (new_cmod != ELK_CONDITIONAL_NONE) { /* Fit this constant in by swapping the operands and * flipping the test */ @@ -1149,23 +1149,23 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, } break; - case BRW_OPCODE_SEL: + case ELK_OPCODE_SEL: if (arg == 1) { inst->src[arg] = val; progress = true; } else if (arg == 0) { if (inst->src[1].file != IMM && - (inst->conditional_mod == BRW_CONDITIONAL_NONE || + (inst->conditional_mod == ELK_CONDITIONAL_NONE || /* Only GE and L are commutative. */ - inst->conditional_mod == BRW_CONDITIONAL_GE || - inst->conditional_mod == BRW_CONDITIONAL_L)) { + inst->conditional_mod == ELK_CONDITIONAL_GE || + inst->conditional_mod == ELK_CONDITIONAL_L)) { inst->src[0] = inst->src[1]; inst->src[1] = val; /* If this was predicated, flipping operands means * we also need to flip the predicate. */ - if (inst->conditional_mod == BRW_CONDITIONAL_NONE) { + if (inst->conditional_mod == ELK_CONDITIONAL_NONE) { inst->predicate_inverse = !inst->predicate_inverse; } @@ -1177,8 +1177,8 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, } break; - case FS_OPCODE_FB_WRITE_LOGICAL: - /* The stencil and omask sources of FS_OPCODE_FB_WRITE_LOGICAL are + case ELK_FS_OPCODE_FB_WRITE_LOGICAL: + /* The stencil and omask sources of ELK_FS_OPCODE_FB_WRITE_LOGICAL are * bit-cast using a strided region so they cannot be immediates. */ if (arg != FB_WRITE_LOGICAL_SRC_SRC_STENCIL && @@ -1188,8 +1188,8 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, } break; - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: /* Allow constant propagation into either source (except on Gen 6 * which doesn't support scalar source math). Constant combining * promote the src1 constant on Gen < 8, and it will promote the src0 @@ -1199,46 +1199,46 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, break; FALLTHROUGH; - case BRW_OPCODE_AND: - case BRW_OPCODE_ASR: - case BRW_OPCODE_BFE: - case BRW_OPCODE_BFI1: - case BRW_OPCODE_BFI2: - case BRW_OPCODE_ROL: - case BRW_OPCODE_ROR: - case BRW_OPCODE_SHL: - case BRW_OPCODE_SHR: - case BRW_OPCODE_OR: - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_UMS_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: - case SHADER_OPCODE_BROADCAST: - case BRW_OPCODE_MAD: - case BRW_OPCODE_LRP: - case FS_OPCODE_PACK_HALF_2x16_SPLIT: - case SHADER_OPCODE_SHUFFLE: + case ELK_OPCODE_AND: + case ELK_OPCODE_ASR: + case ELK_OPCODE_BFE: + case ELK_OPCODE_BFI1: + case ELK_OPCODE_BFI2: + case ELK_OPCODE_ROL: + case ELK_OPCODE_ROR: + case ELK_OPCODE_SHL: + case ELK_OPCODE_SHR: + case ELK_OPCODE_OR: + case ELK_SHADER_OPCODE_TEX_LOGICAL: + case ELK_SHADER_OPCODE_TXD_LOGICAL: + case ELK_SHADER_OPCODE_TXF_LOGICAL: + case ELK_SHADER_OPCODE_TXL_LOGICAL: + case ELK_SHADER_OPCODE_TXS_LOGICAL: + case ELK_FS_OPCODE_TXB_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: + case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL: + case ELK_SHADER_OPCODE_LOD_LOGICAL: + case ELK_SHADER_OPCODE_TG4_LOGICAL: + case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL: + case ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_SHADER_OPCODE_BROADCAST: + case ELK_OPCODE_MAD: + case ELK_OPCODE_LRP: + case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT: + case ELK_SHADER_OPCODE_SHUFFLE: inst->src[arg] = val; progress = true; break; @@ -1251,9 +1251,9 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst, } static bool -can_propagate_from(fs_inst *inst) +can_propagate_from(elk_fs_inst *inst) { - return (inst->opcode == BRW_OPCODE_MOV && + return (inst->opcode == ELK_OPCODE_MOV && inst->dst.file == VGRF && ((inst->src[0].file == VGRF && !grf_regions_overlap(inst->dst, inst->size_written, @@ -1274,14 +1274,14 @@ can_propagate_from(fs_inst *inst) * list. */ static bool -opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx, - bblock_t *block, struct acp &acp, +opt_copy_propagation_local(const elk_compiler *compiler, linear_ctx *lin_ctx, + elk_bblock_t *block, struct acp &acp, const elk::simple_allocator &alloc, uint8_t max_polygons) { bool progress = false; - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(elk_fs_inst, inst, block) { /* Try propagating into this instruction. */ bool instruction_progress = false; for (int i = inst->sources - 1; i >= 0; i--) { @@ -1310,7 +1310,7 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx, progress = true; /* ADD3 can only have the immediate as src0. */ - if (inst->opcode == BRW_OPCODE_ADD3) { + if (inst->opcode == ELK_OPCODE_ADD3) { if (inst->src[2].file == IMM) { const auto src0 = inst->src[0]; inst->src[0] = inst->src[2]; @@ -1366,7 +1366,7 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx, entry->is_partial_write = inst->is_partial_write(); entry->force_writemask_all = inst->force_writemask_all; acp.add(entry); - } else if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD && + } else if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD && inst->dst.file == VGRF) { int offset = 0; for (int i = 0; i < inst->sources; i++) { @@ -1376,9 +1376,9 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx, if (inst->src[i].file == VGRF || (inst->src[i].file == FIXED_GRF && inst->src[i].is_contiguous())) { - const brw_reg_type t = i < inst->header_size ? - BRW_REGISTER_TYPE_UD : inst->src[i].type; - fs_reg dst = byte_offset(retype(inst->dst, t), offset); + const elk_reg_type t = i < inst->header_size ? + ELK_REGISTER_TYPE_UD : inst->src[i].type; + elk_fs_reg dst = byte_offset(retype(inst->dst, t), offset); if (!dst.equals(inst->src[i])) { acp_entry *entry = linear_zalloc(lin_ctx, acp_entry); entry->dst = dst; @@ -1399,7 +1399,7 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx, } bool -fs_visitor::opt_copy_propagation() +elk_fs_visitor::opt_copy_propagation() { bool progress = false; void *copy_prop_ctx = ralloc_context(NULL); diff --git a/src/intel/compiler/elk/elk_fs_cse.cpp b/src/intel/compiler/elk/elk_fs_cse.cpp index 09fef1995f0..a1abe7af07a 100644 --- a/src/intel/compiler/elk/elk_fs_cse.cpp +++ b/src/intel/compiler/elk/elk_fs_cse.cpp @@ -38,76 +38,76 @@ using namespace elk; namespace { struct aeb_entry : public exec_node { /** The instruction that generates the expression value. */ - fs_inst *generator; + elk_fs_inst *generator; /** The temporary where the value is stored. */ - fs_reg tmp; + elk_fs_reg tmp; }; } static bool -is_expression(const fs_visitor *v, const fs_inst *const inst) +is_expression(const elk_fs_visitor *v, const elk_fs_inst *const inst) { switch (inst->opcode) { - case BRW_OPCODE_MOV: - case BRW_OPCODE_SEL: - case BRW_OPCODE_NOT: - case BRW_OPCODE_AND: - case BRW_OPCODE_OR: - case BRW_OPCODE_XOR: - case BRW_OPCODE_SHR: - case BRW_OPCODE_SHL: - case BRW_OPCODE_ASR: - case BRW_OPCODE_CMP: - case BRW_OPCODE_CMPN: - case BRW_OPCODE_ADD: - case BRW_OPCODE_MUL: - case SHADER_OPCODE_MULH: - case BRW_OPCODE_FRC: - case BRW_OPCODE_RNDU: - case BRW_OPCODE_RNDD: - case BRW_OPCODE_RNDE: - case BRW_OPCODE_RNDZ: - case BRW_OPCODE_LINE: - case BRW_OPCODE_PLN: - case BRW_OPCODE_MAD: - case BRW_OPCODE_LRP: - case FS_OPCODE_FB_READ_LOGICAL: - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: - case FS_OPCODE_LINTERP: - case SHADER_OPCODE_FIND_LIVE_CHANNEL: - case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: - case FS_OPCODE_LOAD_LIVE_CHANNELS: - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_MOV_INDIRECT: - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_UMS_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case FS_OPCODE_PACK: + case ELK_OPCODE_MOV: + case ELK_OPCODE_SEL: + case ELK_OPCODE_NOT: + case ELK_OPCODE_AND: + case ELK_OPCODE_OR: + case ELK_OPCODE_XOR: + case ELK_OPCODE_SHR: + case ELK_OPCODE_SHL: + case ELK_OPCODE_ASR: + case ELK_OPCODE_CMP: + case ELK_OPCODE_CMPN: + case ELK_OPCODE_ADD: + case ELK_OPCODE_MUL: + case ELK_SHADER_OPCODE_MULH: + case ELK_OPCODE_FRC: + case ELK_OPCODE_RNDU: + case ELK_OPCODE_RNDD: + case ELK_OPCODE_RNDE: + case ELK_OPCODE_RNDZ: + case ELK_OPCODE_LINE: + case ELK_OPCODE_PLN: + case ELK_OPCODE_MAD: + case ELK_OPCODE_LRP: + case ELK_FS_OPCODE_FB_READ_LOGICAL: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: + case ELK_FS_OPCODE_LINTERP: + case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL: + case ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: + case ELK_FS_OPCODE_LOAD_LIVE_CHANNELS: + case ELK_SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_TEX_LOGICAL: + case ELK_SHADER_OPCODE_TXD_LOGICAL: + case ELK_SHADER_OPCODE_TXF_LOGICAL: + case ELK_SHADER_OPCODE_TXL_LOGICAL: + case ELK_SHADER_OPCODE_TXS_LOGICAL: + case ELK_FS_OPCODE_TXB_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL: + case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL: + case ELK_SHADER_OPCODE_LOD_LOGICAL: + case ELK_SHADER_OPCODE_TG4_LOGICAL: + case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL: + case ELK_FS_OPCODE_PACK: return true; - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: return inst->mlen < 2; - case SHADER_OPCODE_LOAD_PAYLOAD: + case ELK_SHADER_OPCODE_LOAD_PAYLOAD: return !is_coalescing_payload(v->alloc, inst); default: return inst->is_send_from_grf() && !inst->has_side_effects() && @@ -116,16 +116,16 @@ is_expression(const fs_visitor *v, const fs_inst *const inst) } static bool -operands_match(const fs_inst *a, const fs_inst *b, bool *negate) +operands_match(const elk_fs_inst *a, const elk_fs_inst *b, bool *negate) { - fs_reg *xs = a->src; - fs_reg *ys = b->src; + elk_fs_reg *xs = a->src; + elk_fs_reg *ys = b->src; - if (a->opcode == BRW_OPCODE_MAD) { + if (a->opcode == ELK_OPCODE_MAD) { return xs[0].equals(ys[0]) && ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) || (xs[2].equals(ys[1]) && xs[1].equals(ys[2]))); - } else if (a->opcode == BRW_OPCODE_MUL && a->dst.type == BRW_REGISTER_TYPE_F) { + } else if (a->opcode == ELK_OPCODE_MUL && a->dst.type == ELK_REGISTER_TYPE_F) { bool xs0_negate = xs[0].negate; bool xs1_negate = xs[1].file == IMM ? xs[1].f < 0.0f : xs[1].negate; @@ -172,7 +172,7 @@ operands_match(const fs_inst *a, const fs_inst *b, bool *negate) } static bool -instructions_match(fs_inst *a, fs_inst *b, bool *negate) +instructions_match(elk_fs_inst *a, elk_fs_inst *b, bool *negate) { return a->opcode == b->opcode && a->force_writemask_all == b->force_writemask_all && @@ -203,16 +203,16 @@ instructions_match(fs_inst *a, fs_inst *b, bool *negate) } static void -create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate) +create_copy_instr(const fs_builder &bld, elk_fs_inst *inst, elk_fs_reg src, bool negate) { unsigned written = regs_written(inst); unsigned dst_width = DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE); - fs_inst *copy; + elk_fs_inst *copy; - if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { + if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD) { assert(src.file == VGRF); - fs_reg *payload = ralloc_array(bld.shader->mem_ctx, fs_reg, + elk_fs_reg *payload = ralloc_array(bld.shader->mem_ctx, elk_fs_reg, inst->sources); for (int i = 0; i < inst->header_size; i++) { payload[i] = src; @@ -229,7 +229,7 @@ create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate) assert(src.file == VGRF); assert(written % dst_width == 0); const int sources = written / dst_width; - fs_reg *payload = ralloc_array(bld.shader->mem_ctx, fs_reg, sources); + elk_fs_reg *payload = ralloc_array(bld.shader->mem_ctx, elk_fs_reg, sources); for (int i = 0; i < sources; i++) { payload[i] = src; src = offset(src, bld, 1); @@ -245,14 +245,14 @@ create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate) } bool -fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &ip) +elk_fs_visitor::opt_cse_local(const fs_live_variables &live, elk_bblock_t *block, int &ip) { bool progress = false; exec_list aeb; void *cse_ctx = ralloc_context(NULL); - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(elk_fs_inst, inst, block) { /* Skip some cases. */ if (is_expression(this, inst) && !inst->is_partial_write() && ((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) || @@ -272,10 +272,10 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i } if (!found) { - if (inst->opcode != BRW_OPCODE_MOV || - (inst->opcode == BRW_OPCODE_MOV && + if (inst->opcode != ELK_OPCODE_MOV || + (inst->opcode == ELK_OPCODE_MOV && inst->src[0].file == IMM && - inst->src[0].type == BRW_REGISTER_TYPE_VF)) { + inst->src[0].type == ELK_REGISTER_TYPE_VF)) { /* Our first sighting of this expression. Create an entry. */ aeb_entry *entry = ralloc(cse_ctx, aeb_entry); entry->tmp = reg_undef; @@ -292,7 +292,7 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i .at(block, entry->generator->next); int written = regs_written(entry->generator); - entry->tmp = fs_reg(VGRF, alloc.allocate(written), + entry->tmp = elk_fs_reg(VGRF, alloc.allocate(written), entry->generator->dst.type); create_copy_instr(ibld, entry->generator, entry->tmp, false); @@ -313,7 +313,7 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i * will get the instruction in the basic block after the one we've * removed. */ - fs_inst *prev = (fs_inst *)inst->prev; + elk_fs_inst *prev = (elk_fs_inst *)inst->prev; inst->remove(block); inst = prev; @@ -324,10 +324,10 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i * to make sure that they behave as a CSE barrier, since we lack global * dataflow information. This is particularly likely to cause problems * with instructions dependent on the current execution mask like - * SHADER_OPCODE_FIND_LIVE_CHANNEL. + * ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL. */ - if (inst->opcode == BRW_OPCODE_HALT || - inst->opcode == SHADER_OPCODE_HALT_TARGET) + if (inst->opcode == ELK_OPCODE_HALT || + inst->opcode == ELK_SHADER_OPCODE_HALT_TARGET) aeb.make_empty(); foreach_in_list_safe(aeb_entry, entry, &aeb) { @@ -346,7 +346,7 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i } for (int i = 0; i < entry->generator->sources; i++) { - fs_reg *src_reg = &entry->generator->src[i]; + elk_fs_reg *src_reg = &entry->generator->src[i]; /* Kill all AEB entries that use the destination we just * overwrote. @@ -379,7 +379,7 @@ fs_visitor::opt_cse_local(const fs_live_variables &live, bblock_t *block, int &i } bool -fs_visitor::opt_cse() +elk_fs_visitor::opt_cse() { const fs_live_variables &live = live_analysis.require(); bool progress = false; diff --git a/src/intel/compiler/elk/elk_fs_dead_code_eliminate.cpp b/src/intel/compiler/elk/elk_fs_dead_code_eliminate.cpp index fa86aef131d..99c9b779398 100644 --- a/src/intel/compiler/elk/elk_fs_dead_code_eliminate.cpp +++ b/src/intel/compiler/elk/elk_fs_dead_code_eliminate.cpp @@ -40,7 +40,7 @@ using namespace elk; * Is it safe to eliminate the instruction? */ static bool -can_eliminate(const intel_device_info *devinfo, const fs_inst *inst, +can_eliminate(const intel_device_info *devinfo, const elk_fs_inst *inst, BITSET_WORD *flag_live) { return !inst->is_control_flow() && @@ -53,12 +53,12 @@ can_eliminate(const intel_device_info *devinfo, const fs_inst *inst, * Is it safe to omit the write, making the destination ARF null? */ static bool -can_omit_write(const fs_inst *inst) +can_omit_write(const elk_fs_inst *inst) { switch (inst->opcode) { - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: return true; default: /* We can eliminate the destination write for ordinary instructions, @@ -73,7 +73,7 @@ can_omit_write(const fs_inst *inst) } bool -fs_visitor::dead_code_eliminate() +elk_fs_visitor::dead_code_eliminate() { bool progress = false; @@ -88,7 +88,7 @@ fs_visitor::dead_code_eliminate() memcpy(flag_live, live_vars.block_data[block->num].flag_liveout, sizeof(BITSET_WORD)); - foreach_inst_in_block_reverse_safe(fs_inst, inst, block) { + foreach_inst_in_block_reverse_safe(elk_fs_inst, inst, block) { if (inst->dst.file == VGRF) { const unsigned var = live_vars.var_from_reg(inst->dst); bool result_live = false; @@ -98,14 +98,14 @@ fs_visitor::dead_code_eliminate() if (!result_live && (can_omit_write(inst) || can_eliminate(devinfo, inst, flag_live))) { - inst->dst = fs_reg(spread(retype(brw_null_reg(), inst->dst.type), + inst->dst = elk_fs_reg(spread(retype(elk_null_reg(), inst->dst.type), inst->dst.stride)); progress = true; } } if (inst->dst.is_null() && can_eliminate(devinfo, inst, flag_live)) { - inst->opcode = BRW_OPCODE_NOP; + inst->opcode = ELK_OPCODE_NOP; progress = true; } @@ -121,7 +121,7 @@ fs_visitor::dead_code_eliminate() if (!inst->predicate && inst->exec_size >= 8) flag_live[0] &= ~inst->flags_written(devinfo); - if (inst->opcode == BRW_OPCODE_NOP) { + if (inst->opcode == ELK_OPCODE_NOP) { inst->remove(block, true); continue; } diff --git a/src/intel/compiler/elk/elk_fs_generator.cpp b/src/intel/compiler/elk/elk_fs_generator.cpp index e1895a6e2e4..aec5b86378f 100644 --- a/src/intel/compiler/elk/elk_fs_generator.cpp +++ b/src/intel/compiler/elk/elk_fs_generator.cpp @@ -35,40 +35,40 @@ #include "util/mesa-sha1.h" #include "util/half_float.h" -static enum brw_reg_file -brw_file_from_reg(fs_reg *reg) +static enum elk_reg_file +elk_file_from_reg(elk_fs_reg *reg) { switch (reg->file) { case ARF: - return BRW_ARCHITECTURE_REGISTER_FILE; + return ELK_ARCHITECTURE_REGISTER_FILE; case FIXED_GRF: case VGRF: - return BRW_GENERAL_REGISTER_FILE; + return ELK_GENERAL_REGISTER_FILE; case MRF: - return BRW_MESSAGE_REGISTER_FILE; + return ELK_MESSAGE_REGISTER_FILE; case IMM: - return BRW_IMMEDIATE_VALUE; + return ELK_IMMEDIATE_VALUE; case BAD_FILE: case ATTR: case UNIFORM: unreachable("not reached"); } - return BRW_ARCHITECTURE_REGISTER_FILE; + return ELK_ARCHITECTURE_REGISTER_FILE; } -static struct brw_reg -brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst, - fs_reg *reg, bool compressed) +static struct elk_reg +elk_reg_from_fs_reg(const struct intel_device_info *devinfo, elk_fs_inst *inst, + elk_fs_reg *reg, bool compressed) { - struct brw_reg brw_reg; + struct elk_reg elk_reg; switch (reg->file) { case MRF: - assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver)); + assert((reg->nr & ~ELK_MRF_COMPR4) < ELK_MAX_MRF(devinfo->ver)); FALLTHROUGH; case VGRF: if (reg->stride == 0) { - brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0); + elk_reg = elk_vec1_reg(elk_file_from_reg(reg), reg->nr, 0); } else { /* From the Haswell PRM: * @@ -99,12 +99,12 @@ brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst, if (reg->stride > 4) { assert(reg != &inst->dst); assert(reg->stride * type_sz(reg->type) <= REG_SIZE); - brw_reg = brw_vecn_reg(1, brw_file_from_reg(reg), reg->nr, 0); - brw_reg = stride(brw_reg, reg->stride, 1, 0); + elk_reg = elk_vecn_reg(1, elk_file_from_reg(reg), reg->nr, 0); + elk_reg = stride(elk_reg, reg->stride, 1, 0); } else { const unsigned width = MIN3(reg_width, phys_width, max_hw_width); - brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0); - brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride); + elk_reg = elk_vecn_reg(width, elk_file_from_reg(reg), reg->nr, 0); + elk_reg = stride(elk_reg, width * reg->stride, width, reg->stride); } if (devinfo->verx10 == 70) { @@ -130,10 +130,10 @@ brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst, * It applies to BayTrail too. */ if (type_sz(reg->type) == 8) { - brw_reg.width++; - if (brw_reg.vstride > 0) - brw_reg.vstride++; - assert(brw_reg.hstride == BRW_HORIZONTAL_STRIDE_1); + elk_reg.width++; + if (elk_reg.vstride > 0) + elk_reg.vstride++; + assert(elk_reg.hstride == ELK_HORIZONTAL_STRIDE_1); } /* When converting from DF->F, we set the destination stride to 2 @@ -144,26 +144,26 @@ brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst, */ if (reg == &inst->dst && get_exec_type_size(inst) == 8 && type_sz(inst->dst.type) < 8) { - assert(brw_reg.hstride > BRW_HORIZONTAL_STRIDE_1); - brw_reg.hstride--; + assert(elk_reg.hstride > ELK_HORIZONTAL_STRIDE_1); + elk_reg.hstride--; } } } - brw_reg = retype(brw_reg, reg->type); - brw_reg = byte_offset(brw_reg, reg->offset); - brw_reg.abs = reg->abs; - brw_reg.negate = reg->negate; + elk_reg = retype(elk_reg, reg->type); + elk_reg = byte_offset(elk_reg, reg->offset); + elk_reg.abs = reg->abs; + elk_reg.negate = reg->negate; break; case ARF: case FIXED_GRF: case IMM: assert(reg->offset == 0); - brw_reg = reg->as_brw_reg(); + elk_reg = reg->as_elk_reg(); break; case BAD_FILE: /* Probably unused. */ - brw_reg = brw_null_reg(); + elk_reg = elk_null_reg(); break; case ATTR: case UNIFORM: @@ -176,19 +176,19 @@ brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst, */ if (devinfo->verx10 == 70 && type_sz(reg->type) == 8 && - brw_reg.vstride == BRW_VERTICAL_STRIDE_0 && - brw_reg.width == BRW_WIDTH_1 && - brw_reg.hstride == BRW_HORIZONTAL_STRIDE_0) { - brw_reg.width = BRW_WIDTH_2; - brw_reg.hstride = BRW_HORIZONTAL_STRIDE_1; + elk_reg.vstride == ELK_VERTICAL_STRIDE_0 && + elk_reg.width == ELK_WIDTH_1 && + elk_reg.hstride == ELK_HORIZONTAL_STRIDE_0) { + elk_reg.width = ELK_WIDTH_2; + elk_reg.hstride = ELK_HORIZONTAL_STRIDE_1; } - return brw_reg; + return elk_reg; } -fs_generator::fs_generator(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - struct brw_stage_prog_data *prog_data, +elk_fs_generator::elk_fs_generator(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + struct elk_stage_prog_data *prog_data, bool runtime_check_aads_emit, gl_shader_stage stage) @@ -198,8 +198,8 @@ fs_generator::fs_generator(const struct brw_compiler *compiler, runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false), shader_name(NULL), stage(stage), mem_ctx(params->mem_ctx) { - p = rzalloc(mem_ctx, struct brw_codegen); - brw_init_codegen(&compiler->isa, p, mem_ctx); + p = rzalloc(mem_ctx, struct elk_codegen); + elk_init_codegen(&compiler->isa, p, mem_ctx); /* In the FS code generator, we are very careful to ensure that we always * set the right execution size so we don't need the EU code to "help" us @@ -208,7 +208,7 @@ fs_generator::fs_generator(const struct brw_compiler *compiler, p->automatic_exec_sizes = false; } -fs_generator::~fs_generator() +elk_fs_generator::~elk_fs_generator() { } @@ -225,12 +225,12 @@ public: }; bool -fs_generator::patch_halt_jumps() +elk_fs_generator::patch_halt_jumps() { if (this->discard_halt_patches.is_empty()) return false; - int scale = brw_jump_scale(p->devinfo); + int scale = elk_jump_scale(p->devinfo); if (devinfo->ver >= 6) { /* There is a somewhat strange undocumented requirement of using @@ -244,22 +244,22 @@ fs_generator::patch_halt_jumps() * included GPU hangs and sparkly rendering on the piglit discard * tests. */ - brw_inst *last_halt = brw_HALT(p); - brw_inst_set_uip(p->devinfo, last_halt, 1 * scale); - brw_inst_set_jip(p->devinfo, last_halt, 1 * scale); + elk_inst *last_halt = elk_HALT(p); + elk_inst_set_uip(p->devinfo, last_halt, 1 * scale); + elk_inst_set_jip(p->devinfo, last_halt, 1 * scale); } int ip = p->nr_insn; foreach_in_list(ip_record, patch_ip, &discard_halt_patches) { - brw_inst *patch = &p->store[patch_ip->ip]; + elk_inst *patch = &p->store[patch_ip->ip]; - assert(brw_inst_opcode(p->isa, patch) == BRW_OPCODE_HALT); + assert(elk_inst_opcode(p->isa, patch) == ELK_OPCODE_HALT); if (devinfo->ver >= 6) { /* HALT takes a half-instruction distance from the pre-incremented IP. */ - brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale); + elk_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale); } else { - brw_set_src1(p, patch, brw_imm_d((ip - patch_ip->ip) * scale)); + elk_set_src1(p, patch, elk_imm_d((ip - patch_ip->ip) * scale)); } } @@ -274,12 +274,12 @@ fs_generator::patch_halt_jumps() * * DMask lives in the bottom 16 bits of sr0.1. */ - brw_inst *reset = brw_MOV(p, brw_mask_reg(BRW_AMASK), - retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW)); - brw_inst_set_exec_size(devinfo, reset, BRW_EXECUTE_1); - brw_inst_set_mask_control(devinfo, reset, BRW_MASK_DISABLE); - brw_inst_set_qtr_control(devinfo, reset, BRW_COMPRESSION_NONE); - brw_inst_set_thread_control(devinfo, reset, BRW_THREAD_SWITCH); + elk_inst *reset = elk_MOV(p, elk_mask_reg(ELK_AMASK), + retype(elk_sr0_reg(1), ELK_REGISTER_TYPE_UW)); + elk_inst_set_exec_size(devinfo, reset, ELK_EXECUTE_1); + elk_inst_set_mask_control(devinfo, reset, ELK_MASK_DISABLE); + elk_inst_set_qtr_control(devinfo, reset, ELK_COMPRESSION_NONE); + elk_inst_set_thread_control(devinfo, reset, ELK_THREAD_SWITCH); } if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X) { @@ -301,83 +301,83 @@ fs_generator::patch_halt_jumps() * when a mask stack register is used as an explicit source and/or * destination." */ - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); - brw_set_default_exec_size(p, BRW_EXECUTE_2); - brw_MOV(p, vec2(brw_mask_stack_depth_reg(0)), brw_imm_uw(0)); + elk_set_default_exec_size(p, ELK_EXECUTE_2); + elk_MOV(p, vec2(elk_mask_stack_depth_reg(0)), elk_imm_uw(0)); - brw_set_default_exec_size(p, BRW_EXECUTE_16); + elk_set_default_exec_size(p, ELK_EXECUTE_16); /* Reset the if stack. */ - brw_MOV(p, retype(brw_mask_stack_reg(0), BRW_REGISTER_TYPE_UW), - brw_imm_uw(0)); + elk_MOV(p, retype(elk_mask_stack_reg(0), ELK_REGISTER_TYPE_UW), + elk_imm_uw(0)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } return true; } void -fs_generator::generate_send(fs_inst *inst, - struct brw_reg dst, - struct brw_reg desc, - struct brw_reg ex_desc, - struct brw_reg payload, - struct brw_reg payload2) +elk_fs_generator::generate_send(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg desc, + struct elk_reg ex_desc, + struct elk_reg payload, + struct elk_reg payload2) { - const bool dst_is_null = dst.file == BRW_ARCHITECTURE_REGISTER_FILE && - dst.nr == BRW_ARF_NULL; + const bool dst_is_null = dst.file == ELK_ARCHITECTURE_REGISTER_FILE && + dst.nr == ELK_ARF_NULL; const unsigned rlen = dst_is_null ? 0 : inst->size_written / REG_SIZE; uint32_t desc_imm = inst->desc | - brw_message_desc(devinfo, inst->mlen, rlen, inst->header_size); + elk_message_desc(devinfo, inst->mlen, rlen, inst->header_size); uint32_t ex_desc_imm = inst->ex_desc | - brw_message_ex_desc(devinfo, inst->ex_mlen); + elk_message_ex_desc(devinfo, inst->ex_mlen); - if (ex_desc.file != BRW_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm || + if (ex_desc.file != ELK_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm || inst->send_ex_desc_scratch) { /* If we have any sort of extended descriptor, then we need SENDS. This * also covers the dual-payload case because ex_mlen goes in ex_desc. */ - brw_send_indirect_split_message(p, inst->sfid, dst, payload, payload2, + elk_send_indirect_split_message(p, inst->sfid, dst, payload, payload2, desc, desc_imm, ex_desc, ex_desc_imm, inst->send_ex_desc_scratch, inst->send_ex_bso, inst->eot); if (inst->check_tdr) - brw_inst_set_opcode(p->isa, brw_last_inst, - devinfo->ver >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC); + elk_inst_set_opcode(p->isa, elk_last_inst, + devinfo->ver >= 12 ? ELK_OPCODE_SENDC : ELK_OPCODE_SENDSC); } else { - brw_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm, + elk_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm, inst->eot); if (inst->check_tdr) - brw_inst_set_opcode(p->isa, brw_last_inst, BRW_OPCODE_SENDC); + elk_inst_set_opcode(p->isa, elk_last_inst, ELK_OPCODE_SENDC); } } void -fs_generator::fire_fb_write(fs_inst *inst, - struct brw_reg payload, - struct brw_reg implied_header, +elk_fs_generator::fire_fb_write(elk_fs_inst *inst, + struct elk_reg payload, + struct elk_reg implied_header, GLuint nr) { - struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); + struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data); if (devinfo->ver < 6) { - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1), - offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); + elk_MOV(p, offset(retype(payload, ELK_REGISTER_TYPE_UD), 1), + offset(retype(implied_header, ELK_REGISTER_TYPE_UD), 1)); + elk_pop_insn_state(p); } - uint32_t msg_control = brw_fb_write_msg_control(inst, prog_data); + uint32_t msg_control = elk_fb_write_msg_control(inst, prog_data); /* We assume render targets start at 0, because headerless FB write * messages set "Render Target Index" to 0. Using a different binding @@ -385,9 +385,9 @@ fs_generator::fire_fb_write(fs_inst *inst, */ const uint32_t surf_index = inst->target; - brw_inst *insn = brw_fb_WRITE(p, + elk_inst *insn = elk_fb_WRITE(p, payload, - retype(implied_header, BRW_REGISTER_TYPE_UW), + retype(implied_header, ELK_REGISTER_TYPE_UW), msg_control, surf_index, nr, @@ -397,22 +397,22 @@ fs_generator::fire_fb_write(fs_inst *inst, inst->header_size != 0); if (devinfo->ver >= 6) - brw_inst_set_rt_slot_group(devinfo, insn, inst->group / 16); + elk_inst_set_rt_slot_group(devinfo, insn, inst->group / 16); } void -fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) +elk_fs_generator::generate_fb_write(elk_fs_inst *inst, struct elk_reg payload) { assert(devinfo->ver < 7); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); - const struct brw_reg implied_header = - devinfo->ver < 6 ? payload : brw_null_reg(); + const struct elk_reg implied_header = + devinfo->ver < 6 ? payload : elk_null_reg(); if (inst->base_mrf >= 0) - payload = brw_message_reg(inst->base_mrf); + payload = elk_message_reg(inst->base_mrf); if (!runtime_check_aads_emit) { fire_fb_write(inst, payload, implied_header, inst->mlen); @@ -420,51 +420,51 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) /* This can only happen in gen < 6 */ assert(devinfo->ver < 6); - struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); + struct elk_reg v1_null_ud = vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD)); /* Check runtime bit to detect if we have to send AA data or not */ - brw_push_insn_state(p); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_AND(p, + elk_push_insn_state(p); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_AND(p, v1_null_ud, - retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD), - brw_imm_ud(1<<26)); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ); + retype(elk_vec1_grf(1, 6), ELK_REGISTER_TYPE_UD), + elk_imm_ud(1<<26)); + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ); - int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store; - brw_pop_insn_state(p); + int jmp = elk_JMPI(p, elk_imm_ud(0), ELK_PREDICATE_NORMAL) - p->store; + elk_pop_insn_state(p); { /* Don't send AA data */ fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1); } - brw_land_fwd_jump(p, jmp); + elk_land_fwd_jump(p, jmp); fire_fb_write(inst, payload, implied_header, inst->mlen); } } void -fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst, - struct brw_reg payload) +elk_fs_generator::generate_fb_read(elk_fs_inst *inst, struct elk_reg dst, + struct elk_reg payload) { assert(inst->size_written % REG_SIZE == 0); - struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); + struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data); /* We assume that render targets start at binding table index 0. */ const unsigned surf_index = inst->target; - gfx9_fb_READ(p, dst, payload, surf_index, + elk_gfx9_fb_READ(p, dst, payload, surf_index, inst->header_size, inst->size_written / REG_SIZE, prog_data->persample_dispatch); } void -fs_generator::generate_mov_indirect(fs_inst *inst, - struct brw_reg dst, - struct brw_reg reg, - struct brw_reg indirect_byte_offset) +elk_fs_generator::generate_mov_indirect(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg reg, + struct elk_reg indirect_byte_offset) { - assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD); - assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE); + assert(indirect_byte_offset.type == ELK_REGISTER_TYPE_UD); + assert(indirect_byte_offset.file == ELK_GENERAL_REGISTER_FILE); assert(!reg.abs && !reg.negate); /* Gen12.5 adds the following region restriction: @@ -476,38 +476,38 @@ fs_generator::generate_mov_indirect(fs_inst *inst, * unsigned integer type. */ assert(reg.type == dst.type); - reg.type = dst.type = brw_reg_type_from_bit_size(type_sz(reg.type) * 8, - BRW_REGISTER_TYPE_UD); + reg.type = dst.type = elk_reg_type_from_bit_size(type_sz(reg.type) * 8, + ELK_REGISTER_TYPE_UD); unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr; - if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) { + if (indirect_byte_offset.file == ELK_IMMEDIATE_VALUE) { imm_byte_offset += indirect_byte_offset.ud; reg.nr = imm_byte_offset / REG_SIZE; reg.subnr = imm_byte_offset % REG_SIZE; if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) { - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), - subscript(reg, BRW_REGISTER_TYPE_D, 0)); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1), - subscript(reg, BRW_REGISTER_TYPE_D, 1)); + elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 0), + subscript(reg, ELK_REGISTER_TYPE_D, 0)); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 1), + subscript(reg, ELK_REGISTER_TYPE_D, 1)); } else { - brw_MOV(p, dst, reg); + elk_MOV(p, dst, reg); } } else { /* Prior to Broadwell, there are only 8 address registers. */ assert(inst->exec_size <= 8 || devinfo->ver >= 8); /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */ - struct brw_reg addr = vec8(brw_address_reg(0)); + struct elk_reg addr = vec8(elk_address_reg(0)); /* Whether we can use destination dependency control without running the * risk of a hang if an instruction gets shot down. */ const bool use_dep_ctrl = !inst->predicate && inst->exec_size == dispatch_width; - brw_inst *insn; + elk_inst *insn; /* The destination stride of an instruction (in bytes) must be greater * than or equal to the size of the rest of the instruction. Since the @@ -515,7 +515,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst, * In order to get around this, re retype to UW and use a stride. */ indirect_byte_offset = - retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW); + retype(spread(indirect_byte_offset, 2), ELK_REGISTER_TYPE_UW); /* There are a number of reasons why we don't use the base offset here. * One reason is that the field is only 9 bits which means we can only @@ -550,20 +550,20 @@ fs_generator::generate_mov_indirect(fs_inst *inst, * instruction. */ if (devinfo->ver >= 7) { - insn = brw_MOV(p, addr, brw_imm_uw(imm_byte_offset)); - brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); - brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE); + insn = elk_MOV(p, addr, elk_imm_uw(imm_byte_offset)); + elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE); + elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NONE); if (devinfo->ver >= 12) - brw_set_default_swsb(p, tgl_swsb_null()); + elk_set_default_swsb(p, tgl_swsb_null()); else - brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl); + elk_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl); } - insn = brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset)); + insn = elk_ADD(p, addr, indirect_byte_offset, elk_imm_uw(imm_byte_offset)); if (devinfo->ver >= 12) - brw_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); else if (devinfo->ver >= 7) - brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl); + elk_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl); if (type_sz(reg.type) > 4 && ((devinfo->verx10 == 70) || @@ -584,19 +584,19 @@ fs_generator::generate_mov_indirect(fs_inst *inst, * here to handle adding 4 bytes to the offset and avoid the extra * ADD to the register file. */ - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), - retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D)); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1), - retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D)); + elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 0), + retype(elk_VxH_indirect(0, 0), ELK_REGISTER_TYPE_D)); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 1), + retype(elk_VxH_indirect(0, 4), ELK_REGISTER_TYPE_D)); } else { - struct brw_reg ind_src = brw_VxH_indirect(0, 0); + struct elk_reg ind_src = elk_VxH_indirect(0, 0); - brw_inst *mov = brw_MOV(p, dst, retype(ind_src, reg.type)); + elk_inst *mov = elk_MOV(p, dst, retype(ind_src, reg.type)); - if (devinfo->ver == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE && + if (devinfo->ver == 6 && dst.file == ELK_MESSAGE_REGISTER_FILE && !inst->get_next()->is_tail_sentinel() && - ((fs_inst *)inst->get_next())->mlen > 0) { + ((elk_fs_inst *)inst->get_next())->mlen > 0) { /* From the Sandybridge PRM: * * "[Errata: DevSNB(SNB)] If MRF register is updated by any @@ -605,19 +605,19 @@ fs_generator::generate_mov_indirect(fs_inst *inst, * avoid race condition where send may dispatch before MRF is * updated." */ - brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH); + elk_inst_set_thread_control(devinfo, mov, ELK_THREAD_SWITCH); } } } } void -fs_generator::generate_shuffle(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg idx) +elk_fs_generator::generate_shuffle(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg src, + struct elk_reg idx) { - assert(src.file == BRW_GENERAL_REGISTER_FILE); + assert(src.file == ELK_GENERAL_REGISTER_FILE); assert(!src.abs && !src.negate); /* Ivy bridge has some strange behavior that makes this a real pain to @@ -635,8 +635,8 @@ fs_generator::generate_shuffle(fs_inst *inst, * unsigned integer type. */ assert(src.type == dst.type); - src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8, - BRW_REGISTER_TYPE_UD); + src.type = dst.type = elk_reg_type_from_bit_size(type_sz(src.type) * 8, + ELK_REGISTER_TYPE_UD); /* Because we're using the address register, we're limited to 8-wide * execution on gfx7. On gfx8, we're limited to 16-wide by the address @@ -649,27 +649,27 @@ fs_generator::generate_shuffle(fs_inst *inst, devinfo->ver <= 7 || element_sz(src) > 4 || element_sz(dst) > 4 ? 8 : MIN2(16, inst->exec_size); - brw_set_default_exec_size(p, cvt(lower_width) - 1); + elk_set_default_exec_size(p, cvt(lower_width) - 1); for (unsigned group = 0; group < inst->exec_size; group += lower_width) { - brw_set_default_group(p, group); + elk_set_default_group(p, group); if ((src.vstride == 0 && src.hstride == 0) || - idx.file == BRW_IMMEDIATE_VALUE) { + idx.file == ELK_IMMEDIATE_VALUE) { /* Trivial, the source is already uniform or the index is a constant. * We will typically not get here if the optimizer is doing its job, * but asserting would be mean. */ - const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0; - struct brw_reg group_src = stride(suboffset(src, i), 0, 1, 0); - struct brw_reg group_dst = suboffset(dst, group << (dst.hstride - 1)); - brw_MOV(p, group_dst, group_src); + const unsigned i = idx.file == ELK_IMMEDIATE_VALUE ? idx.ud : 0; + struct elk_reg group_src = stride(suboffset(src, i), 0, 1, 0); + struct elk_reg group_dst = suboffset(dst, group << (dst.hstride - 1)); + elk_MOV(p, group_dst, group_src); } else { /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */ - struct brw_reg addr = vec8(brw_address_reg(0)); + struct elk_reg addr = vec8(elk_address_reg(0)); - struct brw_reg group_idx = suboffset(idx, group); + struct elk_reg group_idx = suboffset(idx, group); - if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) { + if (lower_width == 8 && group_idx.width == ELK_WIDTH_16) { /* Things get grumpy if the register is too wide. */ group_idx.width--; group_idx.vstride--; @@ -683,7 +683,7 @@ fs_generator::generate_shuffle(fs_inst *inst, * can't use a D-type instruction. In order to get around this, * re retype to UW and use a stride. */ - group_idx = retype(spread(group_idx, 2), BRW_REGISTER_TYPE_W); + group_idx = retype(spread(group_idx, 2), ELK_REGISTER_TYPE_W); } uint32_t src_start_offset = src.nr * REG_SIZE + src.subnr; @@ -705,7 +705,7 @@ fs_generator::generate_shuffle(fs_inst *inst, */ const bool use_dep_ctrl = !inst->predicate && lower_width == dispatch_width; - brw_inst *insn; + elk_inst *insn; /* Due to a hardware bug some platforms (particularly Gfx11+) seem * to require the address components of all channels to be valid @@ -714,97 +714,97 @@ fs_generator::generate_shuffle(fs_inst *inst, * around that by initializing the whole address register with a * pipelined NoMask MOV instruction. */ - insn = brw_MOV(p, addr, brw_imm_uw(src_start_offset)); - brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); - brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE); + insn = elk_MOV(p, addr, elk_imm_uw(src_start_offset)); + elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE); + elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NONE); if (devinfo->ver >= 12) - brw_set_default_swsb(p, tgl_swsb_null()); + elk_set_default_swsb(p, tgl_swsb_null()); else - brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl); + elk_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl); /* Take into account the component size and horizontal stride. */ assert(src.vstride == src.hstride + src.width); - insn = brw_SHL(p, addr, group_idx, - brw_imm_uw(util_logbase2(type_sz(src.type)) + + insn = elk_SHL(p, addr, group_idx, + elk_imm_uw(util_logbase2(type_sz(src.type)) + src.hstride - 1)); if (devinfo->ver >= 12) - brw_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); else - brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl); + elk_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl); /* Add on the register start offset */ - brw_ADD(p, addr, addr, brw_imm_uw(src_start_offset)); - brw_MOV(p, suboffset(dst, group << (dst.hstride - 1)), - retype(brw_VxH_indirect(0, 0), src.type)); + elk_ADD(p, addr, addr, elk_imm_uw(src_start_offset)); + elk_MOV(p, suboffset(dst, group << (dst.hstride - 1)), + retype(elk_VxH_indirect(0, 0), src.type)); } - brw_set_default_swsb(p, tgl_swsb_null()); + elk_set_default_swsb(p, tgl_swsb_null()); } } void -fs_generator::generate_quad_swizzle(const fs_inst *inst, - struct brw_reg dst, struct brw_reg src, +elk_fs_generator::generate_quad_swizzle(const elk_fs_inst *inst, + struct elk_reg dst, struct elk_reg src, unsigned swiz) { /* Requires a quad. */ assert(inst->exec_size >= 4); - if (src.file == BRW_IMMEDIATE_VALUE || + if (src.file == ELK_IMMEDIATE_VALUE || has_scalar_region(src)) { /* The value is uniform across all channels */ - brw_MOV(p, dst, src); + elk_MOV(p, dst, src); } else if (devinfo->ver < 11 && type_sz(src.type) == 4) { /* This only works on 8-wide 32-bit values */ assert(inst->exec_size == 8); - assert(src.hstride == BRW_HORIZONTAL_STRIDE_1); + assert(src.hstride == ELK_HORIZONTAL_STRIDE_1); assert(src.vstride == src.width + 1); - brw_set_default_access_mode(p, BRW_ALIGN_16); - struct brw_reg swiz_src = stride(src, 4, 4, 1); + elk_set_default_access_mode(p, ELK_ALIGN_16); + struct elk_reg swiz_src = stride(src, 4, 4, 1); swiz_src.swizzle = swiz; - brw_MOV(p, dst, swiz_src); + elk_MOV(p, dst, swiz_src); } else { - assert(src.hstride == BRW_HORIZONTAL_STRIDE_1); + assert(src.hstride == ELK_HORIZONTAL_STRIDE_1); assert(src.vstride == src.width + 1); - const struct brw_reg src_0 = suboffset(src, BRW_GET_SWZ(swiz, 0)); + const struct elk_reg src_0 = suboffset(src, ELK_GET_SWZ(swiz, 0)); switch (swiz) { - case BRW_SWIZZLE_XXXX: - case BRW_SWIZZLE_YYYY: - case BRW_SWIZZLE_ZZZZ: - case BRW_SWIZZLE_WWWW: - brw_MOV(p, dst, stride(src_0, 4, 4, 0)); + case ELK_SWIZZLE_XXXX: + case ELK_SWIZZLE_YYYY: + case ELK_SWIZZLE_ZZZZ: + case ELK_SWIZZLE_WWWW: + elk_MOV(p, dst, stride(src_0, 4, 4, 0)); break; - case BRW_SWIZZLE_XXZZ: - case BRW_SWIZZLE_YYWW: - brw_MOV(p, dst, stride(src_0, 2, 2, 0)); + case ELK_SWIZZLE_XXZZ: + case ELK_SWIZZLE_YYWW: + elk_MOV(p, dst, stride(src_0, 2, 2, 0)); break; - case BRW_SWIZZLE_XYXY: - case BRW_SWIZZLE_ZWZW: + case ELK_SWIZZLE_XYXY: + case ELK_SWIZZLE_ZWZW: assert(inst->exec_size == 4); - brw_MOV(p, dst, stride(src_0, 0, 2, 1)); + elk_MOV(p, dst, stride(src_0, 0, 2, 1)); break; default: assert(inst->force_writemask_all); - brw_set_default_exec_size(p, cvt(inst->exec_size / 4) - 1); + elk_set_default_exec_size(p, cvt(inst->exec_size / 4) - 1); for (unsigned c = 0; c < 4; c++) { - brw_inst *insn = brw_MOV( + elk_inst *insn = elk_MOV( p, stride(suboffset(dst, c), 4 * inst->dst.stride, 1, 4 * inst->dst.stride), - stride(suboffset(src, BRW_GET_SWZ(swiz, c)), 4, 1, 0)); + stride(suboffset(src, ELK_GET_SWZ(swiz, c)), 4, 1, 0)); if (devinfo->ver < 12) { - brw_inst_set_no_dd_clear(devinfo, insn, c < 3); - brw_inst_set_no_dd_check(devinfo, insn, c > 0); + elk_inst_set_no_dd_clear(devinfo, insn, c < 3); + elk_inst_set_no_dd_check(devinfo, insn, c > 0); } - brw_set_default_swsb(p, tgl_swsb_null()); + elk_set_default_swsb(p, tgl_swsb_null()); } break; @@ -813,60 +813,60 @@ fs_generator::generate_quad_swizzle(const fs_inst *inst, } void -fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload) +elk_fs_generator::generate_cs_terminate(elk_fs_inst *inst, struct elk_reg payload) { - struct brw_inst *insn; + struct elk_inst *insn; - insn = brw_next_insn(p, BRW_OPCODE_SEND); + insn = elk_next_insn(p, ELK_OPCODE_SEND); - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW)); - brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW)); + elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_UW)); + elk_set_src0(p, insn, retype(payload, ELK_REGISTER_TYPE_UW)); if (devinfo->ver < 12) - brw_set_src1(p, insn, brw_imm_ud(0u)); + elk_set_src1(p, insn, elk_imm_ud(0u)); /* For XeHP and newer send a message to the message gateway to terminate a * compute shader. For older devices, a message is sent to the thread * spawner. */ if (devinfo->verx10 >= 125) - brw_inst_set_sfid(devinfo, insn, BRW_SFID_MESSAGE_GATEWAY); + elk_inst_set_sfid(devinfo, insn, ELK_SFID_MESSAGE_GATEWAY); else - brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER); - brw_inst_set_mlen(devinfo, insn, 1); - brw_inst_set_rlen(devinfo, insn, 0); - brw_inst_set_eot(devinfo, insn, inst->eot); - brw_inst_set_header_present(devinfo, insn, false); + elk_inst_set_sfid(devinfo, insn, ELK_SFID_THREAD_SPAWNER); + elk_inst_set_mlen(devinfo, insn, 1); + elk_inst_set_rlen(devinfo, insn, 0); + elk_inst_set_eot(devinfo, insn, inst->eot); + elk_inst_set_header_present(devinfo, insn, false); - brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */ + elk_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */ if (devinfo->ver < 11) { - brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */ + elk_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */ /* Note that even though the thread has a URB resource associated with it, * we set the "do not dereference URB" bit, because the URB resource is * managed by the fixed-function unit, so it will free it automatically. */ - brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */ + elk_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */ } - brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); + elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE); } void -fs_generator::generate_barrier(fs_inst *, struct brw_reg src) +elk_fs_generator::generate_barrier(elk_fs_inst *, struct elk_reg src) { - brw_barrier(p, src); + elk_barrier(p, src); if (devinfo->ver >= 12) { - brw_set_default_swsb(p, tgl_swsb_null()); - brw_SYNC(p, TGL_SYNC_BAR); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_SYNC(p, TGL_SYNC_BAR); } else { - brw_WAIT(p); + elk_WAIT(p); } } bool -fs_generator::generate_linterp(fs_inst *inst, - struct brw_reg dst, struct brw_reg *src) +elk_fs_generator::generate_linterp(elk_fs_inst *inst, + struct elk_reg dst, struct elk_reg *src) { /* PLN reads: * / in SIMD16 \ @@ -888,10 +888,10 @@ fs_generator::generate_linterp(fs_inst *inst, * * See also: emit_interpolation_setup_gfx4(). */ - struct brw_reg delta_x = src[0]; - struct brw_reg delta_y = offset(src[0], inst->exec_size / 8); - struct brw_reg interp = src[1]; - brw_inst *i[2]; + struct elk_reg delta_x = src[0]; + struct elk_reg delta_y = offset(src[0], inst->exec_size / 8); + struct elk_reg interp = src[1]; + elk_inst *i[2]; /* nir_lower_interpolation() will do the lowering to MAD instructions for * us on gfx11+ @@ -915,65 +915,65 @@ fs_generator::generate_linterp(fs_inst *inst, assert(inst->exec_size == 8 || inst->exec_size == 16); assert(inst->group % 16 == 0); - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_8); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_8); /* Thanks to two accumulators, we can emit all the LINEs and then all * the MACs. This improves parallelism a bit. */ for (unsigned g = 0; g < inst->exec_size / 8; g++) { - brw_inst *line = brw_LINE(p, brw_null_reg(), interp, + elk_inst *line = elk_LINE(p, elk_null_reg(), interp, offset(delta_x, g * 2)); - brw_inst_set_group(devinfo, line, inst->group + g * 8); + elk_inst_set_group(devinfo, line, inst->group + g * 8); /* LINE writes the accumulator automatically on gfx4-5. On Sandy * Bridge and later, we have to explicitly enable it. */ if (devinfo->ver >= 6) - brw_inst_set_acc_wr_control(p->devinfo, line, true); + elk_inst_set_acc_wr_control(p->devinfo, line, true); - /* brw_set_default_saturate() is called before emitting + /* elk_set_default_saturate() is called before emitting * instructions, so the saturate bit is set in each instruction, * so we need to unset it on the LINE instructions. */ - brw_inst_set_saturate(p->devinfo, line, false); + elk_inst_set_saturate(p->devinfo, line, false); } for (unsigned g = 0; g < inst->exec_size / 8; g++) { - brw_inst *mac = brw_MAC(p, offset(dst, g), suboffset(interp, 1), + elk_inst *mac = elk_MAC(p, offset(dst, g), suboffset(interp, 1), offset(delta_x, g * 2 + 1)); - brw_inst_set_group(devinfo, mac, inst->group + g * 8); - brw_inst_set_cond_modifier(p->devinfo, mac, inst->conditional_mod); + elk_inst_set_group(devinfo, mac, inst->group + g * 8); + elk_inst_set_cond_modifier(p->devinfo, mac, inst->conditional_mod); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); return true; } else { - brw_PLN(p, dst, interp, delta_x); + elk_PLN(p, dst, interp, delta_x); return false; } } else { - i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x); - i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y); + i[0] = elk_LINE(p, elk_null_reg(), interp, delta_x); + i[1] = elk_MAC(p, dst, suboffset(interp, 1), delta_y); - brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod); + elk_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod); - /* brw_set_default_saturate() is called before emitting instructions, so + /* elk_set_default_saturate() is called before emitting instructions, so * the saturate bit is set in each instruction, so we need to unset it on * the first instruction. */ - brw_inst_set_saturate(p->devinfo, i[0], false); + elk_inst_set_saturate(p->devinfo, i[0], false); return true; } } void -fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, - struct brw_reg surface_index, - struct brw_reg sampler_index) +elk_fs_generator::generate_tex(elk_fs_inst *inst, struct elk_reg dst, + struct elk_reg surface_index, + struct elk_reg sampler_index) { assert(devinfo->ver < 7); assert(inst->size_written % REG_SIZE == 0); @@ -987,14 +987,14 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, assert(!inst->eot || inst->exec_size == dispatch_width); switch (dst.type) { - case BRW_REGISTER_TYPE_D: - return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32; + case ELK_REGISTER_TYPE_D: + return_format = ELK_SAMPLER_RETURN_FORMAT_SINT32; break; - case BRW_REGISTER_TYPE_UD: - return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; + case ELK_REGISTER_TYPE_UD: + return_format = ELK_SAMPLER_RETURN_FORMAT_UINT32; break; default: - return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; + return_format = ELK_SAMPLER_RETURN_FORMAT_FLOAT32; break; } @@ -1006,15 +1006,15 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, * the time regasrdless. Since we can really only do non-UINT32 on gfx4, * just stomp it to UINT32 all the time. */ - if (inst->opcode == SHADER_OPCODE_TXS) - return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; + if (inst->opcode == ELK_SHADER_OPCODE_TXS) + return_format = ELK_SAMPLER_RETURN_FORMAT_UINT32; switch (inst->exec_size) { case 8: - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD8; break; case 16: - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16; break; default: unreachable("Invalid width for texture instruction"); @@ -1022,49 +1022,49 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, if (devinfo->ver >= 5) { switch (inst->opcode) { - case SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TEX: if (inst->shadow_compare) { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE; } else { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE; } break; - case FS_OPCODE_TXB: + case ELK_FS_OPCODE_TXB: if (inst->shadow_compare) { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE; } else { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS; } break; - case SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL: if (inst->shadow_compare) { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; } else { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD; } break; - case SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TXS: msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO; break; - case SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXD: assert(!inst->shadow_compare); msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS; break; - case SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF: msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD; break; - case SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS: msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD; break; - case SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_LOD: msg_type = GFX5_SAMPLER_MESSAGE_LOD; break; - case SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4: assert(devinfo->ver == 6); assert(!inst->shadow_compare); msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4; break; - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_SAMPLEINFO: msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO; break; default: @@ -1072,12 +1072,12 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, } } else { switch (inst->opcode) { - case SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TEX: /* Note that G45 and older determines shadow compare and dispatch width * from message length for most messages. */ if (inst->exec_size == 8) { - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; + msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE; if (inst->shadow_compare) { assert(inst->mlen == 6); } else { @@ -1085,51 +1085,51 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, } } else { if (inst->shadow_compare) { - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE; + msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE; assert(inst->mlen == 9); } else { - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE; + msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE; assert(inst->mlen <= 7 && inst->mlen % 2 == 1); } } break; - case FS_OPCODE_TXB: + case ELK_FS_OPCODE_TXB: if (inst->shadow_compare) { assert(inst->exec_size == 8); assert(inst->mlen == 6); - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE; + msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE; } else { assert(inst->mlen == 9); - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16; } break; - case SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL: if (inst->shadow_compare) { assert(inst->exec_size == 8); assert(inst->mlen == 6); - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE; + msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE; } else { assert(inst->mlen == 9); - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD; - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16; } break; - case SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXD: /* There is no sample_d_c message; comparisons are done manually */ assert(inst->exec_size == 8); assert(inst->mlen == 7 || inst->mlen == 10); - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS; + msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS; break; - case SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF: assert(inst->mlen <= 9 && inst->mlen % 2 == 1); - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD; - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + msg_type = ELK_SAMPLER_MESSAGE_SIMD16_LD; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16; break; - case SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TXS: assert(inst->mlen == 3); - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO; - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + msg_type = ELK_SAMPLER_MESSAGE_SIMD16_RESINFO; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16; break; default: unreachable("not reached"); @@ -1137,52 +1137,52 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, } assert(msg_type != -1); - if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) { + if (simd_mode == ELK_SAMPLER_SIMD_MODE_SIMD16) { dst = vec16(dst); } - assert(sampler_index.type == BRW_REGISTER_TYPE_UD); + assert(sampler_index.type == ELK_REGISTER_TYPE_UD); /* Load the message header if present. If there's a texture offset, * we need to set it up explicitly and load the offset bitfield. * Otherwise, we can use an implied move from g0 to the first message reg. */ - struct brw_reg src = brw_null_reg(); + struct elk_reg src = elk_null_reg(); if (inst->header_size != 0) { if (devinfo->ver < 6 && !inst->offset) { /* Set up an implied move from g0 to the MRF. */ - src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); + src = retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UW); } else { - const tgl_swsb swsb = brw_get_default_swsb(p); + const tgl_swsb swsb = elk_get_default_swsb(p); assert(inst->base_mrf != -1); - struct brw_reg header_reg = brw_message_reg(inst->base_mrf); + struct elk_reg header_reg = elk_message_reg(inst->base_mrf); - brw_push_insn_state(p); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); + elk_push_insn_state(p); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_compression_control(p, ELK_COMPRESSION_NONE); /* Explicitly set up the message header by copying g0 to the MRF. */ - brw_MOV(p, header_reg, brw_vec8_grf(0, 0)); - brw_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_MOV(p, header_reg, elk_vec8_grf(0, 0)); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); - brw_set_default_exec_size(p, BRW_EXECUTE_1); + elk_set_default_exec_size(p, ELK_EXECUTE_1); if (inst->offset) { /* Set the offset bits in DWord 2. */ - brw_MOV(p, get_element_ud(header_reg, 2), - brw_imm_ud(inst->offset)); + elk_MOV(p, get_element_ud(header_reg, 2), + elk_imm_ud(inst->offset)); } - brw_pop_insn_state(p); - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + elk_pop_insn_state(p); + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); } } - assert(surface_index.file == BRW_IMMEDIATE_VALUE); - assert(sampler_index.file == BRW_IMMEDIATE_VALUE); + assert(surface_index.file == ELK_IMMEDIATE_VALUE); + assert(sampler_index.file == ELK_IMMEDIATE_VALUE); - brw_SAMPLE(p, - retype(dst, BRW_REGISTER_TYPE_UW), + elk_SAMPLE(p, + retype(dst, ELK_REGISTER_TYPE_UW), inst->base_mrf, src, surface_index.ud, @@ -1225,33 +1225,33 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, * appropriate swizzling. */ void -fs_generator::generate_ddx(const fs_inst *inst, - struct brw_reg dst, struct brw_reg src) +elk_fs_generator::generate_ddx(const elk_fs_inst *inst, + struct elk_reg dst, struct elk_reg src) { unsigned vstride, width; if (devinfo->ver >= 8) { - if (inst->opcode == FS_OPCODE_DDX_FINE) { + if (inst->opcode == ELK_FS_OPCODE_DDX_FINE) { /* produce accurate derivatives */ - vstride = BRW_VERTICAL_STRIDE_2; - width = BRW_WIDTH_2; + vstride = ELK_VERTICAL_STRIDE_2; + width = ELK_WIDTH_2; } else { /* replicate the derivative at the top-left pixel to other pixels */ - vstride = BRW_VERTICAL_STRIDE_4; - width = BRW_WIDTH_4; + vstride = ELK_VERTICAL_STRIDE_4; + width = ELK_WIDTH_4; } - struct brw_reg src0 = byte_offset(src, type_sz(src.type));; - struct brw_reg src1 = src; + struct elk_reg src0 = byte_offset(src, type_sz(src.type));; + struct elk_reg src1 = src; src0.vstride = vstride; src0.width = width; - src0.hstride = BRW_HORIZONTAL_STRIDE_0; + src0.hstride = ELK_HORIZONTAL_STRIDE_0; src1.vstride = vstride; src1.width = width; - src1.hstride = BRW_HORIZONTAL_STRIDE_0; + src1.hstride = ELK_HORIZONTAL_STRIDE_0; - brw_ADD(p, dst, src0, negate(src1)); + elk_ADD(p, dst, src0, negate(src1)); } else { /* On Haswell and earlier, the region used above appears to not work * correctly for compressed instructions. At least on Haswell and @@ -1259,20 +1259,20 @@ fs_generator::generate_ddx(const fs_inst *inst, * would have to split to SIMD8 no matter which method we choose, we * may as well use ALIGN16 on all platforms gfx7 and earlier. */ - struct brw_reg src0 = stride(src, 4, 4, 1); - struct brw_reg src1 = stride(src, 4, 4, 1); - if (inst->opcode == FS_OPCODE_DDX_FINE) { - src0.swizzle = BRW_SWIZZLE_XXZZ; - src1.swizzle = BRW_SWIZZLE_YYWW; + struct elk_reg src0 = stride(src, 4, 4, 1); + struct elk_reg src1 = stride(src, 4, 4, 1); + if (inst->opcode == ELK_FS_OPCODE_DDX_FINE) { + src0.swizzle = ELK_SWIZZLE_XXZZ; + src1.swizzle = ELK_SWIZZLE_YYWW; } else { - src0.swizzle = BRW_SWIZZLE_XXXX; - src1.swizzle = BRW_SWIZZLE_YYYY; + src0.swizzle = ELK_SWIZZLE_XXXX; + src1.swizzle = ELK_SWIZZLE_YYYY; } - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_ADD(p, dst, negate(src0), src1); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_ADD(p, dst, negate(src0), src1); + elk_pop_insn_state(p); } } @@ -1281,12 +1281,12 @@ fs_generator::generate_ddx(const fs_inst *inst, * left. */ void -fs_generator::generate_ddy(const fs_inst *inst, - struct brw_reg dst, struct brw_reg src) +elk_fs_generator::generate_ddy(const elk_fs_inst *inst, + struct elk_reg dst, struct elk_reg src) { const uint32_t type_size = type_sz(src.type); - if (inst->opcode == FS_OPCODE_DDY_FINE) { + if (inst->opcode == ELK_FS_OPCODE_DDY_FINE) { /* produce accurate derivatives. * * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU) @@ -1301,37 +1301,37 @@ fs_generator::generate_ddy(const fs_inst *inst, * inherits its FP16 hardware from SKL, so it is not affected. */ if (devinfo->ver >= 11 || - (devinfo->platform == INTEL_PLATFORM_BDW && src.type == BRW_REGISTER_TYPE_HF)) { + (devinfo->platform == INTEL_PLATFORM_BDW && src.type == ELK_REGISTER_TYPE_HF)) { src = stride(src, 0, 2, 1); - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_4); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_4); for (uint32_t g = 0; g < inst->exec_size; g += 4) { - brw_set_default_group(p, inst->group + g); - brw_ADD(p, byte_offset(dst, g * type_size), + elk_set_default_group(p, inst->group + g); + elk_ADD(p, byte_offset(dst, g * type_size), negate(byte_offset(src, g * type_size)), byte_offset(src, (g + 2) * type_size)); - brw_set_default_swsb(p, tgl_swsb_null()); + elk_set_default_swsb(p, tgl_swsb_null()); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } else { - struct brw_reg src0 = stride(src, 4, 4, 1); - struct brw_reg src1 = stride(src, 4, 4, 1); - src0.swizzle = BRW_SWIZZLE_XYXY; - src1.swizzle = BRW_SWIZZLE_ZWZW; + struct elk_reg src0 = stride(src, 4, 4, 1); + struct elk_reg src1 = stride(src, 4, 4, 1); + src0.swizzle = ELK_SWIZZLE_XYXY; + src1.swizzle = ELK_SWIZZLE_ZWZW; - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_ADD(p, dst, negate(src0), src1); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_ADD(p, dst, negate(src0), src1); + elk_pop_insn_state(p); } } else { /* replicate the derivative at the top-left pixel to other pixels */ if (devinfo->ver >= 8) { - struct brw_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size); - struct brw_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size); + struct elk_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size); + struct elk_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size); - brw_ADD(p, dst, negate(src0), src1); + elk_ADD(p, dst, negate(src0), src1); } else { /* On Haswell and earlier, the region used above appears to not work * correctly for compressed instructions. At least on Haswell and @@ -1339,32 +1339,32 @@ fs_generator::generate_ddy(const fs_inst *inst, * would have to split to SIMD8 no matter which method we choose, we * may as well use ALIGN16 on all platforms gfx7 and earlier. */ - struct brw_reg src0 = stride(src, 4, 4, 1); - struct brw_reg src1 = stride(src, 4, 4, 1); - src0.swizzle = BRW_SWIZZLE_XXXX; - src1.swizzle = BRW_SWIZZLE_ZZZZ; + struct elk_reg src0 = stride(src, 4, 4, 1); + struct elk_reg src1 = stride(src, 4, 4, 1); + src0.swizzle = ELK_SWIZZLE_XXXX; + src1.swizzle = ELK_SWIZZLE_ZZZZ; - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_ADD(p, dst, negate(src0), src1); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_ADD(p, dst, negate(src0), src1); + elk_pop_insn_state(p); } } } void -fs_generator::generate_halt(fs_inst *) +elk_fs_generator::generate_halt(elk_fs_inst *) { /* This HALT will be patched up at FB write time to point UIP at the end of - * the program, and at brw_uip_jip() JIP will be set to the end of the + * the program, and at elk_uip_jip() JIP will be set to the end of the * current block (or the program). */ this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn)); - brw_HALT(p); + elk_HALT(p); } void -fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src) +elk_fs_generator::generate_scratch_write(elk_fs_inst *inst, struct elk_reg src) { /* The 32-wide messages only respect the first 16-wide half of the channel * enable signals which are replicated identically for the second group of @@ -1374,51 +1374,51 @@ fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src) const unsigned lower_size = inst->force_writemask_all ? inst->exec_size : MIN2(16, inst->exec_size); const unsigned block_size = 4 * lower_size / REG_SIZE; - const tgl_swsb swsb = brw_get_default_swsb(p); + const tgl_swsb swsb = elk_get_default_swsb(p); assert(inst->mlen != 0); - brw_push_insn_state(p); - brw_set_default_exec_size(p, cvt(lower_size) - 1); - brw_set_default_compression(p, lower_size > 8); + elk_push_insn_state(p); + elk_set_default_exec_size(p, cvt(lower_size) - 1); + elk_set_default_compression(p, lower_size > 8); for (unsigned i = 0; i < inst->exec_size / lower_size; i++) { - brw_set_default_group(p, inst->group + lower_size * i); + elk_set_default_group(p, inst->group + lower_size * i); if (i > 0) { assert(swsb.mode & TGL_SBID_SET); - brw_set_default_swsb(p, tgl_swsb_sbid(TGL_SBID_SRC, swsb.sbid)); + elk_set_default_swsb(p, tgl_swsb_sbid(TGL_SBID_SRC, swsb.sbid)); } else { - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); } - brw_MOV(p, brw_uvec_mrf(lower_size, inst->base_mrf + 1, 0), - retype(offset(src, block_size * i), BRW_REGISTER_TYPE_UD)); + elk_MOV(p, elk_uvec_mrf(lower_size, inst->base_mrf + 1, 0), + retype(offset(src, block_size * i), ELK_REGISTER_TYPE_UD)); - brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); - brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), + elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1)); + elk_oword_block_write_scratch(p, elk_message_reg(inst->base_mrf), block_size, inst->offset + block_size * REG_SIZE * i); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } void -fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst) +elk_fs_generator::generate_scratch_read(elk_fs_inst *inst, struct elk_reg dst) { assert(inst->exec_size <= 16 || inst->force_writemask_all); assert(inst->mlen != 0); - brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), + elk_oword_block_read_scratch(p, dst, elk_message_reg(inst->base_mrf), inst->exec_size / 8, inst->offset); } void -fs_generator::generate_scratch_read_gfx7(fs_inst *inst, struct brw_reg dst) +elk_fs_generator::generate_scratch_read_gfx7(elk_fs_inst *inst, struct elk_reg dst) { assert(inst->exec_size <= 16 || inst->force_writemask_all); - gfx7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset); + elk_gfx7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset); } /* The A32 messages take a buffer base address in header.5:[31:0] (See @@ -1460,78 +1460,78 @@ fs_generator::generate_scratch_read_gfx7(fs_inst *inst, struct brw_reg dst) * information required by either set of opcodes. */ void -fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst) +elk_fs_generator::generate_scratch_header(elk_fs_inst *inst, struct elk_reg dst) { assert(inst->exec_size == 8 && inst->force_writemask_all); - assert(dst.file == BRW_GENERAL_REGISTER_FILE); + assert(dst.file == ELK_GENERAL_REGISTER_FILE); - dst.type = BRW_REGISTER_TYPE_UD; + dst.type = ELK_REGISTER_TYPE_UD; - brw_inst *insn = brw_MOV(p, dst, brw_imm_ud(0)); + elk_inst *insn = elk_MOV(p, dst, elk_imm_ud(0)); if (devinfo->ver >= 12) - brw_set_default_swsb(p, tgl_swsb_null()); + elk_set_default_swsb(p, tgl_swsb_null()); else - brw_inst_set_no_dd_clear(p->devinfo, insn, true); + elk_inst_set_no_dd_clear(p->devinfo, insn, true); /* Copy the per-thread scratch space size from g0.3[3:0] */ - brw_set_default_exec_size(p, BRW_EXECUTE_1); - insn = brw_AND(p, suboffset(dst, 3), - retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(3, 0))); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + insn = elk_AND(p, suboffset(dst, 3), + retype(elk_vec1_grf(0, 3), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(3, 0))); if (devinfo->ver < 12) { - brw_inst_set_no_dd_clear(p->devinfo, insn, true); - brw_inst_set_no_dd_check(p->devinfo, insn, true); + elk_inst_set_no_dd_clear(p->devinfo, insn, true); + elk_inst_set_no_dd_check(p->devinfo, insn, true); } /* Copy the scratch base address from g0.5[31:10] */ - insn = brw_AND(p, suboffset(dst, 5), - retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(31, 10))); + insn = elk_AND(p, suboffset(dst, 5), + retype(elk_vec1_grf(0, 5), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(31, 10))); if (devinfo->ver < 12) - brw_inst_set_no_dd_check(p->devinfo, insn, true); + elk_inst_set_no_dd_check(p->devinfo, insn, true); } void -fs_generator::generate_uniform_pull_constant_load(fs_inst *inst, - struct brw_reg dst, - struct brw_reg index, - struct brw_reg offset) +elk_fs_generator::generate_uniform_pull_constant_load(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg index, + struct elk_reg offset) { assert(type_sz(dst.type) == 4); assert(inst->mlen != 0); - assert(index.file == BRW_IMMEDIATE_VALUE && - index.type == BRW_REGISTER_TYPE_UD); + assert(index.file == ELK_IMMEDIATE_VALUE && + index.type == ELK_REGISTER_TYPE_UD); uint32_t surf_index = index.ud; - assert(offset.file == BRW_IMMEDIATE_VALUE && - offset.type == BRW_REGISTER_TYPE_UD); + assert(offset.file == ELK_IMMEDIATE_VALUE && + offset.type == ELK_REGISTER_TYPE_UD); uint32_t read_offset = offset.ud; - brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf), + elk_oword_block_read(p, dst, elk_message_reg(inst->base_mrf), read_offset, surf_index); } void -fs_generator::generate_varying_pull_constant_load_gfx4(fs_inst *inst, - struct brw_reg dst, - struct brw_reg index) +elk_fs_generator::generate_varying_pull_constant_load_gfx4(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg index) { assert(devinfo->ver < 7); /* Should use the gfx7 variant. */ assert(inst->header_size != 0); assert(inst->mlen); - assert(index.file == BRW_IMMEDIATE_VALUE && - index.type == BRW_REGISTER_TYPE_UD); + assert(index.file == ELK_IMMEDIATE_VALUE && + index.type == ELK_REGISTER_TYPE_UD); uint32_t surf_index = index.ud; uint32_t simd_mode, rlen, msg_type; if (inst->exec_size == 16) { - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16; rlen = 8; } else { assert(inst->exec_size == 8); - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD8; rlen = 4; } @@ -1541,31 +1541,31 @@ fs_generator::generate_varying_pull_constant_load_gfx4(fs_inst *inst, /* We always use the SIMD16 message so that we only have to load U, and * not V or R. */ - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD; + msg_type = ELK_SAMPLER_MESSAGE_SIMD16_LD; assert(inst->mlen == 3); assert(inst->size_written == 8 * REG_SIZE); rlen = 8; - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16; } - struct brw_reg header = brw_vec8_grf(0, 0); - gfx6_resolve_implied_move(p, &header, inst->base_mrf); + struct elk_reg header = elk_vec8_grf(0, 0); + elk_gfx6_resolve_implied_move(p, &header, inst->base_mrf); - brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); - brw_inst_set_compression(devinfo, send, false); - brw_inst_set_sfid(devinfo, send, BRW_SFID_SAMPLER); - brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW)); - brw_set_src0(p, send, header); + elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND); + elk_inst_set_compression(devinfo, send, false); + elk_inst_set_sfid(devinfo, send, ELK_SFID_SAMPLER); + elk_set_dest(p, send, retype(dst, ELK_REGISTER_TYPE_UW)); + elk_set_src0(p, send, header); if (devinfo->ver < 6) - brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf); + elk_inst_set_base_mrf(p->devinfo, send, inst->base_mrf); /* Our surface is set up as floats, regardless of what actual data is * stored in it. */ - uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; - brw_set_desc(p, send, - brw_message_desc(devinfo, inst->mlen, rlen, inst->header_size) | - brw_sampler_desc(devinfo, surf_index, + uint32_t return_format = ELK_SAMPLER_RETURN_FORMAT_FLOAT32; + elk_set_desc(p, send, + elk_message_desc(devinfo, inst->mlen, rlen, inst->header_size) | + elk_sampler_desc(devinfo, surf_index, 0, /* sampler (unused) */ msg_type, simd_mode, return_format)); } @@ -1574,62 +1574,62 @@ fs_generator::generate_varying_pull_constant_load_gfx4(fs_inst *inst, * the ADD instruction. */ void -fs_generator::generate_set_sample_id(fs_inst *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1) +elk_fs_generator::generate_set_sample_id(elk_fs_inst *inst, + struct elk_reg dst, + struct elk_reg src0, + struct elk_reg src1) { - assert(dst.type == BRW_REGISTER_TYPE_D || - dst.type == BRW_REGISTER_TYPE_UD); - assert(src0.type == BRW_REGISTER_TYPE_D || - src0.type == BRW_REGISTER_TYPE_UD); + assert(dst.type == ELK_REGISTER_TYPE_D || + dst.type == ELK_REGISTER_TYPE_UD); + assert(src0.type == ELK_REGISTER_TYPE_D || + src0.type == ELK_REGISTER_TYPE_UD); - const struct brw_reg reg = stride(src1, 1, 4, 0); + const struct elk_reg reg = stride(src1, 1, 4, 0); const unsigned lower_size = MIN2(inst->exec_size, devinfo->ver >= 8 ? 16 : 8); for (unsigned i = 0; i < inst->exec_size / lower_size; i++) { - brw_inst *insn = brw_ADD(p, offset(dst, i * lower_size / 8), + elk_inst *insn = elk_ADD(p, offset(dst, i * lower_size / 8), offset(src0, (src0.vstride == 0 ? 0 : (1 << (src0.vstride - 1)) * (i * lower_size / (1 << src0.width))) * type_sz(src0.type) / REG_SIZE), suboffset(reg, i * lower_size / 4)); - brw_inst_set_exec_size(devinfo, insn, cvt(lower_size) - 1); - brw_inst_set_group(devinfo, insn, inst->group + lower_size * i); - brw_inst_set_compression(devinfo, insn, lower_size > 8); - brw_set_default_swsb(p, tgl_swsb_null()); + elk_inst_set_exec_size(devinfo, insn, cvt(lower_size) - 1); + elk_inst_set_group(devinfo, insn, inst->group + lower_size * i); + elk_inst_set_compression(devinfo, insn, lower_size > 8); + elk_set_default_swsb(p, tgl_swsb_null()); } } void -fs_generator::enable_debug(const char *shader_name) +elk_fs_generator::enable_debug(const char *shader_name) { debug_flag = true; this->shader_name = shader_name; } -static gfx12_systolic_depth +static elk_gfx12_systolic_depth translate_systolic_depth(unsigned d) { /* Could also return (ffs(d) - 1) & 3. */ switch (d) { - case 2: return BRW_SYSTOLIC_DEPTH_2; - case 4: return BRW_SYSTOLIC_DEPTH_4; - case 8: return BRW_SYSTOLIC_DEPTH_8; - case 16: return BRW_SYSTOLIC_DEPTH_16; + case 2: return ELK_SYSTOLIC_DEPTH_2; + case 4: return ELK_SYSTOLIC_DEPTH_4; + case 8: return ELK_SYSTOLIC_DEPTH_8; + case 16: return ELK_SYSTOLIC_DEPTH_16; default: unreachable("Invalid systolic depth."); } } int -fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, +elk_fs_generator::generate_code(const elk_cfg_t *cfg, int dispatch_width, struct shader_stats shader_stats, const elk::performance &perf, - struct brw_compile_stats *stats, + struct elk_compile_stats *stats, unsigned max_polygons) { /* align to 64 byte boundary. */ - brw_realign(p, 64); + elk_realign(p, 64); this->dispatch_width = dispatch_width; @@ -1638,13 +1638,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, int loop_count = 0, send_count = 0, nop_count = 0, sync_nop_count = 0; bool is_accum_used = false; - struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg); + struct elk_disasm_info *elk_disasm_info = elk_disasm_initialize(p->isa, cfg); - foreach_block_and_inst (block, fs_inst, inst, cfg) { - if (inst->opcode == SHADER_OPCODE_UNDEF) + foreach_block_and_inst (block, elk_fs_inst, inst, cfg) { + if (inst->opcode == ELK_SHADER_OPCODE_UNDEF) continue; - struct brw_reg src[4], dst; + struct elk_reg src[4], dst; unsigned int last_insn_offset = p->next_insn_offset; bool multiple_instructions_emitted = false; tgl_swsb swsb = inst->sched; @@ -1661,10 +1661,10 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, if (devinfo->ver >= 8 && devinfo->ver <= 9 && p->nr_insn > 1 && - brw_inst_opcode(p->isa, brw_last_inst) == BRW_OPCODE_MATH && - brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW && + elk_inst_opcode(p->isa, elk_last_inst) == ELK_OPCODE_MATH && + elk_inst_math_function(devinfo, elk_last_inst) == ELK_MATH_FUNCTION_POW && inst->dst.component_size(inst->exec_size) > REG_SIZE) { - brw_NOP(p); + elk_NOP(p); last_insn_offset = p->next_insn_offset; /* In order to avoid spurious instruction count differences when the @@ -1680,13 +1680,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, */ if (inst->eot && is_accum_used && intel_needs_workaround(devinfo, 14010017096)) { - brw_set_default_exec_size(p, BRW_EXECUTE_16); - brw_set_default_group(p, 0); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); - brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f)); + elk_set_default_exec_size(p, ELK_EXECUTE_16); + elk_set_default_group(p, 0); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_MOV(p, elk_acc_reg(8), elk_imm_f(0.0f)); last_insn_offset = p->next_insn_offset; swsb = tgl_swsb_dst_dep(swsb, 1); } @@ -1702,12 +1702,12 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, */ if (inst->eot && intel_needs_workaround(devinfo, 14013672992)) { if (tgl_swsb_src_dep(swsb).mode) { - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); - brw_SYNC(p, TGL_SYNC_NOP); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_swsb(p, tgl_swsb_src_dep(swsb)); + elk_SYNC(p, TGL_SYNC_NOP); last_insn_offset = p->next_insn_offset; } @@ -1715,7 +1715,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, } if (unlikely(debug_flag)) - disasm_annotate(disasm_info, inst, p->next_insn_offset); + elk_disasm_annotate(elk_disasm_info, inst, p->next_insn_offset); /* If the instruction writes to more than one register, it needs to be * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the @@ -1732,21 +1732,21 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, */ const bool compressed = inst->dst.component_size(inst->exec_size) > REG_SIZE; - brw_set_default_compression(p, compressed); + elk_set_default_compression(p, compressed); if ((devinfo->ver >= 20 || devinfo->ver < 7) && inst->group % 8 != 0) { assert(inst->force_writemask_all); assert(!inst->predicate && !inst->conditional_mod); assert(!inst->writes_accumulator_implicitly(devinfo) && !inst->reads_accumulator_implicitly()); - assert(inst->opcode != SHADER_OPCODE_SEL_EXEC); - brw_set_default_group(p, 0); + assert(inst->opcode != ELK_SHADER_OPCODE_SEL_EXEC); + elk_set_default_group(p, 0); } else { - brw_set_default_group(p, inst->group); + elk_set_default_group(p, inst->group); } for (unsigned int i = 0; i < inst->sources; i++) { - src[i] = brw_reg_from_fs_reg(devinfo, inst, + src[i] = elk_reg_from_fs_reg(devinfo, inst, &inst->src[i], compressed); /* The accumulator result appears to get used for the * conditional modifier generation. When negating a UD @@ -1755,33 +1755,33 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, * equality with a 32-bit value. See piglit fs-op-neg-uvec4. */ assert(!inst->conditional_mod || - inst->src[i].type != BRW_REGISTER_TYPE_UD || + inst->src[i].type != ELK_REGISTER_TYPE_UD || !inst->src[i].negate); } - dst = brw_reg_from_fs_reg(devinfo, inst, + dst = elk_reg_from_fs_reg(devinfo, inst, &inst->dst, compressed); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_predicate_control(p, inst->predicate); - brw_set_default_predicate_inverse(p, inst->predicate_inverse); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_predicate_control(p, inst->predicate); + elk_set_default_predicate_inverse(p, inst->predicate_inverse); /* On gfx7 and above, hardware automatically adds the group onto the * flag subregister number. On Sandy Bridge and older, we have to do it * ourselves. */ const unsigned flag_subreg = inst->flag_subreg + (devinfo->ver >= 7 ? 0 : inst->group / 16); - brw_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2); - brw_set_default_saturate(p, inst->saturate); - brw_set_default_mask_control(p, inst->force_writemask_all); + elk_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2); + elk_set_default_saturate(p, inst->saturate); + elk_set_default_mask_control(p, inst->force_writemask_all); if (devinfo->ver >= 20 && inst->writes_accumulator) { assert(inst->dst.is_accumulator() || - inst->opcode == BRW_OPCODE_ADDC || - inst->opcode == BRW_OPCODE_MACH || - inst->opcode == BRW_OPCODE_SUBB); + inst->opcode == ELK_OPCODE_ADDC || + inst->opcode == ELK_OPCODE_MACH || + inst->opcode == ELK_OPCODE_SUBB); } else { - brw_set_default_acc_write_control(p, inst->writes_accumulator); + elk_set_default_acc_write_control(p, inst->writes_accumulator); } - brw_set_default_swsb(p, swsb); + elk_set_default_swsb(p, swsb); unsigned exec_size = inst->exec_size; if (devinfo->verx10 == 70 && @@ -1789,369 +1789,368 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, exec_size *= 2; } - brw_set_default_exec_size(p, cvt(exec_size) - 1); + elk_set_default_exec_size(p, cvt(exec_size) - 1); assert(inst->force_writemask_all || inst->exec_size >= 4); assert(inst->force_writemask_all || inst->group % inst->exec_size == 0); - assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->ver)); - assert(inst->mlen <= BRW_MAX_MSG_LENGTH * reg_unit(devinfo)); + assert(inst->base_mrf + inst->mlen <= ELK_MAX_MRF(devinfo->ver)); + assert(inst->mlen <= ELK_MAX_MSG_LENGTH * reg_unit(devinfo)); switch (inst->opcode) { - case BRW_OPCODE_SYNC: - assert(src[0].file == BRW_IMMEDIATE_VALUE); - brw_SYNC(p, tgl_sync_function(src[0].ud)); + case ELK_OPCODE_SYNC: + assert(src[0].file == ELK_IMMEDIATE_VALUE); + elk_SYNC(p, tgl_sync_function(src[0].ud)); if (tgl_sync_function(src[0].ud) == TGL_SYNC_NOP) ++sync_nop_count; - break; - case BRW_OPCODE_MOV: - brw_MOV(p, dst, src[0]); + case ELK_OPCODE_MOV: + elk_MOV(p, dst, src[0]); break; - case BRW_OPCODE_ADD: - brw_ADD(p, dst, src[0], src[1]); + case ELK_OPCODE_ADD: + elk_ADD(p, dst, src[0], src[1]); break; - case BRW_OPCODE_MUL: - brw_MUL(p, dst, src[0], src[1]); + case ELK_OPCODE_MUL: + elk_MUL(p, dst, src[0], src[1]); break; - case BRW_OPCODE_AVG: - brw_AVG(p, dst, src[0], src[1]); + case ELK_OPCODE_AVG: + elk_AVG(p, dst, src[0], src[1]); break; - case BRW_OPCODE_MACH: - brw_MACH(p, dst, src[0], src[1]); + case ELK_OPCODE_MACH: + elk_MACH(p, dst, src[0], src[1]); break; - case BRW_OPCODE_DP4A: + case ELK_OPCODE_DP4A: assert(devinfo->ver >= 12); - brw_DP4A(p, dst, src[0], src[1], src[2]); + elk_DP4A(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_LINE: - brw_LINE(p, dst, src[0], src[1]); + case ELK_OPCODE_LINE: + elk_LINE(p, dst, src[0], src[1]); break; - case BRW_OPCODE_DPAS: + case ELK_OPCODE_DPAS: assert(devinfo->verx10 >= 125); - brw_DPAS(p, translate_systolic_depth(inst->sdepth), inst->rcount, + elk_DPAS(p, translate_systolic_depth(inst->sdepth), inst->rcount, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_MAD: + case ELK_OPCODE_MAD: assert(devinfo->ver >= 6); if (devinfo->ver < 10) - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_MAD(p, dst, src[0], src[1], src[2]); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_MAD(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_LRP: + case ELK_OPCODE_LRP: assert(devinfo->ver >= 6 && devinfo->ver <= 10); if (devinfo->ver < 10) - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_LRP(p, dst, src[0], src[1], src[2]); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_LRP(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_ADD3: + case ELK_OPCODE_ADD3: assert(devinfo->verx10 >= 125); - brw_ADD3(p, dst, src[0], src[1], src[2]); + elk_ADD3(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_FRC: - brw_FRC(p, dst, src[0]); + case ELK_OPCODE_FRC: + elk_FRC(p, dst, src[0]); break; - case BRW_OPCODE_RNDD: - brw_RNDD(p, dst, src[0]); + case ELK_OPCODE_RNDD: + elk_RNDD(p, dst, src[0]); break; - case BRW_OPCODE_RNDE: - brw_RNDE(p, dst, src[0]); + case ELK_OPCODE_RNDE: + elk_RNDE(p, dst, src[0]); break; - case BRW_OPCODE_RNDZ: - brw_RNDZ(p, dst, src[0]); + case ELK_OPCODE_RNDZ: + elk_RNDZ(p, dst, src[0]); break; - case BRW_OPCODE_AND: - brw_AND(p, dst, src[0], src[1]); + case ELK_OPCODE_AND: + elk_AND(p, dst, src[0], src[1]); break; - case BRW_OPCODE_OR: - brw_OR(p, dst, src[0], src[1]); + case ELK_OPCODE_OR: + elk_OR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_XOR: - brw_XOR(p, dst, src[0], src[1]); + case ELK_OPCODE_XOR: + elk_XOR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_NOT: - brw_NOT(p, dst, src[0]); + case ELK_OPCODE_NOT: + elk_NOT(p, dst, src[0]); break; - case BRW_OPCODE_ASR: - brw_ASR(p, dst, src[0], src[1]); + case ELK_OPCODE_ASR: + elk_ASR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_SHR: - brw_SHR(p, dst, src[0], src[1]); + case ELK_OPCODE_SHR: + elk_SHR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_SHL: - brw_SHL(p, dst, src[0], src[1]); + case ELK_OPCODE_SHL: + elk_SHL(p, dst, src[0], src[1]); break; - case BRW_OPCODE_ROL: + case ELK_OPCODE_ROL: assert(devinfo->ver >= 11); assert(src[0].type == dst.type); - brw_ROL(p, dst, src[0], src[1]); + elk_ROL(p, dst, src[0], src[1]); break; - case BRW_OPCODE_ROR: + case ELK_OPCODE_ROR: assert(devinfo->ver >= 11); assert(src[0].type == dst.type); - brw_ROR(p, dst, src[0], src[1]); + elk_ROR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_F32TO16: - brw_F32TO16(p, dst, src[0]); + case ELK_OPCODE_F32TO16: + elk_F32TO16(p, dst, src[0]); break; - case BRW_OPCODE_F16TO32: - brw_F16TO32(p, dst, src[0]); + case ELK_OPCODE_F16TO32: + elk_F16TO32(p, dst, src[0]); break; - case BRW_OPCODE_CMP: + case ELK_OPCODE_CMP: if (inst->exec_size >= 16 && devinfo->verx10 == 70 && - dst.file == BRW_ARCHITECTURE_REGISTER_FILE) { + dst.file == ELK_ARCHITECTURE_REGISTER_FILE) { /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround * implemented in the compiler is not sufficient. Overriding the * type when the destination is the null register is necessary but * not sufficient by itself. */ - dst.type = BRW_REGISTER_TYPE_D; + dst.type = ELK_REGISTER_TYPE_D; } - brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); + elk_CMP(p, dst, inst->conditional_mod, src[0], src[1]); break; - case BRW_OPCODE_CMPN: + case ELK_OPCODE_CMPN: if (inst->exec_size >= 16 && devinfo->verx10 == 70 && - dst.file == BRW_ARCHITECTURE_REGISTER_FILE) { + dst.file == ELK_ARCHITECTURE_REGISTER_FILE) { /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround * implemented in the compiler is not sufficient. Overriding the * type when the destination is the null register is necessary but * not sufficient by itself. */ - dst.type = BRW_REGISTER_TYPE_D; + dst.type = ELK_REGISTER_TYPE_D; } - brw_CMPN(p, dst, inst->conditional_mod, src[0], src[1]); + elk_CMPN(p, dst, inst->conditional_mod, src[0], src[1]); break; - case BRW_OPCODE_SEL: - brw_SEL(p, dst, src[0], src[1]); + case ELK_OPCODE_SEL: + elk_SEL(p, dst, src[0], src[1]); break; - case BRW_OPCODE_CSEL: + case ELK_OPCODE_CSEL: assert(devinfo->ver >= 8); if (devinfo->ver < 10) - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_CSEL(p, dst, src[0], src[1], src[2]); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_CSEL(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_BFREV: + case ELK_OPCODE_BFREV: assert(devinfo->ver >= 7); - brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD), - retype(src[0], BRW_REGISTER_TYPE_UD)); + elk_BFREV(p, retype(dst, ELK_REGISTER_TYPE_UD), + retype(src[0], ELK_REGISTER_TYPE_UD)); break; - case BRW_OPCODE_FBH: + case ELK_OPCODE_FBH: assert(devinfo->ver >= 7); - brw_FBH(p, retype(dst, src[0].type), src[0]); + elk_FBH(p, retype(dst, src[0].type), src[0]); break; - case BRW_OPCODE_FBL: + case ELK_OPCODE_FBL: assert(devinfo->ver >= 7); - brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), - retype(src[0], BRW_REGISTER_TYPE_UD)); + elk_FBL(p, retype(dst, ELK_REGISTER_TYPE_UD), + retype(src[0], ELK_REGISTER_TYPE_UD)); break; - case BRW_OPCODE_LZD: - brw_LZD(p, dst, src[0]); + case ELK_OPCODE_LZD: + elk_LZD(p, dst, src[0]); break; - case BRW_OPCODE_CBIT: + case ELK_OPCODE_CBIT: assert(devinfo->ver >= 7); - brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), - retype(src[0], BRW_REGISTER_TYPE_UD)); + elk_CBIT(p, retype(dst, ELK_REGISTER_TYPE_UD), + retype(src[0], ELK_REGISTER_TYPE_UD)); break; - case BRW_OPCODE_ADDC: + case ELK_OPCODE_ADDC: assert(devinfo->ver >= 7); - brw_ADDC(p, dst, src[0], src[1]); + elk_ADDC(p, dst, src[0], src[1]); break; - case BRW_OPCODE_SUBB: + case ELK_OPCODE_SUBB: assert(devinfo->ver >= 7); - brw_SUBB(p, dst, src[0], src[1]); + elk_SUBB(p, dst, src[0], src[1]); break; - case BRW_OPCODE_MAC: - brw_MAC(p, dst, src[0], src[1]); + case ELK_OPCODE_MAC: + elk_MAC(p, dst, src[0], src[1]); break; - case BRW_OPCODE_BFE: + case ELK_OPCODE_BFE: assert(devinfo->ver >= 7); if (devinfo->ver < 10) - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_BFE(p, dst, src[0], src[1], src[2]); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_BFE(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_BFI1: + case ELK_OPCODE_BFI1: assert(devinfo->ver >= 7); - brw_BFI1(p, dst, src[0], src[1]); + elk_BFI1(p, dst, src[0], src[1]); break; - case BRW_OPCODE_BFI2: + case ELK_OPCODE_BFI2: assert(devinfo->ver >= 7); if (devinfo->ver < 10) - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_BFI2(p, dst, src[0], src[1], src[2]); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_BFI2(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_IF: + case ELK_OPCODE_IF: if (inst->src[0].file != BAD_FILE) { /* The instruction has an embedded compare (only allowed on gfx6) */ assert(devinfo->ver == 6); - gfx6_IF(p, inst->conditional_mod, src[0], src[1]); + elk_gfx6_IF(p, inst->conditional_mod, src[0], src[1]); } else { - brw_IF(p, brw_get_default_exec_size(p)); + elk_IF(p, elk_get_default_exec_size(p)); } break; - case BRW_OPCODE_ELSE: - brw_ELSE(p); + case ELK_OPCODE_ELSE: + elk_ELSE(p); break; - case BRW_OPCODE_ENDIF: - brw_ENDIF(p); + case ELK_OPCODE_ENDIF: + elk_ENDIF(p); break; - case BRW_OPCODE_DO: - brw_DO(p, brw_get_default_exec_size(p)); + case ELK_OPCODE_DO: + elk_DO(p, elk_get_default_exec_size(p)); break; - case BRW_OPCODE_BREAK: - brw_BREAK(p); + case ELK_OPCODE_BREAK: + elk_BREAK(p); break; - case BRW_OPCODE_CONTINUE: - brw_CONT(p); + case ELK_OPCODE_CONTINUE: + elk_CONT(p); break; - case BRW_OPCODE_WHILE: - brw_WHILE(p); + case ELK_OPCODE_WHILE: + elk_WHILE(p); loop_count++; break; - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: - assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: + assert(inst->conditional_mod == ELK_CONDITIONAL_NONE); if (devinfo->ver >= 6) { assert(inst->mlen == 0); assert(devinfo->ver >= 7 || inst->exec_size == 8); - gfx6_math(p, dst, brw_math_function(inst->opcode), - src[0], brw_null_reg()); + elk_gfx6_math(p, dst, elk_math_function(inst->opcode), + src[0], elk_null_reg()); } else { assert(inst->mlen >= 1); assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X || inst->exec_size == 8); - gfx4_math(p, dst, - brw_math_function(inst->opcode), + elk_gfx4_math(p, dst, + elk_math_function(inst->opcode), inst->base_mrf, src[0], - BRW_MATH_PRECISION_FULL); + ELK_MATH_PRECISION_FULL); send_count++; } break; - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: - case SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_POW: assert(devinfo->verx10 < 125); - assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); + assert(inst->conditional_mod == ELK_CONDITIONAL_NONE); if (devinfo->ver >= 6) { assert(inst->mlen == 0); - assert((devinfo->ver >= 7 && inst->opcode == SHADER_OPCODE_POW) || + assert((devinfo->ver >= 7 && inst->opcode == ELK_SHADER_OPCODE_POW) || inst->exec_size == 8); - gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]); + elk_gfx6_math(p, dst, elk_math_function(inst->opcode), src[0], src[1]); } else { assert(inst->mlen >= 1); assert(inst->exec_size == 8); - gfx4_math(p, dst, brw_math_function(inst->opcode), + elk_gfx4_math(p, dst, elk_math_function(inst->opcode), inst->base_mrf, src[0], - BRW_MATH_PRECISION_FULL); + ELK_MATH_PRECISION_FULL); send_count++; } break; - case FS_OPCODE_LINTERP: + case ELK_FS_OPCODE_LINTERP: multiple_instructions_emitted = generate_linterp(inst, dst, src); break; - case FS_OPCODE_PIXEL_X: - assert(src[0].type == BRW_REGISTER_TYPE_UW); - assert(src[1].type == BRW_REGISTER_TYPE_UW); + case ELK_FS_OPCODE_PIXEL_X: + assert(src[0].type == ELK_REGISTER_TYPE_UW); + assert(src[1].type == ELK_REGISTER_TYPE_UW); src[0].subnr = 0 * type_sz(src[0].type); - if (src[1].file == BRW_IMMEDIATE_VALUE) { + if (src[1].file == ELK_IMMEDIATE_VALUE) { assert(src[1].ud == 0); - brw_MOV(p, dst, stride(src[0], 8, 4, 1)); + elk_MOV(p, dst, stride(src[0], 8, 4, 1)); } else { /* Coarse pixel case */ - brw_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]); + elk_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]); } break; - case FS_OPCODE_PIXEL_Y: - assert(src[0].type == BRW_REGISTER_TYPE_UW); - assert(src[1].type == BRW_REGISTER_TYPE_UW); + case ELK_FS_OPCODE_PIXEL_Y: + assert(src[0].type == ELK_REGISTER_TYPE_UW); + assert(src[1].type == ELK_REGISTER_TYPE_UW); src[0].subnr = 4 * type_sz(src[0].type); - if (src[1].file == BRW_IMMEDIATE_VALUE) { + if (src[1].file == ELK_IMMEDIATE_VALUE) { assert(src[1].ud == 0); - brw_MOV(p, dst, stride(src[0], 8, 4, 1)); + elk_MOV(p, dst, stride(src[0], 8, 4, 1)); } else { /* Coarse pixel case */ - brw_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]); + elk_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]); } break; - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: generate_send(inst, dst, src[0], src[1], src[2], - inst->ex_mlen > 0 ? src[3] : brw_null_reg()); + inst->ex_mlen > 0 ? src[3] : elk_null_reg()); send_count++; break; - case SHADER_OPCODE_TEX: - case FS_OPCODE_TXB: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_LOD: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_TEX: + case ELK_FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_SAMPLEINFO: assert(inst->src[0].file == BAD_FILE); generate_tex(inst, dst, src[1], src[2]); send_count++; break; - case FS_OPCODE_DDX_COARSE: - case FS_OPCODE_DDX_FINE: + case ELK_FS_OPCODE_DDX_COARSE: + case ELK_FS_OPCODE_DDX_FINE: generate_ddx(inst, dst, src[0]); break; - case FS_OPCODE_DDY_COARSE: - case FS_OPCODE_DDY_FINE: + case ELK_FS_OPCODE_DDY_COARSE: + case ELK_FS_OPCODE_DDY_FINE: generate_ddy(inst, dst, src[0]); break; - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: generate_scratch_write(inst, src[0]); send_count++; break; - case SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: generate_scratch_read(inst, dst); send_count++; break; - case SHADER_OPCODE_GFX7_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX7_SCRATCH_READ: generate_scratch_read_gfx7(inst, dst); send_count++; break; - case SHADER_OPCODE_SCRATCH_HEADER: + case ELK_SHADER_OPCODE_SCRATCH_HEADER: generate_scratch_header(inst, dst); break; - case SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_MOV_INDIRECT: generate_mov_indirect(inst, dst, src[0], src[1]); break; - case SHADER_OPCODE_MOV_RELOC_IMM: - assert(src[0].file == BRW_IMMEDIATE_VALUE); - brw_MOV_reloc_imm(p, dst, dst.type, src[0].ud); + case ELK_SHADER_OPCODE_MOV_RELOC_IMM: + assert(src[0].file == ELK_IMMEDIATE_VALUE); + elk_MOV_reloc_imm(p, dst, dst.type, src[0].ud); break; - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: assert(inst->force_writemask_all); generate_uniform_pull_constant_load(inst, dst, src[PULL_UNIFORM_CONSTANT_SRC_SURFACE], @@ -2159,36 +2158,36 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, send_count++; break; - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: generate_varying_pull_constant_load_gfx4(inst, dst, src[0]); send_count++; break; - case FS_OPCODE_REP_FB_WRITE: - case FS_OPCODE_FB_WRITE: + case ELK_FS_OPCODE_REP_FB_WRITE: + case ELK_FS_OPCODE_FB_WRITE: generate_fb_write(inst, src[0]); send_count++; break; - case FS_OPCODE_FB_READ: + case ELK_FS_OPCODE_FB_READ: generate_fb_read(inst, dst, src[0]); send_count++; break; - case BRW_OPCODE_HALT: + case ELK_OPCODE_HALT: generate_halt(inst); break; - case SHADER_OPCODE_INTERLOCK: - case SHADER_OPCODE_MEMORY_FENCE: { - assert(src[1].file == BRW_IMMEDIATE_VALUE); - assert(src[2].file == BRW_IMMEDIATE_VALUE); + case ELK_SHADER_OPCODE_INTERLOCK: + case ELK_SHADER_OPCODE_MEMORY_FENCE: { + assert(src[1].file == ELK_IMMEDIATE_VALUE); + assert(src[2].file == ELK_IMMEDIATE_VALUE); - const enum opcode send_op = inst->opcode == SHADER_OPCODE_INTERLOCK ? - BRW_OPCODE_SENDC : BRW_OPCODE_SEND; + const enum elk_opcode send_op = inst->opcode == ELK_SHADER_OPCODE_INTERLOCK ? + ELK_OPCODE_SENDC : ELK_OPCODE_SEND; - brw_memory_fence(p, dst, src[0], send_op, - brw_message_target(inst->sfid), + elk_memory_fence(p, dst, src[0], send_op, + elk_message_target(inst->sfid), inst->desc, /* commit_enable */ src[1].ud, /* bti */ src[2].ud); @@ -2196,11 +2195,11 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; } - case FS_OPCODE_SCHEDULING_FENCE: + case ELK_FS_OPCODE_SCHEDULING_FENCE: if (inst->sources == 0 && swsb.regdist == 0 && swsb.mode == TGL_SBID_NULL) { if (unlikely(debug_flag)) - disasm_info->use_tail = true; + elk_disasm_info->use_tail = true; break; } @@ -2210,14 +2209,14 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, * scoreboard algorithm already injected other SYNCs before this * instruction. */ - brw_SYNC(p, TGL_SYNC_NOP); + elk_SYNC(p, TGL_SYNC_NOP); } else { for (unsigned i = 0; i < inst->sources; i++) { /* Emit a MOV to force a stall until the instruction producing the * registers finishes. */ - brw_MOV(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW), - retype(src[i], BRW_REGISTER_TYPE_UW)); + elk_MOV(p, retype(elk_null_reg(), ELK_REGISTER_TYPE_UW), + retype(src[i], ELK_REGISTER_TYPE_UW)); } if (inst->sources > 1) @@ -2226,57 +2225,57 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; - case SHADER_OPCODE_FIND_LIVE_CHANNEL: - brw_find_live_channel(p, dst, false); + case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL: + elk_find_live_channel(p, dst, false); break; - case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: - brw_find_live_channel(p, dst, true); + case ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: + elk_find_live_channel(p, dst, true); break; - case FS_OPCODE_LOAD_LIVE_CHANNELS: { + case ELK_FS_OPCODE_LOAD_LIVE_CHANNELS: { assert(devinfo->ver >= 8); assert(inst->force_writemask_all && inst->group == 0); assert(inst->dst.file == BAD_FILE); - brw_set_default_exec_size(p, BRW_EXECUTE_1); - brw_MOV(p, retype(brw_flag_subreg(inst->flag_subreg), - BRW_REGISTER_TYPE_UD), - retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD)); + elk_set_default_exec_size(p, ELK_EXECUTE_1); + elk_MOV(p, retype(elk_flag_subreg(inst->flag_subreg), + ELK_REGISTER_TYPE_UD), + retype(elk_mask_reg(0), ELK_REGISTER_TYPE_UD)); break; } - case SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_BROADCAST: assert(inst->force_writemask_all); - brw_broadcast(p, dst, src[0], src[1]); + elk_broadcast(p, dst, src[0], src[1]); break; - case SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_SHUFFLE: generate_shuffle(inst, dst, src[0], src[1]); break; - case SHADER_OPCODE_SEL_EXEC: + case ELK_SHADER_OPCODE_SEL_EXEC: assert(inst->force_writemask_all); assert(devinfo->has_64bit_float || type_sz(dst.type) <= 4); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, dst, src[1]); - brw_set_default_mask_control(p, BRW_MASK_ENABLE); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, dst, src[0]); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, dst, src[1]); + elk_set_default_mask_control(p, ELK_MASK_ENABLE); + elk_set_default_swsb(p, tgl_swsb_null()); + elk_MOV(p, dst, src[0]); break; - case SHADER_OPCODE_QUAD_SWIZZLE: - assert(src[1].file == BRW_IMMEDIATE_VALUE); - assert(src[1].type == BRW_REGISTER_TYPE_UD); + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: + assert(src[1].file == ELK_IMMEDIATE_VALUE); + assert(src[1].type == ELK_REGISTER_TYPE_UD); generate_quad_swizzle(inst, dst, src[0], src[1].ud); break; - case SHADER_OPCODE_CLUSTER_BROADCAST: { + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: { assert((devinfo->platform != INTEL_PLATFORM_CHV && !intel_device_info_is_9lp(devinfo) && devinfo->has_64bit_float) || type_sz(src[0].type) <= 4); assert(!src[0].negate && !src[0].abs); - assert(src[1].file == BRW_IMMEDIATE_VALUE); - assert(src[1].type == BRW_REGISTER_TYPE_UD); - assert(src[2].file == BRW_IMMEDIATE_VALUE); - assert(src[2].type == BRW_REGISTER_TYPE_UD); + assert(src[1].file == ELK_IMMEDIATE_VALUE); + assert(src[1].type == ELK_REGISTER_TYPE_UD); + assert(src[2].file == ELK_IMMEDIATE_VALUE); + assert(src[2].type == ELK_REGISTER_TYPE_UD); const unsigned component = src[1].ud; const unsigned cluster_size = src[2].ud; assert(inst->src[0].file != ARF && inst->src[0].file != FIXED_GRF); @@ -2290,84 +2289,84 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, width = 1; } - struct brw_reg strided = stride(suboffset(src[0], component * s), + struct elk_reg strided = stride(suboffset(src[0], component * s), vstride, width, 0); - brw_MOV(p, dst, strided); + elk_MOV(p, dst, strided); break; } - case FS_OPCODE_SET_SAMPLE_ID: + case ELK_FS_OPCODE_SET_SAMPLE_ID: generate_set_sample_id(inst, dst, src[0], src[1]); break; - case SHADER_OPCODE_HALT_TARGET: + case ELK_SHADER_OPCODE_HALT_TARGET: /* This is the place where the final HALT needs to be inserted if * we've emitted any discards. If not, this will emit no code. */ if (!patch_halt_jumps()) { if (unlikely(debug_flag)) { - disasm_info->use_tail = true; + elk_disasm_info->use_tail = true; } } break; - case CS_OPCODE_CS_TERMINATE: + case ELK_CS_OPCODE_CS_TERMINATE: generate_cs_terminate(inst, src[0]); send_count++; break; - case SHADER_OPCODE_BARRIER: + case ELK_SHADER_OPCODE_BARRIER: generate_barrier(inst, src[0]); send_count++; break; - case BRW_OPCODE_DIM: + case ELK_OPCODE_DIM: assert(devinfo->platform == INTEL_PLATFORM_HSW); - assert(src[0].type == BRW_REGISTER_TYPE_DF); - assert(dst.type == BRW_REGISTER_TYPE_DF); - brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F)); + assert(src[0].type == ELK_REGISTER_TYPE_DF); + assert(dst.type == ELK_REGISTER_TYPE_DF); + elk_DIM(p, dst, retype(src[0], ELK_REGISTER_TYPE_F)); break; - case SHADER_OPCODE_RND_MODE: { - assert(src[0].file == BRW_IMMEDIATE_VALUE); + case ELK_SHADER_OPCODE_RND_MODE: { + assert(src[0].file == ELK_IMMEDIATE_VALUE); /* * Changes the floating point rounding mode updating the control * register field defined at cr0.0[5-6] bits. */ - enum brw_rnd_mode mode = - (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT); - brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK); + enum elk_rnd_mode mode = + (enum elk_rnd_mode) (src[0].d << ELK_CR0_RND_MODE_SHIFT); + elk_float_controls_mode(p, mode, ELK_CR0_RND_MODE_MASK); } break; - case SHADER_OPCODE_FLOAT_CONTROL_MODE: - assert(src[0].file == BRW_IMMEDIATE_VALUE); - assert(src[1].file == BRW_IMMEDIATE_VALUE); - brw_float_controls_mode(p, src[0].d, src[1].d); + case ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE: + assert(src[0].file == ELK_IMMEDIATE_VALUE); + assert(src[1].file == ELK_IMMEDIATE_VALUE); + elk_float_controls_mode(p, src[0].d, src[1].d); break; - case SHADER_OPCODE_READ_SR_REG: + case ELK_SHADER_OPCODE_READ_SR_REG: if (devinfo->ver >= 12) { /* There is a SWSB restriction that requires that any time sr0 is * accessed both the instruction doing the access and the next one * have SWSB set to RegDist(1). */ - if (brw_get_default_swsb(p).mode != TGL_SBID_NULL) - brw_SYNC(p, TGL_SYNC_NOP); - assert(src[0].file == BRW_IMMEDIATE_VALUE); - brw_set_default_swsb(p, tgl_swsb_regdist(1)); - brw_MOV(p, dst, brw_sr0_reg(src[0].ud)); - brw_set_default_swsb(p, tgl_swsb_regdist(1)); - brw_AND(p, dst, dst, brw_imm_ud(0xffffffff)); + if (elk_get_default_swsb(p).mode != TGL_SBID_NULL) + elk_SYNC(p, TGL_SYNC_NOP); + assert(src[0].file == ELK_IMMEDIATE_VALUE); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_MOV(p, dst, elk_sr0_reg(src[0].ud)); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_AND(p, dst, dst, elk_imm_ud(0xffffffff)); } else { - brw_MOV(p, dst, brw_sr0_reg(src[0].ud)); + elk_MOV(p, dst, elk_sr0_reg(src[0].ud)); } break; default: unreachable("Unsupported opcode"); - case SHADER_OPCODE_LOAD_PAYLOAD: + case ELK_SHADER_OPCODE_LOAD_PAYLOAD: unreachable("Should be lowered by lower_load_payload()"); } @@ -2379,13 +2378,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, !"conditional_mod, no_dd_check, or no_dd_clear set for IR " "emitting more than 1 instruction"); - brw_inst *last = &p->store[last_insn_offset / 16]; + elk_inst *last = &p->store[last_insn_offset / 16]; if (inst->conditional_mod) - brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod); + elk_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod); if (devinfo->ver < 12) { - brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear); - brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check); + elk_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear); + elk_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check); } } @@ -2393,15 +2392,15 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, * that current instruction depends on the previous instruction. */ if (INTEL_DEBUG(DEBUG_SWSB_STALL) && devinfo->ver >= 12) { - brw_set_default_swsb(p, tgl_swsb_regdist(1)); - brw_SYNC(p, TGL_SYNC_NOP); + elk_set_default_swsb(p, tgl_swsb_regdist(1)); + elk_SYNC(p, TGL_SYNC_NOP); } } - brw_set_uip_jip(p, start_offset); + elk_set_uip_jip(p, start_offset); /* end of program sentinel */ - disasm_new_inst_group(disasm_info, p->next_insn_offset); + elk_disasm_new_inst_group(elk_disasm_info, p->next_insn_offset); /* `send_count` explicitly does not include spills or fills, as we'd * like to use it as a metric for intentional memory access or other @@ -2417,27 +2416,27 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, #else if (unlikely(debug_flag)) #endif - brw_validate_instructions(&compiler->isa, p->store, + elk_validate_instructions(&compiler->isa, p->store, start_offset, p->next_insn_offset, - disasm_info); + elk_disasm_info); int before_size = p->next_insn_offset - start_offset; - brw_compact_instructions(p, start_offset, disasm_info); + elk_compact_instructions(p, start_offset, elk_disasm_info); int after_size = p->next_insn_offset - start_offset; - bool dump_shader_bin = brw_should_dump_shader_bin(); + bool dump_shader_bin = elk_should_dump_shader_bin(); unsigned char sha1[21]; char sha1buf[41]; if (unlikely(debug_flag || dump_shader_bin)) { - _mesa_sha1_compute(p->store + start_offset / sizeof(brw_inst), + _mesa_sha1_compute(p->store + start_offset / sizeof(elk_inst), after_size, sha1); _mesa_sha1_format(sha1buf, sha1); } if (unlikely(dump_shader_bin)) - brw_dump_shader_bin(p->store, start_offset, p->next_insn_offset, + elk_dump_shader_bin(p->store, start_offset, p->next_insn_offset, sha1buf); if (unlikely(debug_flag)) { @@ -2458,15 +2457,15 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, before_size, after_size, 100.0f * (before_size - after_size) / before_size); - /* overriding the shader makes disasm_info invalid */ - if (!brw_try_override_assembly(p, start_offset, sha1buf)) { - dump_assembly(p->store, start_offset, p->next_insn_offset, - disasm_info, perf.block_latency); + /* overriding the shader makes elk_disasm_info invalid */ + if (!elk_try_override_assembly(p, start_offset, sha1buf)) { + elk_dump_assembly(p->store, start_offset, p->next_insn_offset, + elk_disasm_info, perf.block_latency); } else { fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf); } } - ralloc_free(disasm_info); + ralloc_free(elk_disasm_info); #ifndef NDEBUG if (!validated && !debug_flag) { fprintf(stderr, @@ -2475,7 +2474,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, #endif assert(validated); - brw_shader_debug_log(compiler, params->log_data, + elk_shader_debug_log(compiler, params->log_data, "%s SIMD%d shader: %d inst, %d loops, %u cycles, " "%d:%d spills:fills, %u sends, " "scheduled with mode %s, " @@ -2508,19 +2507,19 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, } void -fs_generator::add_const_data(void *data, unsigned size) +elk_fs_generator::add_const_data(void *data, unsigned size) { assert(prog_data->const_data_size == 0); if (size > 0) { prog_data->const_data_size = size; - prog_data->const_data_offset = brw_append_data(p, data, size, 32); + prog_data->const_data_offset = elk_append_data(p, data, size, 32); } } const unsigned * -fs_generator::get_assembly() +elk_fs_generator::get_assembly() { - prog_data->relocs = brw_get_shader_relocs(p, &prog_data->num_relocs); + prog_data->relocs = elk_get_shader_relocs(p, &prog_data->num_relocs); - return brw_get_program(p, &prog_data->program_size); + return elk_get_program(p, &prog_data->program_size); } diff --git a/src/intel/compiler/elk/elk_fs_live_variables.cpp b/src/intel/compiler/elk/elk_fs_live_variables.cpp index e2b5d7897b6..82a717bc17e 100644 --- a/src/intel/compiler/elk/elk_fs_live_variables.cpp +++ b/src/intel/compiler/elk/elk_fs_live_variables.cpp @@ -54,7 +54,7 @@ using namespace elk; void fs_live_variables::setup_one_read(struct block_data *bd, - int ip, const fs_reg ®) + int ip, const elk_fs_reg ®) { int var = var_from_reg(reg); assert(var < num_vars); @@ -71,8 +71,8 @@ fs_live_variables::setup_one_read(struct block_data *bd, } void -fs_live_variables::setup_one_write(struct block_data *bd, fs_inst *inst, - int ip, const fs_reg ®) +fs_live_variables::setup_one_write(struct block_data *bd, elk_fs_inst *inst, + int ip, const elk_fs_reg ®) { int var = var_from_reg(reg); assert(var < num_vars); @@ -112,10 +112,10 @@ fs_live_variables::setup_def_use() struct block_data *bd = &block_data[block->num]; - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(elk_fs_inst, inst, block) { /* Set use[] for this instruction */ for (unsigned int i = 0; i < inst->sources; i++) { - fs_reg reg = inst->src[i]; + elk_fs_reg reg = inst->src[i]; if (reg.file != VGRF) continue; @@ -130,7 +130,7 @@ fs_live_variables::setup_def_use() /* Set def[] for this instruction */ if (inst->dst.file == VGRF) { - fs_reg reg = inst->dst; + elk_fs_reg reg = inst->dst; for (unsigned j = 0; j < regs_written(inst); j++) { setup_one_write(bd, inst, ip, reg); reg.offset += REG_SIZE; @@ -165,7 +165,7 @@ fs_live_variables::compute_live_variables() foreach_block (block, cfg) { const struct block_data *bd = &block_data[block->num]; - foreach_list_typed(bblock_link, child_link, link, &block->children) { + foreach_list_typed(elk_bblock_link, child_link, link, &block->children) { struct block_data *child_bd = &block_data[child_link->block->num]; for (int i = 0; i < bitset_words; i++) { @@ -185,7 +185,7 @@ fs_live_variables::compute_live_variables() struct block_data *bd = &block_data[block->num]; /* Update liveout */ - foreach_list_typed(bblock_link, child_link, link, &block->children) { + foreach_list_typed(elk_bblock_link, child_link, link, &block->children) { struct block_data *child_bd = &block_data[child_link->block->num]; for (int i = 0; i < bitset_words; i++) { @@ -246,7 +246,7 @@ fs_live_variables::compute_start_end() } } -fs_live_variables::fs_live_variables(const backend_shader *s) +fs_live_variables::fs_live_variables(const elk_backend_shader *s) : devinfo(s->devinfo), cfg(s->cfg) { mem_ctx = ralloc_context(NULL); @@ -317,7 +317,7 @@ fs_live_variables::~fs_live_variables() static bool check_register_live_range(const fs_live_variables *live, int ip, - const fs_reg ®, unsigned n) + const elk_fs_reg ®, unsigned n) { const unsigned var = live->var_from_reg(reg); @@ -334,11 +334,11 @@ check_register_live_range(const fs_live_variables *live, int ip, } bool -fs_live_variables::validate(const backend_shader *s) const +fs_live_variables::validate(const elk_backend_shader *s) const { int ip = 0; - foreach_block_and_inst(block, fs_inst, inst, s->cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, s->cfg) { for (unsigned i = 0; i < inst->sources; i++) { if (inst->src[i].file == VGRF && !check_register_live_range(this, ip, diff --git a/src/intel/compiler/elk/elk_fs_live_variables.h b/src/intel/compiler/elk/elk_fs_live_variables.h index 3d9f646a059..0856e9e2dc0 100644 --- a/src/intel/compiler/elk/elk_fs_live_variables.h +++ b/src/intel/compiler/elk/elk_fs_live_variables.h @@ -32,8 +32,8 @@ #include "elk_ir_fs.h" #include "util/bitset.h" -struct cfg_t; -struct backend_shader; +struct elk_cfg_t; +struct elk_backend_shader; namespace elk { @@ -77,10 +77,10 @@ public: BITSET_WORD flag_liveout[1]; }; - fs_live_variables(const backend_shader *s); + fs_live_variables(const elk_backend_shader *s); ~fs_live_variables(); - bool validate(const backend_shader *s) const; + bool validate(const elk_backend_shader *s) const; analysis_dependency_class dependency_class() const @@ -92,7 +92,7 @@ public: bool vars_interfere(int a, int b) const; bool vgrfs_interfere(int a, int b) const; - int var_from_reg(const fs_reg ®) const + int var_from_reg(const elk_fs_reg ®) const { return var_from_vgrf[reg.nr] + reg.offset / REG_SIZE; } @@ -132,14 +132,14 @@ public: protected: void setup_def_use(); - void setup_one_read(struct block_data *bd, int ip, const fs_reg ®); - void setup_one_write(struct block_data *bd, fs_inst *inst, int ip, - const fs_reg ®); + void setup_one_read(struct block_data *bd, int ip, const elk_fs_reg ®); + void setup_one_write(struct block_data *bd, elk_fs_inst *inst, int ip, + const elk_fs_reg ®); void compute_live_variables(); void compute_start_end(); const struct intel_device_info *devinfo; - const cfg_t *cfg; + const elk_cfg_t *cfg; void *mem_ctx; }; diff --git a/src/intel/compiler/elk/elk_fs_lower_pack.cpp b/src/intel/compiler/elk/elk_fs_lower_pack.cpp index 9a033b500ef..43d47241ba8 100644 --- a/src/intel/compiler/elk/elk_fs_lower_pack.cpp +++ b/src/intel/compiler/elk/elk_fs_lower_pack.cpp @@ -29,18 +29,18 @@ using namespace elk; bool -fs_visitor::lower_pack() +elk_fs_visitor::lower_pack() { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { - if (inst->opcode != FS_OPCODE_PACK && - inst->opcode != FS_OPCODE_PACK_HALF_2x16_SPLIT) + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { + if (inst->opcode != ELK_FS_OPCODE_PACK && + inst->opcode != ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT) continue; assert(inst->dst.file == VGRF); assert(inst->saturate == false); - fs_reg dst = inst->dst; + elk_fs_reg dst = inst->dst; const fs_builder ibld(this, block, inst); /* The lowering generates 2 instructions for what was previously 1. This @@ -52,27 +52,27 @@ fs_visitor::lower_pack() ibld.emit_undef_for_dst(inst); switch (inst->opcode) { - case FS_OPCODE_PACK: + case ELK_FS_OPCODE_PACK: for (unsigned i = 0; i < inst->sources; i++) ibld.MOV(subscript(dst, inst->src[i].type, i), inst->src[i]); break; - case FS_OPCODE_PACK_HALF_2x16_SPLIT: - assert(dst.type == BRW_REGISTER_TYPE_UD); + case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT: + assert(dst.type == ELK_REGISTER_TYPE_UD); for (unsigned i = 0; i < inst->sources; i++) { if (inst->src[i].file == IMM) { const uint32_t half = _mesa_float_to_half(inst->src[i].f); - ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_UW, i), - brw_imm_uw(half)); + ibld.MOV(subscript(dst, ELK_REGISTER_TYPE_UW, i), + elk_imm_uw(half)); } else if (i == 1 && devinfo->ver < 9) { /* Pre-Skylake requires DWord aligned destinations */ - fs_reg tmp = ibld.vgrf(BRW_REGISTER_TYPE_UD); - ibld.F32TO16(subscript(tmp, BRW_REGISTER_TYPE_HF, 0), + elk_fs_reg tmp = ibld.vgrf(ELK_REGISTER_TYPE_UD); + ibld.F32TO16(subscript(tmp, ELK_REGISTER_TYPE_HF, 0), inst->src[i]); - ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_UW, 1), - subscript(tmp, BRW_REGISTER_TYPE_UW, 0)); + ibld.MOV(subscript(dst, ELK_REGISTER_TYPE_UW, 1), + subscript(tmp, ELK_REGISTER_TYPE_UW, 0)); } else { - ibld.F32TO16(subscript(dst, BRW_REGISTER_TYPE_HF, i), + ibld.F32TO16(subscript(dst, ELK_REGISTER_TYPE_HF, i), inst->src[i]); } } diff --git a/src/intel/compiler/elk/elk_fs_lower_regioning.cpp b/src/intel/compiler/elk/elk_fs_lower_regioning.cpp index de5882049eb..5b01ec2c10d 100644 --- a/src/intel/compiler/elk/elk_fs_lower_regioning.cpp +++ b/src/intel/compiler/elk/elk_fs_lower_regioning.cpp @@ -36,10 +36,10 @@ namespace { * using raw move." */ bool - is_byte_raw_mov(const fs_inst *inst) + is_byte_raw_mov(const elk_fs_inst *inst) { return type_sz(inst->dst.type) == 1 && - inst->opcode == BRW_OPCODE_MOV && + inst->opcode == ELK_OPCODE_MOV && inst->src[0].type == inst->dst.type && !inst->saturate && !inst->src[0].negate && @@ -51,7 +51,7 @@ namespace { * that requires it to have some particular alignment. */ unsigned - required_dst_byte_stride(const fs_inst *inst) + required_dst_byte_stride(const elk_fs_inst *inst) { if (inst->dst.is_accumulator()) { /* If the destination is an accumulator, insist that we leave the @@ -107,7 +107,7 @@ namespace { * the sources. */ unsigned - required_dst_byte_offset(const intel_device_info *devinfo, const fs_inst *inst) + required_dst_byte_offset(const intel_device_info *devinfo, const elk_fs_inst *inst) { for (unsigned i = 0; i < inst->sources; i++) { if (!is_uniform(inst->src[i]) && !inst->is_control_source(i)) @@ -123,15 +123,15 @@ namespace { * Return the closest legal execution type for an instruction on * the specified platform. */ - brw_reg_type - required_exec_type(const intel_device_info *devinfo, const fs_inst *inst) + elk_reg_type + required_exec_type(const intel_device_info *devinfo, const elk_fs_inst *inst) { - const brw_reg_type t = get_exec_type(inst); - const bool has_64bit = brw_reg_type_is_floating_point(t) ? + const elk_reg_type t = get_exec_type(inst); + const bool has_64bit = elk_reg_type_is_floating_point(t) ? devinfo->has_64bit_float : devinfo->has_64bit_int; switch (inst->opcode) { - case SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_SHUFFLE: /* IVB has an issue (which we found empirically) where it reads * two address register components per channel for indirectly * addressed 64-bit sources. @@ -148,26 +148,26 @@ namespace { if ((!devinfo->has_64bit_int || devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4) - return BRW_REGISTER_TYPE_UD; + return ELK_REGISTER_TYPE_UD; else if (has_dst_aligned_region_restriction(devinfo, inst)) - return brw_int_type(type_sz(t), false); + return elk_int_type(type_sz(t), false); else return t; - case SHADER_OPCODE_SEL_EXEC: + case ELK_SHADER_OPCODE_SEL_EXEC: if ((!has_64bit || devinfo->has_64bit_float_via_math_pipe) && type_sz(t) > 4) - return BRW_REGISTER_TYPE_UD; + return ELK_REGISTER_TYPE_UD; else return t; - case SHADER_OPCODE_QUAD_SWIZZLE: + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: if (has_dst_aligned_region_restriction(devinfo, inst)) - return brw_int_type(type_sz(t), false); + return elk_int_type(type_sz(t), false); else return t; - case SHADER_OPCODE_CLUSTER_BROADCAST: + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: /* From the Cherryview PRM Vol 7. "Register Region Restrictions": * * "When source or destination datatype is 64b or operation is @@ -186,19 +186,19 @@ namespace { if ((!has_64bit || devinfo->verx10 >= 125 || devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4) - return BRW_REGISTER_TYPE_UD; + return ELK_REGISTER_TYPE_UD; else - return brw_int_type(type_sz(t), false); + return elk_int_type(type_sz(t), false); - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_MOV_INDIRECT: if (((devinfo->verx10 == 70 || devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) || devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) || (devinfo->verx10 >= 125 && - brw_reg_type_is_floating_point(inst->src[0].type))) - return brw_int_type(type_sz(t), false); + elk_reg_type_is_floating_point(inst->src[0].type))) + return elk_int_type(type_sz(t), false); else return t; @@ -213,7 +213,7 @@ namespace { * single one-dimensional stride. */ unsigned - byte_stride(const fs_reg ®) + byte_stride(const elk_fs_reg ®) { switch (reg.file) { case BAD_FILE: @@ -250,11 +250,11 @@ namespace { * specified for the i-th source region. */ bool - has_invalid_src_region(const intel_device_info *devinfo, const fs_inst *inst, + has_invalid_src_region(const intel_device_info *devinfo, const elk_fs_inst *inst, unsigned i) { if (is_send(inst) || inst->is_math() || inst->is_control_source(i) || - inst->opcode == BRW_OPCODE_DPAS) { + inst->opcode == ELK_OPCODE_DPAS) { return false; } @@ -269,8 +269,8 @@ namespace { * register. The problem doesn't occur if the stride of the source is 0. */ if (devinfo->ver == 8 && - inst->opcode == BRW_OPCODE_MAD && - inst->src[i].type == BRW_REGISTER_TYPE_HF && + inst->opcode == ELK_OPCODE_MAD && + inst->src[i].type == ELK_REGISTER_TYPE_HF && reg_offset(inst->src[i]) % REG_SIZE > 0 && inst->src[i].stride != 0) { return true; @@ -291,12 +291,12 @@ namespace { */ bool has_invalid_dst_region(const intel_device_info *devinfo, - const fs_inst *inst) + const elk_fs_inst *inst) { if (is_send(inst) || inst->is_math()) { return false; } else { - const brw_reg_type exec_type = get_exec_type(inst); + const elk_reg_type exec_type = get_exec_type(inst); const unsigned dst_byte_offset = reg_offset(inst->dst) % (reg_unit(devinfo) * REG_SIZE); const bool is_narrowing_conversion = !is_byte_raw_mov(inst) && type_sz(inst->dst.type) < type_sz(exec_type); @@ -316,18 +316,18 @@ namespace { * source or destination modifiers into separate MOV instructions. */ unsigned - has_invalid_exec_type(const intel_device_info *devinfo, const fs_inst *inst) + has_invalid_exec_type(const intel_device_info *devinfo, const elk_fs_inst *inst) { if (required_exec_type(devinfo, inst) != get_exec_type(inst)) { switch (inst->opcode) { - case SHADER_OPCODE_SHUFFLE: - case SHADER_OPCODE_QUAD_SWIZZLE: - case SHADER_OPCODE_CLUSTER_BROADCAST: - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: + case ELK_SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_MOV_INDIRECT: return 0x1; - case SHADER_OPCODE_SEL_EXEC: + case ELK_SHADER_OPCODE_SEL_EXEC: return 0x3; default: @@ -344,7 +344,7 @@ namespace { */ bool has_invalid_src_modifiers(const intel_device_info *devinfo, - const fs_inst *inst, unsigned i) + const elk_fs_inst *inst, unsigned i) { return (!inst->can_do_source_mods(devinfo) && (inst->src[i].negate || inst->src[i].abs)) || @@ -358,12 +358,12 @@ namespace { * specified for the destination. */ bool - has_invalid_conversion(const intel_device_info *devinfo, const fs_inst *inst) + has_invalid_conversion(const intel_device_info *devinfo, const elk_fs_inst *inst) { switch (inst->opcode) { - case BRW_OPCODE_MOV: + case ELK_OPCODE_MOV: return false; - case BRW_OPCODE_SEL: + case ELK_OPCODE_SEL: return inst->dst.type != get_exec_type(inst); default: /* FIXME: We assume the opcodes not explicitly mentioned before just @@ -379,7 +379,7 @@ namespace { * Return whether the instruction has unsupported destination modifiers. */ bool - has_invalid_dst_modifiers(const intel_device_info *devinfo, const fs_inst *inst) + has_invalid_dst_modifiers(const intel_device_info *devinfo, const elk_fs_inst *inst) { return (has_invalid_exec_type(devinfo, inst) && (inst->saturate || inst->conditional_mod)) || @@ -392,16 +392,16 @@ namespace { * the comparison result. */ bool - has_inconsistent_cmod(const fs_inst *inst) + has_inconsistent_cmod(const elk_fs_inst *inst) { - return inst->opcode == BRW_OPCODE_SEL || - inst->opcode == BRW_OPCODE_CSEL || - inst->opcode == BRW_OPCODE_IF || - inst->opcode == BRW_OPCODE_WHILE; + return inst->opcode == ELK_OPCODE_SEL || + inst->opcode == ELK_OPCODE_CSEL || + inst->opcode == ELK_OPCODE_IF || + inst->opcode == ELK_OPCODE_WHILE; } bool - lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst); + lower_instruction(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst); } namespace elk { @@ -412,17 +412,17 @@ namespace elk { * MOV instruction prior to the original instruction. */ bool - lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i) + lower_src_modifiers(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst, unsigned i) { assert(inst->components_read(i) == 1); assert(v->devinfo->has_integer_dword_mul || - inst->opcode != BRW_OPCODE_MUL || - brw_reg_type_is_floating_point(get_exec_type(inst)) || + inst->opcode != ELK_OPCODE_MUL || + elk_reg_type_is_floating_point(get_exec_type(inst)) || MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4 || type_sz(inst->src[i].type) == get_exec_type_size(inst)); const fs_builder ibld(v, block, inst); - const fs_reg tmp = ibld.vgrf(get_exec_type(inst)); + const elk_fs_reg tmp = ibld.vgrf(get_exec_type(inst)); lower_instruction(v, block, ibld.MOV(tmp, inst->src[i])); inst->src[i] = tmp; @@ -440,10 +440,10 @@ namespace { * instruction. */ bool - lower_dst_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_dst_modifiers(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst) { const fs_builder ibld(v, block, inst); - const brw_reg_type type = get_exec_type(inst); + const elk_reg_type type = get_exec_type(inst); /* Not strictly necessary, but if possible use a temporary with the same * channel alignment as the current destination in order to avoid * violating the restrictions enforced later on by lower_src_region() @@ -453,16 +453,16 @@ namespace { const unsigned stride = type_sz(inst->dst.type) * inst->dst.stride <= type_sz(type) ? 1 : type_sz(inst->dst.type) * inst->dst.stride / type_sz(type); - fs_reg tmp = ibld.vgrf(type, stride); + elk_fs_reg tmp = ibld.vgrf(type, stride); ibld.UNDEF(tmp); tmp = horiz_stride(tmp, stride); /* Emit a MOV taking care of all the destination modifiers. */ - fs_inst *mov = ibld.at(block, inst->next).MOV(inst->dst, tmp); + elk_fs_inst *mov = ibld.at(block, inst->next).MOV(inst->dst, tmp); mov->saturate = inst->saturate; if (!has_inconsistent_cmod(inst)) mov->conditional_mod = inst->conditional_mod; - if (inst->opcode != BRW_OPCODE_SEL) { + if (inst->opcode != ELK_OPCODE_SEL) { mov->predicate = inst->predicate; mov->predicate_inverse = inst->predicate_inverse; } @@ -477,7 +477,7 @@ namespace { inst->size_written = inst->dst.component_size(inst->exec_size); inst->saturate = false; if (!has_inconsistent_cmod(inst)) - inst->conditional_mod = BRW_CONDITIONAL_NONE; + inst->conditional_mod = ELK_CONDITIONAL_NONE; assert(!inst->flags_written(v->devinfo) || !mov->predicate); return true; @@ -489,24 +489,24 @@ namespace { * copies into a temporary with the same channel layout as the destination. */ bool - lower_src_region(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i) + lower_src_region(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst, unsigned i) { assert(inst->components_read(i) == 1); const fs_builder ibld(v, block, inst); const unsigned stride = type_sz(inst->dst.type) * inst->dst.stride / type_sz(inst->src[i].type); assert(stride > 0); - fs_reg tmp = ibld.vgrf(inst->src[i].type, stride); + elk_fs_reg tmp = ibld.vgrf(inst->src[i].type, stride); ibld.UNDEF(tmp); tmp = horiz_stride(tmp, stride); /* Emit a series of 32-bit integer copies with any source modifiers * cleaned up (because their semantics are dependent on the type). */ - const brw_reg_type raw_type = brw_int_type(MIN2(type_sz(tmp.type), 4), + const elk_reg_type raw_type = elk_int_type(MIN2(type_sz(tmp.type), 4), false); const unsigned n = type_sz(tmp.type) / type_sz(raw_type); - fs_reg raw_src = inst->src[i]; + elk_fs_reg raw_src = inst->src[i]; raw_src.negate = false; raw_src.abs = false; @@ -516,7 +516,7 @@ namespace { /* Point the original instruction at the temporary, making sure to keep * any source modifiers in the instruction. */ - fs_reg lower_src = tmp; + elk_fs_reg lower_src = tmp; lower_src.negate = inst->src[i].negate; lower_src.abs = inst->src[i].abs; inst->src[i] = lower_src; @@ -531,32 +531,32 @@ namespace { * sources. */ bool - lower_dst_region(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_dst_region(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst) { /* We cannot replace the result of an integer multiply which writes the * accumulator because MUL+MACH pairs act on the accumulator as a 66-bit * value whereas the MOV will act on only 32 or 33 bits of the * accumulator. */ - assert(inst->opcode != BRW_OPCODE_MUL || !inst->dst.is_accumulator() || - brw_reg_type_is_floating_point(inst->dst.type)); + assert(inst->opcode != ELK_OPCODE_MUL || !inst->dst.is_accumulator() || + elk_reg_type_is_floating_point(inst->dst.type)); const fs_builder ibld(v, block, inst); const unsigned stride = required_dst_byte_stride(inst) / type_sz(inst->dst.type); assert(stride > 0); - fs_reg tmp = ibld.vgrf(inst->dst.type, stride); + elk_fs_reg tmp = ibld.vgrf(inst->dst.type, stride); ibld.UNDEF(tmp); tmp = horiz_stride(tmp, stride); /* Emit a series of 32-bit integer copies from the temporary into the * original destination. */ - const brw_reg_type raw_type = brw_int_type(MIN2(type_sz(tmp.type), 4), + const elk_reg_type raw_type = elk_int_type(MIN2(type_sz(tmp.type), 4), false); const unsigned n = type_sz(tmp.type) / type_sz(raw_type); - if (inst->predicate && inst->opcode != BRW_OPCODE_SEL) { + if (inst->predicate && inst->opcode != ELK_OPCODE_SEL) { /* Note that in general we cannot simply predicate the copies on the * same flag register as the original instruction, since it may have * been overwritten by the instruction itself. Instead initialize @@ -589,20 +589,20 @@ namespace { * where the execution type of an instruction is unsupported. */ bool - lower_exec_type(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_exec_type(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst) { assert(inst->dst.type == get_exec_type(inst)); const unsigned mask = has_invalid_exec_type(v->devinfo, inst); - const brw_reg_type raw_type = required_exec_type(v->devinfo, inst); + const elk_reg_type raw_type = required_exec_type(v->devinfo, inst); const unsigned n = get_exec_type_size(inst) / type_sz(raw_type); const fs_builder ibld(v, block, inst); - fs_reg tmp = ibld.vgrf(inst->dst.type, inst->dst.stride); + elk_fs_reg tmp = ibld.vgrf(inst->dst.type, inst->dst.stride); ibld.UNDEF(tmp); tmp = horiz_stride(tmp, inst->dst.stride); for (unsigned j = 0; j < n; j++) { - fs_inst sub_inst = *inst; + elk_fs_inst sub_inst = *inst; for (unsigned i = 0; i < inst->sources; i++) { if (mask & (1u << i)) { @@ -617,9 +617,9 @@ namespace { assert(!sub_inst.flags_written(v->devinfo) && !sub_inst.saturate); ibld.emit(sub_inst); - fs_inst *mov = ibld.MOV(subscript(inst->dst, raw_type, j), + elk_fs_inst *mov = ibld.MOV(subscript(inst->dst, raw_type, j), subscript(tmp, raw_type, j)); - if (inst->opcode != BRW_OPCODE_SEL) { + if (inst->opcode != ELK_OPCODE_SEL) { mov->predicate = inst->predicate; mov->predicate_inverse = inst->predicate_inverse; } @@ -636,7 +636,7 @@ namespace { * instruction. */ bool - lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_instruction(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst) { const intel_device_info *devinfo = v->devinfo; bool progress = false; @@ -663,11 +663,11 @@ namespace { } bool -fs_visitor::lower_regioning() +elk_fs_visitor::lower_regioning() { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) progress |= lower_instruction(this, block, inst); if (progress) diff --git a/src/intel/compiler/elk/elk_fs_nir.cpp b/src/intel/compiler/elk/elk_fs_nir.cpp index cb978ea3cfb..733df6cf4f0 100644 --- a/src/intel/compiler/elk/elk_fs_nir.cpp +++ b/src/intel/compiler/elk/elk_fs_nir.cpp @@ -35,7 +35,7 @@ using namespace elk; -struct brw_fs_bind_info { +struct elk_fs_bind_info { bool valid; bool bindless; unsigned block; @@ -43,8 +43,8 @@ struct brw_fs_bind_info { unsigned binding; }; -struct nir_to_brw_state { - fs_visitor &s; +struct nir_to_elk_state { + elk_fs_visitor &s; const nir_shader *nir; const intel_device_info *devinfo; void *mem_ctx; @@ -54,43 +54,43 @@ struct nir_to_brw_state { */ fs_builder bld; - fs_reg *ssa_values; - fs_inst **resource_insts; - struct brw_fs_bind_info *ssa_bind_infos; - fs_reg *resource_values; - fs_reg *system_values; + elk_fs_reg *ssa_values; + elk_fs_inst **resource_insts; + struct elk_fs_bind_info *ssa_bind_infos; + elk_fs_reg *resource_values; + elk_fs_reg *system_values; }; -static fs_reg get_nir_src(nir_to_brw_state &ntb, const nir_src &src); -static fs_reg get_nir_def(nir_to_brw_state &ntb, const nir_def &def); +static elk_fs_reg get_nir_src(nir_to_elk_state &ntb, const nir_src &src); +static elk_fs_reg get_nir_def(nir_to_elk_state &ntb, const nir_def &def); static nir_component_mask_t get_nir_write_mask(const nir_def &def); -static void fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr); -static fs_reg emit_samplepos_setup(nir_to_brw_state &ntb); -static fs_reg emit_sampleid_setup(nir_to_brw_state &ntb); -static fs_reg emit_samplemaskin_setup(nir_to_brw_state &ntb); -static fs_reg emit_shading_rate_setup(nir_to_brw_state &ntb); +static void fs_nir_emit_intrinsic(nir_to_elk_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr); +static elk_fs_reg emit_samplepos_setup(nir_to_elk_state &ntb); +static elk_fs_reg emit_sampleid_setup(nir_to_elk_state &ntb); +static elk_fs_reg emit_samplemaskin_setup(nir_to_elk_state &ntb); +static elk_fs_reg emit_shading_rate_setup(nir_to_elk_state &ntb); -static void fs_nir_emit_impl(nir_to_brw_state &ntb, nir_function_impl *impl); -static void fs_nir_emit_cf_list(nir_to_brw_state &ntb, exec_list *list); -static void fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt); -static void fs_nir_emit_loop(nir_to_brw_state &ntb, nir_loop *loop); -static void fs_nir_emit_block(nir_to_brw_state &ntb, nir_block *block); -static void fs_nir_emit_instr(nir_to_brw_state &ntb, nir_instr *instr); +static void fs_nir_emit_impl(nir_to_elk_state &ntb, nir_function_impl *impl); +static void fs_nir_emit_cf_list(nir_to_elk_state &ntb, exec_list *list); +static void fs_nir_emit_if(nir_to_elk_state &ntb, nir_if *if_stmt); +static void fs_nir_emit_loop(nir_to_elk_state &ntb, nir_loop *loop); +static void fs_nir_emit_block(nir_to_elk_state &ntb, nir_block *block); +static void fs_nir_emit_instr(nir_to_elk_state &ntb, nir_instr *instr); -static void fs_nir_emit_surface_atomic(nir_to_brw_state &ntb, +static void fs_nir_emit_surface_atomic(nir_to_elk_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr, - fs_reg surface, + elk_fs_reg surface, bool bindless); -static void fs_nir_emit_global_atomic(nir_to_brw_state &ntb, +static void fs_nir_emit_global_atomic(nir_to_elk_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr); static void -fs_nir_setup_outputs(nir_to_brw_state &ntb) +fs_nir_setup_outputs(nir_to_elk_state &ntb) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; if (s.stage == MESA_SHADER_TESS_CTRL || s.stage == MESA_SHADER_FRAGMENT) @@ -124,7 +124,7 @@ fs_nir_setup_outputs(nir_to_brw_state &ntb) reg_size = MAX2(vec4s[i + loc] + i, reg_size); } - fs_reg reg = ntb.bld.vgrf(BRW_REGISTER_TYPE_F, 4 * reg_size); + elk_fs_reg reg = ntb.bld.vgrf(ELK_REGISTER_TYPE_F, 4 * reg_size); for (unsigned i = 0; i < reg_size; i++) { assert(loc + i < ARRAY_SIZE(s.outputs)); s.outputs[loc + i] = offset(reg, ntb.bld, 4 * i); @@ -135,7 +135,7 @@ fs_nir_setup_outputs(nir_to_brw_state &ntb) } static void -fs_nir_setup_uniforms(fs_visitor &s) +fs_nir_setup_uniforms(elk_fs_visitor &s) { const intel_device_info *devinfo = s.devinfo; @@ -153,27 +153,27 @@ fs_nir_setup_uniforms(fs_visitor &s) * easier later to split between cross thread and per thread * uniforms. */ - uint32_t *param = brw_stage_prog_data_add_params(s.prog_data, 1); - *param = BRW_PARAM_BUILTIN_SUBGROUP_ID; + uint32_t *param = elk_stage_prog_data_add_params(s.prog_data, 1); + *param = ELK_PARAM_BUILTIN_SUBGROUP_ID; s.uniforms++; } } -static fs_reg -emit_work_group_id_setup(nir_to_brw_state &ntb) +static elk_fs_reg +emit_work_group_id_setup(nir_to_elk_state &ntb) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; const fs_builder &bld = ntb.bld; assert(gl_shader_stage_is_compute(s.stage)); - fs_reg id = bld.vgrf(BRW_REGISTER_TYPE_UD, 3); + elk_fs_reg id = bld.vgrf(ELK_REGISTER_TYPE_UD, 3); - struct brw_reg r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD)); + struct elk_reg r0_1(retype(elk_vec1_grf(0, 1), ELK_REGISTER_TYPE_UD)); bld.MOV(id, r0_1); - struct brw_reg r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD)); - struct brw_reg r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD)); + struct elk_reg r0_6(retype(elk_vec1_grf(0, 6), ELK_REGISTER_TYPE_UD)); + struct elk_reg r0_7(retype(elk_vec1_grf(0, 7), ELK_REGISTER_TYPE_UD)); bld.MOV(offset(id, bld, 1), r0_6); bld.MOV(offset(id, bld, 2), r0_7); @@ -181,10 +181,10 @@ emit_work_group_id_setup(nir_to_brw_state &ntb) } static bool -emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) +emit_system_values_block(nir_to_elk_state &ntb, nir_block *block) { - fs_visitor &s = ntb.s; - fs_reg *reg; + elk_fs_visitor &s = ntb.s; + elk_fs_reg *reg; nir_foreach_instr(instr, block) { if (instr->type != nir_instr_type_intrinsic) @@ -201,11 +201,11 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_instance_id: case nir_intrinsic_load_base_instance: - unreachable("should be lowered by brw_nir_lower_vs_inputs()."); + unreachable("should be lowered by elk_nir_lower_vs_inputs()."); break; case nir_intrinsic_load_draw_id: - unreachable("should be lowered by brw_nir_lower_vs_inputs()."); + unreachable("should be lowered by elk_nir_lower_vs_inputs()."); break; case nir_intrinsic_load_invocation_id: @@ -267,7 +267,7 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) * subspans 0 and 1) in SIMD8 and an additional byte (the pixel * masks for 2 and 3) in SIMD16. */ - fs_reg shifted = abld.vgrf(BRW_REGISTER_TYPE_UW, 1); + elk_fs_reg shifted = abld.vgrf(ELK_REGISTER_TYPE_UW, 1); for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); @@ -276,11 +276,11 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) * stored in R0.15/R1.15 on gfx20+ and in R1.7/R2.7 on * gfx6+. */ - const struct brw_reg reg = s.devinfo->ver >= 20 ? - xe2_vec1_grf(i, 15) : brw_vec1_grf(i + 1, 7); + const struct elk_reg reg = s.devinfo->ver >= 20 ? + xe2_vec1_grf(i, 15) : elk_vec1_grf(i + 1, 7); hbld.SHR(offset(shifted, hbld, i), - stride(retype(reg, BRW_REGISTER_TYPE_UB), 1, 8, 0), - brw_imm_v(0x76543210)); + stride(retype(reg, ELK_REGISTER_TYPE_UB), 1, 8, 0), + elk_imm_v(0x76543210)); } /* A set bit in the pixel mask means the channel is enabled, but @@ -291,20 +291,20 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) * performs 1's complement negation, so we can use that instead of * a NOT instruction. */ - fs_reg inverted = negate(shifted); + elk_fs_reg inverted = negate(shifted); if (s.devinfo->ver < 8) { - inverted = abld.vgrf(BRW_REGISTER_TYPE_UW); + inverted = abld.vgrf(ELK_REGISTER_TYPE_UW); abld.NOT(inverted, shifted); } /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing * with 1 and negating. */ - fs_reg anded = abld.vgrf(BRW_REGISTER_TYPE_UD, 1); - abld.AND(anded, inverted, brw_imm_uw(1)); + elk_fs_reg anded = abld.vgrf(ELK_REGISTER_TYPE_UD, 1); + abld.AND(anded, inverted, elk_imm_uw(1)); - fs_reg dst = abld.vgrf(BRW_REGISTER_TYPE_D, 1); - abld.MOV(dst, negate(retype(anded, BRW_REGISTER_TYPE_D))); + elk_fs_reg dst = abld.vgrf(ELK_REGISTER_TYPE_D, 1); + abld.MOV(dst, negate(retype(anded, ELK_REGISTER_TYPE_D))); *reg = dst; } break; @@ -324,14 +324,14 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) } static void -fs_nir_emit_system_values(nir_to_brw_state &ntb) +fs_nir_emit_system_values(nir_to_elk_state &ntb) { const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; - ntb.system_values = ralloc_array(ntb.mem_ctx, fs_reg, SYSTEM_VALUE_MAX); + ntb.system_values = ralloc_array(ntb.mem_ctx, elk_fs_reg, SYSTEM_VALUE_MAX); for (unsigned i = 0; i < SYSTEM_VALUE_MAX; i++) { - ntb.system_values[i] = fs_reg(); + ntb.system_values[i] = elk_fs_reg(); } /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we @@ -339,17 +339,17 @@ fs_nir_emit_system_values(nir_to_brw_state &ntb) */ { const fs_builder abld = bld.annotate("gl_SubgroupInvocation", NULL); - fs_reg ® = ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]; - reg = abld.vgrf(BRW_REGISTER_TYPE_UW); + elk_fs_reg ® = ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]; + reg = abld.vgrf(ELK_REGISTER_TYPE_UW); abld.UNDEF(reg); const fs_builder allbld8 = abld.group(8, 0).exec_all(); - allbld8.MOV(reg, brw_imm_v(0x76543210)); + allbld8.MOV(reg, elk_imm_v(0x76543210)); if (s.dispatch_width > 8) - allbld8.ADD(byte_offset(reg, 16), reg, brw_imm_uw(8u)); + allbld8.ADD(byte_offset(reg, 16), reg, elk_imm_uw(8u)); if (s.dispatch_width > 16) { const fs_builder allbld16 = abld.group(16, 0).exec_all(); - allbld16.ADD(byte_offset(reg, 32), reg, brw_imm_uw(16u)); + allbld16.ADD(byte_offset(reg, 32), reg, elk_imm_uw(16u)); } } @@ -359,18 +359,18 @@ fs_nir_emit_system_values(nir_to_brw_state &ntb) } static void -fs_nir_emit_impl(nir_to_brw_state &ntb, nir_function_impl *impl) +fs_nir_emit_impl(nir_to_elk_state &ntb, nir_function_impl *impl) { - ntb.ssa_values = rzalloc_array(ntb.mem_ctx, fs_reg, impl->ssa_alloc); - ntb.resource_insts = rzalloc_array(ntb.mem_ctx, fs_inst *, impl->ssa_alloc); - ntb.ssa_bind_infos = rzalloc_array(ntb.mem_ctx, struct brw_fs_bind_info, impl->ssa_alloc); - ntb.resource_values = rzalloc_array(ntb.mem_ctx, fs_reg, impl->ssa_alloc); + ntb.ssa_values = rzalloc_array(ntb.mem_ctx, elk_fs_reg, impl->ssa_alloc); + ntb.resource_insts = rzalloc_array(ntb.mem_ctx, elk_fs_inst *, impl->ssa_alloc); + ntb.ssa_bind_infos = rzalloc_array(ntb.mem_ctx, struct elk_fs_bind_info, impl->ssa_alloc); + ntb.resource_values = rzalloc_array(ntb.mem_ctx, elk_fs_reg, impl->ssa_alloc); fs_nir_emit_cf_list(ntb, &impl->body); } static void -fs_nir_emit_cf_list(nir_to_brw_state &ntb, exec_list *list) +fs_nir_emit_cf_list(nir_to_elk_state &ntb, exec_list *list) { exec_list_validate(list); foreach_list_typed(nir_cf_node, node, node, list) { @@ -394,13 +394,13 @@ fs_nir_emit_cf_list(nir_to_brw_state &ntb, exec_list *list) } static void -fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) +fs_nir_emit_if(nir_to_elk_state &ntb, nir_if *if_stmt) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; bool invert; - fs_reg cond_reg; + elk_fs_reg cond_reg; /* If the condition has the form !other_condition, use other_condition as * the source, but invert the predicate on the if instruction. @@ -412,13 +412,13 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]); if (devinfo->ver <= 5 && - (cond->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) { + (cond->instr.pass_flags & ELK_NIR_BOOLEAN_MASK) == ELK_NIR_BOOLEAN_NEEDS_RESOLVE) { /* redo boolean resolve on gen5 */ - fs_reg masked = ntb.s.vgrf(glsl_int_type()); - bld.AND(masked, cond_reg, brw_imm_d(1)); + elk_fs_reg masked = ntb.s.vgrf(glsl_int_type()); + bld.AND(masked, cond_reg, elk_imm_d(1)); masked.negate = true; - fs_reg tmp = bld.vgrf(cond_reg.type); - bld.MOV(retype(tmp, BRW_REGISTER_TYPE_D), masked); + elk_fs_reg tmp = bld.vgrf(cond_reg.type); + bld.MOV(retype(tmp, ELK_REGISTER_TYPE_D), masked); cond_reg = tmp; } } else { @@ -427,20 +427,20 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) } /* first, put the condition into f0 */ - fs_inst *inst = bld.MOV(bld.null_reg_d(), - retype(cond_reg, BRW_REGISTER_TYPE_D)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; + elk_fs_inst *inst = bld.MOV(bld.null_reg_d(), + retype(cond_reg, ELK_REGISTER_TYPE_D)); + inst->conditional_mod = ELK_CONDITIONAL_NZ; - bld.IF(BRW_PREDICATE_NORMAL)->predicate_inverse = invert; + bld.IF(ELK_PREDICATE_NORMAL)->predicate_inverse = invert; fs_nir_emit_cf_list(ntb, &if_stmt->then_list); if (!nir_cf_list_is_empty_block(&if_stmt->else_list)) { - bld.emit(BRW_OPCODE_ELSE); + bld.emit(ELK_OPCODE_ELSE); fs_nir_emit_cf_list(ntb, &if_stmt->else_list); } - bld.emit(BRW_OPCODE_ENDIF); + bld.emit(ELK_OPCODE_ENDIF); if (devinfo->ver < 7) ntb.s.limit_dispatch_width(16, "Non-uniform control flow unsupported " @@ -448,17 +448,17 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) } static void -fs_nir_emit_loop(nir_to_brw_state &ntb, nir_loop *loop) +fs_nir_emit_loop(nir_to_elk_state &ntb, nir_loop *loop) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; assert(!nir_loop_has_continue_construct(loop)); - bld.emit(BRW_OPCODE_DO); + bld.emit(ELK_OPCODE_DO); fs_nir_emit_cf_list(ntb, &loop->body); - bld.emit(BRW_OPCODE_WHILE); + bld.emit(ELK_OPCODE_WHILE); if (devinfo->ver < 7) ntb.s.limit_dispatch_width(16, "Non-uniform control flow unsupported " @@ -466,7 +466,7 @@ fs_nir_emit_loop(nir_to_brw_state &ntb, nir_loop *loop) } static void -fs_nir_emit_block(nir_to_brw_state &ntb, nir_block *block) +fs_nir_emit_block(nir_to_elk_state &ntb, nir_block *block) { fs_builder bld = ntb.bld; @@ -482,8 +482,8 @@ fs_nir_emit_block(nir_to_brw_state &ntb, nir_block *block) * match instr. */ static bool -optimize_extract_to_float(nir_to_brw_state &ntb, nir_alu_instr *instr, - const fs_reg &result) +optimize_extract_to_float(nir_to_elk_state &ntb, nir_alu_instr *instr, + const elk_fs_reg &result) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; @@ -504,12 +504,12 @@ optimize_extract_to_float(nir_to_brw_state &ntb, nir_alu_instr *instr, unsigned element = nir_src_as_uint(src0->src[1].src); /* Element type to extract.*/ - const brw_reg_type type = brw_int_type( + const elk_reg_type type = elk_int_type( src0->op == nir_op_extract_u16 || src0->op == nir_op_extract_i16 ? 2 : 1, src0->op == nir_op_extract_i16 || src0->op == nir_op_extract_i8); - fs_reg op0 = get_nir_src(ntb, src0->src[0].src); - op0.type = brw_type_for_nir_type(devinfo, + elk_fs_reg op0 = get_nir_src(ntb, src0->src[0].src); + op0.type = elk_type_for_nir_type(devinfo, (nir_alu_type)(nir_op_infos[src0->op].input_types[0] | nir_src_bit_size(src0->src[0].src))); op0 = offset(op0, bld, src0->src[0].swizzle[0]); @@ -519,12 +519,12 @@ optimize_extract_to_float(nir_to_brw_state &ntb, nir_alu_instr *instr, } static bool -optimize_frontfacing_ternary(nir_to_brw_state &ntb, +optimize_frontfacing_ternary(nir_to_elk_state &ntb, nir_alu_instr *instr, - const fs_reg &result) + const elk_fs_reg &result) { const intel_device_info *devinfo = ntb.devinfo; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; nir_intrinsic_instr *src0 = nir_src_as_intrinsic(instr->src[0].src); if (src0 == NULL || src0->intrinsic != nir_intrinsic_load_front_face) @@ -542,7 +542,7 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */ assert(value1 == -value2); - fs_reg tmp = s.vgrf(glsl_int_type()); + elk_fs_reg tmp = s.vgrf(glsl_int_type()); if (devinfo->ver >= 20) { /* Gfx20+ has separate back-facing bits for each pair of @@ -551,20 +551,20 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, * each channel. Unfortunately they're no longer aligned to the * sign bit of a 16-bit word, so a left shift is necessary. */ - fs_reg ff = ntb.bld.vgrf(BRW_REGISTER_TYPE_UW); + elk_fs_reg ff = ntb.bld.vgrf(ELK_REGISTER_TYPE_UW); for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { const fs_builder hbld = ntb.bld.group(16, i); - const struct brw_reg gi_uw = retype(xe2_vec1_grf(i, 9), - BRW_REGISTER_TYPE_UW); - hbld.SHL(offset(ff, hbld, i), stride(gi_uw, 1, 8, 0), brw_imm_ud(4)); + const struct elk_reg gi_uw = retype(xe2_vec1_grf(i, 9), + ELK_REGISTER_TYPE_UW); + hbld.SHL(offset(ff, hbld, i), stride(gi_uw, 1, 8, 0), elk_imm_ud(4)); } if (value1 == -1.0f) ff.negate = true; - ntb.bld.OR(subscript(tmp, BRW_REGISTER_TYPE_UW, 1), ff, - brw_imm_uw(0x3f80)); + ntb.bld.OR(subscript(tmp, ELK_REGISTER_TYPE_UW, 1), ff, + elk_imm_uw(0x3f80)); } else if (devinfo->ver >= 12 && s.max_polygons == 2) { /* According to the BSpec "PS Thread Payload for Normal @@ -577,19 +577,19 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, for (unsigned i = 0; i < s.max_polygons; i++) { const fs_builder hbld = ntb.bld.group(8, i); - struct brw_reg g1 = retype(brw_vec1_grf(1, 1 + 5 * i), - BRW_REGISTER_TYPE_UW); + struct elk_reg g1 = retype(elk_vec1_grf(1, 1 + 5 * i), + ELK_REGISTER_TYPE_UW); if (value1 == -1.0f) g1.negate = true; - hbld.OR(subscript(offset(tmp, hbld, i), BRW_REGISTER_TYPE_UW, 1), - g1, brw_imm_uw(0x3f80)); + hbld.OR(subscript(offset(tmp, hbld, i), ELK_REGISTER_TYPE_UW, 1), + g1, elk_imm_uw(0x3f80)); } } else if (devinfo->ver >= 12) { /* Bit 15 of g1.1 is 0 if the polygon is front facing. */ - fs_reg g1 = fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W)); + elk_fs_reg g1 = elk_fs_reg(retype(elk_vec1_grf(1, 1), ELK_REGISTER_TYPE_W)); /* For (gl_FrontFacing ? 1.0 : -1.0), emit: * @@ -601,11 +601,11 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, if (value1 == -1.0f) g1.negate = true; - ntb.bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1), - g1, brw_imm_uw(0x3f80)); + ntb.bld.OR(subscript(tmp, ELK_REGISTER_TYPE_W, 1), + g1, elk_imm_uw(0x3f80)); } else if (devinfo->ver >= 6) { /* Bit 15 of g0.0 is 0 if the polygon is front facing. */ - fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W)); + elk_fs_reg g0 = elk_fs_reg(retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_W)); /* For (gl_FrontFacing ? 1.0 : -1.0), emit: * @@ -622,11 +622,11 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, g0.negate = true; } - ntb.bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1), - g0, brw_imm_uw(0x3f80)); + ntb.bld.OR(subscript(tmp, ELK_REGISTER_TYPE_W, 1), + g0, elk_imm_uw(0x3f80)); } else { /* Bit 31 of g1.6 is 0 if the polygon is front facing. */ - fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D)); + elk_fs_reg g1_6 = elk_fs_reg(retype(elk_vec1_grf(1, 6), ELK_REGISTER_TYPE_D)); /* For (gl_FrontFacing ? 1.0 : -1.0), emit: * @@ -643,60 +643,60 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, g1_6.negate = true; } - ntb.bld.OR(tmp, g1_6, brw_imm_d(0x3f800000)); + ntb.bld.OR(tmp, g1_6, elk_imm_d(0x3f800000)); } - ntb.bld.AND(retype(result, BRW_REGISTER_TYPE_D), tmp, brw_imm_d(0xbf800000)); + ntb.bld.AND(retype(result, ELK_REGISTER_TYPE_D), tmp, elk_imm_d(0xbf800000)); return true; } -static brw_rnd_mode -brw_rnd_mode_from_nir_op (const nir_op op) { +static elk_rnd_mode +elk_rnd_mode_from_nir_op (const nir_op op) { switch (op) { case nir_op_f2f16_rtz: - return BRW_RND_MODE_RTZ; + return ELK_RND_MODE_RTZ; case nir_op_f2f16_rtne: - return BRW_RND_MODE_RTNE; + return ELK_RND_MODE_RTNE; default: unreachable("Operation doesn't support rounding mode"); } } -static brw_rnd_mode -brw_rnd_mode_from_execution_mode(unsigned execution_mode) +static elk_rnd_mode +elk_rnd_mode_from_execution_mode(unsigned execution_mode) { if (nir_has_any_rounding_mode_rtne(execution_mode)) - return BRW_RND_MODE_RTNE; + return ELK_RND_MODE_RTNE; if (nir_has_any_rounding_mode_rtz(execution_mode)) - return BRW_RND_MODE_RTZ; - return BRW_RND_MODE_UNSPECIFIED; + return ELK_RND_MODE_RTZ; + return ELK_RND_MODE_UNSPECIFIED; } -static fs_reg -prepare_alu_destination_and_sources(nir_to_brw_state &ntb, +static elk_fs_reg +prepare_alu_destination_and_sources(nir_to_elk_state &ntb, const fs_builder &bld, nir_alu_instr *instr, - fs_reg *op, + elk_fs_reg *op, bool need_dest) { const intel_device_info *devinfo = ntb.devinfo; - fs_reg result = + elk_fs_reg result = need_dest ? get_nir_def(ntb, instr->def) : bld.null_reg_ud(); - result.type = brw_type_for_nir_type(devinfo, + result.type = elk_type_for_nir_type(devinfo, (nir_alu_type)(nir_op_infos[instr->op].output_type | instr->def.bit_size)); for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { op[i] = get_nir_src(ntb, instr->src[i].src); - op[i].type = brw_type_for_nir_type(devinfo, + op[i].type = elk_type_for_nir_type(devinfo, (nir_alu_type)(nir_op_infos[instr->op].input_types[i] | nir_src_bit_size(instr->src[i].src))); } /* Move and vecN instrutions may still be vectored. Return the raw, - * vectored source and destination so that fs_visitor::nir_emit_alu can + * vectored source and destination so that elk_fs_visitor::nir_emit_alu can * handle it. Other callers should not have to handle these kinds of * instructions. */ @@ -736,21 +736,21 @@ prepare_alu_destination_and_sources(nir_to_brw_state &ntb, return result; } -static fs_reg -resolve_source_modifiers(const fs_builder &bld, const fs_reg &src) +static elk_fs_reg +resolve_source_modifiers(const fs_builder &bld, const elk_fs_reg &src) { if (!src.abs && !src.negate) return src; - fs_reg temp = bld.vgrf(src.type); + elk_fs_reg temp = bld.vgrf(src.type); bld.MOV(temp, src); return temp; } static void -resolve_inot_sources(nir_to_brw_state &ntb, const fs_builder &bld, nir_alu_instr *instr, - fs_reg *op) +resolve_inot_sources(nir_to_elk_state &ntb, const fs_builder &bld, nir_alu_instr *instr, + elk_fs_reg *op) { for (unsigned i = 0; i < 2; i++) { nir_alu_instr *inot_instr = nir_src_as_alu_instr(instr->src[i].src); @@ -768,8 +768,8 @@ resolve_inot_sources(nir_to_brw_state &ntb, const fs_builder &bld, nir_alu_instr } static bool -try_emit_b2fi_of_inot(nir_to_brw_state &ntb, const fs_builder &bld, - fs_reg result, +try_emit_b2fi_of_inot(nir_to_elk_state &ntb, const fs_builder &bld, + elk_fs_reg result, nir_alu_instr *instr) { const intel_device_info *devinfo = bld.shader->devinfo; @@ -795,14 +795,14 @@ try_emit_b2fi_of_inot(nir_to_brw_state &ntb, const fs_builder &bld, /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1, * this is float(1 + a). */ - fs_reg op; + elk_fs_reg op; prepare_alu_destination_and_sources(ntb, bld, inot_instr, &op, false); /* Ignore the saturate modifier, if there is one. The result of the * arithmetic can only be 0 or 1, so the clamping will do nothing anyway. */ - bld.ADD(result, op, brw_imm_d(1)); + bld.ADD(result, op, elk_imm_d(1)); return true; } @@ -814,13 +814,13 @@ try_emit_b2fi_of_inot(nir_to_brw_state &ntb, const fs_builder &bld, * the source of \c instr that is a \c nir_op_fsign. */ static void -emit_fsign(nir_to_brw_state &ntb, const fs_builder &bld, const nir_alu_instr *instr, - fs_reg result, fs_reg *op, unsigned fsign_src) +emit_fsign(nir_to_elk_state &ntb, const fs_builder &bld, const nir_alu_instr *instr, + elk_fs_reg result, elk_fs_reg *op, unsigned fsign_src) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; const intel_device_info *devinfo = ntb.devinfo; - fs_inst *inst; + elk_fs_inst *inst; assert(instr->op == nir_op_fsign || instr->op == nir_op_fmul); assert(fsign_src < nir_op_infos[instr->op].num_inputs); @@ -843,7 +843,7 @@ emit_fsign(nir_to_brw_state &ntb, const fs_builder &bld, const nir_alu_instr *in (nir_alu_type)(nir_op_infos[instr->op].input_types[0] | nir_src_bit_size(fsign_instr->src[0].src)); - op[0].type = brw_type_for_nir_type(devinfo, t); + op[0].type = elk_type_for_nir_type(devinfo, t); unsigned channel = 0; if (nir_op_infos[instr->op].output_size == 0) { @@ -863,41 +863,41 @@ emit_fsign(nir_to_brw_state &ntb, const fs_builder &bld, const nir_alu_instr *in * * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero. */ - fs_reg zero = retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF); - bld.CMP(bld.null_reg_f(), op[0], zero, BRW_CONDITIONAL_NZ); + elk_fs_reg zero = retype(elk_imm_uw(0), ELK_REGISTER_TYPE_HF); + bld.CMP(bld.null_reg_f(), op[0], zero, ELK_CONDITIONAL_NZ); - op[0].type = BRW_REGISTER_TYPE_UW; - result.type = BRW_REGISTER_TYPE_UW; - bld.AND(result, op[0], brw_imm_uw(0x8000u)); + op[0].type = ELK_REGISTER_TYPE_UW; + result.type = ELK_REGISTER_TYPE_UW; + bld.AND(result, op[0], elk_imm_uw(0x8000u)); if (instr->op == nir_op_fsign) - inst = bld.OR(result, result, brw_imm_uw(0x3c00u)); + inst = bld.OR(result, result, elk_imm_uw(0x3c00u)); else { /* Use XOR here to get the result sign correct. */ - inst = bld.XOR(result, result, retype(op[1], BRW_REGISTER_TYPE_UW)); + inst = bld.XOR(result, result, retype(op[1], ELK_REGISTER_TYPE_UW)); } - inst->predicate = BRW_PREDICATE_NORMAL; + inst->predicate = ELK_PREDICATE_NORMAL; } else if (type_sz(op[0].type) == 4) { /* AND(val, 0x80000000) gives the sign bit. * * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not * zero. */ - bld.CMP(bld.null_reg_f(), op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_f(), op[0], elk_imm_f(0.0f), ELK_CONDITIONAL_NZ); - op[0].type = BRW_REGISTER_TYPE_UD; - result.type = BRW_REGISTER_TYPE_UD; - bld.AND(result, op[0], brw_imm_ud(0x80000000u)); + op[0].type = ELK_REGISTER_TYPE_UD; + result.type = ELK_REGISTER_TYPE_UD; + bld.AND(result, op[0], elk_imm_ud(0x80000000u)); if (instr->op == nir_op_fsign) - inst = bld.OR(result, result, brw_imm_ud(0x3f800000u)); + inst = bld.OR(result, result, elk_imm_ud(0x3f800000u)); else { /* Use XOR here to get the result sign correct. */ - inst = bld.XOR(result, result, retype(op[1], BRW_REGISTER_TYPE_UD)); + inst = bld.XOR(result, result, retype(op[1], ELK_REGISTER_TYPE_UD)); } - inst->predicate = BRW_PREDICATE_NORMAL; + inst->predicate = ELK_PREDICATE_NORMAL; } else { /* For doubles we do the same but we need to consider: * @@ -906,19 +906,19 @@ emit_fsign(nir_to_brw_state &ntb, const fs_builder &bld, const nir_alu_instr *in * - We need to produce a DF result. */ - fs_reg zero = s.vgrf(glsl_double_type()); - bld.MOV(zero, setup_imm_df(bld, 0.0)); - bld.CMP(bld.null_reg_df(), op[0], zero, BRW_CONDITIONAL_NZ); + elk_fs_reg zero = s.vgrf(glsl_double_type()); + bld.MOV(zero, elk_setup_imm_df(bld, 0.0)); + bld.CMP(bld.null_reg_df(), op[0], zero, ELK_CONDITIONAL_NZ); bld.MOV(result, zero); - fs_reg r = subscript(result, BRW_REGISTER_TYPE_UD, 1); - bld.AND(r, subscript(op[0], BRW_REGISTER_TYPE_UD, 1), - brw_imm_ud(0x80000000u)); + elk_fs_reg r = subscript(result, ELK_REGISTER_TYPE_UD, 1); + bld.AND(r, subscript(op[0], ELK_REGISTER_TYPE_UD, 1), + elk_imm_ud(0x80000000u)); if (instr->op == nir_op_fsign) { - set_predicate(BRW_PREDICATE_NORMAL, - bld.OR(r, r, brw_imm_ud(0x3ff00000u))); + set_predicate(ELK_PREDICATE_NORMAL, + bld.OR(r, r, elk_imm_ud(0x3ff00000u))); } else { if (devinfo->has_64bit_int) { /* This could be done better in some cases. If the scale is an @@ -927,16 +927,16 @@ emit_fsign(nir_to_brw_state &ntb, const fs_builder &bld, const nir_alu_instr *in * are currently zero instances of fsign(double(x))*IMM in shader-db * or any test suite, so it is hard to care at this time. */ - fs_reg result_int64 = retype(result, BRW_REGISTER_TYPE_UQ); + elk_fs_reg result_int64 = retype(result, ELK_REGISTER_TYPE_UQ); inst = bld.XOR(result_int64, result_int64, - retype(op[1], BRW_REGISTER_TYPE_UQ)); + retype(op[1], ELK_REGISTER_TYPE_UQ)); } else { - fs_reg result_int64 = retype(result, BRW_REGISTER_TYPE_UQ); - bld.MOV(subscript(result_int64, BRW_REGISTER_TYPE_UD, 0), - subscript(op[1], BRW_REGISTER_TYPE_UD, 0)); - bld.XOR(subscript(result_int64, BRW_REGISTER_TYPE_UD, 1), - subscript(result_int64, BRW_REGISTER_TYPE_UD, 1), - subscript(op[1], BRW_REGISTER_TYPE_UD, 1)); + elk_fs_reg result_int64 = retype(result, ELK_REGISTER_TYPE_UQ); + bld.MOV(subscript(result_int64, ELK_REGISTER_TYPE_UD, 0), + subscript(op[1], ELK_REGISTER_TYPE_UD, 0)); + bld.XOR(subscript(result_int64, ELK_REGISTER_TYPE_UD, 1), + subscript(result_int64, ELK_REGISTER_TYPE_UD, 1), + subscript(op[1], ELK_REGISTER_TYPE_UD, 1)); } } } @@ -983,25 +983,25 @@ is_const_zero(const nir_src &src) } static void -fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, +fs_nir_emit_alu(nir_to_elk_state &ntb, nir_alu_instr *instr, bool need_dest) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; - fs_inst *inst; + elk_fs_inst *inst; unsigned execution_mode = bld.shader->nir->info.float_controls_execution_mode; - fs_reg op[NIR_MAX_VEC_COMPONENTS]; - fs_reg result = prepare_alu_destination_and_sources(ntb, bld, instr, op, need_dest); + elk_fs_reg op[NIR_MAX_VEC_COMPONENTS]; + elk_fs_reg result = prepare_alu_destination_and_sources(ntb, bld, instr, op, need_dest); #ifndef NDEBUG /* Everything except raw moves, some type conversions, iabs, and ineg * should have 8-bit sources lowered by nir_lower_bit_size in - * brw_preprocess_nir or by brw_nir_lower_conversions in - * brw_postprocess_nir. + * elk_preprocess_nir or by elk_nir_lower_conversions in + * elk_postprocess_nir. */ switch (instr->op) { case nir_op_mov: @@ -1037,7 +1037,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_vec4: case nir_op_vec8: case nir_op_vec16: { - fs_reg temp = result; + elk_fs_reg temp = result; bool need_extra_copy = false; nir_intrinsic_instr *store_reg = @@ -1099,17 +1099,17 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_f2f16_rtne: case nir_op_f2f16_rtz: case nir_op_f2f16: { - brw_rnd_mode rnd = BRW_RND_MODE_UNSPECIFIED; + elk_rnd_mode rnd = ELK_RND_MODE_UNSPECIFIED; if (nir_op_f2f16 == instr->op) - rnd = brw_rnd_mode_from_execution_mode(execution_mode); + rnd = elk_rnd_mode_from_execution_mode(execution_mode); else - rnd = brw_rnd_mode_from_nir_op(instr->op); + rnd = elk_rnd_mode_from_nir_op(instr->op); - if (BRW_RND_MODE_UNSPECIFIED != rnd) - bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), brw_imm_d(rnd)); + if (ELK_RND_MODE_UNSPECIFIED != rnd) + bld.exec_all().emit(ELK_SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), elk_imm_d(rnd)); - assert(type_sz(op[0].type) < 8); /* brw_nir_lower_conversions */ + assert(type_sz(op[0].type) < 8); /* elk_nir_lower_conversions */ inst = bld.F32TO16(result, op[0]); break; } @@ -1123,7 +1123,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_b2f64: if (try_emit_b2fi_of_inot(ntb, bld, result, instr)) break; - op[0].type = BRW_REGISTER_TYPE_D; + op[0].type = ELK_REGISTER_TYPE_D; op[0].negate = !op[0].negate; FALLTHROUGH; case nir_op_i2f64: @@ -1143,22 +1143,22 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_f2u16: case nir_op_f2i8: case nir_op_f2u8: - if (result.type == BRW_REGISTER_TYPE_B || - result.type == BRW_REGISTER_TYPE_UB || - result.type == BRW_REGISTER_TYPE_HF) - assert(type_sz(op[0].type) < 8); /* brw_nir_lower_conversions */ + if (result.type == ELK_REGISTER_TYPE_B || + result.type == ELK_REGISTER_TYPE_UB || + result.type == ELK_REGISTER_TYPE_HF) + assert(type_sz(op[0].type) < 8); /* elk_nir_lower_conversions */ - if (op[0].type == BRW_REGISTER_TYPE_B || - op[0].type == BRW_REGISTER_TYPE_UB || - op[0].type == BRW_REGISTER_TYPE_HF) - assert(type_sz(result.type) < 8); /* brw_nir_lower_conversions */ + if (op[0].type == ELK_REGISTER_TYPE_B || + op[0].type == ELK_REGISTER_TYPE_UB || + op[0].type == ELK_REGISTER_TYPE_HF) + assert(type_sz(result.type) < 8); /* elk_nir_lower_conversions */ inst = bld.MOV(result, op[0]); break; case nir_op_i2i8: case nir_op_u2u8: - assert(type_sz(op[0].type) < 8); /* brw_nir_lower_conversions */ + assert(type_sz(op[0].type) < 8); /* elk_nir_lower_conversions */ FALLTHROUGH; case nir_op_i2i16: case nir_op_u2u16: { @@ -1174,8 +1174,8 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, prepare_alu_destination_and_sources(ntb, bld, extract_instr, op, false); const unsigned byte = nir_src_as_uint(extract_instr->src[1].src); - const brw_reg_type type = - brw_int_type(1, extract_instr->op == nir_op_extract_i8); + const elk_reg_type type = + elk_int_type(1, extract_instr->op == nir_op_extract_i8); op[0] = subscript(op[0], type, byte); } else if (extract_instr->op == nir_op_extract_u16 || @@ -1183,8 +1183,8 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, prepare_alu_destination_and_sources(ntb, bld, extract_instr, op, false); const unsigned word = nir_src_as_uint(extract_instr->src[1].src); - const brw_reg_type type = - brw_int_type(2, extract_instr->op == nir_op_extract_i16); + const elk_reg_type type = + elk_int_type(2, extract_instr->op == nir_op_extract_i16); op[0] = subscript(op[0], type, word); } @@ -1214,14 +1214,14 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_f2f32: if (nir_has_any_rounding_mode_enabled(execution_mode)) { - brw_rnd_mode rnd = - brw_rnd_mode_from_execution_mode(execution_mode); - bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), - brw_imm_d(rnd)); + elk_rnd_mode rnd = + elk_rnd_mode_from_execution_mode(execution_mode); + bld.exec_all().emit(ELK_SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), + elk_imm_d(rnd)); } - if (op[0].type == BRW_REGISTER_TYPE_HF) - assert(type_sz(result.type) < 8); /* brw_nir_lower_conversions */ + if (op[0].type == ELK_REGISTER_TYPE_HF) + assert(type_sz(result.type) < 8); /* elk_nir_lower_conversions */ inst = bld.MOV(result, op[0]); break; @@ -1231,46 +1231,46 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; case nir_op_frcp: - inst = bld.emit(SHADER_OPCODE_RCP, result, op[0]); + inst = bld.emit(ELK_SHADER_OPCODE_RCP, result, op[0]); break; case nir_op_fexp2: - inst = bld.emit(SHADER_OPCODE_EXP2, result, op[0]); + inst = bld.emit(ELK_SHADER_OPCODE_EXP2, result, op[0]); break; case nir_op_flog2: - inst = bld.emit(SHADER_OPCODE_LOG2, result, op[0]); + inst = bld.emit(ELK_SHADER_OPCODE_LOG2, result, op[0]); break; case nir_op_fsin: - inst = bld.emit(SHADER_OPCODE_SIN, result, op[0]); + inst = bld.emit(ELK_SHADER_OPCODE_SIN, result, op[0]); break; case nir_op_fcos: - inst = bld.emit(SHADER_OPCODE_COS, result, op[0]); + inst = bld.emit(ELK_SHADER_OPCODE_COS, result, op[0]); break; case nir_op_fddx_fine: - inst = bld.emit(FS_OPCODE_DDX_FINE, result, op[0]); + inst = bld.emit(ELK_FS_OPCODE_DDX_FINE, result, op[0]); break; case nir_op_fddx: case nir_op_fddx_coarse: - inst = bld.emit(FS_OPCODE_DDX_COARSE, result, op[0]); + inst = bld.emit(ELK_FS_OPCODE_DDX_COARSE, result, op[0]); break; case nir_op_fddy_fine: - inst = bld.emit(FS_OPCODE_DDY_FINE, result, op[0]); + inst = bld.emit(ELK_FS_OPCODE_DDY_FINE, result, op[0]); break; case nir_op_fddy: case nir_op_fddy_coarse: - inst = bld.emit(FS_OPCODE_DDY_COARSE, result, op[0]); + inst = bld.emit(ELK_FS_OPCODE_DDY_COARSE, result, op[0]); break; case nir_op_fadd: if (nir_has_any_rounding_mode_enabled(execution_mode)) { - brw_rnd_mode rnd = - brw_rnd_mode_from_execution_mode(execution_mode); - bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), - brw_imm_d(rnd)); + elk_rnd_mode rnd = + elk_rnd_mode_from_execution_mode(execution_mode); + bld.exec_all().emit(ELK_SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), + elk_imm_d(rnd)); } FALLTHROUGH; case nir_op_iadd: @@ -1288,11 +1288,11 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; case nir_op_isub_sat: - bld.emit(SHADER_OPCODE_ISUB_SAT, result, op[0], op[1]); + bld.emit(ELK_SHADER_OPCODE_ISUB_SAT, result, op[0], op[1]); break; case nir_op_usub_sat: - bld.emit(SHADER_OPCODE_USUB_SAT, result, op[0], op[1]); + bld.emit(ELK_SHADER_OPCODE_USUB_SAT, result, op[0], op[1]); break; case nir_op_irhadd: @@ -1304,7 +1304,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_ihadd: case nir_op_uhadd: { assert(instr->def.bit_size < 64); - fs_reg tmp = bld.vgrf(result.type); + elk_fs_reg tmp = bld.vgrf(result.type); if (devinfo->ver >= 8) { op[0] = resolve_source_modifiers(bld, op[0]); @@ -1313,7 +1313,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, /* AVG(x, y) - ((x ^ y) & 1) */ bld.XOR(tmp, op[0], op[1]); - bld.AND(tmp, tmp, retype(brw_imm_ud(1), result.type)); + bld.AND(tmp, tmp, retype(elk_imm_ud(1), result.type)); bld.AVG(result, op[0], op[1]); inst = bld.ADD(result, result, tmp); inst->src[1].negate = true; @@ -1333,10 +1333,10 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, * means. */ if (nir_has_any_rounding_mode_enabled(execution_mode)) { - brw_rnd_mode rnd = - brw_rnd_mode_from_execution_mode(execution_mode); - bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), - brw_imm_d(rnd)); + elk_rnd_mode rnd = + elk_rnd_mode_from_execution_mode(execution_mode); + bld.exec_all().emit(ELK_SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), + elk_imm_d(rnd)); } inst = bld.MUL(result, op[0], op[1]); @@ -1350,10 +1350,10 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_imul_32x16: case nir_op_umul_32x16: { const bool ud = instr->op == nir_op_umul_32x16; - const enum brw_reg_type word_type = - ud ? BRW_REGISTER_TYPE_UW : BRW_REGISTER_TYPE_W; - const enum brw_reg_type dword_type = - ud ? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D; + const enum elk_reg_type word_type = + ud ? ELK_REGISTER_TYPE_UW : ELK_REGISTER_TYPE_W; + const enum elk_reg_type dword_type = + ud ? ELK_REGISTER_TYPE_UD : ELK_REGISTER_TYPE_D; assert(instr->def.bit_size == 32); @@ -1379,9 +1379,9 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_umul_high: assert(instr->def.bit_size < 64); if (instr->def.bit_size == 32) { - bld.emit(SHADER_OPCODE_MULH, result, op[0], op[1]); + bld.emit(ELK_SHADER_OPCODE_MULH, result, op[0], op[1]); } else { - fs_reg tmp = bld.vgrf(brw_reg_type_from_bit_size(32, op[0].type)); + elk_fs_reg tmp = bld.vgrf(elk_reg_type_from_bit_size(32, op[0].type)); bld.MUL(tmp, op[0], op[1]); bld.MOV(result, subscript(tmp, result.type, 1)); } @@ -1390,7 +1390,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_idiv: case nir_op_udiv: assert(instr->def.bit_size < 64); - bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]); + bld.emit(ELK_SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]); break; case nir_op_uadd_carry: @@ -1406,16 +1406,16 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, * remainder. */ assert(instr->def.bit_size < 64); - bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]); + bld.emit(ELK_SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]); break; case nir_op_imod: { /* Get a regular C-style remainder. If a % b == 0, set the predicate. */ - bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]); + bld.emit(ELK_SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]); /* Math instructions don't support conditional mod */ inst = bld.MOV(bld.null_reg_d(), result); - inst->conditional_mod = BRW_CONDITIONAL_NZ; + inst->conditional_mod = ELK_CONDITIONAL_NZ; /* Now, we need to determine if signs of the sources are different. * When we XOR the sources, the top bit is 0 if they are the same and 1 @@ -1426,17 +1426,17 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, * XOR instruction. However, empirical experiments and Curro's reading * of the simulator source both indicate that it's safe. */ - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_D); inst = bld.XOR(tmp, op[0], op[1]); - inst->predicate = BRW_PREDICATE_NORMAL; - inst->conditional_mod = BRW_CONDITIONAL_L; + inst->predicate = ELK_PREDICATE_NORMAL; + inst->conditional_mod = ELK_CONDITIONAL_L; /* If the result of the initial remainder operation is non-zero and the * two sources have different signs, add in a copy of op[1] to get the * final integer modulus value. */ inst = bld.ADD(result, result, op[1]); - inst->predicate = BRW_PREDICATE_NORMAL; + inst->predicate = ELK_PREDICATE_NORMAL; break; } @@ -1444,7 +1444,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_fge32: case nir_op_feq32: case nir_op_fneu32: { - fs_reg dest = result; + elk_fs_reg dest = result; const uint32_t bit_size = nir_src_bit_size(instr->src[0].src); if (bit_size != 32) { @@ -1452,18 +1452,18 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, bld.UNDEF(dest); } - bld.CMP(dest, op[0], op[1], brw_cmod_for_nir_comparison(instr->op)); + bld.CMP(dest, op[0], op[1], elk_cmod_for_nir_comparison(instr->op)); if (bit_size > 32) { - bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0)); + bld.MOV(result, subscript(dest, ELK_REGISTER_TYPE_UD, 0)); } else if(bit_size < 32) { /* When we convert the result to 32-bit we need to be careful and do * it as a signed conversion to get sign extension (for 32-bit true) */ - const brw_reg_type src_type = - brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_D); + const elk_reg_type src_type = + elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_D); - bld.MOV(retype(result, BRW_REGISTER_TYPE_D), retype(dest, src_type)); + bld.MOV(retype(result, ELK_REGISTER_TYPE_D), retype(dest, src_type)); } break; } @@ -1474,7 +1474,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_uge32: case nir_op_ieq32: case nir_op_ine32: { - fs_reg dest = result; + elk_fs_reg dest = result; const uint32_t bit_size = type_sz(op[0].type) * 8; if (bit_size != 32) { @@ -1483,18 +1483,18 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, } bld.CMP(dest, op[0], op[1], - brw_cmod_for_nir_comparison(instr->op)); + elk_cmod_for_nir_comparison(instr->op)); if (bit_size > 32) { - bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0)); + bld.MOV(result, subscript(dest, ELK_REGISTER_TYPE_UD, 0)); } else if (bit_size < 32) { /* When we convert the result to 32-bit we need to be careful and do * it as a signed conversion to get sign extension (for 32-bit true) */ - const brw_reg_type src_type = - brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_D); + const elk_reg_type src_type = + elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_D); - bld.MOV(retype(result, BRW_REGISTER_TYPE_D), retype(dest, src_type)); + bld.MOV(retype(result, ELK_REGISTER_TYPE_D), retype(dest, src_type)); } break; } @@ -1516,18 +1516,18 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, /* Smash all of the sources and destination to be signed. This * doesn't matter for the operation of the instruction, but cmod * propagation fails on unsigned sources with negation (due to - * fs_inst::can_do_cmod returning false). + * elk_fs_inst::can_do_cmod returning false). */ result.type = - brw_type_for_nir_type(devinfo, + elk_type_for_nir_type(devinfo, (nir_alu_type)(nir_type_int | instr->def.bit_size)); op[0].type = - brw_type_for_nir_type(devinfo, + elk_type_for_nir_type(devinfo, (nir_alu_type)(nir_type_int | nir_src_bit_size(inot_src_instr->src[0].src))); op[1].type = - brw_type_for_nir_type(devinfo, + elk_type_for_nir_type(devinfo, (nir_alu_type)(nir_type_int | nir_src_bit_size(inot_src_instr->src[1].src))); @@ -1599,26 +1599,26 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, unreachable("not reached: should be handled by ldexp_to_arith()"); case nir_op_fsqrt: - inst = bld.emit(SHADER_OPCODE_SQRT, result, op[0]); + inst = bld.emit(ELK_SHADER_OPCODE_SQRT, result, op[0]); break; case nir_op_frsq: - inst = bld.emit(SHADER_OPCODE_RSQ, result, op[0]); + inst = bld.emit(ELK_SHADER_OPCODE_RSQ, result, op[0]); break; case nir_op_ftrunc: inst = bld.RNDZ(result, op[0]); if (devinfo->ver < 6) { - set_condmod(BRW_CONDITIONAL_R, inst); - set_predicate(BRW_PREDICATE_NORMAL, - bld.ADD(result, result, brw_imm_f(1.0f))); + set_condmod(ELK_CONDITIONAL_R, inst); + set_predicate(ELK_PREDICATE_NORMAL, + bld.ADD(result, result, elk_imm_f(1.0f))); inst = bld.MOV(result, result); /* for potential saturation */ } break; case nir_op_fceil: { op[0].negate = !op[0].negate; - fs_reg temp = s.vgrf(glsl_float_type()); + elk_fs_reg temp = s.vgrf(glsl_float_type()); bld.RNDD(temp, op[0]); temp.negate = true; inst = bld.MOV(result, temp); @@ -1633,49 +1633,49 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_fround_even: inst = bld.RNDE(result, op[0]); if (devinfo->ver < 6) { - set_condmod(BRW_CONDITIONAL_R, inst); - set_predicate(BRW_PREDICATE_NORMAL, - bld.ADD(result, result, brw_imm_f(1.0f))); + set_condmod(ELK_CONDITIONAL_R, inst); + set_predicate(ELK_PREDICATE_NORMAL, + bld.ADD(result, result, elk_imm_f(1.0f))); inst = bld.MOV(result, result); /* for potential saturation */ } break; case nir_op_fquantize2f16: { - fs_reg tmp16 = bld.vgrf(BRW_REGISTER_TYPE_D); - fs_reg tmp32 = bld.vgrf(BRW_REGISTER_TYPE_F); - fs_reg zero = bld.vgrf(BRW_REGISTER_TYPE_F); + elk_fs_reg tmp16 = bld.vgrf(ELK_REGISTER_TYPE_D); + elk_fs_reg tmp32 = bld.vgrf(ELK_REGISTER_TYPE_F); + elk_fs_reg zero = bld.vgrf(ELK_REGISTER_TYPE_F); /* The destination stride must be at least as big as the source stride. */ - tmp16 = subscript(tmp16, BRW_REGISTER_TYPE_HF, 0); + tmp16 = subscript(tmp16, ELK_REGISTER_TYPE_HF, 0); /* Check for denormal */ - fs_reg abs_src0 = op[0]; + elk_fs_reg abs_src0 = op[0]; abs_src0.abs = true; - bld.CMP(bld.null_reg_f(), abs_src0, brw_imm_f(ldexpf(1.0, -14)), - BRW_CONDITIONAL_L); + bld.CMP(bld.null_reg_f(), abs_src0, elk_imm_f(ldexpf(1.0, -14)), + ELK_CONDITIONAL_L); /* Get the appropriately signed zero */ - bld.AND(retype(zero, BRW_REGISTER_TYPE_UD), - retype(op[0], BRW_REGISTER_TYPE_UD), - brw_imm_ud(0x80000000)); + bld.AND(retype(zero, ELK_REGISTER_TYPE_UD), + retype(op[0], ELK_REGISTER_TYPE_UD), + elk_imm_ud(0x80000000)); /* Do the actual F32 -> F16 -> F32 conversion */ bld.F32TO16(tmp16, op[0]); bld.F16TO32(tmp32, tmp16); /* Select that or zero based on normal status */ inst = bld.SEL(result, zero, tmp32); - inst->predicate = BRW_PREDICATE_NORMAL; + inst->predicate = ELK_PREDICATE_NORMAL; break; } case nir_op_imin: case nir_op_umin: case nir_op_fmin: - inst = bld.emit_minmax(result, op[0], op[1], BRW_CONDITIONAL_L); + inst = bld.emit_minmax(result, op[0], op[1], ELK_CONDITIONAL_L); break; case nir_op_imax: case nir_op_umax: case nir_op_fmax: - inst = bld.emit_minmax(result, op[0], op[1], BRW_CONDITIONAL_GE); + inst = bld.emit_minmax(result, op[0], op[1], ELK_CONDITIONAL_GE); break; case nir_op_pack_snorm_2x16: @@ -1694,45 +1694,45 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 & execution_mode); FALLTHROUGH; case nir_op_unpack_half_2x16_split_x: - inst = bld.F16TO32(result, subscript(op[0], BRW_REGISTER_TYPE_HF, 0)); + inst = bld.F16TO32(result, subscript(op[0], ELK_REGISTER_TYPE_HF, 0)); break; case nir_op_unpack_half_2x16_split_y_flush_to_zero: assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 & execution_mode); FALLTHROUGH; case nir_op_unpack_half_2x16_split_y: - inst = bld.F16TO32(result, subscript(op[0], BRW_REGISTER_TYPE_HF, 1)); + inst = bld.F16TO32(result, subscript(op[0], ELK_REGISTER_TYPE_HF, 1)); break; case nir_op_pack_64_2x32_split: case nir_op_pack_32_2x16_split: - bld.emit(FS_OPCODE_PACK, result, op[0], op[1]); + bld.emit(ELK_FS_OPCODE_PACK, result, op[0], op[1]); break; case nir_op_pack_32_4x8_split: - bld.emit(FS_OPCODE_PACK, result, op, 4); + bld.emit(ELK_FS_OPCODE_PACK, result, op, 4); break; case nir_op_unpack_64_2x32_split_x: case nir_op_unpack_64_2x32_split_y: { if (instr->op == nir_op_unpack_64_2x32_split_x) - bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UD, 0)); + bld.MOV(result, subscript(op[0], ELK_REGISTER_TYPE_UD, 0)); else - bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UD, 1)); + bld.MOV(result, subscript(op[0], ELK_REGISTER_TYPE_UD, 1)); break; } case nir_op_unpack_32_2x16_split_x: case nir_op_unpack_32_2x16_split_y: { if (instr->op == nir_op_unpack_32_2x16_split_x) - bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UW, 0)); + bld.MOV(result, subscript(op[0], ELK_REGISTER_TYPE_UW, 0)); else - bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UW, 1)); + bld.MOV(result, subscript(op[0], ELK_REGISTER_TYPE_UW, 1)); break; } case nir_op_fpow: - inst = bld.emit(SHADER_OPCODE_POW, result, op[0], op[1]); + inst = bld.emit(ELK_SHADER_OPCODE_POW, result, op[0], op[1]); break; case nir_op_bitfield_reverse: @@ -1750,7 +1750,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_uclz: assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); - bld.LZD(retype(result, BRW_REGISTER_TYPE_UD), op[0]); + bld.LZD(retype(result, ELK_REGISTER_TYPE_UD), op[0]); break; case nir_op_ifind_msb: { @@ -1758,17 +1758,17 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); - bld.FBH(retype(result, BRW_REGISTER_TYPE_UD), op[0]); + bld.FBH(retype(result, ELK_REGISTER_TYPE_UD), op[0]); /* FBH counts from the MSB side, while GLSL's findMSB() wants the count * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then * subtract the result from 31 to convert the MSB count into an LSB * count. */ - bld.CMP(bld.null_reg_d(), result, brw_imm_d(-1), BRW_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_d(), result, elk_imm_d(-1), ELK_CONDITIONAL_NZ); - inst = bld.ADD(result, result, brw_imm_d(31)); - inst->predicate = BRW_PREDICATE_NORMAL; + inst = bld.ADD(result, result, elk_imm_d(31)); + inst->predicate = ELK_PREDICATE_NORMAL; inst->src[0].negate = true; break; } @@ -1821,7 +1821,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, */ case nir_op_ishl: if (instr->def.bit_size < 32) { - bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1)); + bld.AND(result, op[1], elk_imm_ud(instr->def.bit_size - 1)); bld.SHL(result, op[0], result); } else { bld.SHL(result, op[0], op[1]); @@ -1830,7 +1830,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; case nir_op_ishr: if (instr->def.bit_size < 32) { - bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1)); + bld.AND(result, op[1], elk_imm_ud(instr->def.bit_size - 1)); bld.ASR(result, op[0], result); } else { bld.ASR(result, op[0], op[1]); @@ -1839,7 +1839,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; case nir_op_ushr: if (instr->def.bit_size < 32) { - bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1)); + bld.AND(result, op[1], elk_imm_ud(instr->def.bit_size - 1)); bld.SHR(result, op[0], result); } else { bld.SHR(result, op[0], op[1]); @@ -1855,15 +1855,15 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; case nir_op_pack_half_2x16_split: - bld.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1]); + bld.emit(ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1]); break; case nir_op_sdot_4x8_iadd: case nir_op_sdot_4x8_iadd_sat: - inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_D), - retype(op[2], BRW_REGISTER_TYPE_D), - retype(op[0], BRW_REGISTER_TYPE_D), - retype(op[1], BRW_REGISTER_TYPE_D)); + inst = bld.DP4A(retype(result, ELK_REGISTER_TYPE_D), + retype(op[2], ELK_REGISTER_TYPE_D), + retype(op[0], ELK_REGISTER_TYPE_D), + retype(op[1], ELK_REGISTER_TYPE_D)); if (instr->op == nir_op_sdot_4x8_iadd_sat) inst->saturate = true; @@ -1871,10 +1871,10 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_udot_4x8_uadd: case nir_op_udot_4x8_uadd_sat: - inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_UD), - retype(op[2], BRW_REGISTER_TYPE_UD), - retype(op[0], BRW_REGISTER_TYPE_UD), - retype(op[1], BRW_REGISTER_TYPE_UD)); + inst = bld.DP4A(retype(result, ELK_REGISTER_TYPE_UD), + retype(op[2], ELK_REGISTER_TYPE_UD), + retype(op[0], ELK_REGISTER_TYPE_UD), + retype(op[1], ELK_REGISTER_TYPE_UD)); if (instr->op == nir_op_udot_4x8_uadd_sat) inst->saturate = true; @@ -1882,10 +1882,10 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_sudot_4x8_iadd: case nir_op_sudot_4x8_iadd_sat: - inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_D), - retype(op[2], BRW_REGISTER_TYPE_D), - retype(op[0], BRW_REGISTER_TYPE_D), - retype(op[1], BRW_REGISTER_TYPE_UD)); + inst = bld.DP4A(retype(result, ELK_REGISTER_TYPE_D), + retype(op[2], ELK_REGISTER_TYPE_D), + retype(op[0], ELK_REGISTER_TYPE_D), + retype(op[1], ELK_REGISTER_TYPE_UD)); if (instr->op == nir_op_sudot_4x8_iadd_sat) inst->saturate = true; @@ -1893,10 +1893,10 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_ffma: if (nir_has_any_rounding_mode_enabled(execution_mode)) { - brw_rnd_mode rnd = - brw_rnd_mode_from_execution_mode(execution_mode); - bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), - brw_imm_d(rnd)); + elk_rnd_mode rnd = + elk_rnd_mode_from_execution_mode(execution_mode); + bld.exec_all().emit(ELK_SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), + elk_imm_d(rnd)); } inst = bld.MAD(result, op[2], op[1], op[0]); @@ -1904,10 +1904,10 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_flrp: if (nir_has_any_rounding_mode_enabled(execution_mode)) { - brw_rnd_mode rnd = - brw_rnd_mode_from_execution_mode(execution_mode); - bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), - brw_imm_d(rnd)); + elk_rnd_mode rnd = + elk_rnd_mode_from_execution_mode(execution_mode); + bld.exec_all().emit(ELK_SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), + elk_imm_d(rnd)); } inst = bld.LRP(result, op[0], op[1], op[2]); @@ -1917,9 +1917,9 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, if (optimize_frontfacing_ternary(ntb, instr, result)) return; - bld.CMP(bld.null_reg_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_d(), op[0], elk_imm_d(0), ELK_CONDITIONAL_NZ); inst = bld.SEL(result, op[1], op[2]); - inst->predicate = BRW_PREDICATE_NORMAL; + inst->predicate = ELK_PREDICATE_NORMAL; break; case nir_op_extract_u8: @@ -1933,11 +1933,11 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, * Use two instructions and a word or DWord intermediate integer type. */ if (instr->def.bit_size == 64) { - const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8); + const elk_reg_type type = elk_int_type(1, instr->op == nir_op_extract_i8); if (instr->op == nir_op_extract_i8) { /* If we need to sign extend, extract to a word first */ - fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W); + elk_fs_reg w_temp = bld.vgrf(ELK_REGISTER_TYPE_W); bld.MOV(w_temp, subscript(op[0], type, byte)); bld.MOV(result, w_temp); } else if (byte & 1) { @@ -1945,16 +1945,16 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, * offset. */ bld.SHR(result, - subscript(op[0], BRW_REGISTER_TYPE_UW, byte / 2), - brw_imm_uw(8)); + subscript(op[0], ELK_REGISTER_TYPE_UW, byte / 2), + elk_imm_uw(8)); } else { /* Otherwise use an AND with 0xff and a word type */ bld.AND(result, - subscript(op[0], BRW_REGISTER_TYPE_UW, byte / 2), - brw_imm_uw(0xff)); + subscript(op[0], ELK_REGISTER_TYPE_UW, byte / 2), + elk_imm_uw(0xff)); } } else { - const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8); + const elk_reg_type type = elk_int_type(1, instr->op == nir_op_extract_i8); bld.MOV(result, subscript(op[0], type, byte)); } break; @@ -1962,7 +1962,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_extract_u16: case nir_op_extract_i16: { - const brw_reg_type type = brw_int_type(2, instr->op == nir_op_extract_i16); + const elk_reg_type type = elk_int_type(2, instr->op == nir_op_extract_i16); unsigned word = nir_src_as_uint(instr->src[1].src); bld.MOV(result, subscript(op[0], type, word)); break; @@ -1977,51 +1977,51 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, */ if (devinfo->ver <= 5 && !result.is_null() && - (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) { - fs_reg masked = s.vgrf(glsl_int_type()); - bld.AND(masked, result, brw_imm_d(1)); + (instr->instr.pass_flags & ELK_NIR_BOOLEAN_MASK) == ELK_NIR_BOOLEAN_NEEDS_RESOLVE) { + elk_fs_reg masked = s.vgrf(glsl_int_type()); + bld.AND(masked, result, elk_imm_d(1)); masked.negate = true; - bld.MOV(retype(result, BRW_REGISTER_TYPE_D), masked); + bld.MOV(retype(result, ELK_REGISTER_TYPE_D), masked); } } static void -fs_nir_emit_load_const(nir_to_brw_state &ntb, +fs_nir_emit_load_const(nir_to_elk_state &ntb, nir_load_const_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - const brw_reg_type reg_type = - brw_reg_type_from_bit_size(instr->def.bit_size, BRW_REGISTER_TYPE_D); - fs_reg reg = bld.vgrf(reg_type, instr->def.num_components); + const elk_reg_type reg_type = + elk_reg_type_from_bit_size(instr->def.bit_size, ELK_REGISTER_TYPE_D); + elk_fs_reg reg = bld.vgrf(reg_type, instr->def.num_components); switch (instr->def.bit_size) { case 8: for (unsigned i = 0; i < instr->def.num_components; i++) - bld.MOV(offset(reg, bld, i), setup_imm_b(bld, instr->value[i].i8)); + bld.MOV(offset(reg, bld, i), elk_setup_imm_b(bld, instr->value[i].i8)); break; case 16: for (unsigned i = 0; i < instr->def.num_components; i++) - bld.MOV(offset(reg, bld, i), brw_imm_w(instr->value[i].i16)); + bld.MOV(offset(reg, bld, i), elk_imm_w(instr->value[i].i16)); break; case 32: for (unsigned i = 0; i < instr->def.num_components; i++) - bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value[i].i32)); + bld.MOV(offset(reg, bld, i), elk_imm_d(instr->value[i].i32)); break; case 64: assert(devinfo->ver >= 7); if (!devinfo->has_64bit_int) { for (unsigned i = 0; i < instr->def.num_components; i++) { - bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_DF), - setup_imm_df(bld, instr->value[i].f64)); + bld.MOV(retype(offset(reg, bld, i), ELK_REGISTER_TYPE_DF), + elk_setup_imm_df(bld, instr->value[i].f64)); } } else { for (unsigned i = 0; i < instr->def.num_components; i++) - bld.MOV(offset(reg, bld, i), brw_imm_q(instr->value[i].i64)); + bld.MOV(offset(reg, bld, i), elk_imm_q(instr->value[i].i64)); } break; @@ -2033,7 +2033,7 @@ fs_nir_emit_load_const(nir_to_brw_state &ntb, } static bool -get_nir_src_bindless(nir_to_brw_state &ntb, const nir_src &src) +get_nir_src_bindless(nir_to_elk_state &ntb, const nir_src &src) { return ntb.ssa_bind_infos[src.ssa->index].bindless; } @@ -2045,27 +2045,27 @@ is_resource_src(nir_src src) nir_instr_as_intrinsic(src.ssa->parent_instr)->intrinsic == nir_intrinsic_resource_intel; } -static fs_reg -get_resource_nir_src(nir_to_brw_state &ntb, const nir_src &src) +static elk_fs_reg +get_resource_nir_src(nir_to_elk_state &ntb, const nir_src &src) { if (!is_resource_src(src)) - return fs_reg(); + return elk_fs_reg(); return ntb.resource_values[src.ssa->index]; } -static fs_reg -get_nir_src(nir_to_brw_state &ntb, const nir_src &src) +static elk_fs_reg +get_nir_src(nir_to_elk_state &ntb, const nir_src &src) { const intel_device_info *devinfo = ntb.devinfo; nir_intrinsic_instr *load_reg = nir_load_reg_for_def(src.ssa); - fs_reg reg; + elk_fs_reg reg; if (!load_reg) { if (nir_src_is_undef(src)) { - const brw_reg_type reg_type = - brw_reg_type_from_bit_size(src.ssa->bit_size, - BRW_REGISTER_TYPE_D); + const elk_reg_type reg_type = + elk_reg_type_from_bit_size(src.ssa->bit_size, + ELK_REGISTER_TYPE_D); reg = ntb.bld.vgrf(reg_type, src.ssa->num_components); } else { reg = ntb.ssa_values[src.ssa->index]; @@ -2080,14 +2080,14 @@ get_nir_src(nir_to_brw_state &ntb, const nir_src &src) if (nir_src_bit_size(src) == 64 && devinfo->ver == 7) { /* The only 64-bit type available on gfx7 is DF, so use that. */ - reg.type = BRW_REGISTER_TYPE_DF; + reg.type = ELK_REGISTER_TYPE_DF; } else { /* To avoid floating-point denorm flushing problems, set the type by * default to an integer type - instructions that need floating point * semantics will set this to F if they need to */ - reg.type = brw_reg_type_from_bit_size(nir_src_bit_size(src), - BRW_REGISTER_TYPE_D); + reg.type = elk_reg_type_from_bit_size(nir_src_bit_size(src), + ELK_REGISTER_TYPE_D); } return reg; @@ -2102,26 +2102,26 @@ get_nir_src(nir_to_brw_state &ntb, const nir_src &src) * enough restrictions in 64-bit immediates that you can't take the return * value and treat it the same as the result of get_nir_src(). */ -static fs_reg -get_nir_src_imm(nir_to_brw_state &ntb, const nir_src &src) +static elk_fs_reg +get_nir_src_imm(nir_to_elk_state &ntb, const nir_src &src) { assert(nir_src_bit_size(src) == 32); return nir_src_is_const(src) ? - fs_reg(brw_imm_d(nir_src_as_int(src))) : get_nir_src(ntb, src); + elk_fs_reg(elk_imm_d(nir_src_as_int(src))) : get_nir_src(ntb, src); } -static fs_reg -get_nir_def(nir_to_brw_state &ntb, const nir_def &def) +static elk_fs_reg +get_nir_def(nir_to_elk_state &ntb, const nir_def &def) { const fs_builder &bld = ntb.bld; nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&def); if (!store_reg) { - const brw_reg_type reg_type = - brw_reg_type_from_bit_size(def.bit_size, + const elk_reg_type reg_type = + elk_reg_type_from_bit_size(def.bit_size, def.bit_size == 8 ? - BRW_REGISTER_TYPE_D : - BRW_REGISTER_TYPE_F); + ELK_REGISTER_TYPE_D : + ELK_REGISTER_TYPE_F); ntb.ssa_values[def.index] = bld.vgrf(reg_type, def.num_components); bld.UNDEF(ntb.ssa_values[def.index]); @@ -2147,24 +2147,24 @@ get_nir_write_mask(const nir_def &def) } } -static fs_inst * +static elk_fs_inst * emit_pixel_interpolater_send(const fs_builder &bld, - enum opcode opcode, - const fs_reg &dst, - const fs_reg &src, - const fs_reg &desc, - const fs_reg &flag_reg, + enum elk_opcode opcode, + const elk_fs_reg &dst, + const elk_fs_reg &src, + const elk_fs_reg &desc, + const elk_fs_reg &flag_reg, glsl_interp_mode interpolation) { - struct brw_wm_prog_data *wm_prog_data = - brw_wm_prog_data(bld.shader->stage_prog_data); + struct elk_wm_prog_data *wm_prog_data = + elk_wm_prog_data(bld.shader->stage_prog_data); - fs_reg srcs[INTERP_NUM_SRCS]; + elk_fs_reg srcs[INTERP_NUM_SRCS]; srcs[INTERP_SRC_OFFSET] = src; srcs[INTERP_SRC_MSG_DESC] = desc; srcs[INTERP_SRC_DYNAMIC_MODE] = flag_reg; - fs_inst *inst = bld.emit(opcode, dst, srcs, INTERP_NUM_SRCS); + elk_fs_inst *inst = bld.emit(opcode, dst, srcs, INTERP_NUM_SRCS); /* 2 floats per slot returned */ inst->size_written = 2 * dst.component_size(inst->exec_size); if (interpolation == INTERP_MODE_NOPERSPECTIVE) { @@ -2184,26 +2184,26 @@ emit_pixel_interpolater_send(const fs_builder &bld, /** * Computes 1 << x, given a D/UD register containing some value x. */ -static fs_reg -intexp2(const fs_builder &bld, const fs_reg &x) +static elk_fs_reg +intexp2(const fs_builder &bld, const elk_fs_reg &x) { - assert(x.type == BRW_REGISTER_TYPE_UD || x.type == BRW_REGISTER_TYPE_D); + assert(x.type == ELK_REGISTER_TYPE_UD || x.type == ELK_REGISTER_TYPE_D); - fs_reg result = bld.vgrf(x.type, 1); - fs_reg one = bld.vgrf(x.type, 1); + elk_fs_reg result = bld.vgrf(x.type, 1); + elk_fs_reg one = bld.vgrf(x.type, 1); - bld.MOV(one, retype(brw_imm_d(1), one.type)); + bld.MOV(one, retype(elk_imm_d(1), one.type)); bld.SHL(result, one, x); return result; } static void -emit_gs_end_primitive(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src) +emit_gs_end_primitive(nir_to_elk_state &ntb, const nir_src &vertex_count_nir_src) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_GEOMETRY); - struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(s.prog_data); + struct elk_gs_prog_data *gs_prog_data = elk_gs_prog_data(s.prog_data); if (s.gs_compile->control_data_header_size_bits == 0) return; @@ -2220,8 +2220,8 @@ emit_gs_end_primitive(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src /* Cut bits use one bit per vertex. */ assert(s.gs_compile->control_data_bits_per_vertex == 1); - fs_reg vertex_count = get_nir_src(ntb, vertex_count_nir_src); - vertex_count.type = BRW_REGISTER_TYPE_UD; + elk_fs_reg vertex_count = get_nir_src(ntb, vertex_count_nir_src); + vertex_count.type = ELK_REGISTER_TYPE_UD; /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting * vertex n, 0 otherwise. So all we need to do here is mark bit @@ -2247,9 +2247,9 @@ emit_gs_end_primitive(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src const fs_builder abld = ntb.bld.annotate("end primitive"); /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */ - fs_reg prev_count = ntb.bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - abld.ADD(prev_count, vertex_count, brw_imm_ud(0xffffffffu)); - fs_reg mask = intexp2(abld, prev_count); + elk_fs_reg prev_count = ntb.bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + abld.ADD(prev_count, vertex_count, elk_imm_ud(0xffffffffu)); + elk_fs_reg mask = intexp2(abld, prev_count); /* Note: we're relying on the fact that the GEN SHL instruction only pays * attention to the lower 5 bits of its second source argument, so on this * architecture, 1 << (vertex_count - 1) is equivalent to 1 << @@ -2259,12 +2259,12 @@ emit_gs_end_primitive(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src } void -fs_visitor::emit_gs_control_data_bits(const fs_reg &vertex_count) +elk_fs_visitor::emit_gs_control_data_bits(const elk_fs_reg &vertex_count) { assert(stage == MESA_SHADER_GEOMETRY); assert(gs_compile->control_data_bits_per_vertex != 0); - struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); + struct elk_gs_prog_data *gs_prog_data = elk_gs_prog_data(prog_data); const fs_builder bld = fs_builder(this).at_end(); const fs_builder abld = bld.annotate("emit control data bits"); @@ -2293,7 +2293,7 @@ fs_visitor::emit_gs_control_data_bits(const fs_reg &vertex_count) * Similarly, if the control data header is <= 32 bits, there is only one * DWord, so we can skip channel masks. */ - fs_reg channel_mask, per_slot_offset; + elk_fs_reg channel_mask, per_slot_offset; if (gs_compile->control_data_header_size_bits > 32) channel_mask = vgrf(glsl_uint_type()); @@ -2311,46 +2311,46 @@ fs_visitor::emit_gs_control_data_bits(const fs_reg &vertex_count) * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex)) */ if (channel_mask.file != BAD_FILE || per_slot_offset.file != BAD_FILE) { - fs_reg dword_index = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - fs_reg prev_count = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - abld.ADD(prev_count, vertex_count, brw_imm_ud(0xffffffffu)); + elk_fs_reg dword_index = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + elk_fs_reg prev_count = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + abld.ADD(prev_count, vertex_count, elk_imm_ud(0xffffffffu)); unsigned log2_bits_per_vertex = util_last_bit(gs_compile->control_data_bits_per_vertex); - abld.SHR(dword_index, prev_count, brw_imm_ud(6u - log2_bits_per_vertex)); + abld.SHR(dword_index, prev_count, elk_imm_ud(6u - log2_bits_per_vertex)); if (per_slot_offset.file != BAD_FILE) { /* Set the per-slot offset to dword_index / 4, so that we'll write to * the appropriate OWord within the control data header. */ - abld.SHR(per_slot_offset, dword_index, brw_imm_ud(2u)); + abld.SHR(per_slot_offset, dword_index, elk_imm_ud(2u)); } /* Set the channel masks to 1 << (dword_index % 4), so that we'll * write to the appropriate DWORD within the OWORD. */ - fs_reg channel = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - fwa_bld.AND(channel, dword_index, brw_imm_ud(3u)); + elk_fs_reg channel = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + fwa_bld.AND(channel, dword_index, elk_imm_ud(3u)); channel_mask = intexp2(fwa_bld, channel); /* Then the channel masks need to be in bits 23:16. */ - fwa_bld.SHL(channel_mask, channel_mask, brw_imm_ud(16u)); + fwa_bld.SHL(channel_mask, channel_mask, elk_imm_ud(16u)); } /* If there are channel masks, add 3 extra copies of the data. */ const unsigned length = 1 + 3 * unsigned(channel_mask.file != BAD_FILE); - fs_reg sources[4]; + elk_fs_reg sources[4]; for (unsigned i = 0; i < ARRAY_SIZE(sources); i++) sources[i] = this->control_data_bits; - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = gs_payload().urb_handles; srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = per_slot_offset; srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = channel_mask; - srcs[URB_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_F, length); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); + srcs[URB_LOGICAL_SRC_DATA] = bld.vgrf(ELK_REGISTER_TYPE_F, length); + srcs[URB_LOGICAL_SRC_COMPONENTS] = elk_imm_ud(length); abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0); - fs_inst *inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + elk_fs_inst *inst = abld.emit(ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); /* We need to increment Global Offset by 256-bits to make room for @@ -2363,10 +2363,10 @@ fs_visitor::emit_gs_control_data_bits(const fs_reg &vertex_count) } static void -set_gs_stream_control_data_bits(nir_to_brw_state &ntb, const fs_reg &vertex_count, +set_gs_stream_control_data_bits(nir_to_elk_state &ntb, const elk_fs_reg &vertex_count, unsigned stream_id) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */ @@ -2389,35 +2389,35 @@ set_gs_stream_control_data_bits(nir_to_brw_state &ntb, const fs_reg &vertex_coun const fs_builder abld = ntb.bld.annotate("set stream control data bits", NULL); /* reg::sid = stream_id */ - fs_reg sid = ntb.bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - abld.MOV(sid, brw_imm_ud(stream_id)); + elk_fs_reg sid = ntb.bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + abld.MOV(sid, elk_imm_ud(stream_id)); /* reg:shift_count = 2 * (vertex_count - 1) */ - fs_reg shift_count = ntb.bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - abld.SHL(shift_count, vertex_count, brw_imm_ud(1u)); + elk_fs_reg shift_count = ntb.bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + abld.SHL(shift_count, vertex_count, elk_imm_ud(1u)); /* Note: we're relying on the fact that the GEN SHL instruction only pays * attention to the lower 5 bits of its second source argument, so on this * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to * stream_id << ((2 * (vertex_count - 1)) % 32). */ - fs_reg mask = ntb.bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + elk_fs_reg mask = ntb.bld.vgrf(ELK_REGISTER_TYPE_UD, 1); abld.SHL(mask, sid, shift_count); abld.OR(s.control_data_bits, s.control_data_bits, mask); } static void -emit_gs_vertex(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src, +emit_gs_vertex(nir_to_elk_state &ntb, const nir_src &vertex_count_nir_src, unsigned stream_id) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_GEOMETRY); - struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(s.prog_data); + struct elk_gs_prog_data *gs_prog_data = elk_gs_prog_data(s.prog_data); - fs_reg vertex_count = get_nir_src(ntb, vertex_count_nir_src); - vertex_count.type = BRW_REGISTER_TYPE_UD; + elk_fs_reg vertex_count = get_nir_src(ntb, vertex_count_nir_src); + vertex_count.type = ELK_REGISTER_TYPE_UD; /* Haswell and later hardware ignores the "Render Stream Select" bits * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled, @@ -2464,20 +2464,20 @@ emit_gs_vertex(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src, * TODO: If vertex_count is an immediate, we could do some of this math * at compile time... */ - fs_inst *inst = + elk_fs_inst *inst = abld.AND(ntb.bld.null_reg_d(), vertex_count, - brw_imm_ud(32u / s.gs_compile->control_data_bits_per_vertex - 1u)); - inst->conditional_mod = BRW_CONDITIONAL_Z; + elk_imm_ud(32u / s.gs_compile->control_data_bits_per_vertex - 1u)); + inst->conditional_mod = ELK_CONDITIONAL_Z; - abld.IF(BRW_PREDICATE_NORMAL); + abld.IF(ELK_PREDICATE_NORMAL); /* If vertex_count is 0, then no control data bits have been * accumulated yet, so we can skip emitting them. */ - abld.CMP(ntb.bld.null_reg_d(), vertex_count, brw_imm_ud(0u), - BRW_CONDITIONAL_NEQ); - abld.IF(BRW_PREDICATE_NORMAL); + abld.CMP(ntb.bld.null_reg_d(), vertex_count, elk_imm_ud(0u), + ELK_CONDITIONAL_NEQ); + abld.IF(ELK_PREDICATE_NORMAL); s.emit_gs_control_data_bits(vertex_count); - abld.emit(BRW_OPCODE_ENDIF); + abld.emit(ELK_OPCODE_ENDIF); /* Reset control_data_bits to 0 so we can start accumulating a new * batch. @@ -2486,9 +2486,9 @@ emit_gs_vertex(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src, * effect of any call to EndPrimitive() that the shader may have * made before outputting its first vertex. */ - inst = abld.MOV(s.control_data_bits, brw_imm_ud(0u)); + inst = abld.MOV(s.control_data_bits, elk_imm_ud(0u)); inst->force_writemask_all = true; - abld.emit(BRW_OPCODE_ENDIF); + abld.emit(ELK_OPCODE_ENDIF); } s.emit_urb_writes(vertex_count); @@ -2505,7 +2505,7 @@ emit_gs_vertex(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src, } static void -emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, +emit_gs_input_load(nir_to_elk_state &ntb, const elk_fs_reg &dst, const nir_src &vertex_src, unsigned base_offset, const nir_src &offset_src, @@ -2514,10 +2514,10 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(type_sz(dst.type) == 4); - struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(s.prog_data); + struct elk_gs_prog_data *gs_prog_data = elk_gs_prog_data(s.prog_data); const unsigned push_reg_count = gs_prog_data->base.urb_read_length * 8; /* TODO: figure out push input layout for invocations == 1 */ @@ -2526,7 +2526,7 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, 4 * (base_offset + nir_src_as_uint(offset_src)) < push_reg_count) { int imm_offset = (base_offset + nir_src_as_uint(offset_src)) * 4 + nir_src_as_uint(vertex_src) * push_reg_count; - const fs_reg attr = fs_reg(ATTR, 0, dst.type); + const elk_fs_reg attr = elk_fs_reg(ATTR, 0, dst.type); for (unsigned i = 0; i < num_components; i++) { ntb.bld.MOV(offset(dst, bld, i), offset(attr, bld, imm_offset + i + first_component)); @@ -2537,8 +2537,8 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, /* Resort to the pull model. Ensure the VUE handles are provided. */ assert(gs_prog_data->base.include_vue_handles); - fs_reg start = s.gs_payload().icp_handle_start; - fs_reg icp_handle = ntb.bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + elk_fs_reg start = s.gs_payload().icp_handle_start; + elk_fs_reg icp_handle = ntb.bld.vgrf(ELK_REGISTER_TYPE_UD, 1); if (gs_prog_data->invocations == 1) { if (nir_src_is_const(vertex_src)) { @@ -2556,27 +2556,27 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, * by 32 (shifting by 5), and add the two together. This is * the final indirect byte offset. */ - fs_reg sequence = + elk_fs_reg sequence = ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]; - fs_reg channel_offsets = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - fs_reg vertex_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + elk_fs_reg channel_offsets = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + elk_fs_reg vertex_offset_bytes = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + elk_fs_reg icp_offset_bytes = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */ - bld.SHL(channel_offsets, sequence, brw_imm_ud(2u)); + bld.SHL(channel_offsets, sequence, elk_imm_ud(2u)); /* Convert vertex_index to bytes (multiply by 32) */ bld.SHL(vertex_offset_bytes, - retype(get_nir_src(ntb, vertex_src), BRW_REGISTER_TYPE_UD), - brw_imm_ud(5u)); + retype(get_nir_src(ntb, vertex_src), ELK_REGISTER_TYPE_UD), + elk_imm_ud(5u)); bld.ADD(icp_offset_bytes, vertex_offset_bytes, channel_offsets); /* Use first_icp_handle as the base offset. There is one register * of URB handles per vertex, so inform the register allocator that * we might read up to nir->info.gs.vertices_in registers. */ - bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, start, - fs_reg(icp_offset_bytes), - brw_imm_ud(s.nir->info.gs.vertices_in * REG_SIZE)); + bld.emit(ELK_SHADER_OPCODE_MOV_INDIRECT, icp_handle, start, + elk_fs_reg(icp_offset_bytes), + elk_imm_ud(s.nir->info.gs.vertices_in * REG_SIZE)); } } else { assert(gs_prog_data->invocations > 1); @@ -2590,36 +2590,36 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, * addressing to fetch the proper URB handle. * */ - fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + elk_fs_reg icp_offset_bytes = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); /* Convert vertex_index to bytes (multiply by 4) */ bld.SHL(icp_offset_bytes, - retype(get_nir_src(ntb, vertex_src), BRW_REGISTER_TYPE_UD), - brw_imm_ud(2u)); + retype(get_nir_src(ntb, vertex_src), ELK_REGISTER_TYPE_UD), + elk_imm_ud(2u)); /* Use first_icp_handle as the base offset. There is one DWord * of URB handles per vertex, so inform the register allocator that * we might read up to ceil(nir->info.gs.vertices_in / 8) registers. */ - bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, start, - fs_reg(icp_offset_bytes), - brw_imm_ud(DIV_ROUND_UP(s.nir->info.gs.vertices_in, 8) * + bld.emit(ELK_SHADER_OPCODE_MOV_INDIRECT, icp_handle, start, + elk_fs_reg(icp_offset_bytes), + elk_imm_ud(DIV_ROUND_UP(s.nir->info.gs.vertices_in, 8) * REG_SIZE)); } } - fs_inst *inst; - fs_reg indirect_offset = get_nir_src(ntb, offset_src); + elk_fs_inst *inst; + elk_fs_reg indirect_offset = get_nir_src(ntb, offset_src); if (nir_src_is_const(offset_src)) { - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = icp_handle; /* Constant indexing - use global offset. */ if (first_component != 0) { unsigned read_components = num_components + first_component; - fs_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, + elk_fs_reg tmp = bld.vgrf(dst.type, read_components); + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); inst->size_written = read_components * tmp.component_size(inst->exec_size); @@ -2628,7 +2628,7 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, offset(tmp, bld, i + first_component)); } } else { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, ARRAY_SIZE(srcs)); inst->size_written = num_components * dst.component_size(inst->exec_size); @@ -2637,14 +2637,14 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, } else { /* Indirect indexing - use per-slot offsets as well. */ unsigned read_components = num_components + first_component; - fs_reg tmp = bld.vgrf(dst.type, read_components); + elk_fs_reg tmp = bld.vgrf(dst.type, read_components); - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = icp_handle; srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; if (first_component != 0) { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, tmp, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); inst->size_written = read_components * tmp.component_size(inst->exec_size); @@ -2653,7 +2653,7 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, offset(tmp, bld, i + first_component)); } } else { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dst, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, ARRAY_SIZE(srcs)); inst->size_written = num_components * dst.component_size(inst->exec_size); @@ -2662,32 +2662,32 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, } } -static fs_reg -get_indirect_offset(nir_to_brw_state &ntb, nir_intrinsic_instr *instr) +static elk_fs_reg +get_indirect_offset(nir_to_elk_state &ntb, nir_intrinsic_instr *instr) { nir_src *offset_src = nir_get_io_offset_src(instr); if (nir_src_is_const(*offset_src)) { - /* The only constant offset we should find is 0. brw_nir.c's + /* The only constant offset we should find is 0. elk_nir.c's * add_const_offset_to_base() will fold other constant offsets * into the "base" index. */ assert(nir_src_as_uint(*offset_src) == 0); - return fs_reg(); + return elk_fs_reg(); } return get_nir_src(ntb, *offset_src); } static void -fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb, +fs_nir_emit_vs_intrinsic(nir_to_elk_state &ntb, nir_intrinsic_instr *instr) { const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_VERTEX); - fs_reg dest; + elk_fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); @@ -2698,7 +2698,7 @@ fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_input: { assert(instr->def.bit_size == 32); - const fs_reg src = offset(fs_reg(ATTR, 0, dest.type), bld, + const elk_fs_reg src = offset(elk_fs_reg(ATTR, 0, dest.type), bld, nir_intrinsic_base(instr) * 4 + nir_intrinsic_component(instr) + nir_src_as_uint(instr->src[0])); @@ -2714,7 +2714,7 @@ fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_draw_id: case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_is_indexed_draw: - unreachable("lowered by brw_nir_lower_vs_inputs"); + unreachable("lowered by elk_nir_lower_vs_inputs"); default: fs_nir_emit_intrinsic(ntb, bld, instr); @@ -2722,23 +2722,23 @@ fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb, } } -static fs_reg -get_tcs_single_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, +static elk_fs_reg +get_tcs_single_patch_icp_handle(nir_to_elk_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; - struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(s.prog_data); + struct elk_tcs_prog_data *tcs_prog_data = elk_tcs_prog_data(s.prog_data); const nir_src &vertex_src = instr->src[0]; nir_intrinsic_instr *vertex_intrin = nir_src_as_intrinsic(vertex_src); - const fs_reg start = s.tcs_payload().icp_handle_start; + const elk_fs_reg start = s.tcs_payload().icp_handle_start; - fs_reg icp_handle; + elk_fs_reg icp_handle; if (nir_src_is_const(vertex_src)) { /* Emit a MOV to resolve <0,1,0> regioning. */ - icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + icp_handle = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); unsigned vertex = nir_src_as_uint(vertex_src); bld.MOV(icp_handle, component(start, vertex)); } else if (tcs_prog_data->instances == 1 && vertex_intrin && @@ -2752,35 +2752,35 @@ get_tcs_single_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, /* The vertex index is non-constant. We need to use indirect * addressing to fetch the proper URB handle. */ - icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + icp_handle = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); /* Each ICP handle is a single DWord (4 bytes) */ - fs_reg vertex_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + elk_fs_reg vertex_offset_bytes = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); bld.SHL(vertex_offset_bytes, - retype(get_nir_src(ntb, vertex_src), BRW_REGISTER_TYPE_UD), - brw_imm_ud(2u)); + retype(get_nir_src(ntb, vertex_src), ELK_REGISTER_TYPE_UD), + elk_imm_ud(2u)); /* We might read up to 4 registers. */ - bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, + bld.emit(ELK_SHADER_OPCODE_MOV_INDIRECT, icp_handle, start, vertex_offset_bytes, - brw_imm_ud(4 * REG_SIZE)); + elk_imm_ud(4 * REG_SIZE)); } return icp_handle; } -static fs_reg -get_tcs_multi_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, +static elk_fs_reg +get_tcs_multi_patch_icp_handle(nir_to_elk_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; const intel_device_info *devinfo = s.devinfo; - struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) s.key; + struct elk_tcs_prog_key *tcs_key = (struct elk_tcs_prog_key *) s.key; const nir_src &vertex_src = instr->src[0]; const unsigned grf_size_bytes = REG_SIZE * reg_unit(devinfo); - const fs_reg start = s.tcs_payload().icp_handle_start; + const elk_fs_reg start = s.tcs_payload().icp_handle_start; if (nir_src_is_const(vertex_src)) return byte_offset(start, nir_src_as_uint(vertex_src) * grf_size_bytes); @@ -2796,28 +2796,28 @@ get_tcs_multi_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, * by the GRF size (by shifting), and add the two together. This is * the final indirect byte offset. */ - fs_reg icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - fs_reg sequence = ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]; - fs_reg channel_offsets = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - fs_reg vertex_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + elk_fs_reg icp_handle = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + elk_fs_reg sequence = ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]; + elk_fs_reg channel_offsets = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + elk_fs_reg vertex_offset_bytes = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + elk_fs_reg icp_offset_bytes = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); /* Offsets will be 0, 4, 8, ... */ - bld.SHL(channel_offsets, sequence, brw_imm_ud(2u)); + bld.SHL(channel_offsets, sequence, elk_imm_ud(2u)); /* Convert vertex_index to bytes (multiply by 32) */ assert(util_is_power_of_two_nonzero(grf_size_bytes)); /* for ffs() */ bld.SHL(vertex_offset_bytes, - retype(get_nir_src(ntb, vertex_src), BRW_REGISTER_TYPE_UD), - brw_imm_ud(ffs(grf_size_bytes) - 1)); + retype(get_nir_src(ntb, vertex_src), ELK_REGISTER_TYPE_UD), + elk_imm_ud(ffs(grf_size_bytes) - 1)); bld.ADD(icp_offset_bytes, vertex_offset_bytes, channel_offsets); /* Use start of ICP handles as the base offset. There is one register * of URB handles per vertex, so inform the register allocator that * we might read up to nir->info.gs.vertices_in registers. */ - bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, start, + bld.emit(ELK_SHADER_OPCODE_MOV_INDIRECT, icp_handle, start, icp_offset_bytes, - brw_imm_ud(brw_tcs_prog_key_input_vertices(tcs_key) * + elk_imm_ud(elk_tcs_prog_key_input_vertices(tcs_key) * grf_size_bytes)); return icp_handle; @@ -2825,32 +2825,32 @@ get_tcs_multi_patch_icp_handle(nir_to_brw_state &ntb, const fs_builder &bld, static void setup_barrier_message_payload_gfx125(const fs_builder &bld, - const fs_reg &msg_payload) + const elk_fs_reg &msg_payload) { assert(bld.shader->devinfo->verx10 >= 125); /* From BSpec: 54006, mov r0.2[31:24] into m0.2[31:24] and m0.2[23:16] */ - fs_reg m0_10ub = component(retype(msg_payload, BRW_REGISTER_TYPE_UB), 10); - fs_reg r0_11ub = - stride(suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UB), 11), + elk_fs_reg m0_10ub = component(retype(msg_payload, ELK_REGISTER_TYPE_UB), 10); + elk_fs_reg r0_11ub = + stride(suboffset(retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_UB), 11), 0, 1, 0); bld.exec_all().group(2, 0).MOV(m0_10ub, r0_11ub); } static void -emit_barrier(nir_to_brw_state &ntb) +emit_barrier(nir_to_elk_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; /* We are getting the barrier ID from the compute shader header */ assert(gl_shader_stage_uses_workgroup(s.stage)); - fs_reg payload = fs_reg(VGRF, s.alloc.allocate(1), BRW_REGISTER_TYPE_UD); + elk_fs_reg payload = elk_fs_reg(VGRF, s.alloc.allocate(1), ELK_REGISTER_TYPE_UD); /* Clear the message payload */ - bld.exec_all().group(8, 0).MOV(payload, brw_imm_ud(0u)); + bld.exec_all().group(8, 0).MOV(payload, elk_imm_ud(0u)); if (devinfo->verx10 >= 125) { setup_barrier_message_payload_gfx125(bld, payload); @@ -2872,73 +2872,73 @@ emit_barrier(nir_to_brw_state &ntb) } /* Copy the barrier id from r0.2 to the message payload reg.2 */ - fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)); + elk_fs_reg r0_2 = elk_fs_reg(retype(elk_vec1_grf(0, 2), ELK_REGISTER_TYPE_UD)); bld.exec_all().group(1, 0).AND(component(payload, 2), r0_2, - brw_imm_ud(barrier_id_mask)); + elk_imm_ud(barrier_id_mask)); } /* Emit a gateway "barrier" message using the payload we set up, followed * by a wait instruction. */ - bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload); + bld.exec_all().emit(ELK_SHADER_OPCODE_BARRIER, reg_undef, payload); } static void -emit_tcs_barrier(nir_to_brw_state &ntb) +emit_tcs_barrier(nir_to_elk_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_TESS_CTRL); - struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(s.prog_data); + struct elk_tcs_prog_data *tcs_prog_data = elk_tcs_prog_data(s.prog_data); - fs_reg m0 = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - fs_reg m0_2 = component(m0, 2); + elk_fs_reg m0 = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + elk_fs_reg m0_2 = component(m0, 2); const fs_builder chanbld = bld.exec_all().group(1, 0); /* Zero the message header */ - bld.exec_all().MOV(m0, brw_imm_ud(0u)); + bld.exec_all().MOV(m0, elk_imm_ud(0u)); if (devinfo->verx10 >= 125) { setup_barrier_message_payload_gfx125(bld, m0); } else if (devinfo->ver >= 11) { - chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(30, 24))); + chanbld.AND(m0_2, retype(elk_vec1_grf(0, 2), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(30, 24))); /* Set the Barrier Count and the enable bit */ chanbld.OR(m0_2, m0_2, - brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15))); + elk_imm_ud(tcs_prog_data->instances << 8 | (1 << 15))); } else { /* Copy "Barrier ID" from r0.2, bits 16:13 */ - chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(16, 13))); + chanbld.AND(m0_2, retype(elk_vec1_grf(0, 2), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(16, 13))); /* Shift it up to bits 27:24. */ - chanbld.SHL(m0_2, m0_2, brw_imm_ud(11)); + chanbld.SHL(m0_2, m0_2, elk_imm_ud(11)); /* Set the Barrier Count and the enable bit */ chanbld.OR(m0_2, m0_2, - brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15))); + elk_imm_ud(tcs_prog_data->instances << 9 | (1 << 15))); } - bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0); + bld.emit(ELK_SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0); } static void -fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, +fs_nir_emit_tcs_intrinsic(nir_to_elk_state &ntb, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_TESS_CTRL); - struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(s.prog_data); - struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base; + struct elk_tcs_prog_data *tcs_prog_data = elk_tcs_prog_data(s.prog_data); + struct elk_vue_prog_data *vue_prog_data = &tcs_prog_data->base; - fs_reg dst; + elk_fs_reg dst; if (nir_intrinsic_infos[instr->intrinsic].has_dest) dst = get_nir_def(ntb, instr->def); @@ -2965,14 +2965,14 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_per_vertex_input: { assert(instr->def.bit_size == 32); - fs_reg indirect_offset = get_indirect_offset(ntb, instr); + elk_fs_reg indirect_offset = get_indirect_offset(ntb, instr); unsigned imm_offset = nir_intrinsic_base(instr); - fs_inst *inst; + elk_fs_inst *inst; const bool multi_patch = vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH; - fs_reg icp_handle = multi_patch ? + elk_fs_reg icp_handle = multi_patch ? get_tcs_multi_patch_icp_handle(ntb, bld, instr) : get_tcs_single_patch_icp_handle(ntb, bld, instr); @@ -2983,22 +2983,22 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, unsigned num_components = instr->num_components; unsigned first_component = nir_intrinsic_component(instr); - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = icp_handle; if (indirect_offset.file == BAD_FILE) { /* Constant indexing - use global offset. */ if (first_component != 0) { unsigned read_components = num_components + first_component; - fs_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, + elk_fs_reg tmp = bld.vgrf(dst.type, read_components); + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); for (unsigned i = 0; i < num_components; i++) { bld.MOV(offset(dst, bld, i), offset(tmp, bld, i + first_component)); } } else { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, ARRAY_SIZE(srcs)); } inst->offset = imm_offset; @@ -3008,15 +3008,15 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, if (first_component != 0) { unsigned read_components = num_components + first_component; - fs_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, tmp, + elk_fs_reg tmp = bld.vgrf(dst.type, read_components); + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); for (unsigned i = 0; i < num_components; i++) { bld.MOV(offset(dst, bld, i), offset(tmp, bld, i + first_component)); } } else { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dst, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, ARRAY_SIZE(srcs)); } inst->offset = imm_offset; @@ -3040,27 +3040,27 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_output: case nir_intrinsic_load_per_vertex_output: { assert(instr->def.bit_size == 32); - fs_reg indirect_offset = get_indirect_offset(ntb, instr); + elk_fs_reg indirect_offset = get_indirect_offset(ntb, instr); unsigned imm_offset = nir_intrinsic_base(instr); unsigned first_component = nir_intrinsic_component(instr); - fs_inst *inst; + elk_fs_inst *inst; if (indirect_offset.file == BAD_FILE) { /* This MOV replicates the output handle to all enabled channels * is SINGLE_PATCH mode. */ - fs_reg patch_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); + elk_fs_reg patch_handle = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); bld.MOV(patch_handle, s.tcs_payload().patch_urb_output); { - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = patch_handle; if (first_component != 0) { unsigned read_components = instr->num_components + first_component; - fs_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, tmp, + elk_fs_reg tmp = bld.vgrf(dst.type, read_components); + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); inst->size_written = read_components * REG_SIZE * reg_unit(devinfo); for (unsigned i = 0; i < instr->num_components; i++) { @@ -3068,7 +3068,7 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, offset(tmp, bld, i + first_component)); } } else { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dst, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, ARRAY_SIZE(srcs)); inst->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); } @@ -3076,15 +3076,15 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, } } else { /* Indirect indexing - use per-slot offsets as well. */ - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = s.tcs_payload().patch_urb_output; srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; if (first_component != 0) { unsigned read_components = instr->num_components + first_component; - fs_reg tmp = bld.vgrf(dst.type, read_components); - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, tmp, + elk_fs_reg tmp = bld.vgrf(dst.type, read_components); + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); inst->size_written = read_components * REG_SIZE * reg_unit(devinfo); for (unsigned i = 0; i < instr->num_components; i++) { @@ -3092,7 +3092,7 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, offset(tmp, bld, i + first_component)); } } else { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dst, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, dst, srcs, ARRAY_SIZE(srcs)); inst->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); } @@ -3104,8 +3104,8 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_store_output: case nir_intrinsic_store_per_vertex_output: { assert(nir_src_bit_size(instr->src[0]) == 32); - fs_reg value = get_nir_src(ntb, instr->src[0]); - fs_reg indirect_offset = get_indirect_offset(ntb, instr); + elk_fs_reg value = get_nir_src(ntb, instr->src[0]); + elk_fs_reg indirect_offset = get_indirect_offset(ntb, instr); unsigned imm_offset = nir_intrinsic_base(instr); unsigned mask = nir_intrinsic_write_mask(instr); @@ -3120,11 +3120,11 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, const bool has_urb_lsc = devinfo->ver >= 20; - fs_reg mask_reg; + elk_fs_reg mask_reg; if (mask != WRITEMASK_XYZW) - mask_reg = brw_imm_ud(mask << 16); + mask_reg = elk_imm_ud(mask << 16); - fs_reg sources[4]; + elk_fs_reg sources[4]; unsigned m = has_urb_lsc ? 0 : first_component; for (unsigned i = 0; i < num_components; i++) { @@ -3138,15 +3138,15 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, assert(has_urb_lsc || m == (first_component + num_components)); - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = s.tcs_payload().patch_urb_output; srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = mask_reg; - srcs[URB_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_F, m); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(m); + srcs[URB_LOGICAL_SRC_DATA] = bld.vgrf(ELK_REGISTER_TYPE_F, m); + srcs[URB_LOGICAL_SRC_COMPONENTS] = elk_imm_ud(m); bld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, m, 0); - fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + elk_fs_inst *inst = bld.emit(ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->offset = imm_offset; break; @@ -3159,17 +3159,17 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, } static void -fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, +fs_nir_emit_tes_intrinsic(nir_to_elk_state &ntb, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_TESS_EVAL); - struct brw_tes_prog_data *tes_prog_data = brw_tes_prog_data(s.prog_data); + struct elk_tes_prog_data *tes_prog_data = elk_tes_prog_data(s.prog_data); - fs_reg dest; + elk_fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); @@ -3186,18 +3186,18 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_input: case nir_intrinsic_load_per_vertex_input: { assert(instr->def.bit_size == 32); - fs_reg indirect_offset = get_indirect_offset(ntb, instr); + elk_fs_reg indirect_offset = get_indirect_offset(ntb, instr); unsigned imm_offset = nir_intrinsic_base(instr); unsigned first_component = nir_intrinsic_component(instr); - fs_inst *inst; + elk_fs_inst *inst; if (indirect_offset.file == BAD_FILE) { /* Arbitrarily only push up to 32 vec4 slots worth of data, * which is 16 registers (since each holds 2 vec4 slots). */ const unsigned max_push_slots = 32; if (imm_offset < max_push_slots) { - const fs_reg src = horiz_offset(fs_reg(ATTR, 0, dest.type), + const elk_fs_reg src = horiz_offset(elk_fs_reg(ATTR, 0, dest.type), 4 * imm_offset + first_component); for (int i = 0; i < instr->num_components; i++) bld.MOV(offset(dest, bld, i), component(src, i)); @@ -3207,14 +3207,14 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, (imm_offset / 2) + 1); } else { /* Replicate the patch handle to all enabled channels */ - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = s.tes_payload().patch_urb_input; if (first_component != 0) { unsigned read_components = instr->num_components + first_component; - fs_reg tmp = bld.vgrf(dest.type, read_components); - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, tmp, + elk_fs_reg tmp = bld.vgrf(dest.type, read_components); + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); inst->size_written = read_components * REG_SIZE * reg_unit(devinfo); for (unsigned i = 0; i < instr->num_components; i++) { @@ -3222,7 +3222,7 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, offset(tmp, bld, i + first_component)); } } else { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dest, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, dest, srcs, ARRAY_SIZE(srcs)); inst->size_written = instr->num_components * REG_SIZE * reg_unit(devinfo); } @@ -3237,22 +3237,22 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, */ unsigned num_components = instr->num_components; - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = s.tes_payload().patch_urb_input; srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; if (first_component != 0) { unsigned read_components = num_components + first_component; - fs_reg tmp = bld.vgrf(dest.type, read_components); - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, tmp, + elk_fs_reg tmp = bld.vgrf(dest.type, read_components); + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); for (unsigned i = 0; i < num_components; i++) { bld.MOV(offset(dest, bld, i), offset(tmp, bld, i + first_component)); } } else { - inst = bld.emit(SHADER_OPCODE_URB_READ_LOGICAL, dest, + inst = bld.emit(ELK_SHADER_OPCODE_URB_READ_LOGICAL, dest, srcs, ARRAY_SIZE(srcs)); } inst->offset = imm_offset; @@ -3268,24 +3268,24 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, } static void -fs_nir_emit_gs_intrinsic(nir_to_brw_state &ntb, +fs_nir_emit_gs_intrinsic(nir_to_elk_state &ntb, nir_intrinsic_instr *instr) { const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_GEOMETRY); - fs_reg indirect_offset; + elk_fs_reg indirect_offset; - fs_reg dest; + elk_fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); switch (instr->intrinsic) { case nir_intrinsic_load_primitive_id: assert(s.stage == MESA_SHADER_GEOMETRY); - assert(brw_gs_prog_data(s.prog_data)->include_primitive_id); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), s.gs_payload().primitive_id); + assert(elk_gs_prog_data(s.prog_data)->include_primitive_id); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_UD), s.gs_payload().primitive_id); break; case nir_intrinsic_load_input: @@ -3310,7 +3310,7 @@ fs_nir_emit_gs_intrinsic(nir_to_brw_state &ntb, break; case nir_intrinsic_load_invocation_id: { - fs_reg val = ntb.system_values[SYSTEM_VALUE_INVOCATION_ID]; + elk_fs_reg val = ntb.system_values[SYSTEM_VALUE_INVOCATION_ID]; assert(val.file != BAD_FILE); dest.type = val.type; bld.MOV(dest, val); @@ -3326,10 +3326,10 @@ fs_nir_emit_gs_intrinsic(nir_to_brw_state &ntb, /** * Fetch the current render target layer index. */ -static fs_reg +static elk_fs_reg fetch_render_target_array_index(const fs_builder &bld) { - const fs_visitor *v = static_cast(bld.shader); + const elk_fs_visitor *v = static_cast(bld.shader); if (bld.shader->devinfo->ver >= 20) { /* Gfx20+ has separate Render Target Array indices for each pair @@ -3337,14 +3337,14 @@ fetch_render_target_array_index(const fs_builder &bld) * to use a <1;8,0> region in order to select the correct word * for each channel. */ - const fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_UD); + const elk_fs_reg idx = bld.vgrf(ELK_REGISTER_TYPE_UD); for (unsigned i = 0; i < DIV_ROUND_UP(bld.dispatch_width(), 16); i++) { const fs_builder hbld = bld.group(16, i); - const struct brw_reg reg = retype(brw_vec1_grf(2 * i + 1, 1), - BRW_REGISTER_TYPE_UW); + const struct elk_reg reg = retype(elk_vec1_grf(2 * i + 1, 1), + ELK_REGISTER_TYPE_UW); hbld.AND(offset(idx, hbld, i), stride(reg, 1, 8, 0), - brw_imm_uw(0x7ff)); + elk_imm_uw(0x7ff)); } return idx; @@ -3356,12 +3356,12 @@ fetch_render_target_array_index(const fs_builder &bld) * dispatch mode. */ assert(bld.dispatch_width() == 16); - const fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_UD); + const elk_fs_reg idx = bld.vgrf(ELK_REGISTER_TYPE_UD); for (unsigned i = 0; i < v->max_polygons; i++) { const fs_builder hbld = bld.group(8, i); - const struct brw_reg g1 = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3 + 10 * i); - hbld.AND(offset(idx, hbld, i), g1, brw_imm_uw(0x7ff)); + const struct elk_reg g1 = elk_uw1_reg(ELK_GENERAL_REGISTER_FILE, 1, 3 + 10 * i); + hbld.AND(offset(idx, hbld, i), g1, elk_imm_uw(0x7ff)); } return idx; @@ -3369,46 +3369,46 @@ fetch_render_target_array_index(const fs_builder &bld) /* The render target array index is provided in the thread payload as * bits 26:16 of r1.1. */ - const fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3), - brw_imm_uw(0x7ff)); + const elk_fs_reg idx = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.AND(idx, elk_uw1_reg(ELK_GENERAL_REGISTER_FILE, 1, 3), + elk_imm_uw(0x7ff)); return idx; } else if (bld.shader->devinfo->ver >= 6) { /* The render target array index is provided in the thread payload as * bits 26:16 of r0.0. */ - const fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 0, 1), - brw_imm_uw(0x7ff)); + const elk_fs_reg idx = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.AND(idx, elk_uw1_reg(ELK_GENERAL_REGISTER_FILE, 0, 1), + elk_imm_uw(0x7ff)); return idx; } else { /* Pre-SNB we only ever render into the first layer of the framebuffer * since layered rendering is not implemented. */ - return brw_imm_ud(0); + return elk_imm_ud(0); } } /* Sample from the MCS surface attached to this multisample texture. */ -static fs_reg -emit_mcs_fetch(nir_to_brw_state &ntb, const fs_reg &coordinate, unsigned components, - const fs_reg &texture, - const fs_reg &texture_handle) +static elk_fs_reg +emit_mcs_fetch(nir_to_elk_state &ntb, const elk_fs_reg &coordinate, unsigned components, + const elk_fs_reg &texture, + const elk_fs_reg &texture_handle) { const fs_builder &bld = ntb.bld; - const fs_reg dest = ntb.s.vgrf(glsl_uvec4_type()); + const elk_fs_reg dest = ntb.s.vgrf(glsl_uvec4_type()); - fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate; srcs[TEX_LOGICAL_SRC_SURFACE] = texture; - srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(0); + srcs[TEX_LOGICAL_SRC_SAMPLER] = elk_imm_ud(0); srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE] = texture_handle; - srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(components); - srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0); - srcs[TEX_LOGICAL_SRC_RESIDENCY] = brw_imm_d(0); + srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = elk_imm_d(components); + srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = elk_imm_d(0); + srcs[TEX_LOGICAL_SRC_RESIDENCY] = elk_imm_d(0); - fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs, + elk_fs_inst *inst = bld.emit(ELK_SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs, ARRAY_SIZE(srcs)); /* We only care about one or two regs of response, but the sampler always @@ -3423,20 +3423,20 @@ emit_mcs_fetch(nir_to_brw_state &ntb, const fs_reg &coordinate, unsigned compone * Fake non-coherent framebuffer read implemented using TXF to fetch from the * framebuffer at the current fragment coordinates and sample index. */ -static fs_inst * -emit_non_coherent_fb_read(nir_to_brw_state &ntb, const fs_builder &bld, const fs_reg &dst, +static elk_fs_inst * +emit_non_coherent_fb_read(nir_to_elk_state &ntb, const fs_builder &bld, const elk_fs_reg &dst, unsigned target) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; const struct intel_device_info *devinfo = s.devinfo; assert(bld.shader->stage == MESA_SHADER_FRAGMENT); - const brw_wm_prog_key *wm_key = - reinterpret_cast(s.key); + const elk_wm_prog_key *wm_key = + reinterpret_cast(s.key); assert(!wm_key->coherent_fb_fetch); /* Calculate the fragment coordinates. */ - const fs_reg coords = bld.vgrf(BRW_REGISTER_TYPE_UD, 3); + const elk_fs_reg coords = bld.vgrf(ELK_REGISTER_TYPE_UD, 3); bld.MOV(offset(coords, bld, 0), s.pixel_x); bld.MOV(offset(coords, bld, 1), s.pixel_y); bld.MOV(offset(coords, bld, 2), fetch_render_target_array_index(bld)); @@ -3446,22 +3446,22 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const fs_builder &bld, const fs * shouldn't be necessary to recompile based on whether the framebuffer is * CMS or UMS. */ - assert(wm_key->multisample_fbo == BRW_ALWAYS || - wm_key->multisample_fbo == BRW_NEVER); + assert(wm_key->multisample_fbo == ELK_ALWAYS || + wm_key->multisample_fbo == ELK_NEVER); if (wm_key->multisample_fbo && ntb.system_values[SYSTEM_VALUE_SAMPLE_ID].file == BAD_FILE) ntb.system_values[SYSTEM_VALUE_SAMPLE_ID] = emit_sampleid_setup(ntb); - const fs_reg sample = ntb.system_values[SYSTEM_VALUE_SAMPLE_ID]; - const fs_reg mcs = wm_key->multisample_fbo ? - emit_mcs_fetch(ntb, coords, 3, brw_imm_ud(target), fs_reg()) : fs_reg(); + const elk_fs_reg sample = ntb.system_values[SYSTEM_VALUE_SAMPLE_ID]; + const elk_fs_reg mcs = wm_key->multisample_fbo ? + emit_mcs_fetch(ntb, coords, 3, elk_imm_ud(target), elk_fs_reg()) : elk_fs_reg(); /* Use either a normal or a CMS texel fetch message depending on whether * the framebuffer is single or multisample. On SKL+ use the wide CMS * message just in case the framebuffer uses 16x multisampling, it should * be equivalent to the normal CMS fetch for lower multisampling modes. */ - opcode op; + elk_opcode op; if (wm_key->multisample_fbo) { /* On SKL+ use the wide CMS message just in case the framebuffer uses 16x * multisampling, it should be equivalent to the normal CMS fetch for @@ -3470,28 +3470,28 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const fs_builder &bld, const fs * On Gfx12HP, there is only CMS_W variant available. */ if (devinfo->verx10 >= 125) - op = SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL; + op = ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL; else if (devinfo->ver >= 9) - op = SHADER_OPCODE_TXF_CMS_W_LOGICAL; + op = ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL; else - op = SHADER_OPCODE_TXF_CMS_LOGICAL; + op = ELK_SHADER_OPCODE_TXF_CMS_LOGICAL; } else { - op = SHADER_OPCODE_TXF_LOGICAL; + op = ELK_SHADER_OPCODE_TXF_LOGICAL; } /* Emit the instruction. */ - fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; srcs[TEX_LOGICAL_SRC_COORDINATE] = coords; - srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0); + srcs[TEX_LOGICAL_SRC_LOD] = elk_imm_ud(0); srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = sample; srcs[TEX_LOGICAL_SRC_MCS] = mcs; - srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(target); - srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(0); - srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_ud(3); - srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_ud(0); - srcs[TEX_LOGICAL_SRC_RESIDENCY] = brw_imm_ud(0); + srcs[TEX_LOGICAL_SRC_SURFACE] = elk_imm_ud(target); + srcs[TEX_LOGICAL_SRC_SAMPLER] = elk_imm_ud(0); + srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = elk_imm_ud(3); + srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = elk_imm_ud(0); + srcs[TEX_LOGICAL_SRC_RESIDENCY] = elk_imm_ud(0); - fs_inst *inst = bld.emit(op, dst, srcs, ARRAY_SIZE(srcs)); + elk_fs_inst *inst = bld.emit(op, dst, srcs, ARRAY_SIZE(srcs)); inst->size_written = 4 * inst->dst.component_size(inst->exec_size); return inst; @@ -3501,25 +3501,25 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const fs_builder &bld, const fs * Actual coherent framebuffer read implemented using the native render target * read message. Requires SKL+. */ -static fs_inst * -emit_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, unsigned target) +static elk_fs_inst * +emit_coherent_fb_read(const fs_builder &bld, const elk_fs_reg &dst, unsigned target) { assert(bld.shader->devinfo->ver >= 9); - fs_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst); + elk_fs_inst *inst = bld.emit(ELK_FS_OPCODE_FB_READ_LOGICAL, dst); inst->target = target; inst->size_written = 4 * inst->dst.component_size(inst->exec_size); return inst; } -static fs_reg -alloc_temporary(const fs_builder &bld, unsigned size, fs_reg *regs, unsigned n) +static elk_fs_reg +alloc_temporary(const fs_builder &bld, unsigned size, elk_fs_reg *regs, unsigned n) { if (n && regs[0].file != BAD_FILE) { return regs[0]; } else { - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, size); + const elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_F, size); for (unsigned i = 0; i < n; i++) regs[i] = tmp; @@ -3528,16 +3528,16 @@ alloc_temporary(const fs_builder &bld, unsigned size, fs_reg *regs, unsigned n) } } -static fs_reg -alloc_frag_output(nir_to_brw_state &ntb, unsigned location) +static elk_fs_reg +alloc_frag_output(nir_to_elk_state &ntb, unsigned location) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); - const brw_wm_prog_key *const key = - reinterpret_cast(s.key); - const unsigned l = GET_FIELD(location, BRW_NIR_FRAG_OUTPUT_LOCATION); - const unsigned i = GET_FIELD(location, BRW_NIR_FRAG_OUTPUT_INDEX); + const elk_wm_prog_key *const key = + reinterpret_cast(s.key); + const unsigned l = GET_FIELD(location, ELK_NIR_FRAG_OUTPUT_LOCATION); + const unsigned i = GET_FIELD(location, ELK_NIR_FRAG_OUTPUT_INDEX); if (i > 0 || (key->force_dual_color_blend && l == FRAG_RESULT_DATA1)) return alloc_temporary(ntb.bld, 4, &s.dual_src_output, 1); @@ -3556,7 +3556,7 @@ alloc_frag_output(nir_to_brw_state &ntb, unsigned location) return alloc_temporary(ntb.bld, 1, &s.sample_mask, 1); else if (l >= FRAG_RESULT_DATA0 && - l < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS) + l < FRAG_RESULT_DATA0 + ELK_MAX_DRAW_BUFFERS) return alloc_temporary(ntb.bld, 4, &s.outputs[l - FRAG_RESULT_DATA0], 1); @@ -3565,7 +3565,7 @@ alloc_frag_output(nir_to_brw_state &ntb, unsigned location) } static void -emit_is_helper_invocation(nir_to_brw_state &ntb, fs_reg result) +emit_is_helper_invocation(nir_to_elk_state &ntb, elk_fs_reg result) { const fs_builder &bld = ntb.bld; @@ -3573,32 +3573,32 @@ emit_is_helper_invocation(nir_to_brw_state &ntb, fs_reg result) * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into * consideration demoted invocations. */ - result.type = BRW_REGISTER_TYPE_UD; + result.type = ELK_REGISTER_TYPE_UD; - bld.MOV(result, brw_imm_ud(0)); + bld.MOV(result, elk_imm_ud(0)); - /* See brw_sample_mask_reg() for why we split SIMD32 into SIMD16 here. */ + /* See elk_sample_mask_reg() for why we split SIMD32 into SIMD16 here. */ unsigned width = bld.dispatch_width(); for (unsigned i = 0; i < DIV_ROUND_UP(width, 16); i++) { const fs_builder b = bld.group(MIN2(width, 16), i); - fs_inst *mov = b.MOV(offset(result, b, i), brw_imm_ud(~0)); + elk_fs_inst *mov = b.MOV(offset(result, b, i), elk_imm_ud(~0)); /* The at() ensures that any code emitted to get the predicate happens * before the mov right above. This is not an issue elsewhere because * lowering code already set up the builder this way. */ - brw_emit_predicate_on_sample_mask(b.at(NULL, mov), mov); + elk_emit_predicate_on_sample_mask(b.at(NULL, mov), mov); mov->predicate_inverse = true; } } static void -emit_fragcoord_interpolation(nir_to_brw_state &ntb, fs_reg wpos) +emit_fragcoord_interpolation(nir_to_elk_state &ntb, elk_fs_reg wpos) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); @@ -3614,8 +3614,8 @@ emit_fragcoord_interpolation(nir_to_brw_state &ntb, fs_reg wpos) if (devinfo->ver >= 6) { bld.MOV(wpos, s.pixel_z); } else { - bld.emit(FS_OPCODE_LINTERP, wpos, - s.delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL], + bld.emit(ELK_FS_OPCODE_LINTERP, wpos, + s.delta_xy[ELK_BARYCENTRIC_PERSPECTIVE_PIXEL], s.interp_reg(bld, VARYING_SLOT_POS, 2, 0)); } wpos = offset(wpos, bld, 1); @@ -3624,14 +3624,14 @@ emit_fragcoord_interpolation(nir_to_brw_state &ntb, fs_reg wpos) bld.MOV(wpos, s.wpos_w); } -static fs_reg -emit_frontfacing_interpolation(nir_to_brw_state &ntb) +static elk_fs_reg +emit_frontfacing_interpolation(nir_to_elk_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; - fs_reg ff = bld.vgrf(BRW_REGISTER_TYPE_D); + elk_fs_reg ff = bld.vgrf(ELK_REGISTER_TYPE_D); if (devinfo->ver >= 20) { /* Gfx20+ has separate back-facing bits for each pair of @@ -3639,16 +3639,16 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) * use a <1;8,0> region in order to select the correct word for * each channel. */ - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UW); + const elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UW); for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { const fs_builder hbld = bld.group(16, i); - const struct brw_reg gi_uw = retype(xe2_vec1_grf(i, 9), - BRW_REGISTER_TYPE_UW); - hbld.AND(offset(tmp, hbld, i), gi_uw, brw_imm_uw(0x800)); + const struct elk_reg gi_uw = retype(xe2_vec1_grf(i, 9), + ELK_REGISTER_TYPE_UW); + hbld.AND(offset(tmp, hbld, i), gi_uw, elk_imm_uw(0x800)); } - bld.CMP(ff, tmp, brw_imm_uw(0), BRW_CONDITIONAL_Z); + bld.CMP(ff, tmp, elk_imm_uw(0), ELK_CONDITIONAL_Z); } else if (devinfo->ver >= 12 && s.max_polygons == 2) { /* According to the BSpec "PS Thread Payload for Normal @@ -3658,22 +3658,22 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) * dispatch mode. */ assert(s.dispatch_width == 16); - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_W); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_W); for (unsigned i = 0; i < s.max_polygons; i++) { const fs_builder hbld = bld.group(8, i); - const struct brw_reg g1 = retype(brw_vec1_grf(1, 1 + 5 * i), - BRW_REGISTER_TYPE_W); - hbld.ASR(offset(tmp, hbld, i), g1, brw_imm_d(15)); + const struct elk_reg g1 = retype(elk_vec1_grf(1, 1 + 5 * i), + ELK_REGISTER_TYPE_W); + hbld.ASR(offset(tmp, hbld, i), g1, elk_imm_d(15)); } bld.NOT(ff, tmp); } else if (devinfo->ver >= 12) { - fs_reg g1 = fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W)); + elk_fs_reg g1 = elk_fs_reg(retype(elk_vec1_grf(1, 1), ELK_REGISTER_TYPE_W)); - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_W); - bld.ASR(tmp, g1, brw_imm_d(15)); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_W); + bld.ASR(tmp, g1, elk_imm_d(15)); bld.NOT(ff, tmp); } else if (devinfo->ver >= 6) { /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create @@ -3687,10 +3687,10 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) * * An ASR 15 fills the low word of the destination. */ - fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W)); + elk_fs_reg g0 = elk_fs_reg(retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_W)); g0.negate = true; - bld.ASR(ff, g0, brw_imm_d(15)); + bld.ASR(ff, g0, elk_imm_d(15)); } else { /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create * a boolean result from this (1/true or 0/false). @@ -3702,37 +3702,37 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) * * Instead, use ASR (which will give ~0/true or 0/false). */ - fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D)); + elk_fs_reg g1_6 = elk_fs_reg(retype(elk_vec1_grf(1, 6), ELK_REGISTER_TYPE_D)); g1_6.negate = true; - bld.ASR(ff, g1_6, brw_imm_d(31)); + bld.ASR(ff, g1_6, elk_imm_d(31)); } return ff; } -static fs_reg -emit_samplepos_setup(nir_to_brw_state &ntb) +static elk_fs_reg +emit_samplepos_setup(nir_to_elk_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); - struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); + struct elk_wm_prog_data *wm_prog_data = elk_wm_prog_data(s.prog_data); assert(devinfo->ver >= 6); const fs_builder abld = bld.annotate("compute sample position"); - fs_reg pos = abld.vgrf(BRW_REGISTER_TYPE_F, 2); + elk_fs_reg pos = abld.vgrf(ELK_REGISTER_TYPE_F, 2); - if (wm_prog_data->persample_dispatch == BRW_NEVER) { + if (wm_prog_data->persample_dispatch == ELK_NEVER) { /* From ARB_sample_shading specification: * "When rendering to a non-multisample buffer, or if multisample * rasterization is disabled, gl_SamplePosition will always be * (0.5, 0.5). */ - bld.MOV(offset(pos, bld, 0), brw_imm_f(0.5f)); - bld.MOV(offset(pos, bld, 1), brw_imm_f(0.5f)); + bld.MOV(offset(pos, bld, 0), elk_imm_f(0.5f)); + bld.MOV(offset(pos, bld, 1), elk_imm_f(0.5f)); return pos; } @@ -3747,48 +3747,48 @@ emit_samplepos_setup(nir_to_brw_state &ntb) * The X, Y sample positions come in as bytes in thread payload. So, read * the positions using vstride=16, width=8, hstride=2. */ - const fs_reg sample_pos_reg = - fetch_payload_reg(abld, s.fs_payload().sample_pos_reg, BRW_REGISTER_TYPE_W); + const elk_fs_reg sample_pos_reg = + fetch_payload_reg(abld, s.fs_payload().sample_pos_reg, ELK_REGISTER_TYPE_W); for (unsigned i = 0; i < 2; i++) { - fs_reg tmp_d = bld.vgrf(BRW_REGISTER_TYPE_D); - abld.MOV(tmp_d, subscript(sample_pos_reg, BRW_REGISTER_TYPE_B, i)); + elk_fs_reg tmp_d = bld.vgrf(ELK_REGISTER_TYPE_D); + abld.MOV(tmp_d, subscript(sample_pos_reg, ELK_REGISTER_TYPE_B, i)); /* Convert int_sample_pos to floating point */ - fs_reg tmp_f = bld.vgrf(BRW_REGISTER_TYPE_F); + elk_fs_reg tmp_f = bld.vgrf(ELK_REGISTER_TYPE_F); abld.MOV(tmp_f, tmp_d); /* Scale to the range [0, 1] */ - abld.MUL(offset(pos, abld, i), tmp_f, brw_imm_f(1 / 16.0f)); + abld.MUL(offset(pos, abld, i), tmp_f, elk_imm_f(1 / 16.0f)); } - if (wm_prog_data->persample_dispatch == BRW_SOMETIMES) { + if (wm_prog_data->persample_dispatch == ELK_SOMETIMES) { check_dynamic_msaa_flag(abld, wm_prog_data, INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH); for (unsigned i = 0; i < 2; i++) { - set_predicate(BRW_PREDICATE_NORMAL, + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(offset(pos, abld, i), offset(pos, abld, i), - brw_imm_f(0.5f))); + elk_imm_f(0.5f))); } } return pos; } -static fs_reg -emit_sampleid_setup(nir_to_brw_state &ntb) +static elk_fs_reg +emit_sampleid_setup(nir_to_elk_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); - ASSERTED brw_wm_prog_key *key = (brw_wm_prog_key*) s.key; - struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); + ASSERTED elk_wm_prog_key *key = (elk_wm_prog_key*) s.key; + struct elk_wm_prog_data *wm_prog_data = elk_wm_prog_data(s.prog_data); assert(devinfo->ver >= 6); const fs_builder abld = bld.annotate("compute sample id"); - fs_reg sample_id = abld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg sample_id = abld.vgrf(ELK_REGISTER_TYPE_UD); - assert(key->multisample_fbo != BRW_NEVER); + assert(key->multisample_fbo != ELK_NEVER); if (devinfo->ver >= 8) { /* Sample ID comes in as 4-bit numbers in g1.0: @@ -3819,7 +3819,7 @@ emit_sampleid_setup(nir_to_brw_state &ntb) * TODO: These payload bits exist on Gfx7 too, but they appear to always * be zero, so this code fails to work. We should find out why. */ - const fs_reg tmp = abld.vgrf(BRW_REGISTER_TYPE_UW); + const elk_fs_reg tmp = abld.vgrf(ELK_REGISTER_TYPE_UW); for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); @@ -3827,17 +3827,17 @@ emit_sampleid_setup(nir_to_brw_state &ntb) * pages on the BSpec, the sample ids are stored in R0.8/R1.8 * on gfx20+ and in R1.0/R2.0 on gfx8+. */ - const struct brw_reg id_reg = devinfo->ver >= 20 ? xe2_vec1_grf(i, 8) : - brw_vec1_grf(i + 1, 0); + const struct elk_reg id_reg = devinfo->ver >= 20 ? xe2_vec1_grf(i, 8) : + elk_vec1_grf(i + 1, 0); hbld.SHR(offset(tmp, hbld, i), - stride(retype(id_reg, BRW_REGISTER_TYPE_UB), 1, 8, 0), - brw_imm_v(0x44440000)); + stride(retype(id_reg, ELK_REGISTER_TYPE_UB), 1, 8, 0), + elk_imm_v(0x44440000)); } - abld.AND(sample_id, tmp, brw_imm_w(0xf)); + abld.AND(sample_id, tmp, elk_imm_w(0xf)); } else { - const fs_reg t1 = component(abld.vgrf(BRW_REGISTER_TYPE_UD), 0); - const fs_reg t2 = abld.vgrf(BRW_REGISTER_TYPE_UW); + const elk_fs_reg t1 = component(abld.vgrf(ELK_REGISTER_TYPE_UD), 0); + const elk_fs_reg t2 = abld.vgrf(ELK_REGISTER_TYPE_UW); /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with * 8x multisampling, subspan 0 will represent sample N (where N @@ -3863,9 +3863,9 @@ emit_sampleid_setup(nir_to_brw_state &ntb) * accommodate 16x MSAA. */ abld.exec_all().group(1, 0) - .AND(t1, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)), - brw_imm_ud(0xc0)); - abld.exec_all().group(1, 0).SHR(t1, t1, brw_imm_d(5)); + .AND(t1, elk_fs_reg(retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_UD)), + elk_imm_ud(0xc0)); + abld.exec_all().group(1, 0).SHR(t1, t1, elk_imm_d(5)); /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we * can assume 4x MSAA. Disallow it on IVB+ @@ -3875,42 +3875,42 @@ emit_sampleid_setup(nir_to_brw_state &ntb) */ if (devinfo->ver >= 7) s.limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gfx7"); - abld.exec_all().group(8, 0).MOV(t2, brw_imm_v(0x32103210)); + abld.exec_all().group(8, 0).MOV(t2, elk_imm_v(0x32103210)); /* This special instruction takes care of setting vstride=1, * width=4, hstride=0 of t2 during an ADD instruction. */ - abld.emit(FS_OPCODE_SET_SAMPLE_ID, sample_id, t1, t2); + abld.emit(ELK_FS_OPCODE_SET_SAMPLE_ID, sample_id, t1, t2); } - if (key->multisample_fbo == BRW_SOMETIMES) { + if (key->multisample_fbo == ELK_SOMETIMES) { check_dynamic_msaa_flag(abld, wm_prog_data, INTEL_MSAA_FLAG_MULTISAMPLE_FBO); - set_predicate(BRW_PREDICATE_NORMAL, - abld.SEL(sample_id, sample_id, brw_imm_ud(0))); + set_predicate(ELK_PREDICATE_NORMAL, + abld.SEL(sample_id, sample_id, elk_imm_ud(0))); } return sample_id; } -static fs_reg -emit_samplemaskin_setup(nir_to_brw_state &ntb) +static elk_fs_reg +emit_samplemaskin_setup(nir_to_elk_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); - struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); + struct elk_wm_prog_data *wm_prog_data = elk_wm_prog_data(s.prog_data); assert(devinfo->ver >= 6); /* The HW doesn't provide us with expected values. */ - assert(wm_prog_data->coarse_pixel_dispatch != BRW_ALWAYS); + assert(wm_prog_data->coarse_pixel_dispatch != ELK_ALWAYS); - fs_reg coverage_mask = - fetch_payload_reg(bld, s.fs_payload().sample_mask_in_reg, BRW_REGISTER_TYPE_D); + elk_fs_reg coverage_mask = + fetch_payload_reg(bld, s.fs_payload().sample_mask_in_reg, ELK_REGISTER_TYPE_D); - if (wm_prog_data->persample_dispatch == BRW_NEVER) + if (wm_prog_data->persample_dispatch == ELK_NEVER) return coverage_mask; /* gl_SampleMaskIn[] comes from two sources: the input coverage mask, @@ -3928,39 +3928,39 @@ emit_samplemaskin_setup(nir_to_brw_state &ntb) if (ntb.system_values[SYSTEM_VALUE_SAMPLE_ID].file == BAD_FILE) ntb.system_values[SYSTEM_VALUE_SAMPLE_ID] = emit_sampleid_setup(ntb); - fs_reg one = s.vgrf(glsl_int_type()); - fs_reg enabled_mask = s.vgrf(glsl_int_type()); - abld.MOV(one, brw_imm_d(1)); + elk_fs_reg one = s.vgrf(glsl_int_type()); + elk_fs_reg enabled_mask = s.vgrf(glsl_int_type()); + abld.MOV(one, elk_imm_d(1)); abld.SHL(enabled_mask, one, ntb.system_values[SYSTEM_VALUE_SAMPLE_ID]); - fs_reg mask = bld.vgrf(BRW_REGISTER_TYPE_D); + elk_fs_reg mask = bld.vgrf(ELK_REGISTER_TYPE_D); abld.AND(mask, enabled_mask, coverage_mask); - if (wm_prog_data->persample_dispatch == BRW_ALWAYS) + if (wm_prog_data->persample_dispatch == ELK_ALWAYS) return mask; check_dynamic_msaa_flag(abld, wm_prog_data, INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH); - set_predicate(BRW_PREDICATE_NORMAL, abld.SEL(mask, mask, coverage_mask)); + set_predicate(ELK_PREDICATE_NORMAL, abld.SEL(mask, mask, coverage_mask)); return mask; } -static fs_reg -emit_shading_rate_setup(nir_to_brw_state &ntb) +static elk_fs_reg +emit_shading_rate_setup(nir_to_elk_state &ntb) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; assert(devinfo->ver >= 11); - struct brw_wm_prog_data *wm_prog_data = - brw_wm_prog_data(bld.shader->stage_prog_data); + struct elk_wm_prog_data *wm_prog_data = + elk_wm_prog_data(bld.shader->stage_prog_data); /* Coarse pixel shading size fields overlap with other fields of not in * coarse pixel dispatch mode, so report 0 when that's not the case. */ - if (wm_prog_data->coarse_pixel_dispatch == BRW_NEVER) - return brw_imm_ud(0); + if (wm_prog_data->coarse_pixel_dispatch == ELK_NEVER) + return elk_imm_ud(0); const fs_builder abld = bld.annotate("compute fragment shading rate"); @@ -3971,53 +3971,53 @@ emit_shading_rate_setup(nir_to_brw_state &ntb) */ /* r1.0 - 0:7 ActualCoarsePixelShadingSize.X */ - fs_reg actual_x = fs_reg(retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UB)); + elk_fs_reg actual_x = elk_fs_reg(retype(elk_vec1_grf(1, 0), ELK_REGISTER_TYPE_UB)); /* r1.0 - 15:8 ActualCoarsePixelShadingSize.Y */ - fs_reg actual_y = byte_offset(actual_x, 1); + elk_fs_reg actual_y = byte_offset(actual_x, 1); - fs_reg int_rate_x = bld.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg int_rate_y = bld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg int_rate_x = bld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg int_rate_y = bld.vgrf(ELK_REGISTER_TYPE_UD); - abld.SHR(int_rate_y, actual_y, brw_imm_ud(1)); - abld.SHR(int_rate_x, actual_x, brw_imm_ud(1)); - abld.SHL(int_rate_x, int_rate_x, brw_imm_ud(2)); + abld.SHR(int_rate_y, actual_y, elk_imm_ud(1)); + abld.SHR(int_rate_x, actual_x, elk_imm_ud(1)); + abld.SHL(int_rate_x, int_rate_x, elk_imm_ud(2)); - fs_reg rate = abld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg rate = abld.vgrf(ELK_REGISTER_TYPE_UD); abld.OR(rate, int_rate_x, int_rate_y); - if (wm_prog_data->coarse_pixel_dispatch == BRW_ALWAYS) + if (wm_prog_data->coarse_pixel_dispatch == ELK_ALWAYS) return rate; check_dynamic_msaa_flag(abld, wm_prog_data, INTEL_MSAA_FLAG_COARSE_RT_WRITES); - set_predicate(BRW_PREDICATE_NORMAL, abld.SEL(rate, rate, brw_imm_ud(0))); + set_predicate(ELK_PREDICATE_NORMAL, abld.SEL(rate, rate, elk_imm_ud(0))); return rate; } static void -fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, +fs_nir_emit_fs_intrinsic(nir_to_elk_state &ntb, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); - fs_reg dest; + elk_fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); switch (instr->intrinsic) { case nir_intrinsic_load_front_face: - bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), + bld.MOV(retype(dest, ELK_REGISTER_TYPE_D), emit_frontfacing_interpolation(ntb)); break; case nir_intrinsic_load_sample_pos: case nir_intrinsic_load_sample_pos_or_center: { - fs_reg sample_pos = ntb.system_values[SYSTEM_VALUE_SAMPLE_POS]; + elk_fs_reg sample_pos = ntb.system_values[SYSTEM_VALUE_SAMPLE_POS]; assert(sample_pos.file != BAD_FILE); dest.type = sample_pos.type; bld.MOV(dest, sample_pos); @@ -4026,7 +4026,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_load_layer_id: - dest.type = BRW_REGISTER_TYPE_UD; + dest.type = ELK_REGISTER_TYPE_UD; bld.MOV(dest, fetch_render_target_array_index(bld)); break; @@ -4039,7 +4039,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_sample_id: case nir_intrinsic_load_frag_shading_rate: { gl_system_value sv = nir_system_value_from_intrinsic(instr->intrinsic); - fs_reg val = ntb.system_values[sv]; + elk_fs_reg val = ntb.system_values[sv]; assert(val.file != BAD_FILE); dest.type = val.type; bld.MOV(dest, val); @@ -4047,11 +4047,11 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_store_output: { - const fs_reg src = get_nir_src(ntb, instr->src[0]); + const elk_fs_reg src = get_nir_src(ntb, instr->src[0]); const unsigned store_offset = nir_src_as_uint(instr->src[1]); const unsigned location = nir_intrinsic_base(instr) + - SET_FIELD(store_offset, BRW_NIR_FRAG_OUTPUT_LOCATION); - const fs_reg new_dest = retype(alloc_frag_output(ntb, location), + SET_FIELD(store_offset, ELK_NIR_FRAG_OUTPUT_LOCATION); + const elk_fs_reg new_dest = retype(alloc_frag_output(ntb, location), src.type); for (unsigned j = 0; j < instr->num_components; j++) @@ -4063,13 +4063,13 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_output: { const unsigned l = GET_FIELD(nir_intrinsic_base(instr), - BRW_NIR_FRAG_OUTPUT_LOCATION); + ELK_NIR_FRAG_OUTPUT_LOCATION); assert(l >= FRAG_RESULT_DATA0); const unsigned load_offset = nir_src_as_uint(instr->src[0]); const unsigned target = l - FRAG_RESULT_DATA0 + load_offset; - const fs_reg tmp = bld.vgrf(dest.type, 4); + const elk_fs_reg tmp = bld.vgrf(dest.type, 4); - if (reinterpret_cast(s.key)->coherent_fb_fetch) + if (reinterpret_cast(s.key)->coherent_fb_fetch) emit_coherent_fb_read(bld, tmp, target); else emit_non_coherent_fb_read(ntb, bld, tmp, target); @@ -4093,7 +4093,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, * no condition, we emit a CMP of g0 != g0, so all currently executing * channels will get turned off. */ - fs_inst *cmp = NULL; + elk_fs_inst *cmp = NULL; if (instr->intrinsic == nir_intrinsic_demote_if || instr->intrinsic == nir_intrinsic_discard_if || instr->intrinsic == nir_intrinsic_terminate_if) { @@ -4102,7 +4102,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, if (alu != NULL && alu->op != nir_op_bcsel && (devinfo->ver > 5 || - (alu->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE || + (alu->instr.pass_flags & ELK_NIR_BOOLEAN_MASK) != ELK_NIR_BOOLEAN_NEEDS_RESOLVE || alu->op == nir_op_fneu32 || alu->op == nir_op_feq32 || alu->op == nir_op_flt32 || alu->op == nir_op_fge32 || alu->op == nir_op_ine32 || alu->op == nir_op_ieq32 || @@ -4124,10 +4124,10 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, */ fs_nir_emit_alu(ntb, alu, false); - cmp = (fs_inst *) s.instructions.get_tail(); - if (cmp->conditional_mod == BRW_CONDITIONAL_NONE) { + cmp = (elk_fs_inst *) s.instructions.get_tail(); + if (cmp->conditional_mod == ELK_CONDITIONAL_NONE) { if (cmp->can_do_cmod()) - cmp->conditional_mod = BRW_CONDITIONAL_Z; + cmp->conditional_mod = ELK_CONDITIONAL_Z; else cmp = NULL; } else { @@ -4135,36 +4135,36 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, * basically, bool_result == false. This is equivalent to * !bool_result, so negate the old modifier. */ - cmp->conditional_mod = brw_negate_cmod(cmp->conditional_mod); + cmp->conditional_mod = elk_negate_cmod(cmp->conditional_mod); } } if (cmp == NULL) { cmp = bld.CMP(bld.null_reg_f(), get_nir_src(ntb, instr->src[0]), - brw_imm_d(0), BRW_CONDITIONAL_Z); + elk_imm_d(0), ELK_CONDITIONAL_Z); } } else { - fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0), - BRW_REGISTER_TYPE_UW)); - cmp = bld.CMP(bld.null_reg_f(), some_reg, some_reg, BRW_CONDITIONAL_NZ); + elk_fs_reg some_reg = elk_fs_reg(retype(elk_vec8_grf(0, 0), + ELK_REGISTER_TYPE_UW)); + cmp = bld.CMP(bld.null_reg_f(), some_reg, some_reg, ELK_CONDITIONAL_NZ); } - cmp->predicate = BRW_PREDICATE_NORMAL; + cmp->predicate = ELK_PREDICATE_NORMAL; cmp->flag_subreg = sample_mask_flag_subreg(s); - fs_inst *jump = bld.emit(BRW_OPCODE_HALT); + elk_fs_inst *jump = bld.emit(ELK_OPCODE_HALT); jump->flag_subreg = sample_mask_flag_subreg(s); jump->predicate_inverse = true; if (instr->intrinsic == nir_intrinsic_terminate || instr->intrinsic == nir_intrinsic_terminate_if) { - jump->predicate = BRW_PREDICATE_NORMAL; + jump->predicate = ELK_PREDICATE_NORMAL; } else { /* Only jump when the whole quad is demoted. For historical * reasons this is also used for discard. */ jump->predicate = (devinfo->ver >= 20 ? XE2_PREDICATE_ANY : - BRW_PREDICATE_ALIGN1_ANY4H); + ELK_PREDICATE_ALIGN1_ANY4H); } if (devinfo->ver < 7) @@ -4213,7 +4213,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, assert(nir_src_as_uint(instr->src[0]) == 0); const unsigned base = nir_intrinsic_base(instr); const unsigned comp = nir_intrinsic_component(instr); - dest.type = BRW_REGISTER_TYPE_F; + dest.type = ELK_REGISTER_TYPE_F; /* Gfx20+ packs the plane parameters of a single logical * input in a vec3 format instead of the previously used vec4 @@ -4236,8 +4236,8 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_barycentric_centroid: case nir_intrinsic_load_barycentric_sample: { /* Use the delta_xy values computed from the payload */ - enum brw_barycentric_mode bary = brw_barycentric_mode(instr); - const fs_reg srcs[] = { offset(s.delta_xy[bary], bld, 0), + enum elk_barycentric_mode bary = elk_barycentric_mode(instr); + const elk_fs_reg srcs[] = { offset(s.delta_xy[bary], bld, 0), offset(s.delta_xy[bary], bld, 1) }; bld.LOAD_PAYLOAD(dest, srcs, ARRAY_SIZE(srcs), 0); break; @@ -4247,32 +4247,32 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, const glsl_interp_mode interpolation = (enum glsl_interp_mode) nir_intrinsic_interp_mode(instr); - fs_reg msg_data; + elk_fs_reg msg_data; if (nir_src_is_const(instr->src[0])) { - msg_data = brw_imm_ud(nir_src_as_uint(instr->src[0]) << 4); + msg_data = elk_imm_ud(nir_src_as_uint(instr->src[0]) << 4); } else { - const fs_reg sample_src = retype(get_nir_src(ntb, instr->src[0]), - BRW_REGISTER_TYPE_UD); - const fs_reg sample_id = bld.emit_uniformize(sample_src); - msg_data = component(bld.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD), 0); - bld.exec_all().group(1, 0).SHL(msg_data, sample_id, brw_imm_ud(4u)); + const elk_fs_reg sample_src = retype(get_nir_src(ntb, instr->src[0]), + ELK_REGISTER_TYPE_UD); + const elk_fs_reg sample_id = bld.emit_uniformize(sample_src); + msg_data = component(bld.group(8, 0).vgrf(ELK_REGISTER_TYPE_UD), 0); + bld.exec_all().group(1, 0).SHL(msg_data, sample_id, elk_imm_ud(4u)); } - fs_reg flag_reg; - struct brw_wm_prog_key *wm_prog_key = (struct brw_wm_prog_key *) s.key; - if (wm_prog_key->multisample_fbo == BRW_SOMETIMES) { - struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); + elk_fs_reg flag_reg; + struct elk_wm_prog_key *wm_prog_key = (struct elk_wm_prog_key *) s.key; + if (wm_prog_key->multisample_fbo == ELK_SOMETIMES) { + struct elk_wm_prog_data *wm_prog_data = elk_wm_prog_data(s.prog_data); check_dynamic_msaa_flag(bld.exec_all().group(8, 0), wm_prog_data, INTEL_MSAA_FLAG_MULTISAMPLE_FBO); - flag_reg = brw_flag_reg(0, 0); + flag_reg = elk_flag_reg(0, 0); } emit_pixel_interpolater_send(bld, - FS_OPCODE_INTERPOLATE_AT_SAMPLE, + ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE, dest, - fs_reg(), /* src */ + elk_fs_reg(), /* src */ msg_data, flag_reg, interpolation); @@ -4291,21 +4291,21 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, unsigned off_y = const_offset[1].u32 & 0xf; emit_pixel_interpolater_send(bld, - FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, + ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dest, - fs_reg(), /* src */ - brw_imm_ud(off_x | (off_y << 4)), - fs_reg(), /* flag_reg */ + elk_fs_reg(), /* src */ + elk_imm_ud(off_x | (off_y << 4)), + elk_fs_reg(), /* flag_reg */ interpolation); } else { - fs_reg src = retype(get_nir_src(ntb, instr->src[0]), BRW_REGISTER_TYPE_D); - const enum opcode opcode = FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET; + elk_fs_reg src = retype(get_nir_src(ntb, instr->src[0]), ELK_REGISTER_TYPE_D); + const enum elk_opcode opcode = ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET; emit_pixel_interpolater_send(bld, opcode, dest, src, - brw_imm_ud(0u), - fs_reg(), /* flag_reg */ + elk_imm_ud(0u), + elk_fs_reg(), /* flag_reg */ interpolation); } break; @@ -4323,31 +4323,31 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_op bary_intrin = bary_intrinsic->intrinsic; enum glsl_interp_mode interp_mode = (enum glsl_interp_mode) nir_intrinsic_interp_mode(bary_intrinsic); - fs_reg dst_xy; + elk_fs_reg dst_xy; if (bary_intrin == nir_intrinsic_load_barycentric_at_offset || bary_intrin == nir_intrinsic_load_barycentric_at_sample) { /* Use the result of the PI message. */ - dst_xy = retype(get_nir_src(ntb, instr->src[0]), BRW_REGISTER_TYPE_F); + dst_xy = retype(get_nir_src(ntb, instr->src[0]), ELK_REGISTER_TYPE_F); } else { /* Use the delta_xy values computed from the payload */ - enum brw_barycentric_mode bary = brw_barycentric_mode(bary_intrinsic); + enum elk_barycentric_mode bary = elk_barycentric_mode(bary_intrinsic); dst_xy = s.delta_xy[bary]; } for (unsigned int i = 0; i < instr->num_components; i++) { - fs_reg interp = + elk_fs_reg interp = s.interp_reg(bld, nir_intrinsic_base(instr), nir_intrinsic_component(instr) + i, 0); - interp.type = BRW_REGISTER_TYPE_F; - dest.type = BRW_REGISTER_TYPE_F; + interp.type = ELK_REGISTER_TYPE_F; + dest.type = ELK_REGISTER_TYPE_F; if (devinfo->ver < 6 && interp_mode == INTERP_MODE_SMOOTH) { - fs_reg tmp = s.vgrf(glsl_float_type()); - bld.emit(FS_OPCODE_LINTERP, tmp, dst_xy, interp); + elk_fs_reg tmp = s.vgrf(glsl_float_type()); + bld.emit(ELK_FS_OPCODE_LINTERP, tmp, dst_xy, interp); bld.MUL(offset(dest, bld, i), tmp, s.pixel_w); } else { - bld.emit(FS_OPCODE_LINTERP, offset(dest, bld, i), dst_xy, interp); + bld.emit(ELK_FS_OPCODE_LINTERP, offset(dest, bld, i), dst_xy, interp); } } break; @@ -4360,17 +4360,17 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, } static void -fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, +fs_nir_emit_cs_intrinsic(nir_to_elk_state &ntb, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; assert(gl_shader_stage_uses_workgroup(s.stage)); - struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(s.prog_data); + struct elk_cs_prog_data *cs_prog_data = elk_cs_prog_data(s.prog_data); - fs_reg dest; + elk_fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); @@ -4385,7 +4385,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, */ if (!s.nir->info.workgroup_size_variable && s.workgroup_size() <= s.dispatch_width) { - bld.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE); + bld.exec_all().group(1, 0).emit(ELK_FS_OPCODE_SCHEDULING_FENCE); break; } @@ -4402,7 +4402,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, /* This is only used for hardware generated local IDs. */ assert(cs_prog_data->generate_local_id); - dest.type = BRW_REGISTER_TYPE_UD; + dest.type = ELK_REGISTER_TYPE_UD; for (unsigned i = 0; i < 3; i++) bld.MOV(offset(dest, bld, i), s.cs_payload().local_invocation_id[i]); @@ -4410,7 +4410,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_workgroup_id: case nir_intrinsic_load_workgroup_id_zero_base: { - fs_reg val = ntb.system_values[SYSTEM_VALUE_WORKGROUP_ID]; + elk_fs_reg val = ntb.system_values[SYSTEM_VALUE_WORKGROUP_ID]; assert(val.file != BAD_FILE); dest.type = val.type; for (unsigned i = 0; i < 3; i++) @@ -4423,14 +4423,14 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, cs_prog_data->uses_num_work_groups = true; - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(0); - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(3); /* num components */ - srcs[SURFACE_LOGICAL_SRC_ADDRESS] = brw_imm_ud(0); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); - fs_inst *inst = - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + srcs[SURFACE_LOGICAL_SRC_SURFACE] = elk_imm_ud(0); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(3); /* num components */ + srcs[SURFACE_LOGICAL_SRC_ADDRESS] = elk_imm_ud(0); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(0); + elk_fs_inst *inst = + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); inst->size_written = 3 * s.dispatch_width * 4; break; @@ -4438,7 +4438,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_shared_atomic: case nir_intrinsic_shared_atomic_swap: - fs_nir_emit_surface_atomic(ntb, bld, instr, brw_imm_ud(GFX7_BTI_SLM), + fs_nir_emit_surface_atomic(ntb, bld, instr, elk_imm_ud(GFX7_BTI_SLM), false /* bindless */); break; @@ -4446,24 +4446,24 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, assert(devinfo->ver >= 7); const unsigned bit_size = instr->def.bit_size; - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM); + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + srcs[SURFACE_LOGICAL_SRC_SURFACE] = elk_imm_ud(GFX7_BTI_SLM); - fs_reg addr = get_nir_src(ntb, instr->src[0]); + elk_fs_reg addr = get_nir_src(ntb, instr->src[0]); int base = nir_intrinsic_base(instr); if (base) { - fs_reg addr_off = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - bld.ADD(addr_off, addr, brw_imm_d(base)); + elk_fs_reg addr_off = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + bld.ADD(addr_off, addr, elk_imm_d(base)); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr_off; } else { srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr; } - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(0); /* Make dest unsigned because that's what the temporary will be */ - dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD); + dest.type = elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_UD); /* Read the vector */ assert(bit_size <= 32); @@ -4471,17 +4471,17 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, if (bit_size == 32 && nir_intrinsic_align(instr) >= 4) { assert(instr->def.num_components <= 4); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components); - fs_inst *inst = - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(instr->num_components); + elk_fs_inst *inst = + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); inst->size_written = instr->num_components * s.dispatch_width * 4; } else { assert(instr->def.num_components == 1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(bit_size); - fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, + elk_fs_reg read_result = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.emit(ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, read_result, srcs, SURFACE_LOGICAL_NUM_SRCS); bld.MOV(dest, subscript(read_result, dest.type, 0)); } @@ -4492,27 +4492,27 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, assert(devinfo->ver >= 7); const unsigned bit_size = nir_src_bit_size(instr->src[0]); - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM); + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + srcs[SURFACE_LOGICAL_SRC_SURFACE] = elk_imm_ud(GFX7_BTI_SLM); - fs_reg addr = get_nir_src(ntb, instr->src[1]); + elk_fs_reg addr = get_nir_src(ntb, instr->src[1]); int base = nir_intrinsic_base(instr); if (base) { - fs_reg addr_off = bld.vgrf(BRW_REGISTER_TYPE_UD, 1); - bld.ADD(addr_off, addr, brw_imm_d(base)); + elk_fs_reg addr_off = bld.vgrf(ELK_REGISTER_TYPE_UD, 1); + bld.ADD(addr_off, addr, elk_imm_d(base)); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr_off; } else { srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr; } - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); /* No point in masking with sample mask, here we're handling compute * intrinsics. */ - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(0); - fs_reg data = get_nir_src(ntb, instr->src[0]); - data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD); + elk_fs_reg data = get_nir_src(ntb, instr->src[0]); + data.type = elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_UD); assert(bit_size <= 32); assert(nir_intrinsic_write_mask(instr) == @@ -4522,24 +4522,24 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_align(instr) >= 4) { assert(nir_src_num_components(instr->src[0]) <= 4); srcs[SURFACE_LOGICAL_SRC_DATA] = data; - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components); - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(instr->num_components); + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); } else { assert(nir_src_num_components(instr->src[0]) == 1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(bit_size); - srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD); + srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(ELK_REGISTER_TYPE_UD); bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data); - bld.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + bld.emit(ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); } break; } case nir_intrinsic_load_workgroup_size: { - /* Should have been lowered by brw_nir_lower_cs_intrinsics() or + /* Should have been lowered by elk_nir_lower_cs_intrinsics() or * crocus/iris_setup_uniforms() for the variable group size case. */ unreachable("Should have been lowered"); @@ -4550,14 +4550,14 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, const unsigned sdepth = nir_intrinsic_systolic_depth(instr); const unsigned rcount = nir_intrinsic_repeat_count(instr); - const brw_reg_type dest_type = - brw_type_for_nir_type(devinfo, nir_intrinsic_dest_type(instr)); - const brw_reg_type src_type = - brw_type_for_nir_type(devinfo, nir_intrinsic_src_type(instr)); + const elk_reg_type dest_type = + elk_type_for_nir_type(devinfo, nir_intrinsic_dest_type(instr)); + const elk_reg_type src_type = + elk_type_for_nir_type(devinfo, nir_intrinsic_src_type(instr)); dest = retype(dest, dest_type); - fs_reg src2 = retype(get_nir_src(ntb, instr->src[2]), dest_type); - const fs_reg dest_hf = dest; + elk_fs_reg src2 = retype(get_nir_src(ntb, instr->src[2]), dest_type); + const elk_fs_reg dest_hf = dest; fs_builder bld8 = bld.exec_all().group(8, 0); fs_builder bld16 = bld.exec_all().group(16, 0); @@ -4568,21 +4568,21 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, * * The float16 source must be expanded to float32. */ - if (devinfo->verx10 == 125 && dest_type == BRW_REGISTER_TYPE_HF && + if (devinfo->verx10 == 125 && dest_type == ELK_REGISTER_TYPE_HF && !s.compiler->lower_dpas) { - dest = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount); + dest = bld8.vgrf(ELK_REGISTER_TYPE_F, rcount); if (src2.file != ARF) { - const fs_reg src2_hf = src2; + const elk_fs_reg src2_hf = src2; - src2 = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount); + src2 = bld8.vgrf(ELK_REGISTER_TYPE_F, rcount); for (unsigned i = 0; i < 4; i++) { bld16.MOV(byte_offset(src2, REG_SIZE * i * 2), byte_offset(src2_hf, REG_SIZE * i)); } } else { - src2 = retype(src2, BRW_REGISTER_TYPE_F); + src2 = retype(src2, ELK_REGISTER_TYPE_F); } } @@ -4612,72 +4612,72 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, } } -static fs_reg -brw_nir_reduction_op_identity(const fs_builder &bld, - nir_op op, brw_reg_type type) +static elk_fs_reg +elk_nir_reduction_op_identity(const fs_builder &bld, + nir_op op, elk_reg_type type) { nir_const_value value = nir_alu_binop_identity(op, type_sz(type) * 8); switch (type_sz(type)) { case 1: - if (type == BRW_REGISTER_TYPE_UB) { - return brw_imm_uw(value.u8); + if (type == ELK_REGISTER_TYPE_UB) { + return elk_imm_uw(value.u8); } else { - assert(type == BRW_REGISTER_TYPE_B); - return brw_imm_w(value.i8); + assert(type == ELK_REGISTER_TYPE_B); + return elk_imm_w(value.i8); } case 2: - return retype(brw_imm_uw(value.u16), type); + return retype(elk_imm_uw(value.u16), type); case 4: - return retype(brw_imm_ud(value.u32), type); + return retype(elk_imm_ud(value.u32), type); case 8: - if (type == BRW_REGISTER_TYPE_DF) - return setup_imm_df(bld, value.f64); + if (type == ELK_REGISTER_TYPE_DF) + return elk_setup_imm_df(bld, value.f64); else - return retype(brw_imm_u64(value.u64), type); + return retype(elk_imm_u64(value.u64), type); default: unreachable("Invalid type size"); } } -static opcode -brw_op_for_nir_reduction_op(nir_op op) +static elk_opcode +elk_op_for_nir_reduction_op(nir_op op) { switch (op) { - case nir_op_iadd: return BRW_OPCODE_ADD; - case nir_op_fadd: return BRW_OPCODE_ADD; - case nir_op_imul: return BRW_OPCODE_MUL; - case nir_op_fmul: return BRW_OPCODE_MUL; - case nir_op_imin: return BRW_OPCODE_SEL; - case nir_op_umin: return BRW_OPCODE_SEL; - case nir_op_fmin: return BRW_OPCODE_SEL; - case nir_op_imax: return BRW_OPCODE_SEL; - case nir_op_umax: return BRW_OPCODE_SEL; - case nir_op_fmax: return BRW_OPCODE_SEL; - case nir_op_iand: return BRW_OPCODE_AND; - case nir_op_ior: return BRW_OPCODE_OR; - case nir_op_ixor: return BRW_OPCODE_XOR; + case nir_op_iadd: return ELK_OPCODE_ADD; + case nir_op_fadd: return ELK_OPCODE_ADD; + case nir_op_imul: return ELK_OPCODE_MUL; + case nir_op_fmul: return ELK_OPCODE_MUL; + case nir_op_imin: return ELK_OPCODE_SEL; + case nir_op_umin: return ELK_OPCODE_SEL; + case nir_op_fmin: return ELK_OPCODE_SEL; + case nir_op_imax: return ELK_OPCODE_SEL; + case nir_op_umax: return ELK_OPCODE_SEL; + case nir_op_fmax: return ELK_OPCODE_SEL; + case nir_op_iand: return ELK_OPCODE_AND; + case nir_op_ior: return ELK_OPCODE_OR; + case nir_op_ixor: return ELK_OPCODE_XOR; default: unreachable("Invalid reduction operation"); } } -static brw_conditional_mod -brw_cond_mod_for_nir_reduction_op(nir_op op) +static elk_conditional_mod +elk_cond_mod_for_nir_reduction_op(nir_op op) { switch (op) { - case nir_op_iadd: return BRW_CONDITIONAL_NONE; - case nir_op_fadd: return BRW_CONDITIONAL_NONE; - case nir_op_imul: return BRW_CONDITIONAL_NONE; - case nir_op_fmul: return BRW_CONDITIONAL_NONE; - case nir_op_imin: return BRW_CONDITIONAL_L; - case nir_op_umin: return BRW_CONDITIONAL_L; - case nir_op_fmin: return BRW_CONDITIONAL_L; - case nir_op_imax: return BRW_CONDITIONAL_GE; - case nir_op_umax: return BRW_CONDITIONAL_GE; - case nir_op_fmax: return BRW_CONDITIONAL_GE; - case nir_op_iand: return BRW_CONDITIONAL_NONE; - case nir_op_ior: return BRW_CONDITIONAL_NONE; - case nir_op_ixor: return BRW_CONDITIONAL_NONE; + case nir_op_iadd: return ELK_CONDITIONAL_NONE; + case nir_op_fadd: return ELK_CONDITIONAL_NONE; + case nir_op_imul: return ELK_CONDITIONAL_NONE; + case nir_op_fmul: return ELK_CONDITIONAL_NONE; + case nir_op_imin: return ELK_CONDITIONAL_L; + case nir_op_umin: return ELK_CONDITIONAL_L; + case nir_op_fmin: return ELK_CONDITIONAL_L; + case nir_op_imax: return ELK_CONDITIONAL_GE; + case nir_op_umax: return ELK_CONDITIONAL_GE; + case nir_op_fmax: return ELK_CONDITIONAL_GE; + case nir_op_iand: return ELK_CONDITIONAL_NONE; + case nir_op_ior: return ELK_CONDITIONAL_NONE; + case nir_op_ixor: return ELK_CONDITIONAL_NONE; default: unreachable("Invalid reduction operation"); } @@ -4703,8 +4703,8 @@ add_rebuild_src(nir_src *src, void *state) return true; } -static fs_reg -try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def *resource_def) +static elk_fs_reg +try_rebuild_resource(nir_to_elk_state &ntb, const elk::fs_builder &bld, nir_def *resource_def) { /* Create a build at the location of the resource_intel intrinsic */ fs_builder ubld8 = bld.exec_all().group(8, 0); @@ -4714,7 +4714,7 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def if (!nir_foreach_src(resource_def->parent_instr, add_rebuild_src, &resources)) - return fs_reg(); + return elk_fs_reg(); resources.array.push_back(resource_def); if (resources.array.size() == 1) { @@ -4723,7 +4723,7 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def if (def->parent_instr->type == nir_instr_type_load_const) { nir_load_const_instr *load_const = nir_instr_as_load_const(def->parent_instr); - return brw_imm_ud(load_const->value[0].i32); + return elk_imm_ud(load_const->value[0].i32); } else { assert(def->parent_instr->type == nir_instr_type_intrinsic && (nir_instr_as_intrinsic(def->parent_instr)->intrinsic == @@ -4731,7 +4731,7 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(def->parent_instr); unsigned base_offset = nir_intrinsic_base(intrin); unsigned load_offset = nir_src_as_uint(intrin->src[0]); - fs_reg src(UNIFORM, base_offset / 4, BRW_REGISTER_TYPE_UD); + elk_fs_reg src(UNIFORM, base_offset / 4, ELK_REGISTER_TYPE_UD); src.offset = load_offset + base_offset % 4; return src; } @@ -4745,9 +4745,9 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def case nir_instr_type_load_const: { nir_load_const_instr *load_const = nir_instr_as_load_const(instr); - fs_reg dst = ubld8.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg dst = ubld8.vgrf(ELK_REGISTER_TYPE_UD); ntb.resource_insts[def->index] = - ubld8.MOV(dst, brw_imm_ud(load_const->value[0].i32)); + ubld8.MOV(dst, elk_imm_ud(load_const->value[0].i32)); break; } @@ -4770,11 +4770,11 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def switch (alu->op) { case nir_op_iadd: { - fs_reg dst = ubld8.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst; - fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst; + elk_fs_reg dst = ubld8.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst; + elk_fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst; assert(src0.file != BAD_FILE && src1.file != BAD_FILE); - assert(src0.type == BRW_REGISTER_TYPE_UD); + assert(src0.type == ELK_REGISTER_TYPE_UD); ntb.resource_insts[def->index] = ubld8.ADD(dst, src0.file != IMM ? src0 : src1, @@ -4782,12 +4782,12 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def break; } case nir_op_iadd3: { - fs_reg dst = ubld8.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst; - fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst; - fs_reg src2 = ntb.resource_insts[alu->src[2].src.ssa->index]->dst; + elk_fs_reg dst = ubld8.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst; + elk_fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst; + elk_fs_reg src2 = ntb.resource_insts[alu->src[2].src.ssa->index]->dst; assert(src0.file != BAD_FILE && src1.file != BAD_FILE && src2.file != BAD_FILE); - assert(src0.type == BRW_REGISTER_TYPE_UD); + assert(src0.type == ELK_REGISTER_TYPE_UD); ntb.resource_insts[def->index] = ubld8.ADD3(dst, src1.file == IMM ? src1 : src0, @@ -4796,20 +4796,20 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def break; } case nir_op_ushr: { - fs_reg dst = ubld8.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst; - fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst; + elk_fs_reg dst = ubld8.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst; + elk_fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst; assert(src0.file != BAD_FILE && src1.file != BAD_FILE); - assert(src0.type == BRW_REGISTER_TYPE_UD); + assert(src0.type == ELK_REGISTER_TYPE_UD); ntb.resource_insts[def->index] = ubld8.SHR(dst, src0, src1); break; } case nir_op_ishl: { - fs_reg dst = ubld8.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst; - fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst; + elk_fs_reg dst = ubld8.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg src0 = ntb.resource_insts[alu->src[0].src.ssa->index]->dst; + elk_fs_reg src1 = ntb.resource_insts[alu->src[1].src.ssa->index]->dst; assert(src0.file != BAD_FILE && src1.file != BAD_FILE); - assert(src0.type == BRW_REGISTER_TYPE_UD); + assert(src0.type == ELK_REGISTER_TYPE_UD); ntb.resource_insts[def->index] = ubld8.SHL(dst, src0, src1); break; } @@ -4836,8 +4836,8 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def unsigned base_offset = nir_intrinsic_base(intrin); unsigned load_offset = nir_src_as_uint(intrin->src[0]); - fs_reg dst = ubld8.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg src(UNIFORM, base_offset / 4, BRW_REGISTER_TYPE_UD); + elk_fs_reg dst = ubld8.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg src(UNIFORM, base_offset / 4, ELK_REGISTER_TYPE_UD); src.offset = load_offset + base_offset % 4; ntb.resource_insts[def->index] = ubld8.MOV(dst, src); break; @@ -4854,31 +4854,31 @@ try_rebuild_resource(nir_to_brw_state &ntb, const elk::fs_builder &bld, nir_def } if (ntb.resource_insts[def->index] == NULL) - return fs_reg(); + return elk_fs_reg(); } assert(ntb.resource_insts[resource_def->index] != NULL); return component(ntb.resource_insts[resource_def->index]->dst, 0); } -static fs_reg -get_nir_image_intrinsic_image(nir_to_brw_state &ntb, const elk::fs_builder &bld, +static elk_fs_reg +get_nir_image_intrinsic_image(nir_to_elk_state &ntb, const elk::fs_builder &bld, nir_intrinsic_instr *instr) { if (is_resource_src(instr->src[0])) { - fs_reg surf_index = get_resource_nir_src(ntb, instr->src[0]); + elk_fs_reg surf_index = get_resource_nir_src(ntb, instr->src[0]); if (surf_index.file != BAD_FILE) return surf_index; } - fs_reg image = retype(get_nir_src_imm(ntb, instr->src[0]), BRW_REGISTER_TYPE_UD); - fs_reg surf_index = image; + elk_fs_reg image = retype(get_nir_src_imm(ntb, instr->src[0]), ELK_REGISTER_TYPE_UD); + elk_fs_reg surf_index = image; return bld.emit_uniformize(surf_index); } -static fs_reg -get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const elk::fs_builder &bld, +static elk_fs_reg +get_nir_buffer_intrinsic_index(nir_to_elk_state &ntb, const elk::fs_builder &bld, nir_intrinsic_instr *instr) { /* SSBO stores are weird in that their index is in src[1] */ @@ -4888,9 +4888,9 @@ get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const elk::fs_builder &bld nir_src src = is_store ? instr->src[1] : instr->src[0]; if (nir_src_is_const(src)) { - return brw_imm_ud(nir_src_as_uint(src)); + return elk_imm_ud(nir_src_as_uint(src)); } else if (is_resource_src(src)) { - fs_reg surf_index = get_resource_nir_src(ntb, src); + elk_fs_reg surf_index = get_resource_nir_src(ntb, src); if (surf_index.file != BAD_FILE) return surf_index; } @@ -4920,35 +4920,35 @@ get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const elk::fs_builder &bld * at the same logical offset, the scratch read/write instruction acts on * continuous elements and we get good cache locality. */ -static fs_reg -swizzle_nir_scratch_addr(nir_to_brw_state &ntb, +static elk_fs_reg +swizzle_nir_scratch_addr(nir_to_elk_state &ntb, const elk::fs_builder &bld, - const fs_reg &nir_addr, + const elk_fs_reg &nir_addr, bool in_dwords) { - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; - const fs_reg &chan_index = + const elk_fs_reg &chan_index = ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]; const unsigned chan_index_bits = ffs(s.dispatch_width) - 1; - fs_reg addr = bld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg addr = bld.vgrf(ELK_REGISTER_TYPE_UD); if (in_dwords) { /* In this case, we know the address is aligned to a DWORD and we want * the final address in DWORDs. */ - bld.SHL(addr, nir_addr, brw_imm_ud(chan_index_bits - 2)); + bld.SHL(addr, nir_addr, elk_imm_ud(chan_index_bits - 2)); bld.OR(addr, addr, chan_index); } else { /* This case substantially more annoying because we have to pay * attention to those pesky two bottom bits. */ - fs_reg addr_hi = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.AND(addr_hi, nir_addr, brw_imm_ud(~0x3u)); - bld.SHL(addr_hi, addr_hi, brw_imm_ud(chan_index_bits)); - fs_reg chan_addr = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.SHL(chan_addr, chan_index, brw_imm_ud(2)); - bld.AND(addr, nir_addr, brw_imm_ud(0x3u)); + elk_fs_reg addr_hi = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.AND(addr_hi, nir_addr, elk_imm_ud(~0x3u)); + bld.SHL(addr_hi, addr_hi, elk_imm_ud(chan_index_bits)); + elk_fs_reg chan_addr = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.SHL(chan_addr, chan_index, elk_imm_ud(2)); + bld.AND(addr, nir_addr, elk_imm_ud(0x3u)); bld.OR(addr, addr, addr_hi); bld.OR(addr, addr, chan_addr); } @@ -4974,32 +4974,32 @@ choose_oword_block_size_dwords(const struct intel_device_info *devinfo, } static void -increment_a64_address(const fs_builder &bld, fs_reg address, uint32_t v) +increment_a64_address(const fs_builder &bld, elk_fs_reg address, uint32_t v) { if (bld.shader->devinfo->has_64bit_int) { - bld.ADD(address, address, brw_imm_ud(v)); + bld.ADD(address, address, elk_imm_ud(v)); } else { - fs_reg low = retype(address, BRW_REGISTER_TYPE_UD); - fs_reg high = offset(low, bld, 1); + elk_fs_reg low = retype(address, ELK_REGISTER_TYPE_UD); + elk_fs_reg high = offset(low, bld, 1); /* Add low and if that overflows, add carry to high. */ - bld.ADD(low, low, brw_imm_ud(v))->conditional_mod = BRW_CONDITIONAL_O; - bld.ADD(high, high, brw_imm_ud(0x1))->predicate = BRW_PREDICATE_NORMAL; + bld.ADD(low, low, elk_imm_ud(v))->conditional_mod = ELK_CONDITIONAL_O; + bld.ADD(high, high, elk_imm_ud(0x1))->predicate = ELK_PREDICATE_NORMAL; } } -static fs_reg -emit_fence(const fs_builder &bld, enum opcode opcode, +static elk_fs_reg +emit_fence(const fs_builder &bld, enum elk_opcode opcode, uint8_t sfid, uint32_t desc, bool commit_enable, uint8_t bti) { - assert(opcode == SHADER_OPCODE_INTERLOCK || - opcode == SHADER_OPCODE_MEMORY_FENCE); + assert(opcode == ELK_SHADER_OPCODE_INTERLOCK || + opcode == ELK_SHADER_OPCODE_MEMORY_FENCE); - fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD); - fs_inst *fence = bld.emit(opcode, dst, brw_vec8_grf(0, 0), - brw_imm_ud(commit_enable), - brw_imm_ud(bti)); + elk_fs_reg dst = bld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_inst *fence = bld.emit(opcode, dst, elk_vec8_grf(0, 0), + elk_imm_ud(commit_enable), + elk_imm_ud(bti)); fence->sfid = sfid; fence->desc = desc; @@ -5042,20 +5042,20 @@ lsc_fence_descriptor_for_intrinsic(const struct intel_device_info *devinfo, /** * Create a MOV to read the timestamp register. */ -static fs_reg +static elk_fs_reg get_timestamp(const fs_builder &bld) { - fs_visitor &s = *bld.shader; + elk_fs_visitor &s = *bld.shader; const intel_device_info *devinfo = s.devinfo; assert(devinfo->ver >= 7); - fs_reg ts = fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_TIMESTAMP, + elk_fs_reg ts = elk_fs_reg(retype(elk_vec4_reg(ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_TIMESTAMP, 0), - BRW_REGISTER_TYPE_UD)); + ELK_REGISTER_TYPE_UD)); - fs_reg dst = fs_reg(VGRF, s.alloc.allocate(1), BRW_REGISTER_TYPE_UD); + elk_fs_reg dst = elk_fs_reg(VGRF, s.alloc.allocate(1), ELK_REGISTER_TYPE_UD); /* We want to read the 3 fields we care about even if it's not enabled in * the dispatch. @@ -5066,21 +5066,21 @@ get_timestamp(const fs_builder &bld) } static void -fs_nir_emit_intrinsic(nir_to_brw_state &ntb, +fs_nir_emit_intrinsic(nir_to_elk_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; /* We handle this as a special case */ if (instr->intrinsic == nir_intrinsic_decl_reg) { assert(nir_intrinsic_num_array_elems(instr) == 0); unsigned bit_size = nir_intrinsic_bit_size(instr); unsigned num_components = nir_intrinsic_num_components(instr); - const brw_reg_type reg_type = - brw_reg_type_from_bit_size(bit_size, bit_size == 8 ? - BRW_REGISTER_TYPE_D : - BRW_REGISTER_TYPE_F); + const elk_reg_type reg_type = + elk_reg_type_from_bit_size(bit_size, bit_size == 8 ? + ELK_REGISTER_TYPE_D : + ELK_REGISTER_TYPE_F); /* Re-use the destination's slot in the table for the register */ ntb.ssa_values[instr->def.index] = @@ -5088,7 +5088,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, return; } - fs_reg dest; + elk_fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); @@ -5107,7 +5107,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, if (nir_intrinsic_resource_access_intel(instr) & nir_resource_intel_non_uniform) { - ntb.resource_values[instr->def.index] = fs_reg(); + ntb.resource_values[instr->def.index] = elk_fs_reg(); } else { ntb.resource_values[instr->def.index] = try_rebuild_resource(ntb, bld, instr->src[1].ssa); @@ -5132,7 +5132,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, /* Get some metadata from the image intrinsic. */ const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic]; - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; switch (instr->intrinsic) { case nir_intrinsic_image_load: @@ -5152,47 +5152,47 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(ntb, instr->src[1]); srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = - brw_imm_ud(nir_image_intrinsic_coord_components(instr)); + elk_imm_ud(nir_image_intrinsic_coord_components(instr)); /* Emit an image load, store or atomic op. */ if (instr->intrinsic == nir_intrinsic_image_load || instr->intrinsic == nir_intrinsic_bindless_image_load) { - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); - fs_inst *inst = - bld.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(instr->num_components); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(0); + elk_fs_inst *inst = + bld.emit(ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); inst->size_written = instr->num_components * s.dispatch_width * 4; } else if (instr->intrinsic == nir_intrinsic_image_store || instr->intrinsic == nir_intrinsic_bindless_image_store) { - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(instr->num_components); srcs[SURFACE_LOGICAL_SRC_DATA] = get_nir_src(ntb, instr->src[3]); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1); - bld.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(1); + bld.emit(ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); } else { unsigned num_srcs = info->num_srcs; - enum lsc_opcode op = lsc_aop_for_nir_intrinsic(instr); + enum elk_lsc_opcode op = elk_lsc_aop_for_nir_intrinsic(instr); if (op == LSC_OP_ATOMIC_INC || op == LSC_OP_ATOMIC_DEC) { assert(num_srcs == 4); num_srcs = 3; } - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(op); - fs_reg data; + elk_fs_reg data; if (num_srcs >= 4) data = get_nir_src(ntb, instr->src[3]); if (num_srcs >= 5) { - fs_reg tmp = bld.vgrf(data.type, 2); - fs_reg sources[2] = { data, get_nir_src(ntb, instr->src[4]) }; + elk_fs_reg tmp = bld.vgrf(data.type, 2); + elk_fs_reg sources[2] = { data, get_nir_src(ntb, instr->src[4]) }; bld.LOAD_PAYLOAD(tmp, sources, 2, 0); data = tmp; } srcs[SURFACE_LOGICAL_SRC_DATA] = data; - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(1); - bld.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, + bld.emit(ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); } break; @@ -5208,29 +5208,29 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * Incidentally, this means that we can handle bindless with exactly the * same code. */ - fs_reg image = retype(get_nir_src_imm(ntb, instr->src[0]), - BRW_REGISTER_TYPE_UD); + elk_fs_reg image = retype(get_nir_src_imm(ntb, instr->src[0]), + ELK_REGISTER_TYPE_UD); image = bld.emit_uniformize(image); assert(nir_src_as_uint(instr->src[1]) == 0); - fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; if (instr->intrinsic == nir_intrinsic_image_size) srcs[TEX_LOGICAL_SRC_SURFACE] = image; else srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE] = image; - srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_d(0); - srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(0); - srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0); - srcs[TEX_LOGICAL_SRC_RESIDENCY] = brw_imm_d(0); + srcs[TEX_LOGICAL_SRC_SAMPLER] = elk_imm_d(0); + srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = elk_imm_d(0); + srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = elk_imm_d(0); + srcs[TEX_LOGICAL_SRC_RESIDENCY] = elk_imm_d(0); /* Since the image size is always uniform, we can just emit a SIMD8 * query instruction and splat the result out. */ const fs_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0); - fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 4); - fs_inst *inst = ubld.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL, + elk_fs_reg tmp = ubld.vgrf(ELK_REGISTER_TYPE_UD, 4); + elk_fs_inst *inst = ubld.emit(ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); inst->size_written = 4 * REG_SIZE * reg_unit(devinfo); @@ -5242,33 +5242,33 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_image_load_raw_intel: { - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[SURFACE_LOGICAL_SRC_SURFACE] = get_nir_image_intrinsic_image(ntb, bld, instr); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(ntb, instr->src[1]); - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(instr->num_components); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(0); - fs_inst *inst = - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, + elk_fs_inst *inst = + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); inst->size_written = instr->num_components * s.dispatch_width * 4; break; } case nir_intrinsic_image_store_raw_intel: { - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[SURFACE_LOGICAL_SRC_SURFACE] = get_nir_image_intrinsic_image(ntb, bld, instr); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(ntb, instr->src[1]); srcs[SURFACE_LOGICAL_SRC_DATA] = get_nir_src(ntb, instr->src[2]); - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(instr->num_components); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(1); - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); break; } @@ -5276,7 +5276,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_begin_invocation_interlock: case nir_intrinsic_end_invocation_interlock: { bool ugm_fence, slm_fence, tgm_fence, urb_fence; - enum opcode opcode = BRW_OPCODE_NOP; + enum elk_opcode opcode = ELK_OPCODE_NOP; /* Handling interlock intrinsics here will allow the logic for IVB * render cache (see below) to be reused. @@ -5294,7 +5294,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, tgm_fence = modes & nir_var_image; urb_fence = modes & (nir_var_shader_out | nir_var_mem_task_payload); if (nir_intrinsic_memory_scope(instr) != SCOPE_NONE) - opcode = SHADER_OPCODE_MEMORY_FENCE; + opcode = ELK_SHADER_OPCODE_MEMORY_FENCE; break; } @@ -5306,7 +5306,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, assert(s.stage == MESA_SHADER_FRAGMENT); ugm_fence = tgm_fence = true; slm_fence = urb_fence = false; - opcode = SHADER_OPCODE_INTERLOCK; + opcode = ELK_SHADER_OPCODE_INTERLOCK; break; case nir_intrinsic_end_invocation_interlock: @@ -5322,14 +5322,14 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, assert(s.stage == MESA_SHADER_FRAGMENT); ugm_fence = tgm_fence = true; slm_fence = urb_fence = false; - opcode = SHADER_OPCODE_MEMORY_FENCE; + opcode = ELK_SHADER_OPCODE_MEMORY_FENCE; break; default: unreachable("invalid intrinsic"); } - if (opcode == BRW_OPCODE_NOP) + if (opcode == ELK_OPCODE_NOP) break; if (s.nir->info.shared_size > 0) { @@ -5357,7 +5357,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } unsigned fence_regs_count = 0; - fs_reg fence_regs[4] = {}; + elk_fs_reg fence_regs[4] = {}; const fs_builder ubld = bld.group(8, 0); @@ -5402,7 +5402,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, (!nir_intrinsic_has_memory_scope(instr) || (nir_intrinsic_memory_semantics(instr) & NIR_MEMORY_ACQUIRE))) { ubld.exec_all().group(1, 0).emit( - BRW_OPCODE_SYNC, ubld.null_reg_ud(), brw_imm_ud(TGL_SYNC_ALLWR)); + ELK_OPCODE_SYNC, ubld.null_reg_ud(), elk_imm_ud(TGL_SYNC_ALLWR)); } if (devinfo->has_lsc) { @@ -5424,7 +5424,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } if (slm_fence) { - assert(opcode == SHADER_OPCODE_MEMORY_FENCE); + assert(opcode == ELK_SHADER_OPCODE_MEMORY_FENCE); if (intel_needs_workaround(devinfo, 14014063774)) { /* Wa_14014063774 * @@ -5432,8 +5432,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * to avoid the SLM data race. */ ubld.exec_all().group(1, 0).emit( - BRW_OPCODE_SYNC, ubld.null_reg_ud(), - brw_imm_ud(TGL_SYNC_ALLWR)); + ELK_OPCODE_SYNC, ubld.null_reg_ud(), + elk_imm_ud(TGL_SYNC_ALLWR)); } fence_regs[fence_regs_count++] = emit_fence(ubld, opcode, GFX12_SFID_SLM, desc, @@ -5442,9 +5442,9 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } if (urb_fence) { - assert(opcode == SHADER_OPCODE_MEMORY_FENCE); + assert(opcode == ELK_SHADER_OPCODE_MEMORY_FENCE); fence_regs[fence_regs_count++] = - emit_fence(ubld, opcode, BRW_SFID_URB, desc, + emit_fence(ubld, opcode, ELK_SFID_URB, desc, true /* commit_enable */, 0 /* BTI; ignored for LSC */); } @@ -5457,7 +5457,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } if (slm_fence) { - assert(opcode == SHADER_OPCODE_MEMORY_FENCE); + assert(opcode == ELK_SHADER_OPCODE_MEMORY_FENCE); fence_regs[fence_regs_count++] = emit_fence(ubld, opcode, GFX7_SFID_DATAPORT_DATA_CACHE, 0, true /* commit_enable HSD ES # 1404612949 */, @@ -5523,7 +5523,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, if (instr->intrinsic == nir_intrinsic_end_invocation_interlock || fence_regs_count != 1 || devinfo->has_lsc || force_stall) { ubld.exec_all().group(1, 0).emit( - FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(), + ELK_FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(), fence_regs, fence_regs_count); } @@ -5532,8 +5532,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_shader_clock: { /* We cannot do anything if there is an event, so ignore it for now */ - const fs_reg shader_clock = get_timestamp(bld); - const fs_reg srcs[] = { component(shader_clock, 0), + const elk_fs_reg shader_clock = get_timestamp(bld); + const elk_fs_reg srcs[] = { component(shader_clock, 0), component(shader_clock, 1) }; bld.LOAD_PAYLOAD(dest, srcs, ARRAY_SIZE(srcs), 0); break; @@ -5544,10 +5544,10 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, /* Emit the reloc in the smallest SIMD size to limit register usage. */ const fs_builder ubld = bld.exec_all().group(1, 0); - fs_reg small_dest = ubld.vgrf(dest.type); + elk_fs_reg small_dest = ubld.vgrf(dest.type); ubld.UNDEF(small_dest); - ubld.exec_all().group(1, 0).emit(SHADER_OPCODE_MOV_RELOC_IMM, - small_dest, brw_imm_ud(id)); + ubld.exec_all().group(1, 0).emit(ELK_SHADER_OPCODE_MOV_RELOC_IMM, + small_dest, elk_imm_ud(id)); /* Copy propagation will get rid of this MOV. */ bld.MOV(dest, component(small_dest, 0)); @@ -5561,7 +5561,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, unsigned base_offset = nir_intrinsic_base(instr); assert(base_offset % 4 == 0 || base_offset % type_sz(dest.type) == 0); - fs_reg src(UNIFORM, base_offset / 4, dest.type); + elk_fs_reg src(UNIFORM, base_offset / 4, dest.type); if (nir_src_is_const(instr->src[0])) { unsigned load_offset = nir_src_as_uint(instr->src[0]); @@ -5576,8 +5576,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, bld.MOV(offset(dest, bld, j), offset(src, bld, j)); } } else { - fs_reg indirect = retype(get_nir_src(ntb, instr->src[0]), - BRW_REGISTER_TYPE_UD); + elk_fs_reg indirect = retype(get_nir_src(ntb, instr->src[0]), + ELK_REGISTER_TYPE_UD); /* We need to pass a size to the MOV_INDIRECT but we don't want it to * go past the end of the uniform. In order to keep the n'th @@ -5594,24 +5594,24 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, if (type_sz(dest.type) != 8 || supports_64bit_indirects) { for (unsigned j = 0; j < instr->num_components; j++) { - bld.emit(SHADER_OPCODE_MOV_INDIRECT, + bld.emit(ELK_SHADER_OPCODE_MOV_INDIRECT, offset(dest, bld, j), offset(src, bld, j), - indirect, brw_imm_ud(read_size)); + indirect, elk_imm_ud(read_size)); } } else { const unsigned num_mov_indirects = - type_sz(dest.type) / type_sz(BRW_REGISTER_TYPE_UD); + type_sz(dest.type) / type_sz(ELK_REGISTER_TYPE_UD); /* We read a little bit less per MOV INDIRECT, as they are now * 32-bits ones instead of 64-bit. Fix read_size then. */ const unsigned read_size_32bit = read_size - - (num_mov_indirects - 1) * type_sz(BRW_REGISTER_TYPE_UD); + (num_mov_indirects - 1) * type_sz(ELK_REGISTER_TYPE_UD); for (unsigned j = 0; j < instr->num_components; j++) { for (unsigned i = 0; i < num_mov_indirects; i++) { - bld.emit(SHADER_OPCODE_MOV_INDIRECT, - subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, i), - subscript(offset(src, bld, j), BRW_REGISTER_TYPE_UD, i), - indirect, brw_imm_ud(read_size_32bit)); + bld.emit(ELK_SHADER_OPCODE_MOV_INDIRECT, + subscript(offset(dest, bld, j), ELK_REGISTER_TYPE_UD, i), + subscript(offset(src, bld, j), ELK_REGISTER_TYPE_UD, i), + indirect, elk_imm_ud(read_size_32bit)); } } } @@ -5621,7 +5621,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_ubo: case nir_intrinsic_load_ubo_uniform_block_intel: { - fs_reg surface, surface_handle; + elk_fs_reg surface, surface_handle; if (get_nir_src_bindless(ntb, instr->src[0])) surface_handle = get_nir_buffer_intrinsic_index(ntb, bld, instr); @@ -5631,8 +5631,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, if (!nir_src_is_const(instr->src[1])) { if (instr->intrinsic == nir_intrinsic_load_ubo) { /* load_ubo with non-uniform offset */ - fs_reg base_offset = retype(get_nir_src(ntb, instr->src[1]), - BRW_REGISTER_TYPE_UD); + elk_fs_reg base_offset = retype(get_nir_src(ntb, instr->src[1]), + ELK_REGISTER_TYPE_UD); const unsigned comps_per_load = type_sz(dest.type) == 8 ? 2 : 4; @@ -5653,15 +5653,15 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const fs_builder ubld8 = bld.exec_all().group(8, 0); const fs_builder ubld16 = bld.exec_all().group(16, 0); - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[SURFACE_LOGICAL_SRC_SURFACE] = surface; srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = surface_handle; const nir_src load_offset = instr->src[1]; if (nir_src_is_const(load_offset)) { - fs_reg addr = ubld8.vgrf(BRW_REGISTER_TYPE_UD); - ubld8.MOV(addr, brw_imm_ud(nir_src_as_uint(load_offset))); + elk_fs_reg addr = ubld8.vgrf(ELK_REGISTER_TYPE_UD); + ubld8.MOV(addr, elk_imm_ud(nir_src_as_uint(load_offset))); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = component(addr, 0); } else { srcs[SURFACE_LOGICAL_SRC_ADDRESS] = @@ -5672,8 +5672,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, ALIGN(instr->num_components, REG_SIZE * reg_unit(devinfo) / 4); unsigned loaded_dwords = 0; - const fs_reg packed_consts = - ubld1.vgrf(BRW_REGISTER_TYPE_UD, total_dwords); + const elk_fs_reg packed_consts = + ubld1.vgrf(ELK_REGISTER_TYPE_UD, total_dwords); while (loaded_dwords < total_dwords) { const unsigned block = @@ -5681,11 +5681,11 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, total_dwords - loaded_dwords); const unsigned block_bytes = block * 4; - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(block); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(block); const fs_builder &ubld = block <= 8 ? ubld8 : ubld16; - ubld.emit(SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, - retype(byte_offset(packed_consts, loaded_dwords * 4), BRW_REGISTER_TYPE_UD), + ubld.emit(ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, + retype(byte_offset(packed_consts, loaded_dwords * 4), ELK_REGISTER_TYPE_UD), srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written = align(block_bytes, REG_SIZE * reg_unit(devinfo)); @@ -5693,11 +5693,11 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, ubld1.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS], srcs[SURFACE_LOGICAL_SRC_ADDRESS], - brw_imm_ud(block_bytes)); + elk_imm_ud(block_bytes)); } for (unsigned c = 0; c < instr->num_components; c++) { - bld.MOV(retype(offset(dest, bld, c), BRW_REGISTER_TYPE_UD), + bld.MOV(retype(offset(dest, bld, c), ELK_REGISTER_TYPE_UD), component(packed_consts, c)); } @@ -5715,20 +5715,20 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const unsigned type_size = type_sz(dest.type); const unsigned load_offset = nir_src_as_uint(instr->src[1]); const unsigned ubo_block = - brw_nir_ubo_surface_index_get_push_block(instr->src[0]); + elk_nir_ubo_surface_index_get_push_block(instr->src[0]); const unsigned offset_256b = load_offset / 32; const unsigned end_256b = DIV_ROUND_UP(load_offset + type_size * instr->num_components, 32); /* See if we've selected this as a push constant candidate */ - fs_reg push_reg; + elk_fs_reg push_reg; for (int i = 0; i < 4; i++) { - const struct brw_ubo_range *range = &s.prog_data->ubo_ranges[i]; + const struct elk_ubo_range *range = &s.prog_data->ubo_ranges[i]; if (range->block == ubo_block && offset_256b >= range->start && end_256b <= range->start + range->length) { - push_reg = fs_reg(UNIFORM, UBO_START + i, dest.type); + push_reg = elk_fs_reg(UNIFORM, UBO_START + i, dest.type); push_reg.offset = load_offset - 32 * range->start; break; } @@ -5753,17 +5753,17 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const unsigned count = MIN2(instr->num_components - c, (block_sz - base % block_sz) / type_size); - const fs_reg packed_consts = ubld.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg srcs[PULL_UNIFORM_CONSTANT_SRCS]; + const elk_fs_reg packed_consts = ubld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg srcs[PULL_UNIFORM_CONSTANT_SRCS]; srcs[PULL_UNIFORM_CONSTANT_SRC_SURFACE] = surface; srcs[PULL_UNIFORM_CONSTANT_SRC_SURFACE_HANDLE] = surface_handle; - srcs[PULL_UNIFORM_CONSTANT_SRC_OFFSET] = brw_imm_ud(base & ~(block_sz - 1)); - srcs[PULL_UNIFORM_CONSTANT_SRC_SIZE] = brw_imm_ud(block_sz); + srcs[PULL_UNIFORM_CONSTANT_SRC_OFFSET] = elk_imm_ud(base & ~(block_sz - 1)); + srcs[PULL_UNIFORM_CONSTANT_SRC_SIZE] = elk_imm_ud(block_sz); - ubld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts, + ubld.emit(ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts, srcs, PULL_UNIFORM_CONSTANT_SRCS); - const fs_reg consts = + const elk_fs_reg consts = retype(byte_offset(packed_consts, base & (block_sz - 1)), dest.type); @@ -5782,31 +5782,31 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, assert(instr->def.bit_size <= 32); assert(nir_intrinsic_align(instr) > 0); - fs_reg srcs[A64_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[A64_LOGICAL_NUM_SRCS]; srcs[A64_LOGICAL_ADDRESS] = get_nir_src(ntb, instr->src[0]); - srcs[A64_LOGICAL_SRC] = fs_reg(); /* No source data */ + srcs[A64_LOGICAL_SRC] = elk_fs_reg(); /* No source data */ srcs[A64_LOGICAL_ENABLE_HELPERS] = - brw_imm_ud(nir_intrinsic_access(instr) & ACCESS_INCLUDE_HELPERS); + elk_imm_ud(nir_intrinsic_access(instr) & ACCESS_INCLUDE_HELPERS); if (instr->def.bit_size == 32 && nir_intrinsic_align(instr) >= 4) { assert(instr->def.num_components <= 4); - srcs[A64_LOGICAL_ARG] = brw_imm_ud(instr->num_components); + srcs[A64_LOGICAL_ARG] = elk_imm_ud(instr->num_components); - fs_inst *inst = - bld.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL, dest, + elk_fs_inst *inst = + bld.emit(ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL, dest, srcs, A64_LOGICAL_NUM_SRCS); inst->size_written = instr->num_components * inst->dst.component_size(inst->exec_size); } else { const unsigned bit_size = instr->def.bit_size; assert(instr->def.num_components == 1); - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD); - srcs[A64_LOGICAL_ARG] = brw_imm_ud(bit_size); + srcs[A64_LOGICAL_ARG] = elk_imm_ud(bit_size); - bld.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL, tmp, + bld.emit(ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL, tmp, srcs, A64_LOGICAL_NUM_SRCS); bld.MOV(dest, subscript(tmp, dest.type, 0)); } @@ -5821,32 +5821,32 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, (1u << instr->num_components) - 1); assert(nir_intrinsic_align(instr) > 0); - fs_reg srcs[A64_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[A64_LOGICAL_NUM_SRCS]; srcs[A64_LOGICAL_ADDRESS] = get_nir_src(ntb, instr->src[1]); srcs[A64_LOGICAL_ENABLE_HELPERS] = - brw_imm_ud(nir_intrinsic_access(instr) & ACCESS_INCLUDE_HELPERS); + elk_imm_ud(nir_intrinsic_access(instr) & ACCESS_INCLUDE_HELPERS); if (nir_src_bit_size(instr->src[0]) == 32 && nir_intrinsic_align(instr) >= 4) { assert(nir_src_num_components(instr->src[0]) <= 4); srcs[A64_LOGICAL_SRC] = get_nir_src(ntb, instr->src[0]); /* Data */ - srcs[A64_LOGICAL_ARG] = brw_imm_ud(instr->num_components); + srcs[A64_LOGICAL_ARG] = elk_imm_ud(instr->num_components); - bld.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL, fs_reg(), + bld.emit(ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL, elk_fs_reg(), srcs, A64_LOGICAL_NUM_SRCS); } else { assert(nir_src_num_components(instr->src[0]) == 1); const unsigned bit_size = nir_src_bit_size(instr->src[0]); - brw_reg_type data_type = - brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD); - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); + elk_reg_type data_type = + elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_UD); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD); bld.MOV(tmp, retype(get_nir_src(ntb, instr->src[0]), data_type)); srcs[A64_LOGICAL_SRC] = tmp; - srcs[A64_LOGICAL_ARG] = brw_imm_ud(bit_size); + srcs[A64_LOGICAL_ARG] = elk_imm_ud(bit_size); - bld.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL, fs_reg(), + bld.emit(ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL, elk_fs_reg(), srcs, A64_LOGICAL_NUM_SRCS); } break; @@ -5862,48 +5862,48 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, assert(instr->num_components == 8 || instr->num_components == 16); const fs_builder ubld = bld.exec_all().group(instr->num_components, 0); - fs_reg load_val; + elk_fs_reg load_val; bool is_pred_const = nir_src_is_const(instr->src[1]); if (is_pred_const && nir_src_as_uint(instr->src[1]) == 0) { /* In this case, we don't want the UBO load at all. We really * shouldn't get here but it's possible. */ - load_val = brw_imm_ud(0); + load_val = elk_imm_ud(0); } else { /* The uniform process may stomp the flag so do this first */ - fs_reg addr = bld.emit_uniformize(get_nir_src(ntb, instr->src[0])); + elk_fs_reg addr = bld.emit_uniformize(get_nir_src(ntb, instr->src[0])); - load_val = ubld.vgrf(BRW_REGISTER_TYPE_UD); + load_val = ubld.vgrf(ELK_REGISTER_TYPE_UD); /* If the predicate is constant and we got here, then it's non-zero * and we don't need the predicate at all. */ if (!is_pred_const) { /* Load the predicate */ - fs_reg pred = bld.emit_uniformize(get_nir_src(ntb, instr->src[1])); - fs_inst *mov = ubld.MOV(bld.null_reg_d(), pred); - mov->conditional_mod = BRW_CONDITIONAL_NZ; + elk_fs_reg pred = bld.emit_uniformize(get_nir_src(ntb, instr->src[1])); + elk_fs_inst *mov = ubld.MOV(bld.null_reg_d(), pred); + mov->conditional_mod = ELK_CONDITIONAL_NZ; /* Stomp the destination with 0 if we're OOB */ - mov = ubld.MOV(load_val, brw_imm_ud(0)); - mov->predicate = BRW_PREDICATE_NORMAL; + mov = ubld.MOV(load_val, elk_imm_ud(0)); + mov->predicate = ELK_PREDICATE_NORMAL; mov->predicate_inverse = true; } - fs_reg srcs[A64_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[A64_LOGICAL_NUM_SRCS]; srcs[A64_LOGICAL_ADDRESS] = addr; - srcs[A64_LOGICAL_SRC] = fs_reg(); /* No source data */ - srcs[A64_LOGICAL_ARG] = brw_imm_ud(instr->num_components); + srcs[A64_LOGICAL_SRC] = elk_fs_reg(); /* No source data */ + srcs[A64_LOGICAL_ARG] = elk_imm_ud(instr->num_components); /* This intrinsic loads memory from a uniform address, sometimes * shared across lanes. We never need to mask it. */ - srcs[A64_LOGICAL_ENABLE_HELPERS] = brw_imm_ud(0); + srcs[A64_LOGICAL_ENABLE_HELPERS] = elk_imm_ud(0); - fs_inst *load = ubld.emit(SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL, + elk_fs_inst *load = ubld.emit(ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL, load_val, srcs, A64_LOGICAL_NUM_SRCS); if (!is_pred_const) - load->predicate = BRW_PREDICATE_NORMAL; + load->predicate = ELK_PREDICATE_NORMAL; } /* From the HW perspective, we just did a single SIMD16 instruction @@ -5914,7 +5914,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * will generally clean them up for us. */ for (unsigned i = 0; i < instr->num_components; i++) { - bld.MOV(retype(offset(dest, bld, i), BRW_REGISTER_TYPE_UD), + bld.MOV(retype(offset(dest, bld, i), ELK_REGISTER_TYPE_UD), component(load_val, i)); } break; @@ -5929,9 +5929,9 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const fs_builder ubld8 = bld.exec_all().group(8, 0); const fs_builder ubld16 = bld.exec_all().group(16, 0); - const fs_reg packed_consts = - ubld1.vgrf(BRW_REGISTER_TYPE_UD, total_dwords); - fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[0])); + const elk_fs_reg packed_consts = + ubld1.vgrf(ELK_REGISTER_TYPE_UD, total_dwords); + elk_fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[0])); while (loaded_dwords < total_dwords) { const unsigned block = @@ -5941,13 +5941,13 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const fs_builder &ubld = block <= 8 ? ubld8 : ubld16; - fs_reg srcs[A64_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[A64_LOGICAL_NUM_SRCS]; srcs[A64_LOGICAL_ADDRESS] = address; - srcs[A64_LOGICAL_SRC] = fs_reg(); /* No source data */ - srcs[A64_LOGICAL_ARG] = brw_imm_ud(block); - srcs[A64_LOGICAL_ENABLE_HELPERS] = brw_imm_ud(0); - ubld.emit(SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, - retype(byte_offset(packed_consts, loaded_dwords * 4), BRW_REGISTER_TYPE_UD), + srcs[A64_LOGICAL_SRC] = elk_fs_reg(); /* No source data */ + srcs[A64_LOGICAL_ARG] = elk_imm_ud(block); + srcs[A64_LOGICAL_ENABLE_HELPERS] = elk_imm_ud(0); + ubld.emit(ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, + retype(byte_offset(packed_consts, loaded_dwords * 4), ELK_REGISTER_TYPE_UD), srcs, A64_LOGICAL_NUM_SRCS)->size_written = align(block_bytes, REG_SIZE * reg_unit(devinfo)); @@ -5956,7 +5956,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } for (unsigned c = 0; c < instr->num_components; c++) - bld.MOV(retype(offset(dest, bld, c), BRW_REGISTER_TYPE_UD), + bld.MOV(retype(offset(dest, bld, c), ELK_REGISTER_TYPE_UD), component(packed_consts, c)); break; @@ -5966,17 +5966,17 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, assert(devinfo->ver >= 7); const unsigned bit_size = instr->def.bit_size; - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[get_nir_src_bindless(ntb, instr->src[0]) ? SURFACE_LOGICAL_SRC_SURFACE_HANDLE : SURFACE_LOGICAL_SRC_SURFACE] = get_nir_buffer_intrinsic_index(ntb, bld, instr); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(ntb, instr->src[1]); - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(0); /* Make dest unsigned because that's what the temporary will be */ - dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD); + dest.type = elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_UD); /* Read the vector */ assert(bit_size <= 32); @@ -5984,17 +5984,17 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, if (bit_size == 32 && nir_intrinsic_align(instr) >= 4) { assert(instr->def.num_components <= 4); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components); - fs_inst *inst = - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(instr->num_components); + elk_fs_inst *inst = + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); inst->size_written = instr->num_components * s.dispatch_width * 4; } else { assert(instr->def.num_components == 1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(bit_size); - fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, + elk_fs_reg read_result = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.emit(ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, read_result, srcs, SURFACE_LOGICAL_NUM_SRCS); bld.MOV(dest, subscript(read_result, dest.type, 0)); } @@ -6005,17 +6005,17 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, assert(devinfo->ver >= 7); const unsigned bit_size = nir_src_bit_size(instr->src[0]); - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[get_nir_src_bindless(ntb, instr->src[1]) ? SURFACE_LOGICAL_SRC_SURFACE_HANDLE : SURFACE_LOGICAL_SRC_SURFACE] = get_nir_buffer_intrinsic_index(ntb, bld, instr); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(ntb, instr->src[2]); - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(1); - fs_reg data = get_nir_src(ntb, instr->src[0]); - data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD); + elk_fs_reg data = get_nir_src(ntb, instr->src[0]); + data.type = elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_UD); assert(bit_size <= 32); assert(nir_intrinsic_write_mask(instr) == @@ -6025,25 +6025,25 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_align(instr) >= 4) { assert(nir_src_num_components(instr->src[0]) <= 4); srcs[SURFACE_LOGICAL_SRC_DATA] = data; - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components); - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(instr->num_components); + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); } else { assert(nir_src_num_components(instr->src[0]) == 1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(bit_size); - srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD); + srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(ELK_REGISTER_TYPE_UD); bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data); - bld.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + bld.emit(ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); } break; } case nir_intrinsic_load_ssbo_uniform_block_intel: case nir_intrinsic_load_shared_uniform_block_intel: { - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; const bool is_ssbo = instr->intrinsic == nir_intrinsic_load_ssbo_uniform_block_intel; @@ -6053,7 +6053,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, SURFACE_LOGICAL_SRC_SURFACE] = get_nir_buffer_intrinsic_index(ntb, bld, instr); } else { - srcs[SURFACE_LOGICAL_SRC_SURFACE] = fs_reg(brw_imm_ud(GFX7_BTI_SLM)); + srcs[SURFACE_LOGICAL_SRC_SURFACE] = elk_fs_reg(elk_imm_ud(GFX7_BTI_SLM)); } const unsigned total_dwords = ALIGN(instr->num_components, @@ -6064,13 +6064,13 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const fs_builder ubld8 = bld.exec_all().group(8, 0); const fs_builder ubld16 = bld.exec_all().group(16, 0); - const fs_reg packed_consts = - ubld1.vgrf(BRW_REGISTER_TYPE_UD, total_dwords); + const elk_fs_reg packed_consts = + ubld1.vgrf(ELK_REGISTER_TYPE_UD, total_dwords); const nir_src load_offset = is_ssbo ? instr->src[1] : instr->src[0]; if (nir_src_is_const(load_offset)) { - fs_reg addr = ubld8.vgrf(BRW_REGISTER_TYPE_UD); - ubld8.MOV(addr, brw_imm_ud(nir_src_as_uint(load_offset))); + elk_fs_reg addr = ubld8.vgrf(ELK_REGISTER_TYPE_UD); + ubld8.MOV(addr, elk_imm_ud(nir_src_as_uint(load_offset))); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = component(addr, 0); } else { srcs[SURFACE_LOGICAL_SRC_ADDRESS] = @@ -6083,11 +6083,11 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, total_dwords - loaded_dwords); const unsigned block_bytes = block * 4; - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(block); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(block); const fs_builder &ubld = block <= 8 ? ubld8 : ubld16; - ubld.emit(SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, - retype(byte_offset(packed_consts, loaded_dwords * 4), BRW_REGISTER_TYPE_UD), + ubld.emit(ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, + retype(byte_offset(packed_consts, loaded_dwords * 4), ELK_REGISTER_TYPE_UD), srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written = align(block_bytes, REG_SIZE * reg_unit(devinfo)); @@ -6095,11 +6095,11 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, ubld1.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS], srcs[SURFACE_LOGICAL_SRC_ADDRESS], - brw_imm_ud(block_bytes)); + elk_imm_ud(block_bytes)); } for (unsigned c = 0; c < instr->num_components; c++) - bld.MOV(retype(offset(dest, bld, c), BRW_REGISTER_TYPE_UD), + bld.MOV(retype(offset(dest, bld, c), ELK_REGISTER_TYPE_UD), component(packed_consts, c)); break; @@ -6107,13 +6107,13 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_store_output: { assert(nir_src_bit_size(instr->src[0]) == 32); - fs_reg src = get_nir_src(ntb, instr->src[0]); + elk_fs_reg src = get_nir_src(ntb, instr->src[0]); unsigned store_offset = nir_src_as_uint(instr->src[1]); unsigned num_components = instr->num_components; unsigned first_component = nir_intrinsic_component(instr); - fs_reg new_dest = retype(offset(s.outputs[instr->const_index[0]], bld, + elk_fs_reg new_dest = retype(offset(s.outputs[instr->const_index[0]], bld, 4 * store_offset), src.type); for (unsigned j = 0; j < num_components; j++) { bld.MOV(offset(new_dest, bld, j + first_component), @@ -6141,19 +6141,19 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * the dispatch width. */ const fs_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0); - fs_reg src_payload = ubld.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg ret_payload = ubld.vgrf(BRW_REGISTER_TYPE_UD, 4); + elk_fs_reg src_payload = ubld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg ret_payload = ubld.vgrf(ELK_REGISTER_TYPE_UD, 4); /* Set LOD = 0 */ - ubld.MOV(src_payload, brw_imm_d(0)); + ubld.MOV(src_payload, elk_imm_d(0)); - fs_reg srcs[GET_BUFFER_SIZE_SRCS]; + elk_fs_reg srcs[GET_BUFFER_SIZE_SRCS]; srcs[get_nir_src_bindless(ntb, instr->src[0]) ? GET_BUFFER_SIZE_SRC_SURFACE_HANDLE : GET_BUFFER_SIZE_SRC_SURFACE] = get_nir_buffer_intrinsic_index(ntb, bld, instr); srcs[GET_BUFFER_SIZE_SRC_LOD] = src_payload; - fs_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload, + elk_fs_inst *inst = ubld.emit(ELK_SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload, srcs, GET_BUFFER_SIZE_SRCS); inst->header_size = 0; inst->mlen = reg_unit(devinfo); @@ -6179,12 +6179,12 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * buffer_size = surface_size & ~3 - surface_size & 3 */ - fs_reg size_aligned4 = ubld.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg size_padding = ubld.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg buffer_size = ubld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg size_aligned4 = ubld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg size_padding = ubld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg buffer_size = ubld.vgrf(ELK_REGISTER_TYPE_UD); - ubld.AND(size_padding, ret_payload, brw_imm_ud(3)); - ubld.AND(size_aligned4, ret_payload, brw_imm_ud(~3)); + ubld.AND(size_padding, ret_payload, elk_imm_ud(3)); + ubld.AND(size_aligned4, ret_payload, elk_imm_ud(~3)); ubld.ADD(buffer_size, size_aligned4, negate(size_padding)); bld.MOV(retype(dest, ret_payload.type), component(buffer_size, 0)); @@ -6196,29 +6196,29 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, assert(instr->def.num_components == 1); const unsigned bit_size = instr->def.bit_size; - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; if (devinfo->verx10 >= 125) { const fs_builder ubld = bld.exec_all().group(1, 0); - fs_reg handle = component(ubld.vgrf(BRW_REGISTER_TYPE_UD), 0); - ubld.AND(handle, retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(31, 10))); - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS); + elk_fs_reg handle = component(ubld.vgrf(ELK_REGISTER_TYPE_UD), 0); + ubld.AND(handle, retype(elk_vec1_grf(0, 5), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(31, 10))); + srcs[SURFACE_LOGICAL_SRC_SURFACE] = elk_imm_ud(GFX125_NON_BINDLESS); srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle; } else if (devinfo->ver >= 8) { srcs[SURFACE_LOGICAL_SRC_SURFACE] = - brw_imm_ud(GFX8_BTI_STATELESS_NON_COHERENT); + elk_imm_ud(GFX8_BTI_STATELESS_NON_COHERENT); } else { - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(BRW_BTI_STATELESS); + srcs[SURFACE_LOGICAL_SRC_SURFACE] = elk_imm_ud(ELK_BTI_STATELESS); } - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); - const fs_reg nir_addr = get_nir_src(ntb, instr->src[0]); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(bit_size); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(0); + const elk_fs_reg nir_addr = get_nir_src(ntb, instr->src[0]); /* Make dest unsigned because that's what the temporary will be */ - dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD); + dest.type = elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_UD); /* Read the vector */ assert(instr->def.num_components == 1); @@ -6232,24 +6232,24 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, srcs[SURFACE_LOGICAL_SRC_ADDRESS] = swizzle_nir_scratch_addr(ntb, bld, nir_addr, false); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(1); - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); } else { /* The offset for a DWORD scattered message is in dwords. */ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = swizzle_nir_scratch_addr(ntb, bld, nir_addr, true); - bld.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, + bld.emit(ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); } } else { srcs[SURFACE_LOGICAL_SRC_ADDRESS] = swizzle_nir_scratch_addr(ntb, bld, nir_addr, false); - fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, + elk_fs_reg read_result = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.emit(ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, read_result, srcs, SURFACE_LOGICAL_NUM_SRCS); bld.MOV(dest, read_result); } @@ -6263,24 +6263,24 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, assert(nir_src_num_components(instr->src[0]) == 1); const unsigned bit_size = nir_src_bit_size(instr->src[0]); - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; if (devinfo->verx10 >= 125) { const fs_builder ubld = bld.exec_all().group(1, 0); - fs_reg handle = component(ubld.vgrf(BRW_REGISTER_TYPE_UD), 0); - ubld.AND(handle, retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(31, 10))); - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS); + elk_fs_reg handle = component(ubld.vgrf(ELK_REGISTER_TYPE_UD), 0); + ubld.AND(handle, retype(elk_vec1_grf(0, 5), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(31, 10))); + srcs[SURFACE_LOGICAL_SRC_SURFACE] = elk_imm_ud(GFX125_NON_BINDLESS); srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle; } else if (devinfo->ver >= 8) { srcs[SURFACE_LOGICAL_SRC_SURFACE] = - brw_imm_ud(GFX8_BTI_STATELESS_NON_COHERENT); + elk_imm_ud(GFX8_BTI_STATELESS_NON_COHERENT); } else { - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(BRW_BTI_STATELESS); + srcs[SURFACE_LOGICAL_SRC_SURFACE] = elk_imm_ud(ELK_BTI_STATELESS); } - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(bit_size); /** * While this instruction has side-effects, it should not be predicated * on sample mask, because otherwise fs helper invocations would @@ -6288,11 +6288,11 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * load-stores are produced from operations without side-effects, thus * they should not have different behaviour in the helper invocations. */ - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); - const fs_reg nir_addr = get_nir_src(ntb, instr->src[1]); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(0); + const elk_fs_reg nir_addr = get_nir_src(ntb, instr->src[1]); - fs_reg data = get_nir_src(ntb, instr->src[0]); - data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD); + elk_fs_reg data = get_nir_src(ntb, instr->src[0]); + data.type = elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_UD); assert(nir_src_num_components(instr->src[0]) == 1); assert(bit_size <= 32); @@ -6305,9 +6305,9 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, srcs[SURFACE_LOGICAL_SRC_ADDRESS] = swizzle_nir_scratch_addr(ntb, bld, nir_addr, false); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(1); - bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, + bld.emit(ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); } else { srcs[SURFACE_LOGICAL_SRC_DATA] = data; @@ -6316,18 +6316,18 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, srcs[SURFACE_LOGICAL_SRC_ADDRESS] = swizzle_nir_scratch_addr(ntb, bld, nir_addr, true); - bld.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + bld.emit(ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); } } else { - srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD); + srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(ELK_REGISTER_TYPE_UD); bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = swizzle_nir_scratch_addr(ntb, bld, nir_addr, false); - bld.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + bld.emit(ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); } s.shader_stats.spill_count += DIV_ROUND_UP(s.dispatch_width, 16); break; @@ -6338,11 +6338,11 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * is lowered in NIR so we can optimize on it. */ assert(s.stage == MESA_SHADER_FRAGMENT); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(s.dispatch_width)); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_D), elk_imm_d(s.dispatch_width)); break; case nir_intrinsic_load_subgroup_invocation: - bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), + bld.MOV(retype(dest, ELK_REGISTER_TYPE_D), ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]); break; @@ -6362,12 +6362,12 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, */ if (s.dispatch_width == 32) { /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */ - ubld1.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD), - brw_imm_ud(0)); + ubld1.MOV(retype(elk_flag_reg(0, 0), ELK_REGISTER_TYPE_UD), + elk_imm_ud(0)); } else { - ubld1.MOV(brw_flag_reg(0, 0), brw_imm_uw(0)); + ubld1.MOV(elk_flag_reg(0, 0), elk_imm_uw(0)); } - bld.CMP(bld.null_reg_d(), get_nir_src(ntb, instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_d(), get_nir_src(ntb, instr->src[0]), elk_imm_d(0), ELK_CONDITIONAL_NZ); /* For some reason, the any/all predicates don't work properly with * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H @@ -6376,15 +6376,15 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * of 1-wide MOVs and scattering the result. */ const fs_builder ubld = devinfo->ver >= 20 ? bld.exec_all() : ubld1; - fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D); - ubld.MOV(res1, brw_imm_d(0)); + elk_fs_reg res1 = ubld.vgrf(ELK_REGISTER_TYPE_D); + ubld.MOV(res1, elk_imm_d(0)); set_predicate(devinfo->ver >= 20 ? XE2_PREDICATE_ANY : - s.dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ANY8H : - s.dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ANY16H : - BRW_PREDICATE_ALIGN1_ANY32H, - ubld.MOV(res1, brw_imm_d(-1))); + s.dispatch_width == 8 ? ELK_PREDICATE_ALIGN1_ANY8H : + s.dispatch_width == 16 ? ELK_PREDICATE_ALIGN1_ANY16H : + ELK_PREDICATE_ALIGN1_ANY32H, + ubld.MOV(res1, elk_imm_d(-1))); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0)); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_D), component(res1, 0)); break; } case nir_intrinsic_vote_all: { @@ -6396,12 +6396,12 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, */ if (s.dispatch_width == 32) { /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */ - ubld1.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD), - brw_imm_ud(0xffffffff)); + ubld1.MOV(retype(elk_flag_reg(0, 0), ELK_REGISTER_TYPE_UD), + elk_imm_ud(0xffffffff)); } else { - ubld1.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff)); + ubld1.MOV(elk_flag_reg(0, 0), elk_imm_uw(0xffff)); } - bld.CMP(bld.null_reg_d(), get_nir_src(ntb, instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_d(), get_nir_src(ntb, instr->src[0]), elk_imm_d(0), ELK_CONDITIONAL_NZ); /* For some reason, the any/all predicates don't work properly with * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H @@ -6410,27 +6410,27 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * of 1-wide MOVs and scattering the result. */ const fs_builder ubld = devinfo->ver >= 20 ? bld.exec_all() : ubld1; - fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D); - ubld.MOV(res1, brw_imm_d(0)); + elk_fs_reg res1 = ubld.vgrf(ELK_REGISTER_TYPE_D); + ubld.MOV(res1, elk_imm_d(0)); set_predicate(devinfo->ver >= 20 ? XE2_PREDICATE_ALL : - s.dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H : - s.dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H : - BRW_PREDICATE_ALIGN1_ALL32H, - ubld.MOV(res1, brw_imm_d(-1))); + s.dispatch_width == 8 ? ELK_PREDICATE_ALIGN1_ALL8H : + s.dispatch_width == 16 ? ELK_PREDICATE_ALIGN1_ALL16H : + ELK_PREDICATE_ALIGN1_ALL32H, + ubld.MOV(res1, elk_imm_d(-1))); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0)); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_D), component(res1, 0)); break; } case nir_intrinsic_vote_feq: case nir_intrinsic_vote_ieq: { - fs_reg value = get_nir_src(ntb, instr->src[0]); + elk_fs_reg value = get_nir_src(ntb, instr->src[0]); if (instr->intrinsic == nir_intrinsic_vote_feq) { const unsigned bit_size = nir_src_bit_size(instr->src[0]); - value.type = bit_size == 8 ? BRW_REGISTER_TYPE_B : - brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_F); + value.type = bit_size == 8 ? ELK_REGISTER_TYPE_B : + elk_reg_type_from_bit_size(bit_size, ELK_REGISTER_TYPE_F); } - fs_reg uniformized = bld.emit_uniformize(value); + elk_fs_reg uniformized = bld.emit_uniformize(value); const fs_builder ubld1 = bld.exec_all().group(1, 0); /* The any/all predicates do not consider channel enables. To prevent @@ -6439,12 +6439,12 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, */ if (s.dispatch_width == 32) { /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */ - ubld1.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD), - brw_imm_ud(0xffffffff)); + ubld1.MOV(retype(elk_flag_reg(0, 0), ELK_REGISTER_TYPE_UD), + elk_imm_ud(0xffffffff)); } else { - ubld1.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff)); + ubld1.MOV(elk_flag_reg(0, 0), elk_imm_uw(0xffff)); } - bld.CMP(bld.null_reg_d(), value, uniformized, BRW_CONDITIONAL_Z); + bld.CMP(bld.null_reg_d(), value, uniformized, ELK_CONDITIONAL_Z); /* For some reason, the any/all predicates don't work properly with * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H @@ -6453,22 +6453,22 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * of 1-wide MOVs and scattering the result. */ const fs_builder ubld = devinfo->ver >= 20 ? bld.exec_all() : ubld1; - fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D); - ubld.MOV(res1, brw_imm_d(0)); + elk_fs_reg res1 = ubld.vgrf(ELK_REGISTER_TYPE_D); + ubld.MOV(res1, elk_imm_d(0)); set_predicate(devinfo->ver >= 20 ? XE2_PREDICATE_ALL : - s.dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H : - s.dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H : - BRW_PREDICATE_ALIGN1_ALL32H, - ubld.MOV(res1, brw_imm_d(-1))); + s.dispatch_width == 8 ? ELK_PREDICATE_ALIGN1_ALL8H : + s.dispatch_width == 16 ? ELK_PREDICATE_ALIGN1_ALL16H : + ELK_PREDICATE_ALIGN1_ALL32H, + ubld.MOV(res1, elk_imm_d(-1))); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0)); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_D), component(res1, 0)); break; } case nir_intrinsic_ballot: { - const fs_reg value = retype(get_nir_src(ntb, instr->src[0]), - BRW_REGISTER_TYPE_UD); - struct brw_reg flag = brw_flag_reg(0, 0); + const elk_fs_reg value = retype(get_nir_src(ntb, instr->src[0]), + ELK_REGISTER_TYPE_UD); + struct elk_reg flag = elk_flag_reg(0, 0); /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well * as f0.0. This is a problem for fragment programs as we currently use * f0.1 for discards. Fortunately, we don't support SIMD32 fragment @@ -6476,87 +6476,87 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * have to change. */ if (s.dispatch_width == 32) - flag.type = BRW_REGISTER_TYPE_UD; + flag.type = ELK_REGISTER_TYPE_UD; - bld.exec_all().group(1, 0).MOV(flag, brw_imm_ud(0u)); - bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ); + bld.exec_all().group(1, 0).MOV(flag, elk_imm_ud(0u)); + bld.CMP(bld.null_reg_ud(), value, elk_imm_ud(0u), ELK_CONDITIONAL_NZ); if (instr->def.bit_size > 32) { - dest.type = BRW_REGISTER_TYPE_UQ; + dest.type = ELK_REGISTER_TYPE_UQ; } else { - dest.type = BRW_REGISTER_TYPE_UD; + dest.type = ELK_REGISTER_TYPE_UD; } bld.MOV(dest, flag); break; } case nir_intrinsic_read_invocation: { - const fs_reg value = get_nir_src(ntb, instr->src[0]); - const fs_reg invocation = get_nir_src(ntb, instr->src[1]); + const elk_fs_reg value = get_nir_src(ntb, instr->src[0]); + const elk_fs_reg invocation = get_nir_src(ntb, instr->src[1]); - fs_reg tmp = bld.vgrf(value.type); + elk_fs_reg tmp = bld.vgrf(value.type); /* When for some reason the subgroup_size picked by NIR is larger than * the dispatch size picked by the backend (this could happen in RT, * FS), bound the invocation to the dispatch size. */ - fs_reg bound_invocation; + elk_fs_reg bound_invocation; if (s.api_subgroup_size == 0 || bld.dispatch_width() < s.api_subgroup_size) { - bound_invocation = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.AND(bound_invocation, invocation, brw_imm_ud(s.dispatch_width - 1)); + bound_invocation = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.AND(bound_invocation, invocation, elk_imm_ud(s.dispatch_width - 1)); } else { bound_invocation = invocation; } - bld.exec_all().emit(SHADER_OPCODE_BROADCAST, tmp, value, + bld.exec_all().emit(ELK_SHADER_OPCODE_BROADCAST, tmp, value, bld.emit_uniformize(bound_invocation)); - bld.MOV(retype(dest, value.type), fs_reg(component(tmp, 0))); + bld.MOV(retype(dest, value.type), elk_fs_reg(component(tmp, 0))); break; } case nir_intrinsic_read_first_invocation: { - const fs_reg value = get_nir_src(ntb, instr->src[0]); + const elk_fs_reg value = get_nir_src(ntb, instr->src[0]); bld.MOV(retype(dest, value.type), bld.emit_uniformize(value)); break; } case nir_intrinsic_shuffle: { - const fs_reg value = get_nir_src(ntb, instr->src[0]); - const fs_reg index = get_nir_src(ntb, instr->src[1]); + const elk_fs_reg value = get_nir_src(ntb, instr->src[0]); + const elk_fs_reg index = get_nir_src(ntb, instr->src[1]); - bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, index); + bld.emit(ELK_SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, index); break; } case nir_intrinsic_first_invocation: { - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, tmp); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), - fs_reg(component(tmp, 0))); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.exec_all().emit(ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, tmp); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_UD), + elk_fs_reg(component(tmp, 0))); break; } case nir_intrinsic_last_invocation: { - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.exec_all().emit(SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL, tmp); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), - fs_reg(component(tmp, 0))); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.exec_all().emit(ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL, tmp); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_UD), + elk_fs_reg(component(tmp, 0))); break; } case nir_intrinsic_quad_broadcast: { - const fs_reg value = get_nir_src(ntb, instr->src[0]); + const elk_fs_reg value = get_nir_src(ntb, instr->src[0]); const unsigned index = nir_src_as_uint(instr->src[1]); - bld.emit(SHADER_OPCODE_CLUSTER_BROADCAST, retype(dest, value.type), - value, brw_imm_ud(index), brw_imm_ud(4)); + bld.emit(ELK_SHADER_OPCODE_CLUSTER_BROADCAST, retype(dest, value.type), + value, elk_imm_ud(index), elk_imm_ud(4)); break; } case nir_intrinsic_quad_swap_horizontal: { - const fs_reg value = get_nir_src(ntb, instr->src[0]); - const fs_reg tmp = bld.vgrf(value.type); + const elk_fs_reg value = get_nir_src(ntb, instr->src[0]); + const elk_fs_reg tmp = bld.vgrf(value.type); if (devinfo->ver <= 7) { /* The hardware doesn't seem to support these crazy regions with * compressed instructions on gfx7 and earlier so we fall back to @@ -6565,16 +6565,16 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, */ assert(nir_src_bit_size(instr->src[0]) == 32); const fs_builder ubld = bld.exec_all(); - ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp, value, - brw_imm_ud(BRW_SWIZZLE4(1,0,3,2))); + ubld.emit(ELK_SHADER_OPCODE_QUAD_SWIZZLE, tmp, value, + elk_imm_ud(ELK_SWIZZLE4(1,0,3,2))); bld.MOV(retype(dest, value.type), tmp); } else { const fs_builder ubld = bld.exec_all().group(s.dispatch_width / 2, 0); - const fs_reg src_left = horiz_stride(value, 2); - const fs_reg src_right = horiz_stride(horiz_offset(value, 1), 2); - const fs_reg tmp_left = horiz_stride(tmp, 2); - const fs_reg tmp_right = horiz_stride(horiz_offset(tmp, 1), 2); + const elk_fs_reg src_left = horiz_stride(value, 2); + const elk_fs_reg src_right = horiz_stride(horiz_offset(value, 1), 2); + const elk_fs_reg tmp_left = horiz_stride(tmp, 2); + const elk_fs_reg tmp_right = horiz_stride(horiz_offset(tmp, 1), 2); ubld.MOV(tmp_left, src_right); ubld.MOV(tmp_right, src_left); @@ -6585,70 +6585,70 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_quad_swap_vertical: { - const fs_reg value = get_nir_src(ntb, instr->src[0]); + const elk_fs_reg value = get_nir_src(ntb, instr->src[0]); if (nir_src_bit_size(instr->src[0]) == 32) { /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */ - const fs_reg tmp = bld.vgrf(value.type); + const elk_fs_reg tmp = bld.vgrf(value.type); const fs_builder ubld = bld.exec_all(); - ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp, value, - brw_imm_ud(BRW_SWIZZLE4(2,3,0,1))); + ubld.emit(ELK_SHADER_OPCODE_QUAD_SWIZZLE, tmp, value, + elk_imm_ud(ELK_SWIZZLE4(2,3,0,1))); bld.MOV(retype(dest, value.type), tmp); } else { /* For larger data types, we have to either emit dispatch_width many * MOVs or else fall back to doing indirects. */ - fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_W); + elk_fs_reg idx = bld.vgrf(ELK_REGISTER_TYPE_W); bld.XOR(idx, ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION], - brw_imm_w(0x2)); - bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, idx); + elk_imm_w(0x2)); + bld.emit(ELK_SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, idx); } break; } case nir_intrinsic_quad_swap_diagonal: { - const fs_reg value = get_nir_src(ntb, instr->src[0]); + const elk_fs_reg value = get_nir_src(ntb, instr->src[0]); if (nir_src_bit_size(instr->src[0]) == 32) { /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */ - const fs_reg tmp = bld.vgrf(value.type); + const elk_fs_reg tmp = bld.vgrf(value.type); const fs_builder ubld = bld.exec_all(); - ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp, value, - brw_imm_ud(BRW_SWIZZLE4(3,2,1,0))); + ubld.emit(ELK_SHADER_OPCODE_QUAD_SWIZZLE, tmp, value, + elk_imm_ud(ELK_SWIZZLE4(3,2,1,0))); bld.MOV(retype(dest, value.type), tmp); } else { /* For larger data types, we have to either emit dispatch_width many * MOVs or else fall back to doing indirects. */ - fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_W); + elk_fs_reg idx = bld.vgrf(ELK_REGISTER_TYPE_W); bld.XOR(idx, ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION], - brw_imm_w(0x3)); - bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, idx); + elk_imm_w(0x3)); + bld.emit(ELK_SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, idx); } break; } case nir_intrinsic_reduce: { - fs_reg src = get_nir_src(ntb, instr->src[0]); + elk_fs_reg src = get_nir_src(ntb, instr->src[0]); nir_op redop = (nir_op)nir_intrinsic_reduction_op(instr); unsigned cluster_size = nir_intrinsic_cluster_size(instr); if (cluster_size == 0 || cluster_size > s.dispatch_width) cluster_size = s.dispatch_width; /* Figure out the source type */ - src.type = brw_type_for_nir_type(devinfo, + src.type = elk_type_for_nir_type(devinfo, (nir_alu_type)(nir_op_infos[redop].input_types[0] | nir_src_bit_size(instr->src[0]))); - fs_reg identity = brw_nir_reduction_op_identity(bld, redop, src.type); - opcode brw_op = brw_op_for_nir_reduction_op(redop); - brw_conditional_mod cond_mod = brw_cond_mod_for_nir_reduction_op(redop); + elk_fs_reg identity = elk_nir_reduction_op_identity(bld, redop, src.type); + elk_opcode elk_op = elk_op_for_nir_reduction_op(redop); + elk_conditional_mod cond_mod = elk_cond_mod_for_nir_reduction_op(redop); /* Set up a register for all of our scratching around and initialize it * to reduction operation's identity value. */ - fs_reg scan = bld.vgrf(src.type); - bld.exec_all().emit(SHADER_OPCODE_SEL_EXEC, scan, src, identity); + elk_fs_reg scan = bld.vgrf(src.type); + bld.exec_all().emit(ELK_SHADER_OPCODE_SEL_EXEC, scan, src, identity); - bld.emit_scan(brw_op, scan, cluster_size, cond_mod); + bld.emit_scan(elk_op, scan, cluster_size, cond_mod); dest.type = src.type; if (cluster_size * type_sz(src.type) >= REG_SIZE * 2) { @@ -6668,48 +6668,48 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, component(scan, comp)); } } else { - bld.emit(SHADER_OPCODE_CLUSTER_BROADCAST, dest, scan, - brw_imm_ud(cluster_size - 1), brw_imm_ud(cluster_size)); + bld.emit(ELK_SHADER_OPCODE_CLUSTER_BROADCAST, dest, scan, + elk_imm_ud(cluster_size - 1), elk_imm_ud(cluster_size)); } break; } case nir_intrinsic_inclusive_scan: case nir_intrinsic_exclusive_scan: { - fs_reg src = get_nir_src(ntb, instr->src[0]); + elk_fs_reg src = get_nir_src(ntb, instr->src[0]); nir_op redop = (nir_op)nir_intrinsic_reduction_op(instr); /* Figure out the source type */ - src.type = brw_type_for_nir_type(devinfo, + src.type = elk_type_for_nir_type(devinfo, (nir_alu_type)(nir_op_infos[redop].input_types[0] | nir_src_bit_size(instr->src[0]))); - fs_reg identity = brw_nir_reduction_op_identity(bld, redop, src.type); - opcode brw_op = brw_op_for_nir_reduction_op(redop); - brw_conditional_mod cond_mod = brw_cond_mod_for_nir_reduction_op(redop); + elk_fs_reg identity = elk_nir_reduction_op_identity(bld, redop, src.type); + elk_opcode elk_op = elk_op_for_nir_reduction_op(redop); + elk_conditional_mod cond_mod = elk_cond_mod_for_nir_reduction_op(redop); /* Set up a register for all of our scratching around and initialize it * to reduction operation's identity value. */ - fs_reg scan = bld.vgrf(src.type); + elk_fs_reg scan = bld.vgrf(src.type); const fs_builder allbld = bld.exec_all(); - allbld.emit(SHADER_OPCODE_SEL_EXEC, scan, src, identity); + allbld.emit(ELK_SHADER_OPCODE_SEL_EXEC, scan, src, identity); if (instr->intrinsic == nir_intrinsic_exclusive_scan) { /* Exclusive scan is a bit harder because we have to do an annoying * shift of the contents before we can begin. To make things worse, * we can't do this with a normal stride; we have to use indirects. */ - fs_reg shifted = bld.vgrf(src.type); - fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_W); + elk_fs_reg shifted = bld.vgrf(src.type); + elk_fs_reg idx = bld.vgrf(ELK_REGISTER_TYPE_W); allbld.ADD(idx, ntb.system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION], - brw_imm_w(-1)); - allbld.emit(SHADER_OPCODE_SHUFFLE, shifted, scan, idx); + elk_imm_w(-1)); + allbld.emit(ELK_SHADER_OPCODE_SHUFFLE, shifted, scan, idx); allbld.group(1, 0).MOV(component(shifted, 0), identity); scan = shifted; } - bld.emit_scan(brw_op, scan, s.dispatch_width, cond_mod); + bld.emit_scan(elk_op, scan, s.dispatch_width, cond_mod); bld.MOV(retype(dest, src.type), scan); break; @@ -6718,7 +6718,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_global_block_intel: { assert(instr->def.bit_size == 32); - fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[0])); + elk_fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[0])); const fs_builder ubld1 = bld.exec_all().group(1, 0); const fs_builder ubld8 = bld.exec_all().group(8, 0); @@ -6734,13 +6734,13 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const fs_builder &ubld = block == 8 ? ubld8 : ubld16; - fs_reg srcs[A64_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[A64_LOGICAL_NUM_SRCS]; srcs[A64_LOGICAL_ADDRESS] = address; - srcs[A64_LOGICAL_SRC] = fs_reg(); /* No source data */ - srcs[A64_LOGICAL_ARG] = brw_imm_ud(block); - srcs[A64_LOGICAL_ENABLE_HELPERS] = brw_imm_ud(1); - ubld.emit(SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, - retype(byte_offset(dest, loaded * 4), BRW_REGISTER_TYPE_UD), + srcs[A64_LOGICAL_SRC] = elk_fs_reg(); /* No source data */ + srcs[A64_LOGICAL_ARG] = elk_imm_ud(block); + srcs[A64_LOGICAL_ENABLE_HELPERS] = elk_imm_ud(1); + ubld.emit(ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, + retype(byte_offset(dest, loaded * 4), ELK_REGISTER_TYPE_UD), srcs, A64_LOGICAL_NUM_SRCS)->size_written = block_bytes; increment_a64_address(ubld1, address, block_bytes); @@ -6754,8 +6754,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_store_global_block_intel: { assert(nir_src_bit_size(instr->src[0]) == 32); - fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[1])); - fs_reg src = get_nir_src(ntb, instr->src[0]); + elk_fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[1])); + elk_fs_reg src = get_nir_src(ntb, instr->src[0]); const fs_builder ubld1 = bld.exec_all().group(1, 0); const fs_builder ubld8 = bld.exec_all().group(8, 0); @@ -6768,15 +6768,15 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const unsigned block = choose_oword_block_size_dwords(devinfo, total - written); - fs_reg srcs[A64_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[A64_LOGICAL_NUM_SRCS]; srcs[A64_LOGICAL_ADDRESS] = address; srcs[A64_LOGICAL_SRC] = retype(byte_offset(src, written * 4), - BRW_REGISTER_TYPE_UD); - srcs[A64_LOGICAL_ARG] = brw_imm_ud(block); - srcs[A64_LOGICAL_ENABLE_HELPERS] = brw_imm_ud(0); + ELK_REGISTER_TYPE_UD); + srcs[A64_LOGICAL_ARG] = elk_imm_ud(block); + srcs[A64_LOGICAL_ENABLE_HELPERS] = elk_imm_ud(0); const fs_builder &ubld = block == 8 ? ubld8 : ubld16; - ubld.emit(SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL, fs_reg(), + ubld.emit(ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL, elk_fs_reg(), srcs, A64_LOGICAL_NUM_SRCS); const unsigned block_bytes = block * 4; @@ -6794,12 +6794,12 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const bool is_ssbo = instr->intrinsic == nir_intrinsic_load_ssbo_block_intel; - fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[is_ssbo ? 1 : 0])); + elk_fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[is_ssbo ? 1 : 0])); - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ? get_nir_buffer_intrinsic_index(ntb, bld, instr) : - fs_reg(brw_imm_ud(GFX7_BTI_SLM)); + elk_fs_reg(elk_imm_ud(GFX7_BTI_SLM)); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address; const fs_builder ubld1 = bld.exec_all().group(1, 0); @@ -6814,14 +6814,14 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, choose_oword_block_size_dwords(devinfo, total - loaded); const unsigned block_bytes = block * 4; - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(block); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(block); const fs_builder &ubld = block == 8 ? ubld8 : ubld16; - ubld.emit(SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, - retype(byte_offset(dest, loaded * 4), BRW_REGISTER_TYPE_UD), + ubld.emit(ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, + retype(byte_offset(dest, loaded * 4), ELK_REGISTER_TYPE_UD), srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written = block_bytes; - ubld1.ADD(address, address, brw_imm_ud(block_bytes)); + ubld1.ADD(address, address, elk_imm_ud(block_bytes)); loaded += block; } @@ -6836,13 +6836,13 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const bool is_ssbo = instr->intrinsic == nir_intrinsic_store_ssbo_block_intel; - fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[is_ssbo ? 2 : 1])); - fs_reg src = get_nir_src(ntb, instr->src[0]); + elk_fs_reg address = bld.emit_uniformize(get_nir_src(ntb, instr->src[is_ssbo ? 2 : 1])); + elk_fs_reg src = get_nir_src(ntb, instr->src[0]); - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ? get_nir_buffer_intrinsic_index(ntb, bld, instr) : - fs_reg(brw_imm_ud(GFX7_BTI_SLM)); + elk_fs_reg(elk_imm_ud(GFX7_BTI_SLM)); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address; const fs_builder ubld1 = bld.exec_all().group(1, 0); @@ -6856,16 +6856,16 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const unsigned block = choose_oword_block_size_dwords(devinfo, total - written); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(block); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(block); srcs[SURFACE_LOGICAL_SRC_DATA] = - retype(byte_offset(src, written * 4), BRW_REGISTER_TYPE_UD); + retype(byte_offset(src, written * 4), ELK_REGISTER_TYPE_UD); const fs_builder &ubld = block == 8 ? ubld8 : ubld16; - ubld.emit(SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL, - fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); + ubld.emit(ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL, + elk_fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); const unsigned block_bytes = block * 4; - ubld1.ADD(address, address, brw_imm_ud(block_bytes)); + ubld1.ADD(address, address, elk_imm_ud(block_bytes)); written += block; } @@ -6898,10 +6898,10 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * [6:4] : EUID * [2:0] : Thread ID */ - fs_reg raw_id = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_READ_SR_REG, raw_id, brw_imm_ud(0)); + elk_fs_reg raw_id = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.emit(ELK_SHADER_OPCODE_READ_SR_REG, raw_id, elk_imm_ud(0)); switch (nir_intrinsic_base(instr)) { - case BRW_TOPOLOGY_ID_DSS: + case ELK_TOPOLOGY_ID_DSS: if (devinfo->ver >= 20) { /* Xe2+: 3D and GPGPU Programs, Shared Functions, Ray Tracing: * https://gfxspecs.intel.com/Predator/Home/Index/56936 @@ -6920,31 +6920,31 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * * We are using the state register to calculate the DSSID. */ - fs_reg slice_id = bld.vgrf(BRW_REGISTER_TYPE_UD); - fs_reg subslice_id = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.AND(slice_id, raw_id, brw_imm_ud(INTEL_MASK(15, 11))); - bld.SHR(slice_id, slice_id, brw_imm_ud(11)); + elk_fs_reg slice_id = bld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_reg subslice_id = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.AND(slice_id, raw_id, elk_imm_ud(INTEL_MASK(15, 11))); + bld.SHR(slice_id, slice_id, elk_imm_ud(11)); /* Assert that max subslices covers at least 2 bits that we use for * subslices. */ assert(devinfo->max_subslices_per_slice >= (1 << 2)); bld.MUL(slice_id, slice_id, - brw_imm_ud(devinfo->max_subslices_per_slice)); - bld.AND(subslice_id, raw_id, brw_imm_ud(INTEL_MASK(9, 8))); - bld.SHR(subslice_id, subslice_id, brw_imm_ud(8)); - bld.ADD(retype(dest, BRW_REGISTER_TYPE_UD), slice_id, + elk_imm_ud(devinfo->max_subslices_per_slice)); + bld.AND(subslice_id, raw_id, elk_imm_ud(INTEL_MASK(9, 8))); + bld.SHR(subslice_id, subslice_id, elk_imm_ud(8)); + bld.ADD(retype(dest, ELK_REGISTER_TYPE_UD), slice_id, subslice_id); } else { - bld.AND(raw_id, raw_id, brw_imm_ud(0x3fff)); + bld.AND(raw_id, raw_id, elk_imm_ud(0x3fff)); /* Get rid of anything below dualsubslice */ - bld.SHR(retype(dest, BRW_REGISTER_TYPE_UD), raw_id, brw_imm_ud(9)); + bld.SHR(retype(dest, ELK_REGISTER_TYPE_UD), raw_id, elk_imm_ud(9)); } break; - case BRW_TOPOLOGY_ID_EU_THREAD_SIMD: { + case ELK_TOPOLOGY_ID_EU_THREAD_SIMD: { s.limit_dispatch_width(16, "Topology helper for Ray queries, " "not supported in SIMD32 mode."); - fs_reg dst = retype(dest, BRW_REGISTER_TYPE_UD); + elk_fs_reg dst = retype(dest, ELK_REGISTER_TYPE_UD); if (devinfo->ver >= 20) { /* Xe2+: Graphics Engine, 3D and GPGPU Programs, Shared Functions @@ -6961,8 +6961,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * * EU[2:0] = raw_id[6:4] (identified as EUID[2:0]) */ - bld.AND(dst, raw_id, brw_imm_ud(INTEL_MASK(6, 4))); - bld.SHL(dst, dst, brw_imm_ud(4)); + bld.AND(dst, raw_id, elk_imm_ud(INTEL_MASK(6, 4))); + bld.SHL(dst, dst, elk_imm_ud(4)); } else { /* EU[3:0] << 7 * @@ -6973,21 +6973,21 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * EU[2] = raw_id[8] (identified as SubSlice ID) * EU[3] = raw_id[7] (identified as EUID[2] or Row ID) */ - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.AND(tmp, raw_id, brw_imm_ud(INTEL_MASK(7, 7))); - bld.SHL(dst, tmp, brw_imm_ud(3)); - bld.AND(tmp, raw_id, brw_imm_ud(INTEL_MASK(8, 8))); - bld.SHL(tmp, tmp, brw_imm_ud(1)); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.AND(tmp, raw_id, elk_imm_ud(INTEL_MASK(7, 7))); + bld.SHL(dst, tmp, elk_imm_ud(3)); + bld.AND(tmp, raw_id, elk_imm_ud(INTEL_MASK(8, 8))); + bld.SHL(tmp, tmp, elk_imm_ud(1)); bld.OR(dst, dst, tmp); - bld.AND(tmp, raw_id, brw_imm_ud(INTEL_MASK(5, 4))); - bld.SHL(tmp, tmp, brw_imm_ud(3)); + bld.AND(tmp, raw_id, elk_imm_ud(INTEL_MASK(5, 4))); + bld.SHL(tmp, tmp, elk_imm_ud(3)); bld.OR(dst, dst, tmp); } /* ThreadID[2:0] << 4 (ThreadID comes from raw_id[2:0]) */ { - bld.AND(raw_id, raw_id, brw_imm_ud(INTEL_MASK(2, 0))); - bld.SHL(raw_id, raw_id, brw_imm_ud(4)); + bld.AND(raw_id, raw_id, elk_imm_ud(INTEL_MASK(2, 0))); + bld.SHL(raw_id, raw_id, elk_imm_ud(4)); bld.OR(dst, dst, raw_id); } @@ -7012,12 +7012,12 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } } -static fs_reg -expand_to_32bit(const fs_builder &bld, const fs_reg &src) +static elk_fs_reg +expand_to_32bit(const fs_builder &bld, const elk_fs_reg &src) { if (type_sz(src.type) == 2) { - fs_reg src32 = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.MOV(src32, retype(src, BRW_REGISTER_TYPE_UW)); + elk_fs_reg src32 = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.MOV(src32, retype(src, ELK_REGISTER_TYPE_UW)); return src32; } else { return src; @@ -7025,15 +7025,15 @@ expand_to_32bit(const fs_builder &bld, const fs_reg &src) } static void -fs_nir_emit_surface_atomic(nir_to_brw_state &ntb, const fs_builder &bld, +fs_nir_emit_surface_atomic(nir_to_elk_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr, - fs_reg surface, + elk_fs_reg surface, bool bindless) { const intel_device_info *devinfo = ntb.devinfo; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; - enum lsc_opcode op = lsc_aop_for_nir_intrinsic(instr); + enum elk_lsc_opcode op = elk_lsc_aop_for_nir_intrinsic(instr); int num_data = lsc_op_num_data_values(op); bool shared = surface.file == IMM && surface.ud == GFX7_BTI_SLM; @@ -7048,42 +7048,42 @@ fs_nir_emit_surface_atomic(nir_to_brw_state &ntb, const fs_builder &bld, assert(instr->def.bit_size == 32 || (instr->def.bit_size == 64 && devinfo->has_lsc) || (instr->def.bit_size == 16 && - (devinfo->has_lsc || lsc_opcode_is_atomic_float(op)))); + (devinfo->has_lsc || elk_lsc_opcode_is_atomic_float(op)))); - fs_reg dest = get_nir_def(ntb, instr->def); + elk_fs_reg dest = get_nir_def(ntb, instr->def); - fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[bindless ? SURFACE_LOGICAL_SRC_SURFACE_HANDLE : SURFACE_LOGICAL_SRC_SURFACE] = surface; - srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); - srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op); - srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = elk_imm_ud(1); + srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = elk_imm_ud(op); + srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = elk_imm_ud(1); if (shared) { /* SLM - Get the offset */ if (nir_src_is_const(instr->src[0])) { srcs[SURFACE_LOGICAL_SRC_ADDRESS] = - brw_imm_ud(nir_intrinsic_base(instr) + + elk_imm_ud(nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0])); } else { srcs[SURFACE_LOGICAL_SRC_ADDRESS] = s.vgrf(glsl_uint_type()); bld.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS], - retype(get_nir_src(ntb, instr->src[0]), BRW_REGISTER_TYPE_UD), - brw_imm_ud(nir_intrinsic_base(instr))); + retype(get_nir_src(ntb, instr->src[0]), ELK_REGISTER_TYPE_UD), + elk_imm_ud(nir_intrinsic_base(instr))); } } else { /* SSBOs */ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(ntb, instr->src[1]); } - fs_reg data; + elk_fs_reg data; if (num_data >= 1) data = expand_to_32bit(bld, get_nir_src(ntb, instr->src[shared ? 1 : 2])); if (num_data >= 2) { - fs_reg tmp = bld.vgrf(data.type, 2); - fs_reg sources[2] = { + elk_fs_reg tmp = bld.vgrf(data.type, 2); + elk_fs_reg sources[2] = { data, expand_to_32bit(bld, get_nir_src(ntb, instr->src[shared ? 2 : 3])) }; @@ -7096,18 +7096,18 @@ fs_nir_emit_surface_atomic(nir_to_brw_state &ntb, const fs_builder &bld, switch (instr->def.bit_size) { case 16: { - fs_reg dest32 = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, + elk_fs_reg dest32 = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.emit(ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, retype(dest32, dest.type), srcs, SURFACE_LOGICAL_NUM_SRCS); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_UW), - retype(dest32, BRW_REGISTER_TYPE_UD)); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_UW), + retype(dest32, ELK_REGISTER_TYPE_UD)); break; } case 32: case 64: - bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, + bld.emit(ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, dest, srcs, SURFACE_LOGICAL_NUM_SRCS); break; default: @@ -7116,23 +7116,23 @@ fs_nir_emit_surface_atomic(nir_to_brw_state &ntb, const fs_builder &bld, } static void -fs_nir_emit_global_atomic(nir_to_brw_state &ntb, const fs_builder &bld, +fs_nir_emit_global_atomic(nir_to_elk_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr) { - enum lsc_opcode op = lsc_aop_for_nir_intrinsic(instr); + enum elk_lsc_opcode op = elk_lsc_aop_for_nir_intrinsic(instr); int num_data = lsc_op_num_data_values(op); - fs_reg dest = get_nir_def(ntb, instr->def); + elk_fs_reg dest = get_nir_def(ntb, instr->def); - fs_reg addr = get_nir_src(ntb, instr->src[0]); + elk_fs_reg addr = get_nir_src(ntb, instr->src[0]); - fs_reg data; + elk_fs_reg data; if (num_data >= 1) data = expand_to_32bit(bld, get_nir_src(ntb, instr->src[1])); if (num_data >= 2) { - fs_reg tmp = bld.vgrf(data.type, 2); - fs_reg sources[2] = { + elk_fs_reg tmp = bld.vgrf(data.type, 2); + elk_fs_reg sources[2] = { data, expand_to_32bit(bld, get_nir_src(ntb, instr->src[2])) }; @@ -7140,24 +7140,24 @@ fs_nir_emit_global_atomic(nir_to_brw_state &ntb, const fs_builder &bld, data = tmp; } - fs_reg srcs[A64_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[A64_LOGICAL_NUM_SRCS]; srcs[A64_LOGICAL_ADDRESS] = addr; srcs[A64_LOGICAL_SRC] = data; - srcs[A64_LOGICAL_ARG] = brw_imm_ud(op); - srcs[A64_LOGICAL_ENABLE_HELPERS] = brw_imm_ud(0); + srcs[A64_LOGICAL_ARG] = elk_imm_ud(op); + srcs[A64_LOGICAL_ENABLE_HELPERS] = elk_imm_ud(0); switch (instr->def.bit_size) { case 16: { - fs_reg dest32 = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, + elk_fs_reg dest32 = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.emit(ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, retype(dest32, dest.type), srcs, A64_LOGICAL_NUM_SRCS); - bld.MOV(retype(dest, BRW_REGISTER_TYPE_UW), dest32); + bld.MOV(retype(dest, ELK_REGISTER_TYPE_UW), dest32); break; } case 32: case 64: - bld.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, dest, + bld.emit(ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, dest, srcs, A64_LOGICAL_NUM_SRCS); break; default: @@ -7166,14 +7166,14 @@ fs_nir_emit_global_atomic(nir_to_brw_state &ntb, const fs_builder &bld, } static void -fs_nir_emit_texture(nir_to_brw_state &ntb, +fs_nir_emit_texture(nir_to_elk_state &ntb, nir_tex_instr *instr) { const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; - fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; /* SKL PRMs: Volume 7: 3D-Media-GPGPU: * @@ -7186,30 +7186,30 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, */ assert(!instr->is_sparse || srcs[TEX_LOGICAL_SRC_SHADOW_C].file == BAD_FILE); - srcs[TEX_LOGICAL_SRC_RESIDENCY] = brw_imm_ud(instr->is_sparse); + srcs[TEX_LOGICAL_SRC_RESIDENCY] = elk_imm_ud(instr->is_sparse); int lod_components = 0; /* The hardware requires a LOD for buffer textures */ if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) - srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_d(0); + srcs[TEX_LOGICAL_SRC_LOD] = elk_imm_d(0); ASSERTED bool got_lod = false; ASSERTED bool got_bias = false; uint32_t header_bits = 0; for (unsigned i = 0; i < instr->num_srcs; i++) { nir_src nir_src = instr->src[i].src; - fs_reg src = get_nir_src(ntb, nir_src); + elk_fs_reg src = get_nir_src(ntb, nir_src); switch (instr->src[i].src_type) { case nir_tex_src_bias: assert(!got_lod); got_bias = true; srcs[TEX_LOGICAL_SRC_LOD] = - retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F); + retype(get_nir_src_imm(ntb, instr->src[i].src), ELK_REGISTER_TYPE_F); break; case nir_tex_src_comparator: - srcs[TEX_LOGICAL_SRC_SHADOW_C] = retype(src, BRW_REGISTER_TYPE_F); + srcs[TEX_LOGICAL_SRC_SHADOW_C] = retype(src, ELK_REGISTER_TYPE_F); break; case nir_tex_src_coord: switch (instr->op) { @@ -7217,19 +7217,19 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, case nir_texop_txf_ms: case nir_texop_txf_ms_mcs_intel: case nir_texop_samples_identical: - srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, BRW_REGISTER_TYPE_D); + srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, ELK_REGISTER_TYPE_D); break; default: - srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, BRW_REGISTER_TYPE_F); + srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, ELK_REGISTER_TYPE_F); break; } break; case nir_tex_src_ddx: - srcs[TEX_LOGICAL_SRC_LOD] = retype(src, BRW_REGISTER_TYPE_F); + srcs[TEX_LOGICAL_SRC_LOD] = retype(src, ELK_REGISTER_TYPE_F); lod_components = nir_tex_instr_src_size(instr, i); break; case nir_tex_src_ddy: - srcs[TEX_LOGICAL_SRC_LOD2] = retype(src, BRW_REGISTER_TYPE_F); + srcs[TEX_LOGICAL_SRC_LOD2] = retype(src, ELK_REGISTER_TYPE_F); break; case nir_tex_src_lod: assert(!got_bias); @@ -7238,29 +7238,29 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, switch (instr->op) { case nir_texop_txs: srcs[TEX_LOGICAL_SRC_LOD] = - retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_UD); + retype(get_nir_src_imm(ntb, instr->src[i].src), ELK_REGISTER_TYPE_UD); break; case nir_texop_txf: srcs[TEX_LOGICAL_SRC_LOD] = - retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_D); + retype(get_nir_src_imm(ntb, instr->src[i].src), ELK_REGISTER_TYPE_D); break; default: srcs[TEX_LOGICAL_SRC_LOD] = - retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F); + retype(get_nir_src_imm(ntb, instr->src[i].src), ELK_REGISTER_TYPE_F); break; } break; case nir_tex_src_min_lod: srcs[TEX_LOGICAL_SRC_MIN_LOD] = - retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F); + retype(get_nir_src_imm(ntb, instr->src[i].src), ELK_REGISTER_TYPE_F); break; case nir_tex_src_ms_index: - srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = retype(src, BRW_REGISTER_TYPE_UD); + srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = retype(src, ELK_REGISTER_TYPE_UD); break; case nir_tex_src_offset: { uint32_t offset_bits = 0; - if (brw_texture_offset(instr, i, &offset_bits)) { + if (elk_texture_offset(instr, i, &offset_bits)) { header_bits |= offset_bits; } else { /* On gfx12.5+, if the offsets are not both constant and in the @@ -7269,7 +7269,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, */ assert(devinfo->verx10 < 125); srcs[TEX_LOGICAL_SRC_TG4_OFFSET] = - retype(src, BRW_REGISTER_TYPE_D); + retype(src, ELK_REGISTER_TYPE_D); } break; } @@ -7283,8 +7283,8 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, if (instr->texture_index == 0 && is_resource_src(nir_src)) srcs[TEX_LOGICAL_SRC_SURFACE] = get_resource_nir_src(ntb, nir_src); if (srcs[TEX_LOGICAL_SRC_SURFACE].file == BAD_FILE) { - fs_reg tmp = s.vgrf(glsl_uint_type()); - bld.ADD(tmp, src, brw_imm_ud(instr->texture_index)); + elk_fs_reg tmp = s.vgrf(glsl_uint_type()); + bld.ADD(tmp, src, elk_imm_ud(instr->texture_index)); srcs[TEX_LOGICAL_SRC_SURFACE] = bld.emit_uniformize(tmp); } assert(srcs[TEX_LOGICAL_SRC_SURFACE].file != BAD_FILE); @@ -7296,8 +7296,8 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, if (instr->sampler_index == 0 && is_resource_src(nir_src)) srcs[TEX_LOGICAL_SRC_SAMPLER] = get_resource_nir_src(ntb, nir_src); if (srcs[TEX_LOGICAL_SRC_SAMPLER].file == BAD_FILE) { - fs_reg tmp = s.vgrf(glsl_uint_type()); - bld.ADD(tmp, src, brw_imm_ud(instr->sampler_index)); + elk_fs_reg tmp = s.vgrf(glsl_uint_type()); + bld.ADD(tmp, src, elk_imm_ud(instr->sampler_index)); srcs[TEX_LOGICAL_SRC_SAMPLER] = bld.emit_uniformize(tmp); } break; @@ -7305,7 +7305,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, case nir_tex_src_texture_handle: assert(nir_tex_instr_src_index(instr, nir_tex_src_texture_offset) == -1); - srcs[TEX_LOGICAL_SRC_SURFACE] = fs_reg(); + srcs[TEX_LOGICAL_SRC_SURFACE] = elk_fs_reg(); if (is_resource_src(nir_src)) srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE] = get_resource_nir_src(ntb, nir_src); if (srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE].file == BAD_FILE) @@ -7314,7 +7314,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, case nir_tex_src_sampler_handle: assert(nir_tex_instr_src_index(instr, nir_tex_src_sampler_offset) == -1); - srcs[TEX_LOGICAL_SRC_SAMPLER] = fs_reg(); + srcs[TEX_LOGICAL_SRC_SAMPLER] = elk_fs_reg(); if (is_resource_src(nir_src)) srcs[TEX_LOGICAL_SRC_SAMPLER_HANDLE] = get_resource_nir_src(ntb, nir_src); if (srcs[TEX_LOGICAL_SRC_SAMPLER_HANDLE].file == BAD_FILE) @@ -7323,7 +7323,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, case nir_tex_src_ms_mcs_intel: assert(instr->op == nir_texop_txf_ms); - srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D); + srcs[TEX_LOGICAL_SRC_MCS] = retype(src, ELK_REGISTER_TYPE_D); break; /* If this parameter is present, we are packing either the explicit LOD @@ -7336,7 +7336,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, assert(instr->op == nir_texop_txl || instr->op == nir_texop_txb); srcs[TEX_LOGICAL_SRC_LOD] = - retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F); + retype(get_nir_src_imm(ntb, instr->src[i].src), ELK_REGISTER_TYPE_F); break; default: @@ -7349,10 +7349,10 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, */ if (srcs[TEX_LOGICAL_SRC_SURFACE].file == BAD_FILE && srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE].file == BAD_FILE) - srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(instr->texture_index); + srcs[TEX_LOGICAL_SRC_SURFACE] = elk_imm_ud(instr->texture_index); if (srcs[TEX_LOGICAL_SRC_SAMPLER].file == BAD_FILE && srcs[TEX_LOGICAL_SRC_SAMPLER_HANDLE].file == BAD_FILE) - srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(instr->sampler_index); + srcs[TEX_LOGICAL_SRC_SAMPLER] = elk_imm_ud(instr->sampler_index); if (srcs[TEX_LOGICAL_SRC_MCS].file == BAD_FILE && (instr->op == nir_texop_txf_ms || @@ -7364,29 +7364,29 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, srcs[TEX_LOGICAL_SRC_SURFACE], srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE]); } else { - srcs[TEX_LOGICAL_SRC_MCS] = brw_imm_ud(0u); + srcs[TEX_LOGICAL_SRC_MCS] = elk_imm_ud(0u); } } - srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(instr->coord_components); - srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(lod_components); + srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = elk_imm_d(instr->coord_components); + srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = elk_imm_d(lod_components); - enum opcode opcode; + enum elk_opcode opcode; switch (instr->op) { case nir_texop_tex: - opcode = SHADER_OPCODE_TEX_LOGICAL; + opcode = ELK_SHADER_OPCODE_TEX_LOGICAL; break; case nir_texop_txb: - opcode = FS_OPCODE_TXB_LOGICAL; + opcode = ELK_FS_OPCODE_TXB_LOGICAL; break; case nir_texop_txl: - opcode = SHADER_OPCODE_TXL_LOGICAL; + opcode = ELK_SHADER_OPCODE_TXL_LOGICAL; break; case nir_texop_txd: - opcode = SHADER_OPCODE_TXD_LOGICAL; + opcode = ELK_SHADER_OPCODE_TXD_LOGICAL; break; case nir_texop_txf: - opcode = SHADER_OPCODE_TXF_LOGICAL; + opcode = ELK_SHADER_OPCODE_TXF_LOGICAL; break; case nir_texop_txf_ms: /* On Gfx12HP there is only CMS_W available. From the Bspec: Shared @@ -7395,47 +7395,47 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, * ld2dms REMOVEDBY(GEN:HAS:1406788836) */ if (devinfo->verx10 >= 125) - opcode = SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL; + opcode = ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL; else if (devinfo->ver >= 9) - opcode = SHADER_OPCODE_TXF_CMS_W_LOGICAL; + opcode = ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL; else - opcode = SHADER_OPCODE_TXF_CMS_LOGICAL; + opcode = ELK_SHADER_OPCODE_TXF_CMS_LOGICAL; break; case nir_texop_txf_ms_mcs_intel: - opcode = SHADER_OPCODE_TXF_MCS_LOGICAL; + opcode = ELK_SHADER_OPCODE_TXF_MCS_LOGICAL; break; case nir_texop_query_levels: case nir_texop_txs: - opcode = SHADER_OPCODE_TXS_LOGICAL; + opcode = ELK_SHADER_OPCODE_TXS_LOGICAL; break; case nir_texop_lod: - opcode = SHADER_OPCODE_LOD_LOGICAL; + opcode = ELK_SHADER_OPCODE_LOD_LOGICAL; break; case nir_texop_tg4: if (srcs[TEX_LOGICAL_SRC_TG4_OFFSET].file != BAD_FILE) - opcode = SHADER_OPCODE_TG4_OFFSET_LOGICAL; + opcode = ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL; else - opcode = SHADER_OPCODE_TG4_LOGICAL; + opcode = ELK_SHADER_OPCODE_TG4_LOGICAL; break; case nir_texop_texture_samples: - opcode = SHADER_OPCODE_SAMPLEINFO_LOGICAL; + opcode = ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL; break; case nir_texop_samples_identical: { - fs_reg dst = retype(get_nir_def(ntb, instr->def), BRW_REGISTER_TYPE_D); + elk_fs_reg dst = retype(get_nir_def(ntb, instr->def), ELK_REGISTER_TYPE_D); /* If mcs is an immediate value, it means there is no MCS. In that case * just return false. */ - if (srcs[TEX_LOGICAL_SRC_MCS].file == BRW_IMMEDIATE_VALUE) { - bld.MOV(dst, brw_imm_ud(0u)); + if (srcs[TEX_LOGICAL_SRC_MCS].file == ELK_IMMEDIATE_VALUE) { + bld.MOV(dst, elk_imm_ud(0u)); } else if (devinfo->ver >= 9) { - fs_reg tmp = s.vgrf(glsl_uint_type()); + elk_fs_reg tmp = s.vgrf(glsl_uint_type()); bld.OR(tmp, srcs[TEX_LOGICAL_SRC_MCS], offset(srcs[TEX_LOGICAL_SRC_MCS], bld, 1)); - bld.CMP(dst, tmp, brw_imm_ud(0u), BRW_CONDITIONAL_EQ); + bld.CMP(dst, tmp, elk_imm_ud(0u), ELK_CONDITIONAL_EQ); } else { - bld.CMP(dst, srcs[TEX_LOGICAL_SRC_MCS], brw_imm_ud(0u), - BRW_CONDITIONAL_EQ); + bld.CMP(dst, srcs[TEX_LOGICAL_SRC_MCS], elk_imm_ud(0u), + ELK_CONDITIONAL_EQ); } return; } @@ -7455,8 +7455,8 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, } } - fs_reg dst = bld.vgrf(brw_type_for_nir_type(devinfo, instr->dest_type), 4 + instr->is_sparse); - fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs)); + elk_fs_reg dst = bld.vgrf(elk_type_for_nir_type(devinfo, instr->dest_type), 4 + instr->is_sparse); + elk_fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs)); inst->offset = header_bits; const unsigned dest_size = nir_tex_instr_dest_size(instr); @@ -7496,7 +7496,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, inst->keep_payload_trailing_zeros = true; } - fs_reg nir_dest[5]; + elk_fs_reg nir_dest[5]; for (unsigned i = 0; i < dest_size; i++) nir_dest[i] = offset(dst, bld, i); @@ -7509,20 +7509,20 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, * When a surface of type SURFTYPE_NULL is accessed by resinfo, the * MIPCount returned is undefined instead of 0. */ - fs_inst *mov = bld.MOV(bld.null_reg_d(), dst); - mov->conditional_mod = BRW_CONDITIONAL_NZ; - nir_dest[0] = bld.vgrf(BRW_REGISTER_TYPE_D); - fs_inst *sel = bld.SEL(nir_dest[0], offset(dst, bld, 3), brw_imm_d(0)); - sel->predicate = BRW_PREDICATE_NORMAL; + elk_fs_inst *mov = bld.MOV(bld.null_reg_d(), dst); + mov->conditional_mod = ELK_CONDITIONAL_NZ; + nir_dest[0] = bld.vgrf(ELK_REGISTER_TYPE_D); + elk_fs_inst *sel = bld.SEL(nir_dest[0], offset(dst, bld, 3), elk_imm_d(0)); + sel->predicate = ELK_PREDICATE_NORMAL; } else { nir_dest[0] = offset(dst, bld, 3); } } else if (instr->op == nir_texop_txs && dest_size >= 3 && devinfo->ver < 7) { /* Gfx4-6 return 0 instead of 1 for single layer surfaces. */ - fs_reg depth = offset(dst, bld, 2); + elk_fs_reg depth = offset(dst, bld, 2); nir_dest[2] = s.vgrf(glsl_int_type()); - bld.emit_minmax(nir_dest[2], depth, brw_imm_d(1), BRW_CONDITIONAL_GE); + bld.emit_minmax(nir_dest[2], depth, elk_imm_d(1), ELK_CONDITIONAL_GE); } /* The residency bits are only in the first component. */ @@ -7533,17 +7533,17 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, } static void -fs_nir_emit_jump(nir_to_brw_state &ntb, nir_jump_instr *instr) +fs_nir_emit_jump(nir_to_elk_state &ntb, nir_jump_instr *instr) { switch (instr->type) { case nir_jump_break: - ntb.bld.emit(BRW_OPCODE_BREAK); + ntb.bld.emit(ELK_OPCODE_BREAK); break; case nir_jump_continue: - ntb.bld.emit(BRW_OPCODE_CONTINUE); + ntb.bld.emit(ELK_OPCODE_CONTINUE); break; case nir_jump_halt: - ntb.bld.emit(BRW_OPCODE_HALT); + ntb.bld.emit(ELK_OPCODE_HALT); break; case nir_jump_return: default: @@ -7595,9 +7595,9 @@ fs_nir_emit_jump(nir_to_brw_state &ntb, nir_jump_instr *instr) * - first_component parameter allows skipping source components. */ void -shuffle_src_to_dst(const fs_builder &bld, - const fs_reg &dst, - const fs_reg &src, +elk_shuffle_src_to_dst(const fs_builder &bld, + const elk_fs_reg &dst, + const elk_fs_reg &src, uint32_t first_component, uint32_t components) { @@ -7619,11 +7619,11 @@ shuffle_src_to_dst(const fs_builder &bld, offset(src, bld, first_component), type_sz(src.type) * bld.dispatch_width() * components)); - brw_reg_type shuffle_type = - brw_reg_type_from_bit_size(8 * type_sz(src.type), - BRW_REGISTER_TYPE_D); + elk_reg_type shuffle_type = + elk_reg_type_from_bit_size(8 * type_sz(src.type), + ELK_REGISTER_TYPE_D); for (unsigned i = 0; i < components; i++) { - fs_reg shuffle_component_i = + elk_fs_reg shuffle_component_i = subscript(offset(dst, bld, i / size_ratio), shuffle_type, i % size_ratio); bld.MOV(shuffle_component_i, @@ -7639,11 +7639,11 @@ shuffle_src_to_dst(const fs_builder &bld, DIV_ROUND_UP(components + (first_component % size_ratio), size_ratio))); - brw_reg_type shuffle_type = - brw_reg_type_from_bit_size(8 * type_sz(dst.type), - BRW_REGISTER_TYPE_D); + elk_reg_type shuffle_type = + elk_reg_type_from_bit_size(8 * type_sz(dst.type), + ELK_REGISTER_TYPE_D); for (unsigned i = 0; i < components; i++) { - fs_reg shuffle_component_i = + elk_fs_reg shuffle_component_i = subscript(offset(src, bld, (first_component + i) / size_ratio), shuffle_type, (first_component + i) % size_ratio); bld.MOV(retype(offset(dst, bld, i), shuffle_type), @@ -7653,16 +7653,16 @@ shuffle_src_to_dst(const fs_builder &bld, } void -shuffle_from_32bit_read(const fs_builder &bld, - const fs_reg &dst, - const fs_reg &src, +elk_shuffle_from_32bit_read(const fs_builder &bld, + const elk_fs_reg &dst, + const elk_fs_reg &src, uint32_t first_component, uint32_t components) { assert(type_sz(src.type) == 4); /* This function takes components in units of the destination type while - * shuffle_src_to_dst takes components in units of the smallest type + * elk_shuffle_src_to_dst takes components in units of the smallest type */ if (type_sz(dst.type) > 4) { assert(type_sz(dst.type) == 8); @@ -7670,25 +7670,25 @@ shuffle_from_32bit_read(const fs_builder &bld, components *= 2; } - shuffle_src_to_dst(bld, dst, src, first_component, components); + elk_shuffle_src_to_dst(bld, dst, src, first_component, components); } -fs_reg -setup_imm_df(const fs_builder &bld, double v) +elk_fs_reg +elk_setup_imm_df(const fs_builder &bld, double v) { const struct intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->ver >= 7); if (devinfo->ver >= 8) - return brw_imm_df(v); + return elk_imm_df(v); /* gfx7.5 does not support DF immediates straightforward but the DIM * instruction allows to set the 64-bit immediate value. */ if (devinfo->platform == INTEL_PLATFORM_HSW) { const fs_builder ubld = bld.exec_all().group(1, 0); - fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1); - ubld.DIM(dst, brw_imm_df(v)); + elk_fs_reg dst = ubld.vgrf(ELK_REGISTER_TYPE_DF, 1); + ubld.DIM(dst, elk_imm_df(v)); return component(dst, 0); } @@ -7714,31 +7714,31 @@ setup_imm_df(const fs_builder &bld, double v) di.d = v; const fs_builder ubld = bld.exec_all().group(1, 0); - const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2); - ubld.MOV(tmp, brw_imm_ud(di.i1)); - ubld.MOV(horiz_offset(tmp, 1), brw_imm_ud(di.i2)); + const elk_fs_reg tmp = ubld.vgrf(ELK_REGISTER_TYPE_UD, 2); + ubld.MOV(tmp, elk_imm_ud(di.i1)); + ubld.MOV(horiz_offset(tmp, 1), elk_imm_ud(di.i2)); - return component(retype(tmp, BRW_REGISTER_TYPE_DF), 0); + return component(retype(tmp, ELK_REGISTER_TYPE_DF), 0); } -fs_reg -setup_imm_b(const fs_builder &bld, int8_t v) +elk_fs_reg +elk_setup_imm_b(const fs_builder &bld, int8_t v) { - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_B); - bld.MOV(tmp, brw_imm_w(v)); + const elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_B); + bld.MOV(tmp, elk_imm_w(v)); return tmp; } -fs_reg -setup_imm_ub(const fs_builder &bld, uint8_t v) +elk_fs_reg +elk_setup_imm_ub(const fs_builder &bld, uint8_t v) { - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UB); - bld.MOV(tmp, brw_imm_uw(v)); + const elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UB); + bld.MOV(tmp, elk_imm_uw(v)); return tmp; } static void -fs_nir_emit_instr(nir_to_brw_state &ntb, nir_instr *instr) +fs_nir_emit_instr(nir_to_elk_state &ntb, nir_instr *instr) { ntb.bld = ntb.bld.annotate(NULL, instr); @@ -7801,57 +7801,57 @@ fs_nir_emit_instr(nir_to_brw_state &ntb, nir_instr *instr) } static unsigned -brw_rnd_mode_from_nir(unsigned mode, unsigned *mask) +elk_rnd_mode_from_nir(unsigned mode, unsigned *mask) { - unsigned brw_mode = 0; + unsigned elk_mode = 0; *mask = 0; if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64) & mode) { - brw_mode |= BRW_RND_MODE_RTZ << BRW_CR0_RND_MODE_SHIFT; - *mask |= BRW_CR0_RND_MODE_MASK; + elk_mode |= ELK_RND_MODE_RTZ << ELK_CR0_RND_MODE_SHIFT; + *mask |= ELK_CR0_RND_MODE_MASK; } if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64) & mode) { - brw_mode |= BRW_RND_MODE_RTNE << BRW_CR0_RND_MODE_SHIFT; - *mask |= BRW_CR0_RND_MODE_MASK; + elk_mode |= ELK_RND_MODE_RTNE << ELK_CR0_RND_MODE_SHIFT; + *mask |= ELK_CR0_RND_MODE_MASK; } if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP16) { - brw_mode |= BRW_CR0_FP16_DENORM_PRESERVE; - *mask |= BRW_CR0_FP16_DENORM_PRESERVE; + elk_mode |= ELK_CR0_FP16_DENORM_PRESERVE; + *mask |= ELK_CR0_FP16_DENORM_PRESERVE; } if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP32) { - brw_mode |= BRW_CR0_FP32_DENORM_PRESERVE; - *mask |= BRW_CR0_FP32_DENORM_PRESERVE; + elk_mode |= ELK_CR0_FP32_DENORM_PRESERVE; + *mask |= ELK_CR0_FP32_DENORM_PRESERVE; } if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP64) { - brw_mode |= BRW_CR0_FP64_DENORM_PRESERVE; - *mask |= BRW_CR0_FP64_DENORM_PRESERVE; + elk_mode |= ELK_CR0_FP64_DENORM_PRESERVE; + *mask |= ELK_CR0_FP64_DENORM_PRESERVE; } if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16) - *mask |= BRW_CR0_FP16_DENORM_PRESERVE; + *mask |= ELK_CR0_FP16_DENORM_PRESERVE; if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) - *mask |= BRW_CR0_FP32_DENORM_PRESERVE; + *mask |= ELK_CR0_FP32_DENORM_PRESERVE; if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64) - *mask |= BRW_CR0_FP64_DENORM_PRESERVE; + *mask |= ELK_CR0_FP64_DENORM_PRESERVE; if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE) - *mask |= BRW_CR0_FP_MODE_MASK; + *mask |= ELK_CR0_FP_MODE_MASK; if (*mask != 0) - assert((*mask & brw_mode) == brw_mode); + assert((*mask & elk_mode) == elk_mode); - return brw_mode; + return elk_mode; } static void -emit_shader_float_controls_execution_mode(nir_to_brw_state &ntb) +emit_shader_float_controls_execution_mode(nir_to_elk_state &ntb) { const fs_builder &bld = ntb.bld; - fs_visitor &s = ntb.s; + elk_fs_visitor &s = ntb.s; unsigned execution_mode = s.nir->info.float_controls_execution_mode; if (execution_mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE) @@ -7859,19 +7859,19 @@ emit_shader_float_controls_execution_mode(nir_to_brw_state &ntb) fs_builder ubld = bld.exec_all().group(1, 0); fs_builder abld = ubld.annotate("shader floats control execution mode"); - unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask); + unsigned mask, mode = elk_rnd_mode_from_nir(execution_mode, &mask); if (mask == 0) return; - abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(), - brw_imm_d(mode), brw_imm_d(mask)); + abld.emit(ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(), + elk_imm_d(mode), elk_imm_d(mask)); } void -nir_to_brw(fs_visitor *s) +nir_to_elk(elk_fs_visitor *s) { - nir_to_brw_state ntb = { + nir_to_elk_state ntb = { .s = *s, .nir = s->nir, .devinfo = s->devinfo, @@ -7891,7 +7891,7 @@ nir_to_brw(fs_visitor *s) fs_nir_emit_impl(ntb, nir_shader_get_entrypoint((nir_shader *)ntb.nir)); - ntb.bld.emit(SHADER_OPCODE_HALT_TARGET); + ntb.bld.emit(ELK_SHADER_OPCODE_HALT_TARGET); ralloc_free(ntb.mem_ctx); } diff --git a/src/intel/compiler/elk/elk_fs_reg_allocate.cpp b/src/intel/compiler/elk/elk_fs_reg_allocate.cpp index 671b6fd14d9..7cfb591124f 100644 --- a/src/intel/compiler/elk/elk_fs_reg_allocate.cpp +++ b/src/intel/compiler/elk/elk_fs_reg_allocate.cpp @@ -38,7 +38,7 @@ using namespace elk; static void assign_reg(const struct intel_device_info *devinfo, - unsigned *reg_hw_locations, fs_reg *reg) + unsigned *reg_hw_locations, elk_fs_reg *reg) { if (reg->file == VGRF) { reg->nr = reg_unit(devinfo) * reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; @@ -47,7 +47,7 @@ assign_reg(const struct intel_device_info *devinfo, } void -fs_visitor::assign_regs_trivial() +elk_fs_visitor::assign_regs_trivial() { unsigned hw_reg_mapping[this->alloc.count + 1]; unsigned i; @@ -62,7 +62,7 @@ fs_visitor::assign_regs_trivial() } this->grf_used = hw_reg_mapping[this->alloc.count]; - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { assign_reg(devinfo, hw_reg_mapping, &inst->dst); for (i = 0; i < inst->sources; i++) { assign_reg(devinfo, hw_reg_mapping, &inst->src[i]); @@ -88,10 +88,10 @@ aligned_bary_size(unsigned dispatch_width) } static void -brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) +elk_alloc_reg_set(struct elk_compiler *compiler, int dispatch_width) { const struct intel_device_info *devinfo = compiler->devinfo; - int base_reg_count = BRW_MAX_GRF; + int base_reg_count = ELK_MAX_GRF; const int index = util_logbase2(dispatch_width / 8); if (dispatch_width > 8 && devinfo->ver >= 7) { @@ -123,7 +123,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) for (unsigned i = 0; i < REG_CLASS_COUNT; i++) class_sizes[i] = i + 1; - struct ra_regs *regs = ra_alloc_reg_set(compiler, BRW_MAX_GRF, false); + struct ra_regs *regs = ra_alloc_reg_set(compiler, ELK_MAX_GRF, false); if (devinfo->ver >= 6) ra_set_allocate_round_robin(regs); struct ra_class **classes = ralloc_array(compiler, struct ra_class *, @@ -178,17 +178,17 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) } void -brw_fs_alloc_reg_sets(struct brw_compiler *compiler) +elk_fs_alloc_reg_sets(struct elk_compiler *compiler) { - brw_alloc_reg_set(compiler, 8); - brw_alloc_reg_set(compiler, 16); - brw_alloc_reg_set(compiler, 32); + elk_alloc_reg_set(compiler, 8); + elk_alloc_reg_set(compiler, 16); + elk_alloc_reg_set(compiler, 32); } static int -count_to_loop_end(const bblock_t *block) +count_to_loop_end(const elk_bblock_t *block) { - if (block->end()->opcode == BRW_OPCODE_WHILE) + if (block->end()->opcode == ELK_OPCODE_WHILE) return block->end_ip; int depth = 1; @@ -198,9 +198,9 @@ count_to_loop_end(const bblock_t *block) for (block = block->next(); depth > 0; block = block->next()) { - if (block->start()->opcode == BRW_OPCODE_DO) + if (block->start()->opcode == ELK_OPCODE_DO) depth++; - if (block->end()->opcode == BRW_OPCODE_WHILE) { + if (block->end()->opcode == ELK_OPCODE_WHILE) { depth--; if (depth == 0) return block->end_ip; @@ -209,7 +209,7 @@ count_to_loop_end(const bblock_t *block) unreachable("not reached"); } -void fs_visitor::calculate_payload_ranges(unsigned payload_node_count, +void elk_fs_visitor::calculate_payload_ranges(unsigned payload_node_count, int *payload_last_use_ip) const { int loop_depth = 0; @@ -219,9 +219,9 @@ void fs_visitor::calculate_payload_ranges(unsigned payload_node_count, payload_last_use_ip[i] = -1; int ip = 0; - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { switch (inst->opcode) { - case BRW_OPCODE_DO: + case ELK_OPCODE_DO: loop_depth++; /* Since payload regs are deffed only at the start of the shader @@ -232,7 +232,7 @@ void fs_visitor::calculate_payload_ranges(unsigned payload_node_count, if (loop_depth == 1) loop_end_ip = count_to_loop_end(block); break; - case BRW_OPCODE_WHILE: + case ELK_OPCODE_WHILE: loop_depth--; break; default: @@ -280,7 +280,7 @@ void fs_visitor::calculate_payload_ranges(unsigned payload_node_count, /* Special case instructions which have extra implied registers used. */ switch (inst->opcode) { - case CS_OPCODE_CS_TERMINATE: + case ELK_CS_OPCODE_CS_TERMINATE: payload_last_use_ip[0] = use_ip; break; @@ -302,9 +302,9 @@ void fs_visitor::calculate_payload_ranges(unsigned payload_node_count, } } -class fs_reg_alloc { +class elk_fs_reg_alloc { public: - fs_reg_alloc(fs_visitor *fs): + elk_fs_reg_alloc(elk_fs_visitor *fs): fs(fs), devinfo(fs->devinfo), compiler(fs->compiler), live(fs->live_analysis.require()), g(NULL), have_spill_costs(false) @@ -345,7 +345,7 @@ public: spill_node_count = 0; } - ~fs_reg_alloc() + ~elk_fs_reg_alloc() { ralloc_free(mem_ctx); } @@ -355,31 +355,31 @@ public: private: void setup_live_interference(unsigned node, int node_start_ip, int node_end_ip); - void setup_inst_interference(const fs_inst *inst); + void setup_inst_interference(const elk_fs_inst *inst); void build_interference_graph(bool allow_spilling); void discard_interference_graph(); - fs_reg build_lane_offsets(const fs_builder &bld, + elk_fs_reg build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, int ip); - fs_reg build_single_offset(const fs_builder &bld, + elk_fs_reg build_single_offset(const fs_builder &bld, uint32_t spill_offset, int ip); void emit_unspill(const fs_builder &bld, struct shader_stats *stats, - fs_reg dst, uint32_t spill_offset, unsigned count, int ip); + elk_fs_reg dst, uint32_t spill_offset, unsigned count, int ip); void emit_spill(const fs_builder &bld, struct shader_stats *stats, - fs_reg src, uint32_t spill_offset, unsigned count, int ip); + elk_fs_reg src, uint32_t spill_offset, unsigned count, int ip); void set_spill_costs(); int choose_spill_reg(); - fs_reg alloc_scratch_header(); - fs_reg alloc_spill_reg(unsigned size, int ip); + elk_fs_reg alloc_scratch_header(); + elk_fs_reg alloc_spill_reg(unsigned size, int ip); void spill_reg(unsigned spill_reg); void *mem_ctx; - fs_visitor *fs; + elk_fs_visitor *fs; const intel_device_info *devinfo; - const brw_compiler *compiler; + const elk_compiler *compiler; const fs_live_variables &live; int live_instr_count; @@ -407,7 +407,7 @@ private: int spill_vgrf_ip_alloc; int spill_node_count; - fs_reg scratch_header; + elk_fs_reg scratch_header; }; /** @@ -419,18 +419,18 @@ private: * contents. */ static void -get_used_mrfs(const fs_visitor *v, bool *mrf_used) +get_used_mrfs(const elk_fs_visitor *v, bool *mrf_used) { int reg_width = v->dispatch_width / 8; - memset(mrf_used, 0, BRW_MAX_MRF(v->devinfo->ver) * sizeof(bool)); + memset(mrf_used, 0, ELK_MAX_MRF(v->devinfo->ver) * sizeof(bool)); - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, v->cfg) { if (inst->dst.file == MRF) { - int reg = inst->dst.nr & ~BRW_MRF_COMPR4; + int reg = inst->dst.nr & ~ELK_MRF_COMPR4; mrf_used[reg] = true; if (reg_width == 2) { - if (inst->dst.nr & BRW_MRF_COMPR4) { + if (inst->dst.nr & ELK_MRF_COMPR4) { mrf_used[reg + 4] = true; } else { mrf_used[reg + 1] = true; @@ -463,7 +463,7 @@ namespace { * into multiple (force_writemask_all) scratch messages. */ unsigned - spill_max_size(const backend_shader *s) + spill_max_size(const elk_backend_shader *s) { /* LSC is limited to SIMD16 sends */ if (s->devinfo->has_lsc) @@ -475,26 +475,26 @@ namespace { * scratch write header). */ /* FINISHME - The shader's dispatch width probably belongs in - * backend_shader (or some nonexistent fs_shader class?) + * elk_backend_shader (or some nonexistent fs_shader class?) * rather than in the visitor class. */ - return static_cast(s)->dispatch_width / 8; + return static_cast(s)->dispatch_width / 8; } /** * First MRF register available for spilling. */ unsigned - spill_base_mrf(const backend_shader *s) + spill_base_mrf(const elk_backend_shader *s) { /* We don't use the MRF hack on Gfx9+ */ assert(s->devinfo->ver < 9); - return BRW_MAX_MRF(s->devinfo->ver) - spill_max_size(s) - 1; + return ELK_MAX_MRF(s->devinfo->ver) - spill_max_size(s) - 1; } } void -fs_reg_alloc::setup_live_interference(unsigned node, +elk_fs_reg_alloc::setup_live_interference(unsigned node, int node_start_ip, int node_end_ip) { /* Mark any virtual grf that is live between the start of the program and @@ -516,7 +516,7 @@ fs_reg_alloc::setup_live_interference(unsigned node, * MRF registers. */ if (first_mrf_hack_node >= 0) { - for (int i = spill_base_mrf(fs); i < BRW_MAX_MRF(devinfo->ver); i++) + for (int i = spill_base_mrf(fs); i < ELK_MAX_MRF(devinfo->ver); i++) ra_add_node_interference(g, node, first_mrf_hack_node + i); } @@ -538,7 +538,7 @@ fs_reg_alloc::setup_live_interference(unsigned node, } void -fs_reg_alloc::setup_inst_interference(const fs_inst *inst) +elk_fs_reg_alloc::setup_inst_interference(const elk_fs_inst *inst) { /* Certain instructions can't safely use the same register for their * sources and destination. Add interference. @@ -597,8 +597,8 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst) * message as source. So as we will have an overlap for sure, we create * an interference between destination and grf127. */ - if ((inst->opcode == SHADER_OPCODE_GFX7_SCRATCH_READ || - inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_READ) && + if ((inst->opcode == ELK_SHADER_OPCODE_GFX7_SCRATCH_READ || + inst->opcode == ELK_SHADER_OPCODE_GFX4_SCRATCH_READ) && inst->dst.file == VGRF) ra_add_node_interference(g, first_vgrf_node + inst->dst.nr, grf127_send_hack_node); @@ -616,7 +616,7 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst) * interference here. */ if (devinfo->ver >= 9) { - if (inst->opcode == SHADER_OPCODE_SEND && inst->ex_mlen > 0 && + if (inst->opcode == ELK_SHADER_OPCODE_SEND && inst->ex_mlen > 0 && inst->src[2].file == VGRF && inst->src[3].file == VGRF && inst->src[2].nr != inst->src[3].nr) ra_add_node_interference(g, first_vgrf_node + inst->src[2].nr, @@ -633,17 +633,17 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst) * register that works. */ if (inst->eot) { - const int vgrf = inst->opcode == SHADER_OPCODE_SEND ? + const int vgrf = inst->opcode == ELK_SHADER_OPCODE_SEND ? inst->src[2].nr : inst->src[0].nr; const int size = DIV_ROUND_UP(fs->alloc.sizes[vgrf], reg_unit(devinfo)); - int reg = BRW_MAX_GRF - size; + int reg = ELK_MAX_GRF - size; if (first_mrf_hack_node >= 0) { /* If something happened to spill, we want to push the EOT send * register early enough in the register file that we don't * conflict with any used MRF hack registers. */ - reg -= BRW_MAX_MRF(devinfo->ver) - spill_base_mrf(fs); + reg -= ELK_MAX_MRF(devinfo->ver) - spill_base_mrf(fs); } else if (grf127_send_hack_node >= 0) { /* Avoid r127 which might be unusable if the node was previously * written by a SIMD8 SEND message with source/destination overlap. @@ -662,7 +662,7 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst) } void -fs_reg_alloc::build_interference_graph(bool allow_spilling) +elk_fs_reg_alloc::build_interference_graph(bool allow_spilling) { /* Compute the RA node layout */ node_count = 0; @@ -670,7 +670,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling) node_count += payload_node_count; if (devinfo->ver >= 7 && devinfo->ver < 9 && allow_spilling) { first_mrf_hack_node = node_count; - node_count += BRW_MAX_GRF - GFX7_MRF_HACK_START; + node_count += ELK_MAX_GRF - GFX7_MRF_HACK_START; } else { first_mrf_hack_node = -1; } @@ -708,7 +708,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling) * The alternative would be to have per-physical-register classes, * which would just be silly. */ - for (int i = 0; i < BRW_MAX_MRF(devinfo->ver); i++) { + for (int i = 0; i < ELK_MAX_MRF(devinfo->ver); i++) { ra_set_node_reg(g, first_mrf_hack_node + i, GFX7_MRF_HACK_START + i); } @@ -733,8 +733,8 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling) * special register class aligned_bary_class to handle this case. */ if (compiler->fs_reg_sets[rsi].aligned_bary_class) { - foreach_block_and_inst(block, fs_inst, inst, fs->cfg) { - if (inst->opcode == FS_OPCODE_LINTERP && inst->src[0].file == VGRF && + foreach_block_and_inst(block, elk_fs_inst, inst, fs->cfg) { + if (inst->opcode == ELK_FS_OPCODE_LINTERP && inst->src[0].file == VGRF && fs->alloc.sizes[inst->src[0].nr] == aligned_bary_size(fs->dispatch_width)) { ra_set_node_class(g, first_vgrf_node + inst->src[0].nr, @@ -752,29 +752,29 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling) /* Add interference based on the instructions in which a register is used. */ - foreach_block_and_inst(block, fs_inst, inst, fs->cfg) + foreach_block_and_inst(block, elk_fs_inst, inst, fs->cfg) setup_inst_interference(inst); } void -fs_reg_alloc::discard_interference_graph() +elk_fs_reg_alloc::discard_interference_graph() { ralloc_free(g); g = NULL; have_spill_costs = false; } -fs_reg -fs_reg_alloc::build_single_offset(const fs_builder &bld, uint32_t spill_offset, int ip) +elk_fs_reg +elk_fs_reg_alloc::build_single_offset(const fs_builder &bld, uint32_t spill_offset, int ip) { - fs_reg offset = retype(alloc_spill_reg(1, ip), BRW_REGISTER_TYPE_UD); - fs_inst *inst = bld.MOV(offset, brw_imm_ud(spill_offset)); + elk_fs_reg offset = retype(alloc_spill_reg(1, ip), ELK_REGISTER_TYPE_UD); + elk_fs_inst *inst = bld.MOV(offset, elk_imm_ud(spill_offset)); _mesa_set_add(spill_insts, inst); return offset; } -fs_reg -fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, int ip) +elk_fs_reg +elk_fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, int ip) { /* LSC messages are limited to SIMD16 */ assert(bld.dispatch_width() <= 16); @@ -782,14 +782,14 @@ fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, i const fs_builder ubld = bld.exec_all(); const unsigned reg_count = ubld.dispatch_width() / 8; - fs_reg offset = retype(alloc_spill_reg(reg_count, ip), BRW_REGISTER_TYPE_UD); - fs_inst *inst; + elk_fs_reg offset = retype(alloc_spill_reg(reg_count, ip), ELK_REGISTER_TYPE_UD); + elk_fs_inst *inst; /* Build an offset per lane in SIMD8 */ - inst = ubld.group(8, 0).MOV(retype(offset, BRW_REGISTER_TYPE_UW), - brw_imm_uv(0x76543210)); + inst = ubld.group(8, 0).MOV(retype(offset, ELK_REGISTER_TYPE_UW), + elk_imm_uv(0x76543210)); _mesa_set_add(spill_insts, inst); - inst = ubld.group(8, 0).MOV(offset, retype(offset, BRW_REGISTER_TYPE_UW)); + inst = ubld.group(8, 0).MOV(offset, retype(offset, ELK_REGISTER_TYPE_UW)); _mesa_set_add(spill_insts, inst); /* Build offsets in the upper 8 lanes of SIMD16 */ @@ -797,25 +797,25 @@ fs_reg_alloc::build_lane_offsets(const fs_builder &bld, uint32_t spill_offset, i inst = ubld.group(8, 0).ADD( byte_offset(offset, REG_SIZE), byte_offset(offset, 0), - brw_imm_ud(8)); + elk_imm_ud(8)); _mesa_set_add(spill_insts, inst); } /* Make the offset a dword */ - inst = ubld.SHL(offset, offset, brw_imm_ud(2)); + inst = ubld.SHL(offset, offset, elk_imm_ud(2)); _mesa_set_add(spill_insts, inst); /* Add the base offset */ - inst = ubld.ADD(offset, offset, brw_imm_ud(spill_offset)); + inst = ubld.ADD(offset, offset, elk_imm_ud(spill_offset)); _mesa_set_add(spill_insts, inst); return offset; } void -fs_reg_alloc::emit_unspill(const fs_builder &bld, +elk_fs_reg_alloc::emit_unspill(const fs_builder &bld, struct shader_stats *stats, - fs_reg dst, + elk_fs_reg dst, uint32_t spill_offset, unsigned count, int ip) { const intel_device_info *devinfo = bld.shader->devinfo; @@ -826,14 +826,14 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, for (unsigned i = 0; i < count / reg_size; i++) { ++stats->fill_count; - fs_inst *unspill_inst; + elk_fs_inst *unspill_inst; if (devinfo->verx10 >= 125) { /* LSC is limited to SIMD16 load/store but we can load more using * transpose messages. */ const bool use_transpose = bld.dispatch_width() > 16; const fs_builder ubld = use_transpose ? bld.exec_all().group(1, 0) : bld; - fs_reg offset; + elk_fs_reg offset; if (use_transpose) { offset = build_single_offset(ubld, spill_offset, ip); } else { @@ -844,14 +844,14 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, * register. That way we don't need to burn an additional register * for register allocation spill/fill. */ - fs_reg srcs[] = { - brw_imm_ud(0), /* desc */ - brw_imm_ud(0), /* ex_desc */ + elk_fs_reg srcs[] = { + elk_imm_ud(0), /* desc */ + elk_imm_ud(0), /* ex_desc */ offset, /* payload */ - fs_reg(), /* payload2 */ + elk_fs_reg(), /* payload2 */ }; - unspill_inst = ubld.emit(SHADER_OPCODE_SEND, dst, + unspill_inst = ubld.emit(ELK_SHADER_OPCODE_SEND, dst, srcs, ARRAY_SIZE(srcs)); unspill_inst->sfid = GFX12_SFID_UGM; unspill_inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, @@ -874,18 +874,18 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, unspill_inst->send_is_volatile = true; unspill_inst->send_ex_desc_scratch = true; } else if (devinfo->ver >= 9) { - fs_reg header = this->scratch_header; + elk_fs_reg header = this->scratch_header; fs_builder ubld = bld.exec_all().group(1, 0); assert(spill_offset % 16 == 0); unspill_inst = ubld.MOV(component(header, 2), - brw_imm_ud(spill_offset / 16)); + elk_imm_ud(spill_offset / 16)); _mesa_set_add(spill_insts, unspill_inst); const unsigned bti = GFX8_BTI_STATELESS_NON_COHERENT; - const fs_reg ex_desc = brw_imm_ud(0); + const elk_fs_reg ex_desc = elk_imm_ud(0); - fs_reg srcs[] = { brw_imm_ud(0), ex_desc, header }; - unspill_inst = bld.emit(SHADER_OPCODE_SEND, dst, + elk_fs_reg srcs[] = { elk_imm_ud(0), ex_desc, header }; + unspill_inst = bld.emit(ELK_SHADER_OPCODE_SEND, dst, srcs, ARRAY_SIZE(srcs)); unspill_inst->mlen = 1; unspill_inst->header_size = 1; @@ -894,9 +894,9 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, unspill_inst->send_is_volatile = true; unspill_inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE; unspill_inst->desc = - brw_dp_desc(devinfo, bti, - BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, - BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8)); + elk_dp_desc(devinfo, bti, + ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, + ELK_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8)); } else if (devinfo->ver >= 7 && spill_offset < (1 << 12) * REG_SIZE) { /* The Gfx7 descriptor-based offset is 12 bits of HWORD units. * Because the Gfx7-style scratch block read is hardwired to BTI 255, @@ -905,10 +905,10 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, * the address as part of the message header, so we're better off * using plain old oword block reads. */ - unspill_inst = bld.emit(SHADER_OPCODE_GFX7_SCRATCH_READ, dst); + unspill_inst = bld.emit(ELK_SHADER_OPCODE_GFX7_SCRATCH_READ, dst); unspill_inst->offset = spill_offset; } else { - unspill_inst = bld.emit(SHADER_OPCODE_GFX4_SCRATCH_READ, dst); + unspill_inst = bld.emit(ELK_SHADER_OPCODE_GFX4_SCRATCH_READ, dst); unspill_inst->offset = spill_offset; unspill_inst->base_mrf = spill_base_mrf(bld.shader); unspill_inst->mlen = 1; /* header contains offset */ @@ -921,9 +921,9 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, } void -fs_reg_alloc::emit_spill(const fs_builder &bld, +elk_fs_reg_alloc::emit_spill(const fs_builder &bld, struct shader_stats *stats, - fs_reg src, + elk_fs_reg src, uint32_t spill_offset, unsigned count, int ip) { const intel_device_info *devinfo = bld.shader->devinfo; @@ -934,21 +934,21 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, for (unsigned i = 0; i < count / reg_size; i++) { ++stats->spill_count; - fs_inst *spill_inst; + elk_fs_inst *spill_inst; if (devinfo->verx10 >= 125) { - fs_reg offset = build_lane_offsets(bld, spill_offset, ip); + elk_fs_reg offset = build_lane_offsets(bld, spill_offset, ip); /* We leave the extended descriptor empty and flag the instruction * relocate the extended descriptor. That way the surface offset is * directly put into the instruction and we don't need to use a * register to hold it. */ - fs_reg srcs[] = { - brw_imm_ud(0), /* desc */ - brw_imm_ud(0), /* ex_desc */ + elk_fs_reg srcs[] = { + elk_imm_ud(0), /* desc */ + elk_imm_ud(0), /* ex_desc */ offset, /* payload */ src, /* payload2 */ }; - spill_inst = bld.emit(SHADER_OPCODE_SEND, bld.null_reg_f(), + spill_inst = bld.emit(ELK_SHADER_OPCODE_SEND, bld.null_reg_f(), srcs, ARRAY_SIZE(srcs)); spill_inst->sfid = GFX12_SFID_UGM; spill_inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE, @@ -969,18 +969,18 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, spill_inst->send_is_volatile = false; spill_inst->send_ex_desc_scratch = true; } else if (devinfo->ver >= 9) { - fs_reg header = this->scratch_header; + elk_fs_reg header = this->scratch_header; fs_builder ubld = bld.exec_all().group(1, 0); assert(spill_offset % 16 == 0); spill_inst = ubld.MOV(component(header, 2), - brw_imm_ud(spill_offset / 16)); + elk_imm_ud(spill_offset / 16)); _mesa_set_add(spill_insts, spill_inst); const unsigned bti = GFX8_BTI_STATELESS_NON_COHERENT; - const fs_reg ex_desc = brw_imm_ud(0); + const elk_fs_reg ex_desc = elk_imm_ud(0); - fs_reg srcs[] = { brw_imm_ud(0), ex_desc, header, src }; - spill_inst = bld.emit(SHADER_OPCODE_SEND, bld.null_reg_f(), + elk_fs_reg srcs[] = { elk_imm_ud(0), ex_desc, header, src }; + spill_inst = bld.emit(ELK_SHADER_OPCODE_SEND, bld.null_reg_f(), srcs, ARRAY_SIZE(srcs)); spill_inst->mlen = 1; spill_inst->ex_mlen = reg_size; @@ -990,11 +990,11 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, spill_inst->send_is_volatile = false; spill_inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE; spill_inst->desc = - brw_dp_desc(devinfo, bti, + elk_dp_desc(devinfo, bti, GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE, - BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8)); + ELK_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8)); } else { - spill_inst = bld.emit(SHADER_OPCODE_GFX4_SCRATCH_WRITE, + spill_inst = bld.emit(ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE, bld.null_reg_f(), src); spill_inst->offset = spill_offset; spill_inst->mlen = 1 + reg_size; /* header, value */ @@ -1008,7 +1008,7 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, } void -fs_reg_alloc::set_spill_costs() +elk_fs_reg_alloc::set_spill_costs() { float block_scale = 1.0; float spill_costs[fs->alloc.count]; @@ -1023,7 +1023,7 @@ fs_reg_alloc::set_spill_costs() * spill/unspill we'll have to do, and guess that the insides of * loops run 10 times. */ - foreach_block_and_inst(block, fs_inst, inst, fs->cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, fs->cfg) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == VGRF) spill_costs[inst->src[i].nr] += regs_read(inst, i) * block_scale; @@ -1044,20 +1044,20 @@ fs_reg_alloc::set_spill_costs() switch (inst->opcode) { - case BRW_OPCODE_DO: + case ELK_OPCODE_DO: block_scale *= 10; break; - case BRW_OPCODE_WHILE: + case ELK_OPCODE_WHILE: block_scale /= 10; break; - case BRW_OPCODE_IF: - case BRW_OPCODE_IFF: + case ELK_OPCODE_IF: + case ELK_OPCODE_IFF: block_scale *= 0.5; break; - case BRW_OPCODE_ENDIF: + case ELK_OPCODE_ENDIF: block_scale /= 0.5; break; @@ -1095,7 +1095,7 @@ fs_reg_alloc::set_spill_costs() } int -fs_reg_alloc::choose_spill_reg() +elk_fs_reg_alloc::choose_spill_reg() { if (!have_spill_costs) set_spill_costs(); @@ -1108,8 +1108,8 @@ fs_reg_alloc::choose_spill_reg() return node - first_vgrf_node; } -fs_reg -fs_reg_alloc::alloc_scratch_header() +elk_fs_reg +elk_fs_reg_alloc::alloc_scratch_header() { int vgrf = fs->alloc.allocate(1); assert(first_vgrf_node + vgrf == scratch_header_node); @@ -1118,11 +1118,11 @@ fs_reg_alloc::alloc_scratch_header() setup_live_interference(scratch_header_node, 0, INT_MAX); - return fs_reg(VGRF, vgrf, BRW_REGISTER_TYPE_UD); + return elk_fs_reg(VGRF, vgrf, ELK_REGISTER_TYPE_UD); } -fs_reg -fs_reg_alloc::alloc_spill_reg(unsigned size, int ip) +elk_fs_reg +elk_fs_reg_alloc::alloc_spill_reg(unsigned size, int ip) { int vgrf = fs->alloc.allocate(ALIGN(size, reg_unit(devinfo))); int class_idx = DIV_ROUND_UP(size, reg_unit(devinfo)) - 1; @@ -1151,11 +1151,11 @@ fs_reg_alloc::alloc_spill_reg(unsigned size, int ip) } spill_vgrf_ip[spill_node_count++] = ip; - return fs_reg(VGRF, vgrf); + return elk_fs_reg(VGRF, vgrf); } void -fs_reg_alloc::spill_reg(unsigned spill_reg) +elk_fs_reg_alloc::spill_reg(unsigned spill_reg) { int size = fs->alloc.sizes[spill_reg]; unsigned int spill_offset = fs->last_scratch; @@ -1176,14 +1176,14 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) fs_builder ubld = fs_builder(fs, 8).exec_all().at( fs->cfg->first_block(), fs->cfg->first_block()->start()); - fs_inst *inst = ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, + elk_fs_inst *inst = ubld.emit(ELK_SHADER_OPCODE_SCRATCH_HEADER, this->scratch_header); _mesa_set_add(spill_insts, inst); } else { - bool mrf_used[BRW_MAX_MRF(devinfo->ver)]; + bool mrf_used[ELK_MAX_MRF(devinfo->ver)]; get_used_mrfs(fs, mrf_used); - for (int i = spill_base_mrf(fs); i < BRW_MAX_MRF(devinfo->ver); i++) { + for (int i = spill_base_mrf(fs); i < ELK_MAX_MRF(devinfo->ver); i++) { if (mrf_used[i]) { fs->fail("Register spilling not supported with m%d used", i); return; @@ -1208,7 +1208,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) * could just spill/unspill the GRF being accessed. */ int ip = 0; - foreach_block_and_inst (block, fs_inst, inst, fs->cfg) { + foreach_block_and_inst (block, elk_fs_inst, inst, fs->cfg) { const fs_builder ibld = fs_builder(fs, block, inst); exec_node *before = inst->prev; exec_node *after = inst->next; @@ -1219,7 +1219,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) int count = regs_read(inst, i); int subset_spill_offset = spill_offset + ROUND_DOWN_TO(inst->src[i].offset, REG_SIZE); - fs_reg unspill_dst = alloc_spill_reg(count, ip); + elk_fs_reg unspill_dst = alloc_spill_reg(count, ip); inst->src[i].nr = unspill_dst.nr; inst->src[i].offset %= REG_SIZE; @@ -1245,10 +1245,10 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) if (inst->dst.file == VGRF && inst->dst.nr == spill_reg && - inst->opcode != SHADER_OPCODE_UNDEF) { + inst->opcode != ELK_SHADER_OPCODE_UNDEF) { int subset_spill_offset = spill_offset + ROUND_DOWN_TO(inst->dst.offset, REG_SIZE); - fs_reg spill_src = alloc_spill_reg(regs_written(inst), ip); + elk_fs_reg spill_src = alloc_spill_reg(regs_written(inst), ip); inst->dst.nr = spill_src.nr; inst->dst.offset %= REG_SIZE; @@ -1301,8 +1301,8 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) subset_spill_offset, regs_written(inst), ip); } - for (fs_inst *inst = (fs_inst *)before->next; - inst != after; inst = (fs_inst *)inst->next) + for (elk_fs_inst *inst = (elk_fs_inst *)before->next; + inst != after; inst = (elk_fs_inst *)inst->next) setup_inst_interference(inst); /* We don't advance the ip for scratch read/write instructions @@ -1319,7 +1319,7 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) } bool -fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all) +elk_fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all) { build_interference_graph(fs->spilled_any_registers || spill_all); @@ -1387,7 +1387,7 @@ fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all) reg_unit(devinfo))); } - foreach_block_and_inst(block, fs_inst, inst, fs->cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, fs->cfg) { assign_reg(devinfo, hw_reg_mapping, &inst->dst); for (int i = 0; i < inst->sources; i++) { assign_reg(devinfo, hw_reg_mapping, &inst->src[i]); @@ -1400,9 +1400,9 @@ fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all) } bool -fs_visitor::assign_regs(bool allow_spilling, bool spill_all) +elk_fs_visitor::assign_regs(bool allow_spilling, bool spill_all) { - fs_reg_alloc alloc(this); + elk_fs_reg_alloc alloc(this); bool success = alloc.assign_regs(allow_spilling, spill_all); if (!success && allow_spilling) { fail("no register to spill:\n"); diff --git a/src/intel/compiler/elk/elk_fs_register_coalesce.cpp b/src/intel/compiler/elk/elk_fs_register_coalesce.cpp index 5b71be0a4c8..b42596a68fc 100644 --- a/src/intel/compiler/elk/elk_fs_register_coalesce.cpp +++ b/src/intel/compiler/elk/elk_fs_register_coalesce.cpp @@ -47,10 +47,10 @@ using namespace elk; static bool -is_nop_mov(const fs_inst *inst) +is_nop_mov(const elk_fs_inst *inst) { - if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { - fs_reg dst = inst->dst; + if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD) { + elk_fs_reg dst = inst->dst; for (int i = 0; i < inst->sources; i++) { if (!dst.equals(inst->src[i])) { return false; @@ -60,7 +60,7 @@ is_nop_mov(const fs_inst *inst) type_sz(inst->src[i].type)); } return true; - } else if (inst->opcode == BRW_OPCODE_MOV) { + } else if (inst->opcode == ELK_OPCODE_MOV) { return inst->dst.equals(inst->src[0]); } @@ -68,10 +68,10 @@ is_nop_mov(const fs_inst *inst) } static bool -is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst) +is_coalesce_candidate(const elk_fs_visitor *v, const elk_fs_inst *inst) { - if ((inst->opcode != BRW_OPCODE_MOV && - inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) || + if ((inst->opcode != ELK_OPCODE_MOV && + inst->opcode != ELK_SHADER_OPCODE_LOAD_PAYLOAD) || inst->is_partial_write() || inst->saturate || inst->src[0].file != VGRF || @@ -87,7 +87,7 @@ is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst) v->alloc.sizes[inst->dst.nr]) return false; - if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { + if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD) { if (!is_coalescing_payload(v->alloc, inst)) { return false; } @@ -97,8 +97,8 @@ is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst) } static bool -can_coalesce_vars(const fs_live_variables &live, const cfg_t *cfg, - const bblock_t *block, const fs_inst *inst, +can_coalesce_vars(const fs_live_variables &live, const elk_cfg_t *cfg, + const elk_bblock_t *block, const elk_fs_inst *inst, int dst_var, int src_var) { if (!live.vars_interfere(src_var, dst_var)) @@ -128,7 +128,7 @@ can_coalesce_vars(const fs_live_variables &live, const cfg_t *cfg, bool seen_src_write = false; bool seen_copy = false; - foreach_inst_in_block(fs_inst, scan_inst, scan_block) { + foreach_inst_in_block(elk_fs_inst, scan_inst, scan_block) { scan_ip++; /* Ignore anything before the intersection of the live ranges */ @@ -189,7 +189,7 @@ can_coalesce_vars(const fs_live_variables &live, const cfg_t *cfg, } bool -fs_visitor::register_coalesce() +elk_fs_visitor::register_coalesce() { bool progress = false; fs_live_variables &live = live_analysis.require(); @@ -197,16 +197,16 @@ fs_visitor::register_coalesce() int channels_remaining = 0; unsigned src_reg = ~0u, dst_reg = ~0u; int *dst_reg_offset = new int[MAX_VGRF_SIZE(devinfo)]; - fs_inst **mov = new fs_inst *[MAX_VGRF_SIZE(devinfo)]; + elk_fs_inst **mov = new elk_fs_inst *[MAX_VGRF_SIZE(devinfo)]; int *dst_var = new int[MAX_VGRF_SIZE(devinfo)]; int *src_var = new int[MAX_VGRF_SIZE(devinfo)]; - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, inst, cfg) { if (!is_coalesce_candidate(this, inst)) continue; if (is_nop_mov(inst)) { - inst->opcode = BRW_OPCODE_NOP; + inst->opcode = ELK_OPCODE_NOP; progress = true; continue; } @@ -226,7 +226,7 @@ fs_visitor::register_coalesce() if (dst_reg != inst->dst.nr) continue; - if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { + if (inst->opcode == ELK_SHADER_OPCODE_LOAD_PAYLOAD) { for (int i = 0; i < src_size; i++) { dst_reg_offset[i] = i; } @@ -281,8 +281,8 @@ fs_visitor::register_coalesce() if (!mov[i]) continue; - if (mov[i]->conditional_mod == BRW_CONDITIONAL_NONE) { - mov[i]->opcode = BRW_OPCODE_NOP; + if (mov[i]->conditional_mod == ELK_CONDITIONAL_NONE) { + mov[i]->opcode = ELK_OPCODE_NOP; mov[i]->dst = reg_undef; for (int j = 0; j < mov[i]->sources; j++) { mov[i]->src[j] = reg_undef; @@ -294,14 +294,14 @@ fs_visitor::register_coalesce() * that writes the register. If not, this keeps things correct * while still letting us coalesce. */ - assert(mov[i]->opcode == BRW_OPCODE_MOV); + assert(mov[i]->opcode == ELK_OPCODE_MOV); assert(mov[i]->sources == 1); mov[i]->src[0] = mov[i]->dst; - mov[i]->dst = retype(brw_null_reg(), mov[i]->dst.type); + mov[i]->dst = retype(elk_null_reg(), mov[i]->dst.type); } } - foreach_block_and_inst(block, fs_inst, scan_inst, cfg) { + foreach_block_and_inst(block, elk_fs_inst, scan_inst, cfg) { if (scan_inst->dst.file == VGRF && scan_inst->dst.nr == src_reg) { scan_inst->dst.nr = dst_reg; @@ -329,8 +329,8 @@ fs_visitor::register_coalesce() } if (progress) { - foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) { - if (inst->opcode == BRW_OPCODE_NOP) { + foreach_block_and_inst_safe (block, elk_backend_instruction, inst, cfg) { + if (inst->opcode == ELK_OPCODE_NOP) { inst->remove(block, true); } } diff --git a/src/intel/compiler/elk/elk_fs_saturate_propagation.cpp b/src/intel/compiler/elk/elk_fs_saturate_propagation.cpp index 8a49a39296f..73910dd1f63 100644 --- a/src/intel/compiler/elk/elk_fs_saturate_propagation.cpp +++ b/src/intel/compiler/elk/elk_fs_saturate_propagation.cpp @@ -45,15 +45,15 @@ using namespace elk; */ static bool -opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block) +opt_saturate_propagation_local(const fs_live_variables &live, elk_bblock_t *block) { bool progress = false; int ip = block->end_ip + 1; - foreach_inst_in_block_reverse(fs_inst, inst, block) { + foreach_inst_in_block_reverse(elk_fs_inst, inst, block) { ip--; - if (inst->opcode != BRW_OPCODE_MOV || + if (inst->opcode != ELK_OPCODE_MOV || !inst->saturate || inst->dst.file != VGRF || inst->dst.type != inst->src[0].type || @@ -65,7 +65,7 @@ opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block) int src_end_ip = live.end[src_var]; bool interfered = false; - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(elk_fs_inst, scan_inst, inst) { if (scan_inst->exec_size == inst->exec_size && regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) { @@ -87,23 +87,23 @@ opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block) } if (inst->src[0].negate) { - if (scan_inst->opcode == BRW_OPCODE_MUL) { + if (scan_inst->opcode == ELK_OPCODE_MUL) { scan_inst->src[0].negate = !scan_inst->src[0].negate; inst->src[0].negate = false; - } else if (scan_inst->opcode == BRW_OPCODE_MAD) { + } else if (scan_inst->opcode == ELK_OPCODE_MAD) { for (int i = 0; i < 2; i++) { if (scan_inst->src[i].file == IMM) { - brw_negate_immediate(scan_inst->src[i].type, - &scan_inst->src[i].as_brw_reg()); + elk_negate_immediate(scan_inst->src[i].type, + &scan_inst->src[i].as_elk_reg()); } else { scan_inst->src[i].negate = !scan_inst->src[i].negate; } } inst->src[0].negate = false; - } else if (scan_inst->opcode == BRW_OPCODE_ADD) { + } else if (scan_inst->opcode == ELK_OPCODE_ADD) { if (scan_inst->src[1].file == IMM) { - if (!brw_negate_immediate(scan_inst->src[1].type, - &scan_inst->src[1].as_brw_reg())) { + if (!elk_negate_immediate(scan_inst->src[1].type, + &scan_inst->src[1].as_elk_reg())) { break; } } else { @@ -129,7 +129,7 @@ opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block) regions_overlap( scan_inst->src[i], scan_inst->size_read(i), inst->src[0], inst->size_read(0))) { - if (scan_inst->opcode != BRW_OPCODE_MOV || + if (scan_inst->opcode != ELK_OPCODE_MOV || !scan_inst->saturate || scan_inst->src[0].abs || scan_inst->src[0].negate || @@ -150,7 +150,7 @@ opt_saturate_propagation_local(const fs_live_variables &live, bblock_t *block) } bool -fs_visitor::opt_saturate_propagation() +elk_fs_visitor::opt_saturate_propagation() { const fs_live_variables &live = live_analysis.require(); bool progress = false; diff --git a/src/intel/compiler/elk/elk_fs_sel_peephole.cpp b/src/intel/compiler/elk/elk_fs_sel_peephole.cpp index 5090d44ae95..2458cfdaec0 100644 --- a/src/intel/compiler/elk/elk_fs_sel_peephole.cpp +++ b/src/intel/compiler/elk/elk_fs_sel_peephole.cpp @@ -44,7 +44,7 @@ using namespace elk; * Scans forwards from an IF counting consecutive MOV instructions in the * "then" and "else" blocks of the if statement. * - * A pointer to the bblock_t following the IF is passed as the + * A pointer to the elk_bblock_t following the IF is passed as the * argument. The function stores pointers to the MOV instructions in the * and arrays. * @@ -65,12 +65,12 @@ using namespace elk; */ static int count_movs_from_if(const intel_device_info *devinfo, - fs_inst *then_mov[MAX_MOVS], fs_inst *else_mov[MAX_MOVS], - bblock_t *then_block, bblock_t *else_block) + elk_fs_inst *then_mov[MAX_MOVS], elk_fs_inst *else_mov[MAX_MOVS], + elk_bblock_t *then_block, elk_bblock_t *else_block) { int then_movs = 0; - foreach_inst_in_block(fs_inst, inst, then_block) { - if (then_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV || + foreach_inst_in_block(elk_fs_inst, inst, then_block) { + if (then_movs == MAX_MOVS || inst->opcode != ELK_OPCODE_MOV || inst->flags_written(devinfo)) break; @@ -79,8 +79,8 @@ count_movs_from_if(const intel_device_info *devinfo, } int else_movs = 0; - foreach_inst_in_block(fs_inst, inst, else_block) { - if (else_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV || + foreach_inst_in_block(elk_fs_inst, inst, else_block) { + if (else_movs == MAX_MOVS || inst->opcode != ELK_OPCODE_MOV || inst->flags_written(devinfo)) break; @@ -126,7 +126,7 @@ count_movs_from_if(const intel_device_info *devinfo, * If src0 is an immediate value, we promote it to a temporary GRF. */ bool -fs_visitor::opt_peephole_sel() +elk_fs_visitor::opt_peephole_sel() { bool progress = false; @@ -134,18 +134,18 @@ fs_visitor::opt_peephole_sel() /* IF instructions, by definition, can only be found at the ends of * basic blocks. */ - fs_inst *if_inst = (fs_inst *)block->end(); - if (if_inst->opcode != BRW_OPCODE_IF) + elk_fs_inst *if_inst = (elk_fs_inst *)block->end(); + if (if_inst->opcode != ELK_OPCODE_IF) continue; - fs_inst *else_mov[MAX_MOVS] = { NULL }; - fs_inst *then_mov[MAX_MOVS] = { NULL }; + elk_fs_inst *else_mov[MAX_MOVS] = { NULL }; + elk_fs_inst *then_mov[MAX_MOVS] = { NULL }; - bblock_t *then_block = block->next(); - bblock_t *else_block = NULL; - foreach_list_typed(bblock_link, child, link, &block->children) { + elk_bblock_t *then_block = block->next(); + elk_bblock_t *else_block = NULL; + foreach_list_typed(elk_bblock_link, child, link, &block->children) { if (child->block != then_block) { - if (child->block->prev()->end()->opcode == BRW_OPCODE_ELSE) { + if (child->block->prev()->end()->opcode == ELK_OPCODE_ELSE) { else_block = child->block; } break; @@ -171,8 +171,8 @@ fs_visitor::opt_peephole_sel() then_mov[i]->force_writemask_all != else_mov[i]->force_writemask_all || then_mov[i]->is_partial_write() || else_mov[i]->is_partial_write() || - then_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE || - else_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE) { + then_mov[i]->conditional_mod != ELK_CONDITIONAL_NONE || + else_mov[i]->conditional_mod != ELK_CONDITIONAL_NONE) { movs = i; break; } @@ -198,14 +198,14 @@ fs_visitor::opt_peephole_sel() * in the "then" clause uses a constant, we need to put it in a * temporary. */ - fs_reg src0(then_mov[i]->src[0]); + elk_fs_reg src0(then_mov[i]->src[0]); if (src0.file == IMM) { src0 = ibld.vgrf(then_mov[i]->src[0].type); ibld.MOV(src0, then_mov[i]->src[0]); } /* 64-bit immediates can't be placed in src1. */ - fs_reg src1(else_mov[i]->src[0]); + elk_fs_reg src1(else_mov[i]->src[0]); if (src1.file == IMM && type_sz(src1.type) == 8) { src1 = ibld.vgrf(else_mov[i]->src[0].type); ibld.MOV(src1, else_mov[i]->src[0]); diff --git a/src/intel/compiler/elk/elk_fs_thread_payload.cpp b/src/intel/compiler/elk/elk_fs_thread_payload.cpp index 37f8a151b16..58d52df0e80 100644 --- a/src/intel/compiler/elk/elk_fs_thread_payload.cpp +++ b/src/intel/compiler/elk/elk_fs_thread_payload.cpp @@ -26,7 +26,7 @@ using namespace elk; -vs_thread_payload::vs_thread_payload(const fs_visitor &v) +elk_vs_thread_payload::elk_vs_thread_payload(const elk_fs_visitor &v) { unsigned r = 0; @@ -34,94 +34,94 @@ vs_thread_payload::vs_thread_payload(const fs_visitor &v) r += reg_unit(v.devinfo); /* R1: URB handles. */ - urb_handles = brw_ud8_grf(r, 0); + urb_handles = elk_ud8_grf(r, 0); r += reg_unit(v.devinfo); num_regs = r; } -tcs_thread_payload::tcs_thread_payload(const fs_visitor &v) +elk_tcs_thread_payload::elk_tcs_thread_payload(const elk_fs_visitor &v) { - struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data); - struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(v.prog_data); - struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) v.key; + struct elk_vue_prog_data *vue_prog_data = elk_vue_prog_data(v.prog_data); + struct elk_tcs_prog_data *tcs_prog_data = elk_tcs_prog_data(v.prog_data); + struct elk_tcs_prog_key *tcs_key = (struct elk_tcs_prog_key *) v.key; if (vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH) { - patch_urb_output = brw_ud1_grf(0, 0); - primitive_id = brw_vec1_grf(0, 1); + patch_urb_output = elk_ud1_grf(0, 0); + primitive_id = elk_vec1_grf(0, 1); /* r1-r4 contain the ICP handles. */ - icp_handle_start = brw_ud8_grf(1, 0); + icp_handle_start = elk_ud8_grf(1, 0); num_regs = 5; } else { assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH); - assert(tcs_key->input_vertices <= BRW_MAX_TCS_INPUT_VERTICES); + assert(tcs_key->input_vertices <= ELK_MAX_TCS_INPUT_VERTICES); unsigned r = 0; r += reg_unit(v.devinfo); - patch_urb_output = brw_ud8_grf(r, 0); + patch_urb_output = elk_ud8_grf(r, 0); r += reg_unit(v.devinfo); if (tcs_prog_data->include_primitive_id) { - primitive_id = brw_vec8_grf(r, 0); + primitive_id = elk_vec8_grf(r, 0); r += reg_unit(v.devinfo); } /* ICP handles occupy the next 1-32 registers. */ - icp_handle_start = brw_ud8_grf(r, 0); - r += brw_tcs_prog_key_input_vertices(tcs_key) * reg_unit(v.devinfo); + icp_handle_start = elk_ud8_grf(r, 0); + r += elk_tcs_prog_key_input_vertices(tcs_key) * reg_unit(v.devinfo); num_regs = r; } } -tes_thread_payload::tes_thread_payload(const fs_visitor &v) +elk_tes_thread_payload::elk_tes_thread_payload(const elk_fs_visitor &v) { unsigned r = 0; /* R0: Thread Header. */ - patch_urb_input = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD); - primitive_id = brw_vec1_grf(0, 1); + patch_urb_input = retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_UD); + primitive_id = elk_vec1_grf(0, 1); r += reg_unit(v.devinfo); /* R1-3: gl_TessCoord.xyz. */ for (unsigned i = 0; i < 3; i++) { - coords[i] = brw_vec8_grf(r, 0); + coords[i] = elk_vec8_grf(r, 0); r += reg_unit(v.devinfo); } /* R4: URB output handles. */ - urb_output = brw_ud8_grf(r, 0); + urb_output = elk_ud8_grf(r, 0); r += reg_unit(v.devinfo); num_regs = r; } -gs_thread_payload::gs_thread_payload(fs_visitor &v) +elk_gs_thread_payload::elk_gs_thread_payload(elk_fs_visitor &v) { - struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data); - struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(v.prog_data); + struct elk_vue_prog_data *vue_prog_data = elk_vue_prog_data(v.prog_data); + struct elk_gs_prog_data *gs_prog_data = elk_gs_prog_data(v.prog_data); const fs_builder bld = fs_builder(&v).at_end(); /* R0: thread header. */ unsigned r = reg_unit(v.devinfo); /* R1: output URB handles. */ - urb_handles = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.AND(urb_handles, brw_ud8_grf(r, 0), - v.devinfo->ver >= 20 ? brw_imm_ud(0xFFFFFF) : brw_imm_ud(0xFFFF)); + urb_handles = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.AND(urb_handles, elk_ud8_grf(r, 0), + v.devinfo->ver >= 20 ? elk_imm_ud(0xFFFFFF) : elk_imm_ud(0xFFFF)); /* R1: Instance ID stored in bits 31:27 */ - instance_id = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.SHR(instance_id, brw_ud8_grf(r, 0), brw_imm_ud(27u)); + instance_id = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.SHR(instance_id, elk_ud8_grf(r, 0), elk_imm_ud(27u)); r += reg_unit(v.devinfo); if (gs_prog_data->include_primitive_id) { - primitive_id = brw_ud8_grf(r, 0); + primitive_id = elk_ud8_grf(r, 0); r += reg_unit(v.devinfo); } @@ -134,7 +134,7 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v) gs_prog_data->base.include_vue_handles = true; /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */ - icp_handle_start = brw_ud8_grf(r, 0); + icp_handle_start = elk_ud8_grf(r, 0); r += v.nir->info.gs.vertices_in * reg_unit(v.devinfo); num_regs = r; @@ -156,11 +156,11 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v) } static inline void -setup_fs_payload_gfx20(fs_thread_payload &payload, - const fs_visitor &v, +setup_fs_payload_gfx20(elk_fs_thread_payload &payload, + const elk_fs_visitor &v, bool &source_depth_to_render_target) { - struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data); + struct elk_wm_prog_data *prog_data = elk_wm_prog_data(v.prog_data); const unsigned payload_width = 16; assert(v.dispatch_width % payload_width == 0); assert(v.devinfo->ver >= 20); @@ -173,12 +173,12 @@ setup_fs_payload_gfx20(fs_thread_payload &payload, for (unsigned j = 0; j < v.dispatch_width / payload_width; j++) { /* R2-13: Barycentric interpolation coordinates. These appear - * in the same order that they appear in the brw_barycentric_mode + * in the same order that they appear in the elk_barycentric_mode * enum. Each set of coordinates occupies 2 64B registers per * SIMD16 half. Coordinates only appear if they were enabled * using the "Barycentric Interpolation Mode" bits in WM_STATE. */ - for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) { + for (int i = 0; i < ELK_BARYCENTRIC_MODE_COUNT; ++i) { if (prog_data->barycentric_interp_modes & (1 << i)) { payload.barycentric_coord_reg[i][j] = payload.num_regs; payload.num_regs += payload_width / 4; @@ -230,11 +230,11 @@ setup_fs_payload_gfx20(fs_thread_payload &payload, } static inline void -setup_fs_payload_gfx6(fs_thread_payload &payload, - const fs_visitor &v, +setup_fs_payload_gfx6(elk_fs_thread_payload &payload, + const elk_fs_visitor &v, bool &source_depth_to_render_target) { - struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data); + struct elk_wm_prog_data *prog_data = elk_wm_prog_data(v.prog_data); const unsigned payload_width = MIN2(16, v.dispatch_width); assert(v.dispatch_width % payload_width == 0); @@ -252,13 +252,13 @@ setup_fs_payload_gfx6(fs_thread_payload &payload, for (unsigned j = 0; j < v.dispatch_width / payload_width; j++) { /* R3-26: barycentric interpolation coordinates. These appear in the - * same order that they appear in the brw_barycentric_mode enum. Each + * same order that they appear in the elk_barycentric_mode enum. Each * set of coordinates occupies 2 registers if dispatch width == 8 and 4 * registers if dispatch width == 16. Coordinates only appear if they * were enabled using the "Barycentric Interpolation Mode" bits in * WM_STATE. */ - for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) { + for (int i = 0; i < ELK_BARYCENTRIC_MODE_COUNT; ++i) { if (prog_data->barycentric_interp_modes & (1 << i)) { payload.barycentric_coord_reg[i][j] = payload.num_regs; payload.num_regs += payload_width / 4; @@ -317,7 +317,7 @@ static const struct { GLuint sd_to_rt:1; GLuint dd_present:1; GLuint ds_present:1; -} wm_iz_table[BRW_WM_IZ_BIT_MAX] = +} wm_iz_table[ELK_WM_IZ_BIT_MAX] = { { P, 0, 0, 0, 0 }, { P, 0, 0, 0, 0 }, @@ -386,25 +386,25 @@ static const struct { }; /** - * \param line_aa BRW_NEVER, BRW_ALWAYS or BRW_SOMETIMES - * \param lookup bitmask of BRW_WM_IZ_* flags + * \param line_aa ELK_NEVER, ELK_ALWAYS or ELK_SOMETIMES + * \param lookup bitmask of ELK_WM_IZ_* flags */ static inline void -setup_fs_payload_gfx4(fs_thread_payload &payload, - const fs_visitor &v, +setup_fs_payload_gfx4(elk_fs_thread_payload &payload, + const elk_fs_visitor &v, bool &source_depth_to_render_target, bool &runtime_check_aads_emit) { assert(v.dispatch_width <= 16); - struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data); - brw_wm_prog_key *key = (brw_wm_prog_key *) v.key; + struct elk_wm_prog_data *prog_data = elk_wm_prog_data(v.prog_data); + elk_wm_prog_key *key = (elk_wm_prog_key *) v.key; GLuint reg = 1; bool kill_stats_promoted_workaround = false; int lookup = key->iz_lookup; - assert(lookup < BRW_WM_IZ_BIT_MAX); + assert(lookup < ELK_WM_IZ_BIT_MAX); /* Crazy workaround in the windowizer, which we need to track in * our register allocation and render target writes. See the "If @@ -412,7 +412,7 @@ setup_fs_payload_gfx4(fs_thread_payload &payload, * Test Cases [Pre-DevGT] of the 3D Pipeline - Windower B-Spec. */ if (key->stats_wm && - (lookup & BRW_WM_IZ_PS_KILL_ALPHATEST_BIT) && + (lookup & ELK_WM_IZ_PS_KILL_ALPHATEST_BIT) && wm_iz_table[lookup].mode == P) { kill_stats_promoted_workaround = true; } @@ -428,10 +428,10 @@ setup_fs_payload_gfx4(fs_thread_payload &payload, if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround) source_depth_to_render_target = true; - if (wm_iz_table[lookup].ds_present || key->line_aa != BRW_NEVER) { + if (wm_iz_table[lookup].ds_present || key->line_aa != ELK_NEVER) { payload.aa_dest_stencil_reg[0] = reg; runtime_check_aads_emit = - !wm_iz_table[lookup].ds_present && key->line_aa == BRW_SOMETIMES; + !wm_iz_table[lookup].ds_present && key->line_aa == ELK_SOMETIMES; reg++; } @@ -447,7 +447,7 @@ setup_fs_payload_gfx4(fs_thread_payload &payload, #undef C /* computed */ #undef N /* non-promoted? */ -fs_thread_payload::fs_thread_payload(const fs_visitor &v, +elk_fs_thread_payload::elk_fs_thread_payload(const elk_fs_visitor &v, bool &source_depth_to_render_target, bool &runtime_check_aads_emit) : subspan_coord_reg(), @@ -469,24 +469,24 @@ fs_thread_payload::fs_thread_payload(const fs_visitor &v, runtime_check_aads_emit); } -cs_thread_payload::cs_thread_payload(const fs_visitor &v) +elk_cs_thread_payload::elk_cs_thread_payload(const elk_fs_visitor &v) { - struct brw_cs_prog_data *prog_data = brw_cs_prog_data(v.prog_data); + struct elk_cs_prog_data *prog_data = elk_cs_prog_data(v.prog_data); unsigned r = reg_unit(v.devinfo); /* See nir_setup_uniforms for subgroup_id in earlier versions. */ if (v.devinfo->verx10 >= 125) { - subgroup_id_ = brw_ud1_grf(0, 2); + subgroup_id_ = elk_ud1_grf(0, 2); for (int i = 0; i < 3; i++) { if (prog_data->generate_local_id & (1 << i)) { - local_invocation_id[i] = brw_uw8_grf(r, 0); + local_invocation_id[i] = elk_uw8_grf(r, 0); r += reg_unit(v.devinfo); if (v.devinfo->ver < 20 && v.dispatch_width == 32) r += reg_unit(v.devinfo); } else { - local_invocation_id[i] = brw_imm_uw(0); + local_invocation_id[i] = elk_imm_uw(0); } } @@ -499,21 +499,21 @@ cs_thread_payload::cs_thread_payload(const fs_visitor &v) } void -cs_thread_payload::load_subgroup_id(const fs_builder &bld, - fs_reg &dest) const +elk_cs_thread_payload::load_subgroup_id(const fs_builder &bld, + elk_fs_reg &dest) const { auto devinfo = bld.shader->devinfo; - dest = retype(dest, BRW_REGISTER_TYPE_UD); + dest = retype(dest, ELK_REGISTER_TYPE_UD); if (subgroup_id_.file != BAD_FILE) { assert(devinfo->verx10 >= 125); - bld.AND(dest, subgroup_id_, brw_imm_ud(INTEL_MASK(7, 0))); + bld.AND(dest, subgroup_id_, elk_imm_ud(INTEL_MASK(7, 0))); } else { assert(devinfo->verx10 < 125); assert(gl_shader_stage_is_compute(bld.shader->stage)); - int index = brw_get_subgroup_id_param_index(devinfo, + int index = elk_get_subgroup_id_param_index(devinfo, bld.shader->stage_prog_data); - bld.MOV(dest, fs_reg(UNIFORM, index, BRW_REGISTER_TYPE_UD)); + bld.MOV(dest, elk_fs_reg(UNIFORM, index, ELK_REGISTER_TYPE_UD)); } } diff --git a/src/intel/compiler/elk/elk_fs_validate.cpp b/src/intel/compiler/elk/elk_fs_validate.cpp index d1b5c8ef7d7..e84daddb3da 100644 --- a/src/intel/compiler/elk/elk_fs_validate.cpp +++ b/src/intel/compiler/elk/elk_fs_validate.cpp @@ -88,17 +88,17 @@ #ifndef NDEBUG void -fs_visitor::validate() +elk_fs_visitor::validate() { cfg->validate(_mesa_shader_stage_to_abbrev(stage)); - foreach_block_and_inst (block, fs_inst, inst, cfg) { + foreach_block_and_inst (block, elk_fs_inst, inst, cfg) { switch (inst->opcode) { - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: fsv_assert(is_uniform(inst->src[0]) && is_uniform(inst->src[1])); break; - case BRW_OPCODE_MOV: + case ELK_OPCODE_MOV: fsv_assert(inst->sources == 1); break; @@ -106,36 +106,36 @@ fs_visitor::validate() break; } - if (inst->is_3src(compiler)) { + if (inst->elk_is_3src(compiler)) { const unsigned integer_sources = - brw_reg_type_is_integer(inst->src[0].type) + - brw_reg_type_is_integer(inst->src[1].type) + - brw_reg_type_is_integer(inst->src[2].type); + elk_reg_type_is_integer(inst->src[0].type) + + elk_reg_type_is_integer(inst->src[1].type) + + elk_reg_type_is_integer(inst->src[2].type); const unsigned float_sources = - brw_reg_type_is_floating_point(inst->src[0].type) + - brw_reg_type_is_floating_point(inst->src[1].type) + - brw_reg_type_is_floating_point(inst->src[2].type); + elk_reg_type_is_floating_point(inst->src[0].type) + + elk_reg_type_is_floating_point(inst->src[1].type) + + elk_reg_type_is_floating_point(inst->src[2].type); fsv_assert((integer_sources == 3 && float_sources == 0) || (integer_sources == 0 && float_sources == 3)); if (devinfo->ver >= 10) { for (unsigned i = 0; i < 3; i++) { - if (inst->src[i].file == BRW_IMMEDIATE_VALUE) + if (inst->src[i].file == ELK_IMMEDIATE_VALUE) continue; switch (inst->src[i].vstride) { - case BRW_VERTICAL_STRIDE_0: - case BRW_VERTICAL_STRIDE_4: - case BRW_VERTICAL_STRIDE_8: - case BRW_VERTICAL_STRIDE_16: + case ELK_VERTICAL_STRIDE_0: + case ELK_VERTICAL_STRIDE_4: + case ELK_VERTICAL_STRIDE_8: + case ELK_VERTICAL_STRIDE_16: break; - case BRW_VERTICAL_STRIDE_1: + case ELK_VERTICAL_STRIDE_1: fsv_assert_lte(12, devinfo->ver); break; - case BRW_VERTICAL_STRIDE_2: + case ELK_VERTICAL_STRIDE_2: fsv_assert_lte(devinfo->ver, 11); break; @@ -153,7 +153,7 @@ fs_visitor::validate() * passes (e.g., combine constants) will fix them. */ for (unsigned i = 0; i < 3; i++) { - fsv_assert_ne(inst->src[i].file, BRW_IMMEDIATE_VALUE); + fsv_assert_ne(inst->src[i].file, ELK_IMMEDIATE_VALUE); /* A stride of 1 (the usual case) or 0, with a special * "repctrl" bit, is allowed. The repctrl bit doesn't work for diff --git a/src/intel/compiler/elk/elk_fs_visitor.cpp b/src/intel/compiler/elk/elk_fs_visitor.cpp index 9def6055a74..3316f1f7d7d 100644 --- a/src/intel/compiler/elk/elk_fs_visitor.cpp +++ b/src/intel/compiler/elk/elk_fs_visitor.cpp @@ -44,14 +44,14 @@ using namespace elk; * data. It will get adjusted to be a real location before * generate_code() time. */ -fs_reg -fs_visitor::interp_reg(const fs_builder &bld, unsigned location, +elk_fs_reg +elk_fs_visitor::interp_reg(const fs_builder &bld, unsigned location, unsigned channel, unsigned comp) { assert(stage == MESA_SHADER_FRAGMENT); assert(BITFIELD64_BIT(location) & ~nir->info.per_primitive_inputs); - const struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); + const struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data); assert(prog_data->urb_setup[location] >= 0); unsigned nr = prog_data->urb_setup[location]; @@ -70,12 +70,12 @@ fs_visitor::interp_reg(const fs_builder &bld, unsigned location, * assign_urb_setup()), so we need to use offset() instead of * component() to select the specified parameter. */ - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.MOV(tmp, offset(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_UD), + const elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.MOV(tmp, offset(elk_fs_reg(ATTR, regnr, ELK_REGISTER_TYPE_UD), dispatch_width, comp)); - return retype(tmp, BRW_REGISTER_TYPE_F); + return retype(tmp, ELK_REGISTER_TYPE_F); } else { - return component(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F), comp); + return component(elk_fs_reg(ATTR, regnr, ELK_REGISTER_TYPE_F), comp); } } @@ -83,13 +83,13 @@ fs_visitor::interp_reg(const fs_builder &bld, unsigned location, * data. It will get adjusted to be a real location before * generate_code() time. */ -fs_reg -fs_visitor::per_primitive_reg(const fs_builder &bld, int location, unsigned comp) +elk_fs_reg +elk_fs_visitor::per_primitive_reg(const fs_builder &bld, int location, unsigned comp) { assert(stage == MESA_SHADER_FRAGMENT); assert(BITFIELD64_BIT(location) & nir->info.per_primitive_inputs); - const struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); + const struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data); comp += prog_data->urb_setup_channel[location]; @@ -105,41 +105,41 @@ fs_visitor::per_primitive_reg(const fs_builder &bld, int location, unsigned comp * assign_urb_setup()), so we need to use offset() instead of * component() to select the specified parameter. */ - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.MOV(tmp, offset(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_UD), + const elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.MOV(tmp, offset(elk_fs_reg(ATTR, regnr, ELK_REGISTER_TYPE_UD), dispatch_width, comp % 4)); - return retype(tmp, BRW_REGISTER_TYPE_F); + return retype(tmp, ELK_REGISTER_TYPE_F); } else { - return component(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F), comp % 4); + return component(elk_fs_reg(ATTR, regnr, ELK_REGISTER_TYPE_F), comp % 4); } } /** Emits the interpolation for the varying inputs. */ void -fs_visitor::emit_interpolation_setup_gfx4() +elk_fs_visitor::emit_interpolation_setup_gfx4() { - struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); + struct elk_reg g1_uw = retype(elk_vec1_grf(1, 0), ELK_REGISTER_TYPE_UW); fs_builder abld = fs_builder(this).at_end().annotate("compute pixel centers"); this->pixel_x = vgrf(glsl_uint_type()); this->pixel_y = vgrf(glsl_uint_type()); - this->pixel_x.type = BRW_REGISTER_TYPE_UW; - this->pixel_y.type = BRW_REGISTER_TYPE_UW; + this->pixel_x.type = ELK_REGISTER_TYPE_UW; + this->pixel_y.type = ELK_REGISTER_TYPE_UW; abld.ADD(this->pixel_x, - fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), - fs_reg(brw_imm_v(0x10101010))); + elk_fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), + elk_fs_reg(elk_imm_v(0x10101010))); abld.ADD(this->pixel_y, - fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), - fs_reg(brw_imm_v(0x11001100))); + elk_fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), + elk_fs_reg(elk_imm_v(0x11001100))); const fs_builder bld = fs_builder(this).at_end(); abld = bld.annotate("compute pixel deltas from v0"); - this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL] = + this->delta_xy[ELK_BARYCENTRIC_PERSPECTIVE_PIXEL] = vgrf(glsl_vec2_type()); - const fs_reg &delta_xy = this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL]; - const fs_reg xstart(negate(brw_vec1_grf(1, 0))); - const fs_reg ystart(negate(brw_vec1_grf(1, 1))); + const elk_fs_reg &delta_xy = this->delta_xy[ELK_BARYCENTRIC_PERSPECTIVE_PIXEL]; + const elk_fs_reg xstart(negate(elk_vec1_grf(1, 0))); + const elk_fs_reg ystart(negate(elk_vec1_grf(1, 1))); if (devinfo->has_pln) { for (unsigned i = 0; i < dispatch_width / 8; i++) { @@ -159,24 +159,24 @@ fs_visitor::emit_interpolation_setup_gfx4() * not based on wm_prog_data::interp_mode[] so we can use the same pixel * offsets for both perspective and non-perspective. */ - this->delta_xy[BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL] = - this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL]; + this->delta_xy[ELK_BARYCENTRIC_NONPERSPECTIVE_PIXEL] = + this->delta_xy[ELK_BARYCENTRIC_PERSPECTIVE_PIXEL]; abld = bld.annotate("compute pos.w and 1/pos.w"); /* Compute wpos.w. It's always in our setup, since it's needed to * interpolate the other attributes. */ this->wpos_w = vgrf(glsl_float_type()); - abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy, + abld.emit(ELK_FS_OPCODE_LINTERP, wpos_w, delta_xy, interp_reg(abld, VARYING_SLOT_POS, 3, 0)); /* Compute the pixel 1/W value from wpos.w. */ this->pixel_w = vgrf(glsl_float_type()); - abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); + abld.emit(ELK_SHADER_OPCODE_RCP, this->pixel_w, wpos_w); } /** Emits the interpolation for the varying inputs. */ void -fs_visitor::emit_interpolation_setup_gfx6() +elk_fs_visitor::emit_interpolation_setup_gfx6() { const fs_builder bld = fs_builder(this).at_end(); fs_builder abld = bld.annotate("compute pixel centers"); @@ -184,13 +184,13 @@ fs_visitor::emit_interpolation_setup_gfx6() this->pixel_x = vgrf(glsl_float_type()); this->pixel_y = vgrf(glsl_float_type()); - const struct brw_wm_prog_key *wm_key = (brw_wm_prog_key*) this->key; - struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data); + const struct elk_wm_prog_key *wm_key = (elk_wm_prog_key*) this->key; + struct elk_wm_prog_data *wm_prog_data = elk_wm_prog_data(prog_data); - fs_reg int_sample_offset_x, int_sample_offset_y; /* Used on Gen12HP+ */ - fs_reg int_sample_offset_xy; /* Used on Gen8+ */ - fs_reg half_int_sample_offset_x, half_int_sample_offset_y; - if (wm_prog_data->coarse_pixel_dispatch != BRW_ALWAYS) { + elk_fs_reg int_sample_offset_x, int_sample_offset_y; /* Used on Gen12HP+ */ + elk_fs_reg int_sample_offset_xy; /* Used on Gen8+ */ + elk_fs_reg half_int_sample_offset_x, half_int_sample_offset_y; + if (wm_prog_data->coarse_pixel_dispatch != ELK_ALWAYS) { /* The thread payload only delivers subspan locations (ss0, ss1, * ss2, ...). Since subspans covers 2x2 pixels blocks, we need to * generate 4 pixel coordinates out of each subspan location. We do this @@ -220,9 +220,9 @@ fs_visitor::emit_interpolation_setup_gfx6() * coordinates out of 2 subspans coordinates in a single ADD instruction * (twice the operation above). */ - int_sample_offset_xy = fs_reg(brw_imm_v(0x11001010)); - half_int_sample_offset_x = fs_reg(brw_imm_uw(0)); - half_int_sample_offset_y = fs_reg(brw_imm_uw(0)); + int_sample_offset_xy = elk_fs_reg(elk_imm_v(0x11001010)); + half_int_sample_offset_x = elk_fs_reg(elk_imm_uw(0)); + half_int_sample_offset_y = elk_fs_reg(elk_imm_uw(0)); /* On Gfx12.5, because of regioning restrictions, the interpolation code * is slightly different and works off X & Y only inputs. The ordering * of the half bytes here is a bit odd, with each subspan replicated @@ -232,21 +232,21 @@ fs_visitor::emit_interpolation_setup_gfx6() * X offset: 0 0 1 0 0 0 1 0 * Y offset: 0 0 0 0 1 0 1 0 */ - int_sample_offset_x = fs_reg(brw_imm_v(0x01000100)); - int_sample_offset_y = fs_reg(brw_imm_v(0x01010000)); + int_sample_offset_x = elk_fs_reg(elk_imm_v(0x01000100)); + int_sample_offset_y = elk_fs_reg(elk_imm_v(0x01010000)); } - fs_reg int_coarse_offset_x, int_coarse_offset_y; /* Used on Gen12HP+ */ - fs_reg int_coarse_offset_xy; /* Used on Gen8+ */ - fs_reg half_int_coarse_offset_x, half_int_coarse_offset_y; - if (wm_prog_data->coarse_pixel_dispatch != BRW_NEVER) { + elk_fs_reg int_coarse_offset_x, int_coarse_offset_y; /* Used on Gen12HP+ */ + elk_fs_reg int_coarse_offset_xy; /* Used on Gen8+ */ + elk_fs_reg half_int_coarse_offset_x, half_int_coarse_offset_y; + if (wm_prog_data->coarse_pixel_dispatch != ELK_NEVER) { /* In coarse pixel dispatch we have to do the same ADD instruction that * we do in normal per pixel dispatch, except this time we're not adding * 1 in each direction, but instead the coarse pixel size. * * The coarse pixel size is delivered as 2 u8 in r1.0 */ - struct brw_reg r1_0 = retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), BRW_REGISTER_TYPE_UB); + struct elk_reg r1_0 = retype(elk_vec1_reg(ELK_GENERAL_REGISTER_FILE, 1, 0), ELK_REGISTER_TYPE_UB); const fs_builder dbld = abld.exec_all().group(MIN2(16, dispatch_width) * 2, 0); @@ -255,41 +255,41 @@ fs_visitor::emit_interpolation_setup_gfx6() /* To build the array of half bytes we do and AND operation with the * right mask in X. */ - int_coarse_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); - dbld.AND(int_coarse_offset_x, byte_offset(r1_0, 0), brw_imm_v(0x0f000f00)); + int_coarse_offset_x = dbld.vgrf(ELK_REGISTER_TYPE_UW); + dbld.AND(int_coarse_offset_x, byte_offset(r1_0, 0), elk_imm_v(0x0f000f00)); /* And the right mask in Y. */ - int_coarse_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); - dbld.AND(int_coarse_offset_y, byte_offset(r1_0, 1), brw_imm_v(0x0f0f0000)); + int_coarse_offset_y = dbld.vgrf(ELK_REGISTER_TYPE_UW); + dbld.AND(int_coarse_offset_y, byte_offset(r1_0, 1), elk_imm_v(0x0f0f0000)); } else { /* To build the array of half bytes we do and AND operation with the * right mask in X. */ - int_coarse_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); - dbld.AND(int_coarse_offset_x, byte_offset(r1_0, 0), brw_imm_v(0x0000f0f0)); + int_coarse_offset_x = dbld.vgrf(ELK_REGISTER_TYPE_UW); + dbld.AND(int_coarse_offset_x, byte_offset(r1_0, 0), elk_imm_v(0x0000f0f0)); /* And the right mask in Y. */ - int_coarse_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); - dbld.AND(int_coarse_offset_y, byte_offset(r1_0, 1), brw_imm_v(0xff000000)); + int_coarse_offset_y = dbld.vgrf(ELK_REGISTER_TYPE_UW); + dbld.AND(int_coarse_offset_y, byte_offset(r1_0, 1), elk_imm_v(0xff000000)); /* Finally OR the 2 registers. */ - int_coarse_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); + int_coarse_offset_xy = dbld.vgrf(ELK_REGISTER_TYPE_UW); dbld.OR(int_coarse_offset_xy, int_coarse_offset_x, int_coarse_offset_y); } /* Also compute the half coarse size used to center coarses. */ - half_int_coarse_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW); - half_int_coarse_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW); + half_int_coarse_offset_x = bld.vgrf(ELK_REGISTER_TYPE_UW); + half_int_coarse_offset_y = bld.vgrf(ELK_REGISTER_TYPE_UW); - bld.SHR(half_int_coarse_offset_x, suboffset(r1_0, 0), brw_imm_ud(1)); - bld.SHR(half_int_coarse_offset_y, suboffset(r1_0, 1), brw_imm_ud(1)); + bld.SHR(half_int_coarse_offset_x, suboffset(r1_0, 0), elk_imm_ud(1)); + bld.SHR(half_int_coarse_offset_y, suboffset(r1_0, 1), elk_imm_ud(1)); } - fs_reg int_pixel_offset_x, int_pixel_offset_y; /* Used on Gen12HP+ */ - fs_reg int_pixel_offset_xy; /* Used on Gen8+ */ - fs_reg half_int_pixel_offset_x, half_int_pixel_offset_y; + elk_fs_reg int_pixel_offset_x, int_pixel_offset_y; /* Used on Gen12HP+ */ + elk_fs_reg int_pixel_offset_xy; /* Used on Gen8+ */ + elk_fs_reg half_int_pixel_offset_x, half_int_pixel_offset_y; switch (wm_prog_data->coarse_pixel_dispatch) { - case BRW_NEVER: + case ELK_NEVER: int_pixel_offset_x = int_sample_offset_x; int_pixel_offset_y = int_sample_offset_y; int_pixel_offset_xy = int_sample_offset_xy; @@ -297,46 +297,46 @@ fs_visitor::emit_interpolation_setup_gfx6() half_int_pixel_offset_y = half_int_sample_offset_y; break; - case BRW_SOMETIMES: { + case ELK_SOMETIMES: { const fs_builder dbld = abld.exec_all().group(MIN2(16, dispatch_width) * 2, 0); check_dynamic_msaa_flag(dbld, wm_prog_data, INTEL_MSAA_FLAG_COARSE_RT_WRITES); - int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); - set_predicate(BRW_PREDICATE_NORMAL, + int_pixel_offset_x = dbld.vgrf(ELK_REGISTER_TYPE_UW); + set_predicate(ELK_PREDICATE_NORMAL, dbld.SEL(int_pixel_offset_x, int_coarse_offset_x, int_sample_offset_x)); - int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); - set_predicate(BRW_PREDICATE_NORMAL, + int_pixel_offset_y = dbld.vgrf(ELK_REGISTER_TYPE_UW); + set_predicate(ELK_PREDICATE_NORMAL, dbld.SEL(int_pixel_offset_y, int_coarse_offset_y, int_sample_offset_y)); - int_pixel_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); - set_predicate(BRW_PREDICATE_NORMAL, + int_pixel_offset_xy = dbld.vgrf(ELK_REGISTER_TYPE_UW); + set_predicate(ELK_PREDICATE_NORMAL, dbld.SEL(int_pixel_offset_xy, int_coarse_offset_xy, int_sample_offset_xy)); - half_int_pixel_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW); - set_predicate(BRW_PREDICATE_NORMAL, + half_int_pixel_offset_x = bld.vgrf(ELK_REGISTER_TYPE_UW); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(half_int_pixel_offset_x, half_int_coarse_offset_x, half_int_sample_offset_x)); - half_int_pixel_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW); - set_predicate(BRW_PREDICATE_NORMAL, + half_int_pixel_offset_y = bld.vgrf(ELK_REGISTER_TYPE_UW); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(half_int_pixel_offset_y, half_int_coarse_offset_y, half_int_sample_offset_y)); break; } - case BRW_ALWAYS: + case ELK_ALWAYS: int_pixel_offset_x = int_coarse_offset_x; int_pixel_offset_y = int_coarse_offset_y; int_pixel_offset_xy = int_coarse_offset_xy; @@ -353,31 +353,31 @@ fs_visitor::emit_interpolation_setup_gfx6() * on gfx20+. gi_reg is the 32B section of the GRF that * contains the subspan coordinates. */ - const struct brw_reg gi_reg = devinfo->ver >= 20 ? xe2_vec1_grf(i, 8) : - brw_vec1_grf(i + 1, 0); - const struct brw_reg gi_uw = retype(gi_reg, BRW_REGISTER_TYPE_UW); + const struct elk_reg gi_reg = devinfo->ver >= 20 ? xe2_vec1_grf(i, 8) : + elk_vec1_grf(i + 1, 0); + const struct elk_reg gi_uw = retype(gi_reg, ELK_REGISTER_TYPE_UW); if (devinfo->verx10 >= 125) { const fs_builder dbld = abld.exec_all().group(hbld.dispatch_width() * 2, 0); - const fs_reg int_pixel_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); - const fs_reg int_pixel_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); + const elk_fs_reg int_pixel_x = dbld.vgrf(ELK_REGISTER_TYPE_UW); + const elk_fs_reg int_pixel_y = dbld.vgrf(ELK_REGISTER_TYPE_UW); dbld.ADD(int_pixel_x, - fs_reg(stride(suboffset(gi_uw, 4), 2, 8, 0)), + elk_fs_reg(stride(suboffset(gi_uw, 4), 2, 8, 0)), int_pixel_offset_x); dbld.ADD(int_pixel_y, - fs_reg(stride(suboffset(gi_uw, 5), 2, 8, 0)), + elk_fs_reg(stride(suboffset(gi_uw, 5), 2, 8, 0)), int_pixel_offset_y); - if (wm_prog_data->coarse_pixel_dispatch != BRW_NEVER) { - fs_inst *addx = dbld.ADD(int_pixel_x, int_pixel_x, + if (wm_prog_data->coarse_pixel_dispatch != ELK_NEVER) { + elk_fs_inst *addx = dbld.ADD(int_pixel_x, int_pixel_x, horiz_stride(half_int_pixel_offset_x, 0)); - fs_inst *addy = dbld.ADD(int_pixel_y, int_pixel_y, + elk_fs_inst *addy = dbld.ADD(int_pixel_y, int_pixel_y, horiz_stride(half_int_pixel_offset_y, 0)); - if (wm_prog_data->coarse_pixel_dispatch != BRW_ALWAYS) { - addx->predicate = BRW_PREDICATE_NORMAL; - addy->predicate = BRW_PREDICATE_NORMAL; + if (wm_prog_data->coarse_pixel_dispatch != ELK_ALWAYS) { + addx->predicate = ELK_PREDICATE_NORMAL; + addy->predicate = ELK_PREDICATE_NORMAL; } } @@ -397,15 +397,15 @@ fs_visitor::emit_interpolation_setup_gfx6() */ const fs_builder dbld = abld.exec_all().group(hbld.dispatch_width() * 2, 0); - fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); + elk_fs_reg int_pixel_xy = dbld.vgrf(ELK_REGISTER_TYPE_UW); dbld.ADD(int_pixel_xy, - fs_reg(stride(suboffset(gi_uw, 4), 1, 4, 0)), + elk_fs_reg(stride(suboffset(gi_uw, 4), 1, 4, 0)), int_pixel_offset_xy); - hbld.emit(FS_OPCODE_PIXEL_X, offset(pixel_x, hbld, i), int_pixel_xy, + hbld.emit(ELK_FS_OPCODE_PIXEL_X, offset(pixel_x, hbld, i), int_pixel_xy, horiz_stride(half_int_pixel_offset_x, 0)); - hbld.emit(FS_OPCODE_PIXEL_Y, offset(pixel_y, hbld, i), int_pixel_xy, + hbld.emit(ELK_FS_OPCODE_PIXEL_Y, offset(pixel_y, hbld, i), int_pixel_xy, horiz_stride(half_int_pixel_offset_y, 0)); } else { /* The "Register Region Restrictions" page says for SNB, IVB, HSW: @@ -416,15 +416,15 @@ fs_visitor::emit_interpolation_setup_gfx6() * Since the GRF source of the ADD will only read a single register, * we must do two separate ADDs in SIMD16. */ - const fs_reg int_pixel_x = hbld.vgrf(BRW_REGISTER_TYPE_UW); - const fs_reg int_pixel_y = hbld.vgrf(BRW_REGISTER_TYPE_UW); + const elk_fs_reg int_pixel_x = hbld.vgrf(ELK_REGISTER_TYPE_UW); + const elk_fs_reg int_pixel_y = hbld.vgrf(ELK_REGISTER_TYPE_UW); hbld.ADD(int_pixel_x, - fs_reg(stride(suboffset(gi_uw, 4), 2, 4, 0)), - fs_reg(brw_imm_v(0x10101010))); + elk_fs_reg(stride(suboffset(gi_uw, 4), 2, 4, 0)), + elk_fs_reg(elk_imm_v(0x10101010))); hbld.ADD(int_pixel_y, - fs_reg(stride(suboffset(gi_uw, 5), 2, 4, 0)), - fs_reg(brw_imm_v(0x11001100))); + elk_fs_reg(stride(suboffset(gi_uw, 5), 2, 4, 0)), + elk_fs_reg(elk_imm_v(0x11001100))); /* As of gfx6, we can no longer mix float and int sources. We have * to turn the integer pixel centers into floats for their actual @@ -436,45 +436,45 @@ fs_visitor::emit_interpolation_setup_gfx6() } abld = bld.annotate("compute pos.z"); - fs_reg coarse_z; + elk_fs_reg coarse_z; if (wm_prog_data->uses_depth_w_coefficients) { /* In coarse pixel mode, the HW doesn't interpolate Z coordinate * properly. In the same way we have to add the coarse pixel size to * pixels locations, here we recompute the Z value with 2 coefficients * in X & Y axis. */ - fs_reg coef_payload = brw_vec8_grf(fs_payload().depth_w_coef_reg, 0); - const fs_reg x_start = brw_vec1_grf(coef_payload.nr, 2); - const fs_reg y_start = brw_vec1_grf(coef_payload.nr, 6); - const fs_reg z_cx = brw_vec1_grf(coef_payload.nr, 1); - const fs_reg z_cy = brw_vec1_grf(coef_payload.nr, 0); - const fs_reg z_c0 = brw_vec1_grf(coef_payload.nr, 3); + elk_fs_reg coef_payload = elk_vec8_grf(fs_payload().depth_w_coef_reg, 0); + const elk_fs_reg x_start = elk_vec1_grf(coef_payload.nr, 2); + const elk_fs_reg y_start = elk_vec1_grf(coef_payload.nr, 6); + const elk_fs_reg z_cx = elk_vec1_grf(coef_payload.nr, 1); + const elk_fs_reg z_cy = elk_vec1_grf(coef_payload.nr, 0); + const elk_fs_reg z_c0 = elk_vec1_grf(coef_payload.nr, 3); - const fs_reg float_pixel_x = abld.vgrf(BRW_REGISTER_TYPE_F); - const fs_reg float_pixel_y = abld.vgrf(BRW_REGISTER_TYPE_F); + const elk_fs_reg float_pixel_x = abld.vgrf(ELK_REGISTER_TYPE_F); + const elk_fs_reg float_pixel_y = abld.vgrf(ELK_REGISTER_TYPE_F); abld.ADD(float_pixel_x, this->pixel_x, negate(x_start)); abld.ADD(float_pixel_y, this->pixel_y, negate(y_start)); /* r1.0 - 0:7 ActualCoarsePixelShadingSize.X */ - const fs_reg u8_cps_width = fs_reg(retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UB)); + const elk_fs_reg u8_cps_width = elk_fs_reg(retype(elk_vec1_grf(1, 0), ELK_REGISTER_TYPE_UB)); /* r1.0 - 15:8 ActualCoarsePixelShadingSize.Y */ - const fs_reg u8_cps_height = byte_offset(u8_cps_width, 1); - const fs_reg u32_cps_width = abld.vgrf(BRW_REGISTER_TYPE_UD); - const fs_reg u32_cps_height = abld.vgrf(BRW_REGISTER_TYPE_UD); + const elk_fs_reg u8_cps_height = byte_offset(u8_cps_width, 1); + const elk_fs_reg u32_cps_width = abld.vgrf(ELK_REGISTER_TYPE_UD); + const elk_fs_reg u32_cps_height = abld.vgrf(ELK_REGISTER_TYPE_UD); abld.MOV(u32_cps_width, u8_cps_width); abld.MOV(u32_cps_height, u8_cps_height); - const fs_reg f_cps_width = abld.vgrf(BRW_REGISTER_TYPE_F); - const fs_reg f_cps_height = abld.vgrf(BRW_REGISTER_TYPE_F); + const elk_fs_reg f_cps_width = abld.vgrf(ELK_REGISTER_TYPE_F); + const elk_fs_reg f_cps_height = abld.vgrf(ELK_REGISTER_TYPE_F); abld.MOV(f_cps_width, u32_cps_width); abld.MOV(f_cps_height, u32_cps_height); /* Center in the middle of the coarse pixel. */ - abld.MAD(float_pixel_x, float_pixel_x, brw_imm_f(0.5f), f_cps_width); - abld.MAD(float_pixel_y, float_pixel_y, brw_imm_f(0.5f), f_cps_height); + abld.MAD(float_pixel_x, float_pixel_x, elk_imm_f(0.5f), f_cps_width); + abld.MAD(float_pixel_y, float_pixel_y, elk_imm_f(0.5f), f_cps_height); - coarse_z = abld.vgrf(BRW_REGISTER_TYPE_F); + coarse_z = abld.vgrf(ELK_REGISTER_TYPE_F); abld.MAD(coarse_z, z_c0, z_cx, float_pixel_x); abld.MAD(coarse_z, coarse_z, z_cy, float_pixel_y); } @@ -484,26 +484,26 @@ fs_visitor::emit_interpolation_setup_gfx6() if (wm_prog_data->uses_depth_w_coefficients || wm_prog_data->uses_src_depth) { - fs_reg sample_z = this->pixel_z; + elk_fs_reg sample_z = this->pixel_z; switch (wm_prog_data->coarse_pixel_dispatch) { - case BRW_NEVER: + case ELK_NEVER: assert(wm_prog_data->uses_src_depth); assert(!wm_prog_data->uses_depth_w_coefficients); this->pixel_z = sample_z; break; - case BRW_SOMETIMES: + case ELK_SOMETIMES: assert(wm_prog_data->uses_src_depth); assert(wm_prog_data->uses_depth_w_coefficients); - this->pixel_z = abld.vgrf(BRW_REGISTER_TYPE_F); + this->pixel_z = abld.vgrf(ELK_REGISTER_TYPE_F); /* We re-use the check_dynamic_msaa_flag() call from above */ - set_predicate(BRW_PREDICATE_NORMAL, + set_predicate(ELK_PREDICATE_NORMAL, abld.SEL(this->pixel_z, coarse_z, sample_z)); break; - case BRW_ALWAYS: + case ELK_ALWAYS: assert(!wm_prog_data->uses_src_depth); assert(wm_prog_data->uses_depth_w_coefficients); this->pixel_z = coarse_z; @@ -515,32 +515,32 @@ fs_visitor::emit_interpolation_setup_gfx6() abld = bld.annotate("compute pos.w"); this->pixel_w = fetch_payload_reg(abld, fs_payload().source_w_reg); this->wpos_w = vgrf(glsl_float_type()); - abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); + abld.emit(ELK_SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); } - if (wm_key->persample_interp == BRW_SOMETIMES) { + if (wm_key->persample_interp == ELK_SOMETIMES) { assert(!devinfo->needs_unlit_centroid_workaround); const fs_builder ubld = bld.exec_all().group(16, 0); bool loaded_flag = false; - for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) { + for (int i = 0; i < ELK_BARYCENTRIC_MODE_COUNT; ++i) { if (!(wm_prog_data->barycentric_interp_modes & BITFIELD_BIT(i))) continue; /* The sample mode will always be the top bit set in the perspective * or non-perspective section. In the case where no SAMPLE mode was - * requested, wm_prog_data_barycentric_modes() will swap out the top + * requested, elk_wm_prog_data_barycentric_modes() will swap out the top * mode for SAMPLE so this works regardless of whether SAMPLE was * requested or not. */ int sample_mode; - if (BITFIELD_BIT(i) & BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) { + if (BITFIELD_BIT(i) & ELK_BARYCENTRIC_NONPERSPECTIVE_BITS) { sample_mode = util_last_bit(wm_prog_data->barycentric_interp_modes & - BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) - 1; + ELK_BARYCENTRIC_NONPERSPECTIVE_BITS) - 1; } else { sample_mode = util_last_bit(wm_prog_data->barycentric_interp_modes & - BRW_BARYCENTRIC_PERSPECTIVE_BITS) - 1; + ELK_BARYCENTRIC_PERSPECTIVE_BITS) - 1; } assert(wm_prog_data->barycentric_interp_modes & BITFIELD_BIT(sample_mode)); @@ -560,21 +560,21 @@ fs_visitor::emit_interpolation_setup_gfx6() for (unsigned j = 0; j < dispatch_width / 8; j++) { set_predicate( - BRW_PREDICATE_NORMAL, - ubld.MOV(brw_vec8_grf(barys[j / 2] + (j % 2) * 2, 0), - brw_vec8_grf(sample_barys[j / 2] + (j % 2) * 2, 0))); + ELK_PREDICATE_NORMAL, + ubld.MOV(elk_vec8_grf(barys[j / 2] + (j % 2) * 2, 0), + elk_vec8_grf(sample_barys[j / 2] + (j % 2) * 2, 0))); } } } - for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) { + for (int i = 0; i < ELK_BARYCENTRIC_MODE_COUNT; ++i) { this->delta_xy[i] = fetch_barycentric_reg( bld, fs_payload().barycentric_coord_reg[i]); } uint32_t centroid_modes = wm_prog_data->barycentric_interp_modes & - (1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID | - 1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID); + (1 << ELK_BARYCENTRIC_PERSPECTIVE_CENTROID | + 1 << ELK_BARYCENTRIC_NONPERSPECTIVE_CENTROID); if (devinfo->needs_unlit_centroid_workaround && centroid_modes) { /* Get the pixel/sample mask into f0 so that we know which @@ -583,22 +583,22 @@ fs_visitor::emit_interpolation_setup_gfx6() */ for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) { bld.exec_all().group(1, 0) - .MOV(retype(brw_flag_reg(0, i), BRW_REGISTER_TYPE_UW), - retype(brw_vec1_grf(1 + i, 7), BRW_REGISTER_TYPE_UW)); + .MOV(retype(elk_flag_reg(0, i), ELK_REGISTER_TYPE_UW), + retype(elk_vec1_grf(1 + i, 7), ELK_REGISTER_TYPE_UW)); } - for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) { + for (int i = 0; i < ELK_BARYCENTRIC_MODE_COUNT; ++i) { if (!(centroid_modes & (1 << i))) continue; - const fs_reg centroid_delta_xy = delta_xy[i]; - const fs_reg &pixel_delta_xy = delta_xy[i - 1]; + const elk_fs_reg centroid_delta_xy = delta_xy[i]; + const elk_fs_reg &pixel_delta_xy = delta_xy[i - 1]; - delta_xy[i] = bld.vgrf(BRW_REGISTER_TYPE_F, 2); + delta_xy[i] = bld.vgrf(ELK_REGISTER_TYPE_F, 2); for (unsigned c = 0; c < 2; c++) { for (unsigned q = 0; q < dispatch_width / 8; q++) { - set_predicate(BRW_PREDICATE_NORMAL, + set_predicate(ELK_PREDICATE_NORMAL, bld.quarter(q).SEL( quarter(offset(delta_xy[i], bld, c), q), quarter(offset(centroid_delta_xy, bld, c), q), @@ -609,22 +609,22 @@ fs_visitor::emit_interpolation_setup_gfx6() } } -static enum brw_conditional_mod +static enum elk_conditional_mod cond_for_alpha_func(enum compare_func func) { switch(func) { case COMPARE_FUNC_GREATER: - return BRW_CONDITIONAL_G; + return ELK_CONDITIONAL_G; case COMPARE_FUNC_GEQUAL: - return BRW_CONDITIONAL_GE; + return ELK_CONDITIONAL_GE; case COMPARE_FUNC_LESS: - return BRW_CONDITIONAL_L; + return ELK_CONDITIONAL_L; case COMPARE_FUNC_LEQUAL: - return BRW_CONDITIONAL_LE; + return ELK_CONDITIONAL_LE; case COMPARE_FUNC_EQUAL: - return BRW_CONDITIONAL_EQ; + return ELK_CONDITIONAL_EQ; case COMPARE_FUNC_NOTEQUAL: - return BRW_CONDITIONAL_NEQ; + return ELK_CONDITIONAL_NEQ; default: unreachable("Not reached"); } @@ -635,46 +635,46 @@ cond_for_alpha_func(enum compare_func func) * of using the normal fixed-function alpha test. */ void -fs_visitor::emit_alpha_test() +elk_fs_visitor::emit_alpha_test() { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; + elk_wm_prog_key *key = (elk_wm_prog_key*) this->key; const fs_builder bld = fs_builder(this).at_end(); const fs_builder abld = bld.annotate("Alpha test"); - fs_inst *cmp; + elk_fs_inst *cmp; if (key->alpha_test_func == COMPARE_FUNC_ALWAYS) return; if (key->alpha_test_func == COMPARE_FUNC_NEVER) { /* f0.1 = 0 */ - fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0), - BRW_REGISTER_TYPE_UW)); + elk_fs_reg some_reg = elk_fs_reg(retype(elk_vec8_grf(0, 0), + ELK_REGISTER_TYPE_UW)); cmp = abld.CMP(bld.null_reg_f(), some_reg, some_reg, - BRW_CONDITIONAL_NEQ); + ELK_CONDITIONAL_NEQ); } else { /* RT0 alpha */ - fs_reg color = offset(outputs[0], bld, 3); + elk_fs_reg color = offset(outputs[0], bld, 3); /* f0.1 &= func(color, ref) */ - cmp = abld.CMP(bld.null_reg_f(), color, brw_imm_f(key->alpha_test_ref), + cmp = abld.CMP(bld.null_reg_f(), color, elk_imm_f(key->alpha_test_ref), cond_for_alpha_func(key->alpha_test_func)); } - cmp->predicate = BRW_PREDICATE_NORMAL; + cmp->predicate = ELK_PREDICATE_NORMAL; cmp->flag_subreg = 1; } -fs_inst * -fs_visitor::emit_single_fb_write(const fs_builder &bld, - fs_reg color0, fs_reg color1, - fs_reg src0_alpha, unsigned components) +elk_fs_inst * +elk_fs_visitor::emit_single_fb_write(const fs_builder &bld, + elk_fs_reg color0, elk_fs_reg color1, + elk_fs_reg src0_alpha, unsigned components) { assert(stage == MESA_SHADER_FRAGMENT); - struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); + struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data); /* Hand over gl_FragDepth or the payload depth. */ - const fs_reg dst_depth = fetch_payload_reg(bld, fs_payload().dest_depth_reg); - fs_reg src_depth, src_stencil; + const elk_fs_reg dst_depth = fetch_payload_reg(bld, fs_payload().dest_depth_reg); + elk_fs_reg src_depth, src_stencil; if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { src_depth = frag_depth; @@ -693,17 +693,17 @@ fs_visitor::emit_single_fb_write(const fs_builder &bld, if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL)) src_stencil = frag_stencil; - const fs_reg sources[] = { + const elk_fs_reg sources[] = { color0, color1, src0_alpha, src_depth, dst_depth, src_stencil, - (prog_data->uses_omask ? sample_mask : fs_reg()), - brw_imm_ud(components) + (prog_data->uses_omask ? sample_mask : elk_fs_reg()), + elk_imm_ud(components) }; assert(ARRAY_SIZE(sources) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS); - fs_inst *write = bld.emit(FS_OPCODE_FB_WRITE_LOGICAL, fs_reg(), + elk_fs_inst *write = bld.emit(ELK_FS_OPCODE_FB_WRITE_LOGICAL, elk_fs_reg(), sources, ARRAY_SIZE(sources)); if (prog_data->uses_kill) { - write->predicate = BRW_PREDICATE_NORMAL; + write->predicate = ELK_PREDICATE_NORMAL; write->flag_subreg = sample_mask_flag_subreg(*this); } @@ -711,10 +711,10 @@ fs_visitor::emit_single_fb_write(const fs_builder &bld, } void -fs_visitor::do_emit_fb_writes(int nr_color_regions, bool replicate_alpha) +elk_fs_visitor::do_emit_fb_writes(int nr_color_regions, bool replicate_alpha) { const fs_builder bld = fs_builder(this).at_end(); - fs_inst *inst = NULL; + elk_fs_inst *inst = NULL; for (int target = 0; target < nr_color_regions; target++) { /* Skip over outputs that weren't written. */ @@ -724,7 +724,7 @@ fs_visitor::do_emit_fb_writes(int nr_color_regions, bool replicate_alpha) const fs_builder abld = bld.annotate( ralloc_asprintf(this->mem_ctx, "FB write target %d", target)); - fs_reg src0_alpha; + elk_fs_reg src0_alpha; if (devinfo->ver >= 6 && replicate_alpha && target != 0) src0_alpha = offset(outputs[0], bld, 3); @@ -741,9 +741,9 @@ fs_visitor::do_emit_fb_writes(int nr_color_regions, bool replicate_alpha) /* FINISHME: Factor out this frequently recurring pattern into a * helper function. */ - const fs_reg srcs[] = { reg_undef, reg_undef, + const elk_fs_reg srcs[] = { reg_undef, reg_undef, reg_undef, offset(this->outputs[0], bld, 3) }; - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 4); + const elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD, 4); bld.LOAD_PAYLOAD(tmp, srcs, 4, 0); inst = emit_single_fb_write(bld, tmp, reg_undef, reg_undef, 4); @@ -755,11 +755,11 @@ fs_visitor::do_emit_fb_writes(int nr_color_regions, bool replicate_alpha) } void -fs_visitor::emit_fb_writes() +elk_fs_visitor::emit_fb_writes() { assert(stage == MESA_SHADER_FRAGMENT); - struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); - brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; + struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data); + elk_wm_prog_key *key = (elk_wm_prog_key*) this->key; if (source_depth_to_render_target && devinfo->ver == 6) { /* For outputting oDepth on gfx6, SIMD8 writes have to be used. This @@ -819,20 +819,20 @@ fs_visitor::emit_fb_writes() } void -fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) +elk_fs_visitor::emit_urb_writes(const elk_fs_reg &gs_vertex_count) { int slot, urb_offset, length; int starting_urb_offset = 0; - const struct brw_vue_prog_data *vue_prog_data = - brw_vue_prog_data(this->prog_data); - const struct brw_vs_prog_key *vs_key = - (const struct brw_vs_prog_key *) this->key; + const struct elk_vue_prog_data *vue_prog_data = + elk_vue_prog_data(this->prog_data); + const struct elk_vs_prog_key *vs_key = + (const struct elk_vs_prog_key *) this->key; const GLbitfield64 psiz_mask = VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PSIZ | VARYING_BIT_PRIMITIVE_SHADING_RATE; const struct intel_vue_map *vue_map = &vue_prog_data->vue_map; bool flush; - fs_reg sources[8]; - fs_reg urb_handle; + elk_fs_reg sources[8]; + elk_fs_reg urb_handle; switch (stage) { case MESA_SHADER_VERTEX: @@ -850,11 +850,11 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) const fs_builder bld = fs_builder(this).at_end(); - fs_reg per_slot_offsets; + elk_fs_reg per_slot_offsets; if (stage == MESA_SHADER_GEOMETRY) { - const struct brw_gs_prog_data *gs_prog_data = - brw_gs_prog_data(this->prog_data); + const struct elk_gs_prog_data *gs_prog_data = + elk_gs_prog_data(this->prog_data); /* We need to increment the Global Offset to skip over the control data * header and the extra "Vertex Count" field (1 HWord) at the beginning @@ -869,12 +869,12 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) gs_prog_data->output_vertex_size_hwords * 2; if (gs_vertex_count.file == IMM) { - per_slot_offsets = brw_imm_ud(output_vertex_size_owords * + per_slot_offsets = elk_imm_ud(output_vertex_size_owords * gs_vertex_count.ud); } else { per_slot_offsets = vgrf(glsl_uint_type()); bld.MUL(per_slot_offsets, gs_vertex_count, - brw_imm_ud(output_vertex_size_owords)); + elk_imm_ud(output_vertex_size_owords)); } } @@ -887,7 +887,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) */ int last_slot = vue_map->num_slots - 1; while (last_slot > 0 && - (vue_map->slot_to_varying[last_slot] == BRW_VARYING_SLOT_PAD || + (vue_map->slot_to_varying[last_slot] == ELK_VARYING_SLOT_PAD || outputs[vue_map->slot_to_varying[last_slot]].file == BAD_FILE)) { last_slot--; } @@ -908,18 +908,18 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) break; } - fs_reg zero(VGRF, alloc.allocate(dispatch_width / 8), - BRW_REGISTER_TYPE_UD); - bld.MOV(zero, brw_imm_ud(0u)); + elk_fs_reg zero(VGRF, alloc.allocate(dispatch_width / 8), + ELK_REGISTER_TYPE_UD); + bld.MOV(zero, elk_imm_ud(0u)); if (vue_map->slots_valid & VARYING_BIT_PRIMITIVE_SHADING_RATE && this->outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE].file != BAD_FILE) { sources[length++] = this->outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE]; } else if (devinfo->has_coarse_pixel_primitive_and_cb) { uint32_t one_fp16 = 0x3C00; - fs_reg one_by_one_fp16(VGRF, alloc.allocate(dispatch_width / 8), - BRW_REGISTER_TYPE_UD); - bld.MOV(one_by_one_fp16, brw_imm_ud((one_fp16 << 16) | one_fp16)); + elk_fs_reg one_by_one_fp16(VGRF, alloc.allocate(dispatch_width / 8), + ELK_REGISTER_TYPE_UD); + bld.MOV(one_by_one_fp16, elk_imm_ud((one_fp16 << 16) | one_fp16)); sources[length++] = one_by_one_fp16; } else { sources[length++] = zero; @@ -941,7 +941,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) sources[length++] = zero; break; } - case BRW_VARYING_SLOT_NDC: + case ELK_VARYING_SLOT_NDC: case VARYING_SLOT_EDGE: unreachable("unexpected scalar vs output"); break; @@ -955,7 +955,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) * slot for writing we flush a mlen 5 urb write, otherwise we just * advance the urb_offset. */ - if (varying == BRW_VARYING_SLOT_PAD || + if (varying == ELK_VARYING_SLOT_PAD || this->outputs[varying].file == BAD_FILE) { if (length > 0) flush = true; @@ -973,9 +973,9 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) * temp register and use that for the payload. */ for (int i = 0; i < 4; i++) { - fs_reg reg = fs_reg(VGRF, alloc.allocate(dispatch_width / 8), + elk_fs_reg reg = elk_fs_reg(VGRF, alloc.allocate(dispatch_width / 8), outputs[varying].type); - fs_reg src = offset(this->outputs[varying], bld, i); + elk_fs_reg src = offset(this->outputs[varying], bld, i); set_saturate(true, bld.MOV(reg, src)); sources[length++] = reg; } @@ -1005,17 +1005,17 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) if (length == 8 || (length > 0 && slot == last_slot)) flush = true; if (flush) { - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle; srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = per_slot_offsets; - srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, + srcs[URB_LOGICAL_SRC_DATA] = elk_fs_reg(VGRF, alloc.allocate((dispatch_width / 8) * length), - BRW_REGISTER_TYPE_F); - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); + ELK_REGISTER_TYPE_F); + srcs[URB_LOGICAL_SRC_COMPONENTS] = elk_imm_ud(length); abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0); - fs_inst *inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + elk_fs_inst *inst = abld.emit(ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); /* For ICL Wa_1805992985 one needs additional write in the end. */ @@ -1050,19 +1050,19 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) if (stage == MESA_SHADER_GEOMETRY) return; - fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(dispatch_width / 8), - BRW_REGISTER_TYPE_UD); - fs_reg payload = fs_reg(VGRF, alloc.allocate(dispatch_width / 8), - BRW_REGISTER_TYPE_UD); + elk_fs_reg uniform_urb_handle = elk_fs_reg(VGRF, alloc.allocate(dispatch_width / 8), + ELK_REGISTER_TYPE_UD); + elk_fs_reg payload = elk_fs_reg(VGRF, alloc.allocate(dispatch_width / 8), + ELK_REGISTER_TYPE_UD); bld.exec_all().MOV(uniform_urb_handle, urb_handle); - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = uniform_urb_handle; srcs[URB_LOGICAL_SRC_DATA] = payload; - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(1); + srcs[URB_LOGICAL_SRC_COMPONENTS] = elk_imm_ud(1); - fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + elk_fs_inst *inst = bld.emit(ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->eot = true; inst->offset = 1; @@ -1077,9 +1077,9 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) */ if (devinfo->ver == 11 && stage == MESA_SHADER_TESS_EVAL) { assert(dispatch_width == 8); - fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); - fs_reg uniform_mask = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); - fs_reg payload = fs_reg(VGRF, alloc.allocate(4), BRW_REGISTER_TYPE_UD); + elk_fs_reg uniform_urb_handle = elk_fs_reg(VGRF, alloc.allocate(1), ELK_REGISTER_TYPE_UD); + elk_fs_reg uniform_mask = elk_fs_reg(VGRF, alloc.allocate(1), ELK_REGISTER_TYPE_UD); + elk_fs_reg payload = elk_fs_reg(VGRF, alloc.allocate(4), ELK_REGISTER_TYPE_UD); /* Workaround requires all 8 channels (lanes) to be valid. This is * understood to mean they all need to be alive. First trick is to find @@ -1102,19 +1102,19 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) * 4 slots data. All are explicitly zeros in order to to keep the MBZ * area written as zeros. */ - bld.exec_all().MOV(uniform_mask, brw_imm_ud(0x10000u)); - bld.exec_all().MOV(offset(payload, bld, 0), brw_imm_ud(0u)); - bld.exec_all().MOV(offset(payload, bld, 1), brw_imm_ud(0u)); - bld.exec_all().MOV(offset(payload, bld, 2), brw_imm_ud(0u)); - bld.exec_all().MOV(offset(payload, bld, 3), brw_imm_ud(0u)); + bld.exec_all().MOV(uniform_mask, elk_imm_ud(0x10000u)); + bld.exec_all().MOV(offset(payload, bld, 0), elk_imm_ud(0u)); + bld.exec_all().MOV(offset(payload, bld, 1), elk_imm_ud(0u)); + bld.exec_all().MOV(offset(payload, bld, 2), elk_imm_ud(0u)); + bld.exec_all().MOV(offset(payload, bld, 3), elk_imm_ud(0u)); - fs_reg srcs[URB_LOGICAL_NUM_SRCS]; + elk_fs_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = uniform_urb_handle; srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = uniform_mask; srcs[URB_LOGICAL_SRC_DATA] = payload; - srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(4); + srcs[URB_LOGICAL_SRC_COMPONENTS] = elk_imm_ud(4); - fs_inst *inst = bld.exec_all().emit(SHADER_OPCODE_URB_WRITE_LOGICAL, + elk_fs_inst *inst = bld.exec_all().emit(ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->eot = true; inst->offset = 0; @@ -1122,26 +1122,26 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) } void -fs_visitor::emit_urb_fence() +elk_fs_visitor::emit_urb_fence() { const fs_builder bld = fs_builder(this).at_end(); - fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD); - fs_inst *fence = bld.emit(SHADER_OPCODE_MEMORY_FENCE, dst, - brw_vec8_grf(0, 0), - brw_imm_ud(true), - brw_imm_ud(0)); - fence->sfid = BRW_SFID_URB; + elk_fs_reg dst = bld.vgrf(ELK_REGISTER_TYPE_UD); + elk_fs_inst *fence = bld.emit(ELK_SHADER_OPCODE_MEMORY_FENCE, dst, + elk_vec8_grf(0, 0), + elk_imm_ud(true), + elk_imm_ud(0)); + fence->sfid = ELK_SFID_URB; fence->desc = lsc_fence_msg_desc(devinfo, LSC_FENCE_LOCAL, LSC_FLUSH_TYPE_NONE, true); - bld.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE, + bld.exec_all().group(1, 0).emit(ELK_FS_OPCODE_SCHEDULING_FENCE, bld.null_reg_ud(), &dst, 1); } void -fs_visitor::emit_cs_terminate() +elk_fs_visitor::emit_cs_terminate() { assert(devinfo->ver >= 7); const fs_builder bld = fs_builder(this).at_end(); @@ -1150,45 +1150,45 @@ fs_visitor::emit_cs_terminate() * g112-127. So, copy it to a virtual register, The register allocator will * make sure it uses the appropriate register range. */ - struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD); - fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); + struct elk_reg g0 = retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD); + elk_fs_reg payload = elk_fs_reg(VGRF, alloc.allocate(1), ELK_REGISTER_TYPE_UD); bld.group(8, 0).exec_all().MOV(payload, g0); /* Send a message to the thread spawner to terminate the thread. */ - fs_inst *inst = bld.exec_all() - .emit(CS_OPCODE_CS_TERMINATE, reg_undef, payload); + elk_fs_inst *inst = bld.exec_all() + .emit(ELK_CS_OPCODE_CS_TERMINATE, reg_undef, payload); inst->eot = true; } -fs_visitor::fs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const brw_base_prog_key *key, - struct brw_stage_prog_data *prog_data, +elk_fs_visitor::elk_fs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const elk_base_prog_key *key, + struct elk_stage_prog_data *prog_data, const nir_shader *shader, unsigned dispatch_width, bool needs_register_pressure, bool debug_enabled) - : backend_shader(compiler, params, shader, prog_data, debug_enabled), + : elk_backend_shader(compiler, params, shader, prog_data, debug_enabled), key(key), gs_compile(NULL), prog_data(prog_data), live_analysis(this), regpressure_analysis(this), performance_analysis(this), needs_register_pressure(needs_register_pressure), dispatch_width(dispatch_width), max_polygons(0), - api_subgroup_size(brw_nir_api_subgroup_size(shader, dispatch_width)) + api_subgroup_size(elk_nir_api_subgroup_size(shader, dispatch_width)) { init(); } -fs_visitor::fs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const brw_wm_prog_key *key, - struct brw_wm_prog_data *prog_data, +elk_fs_visitor::elk_fs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const elk_wm_prog_key *key, + struct elk_wm_prog_data *prog_data, const nir_shader *shader, unsigned dispatch_width, unsigned max_polygons, bool needs_register_pressure, bool debug_enabled) - : backend_shader(compiler, params, shader, &prog_data->base, + : elk_backend_shader(compiler, params, shader, &prog_data->base, debug_enabled), key(&key->base), gs_compile(NULL), prog_data(&prog_data->base), live_analysis(this), regpressure_analysis(this), @@ -1196,7 +1196,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler, needs_register_pressure(needs_register_pressure), dispatch_width(dispatch_width), max_polygons(max_polygons), - api_subgroup_size(brw_nir_api_subgroup_size(shader, dispatch_width)) + api_subgroup_size(elk_nir_api_subgroup_size(shader, dispatch_width)) { init(); assert(api_subgroup_size == 0 || @@ -1205,14 +1205,14 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler, api_subgroup_size == 32); } -fs_visitor::fs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - struct brw_gs_compile *c, - struct brw_gs_prog_data *prog_data, +elk_fs_visitor::elk_fs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + struct elk_gs_compile *c, + struct elk_gs_prog_data *prog_data, const nir_shader *shader, bool needs_register_pressure, bool debug_enabled) - : backend_shader(compiler, params, shader, &prog_data->base.base, + : elk_backend_shader(compiler, params, shader, &prog_data->base.base, debug_enabled), key(&c->key.base), gs_compile(c), prog_data(&prog_data->base.base), @@ -1221,7 +1221,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler, needs_register_pressure(needs_register_pressure), dispatch_width(compiler->devinfo->ver >= 20 ? 16 : 8), max_polygons(0), - api_subgroup_size(brw_nir_api_subgroup_size(shader, dispatch_width)) + api_subgroup_size(elk_nir_api_subgroup_size(shader, dispatch_width)) { init(); assert(api_subgroup_size == 0 || @@ -1231,7 +1231,7 @@ fs_visitor::fs_visitor(const struct brw_compiler *compiler, } void -fs_visitor::init() +elk_fs_visitor::init() { if (key) this->key_tex = &key->tex; @@ -1248,7 +1248,7 @@ fs_visitor::init() this->source_depth_to_render_target = false; this->runtime_check_aads_emit = false; this->first_non_payload_grf = 0; - this->max_grf = devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF; + this->max_grf = devinfo->ver >= 7 ? GFX7_MRF_HACK_START : ELK_MAX_GRF; this->uniforms = 0; this->last_scratch = 0; @@ -1260,7 +1260,7 @@ fs_visitor::init() this->spilled_any_registers = false; } -fs_visitor::~fs_visitor() +elk_fs_visitor::~elk_fs_visitor() { delete this->payload_; } diff --git a/src/intel/compiler/elk/elk_gfx6_gs_visitor.cpp b/src/intel/compiler/elk/elk_gfx6_gs_visitor.cpp index 188d1935a36..ba74c2045b8 100644 --- a/src/intel/compiler/elk/elk_gfx6_gs_visitor.cpp +++ b/src/intel/compiler/elk/elk_gfx6_gs_visitor.cpp @@ -67,14 +67,14 @@ gfx6_gs_visitor::emit_prolog() (prog_data->vue_map.num_slots + 1) * nir->info.gs.vertices_out); this->vertex_output_offset = src_reg(this, glsl_uint_type()); - emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u))); + emit(MOV(dst_reg(this->vertex_output_offset), elk_imm_ud(0u))); /* MRF 1 will be the header for all messages (FF_SYNC and URB_WRITES), * so initialize it once to R0. */ vec4_instruction *inst = emit(MOV(dst_reg(MRF, 1), - retype(brw_vec8_grf(0, 0), - BRW_REGISTER_TYPE_UD))); + retype(elk_vec8_grf(0, 0), + ELK_REGISTER_TYPE_UD))); inst->force_writemask_all = true; /* This will be used as a temporary to store writeback data of FF_SYNC @@ -89,13 +89,13 @@ gfx6_gs_visitor::emit_prolog() * headers. */ this->first_vertex = src_reg(this, glsl_uint_type()); - emit(MOV(dst_reg(this->first_vertex), brw_imm_ud(URB_WRITE_PRIM_START))); + emit(MOV(dst_reg(this->first_vertex), elk_imm_ud(URB_WRITE_PRIM_START))); /* The FF_SYNC message requires to know the number of primitives generated, * so keep a counter for this. */ this->prim_count = src_reg(this, glsl_uint_type()); - emit(MOV(dst_reg(this->prim_count), brw_imm_ud(0u))); + emit(MOV(dst_reg(this->prim_count), elk_imm_ud(0u))); if (gs_prog_data->num_transform_feedback_bindings) { /* Create a virtual register to hold destination indices in SOL */ @@ -107,7 +107,7 @@ gfx6_gs_visitor::emit_prolog() /* Create a virtual register to hold max values of SVBI */ this->max_svbi = src_reg(this, glsl_uvec4_type()); emit(MOV(dst_reg(this->max_svbi), - src_reg(retype(brw_vec1_grf(1, 4), BRW_REGISTER_TYPE_UD)))); + src_reg(retype(elk_vec1_grf(1, 4), ELK_REGISTER_TYPE_UD)))); } /* PrimitveID is delivered in r0.1 of the thread payload. If the program @@ -130,8 +130,8 @@ gfx6_gs_visitor::emit_prolog() */ if (gs_prog_data->include_primitive_id) { this->primitive_id = - src_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD)); - emit(GS_OPCODE_SET_PRIMITIVE_ID, dst_reg(this->primitive_id)); + src_reg(retype(elk_vec8_grf(1, 0), ELK_REGISTER_TYPE_UD)); + emit(ELK_GS_OPCODE_SET_PRIMITIVE_ID, dst_reg(this->primitive_id)); } } @@ -170,7 +170,7 @@ gfx6_gs_visitor::gs_emit_vertex(int stream_id) } emit(ADD(dst_reg(this->vertex_output_offset), - this->vertex_output_offset, brw_imm_ud(1u))); + this->vertex_output_offset, elk_imm_ud(1u))); } /* Now buffer flags for this vertex */ @@ -181,9 +181,9 @@ gfx6_gs_visitor::gs_emit_vertex(int stream_id) /* If we are outputting points, then every vertex has PrimStart and * PrimEnd set. */ - emit(MOV(dst, brw_imm_d((_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT) | + emit(MOV(dst, elk_imm_d((_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START | URB_WRITE_PRIM_END))); - emit(ADD(dst_reg(this->prim_count), this->prim_count, brw_imm_ud(1u))); + emit(ADD(dst_reg(this->prim_count), this->prim_count, elk_imm_ud(1u))); } else { /* Otherwise, we can only set the PrimStart flag, which we have stored * in the first_vertex register. We will have to wait until we execute @@ -191,12 +191,12 @@ gfx6_gs_visitor::gs_emit_vertex(int stream_id) * vertex. */ emit(OR(dst, this->first_vertex, - brw_imm_ud(gs_prog_data->output_topology << + elk_imm_ud(gs_prog_data->output_topology << URB_WRITE_PRIM_TYPE_SHIFT))); - emit(MOV(dst_reg(this->first_vertex), brw_imm_ud(0u))); + emit(MOV(dst_reg(this->first_vertex), elk_imm_ud(0u))); } emit(ADD(dst_reg(this->vertex_output_offset), - this->vertex_output_offset, brw_imm_ud(1u))); + this->vertex_output_offset, elk_imm_ud(1u))); } void @@ -220,33 +220,33 @@ gfx6_gs_visitor::gs_end_primitive() */ unsigned num_output_vertices = nir->info.gs.vertices_out; emit(CMP(dst_null_ud(), this->vertex_count, - brw_imm_ud(num_output_vertices + 1), BRW_CONDITIONAL_L)); + elk_imm_ud(num_output_vertices + 1), ELK_CONDITIONAL_L)); vec4_instruction *inst = emit(CMP(dst_null_ud(), - this->vertex_count, brw_imm_ud(0u), - BRW_CONDITIONAL_NEQ)); - inst->predicate = BRW_PREDICATE_NORMAL; - emit(IF(BRW_PREDICATE_NORMAL)); + this->vertex_count, elk_imm_ud(0u), + ELK_CONDITIONAL_NEQ)); + inst->predicate = ELK_PREDICATE_NORMAL; + emit(IF(ELK_PREDICATE_NORMAL)); { /* vertex_output_offset is already pointing at the first entry of the * next vertex. So subtract 1 to modify the flags for the previous * vertex. */ src_reg offset(this, glsl_uint_type()); - emit(ADD(dst_reg(offset), this->vertex_output_offset, brw_imm_d(-1))); + emit(ADD(dst_reg(offset), this->vertex_output_offset, elk_imm_d(-1))); src_reg dst(this->vertex_output); dst.reladdr = ralloc(mem_ctx, src_reg); memcpy(dst.reladdr, &offset, sizeof(src_reg)); - emit(OR(dst_reg(dst), dst, brw_imm_d(URB_WRITE_PRIM_END))); - emit(ADD(dst_reg(this->prim_count), this->prim_count, brw_imm_ud(1u))); + emit(OR(dst_reg(dst), dst, elk_imm_d(URB_WRITE_PRIM_END))); + emit(ADD(dst_reg(this->prim_count), this->prim_count, elk_imm_ud(1u))); /* Set the first vertex flag to indicate that the next vertex will start * a primitive. */ - emit(MOV(dst_reg(this->first_vertex), brw_imm_d(URB_WRITE_PRIM_START))); + emit(MOV(dst_reg(this->first_vertex), elk_imm_d(URB_WRITE_PRIM_START))); } - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); } void @@ -264,13 +264,13 @@ gfx6_gs_visitor::emit_urb_write_header(int mrf) src_reg flags_offset(this, glsl_uint_type()); emit(ADD(dst_reg(flags_offset), this->vertex_output_offset, - brw_imm_d(prog_data->vue_map.num_slots))); + elk_imm_d(prog_data->vue_map.num_slots))); src_reg flags_data(this->vertex_output); flags_data.reladdr = ralloc(mem_ctx, src_reg); memcpy(flags_data.reladdr, &flags_offset, sizeof(src_reg)); - emit(GS_OPCODE_SET_DWORD_2, dst_reg(MRF, mrf), flags_data); + emit(ELK_GS_OPCODE_SET_DWORD_2, dst_reg(MRF, mrf), flags_data); } static unsigned @@ -293,8 +293,8 @@ gfx6_gs_visitor::emit_snb_gs_urb_write_opcode(bool complete, int base_mrf, if (!complete) { /* If the vertex is not complete we don't have to do anything special */ - inst = emit(VEC4_GS_OPCODE_URB_WRITE); - inst->urb_write_flags = BRW_URB_WRITE_NO_FLAGS; + inst = emit(ELK_VEC4_GS_OPCODE_URB_WRITE); + inst->urb_write_flags = ELK_URB_WRITE_NO_FLAGS; } else { /* Otherwise we always request to allocate a new VUE handle. If this is * the last write before the EOT message and the new handle never gets @@ -304,8 +304,8 @@ gfx6_gs_visitor::emit_snb_gs_urb_write_opcode(bool complete, int base_mrf, * which would require to end the program with an IF/ELSE/ENDIF block, * something we do not want. */ - inst = emit(VEC4_GS_OPCODE_URB_WRITE_ALLOCATE); - inst->urb_write_flags = BRW_URB_WRITE_COMPLETE; + inst = emit(ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE); + inst->urb_write_flags = ELK_URB_WRITE_COMPLETE; inst->dst = dst_reg(MRF, base_mrf); inst->src[0] = this->temp; } @@ -323,10 +323,10 @@ gfx6_gs_visitor::emit_thread_end() * points because in the point case we set PrimEnd on all vertices. */ if (nir->info.gs.output_primitive != MESA_PRIM_POINTS) { - emit(CMP(dst_null_ud(), this->first_vertex, brw_imm_ud(0u), BRW_CONDITIONAL_Z)); - emit(IF(BRW_PREDICATE_NORMAL)); + emit(CMP(dst_null_ud(), this->first_vertex, elk_imm_ud(0u), ELK_CONDITIONAL_Z)); + emit(IF(ELK_PREDICATE_NORMAL)); gs_end_primitive(); - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); } /* Here we have to: @@ -354,34 +354,34 @@ gfx6_gs_visitor::emit_thread_end() vec4_instruction *inst = NULL; if (gs_prog_data->num_transform_feedback_bindings) { src_reg sol_temp(this, glsl_uvec4_type()); - emit(GS_OPCODE_FF_SYNC_SET_PRIMITIVES, + emit(ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES, dst_reg(this->svbi), this->vertex_count, this->prim_count, sol_temp); - inst = emit(GS_OPCODE_FF_SYNC, + inst = emit(ELK_GS_OPCODE_FF_SYNC, dst_reg(this->temp), this->prim_count, this->svbi); } else { - inst = emit(GS_OPCODE_FF_SYNC, - dst_reg(this->temp), this->prim_count, brw_imm_ud(0u)); + inst = emit(ELK_GS_OPCODE_FF_SYNC, + dst_reg(this->temp), this->prim_count, elk_imm_ud(0u)); } inst->base_mrf = base_mrf; - emit(CMP(dst_null_ud(), this->vertex_count, brw_imm_ud(0u), BRW_CONDITIONAL_G)); - emit(IF(BRW_PREDICATE_NORMAL)); + emit(CMP(dst_null_ud(), this->vertex_count, elk_imm_ud(0u), ELK_CONDITIONAL_G)); + emit(IF(ELK_PREDICATE_NORMAL)); { /* Loop over all buffered vertices and emit URB write messages */ this->current_annotation = "gfx6 thread end: urb writes init"; src_reg vertex(this, glsl_uint_type()); - emit(MOV(dst_reg(vertex), brw_imm_ud(0u))); - emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u))); + emit(MOV(dst_reg(vertex), elk_imm_ud(0u))); + emit(MOV(dst_reg(this->vertex_output_offset), elk_imm_ud(0u))); this->current_annotation = "gfx6 thread end: urb writes"; - emit(BRW_OPCODE_DO); + emit(ELK_OPCODE_DO); { - emit(CMP(dst_null_d(), vertex, this->vertex_count, BRW_CONDITIONAL_GE)); - inst = emit(BRW_OPCODE_BREAK); - inst->predicate = BRW_PREDICATE_NORMAL; + emit(CMP(dst_null_d(), vertex, this->vertex_count, ELK_CONDITIONAL_GE)); + inst = emit(ELK_OPCODE_BREAK); + inst->predicate = ELK_PREDICATE_NORMAL; /* First we prepare the message header */ emit_urb_write_header(base_mrf); @@ -418,13 +418,13 @@ gfx6_gs_visitor::emit_thread_end() mrf++; emit(ADD(dst_reg(this->vertex_output_offset), - this->vertex_output_offset, brw_imm_ud(1u))); + this->vertex_output_offset, elk_imm_ud(1u))); /* If this was max_usable_mrf, we can't fit anything more into * this URB WRITE. Same if we reached the max. message length. */ if (mrf > max_usable_mrf || - align_interleaved_urb_mlen(mrf - base_mrf + 1) > BRW_MAX_MSG_LENGTH) { + align_interleaved_urb_mlen(mrf - base_mrf + 1) > ELK_MAX_MSG_LENGTH) { slot++; break; } @@ -439,16 +439,16 @@ gfx6_gs_visitor::emit_thread_end() * writing the next vertex. */ emit(ADD(dst_reg(this->vertex_output_offset), - this->vertex_output_offset, brw_imm_ud(1u))); + this->vertex_output_offset, elk_imm_ud(1u))); - emit(ADD(dst_reg(vertex), vertex, brw_imm_ud(1u))); + emit(ADD(dst_reg(vertex), vertex, elk_imm_ud(1u))); } - emit(BRW_OPCODE_WHILE); + emit(ELK_OPCODE_WHILE); if (gs_prog_data->num_transform_feedback_bindings) xfb_write(); } - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); /* Finally, emit EOT message. * @@ -470,13 +470,13 @@ gfx6_gs_visitor::emit_thread_end() if (gs_prog_data->num_transform_feedback_bindings) { /* When emitting EOT, set SONumPrimsWritten Increment Value. */ src_reg data(this, glsl_uint_type()); - emit(AND(dst_reg(data), this->sol_prim_written, brw_imm_ud(0xffffu))); - emit(SHL(dst_reg(data), data, brw_imm_ud(16u))); - emit(GS_OPCODE_SET_DWORD_2, dst_reg(MRF, base_mrf), data); + emit(AND(dst_reg(data), this->sol_prim_written, elk_imm_ud(0xffffu))); + emit(SHL(dst_reg(data), data, elk_imm_ud(16u))); + emit(ELK_GS_OPCODE_SET_DWORD_2, dst_reg(MRF, base_mrf), data); } - inst = emit(GS_OPCODE_THREAD_END); - inst->urb_write_flags = BRW_URB_WRITE_COMPLETE | BRW_URB_WRITE_UNUSED; + inst = emit(ELK_GS_OPCODE_THREAD_END); + inst->urb_write_flags = ELK_URB_WRITE_COMPLETE | ELK_URB_WRITE_UNUSED; inst->base_mrf = base_mrf; inst->mlen = 1; } @@ -484,7 +484,7 @@ gfx6_gs_visitor::emit_thread_end() void gfx6_gs_visitor::setup_payload() { - int attribute_map[BRW_VARYING_SLOT_COUNT * MAX_GS_INPUT_VERTICES]; + int attribute_map[ELK_VARYING_SLOT_COUNT * MAX_GS_INPUT_VERTICES]; /* Attributes are going to be interleaved, so one register contains two * attribute slots. @@ -551,8 +551,8 @@ gfx6_gs_visitor::xfb_write() this->current_annotation = "gfx6 thread end: svb writes init"; - emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u))); - emit(MOV(dst_reg(this->sol_prim_written), brw_imm_ud(0u))); + emit(MOV(dst_reg(this->vertex_output_offset), elk_imm_ud(0u))); + emit(MOV(dst_reg(this->sol_prim_written), elk_imm_ud(0u))); /* Check that at least one primitive can be written * @@ -563,37 +563,37 @@ gfx6_gs_visitor::xfb_write() * transform feedback is in interleaved or separate attribs mode. */ src_reg sol_temp(this, glsl_uvec4_type()); - emit(ADD(dst_reg(sol_temp), this->svbi, brw_imm_ud(num_verts))); + emit(ADD(dst_reg(sol_temp), this->svbi, elk_imm_ud(num_verts))); /* Compare SVBI calculated number with the maximum value, which is * in R1.4 (previously saved in this->max_svbi) for gfx6. */ - emit(CMP(dst_null_d(), sol_temp, this->max_svbi, BRW_CONDITIONAL_LE)); - emit(IF(BRW_PREDICATE_NORMAL)); + emit(CMP(dst_null_d(), sol_temp, this->max_svbi, ELK_CONDITIONAL_LE)); + emit(IF(ELK_PREDICATE_NORMAL)); { vec4_instruction *inst = emit(MOV(dst_reg(destination_indices), - brw_imm_vf4(brw_float_to_vf(0.0), - brw_float_to_vf(1.0), - brw_float_to_vf(2.0), - brw_float_to_vf(0.0)))); + elk_imm_vf4(elk_float_to_vf(0.0), + elk_float_to_vf(1.0), + elk_float_to_vf(2.0), + elk_float_to_vf(0.0)))); inst->force_writemask_all = true; emit(ADD(dst_reg(this->destination_indices), this->destination_indices, this->svbi)); } - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); /* Write transform feedback data for all processed vertices. */ for (int i = 0; i < (int)nir->info.gs.vertices_out; i++) { - emit(MOV(dst_reg(sol_temp), brw_imm_d(i))); + emit(MOV(dst_reg(sol_temp), elk_imm_d(i))); emit(CMP(dst_null_d(), sol_temp, this->vertex_count, - BRW_CONDITIONAL_L)); - emit(IF(BRW_PREDICATE_NORMAL)); + ELK_CONDITIONAL_L)); + emit(IF(ELK_PREDICATE_NORMAL)); { xfb_program(i, num_verts); } - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); } } @@ -607,11 +607,11 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts) /* Check for buffer overflow: we need room to write the complete primitive * (all vertices). Otherwise, avoid writing any vertices for it */ - emit(ADD(dst_reg(sol_temp), this->sol_prim_written, brw_imm_ud(1u))); - emit(MUL(dst_reg(sol_temp), sol_temp, brw_imm_ud(num_verts))); + emit(ADD(dst_reg(sol_temp), this->sol_prim_written, elk_imm_ud(1u))); + emit(MUL(dst_reg(sol_temp), sol_temp, elk_imm_ud(num_verts))); emit(ADD(dst_reg(sol_temp), sol_temp, this->svbi)); - emit(CMP(dst_null_d(), sol_temp, this->max_svbi, BRW_CONDITIONAL_LE)); - emit(IF(BRW_PREDICATE_NORMAL)); + emit(CMP(dst_null_d(), sol_temp, this->max_svbi, ELK_CONDITIONAL_LE)); + emit(IF(ELK_PREDICATE_NORMAL)); { /* Avoid overwriting MRF 1 as it is used as URB write message header */ dst_reg mrf_reg(MRF, 2); @@ -625,7 +625,7 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts) gs_prog_data->transform_feedback_bindings[binding]; /* Set up the correct destination index for this vertex */ - vec4_instruction *inst = emit(GS_OPCODE_SVB_SET_DST_INDEX, + vec4_instruction *inst = emit(ELK_GS_OPCODE_SVB_SET_DST_INDEX, mrf_reg, this->destination_indices); inst->sol_vertex = vertex % num_verts; @@ -646,13 +646,13 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts) src_reg data(this->vertex_output); data.reladdr = ralloc(mem_ctx, src_reg); int offset = get_vertex_output_offset_for_varying(vertex, varying); - emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_d(offset))); + emit(MOV(dst_reg(this->vertex_output_offset), elk_imm_d(offset))); memcpy(data.reladdr, &this->vertex_output_offset, sizeof(src_reg)); data.type = output_reg[varying][0].type; data.swizzle = gs_prog_data->transform_feedback_swizzles[binding]; /* Write data */ - inst = emit(GS_OPCODE_SVB_WRITE, mrf_reg, data, sol_temp); + inst = emit(ELK_GS_OPCODE_SVB_WRITE, mrf_reg, data, sol_temp); inst->sol_binding = binding; inst->sol_final_write = final_write; @@ -662,15 +662,15 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts) */ emit(ADD(dst_reg(this->destination_indices), this->destination_indices, - brw_imm_ud(num_verts))); + elk_imm_ud(num_verts))); emit(ADD(dst_reg(this->sol_prim_written), - this->sol_prim_written, brw_imm_ud(1u))); + this->sol_prim_written, elk_imm_ud(1u))); } } this->current_annotation = NULL; } - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); } int diff --git a/src/intel/compiler/elk/elk_gfx6_gs_visitor.h b/src/intel/compiler/elk/elk_gfx6_gs_visitor.h index c0a35713e1f..31d508f0e56 100644 --- a/src/intel/compiler/elk/elk_gfx6_gs_visitor.h +++ b/src/intel/compiler/elk/elk_gfx6_gs_visitor.h @@ -35,10 +35,10 @@ namespace elk { class gfx6_gs_visitor : public vec4_gs_visitor { public: - gfx6_gs_visitor(const struct brw_compiler *comp, - const struct brw_compile_params *params, - struct brw_gs_compile *c, - struct brw_gs_prog_data *prog_data, + gfx6_gs_visitor(const struct elk_compiler *comp, + const struct elk_compile_params *params, + struct elk_gs_compile *c, + struct elk_gs_prog_data *prog_data, const nir_shader *shader, bool no_spills, bool debug_enabled) : diff --git a/src/intel/compiler/elk/elk_gram.y b/src/intel/compiler/elk/elk_gram.y index ea3d9238696..ad1f83306c5 100644 --- a/src/intel/compiler/elk/elk_gram.y +++ b/src/intel/compiler/elk/elk_gram.y @@ -90,10 +90,10 @@ isPowerofTwo(unsigned int x) return x && (!(x & (x - 1))); } -static struct brw_reg -set_direct_src_operand(struct brw_reg *reg, int type) +static struct elk_reg +set_direct_src_operand(struct elk_reg *reg, int type) { - return brw_reg(reg->file, + return elk_reg(reg->file, reg->nr, reg->subnr, 0, // negate @@ -102,59 +102,59 @@ set_direct_src_operand(struct brw_reg *reg, int type) 0, // vstride 0, // width 0, // hstride - BRW_SWIZZLE_NOOP, + ELK_SWIZZLE_NOOP, WRITEMASK_XYZW); } static void -i965_asm_unary_instruction(int opcode, struct brw_codegen *p, - struct brw_reg dest, struct brw_reg src0) +i965_asm_unary_instruction(int opcode, struct elk_codegen *p, + struct elk_reg dest, struct elk_reg src0) { switch (opcode) { - case BRW_OPCODE_BFREV: - brw_BFREV(p, dest, src0); + case ELK_OPCODE_BFREV: + elk_BFREV(p, dest, src0); break; - case BRW_OPCODE_CBIT: - brw_CBIT(p, dest, src0); + case ELK_OPCODE_CBIT: + elk_CBIT(p, dest, src0); break; - case BRW_OPCODE_F32TO16: - brw_F32TO16(p, dest, src0); + case ELK_OPCODE_F32TO16: + elk_F32TO16(p, dest, src0); break; - case BRW_OPCODE_F16TO32: - brw_F16TO32(p, dest, src0); + case ELK_OPCODE_F16TO32: + elk_F16TO32(p, dest, src0); break; - case BRW_OPCODE_MOV: - brw_MOV(p, dest, src0); + case ELK_OPCODE_MOV: + elk_MOV(p, dest, src0); break; - case BRW_OPCODE_FBL: - brw_FBL(p, dest, src0); + case ELK_OPCODE_FBL: + elk_FBL(p, dest, src0); break; - case BRW_OPCODE_FRC: - brw_FRC(p, dest, src0); + case ELK_OPCODE_FRC: + elk_FRC(p, dest, src0); break; - case BRW_OPCODE_FBH: - brw_FBH(p, dest, src0); + case ELK_OPCODE_FBH: + elk_FBH(p, dest, src0); break; - case BRW_OPCODE_NOT: - brw_NOT(p, dest, src0); + case ELK_OPCODE_NOT: + elk_NOT(p, dest, src0); break; - case BRW_OPCODE_RNDE: - brw_RNDE(p, dest, src0); + case ELK_OPCODE_RNDE: + elk_RNDE(p, dest, src0); break; - case BRW_OPCODE_RNDZ: - brw_RNDZ(p, dest, src0); + case ELK_OPCODE_RNDZ: + elk_RNDZ(p, dest, src0); break; - case BRW_OPCODE_RNDD: - brw_RNDD(p, dest, src0); + case ELK_OPCODE_RNDD: + elk_RNDD(p, dest, src0); break; - case BRW_OPCODE_LZD: - brw_LZD(p, dest, src0); + case ELK_OPCODE_LZD: + elk_LZD(p, dest, src0); break; - case BRW_OPCODE_DIM: - brw_DIM(p, dest, src0); + case ELK_OPCODE_DIM: + elk_DIM(p, dest, src0); break; - case BRW_OPCODE_RNDU: - fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n"); + case ELK_OPCODE_RNDU: + fprintf(stderr, "Opcode ELK_OPCODE_RNDU unhandled\n"); break; default: fprintf(stderr, "Unsupported unary opcode\n"); @@ -163,92 +163,92 @@ i965_asm_unary_instruction(int opcode, struct brw_codegen *p, static void i965_asm_binary_instruction(int opcode, - struct brw_codegen *p, - struct brw_reg dest, - struct brw_reg src0, - struct brw_reg src1) + struct elk_codegen *p, + struct elk_reg dest, + struct elk_reg src0, + struct elk_reg src1) { switch (opcode) { - case BRW_OPCODE_ADDC: - brw_ADDC(p, dest, src0, src1); + case ELK_OPCODE_ADDC: + elk_ADDC(p, dest, src0, src1); break; - case BRW_OPCODE_BFI1: - brw_BFI1(p, dest, src0, src1); + case ELK_OPCODE_BFI1: + elk_BFI1(p, dest, src0, src1); break; - case BRW_OPCODE_DP2: - brw_DP2(p, dest, src0, src1); + case ELK_OPCODE_DP2: + elk_DP2(p, dest, src0, src1); break; - case BRW_OPCODE_DP3: - brw_DP3(p, dest, src0, src1); + case ELK_OPCODE_DP3: + elk_DP3(p, dest, src0, src1); break; - case BRW_OPCODE_DP4: - brw_DP4(p, dest, src0, src1); + case ELK_OPCODE_DP4: + elk_DP4(p, dest, src0, src1); break; - case BRW_OPCODE_DPH: - brw_DPH(p, dest, src0, src1); + case ELK_OPCODE_DPH: + elk_DPH(p, dest, src0, src1); break; - case BRW_OPCODE_LINE: - brw_LINE(p, dest, src0, src1); + case ELK_OPCODE_LINE: + elk_LINE(p, dest, src0, src1); break; - case BRW_OPCODE_MAC: - brw_MAC(p, dest, src0, src1); + case ELK_OPCODE_MAC: + elk_MAC(p, dest, src0, src1); break; - case BRW_OPCODE_MACH: - brw_MACH(p, dest, src0, src1); + case ELK_OPCODE_MACH: + elk_MACH(p, dest, src0, src1); break; - case BRW_OPCODE_PLN: - brw_PLN(p, dest, src0, src1); + case ELK_OPCODE_PLN: + elk_PLN(p, dest, src0, src1); break; - case BRW_OPCODE_ROL: - brw_ROL(p, dest, src0, src1); + case ELK_OPCODE_ROL: + elk_ROL(p, dest, src0, src1); break; - case BRW_OPCODE_ROR: - brw_ROR(p, dest, src0, src1); + case ELK_OPCODE_ROR: + elk_ROR(p, dest, src0, src1); break; - case BRW_OPCODE_SAD2: - fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n"); + case ELK_OPCODE_SAD2: + fprintf(stderr, "Opcode ELK_OPCODE_SAD2 unhandled\n"); break; - case BRW_OPCODE_SADA2: - fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n"); + case ELK_OPCODE_SADA2: + fprintf(stderr, "Opcode ELK_OPCODE_SADA2 unhandled\n"); break; - case BRW_OPCODE_SUBB: - brw_SUBB(p, dest, src0, src1); + case ELK_OPCODE_SUBB: + elk_SUBB(p, dest, src0, src1); break; - case BRW_OPCODE_ADD: - brw_ADD(p, dest, src0, src1); + case ELK_OPCODE_ADD: + elk_ADD(p, dest, src0, src1); break; - case BRW_OPCODE_CMP: + case ELK_OPCODE_CMP: /* Third parameter is conditional modifier * which gets updated later */ - brw_CMP(p, dest, 0, src0, src1); + elk_CMP(p, dest, 0, src0, src1); break; - case BRW_OPCODE_AND: - brw_AND(p, dest, src0, src1); + case ELK_OPCODE_AND: + elk_AND(p, dest, src0, src1); break; - case BRW_OPCODE_ASR: - brw_ASR(p, dest, src0, src1); + case ELK_OPCODE_ASR: + elk_ASR(p, dest, src0, src1); break; - case BRW_OPCODE_AVG: - brw_AVG(p, dest, src0, src1); + case ELK_OPCODE_AVG: + elk_AVG(p, dest, src0, src1); break; - case BRW_OPCODE_OR: - brw_OR(p, dest, src0, src1); + case ELK_OPCODE_OR: + elk_OR(p, dest, src0, src1); break; - case BRW_OPCODE_SEL: - brw_SEL(p, dest, src0, src1); + case ELK_OPCODE_SEL: + elk_SEL(p, dest, src0, src1); break; - case BRW_OPCODE_SHL: - brw_SHL(p, dest, src0, src1); + case ELK_OPCODE_SHL: + elk_SHL(p, dest, src0, src1); break; - case BRW_OPCODE_SHR: - brw_SHR(p, dest, src0, src1); + case ELK_OPCODE_SHR: + elk_SHR(p, dest, src0, src1); break; - case BRW_OPCODE_XOR: - brw_XOR(p, dest, src0, src1); + case ELK_OPCODE_XOR: + elk_XOR(p, dest, src0, src1); break; - case BRW_OPCODE_MUL: - brw_MUL(p, dest, src0, src1); + case ELK_OPCODE_MUL: + elk_MUL(p, dest, src0, src1); break; default: fprintf(stderr, "Unsupported binary opcode\n"); @@ -257,33 +257,33 @@ i965_asm_binary_instruction(int opcode, static void i965_asm_ternary_instruction(int opcode, - struct brw_codegen *p, - struct brw_reg dest, - struct brw_reg src0, - struct brw_reg src1, - struct brw_reg src2) + struct elk_codegen *p, + struct elk_reg dest, + struct elk_reg src0, + struct elk_reg src1, + struct elk_reg src2) { switch (opcode) { - case BRW_OPCODE_MAD: - brw_MAD(p, dest, src0, src1, src2); + case ELK_OPCODE_MAD: + elk_MAD(p, dest, src0, src1, src2); break; - case BRW_OPCODE_CSEL: - brw_CSEL(p, dest, src0, src1, src2); + case ELK_OPCODE_CSEL: + elk_CSEL(p, dest, src0, src1, src2); break; - case BRW_OPCODE_LRP: - brw_LRP(p, dest, src0, src1, src2); + case ELK_OPCODE_LRP: + elk_LRP(p, dest, src0, src1, src2); break; - case BRW_OPCODE_BFE: - brw_BFE(p, dest, src0, src1, src2); + case ELK_OPCODE_BFE: + elk_BFE(p, dest, src0, src1, src2); break; - case BRW_OPCODE_BFI2: - brw_BFI2(p, dest, src0, src1, src2); + case ELK_OPCODE_BFI2: + elk_BFI2(p, dest, src0, src1, src2); break; - case BRW_OPCODE_DP4A: - brw_DP4A(p, dest, src0, src1, src2); + case ELK_OPCODE_DP4A: + elk_DP4A(p, dest, src0, src1, src2); break; - case BRW_OPCODE_ADD3: - brw_ADD3(p, dest, src0, src1, src2); + case ELK_OPCODE_ADD3: + elk_ADD3(p, dest, src0, src1, src2); break; default: fprintf(stderr, "Unsupported ternary opcode\n"); @@ -291,48 +291,48 @@ i965_asm_ternary_instruction(int opcode, } static void -i965_asm_set_instruction_options(struct brw_codegen *p, +i965_asm_set_instruction_options(struct elk_codegen *p, struct options options) { - brw_inst_set_access_mode(p->devinfo, brw_last_inst, + elk_inst_set_access_mode(p->devinfo, elk_last_inst, options.access_mode); - brw_inst_set_mask_control(p->devinfo, brw_last_inst, + elk_inst_set_mask_control(p->devinfo, elk_last_inst, options.mask_control); if (p->devinfo->ver < 12) { - brw_inst_set_thread_control(p->devinfo, brw_last_inst, + elk_inst_set_thread_control(p->devinfo, elk_last_inst, options.thread_control); - brw_inst_set_no_dd_check(p->devinfo, brw_last_inst, + elk_inst_set_no_dd_check(p->devinfo, elk_last_inst, options.no_dd_check); - brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst, + elk_inst_set_no_dd_clear(p->devinfo, elk_last_inst, options.no_dd_clear); } else { - brw_inst_set_swsb(p->devinfo, brw_last_inst, + elk_inst_set_swsb(p->devinfo, elk_last_inst, tgl_swsb_encode(p->devinfo, options.depinfo)); } - brw_inst_set_debug_control(p->devinfo, brw_last_inst, + elk_inst_set_debug_control(p->devinfo, elk_last_inst, options.debug_control); if (p->devinfo->ver >= 6) - brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst, + elk_inst_set_acc_wr_control(p->devinfo, elk_last_inst, options.acc_wr_control); - brw_inst_set_cmpt_control(p->devinfo, brw_last_inst, + elk_inst_set_cmpt_control(p->devinfo, elk_last_inst, options.compaction); } static void -i965_asm_set_dst_nr(struct brw_codegen *p, - struct brw_reg *reg, +i965_asm_set_dst_nr(struct elk_codegen *p, + struct elk_reg *reg, struct options options) { if (p->devinfo->ver <= 6) { - if (reg->file == BRW_MESSAGE_REGISTER_FILE && - options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED && + if (reg->file == ELK_MESSAGE_REGISTER_FILE && + options.qtr_ctrl == ELK_COMPRESSION_COMPRESSED && !options.is_compr) - reg->nr |= BRW_MRF_COMPR4; + reg->nr |= ELK_MRF_COMPR4; } } static void -add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type type) +add_label(struct elk_codegen *p, const char* label_name, enum instr_label_type type) { if (!label_name) { return; @@ -358,16 +358,16 @@ add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type t double number; int integer; unsigned long long int llint; - struct brw_reg reg; - enum brw_reg_type reg_type; - struct brw_codegen *program; + struct elk_reg reg; + enum elk_reg_type reg_type; + struct elk_codegen *program; struct predicate predicate; struct condition condition; struct options options; struct instoption instoption; struct msgdesc msgdesc; struct tgl_swsb depinfo; - brw_inst *instruction; + elk_inst *instruction; } %token ABS @@ -591,41 +591,41 @@ add_instruction_option(struct options *options, struct instoption opt) } switch (opt.uint_value) { case ALIGN1: - options->access_mode = BRW_ALIGN_1; + options->access_mode = ELK_ALIGN_1; break; case ALIGN16: - options->access_mode = BRW_ALIGN_16; + options->access_mode = ELK_ALIGN_16; break; case SECHALF: - options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF; + options->qtr_ctrl |= ELK_COMPRESSION_2NDHALF; break; case COMPR: - options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED; + options->qtr_ctrl |= ELK_COMPRESSION_COMPRESSED; options->is_compr = true; break; case COMPR4: - options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED; + options->qtr_ctrl |= ELK_COMPRESSION_COMPRESSED; break; case SWITCH: - options->thread_control |= BRW_THREAD_SWITCH; + options->thread_control |= ELK_THREAD_SWITCH; break; case ATOMIC: - options->thread_control |= BRW_THREAD_ATOMIC; + options->thread_control |= ELK_THREAD_ATOMIC; break; case NODDCHK: options->no_dd_check = true; break; case NODDCLR: - options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED; + options->no_dd_clear = ELK_DEPENDENCY_NOTCLEARED; break; case MASK_DISABLE: - options->mask_control |= BRW_MASK_DISABLE; + options->mask_control |= ELK_MASK_DISABLE; break; case BREAKPOINT: - options->debug_control = BRW_DEBUG_BREAKPOINT; + options->debug_control = ELK_DEBUG_BREAKPOINT; break; case WECTRL: - options->mask_control |= BRW_WE_ALL; + options->mask_control |= ELK_WE_ALL; break; case CMPTCTRL: options->compaction = true; @@ -640,33 +640,33 @@ add_instruction_option(struct options *options, struct instoption opt) * code below */ case QTR_2Q: - options->qtr_ctrl = BRW_COMPRESSION_2NDHALF; + options->qtr_ctrl = ELK_COMPRESSION_2NDHALF; break; case QTR_3Q: - options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED; + options->qtr_ctrl = ELK_COMPRESSION_COMPRESSED; break; case QTR_4Q: options->qtr_ctrl = 3; break; case QTR_2H: - options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED; + options->qtr_ctrl = ELK_COMPRESSION_COMPRESSED; break; case QTR_2N: - options->qtr_ctrl = BRW_COMPRESSION_NONE; + options->qtr_ctrl = ELK_COMPRESSION_NONE; options->nib_ctrl = true; break; case QTR_3N: - options->qtr_ctrl = BRW_COMPRESSION_2NDHALF; + options->qtr_ctrl = ELK_COMPRESSION_2NDHALF; break; case QTR_4N: - options->qtr_ctrl = BRW_COMPRESSION_2NDHALF; + options->qtr_ctrl = ELK_COMPRESSION_2NDHALF; options->nib_ctrl = true; break; case QTR_5N: - options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED; + options->qtr_ctrl = ELK_COMPRESSION_COMPRESSED; break; case QTR_6N: - options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED; + options->qtr_ctrl = ELK_COMPRESSION_COMPRESSED; options->nib_ctrl = true; break; case QTR_7N: @@ -718,8 +718,8 @@ relocatableinstruction: illegalinstruction: ILLEGAL execsize instoptions { - brw_next_insn(p, $1); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2); + elk_next_insn(p, $1); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $2); i965_asm_set_instruction_options(p, $3); } ; @@ -729,35 +729,35 @@ unaryinstruction: predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions { i965_asm_set_dst_nr(p, &$6, $8); - brw_set_default_access_mode(p, $8.access_mode); + elk_set_default_access_mode(p, $8.access_mode); i965_asm_unary_instruction($2, p, $6, $7); - brw_pop_insn_state(p); + elk_pop_insn_state(p); i965_asm_set_instruction_options(p, $8); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, $4.cond_modifier); - if (p->devinfo->ver >= 7 && $2 != BRW_OPCODE_DIM && - !brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) { - brw_inst_set_flag_reg_nr(p->devinfo, - brw_last_inst, + if (p->devinfo->ver >= 7 && $2 != ELK_OPCODE_DIM && + !elk_inst_flag_reg_nr(p->devinfo, elk_last_inst)) { + elk_inst_set_flag_reg_nr(p->devinfo, + elk_last_inst, $4.flag_reg_nr); - brw_inst_set_flag_subreg_nr(p->devinfo, - brw_last_inst, + elk_inst_set_flag_subreg_nr(p->devinfo, + elk_last_inst, $4.flag_subreg_nr); } - if ($7.file != BRW_IMMEDIATE_VALUE) { - brw_inst_set_src0_vstride(p->devinfo, brw_last_inst, + if ($7.file != ELK_IMMEDIATE_VALUE) { + elk_inst_set_src0_vstride(p->devinfo, elk_last_inst, $7.vstride); } - brw_inst_set_saturate(p->devinfo, brw_last_inst, $3); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5); + elk_inst_set_saturate(p->devinfo, elk_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $5); // TODO: set instruction group instead of qtr and nib ctrl - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $8.qtr_ctrl); if (p->devinfo->ver >= 7) - brw_inst_set_nib_control(p->devinfo, brw_last_inst, + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $8.nib_ctrl); } ; @@ -785,31 +785,31 @@ binaryinstruction: predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions { i965_asm_set_dst_nr(p, &$6, $9); - brw_set_default_access_mode(p, $9.access_mode); + elk_set_default_access_mode(p, $9.access_mode); i965_asm_binary_instruction($2, p, $6, $7, $8); i965_asm_set_instruction_options(p, $9); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, $4.cond_modifier); if (p->devinfo->ver >= 7 && - !brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) { - brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst, + !elk_inst_flag_reg_nr(p->devinfo, elk_last_inst)) { + elk_inst_set_flag_reg_nr(p->devinfo, elk_last_inst, $4.flag_reg_nr); - brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst, + elk_inst_set_flag_subreg_nr(p->devinfo, elk_last_inst, $4.flag_subreg_nr); } - brw_inst_set_saturate(p->devinfo, brw_last_inst, $3); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5); + elk_inst_set_saturate(p->devinfo, elk_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $5); // TODO: set instruction group instead of qtr and nib ctrl - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $9.qtr_ctrl); if (p->devinfo->ver >= 7) - brw_inst_set_nib_control(p->devinfo, brw_last_inst, + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $9.nib_ctrl); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } ; @@ -837,31 +837,31 @@ binaryaccinstruction: predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions { i965_asm_set_dst_nr(p, &$6, $9); - brw_set_default_access_mode(p, $9.access_mode); + elk_set_default_access_mode(p, $9.access_mode); i965_asm_binary_instruction($2, p, $6, $7, $8); - brw_pop_insn_state(p); + elk_pop_insn_state(p); i965_asm_set_instruction_options(p, $9); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, $4.cond_modifier); if (p->devinfo->ver >= 7 && - !brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) { - brw_inst_set_flag_reg_nr(p->devinfo, - brw_last_inst, + !elk_inst_flag_reg_nr(p->devinfo, elk_last_inst)) { + elk_inst_set_flag_reg_nr(p->devinfo, + elk_last_inst, $4.flag_reg_nr); - brw_inst_set_flag_subreg_nr(p->devinfo, - brw_last_inst, + elk_inst_set_flag_subreg_nr(p->devinfo, + elk_last_inst, $4.flag_subreg_nr); } - brw_inst_set_saturate(p->devinfo, brw_last_inst, $3); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5); + elk_inst_set_saturate(p->devinfo, elk_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $5); // TODO: set instruction group instead of qtr and nib ctrl - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $9.qtr_ctrl); if (p->devinfo->ver >= 7) - brw_inst_set_nib_control(p->devinfo, brw_last_inst, + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $9.nib_ctrl); } ; @@ -884,20 +884,20 @@ binaryaccopcodes: mathinstruction: predicate MATH saturate math_function execsize dst src srcimm instoptions { - brw_set_default_access_mode(p, $9.access_mode); - gfx6_math(p, $6, $4, $7, $8); + elk_set_default_access_mode(p, $9.access_mode); + elk_gfx6_math(p, $6, $4, $7, $8); i965_asm_set_instruction_options(p, $9); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5); - brw_inst_set_saturate(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $5); + elk_inst_set_saturate(p->devinfo, elk_last_inst, $3); // TODO: set instruction group instead - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $9.qtr_ctrl); if (p->devinfo->ver >= 7) - brw_inst_set_nib_control(p->devinfo, brw_last_inst, + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $9.nib_ctrl); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } ; @@ -923,7 +923,7 @@ math_function: nopinstruction: NOP { - brw_NOP(p); + elk_NOP(p); } ; @@ -931,28 +931,28 @@ nopinstruction: ternaryinstruction: predicate ternaryopcodes saturate cond_mod execsize dst srcimm src srcimm instoptions { - brw_set_default_access_mode(p, $10.access_mode); + elk_set_default_access_mode(p, $10.access_mode); i965_asm_ternary_instruction($2, p, $6, $7, $8, $9); - brw_pop_insn_state(p); + elk_pop_insn_state(p); i965_asm_set_instruction_options(p, $10); - brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, + elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, $4.cond_modifier); if (p->devinfo->ver >= 7 && p->devinfo->ver < 12) { - brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst, + elk_inst_set_3src_a16_flag_reg_nr(p->devinfo, elk_last_inst, $4.flag_reg_nr); - brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst, + elk_inst_set_3src_a16_flag_subreg_nr(p->devinfo, elk_last_inst, $4.flag_subreg_nr); } - brw_inst_set_saturate(p->devinfo, brw_last_inst, $3); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5); + elk_inst_set_saturate(p->devinfo, elk_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $5); // TODO: set instruction group instead of qtr and nib ctrl - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $10.qtr_ctrl); if (p->devinfo->ver >= 7) - brw_inst_set_nib_control(p->devinfo, brw_last_inst, + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $10.nib_ctrl); } ; @@ -971,18 +971,18 @@ ternaryopcodes: waitinstruction: WAIT execsize dst instoptions { - brw_next_insn(p, $1); + elk_next_insn(p, $1); i965_asm_set_instruction_options(p, $4); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2); - brw_set_default_access_mode(p, $4.access_mode); - struct brw_reg dest = $3; - dest.swizzle = brw_swizzle_for_mask(dest.writemask); - if (dest.file != ARF || dest.nr != BRW_ARF_NOTIFICATION_COUNT) + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $2); + elk_set_default_access_mode(p, $4.access_mode); + struct elk_reg dest = $3; + dest.swizzle = elk_swizzle_for_mask(dest.writemask); + if (dest.file != ARF || dest.nr != ELK_ARF_NOTIFICATION_COUNT) error(&@1, "WAIT must use the notification register\n"); - brw_set_dest(p, brw_last_inst, dest); - brw_set_src0(p, brw_last_inst, dest); - brw_set_src1(p, brw_last_inst, brw_null_reg()); - brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE); + elk_set_dest(p, elk_last_inst, dest); + elk_set_src0(p, elk_last_inst, dest); + elk_set_src1(p, elk_last_inst, elk_null_reg()); + elk_inst_set_mask_control(p->devinfo, elk_last_inst, ELK_MASK_DISABLE); } ; @@ -991,108 +991,108 @@ sendinstruction: predicate sendopcode execsize dst payload exp2 sharedfunction msgdesc instoptions { i965_asm_set_instruction_options(p, $9); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, $4); - brw_set_src0(p, brw_last_inst, $5); - brw_inst_set_bits(brw_last_inst, 127, 96, $6); - brw_inst_set_src1_file_type(p->devinfo, brw_last_inst, - BRW_IMMEDIATE_VALUE, - BRW_REGISTER_TYPE_UD); - brw_inst_set_sfid(p->devinfo, brw_last_inst, $7); - brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); + elk_set_dest(p, elk_last_inst, $4); + elk_set_src0(p, elk_last_inst, $5); + elk_inst_set_bits(elk_last_inst, 127, 96, $6); + elk_inst_set_src1_file_type(p->devinfo, elk_last_inst, + ELK_IMMEDIATE_VALUE, + ELK_REGISTER_TYPE_UD); + elk_inst_set_sfid(p->devinfo, elk_last_inst, $7); + elk_inst_set_eot(p->devinfo, elk_last_inst, $9.end_of_thread); // TODO: set instruction group instead of qtr and nib ctrl - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $9.qtr_ctrl); if (p->devinfo->ver >= 7) - brw_inst_set_nib_control(p->devinfo, brw_last_inst, + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $9.nib_ctrl); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate sendopcode execsize exp dst payload exp2 sharedfunction msgdesc instoptions { assert(p->devinfo->ver < 6); i965_asm_set_instruction_options(p, $10); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4); - brw_set_dest(p, brw_last_inst, $5); - brw_set_src0(p, brw_last_inst, $6); - brw_inst_set_bits(brw_last_inst, 127, 96, $7); - brw_inst_set_src1_file_type(p->devinfo, brw_last_inst, - BRW_IMMEDIATE_VALUE, - BRW_REGISTER_TYPE_UD); - brw_inst_set_sfid(p->devinfo, brw_last_inst, $8); - brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); + elk_inst_set_base_mrf(p->devinfo, elk_last_inst, $4); + elk_set_dest(p, elk_last_inst, $5); + elk_set_src0(p, elk_last_inst, $6); + elk_inst_set_bits(elk_last_inst, 127, 96, $7); + elk_inst_set_src1_file_type(p->devinfo, elk_last_inst, + ELK_IMMEDIATE_VALUE, + ELK_REGISTER_TYPE_UD); + elk_inst_set_sfid(p->devinfo, elk_last_inst, $8); + elk_inst_set_eot(p->devinfo, elk_last_inst, $10.end_of_thread); // TODO: set instruction group instead of qtr and nib ctrl - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $10.qtr_ctrl); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate sendopcode execsize dst payload payload exp2 sharedfunction msgdesc instoptions { assert(p->devinfo->ver >= 6 && p->devinfo->ver < 12); i965_asm_set_instruction_options(p, $10); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, $4); - brw_set_src0(p, brw_last_inst, $5); - brw_inst_set_bits(brw_last_inst, 127, 96, $7); - brw_inst_set_sfid(p->devinfo, brw_last_inst, $8); - brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); + elk_set_dest(p, elk_last_inst, $4); + elk_set_src0(p, elk_last_inst, $5); + elk_inst_set_bits(elk_last_inst, 127, 96, $7); + elk_inst_set_sfid(p->devinfo, elk_last_inst, $8); + elk_inst_set_eot(p->devinfo, elk_last_inst, $10.end_of_thread); // TODO: set instruction group instead of qtr and nib ctrl - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $10.qtr_ctrl); if (p->devinfo->ver >= 7) - brw_inst_set_nib_control(p->devinfo, brw_last_inst, + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $10.nib_ctrl); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate sendsopcode execsize dst payload payload desc ex_desc sharedfunction msgdesc instoptions { assert(p->devinfo->ver >= 9); i965_asm_set_instruction_options(p, $11); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, $4); - brw_set_src0(p, brw_last_inst, $5); - brw_set_src1(p, brw_last_inst, $6); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); + elk_set_dest(p, elk_last_inst, $4); + elk_set_src0(p, elk_last_inst, $5); + elk_set_src1(p, elk_last_inst, $6); - if ($7.file == BRW_IMMEDIATE_VALUE) { - brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 0); - brw_inst_set_send_desc(p->devinfo, brw_last_inst, $7.ud); + if ($7.file == ELK_IMMEDIATE_VALUE) { + elk_inst_set_send_sel_reg32_desc(p->devinfo, elk_last_inst, 0); + elk_inst_set_send_desc(p->devinfo, elk_last_inst, $7.ud); } else { - brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1); + elk_inst_set_send_sel_reg32_desc(p->devinfo, elk_last_inst, 1); } - if ($8.file == BRW_IMMEDIATE_VALUE) { - brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 0); - brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8.ud); + if ($8.file == ELK_IMMEDIATE_VALUE) { + elk_inst_set_send_sel_reg32_ex_desc(p->devinfo, elk_last_inst, 0); + elk_inst_set_sends_ex_desc(p->devinfo, elk_last_inst, $8.ud); } else { - brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 1); - brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $8.subnr >> 2); + elk_inst_set_send_sel_reg32_ex_desc(p->devinfo, elk_last_inst, 1); + elk_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, elk_last_inst, $8.subnr >> 2); } - brw_inst_set_sfid(p->devinfo, brw_last_inst, $9); - brw_inst_set_eot(p->devinfo, brw_last_inst, $11.end_of_thread); + elk_inst_set_sfid(p->devinfo, elk_last_inst, $9); + elk_inst_set_eot(p->devinfo, elk_last_inst, $11.end_of_thread); // TODO: set instruction group instead of qtr and nib ctrl - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $11.qtr_ctrl); - brw_inst_set_nib_control(p->devinfo, brw_last_inst, + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $11.nib_ctrl); if (p->devinfo->verx10 >= 125 && $10.ex_bso) { - brw_inst_set_send_ex_bso(p->devinfo, brw_last_inst, 1); - brw_inst_set_send_src1_len(p->devinfo, brw_last_inst, + elk_inst_set_send_ex_bso(p->devinfo, elk_last_inst, 1); + elk_inst_set_send_src1_len(p->devinfo, elk_last_inst, $10.src1_len); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } ; @@ -1109,29 +1109,29 @@ sendsop: ; sendopcode: - sendop { $$ = brw_next_insn(p, $1); } + sendop { $$ = elk_next_insn(p, $1); } ; sendsopcode: - sendsop { $$ = brw_next_insn(p, $1); } + sendsop { $$ = elk_next_insn(p, $1); } ; sharedfunction: - NULL_TOKEN { $$ = BRW_SFID_NULL; } - | MATH { $$ = BRW_SFID_MATH; } - | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; } - | READ { $$ = BRW_SFID_DATAPORT_READ; } - | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; } - | URB { $$ = BRW_SFID_URB; } - | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; } - | VME { $$ = BRW_SFID_VME; } + NULL_TOKEN { $$ = ELK_SFID_NULL; } + | MATH { $$ = ELK_SFID_MATH; } + | GATEWAY { $$ = ELK_SFID_MESSAGE_GATEWAY; } + | READ { $$ = ELK_SFID_DATAPORT_READ; } + | WRITE { $$ = ELK_SFID_DATAPORT_WRITE; } + | URB { $$ = ELK_SFID_URB; } + | THREAD_SPAWNER { $$ = ELK_SFID_THREAD_SPAWNER; } + | VME { $$ = ELK_SFID_VME; } | RENDER { $$ = GFX6_SFID_DATAPORT_RENDER_CACHE; } | CONST { $$ = GFX6_SFID_DATAPORT_CONSTANT_CACHE; } | DATA { $$ = GFX7_SFID_DATAPORT_DATA_CACHE; } | PIXEL_INTERP { $$ = GFX7_SFID_PIXEL_INTERPOLATOR; } | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; } | CRE { $$ = HSW_SFID_CRE; } - | SAMPLER { $$ = BRW_SFID_SAMPLER; } + | SAMPLER { $$ = ELK_SFID_SAMPLER; } | DP_SAMPLER { $$ = GFX6_SFID_DATAPORT_SAMPLER_CACHE; } | SLM { $$ = GFX12_SFID_SLM; } | TGM { $$ = GFX12_SFID_TGM; } @@ -1147,7 +1147,7 @@ desc: reg32a | exp2 { - $$ = brw_imm_ud($1); + $$ = elk_imm_ud($1); } ; @@ -1155,7 +1155,7 @@ ex_desc: reg32a | exp2 { - $$ = brw_imm_ud($1); + $$ = elk_imm_ud($1); } ; @@ -1172,16 +1172,16 @@ reg32a: jumpinstruction: predicate JMPI execsize relativelocation2 instoptions { - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); - brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_set_src1(p, brw_last_inst, $4); - brw_inst_set_pred_control(p->devinfo, brw_last_inst, - brw_inst_pred_control(p->devinfo, - brw_last_inst)); - brw_pop_insn_state(p); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); + elk_set_dest(p, elk_last_inst, elk_ip_reg()); + elk_set_src0(p, elk_last_inst, elk_ip_reg()); + elk_set_src1(p, elk_last_inst, $4); + elk_inst_set_pred_control(p->devinfo, elk_last_inst, + elk_inst_pred_control(p->devinfo, + elk_last_inst)); + elk_pop_insn_state(p); } ; @@ -1191,192 +1191,192 @@ branchinstruction: { add_label(p, $4, INSTR_LABEL_JIP); - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); if (p->devinfo->ver == 6) { - brw_set_dest(p, brw_last_inst, brw_imm_w(0x0)); - brw_set_src0(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); + elk_set_dest(p, elk_last_inst, elk_imm_w(0x0)); + elk_set_src0(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); } else if (p->devinfo->ver == 7) { - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src0(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, brw_imm_w(0x0)); + elk_set_dest(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src0(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, elk_imm_w(0x0)); } else { - brw_set_src0(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, elk_imm_d(0x0)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate ENDIF execsize relativelocation instoptions { - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src0(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $4); + elk_set_dest(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src0(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); + elk_inst_set_gfx4_pop_count(p->devinfo, elk_last_inst, $4); - brw_inst_set_thread_control(p->devinfo, brw_last_inst, - BRW_THREAD_SWITCH); + elk_inst_set_thread_control(p->devinfo, elk_last_inst, + ELK_THREAD_SWITCH); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | ELSE execsize JUMP_LABEL jumplabel instoptions { add_label(p, $3, INSTR_LABEL_JIP); add_label(p, $4, INSTR_LABEL_UIP); - brw_next_insn(p, $1); + elk_next_insn(p, $1); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $2); if (p->devinfo->ver == 6) { - brw_set_dest(p, brw_last_inst, brw_imm_w(0x0)); - brw_set_src0(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); + elk_set_dest(p, elk_last_inst, elk_imm_w(0x0)); + elk_set_src0(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); } else if (p->devinfo->ver == 7) { - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src0(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, brw_imm_w(0)); + elk_set_dest(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src0(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, elk_imm_w(0)); } else { - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); + elk_set_dest(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); if (p->devinfo->ver < 12) - brw_set_src0(p, brw_last_inst, brw_imm_d(0)); + elk_set_src0(p, elk_last_inst, elk_imm_d(0)); } } | ELSE execsize relativelocation rellocation instoptions { - brw_next_insn(p, $1); + elk_next_insn(p, $1); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $2); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); - brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $3); - brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $4); + elk_set_dest(p, elk_last_inst, elk_ip_reg()); + elk_set_src0(p, elk_last_inst, elk_ip_reg()); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); + elk_inst_set_gfx4_jump_count(p->devinfo, elk_last_inst, $3); + elk_inst_set_gfx4_pop_count(p->devinfo, elk_last_inst, $4); if (!p->single_program_flow) - brw_inst_set_thread_control(p->devinfo, brw_last_inst, - BRW_THREAD_SWITCH); + elk_inst_set_thread_control(p->devinfo, elk_last_inst, + ELK_THREAD_SWITCH); } | predicate IF execsize JUMP_LABEL jumplabel instoptions { add_label(p, $4, INSTR_LABEL_JIP); add_label(p, $5, INSTR_LABEL_UIP); - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $6); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); if (p->devinfo->ver == 6) { - brw_set_dest(p, brw_last_inst, brw_imm_w(0x0)); - brw_set_src0(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); - brw_set_src1(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); + elk_set_dest(p, elk_last_inst, elk_imm_w(0x0)); + elk_set_src0(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); + elk_set_src1(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); } else if (p->devinfo->ver == 7) { - brw_set_dest(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); - brw_set_src0(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); - brw_set_src1(p, brw_last_inst, brw_imm_w(0x0)); + elk_set_dest(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); + elk_set_src0(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); + elk_set_src1(p, elk_last_inst, elk_imm_w(0x0)); } else { - brw_set_dest(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); + elk_set_dest(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); if (p->devinfo->ver < 12) - brw_set_src0(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, elk_imm_d(0x0)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate IF execsize relativelocation rellocation instoptions { - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $6); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); - brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); - brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5); + elk_set_dest(p, elk_last_inst, elk_ip_reg()); + elk_set_src0(p, elk_last_inst, elk_ip_reg()); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); + elk_inst_set_gfx4_jump_count(p->devinfo, elk_last_inst, $4); + elk_inst_set_gfx4_pop_count(p->devinfo, elk_last_inst, $5); if (!p->single_program_flow) - brw_inst_set_thread_control(p->devinfo, brw_last_inst, - BRW_THREAD_SWITCH); + elk_inst_set_thread_control(p->devinfo, elk_last_inst, + ELK_THREAD_SWITCH); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate IFF execsize JUMP_LABEL instoptions { add_label(p, $4, INSTR_LABEL_JIP); - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); if (p->devinfo->ver == 6) { - brw_set_src0(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); - brw_set_src1(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); + elk_set_src0(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); + elk_set_src1(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); } else if (p->devinfo->ver == 7) { - brw_set_dest(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); - brw_set_src0(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); - brw_set_src1(p, brw_last_inst, brw_imm_w(0x0)); + elk_set_dest(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); + elk_set_src0(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); + elk_set_src1(p, elk_last_inst, elk_imm_w(0x0)); } else { - brw_set_dest(p, brw_last_inst, - vec1(retype(brw_null_reg(), - BRW_REGISTER_TYPE_D))); + elk_set_dest(p, elk_last_inst, + vec1(retype(elk_null_reg(), + ELK_REGISTER_TYPE_D))); if (p->devinfo->ver < 12) - brw_set_src0(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, elk_imm_d(0x0)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate IFF execsize relativelocation instoptions { - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); - brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); - brw_set_src1(p, brw_last_inst, brw_imm_d($4)); + elk_set_dest(p, elk_last_inst, elk_ip_reg()); + elk_set_src0(p, elk_last_inst, elk_ip_reg()); + elk_inst_set_gfx4_jump_count(p->devinfo, elk_last_inst, $4); + elk_set_src1(p, elk_last_inst, elk_imm_d($4)); if (!p->single_program_flow) - brw_inst_set_thread_control(p->devinfo, brw_last_inst, - BRW_THREAD_SWITCH); + elk_inst_set_thread_control(p->devinfo, elk_last_inst, + ELK_THREAD_SWITCH); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } ; @@ -1387,93 +1387,93 @@ breakinstruction: add_label(p, $4, INSTR_LABEL_JIP); add_label(p, $5, INSTR_LABEL_UIP); - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $6); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); if (p->devinfo->ver >= 8) { - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src0(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_dest(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src0(p, elk_last_inst, elk_imm_d(0x0)); } else { - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src0(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_dest(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src0(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate BREAK execsize relativelocation relativelocation instoptions { - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $6); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); - brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); - brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5); + elk_set_dest(p, elk_last_inst, elk_ip_reg()); + elk_set_src0(p, elk_last_inst, elk_ip_reg()); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); + elk_inst_set_gfx4_jump_count(p->devinfo, elk_last_inst, $4); + elk_inst_set_gfx4_pop_count(p->devinfo, elk_last_inst, $5); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate HALT execsize JUMP_LABEL JUMP_LABEL instoptions { add_label(p, $4, INSTR_LABEL_JIP); add_label(p, $5, INSTR_LABEL_UIP); - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $6); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); - brw_set_dest(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); + elk_set_dest(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); if (p->devinfo->ver < 8) { - brw_set_src0(p, brw_last_inst, retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); } else if (p->devinfo->ver < 12) { - brw_set_src0(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, elk_imm_d(0x0)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate CONT execsize JUMP_LABEL JUMP_LABEL instoptions { add_label(p, $4, INSTR_LABEL_JIP); add_label(p, $5, INSTR_LABEL_UIP); - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $6); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); + elk_set_dest(p, elk_last_inst, elk_ip_reg()); if (p->devinfo->ver >= 8) { - brw_set_src0(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, elk_imm_d(0x0)); } else { - brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, elk_ip_reg()); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate CONT execsize relativelocation relativelocation instoptions { - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $6); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); + elk_set_dest(p, elk_last_inst, elk_ip_reg()); - brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, elk_ip_reg()); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); - brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); - brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5); + elk_inst_set_gfx4_jump_count(p->devinfo, elk_last_inst, $4); + elk_inst_set_gfx4_pop_count(p->devinfo, elk_last_inst, $5); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } ; @@ -1483,62 +1483,62 @@ loopinstruction: { add_label(p, $4, INSTR_LABEL_JIP); - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); if (p->devinfo->ver >= 8) { - brw_set_dest(p, brw_last_inst, - retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); + elk_set_dest(p, elk_last_inst, + retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); if (p->devinfo->ver < 12) - brw_set_src0(p, brw_last_inst, brw_imm_d(0x0)); + elk_set_src0(p, elk_last_inst, elk_imm_d(0x0)); } else if (p->devinfo->ver == 7) { - brw_set_dest(p, brw_last_inst, - retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src0(p, brw_last_inst, - retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, - brw_imm_w(0x0)); + elk_set_dest(p, elk_last_inst, + retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src0(p, elk_last_inst, + retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, + elk_imm_w(0x0)); } else { - brw_set_dest(p, brw_last_inst, brw_imm_w(0x0)); - brw_set_src0(p, brw_last_inst, - retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); - brw_set_src1(p, brw_last_inst, - retype(brw_null_reg(), - BRW_REGISTER_TYPE_D)); + elk_set_dest(p, elk_last_inst, elk_imm_w(0x0)); + elk_set_src0(p, elk_last_inst, + retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); + elk_set_src1(p, elk_last_inst, + retype(elk_null_reg(), + ELK_REGISTER_TYPE_D)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | predicate WHILE execsize relativelocation instoptions { - brw_next_insn(p, $2); + elk_next_insn(p, $2); i965_asm_set_instruction_options(p, $5); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $3); - brw_set_dest(p, brw_last_inst, brw_ip_reg()); - brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); - brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, 0); + elk_set_dest(p, elk_last_inst, elk_ip_reg()); + elk_set_src0(p, elk_last_inst, elk_ip_reg()); + elk_set_src1(p, elk_last_inst, elk_imm_d(0x0)); + elk_inst_set_gfx4_jump_count(p->devinfo, elk_last_inst, $4); + elk_inst_set_gfx4_pop_count(p->devinfo, elk_last_inst, 0); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } | DO execsize instoptions { - brw_next_insn(p, $1); + elk_next_insn(p, $1); if (p->devinfo->ver < 6) { - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $2); i965_asm_set_instruction_options(p, $3); - brw_set_dest(p, brw_last_inst, brw_null_reg()); - brw_set_src0(p, brw_last_inst, brw_null_reg()); - brw_set_src1(p, brw_last_inst, brw_null_reg()); + elk_set_dest(p, elk_last_inst, elk_null_reg()); + elk_set_src0(p, elk_last_inst, elk_null_reg()); + elk_set_src1(p, elk_last_inst, elk_null_reg()); - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE); + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, ELK_COMPRESSION_NONE); } } ; @@ -1551,22 +1551,22 @@ syncinstruction: error(&@2, "sync instruction is supported only on gfx12+\n"); } - if ($5.file == BRW_IMMEDIATE_VALUE && + if ($5.file == ELK_IMMEDIATE_VALUE && $3 != TGL_SYNC_ALLRD && $3 != TGL_SYNC_ALLWR) { error(&@2, "Only allrd and allwr support immediate argument\n"); } - brw_set_default_access_mode(p, $6.access_mode); - brw_SYNC(p, $3); + elk_set_default_access_mode(p, $6.access_mode); + elk_SYNC(p, $3); i965_asm_set_instruction_options(p, $6); - brw_inst_set_exec_size(p->devinfo, brw_last_inst, $4); - brw_set_src0(p, brw_last_inst, $5); - brw_inst_set_eot(p->devinfo, brw_last_inst, $6.end_of_thread); - brw_inst_set_qtr_control(p->devinfo, brw_last_inst, $6.qtr_ctrl); - brw_inst_set_nib_control(p->devinfo, brw_last_inst, $6.nib_ctrl); + elk_inst_set_exec_size(p->devinfo, elk_last_inst, $4); + elk_set_src0(p, elk_last_inst, $5); + elk_inst_set_eot(p->devinfo, elk_last_inst, $6.end_of_thread); + elk_inst_set_qtr_control(p->devinfo, elk_last_inst, $6.qtr_ctrl); + elk_inst_set_nib_control(p->devinfo, elk_last_inst, $6.nib_ctrl); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } ; @@ -1643,13 +1643,13 @@ dstoperand: dstreg dstregion writemask reg_type { $$ = $1; - $$.vstride = BRW_VERTICAL_STRIDE_1; - $$.width = BRW_WIDTH_1; + $$.vstride = ELK_VERTICAL_STRIDE_1; + $$.width = ELK_WIDTH_1; $$.hstride = $2; $$.type = $4; $$.writemask = $3; - $$.swizzle = BRW_SWIZZLE_NOOP; - $$.subnr = $$.subnr * brw_reg_type_to_size($4); + $$.swizzle = ELK_SWIZZLE_NOOP; + $$.subnr = $$.subnr * elk_reg_type_to_size($4); } ; @@ -1660,7 +1660,7 @@ dstoperandex: $$.hstride = $2; $$.type = $4; $$.writemask = $3; - $$.subnr = $$.subnr * brw_reg_type_to_size($4); + $$.subnr = $$.subnr * elk_reg_type_to_size($4); } /* BSpec says "When the conditional modifier is present, updates * to the selected flag register also occur. In this case, the @@ -1669,8 +1669,8 @@ dstoperandex: | nullreg dstregion writemask reg_type { $$ = $1; - $$.vstride = BRW_VERTICAL_STRIDE_1; - $$.width = BRW_WIDTH_1; + $$.vstride = ELK_VERTICAL_STRIDE_1; + $$.width = ELK_WIDTH_1; $$.hstride = $2; $$.writemask = $3; $$.type = $4; @@ -1679,7 +1679,7 @@ dstoperandex: { $$ = $1; $$.hstride = 1; - $$.type = BRW_REGISTER_TYPE_UW; + $$.type = ELK_REGISTER_TYPE_UW; } ; @@ -1700,22 +1700,22 @@ dstreg: directgenreg { $$ = $1; - $$.address_mode = BRW_ADDRESS_DIRECT; + $$.address_mode = ELK_ADDRESS_DIRECT; } | indirectgenreg { $$ = $1; - $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.address_mode = ELK_ADDRESS_REGISTER_INDIRECT_REGISTER; } | directmsgreg { $$ = $1; - $$.address_mode = BRW_ADDRESS_DIRECT; + $$.address_mode = ELK_ADDRESS_DIRECT; } | indirectmsgreg { $$ = $1; - $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.address_mode = ELK_ADDRESS_REGISTER_INDIRECT_REGISTER; } ; @@ -1729,49 +1729,49 @@ immreg: immval imm_type { switch ($2) { - case BRW_REGISTER_TYPE_UD: - $$ = brw_imm_ud($1); + case ELK_REGISTER_TYPE_UD: + $$ = elk_imm_ud($1); break; - case BRW_REGISTER_TYPE_D: - $$ = brw_imm_d($1); + case ELK_REGISTER_TYPE_D: + $$ = elk_imm_d($1); break; - case BRW_REGISTER_TYPE_UW: - $$ = brw_imm_uw($1 | ($1 << 16)); + case ELK_REGISTER_TYPE_UW: + $$ = elk_imm_uw($1 | ($1 << 16)); break; - case BRW_REGISTER_TYPE_W: - $$ = brw_imm_w($1); + case ELK_REGISTER_TYPE_W: + $$ = elk_imm_w($1); break; - case BRW_REGISTER_TYPE_F: - $$ = brw_imm_reg(BRW_REGISTER_TYPE_F); + case ELK_REGISTER_TYPE_F: + $$ = elk_imm_reg(ELK_REGISTER_TYPE_F); /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */ $$.u64 = $1; break; - case BRW_REGISTER_TYPE_V: - $$ = brw_imm_v($1); + case ELK_REGISTER_TYPE_V: + $$ = elk_imm_v($1); break; - case BRW_REGISTER_TYPE_UV: - $$ = brw_imm_uv($1); + case ELK_REGISTER_TYPE_UV: + $$ = elk_imm_uv($1); break; - case BRW_REGISTER_TYPE_VF: - $$ = brw_imm_vf($1); + case ELK_REGISTER_TYPE_VF: + $$ = elk_imm_vf($1); break; - case BRW_REGISTER_TYPE_Q: - $$ = brw_imm_q($1); + case ELK_REGISTER_TYPE_Q: + $$ = elk_imm_q($1); break; - case BRW_REGISTER_TYPE_UQ: - $$ = brw_imm_uq($1); + case ELK_REGISTER_TYPE_UQ: + $$ = elk_imm_uq($1); break; - case BRW_REGISTER_TYPE_DF: - $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF); + case ELK_REGISTER_TYPE_DF: + $$ = elk_imm_reg(ELK_REGISTER_TYPE_DF); $$.d64 = $1; break; - case BRW_REGISTER_TYPE_HF: - $$ = brw_imm_reg(BRW_REGISTER_TYPE_HF); + case ELK_REGISTER_TYPE_HF: + $$ = elk_imm_reg(ELK_REGISTER_TYPE_HF); $$.ud = $1 | ($1 << 16); break; default: error(&@2, "Unknown immediate type %s\n", - brw_reg_type_to_letters($2)); + elk_reg_type_to_letters($2)); } } ; @@ -1820,7 +1820,7 @@ directsrcaccoperand: srcarcoperandex: srcarcoperandex_typed region reg_type { - $$ = brw_reg($1.file, + $$ = elk_reg($1.file, $1.nr, $1.subnr, 0, @@ -1829,7 +1829,7 @@ srcarcoperandex: $2.vstride, $2.width, $2.hstride, - BRW_SWIZZLE_NOOP, + ELK_SWIZZLE_NOOP, WRITEMASK_XYZW); } | nullreg region reg_type @@ -1841,7 +1841,7 @@ srcarcoperandex: } | threadcontrolreg { - $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW); + $$ = set_direct_src_operand(&$1, ELK_REGISTER_TYPE_UW); } ; @@ -1857,7 +1857,7 @@ srcarcoperandex_typed: indirectsrcoperand: negate abs indirectgenreg indirectregion swizzle reg_type { - $$ = brw_reg($3.file, + $$ = elk_reg($3.file, 0, $3.subnr, $1, // negate @@ -1869,8 +1869,8 @@ indirectsrcoperand: $5, WRITEMASK_X); - $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; - // brw_reg set indirect_offset to 0 so set it to valid value + $$.address_mode = ELK_ADDRESS_REGISTER_INDIRECT_REGISTER; + // elk_reg set indirect_offset to 0 so set it to valid value $$.indirect_offset = $3.indirect_offset; } ; @@ -1886,7 +1886,7 @@ directgenreg_list: directsrcoperand: negate abs directgenreg_list region swizzle reg_type { - $$ = brw_reg($3.file, + $$ = elk_reg($3.file, $3.nr, $3.subnr, $1, @@ -1927,7 +1927,7 @@ directgenreg: GENREG subregnum { memset(&$$, '\0', sizeof($$)); - $$.file = BRW_GENERAL_REGISTER_FILE; + $$.file = ELK_GENERAL_REGISTER_FILE; $$.nr = $1; $$.subnr = $2; } @@ -1937,7 +1937,7 @@ indirectgenreg: GENREGFILE LSQUARE addrparam RSQUARE { memset(&$$, '\0', sizeof($$)); - $$.file = BRW_GENERAL_REGISTER_FILE; + $$.file = ELK_GENERAL_REGISTER_FILE; $$.subnr = $3.subnr; $$.indirect_offset = $3.indirect_offset; } @@ -1946,7 +1946,7 @@ indirectgenreg: directmsgreg: MSGREG subregnum { - $$.file = BRW_MESSAGE_REGISTER_FILE; + $$.file = ELK_MESSAGE_REGISTER_FILE; $$.nr = $1; $$.subnr = $2; } @@ -1956,7 +1956,7 @@ indirectmsgreg: MSGREGFILE LSQUARE addrparam RSQUARE { memset(&$$, '\0', sizeof($$)); - $$.file = BRW_MESSAGE_REGISTER_FILE; + $$.file = ELK_MESSAGE_REGISTER_FILE; $$.subnr = $3.subnr; $$.indirect_offset = $3.indirect_offset; } @@ -1971,8 +1971,8 @@ addrreg: error(&@2, "Address sub register number %d" "out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_ADDRESS; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_ADDRESS; $$.subnr = $2; } ; @@ -1991,8 +1991,8 @@ accreg: " out of range\n", $1); memset(&$$, '\0', sizeof($$)); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_ACCUMULATOR; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_ACCUMULATOR; $$.subnr = $2; } ; @@ -2011,8 +2011,8 @@ flagreg: error(&@2, "Flag subregister number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_FLAG | $1; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_FLAG | $1; $$.subnr = $2; } ; @@ -2024,8 +2024,8 @@ maskreg: error(&@1, "Mask register number %d" " out of range\n", $1); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_MASK; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_MASK; $$.subnr = $2; } ; @@ -2038,8 +2038,8 @@ notifyreg: error(&@2, "Notification sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_NOTIFICATION_COUNT; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_NOTIFICATION_COUNT; $$.subnr = $2; } ; @@ -2055,8 +2055,8 @@ statereg: error(&@2, "State sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_STATE; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_STATE; $$.subnr = $2; } ; @@ -2068,18 +2068,18 @@ controlreg: error(&@2, "control sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_CONTROL; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_CONTROL; $$.subnr = $2; } ; ipreg: - IPREG { $$ = brw_ip_reg(); } + IPREG { $$ = elk_ip_reg(); } ; nullreg: - NULL_TOKEN { $$ = brw_null_reg(); } + NULL_TOKEN { $$ = elk_null_reg(); } ; threadcontrolreg: @@ -2089,8 +2089,8 @@ threadcontrolreg: error(&@2, "Thread control sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_TDR; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_TDR; $$.subnr = $2; } ; @@ -2110,8 +2110,8 @@ performancereg: error(&@2, "Performance sub register number %d" " out of range\n", $2); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_TIMESTAMP; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_TIMESTAMP; $$.subnr = $2; } ; @@ -2123,8 +2123,8 @@ channelenablereg: error(&@1, "Channel enable register number %d" " out of range\n", $1); - $$.file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.nr = BRW_ARF_MASK; + $$.file = ELK_ARCHITECTURE_REGISTER_FILE; + $$.nr = ELK_ARF_MASK; $$.subnr = $2; } ; @@ -2145,7 +2145,7 @@ immval: dstregion: /* empty */ { - $$ = BRW_HORIZONTAL_STRIDE_1; + $$ = ELK_HORIZONTAL_STRIDE_1; } | LANGLE exp RANGLE { @@ -2211,7 +2211,7 @@ region: error(&@6, "Invalid Horizontal stride in" " region_wh %d\n", $6); - $$ = brw_VxH_indirect(0, 0); + $$ = elk_VxH_indirect(0, 0); } ; @@ -2226,30 +2226,30 @@ region_wh: " region_wh %d\n", $4); $$ = stride($$, 0, $2, $4); - $$.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL; + $$.vstride = ELK_VERTICAL_STRIDE_ONE_DIMENSIONAL; } ; reg_type: - TYPE_F { $$ = BRW_REGISTER_TYPE_F; } - | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; } - | TYPE_D { $$ = BRW_REGISTER_TYPE_D; } - | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; } - | TYPE_W { $$ = BRW_REGISTER_TYPE_W; } - | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; } - | TYPE_B { $$ = BRW_REGISTER_TYPE_B; } - | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; } - | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; } - | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; } - | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; } - | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; } + TYPE_F { $$ = ELK_REGISTER_TYPE_F; } + | TYPE_UD { $$ = ELK_REGISTER_TYPE_UD; } + | TYPE_D { $$ = ELK_REGISTER_TYPE_D; } + | TYPE_UW { $$ = ELK_REGISTER_TYPE_UW; } + | TYPE_W { $$ = ELK_REGISTER_TYPE_W; } + | TYPE_UB { $$ = ELK_REGISTER_TYPE_UB; } + | TYPE_B { $$ = ELK_REGISTER_TYPE_B; } + | TYPE_DF { $$ = ELK_REGISTER_TYPE_DF; } + | TYPE_UQ { $$ = ELK_REGISTER_TYPE_UQ; } + | TYPE_Q { $$ = ELK_REGISTER_TYPE_Q; } + | TYPE_HF { $$ = ELK_REGISTER_TYPE_HF; } + | TYPE_NF { $$ = ELK_REGISTER_TYPE_NF; } ; imm_type: reg_type { $$ = $1; } - | TYPE_V { $$ = BRW_REGISTER_TYPE_V; } - | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; } - | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; } + | TYPE_V { $$ = ELK_REGISTER_TYPE_V; } + | TYPE_VF { $$ = ELK_REGISTER_TYPE_VF; } + | TYPE_UV { $$ = ELK_REGISTER_TYPE_UV; } ; writemask: @@ -2265,36 +2265,36 @@ writemask: writemask_x: /* empty */ { $$ = 0; } - | X { $$ = 1 << BRW_CHANNEL_X; } + | X { $$ = 1 << ELK_CHANNEL_X; } ; writemask_y: /* empty */ { $$ = 0; } - | Y { $$ = 1 << BRW_CHANNEL_Y; } + | Y { $$ = 1 << ELK_CHANNEL_Y; } ; writemask_z: /* empty */ { $$ = 0; } - | Z { $$ = 1 << BRW_CHANNEL_Z; } + | Z { $$ = 1 << ELK_CHANNEL_Z; } ; writemask_w: /* empty */ { $$ = 0; } - | W { $$ = 1 << BRW_CHANNEL_W; } + | W { $$ = 1 << ELK_CHANNEL_W; } ; swizzle: /* empty */ { - $$ = BRW_SWIZZLE_NOOP; + $$ = ELK_SWIZZLE_NOOP; } | DOT chansel { - $$ = BRW_SWIZZLE4($2, $2, $2, $2); + $$ = ELK_SWIZZLE4($2, $2, $2, $2); } | DOT chansel chansel chansel chansel { - $$ = BRW_SWIZZLE4($2, $3, $4, $5); + $$ = ELK_SWIZZLE4($2, $3, $4, $5); } ; @@ -2309,17 +2309,17 @@ chansel: predicate: /* empty */ { - brw_push_insn_state(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_set_default_predicate_inverse(p, false); + elk_push_insn_state(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_set_default_predicate_inverse(p, false); } | LPAREN predstate flagreg predctrl RPAREN { - brw_push_insn_state(p); - brw_set_default_predicate_inverse(p, $2); - brw_set_default_flag_reg(p, $3.nr, $3.subnr); - brw_set_default_predicate_control(p, $4); + elk_push_insn_state(p); + elk_set_default_predicate_inverse(p, $2); + elk_set_default_flag_reg(p, $3.nr, $3.subnr); + elk_set_default_predicate_control(p, $4); } ; @@ -2330,11 +2330,11 @@ predstate: ; predctrl: - /* empty */ { $$ = BRW_PREDICATE_NORMAL; } - | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; } - | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; } - | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; } - | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; } + /* empty */ { $$ = ELK_PREDICATE_NORMAL; } + | DOT X { $$ = ELK_PREDICATE_ALIGN16_REPLICATE_X; } + | DOT Y { $$ = ELK_PREDICATE_ALIGN16_REPLICATE_Y; } + | DOT Z { $$ = ELK_PREDICATE_ALIGN16_REPLICATE_Z; } + | DOT W { $$ = ELK_PREDICATE_ALIGN16_REPLICATE_W; } | ANYV | ALLV | ANY2H @@ -2377,7 +2377,7 @@ cond_mod: ; condModifiers: - /* empty */ { $$ = BRW_CONDITIONAL_NONE; } + /* empty */ { $$ = ELK_CONDITIONAL_NONE; } | ZERO | EQUAL | NOT_ZERO @@ -2416,8 +2416,8 @@ msgdesc_parts: ; saturate: - /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; } - | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; } + /* empty */ { $$ = ELK_INSTRUCTION_NORMAL; } + | SATURATE { $$ = ELK_INSTRUCTION_SATURATE; } ; /* Execution size */ diff --git a/src/intel/compiler/elk/elk_inst.h b/src/intel/compiler/elk/elk_inst.h index c96b2a4c28c..70b1f40cb44 100644 --- a/src/intel/compiler/elk/elk_inst.h +++ b/src/intel/compiler/elk/elk_inst.h @@ -43,37 +43,37 @@ extern "C" { #endif -/* brw_context.h has a forward declaration of brw_inst, so name the struct. */ -typedef struct brw_inst { +/* elk_context.h has a forward declaration of elk_inst, so name the struct. */ +typedef struct elk_inst { uint64_t data[2]; -} brw_inst; +} elk_inst; -static inline uint64_t brw_inst_bits(const brw_inst *inst, +static inline uint64_t elk_inst_bits(const elk_inst *inst, unsigned high, unsigned low); -static inline void brw_inst_set_bits(brw_inst *inst, +static inline void elk_inst_set_bits(elk_inst *inst, unsigned high, unsigned low, uint64_t value); #define FC(name, hi4, lo4, hi12, lo12, assertions) \ static inline void \ -brw_inst_set_##name(const struct intel_device_info *devinfo, \ - brw_inst *inst, uint64_t v) \ +elk_inst_set_##name(const struct intel_device_info *devinfo, \ + elk_inst *inst, uint64_t v) \ { \ assert(assertions); \ if (devinfo->ver >= 12) \ - brw_inst_set_bits(inst, hi12, lo12, v); \ + elk_inst_set_bits(inst, hi12, lo12, v); \ else \ - brw_inst_set_bits(inst, hi4, lo4, v); \ + elk_inst_set_bits(inst, hi4, lo4, v); \ } \ static inline uint64_t \ -brw_inst_##name(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ +elk_inst_##name(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ assert(assertions); \ if (devinfo->ver >= 12) \ - return brw_inst_bits(inst, hi12, lo12); \ + return elk_inst_bits(inst, hi12, lo12); \ else \ - return brw_inst_bits(inst, hi4, lo4); \ + return elk_inst_bits(inst, hi4, lo4); \ } /* A simple macro for fields which stay in the same place on all generations, @@ -86,81 +86,81 @@ brw_inst_##name(const struct intel_device_info *devinfo, \ */ #define F20(name, hi4, lo4, hi12, lo12, hi20, lo20) \ static inline void \ - brw_inst_set_##name(const struct intel_device_info *devinfo, \ - brw_inst *inst, uint64_t v) \ + elk_inst_set_##name(const struct intel_device_info *devinfo, \ + elk_inst *inst, uint64_t v) \ { \ if (devinfo->ver >= 20) \ - brw_inst_set_bits(inst, hi20, lo20, v); \ + elk_inst_set_bits(inst, hi20, lo20, v); \ else if (devinfo->ver >= 12) \ - brw_inst_set_bits(inst, hi12, lo12, v); \ + elk_inst_set_bits(inst, hi12, lo12, v); \ else \ - brw_inst_set_bits(inst, hi4, lo4, v); \ + elk_inst_set_bits(inst, hi4, lo4, v); \ } \ static inline uint64_t \ - brw_inst_##name(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ + elk_inst_##name(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ if (devinfo->ver >= 20) \ - return brw_inst_bits(inst, hi20, lo20); \ + return elk_inst_bits(inst, hi20, lo20); \ else if (devinfo->ver >= 12) \ - return brw_inst_bits(inst, hi12, lo12); \ + return elk_inst_bits(inst, hi12, lo12); \ else \ - return brw_inst_bits(inst, hi4, lo4); \ + return elk_inst_bits(inst, hi4, lo4); \ } #define FV20(name, hi4, lo4, hi12, lo12, hi20, lo20) \ static inline void \ - brw_inst_set_##name(const struct intel_device_info *devinfo, \ - brw_inst *inst, uint64_t v) \ + elk_inst_set_##name(const struct intel_device_info *devinfo, \ + elk_inst *inst, uint64_t v) \ { \ if (devinfo->ver >= 20) \ - brw_inst_set_bits(inst, hi20, lo20, v & 0x7); \ + elk_inst_set_bits(inst, hi20, lo20, v & 0x7); \ else if (devinfo->ver >= 12) \ - brw_inst_set_bits(inst, hi12, lo12, v); \ + elk_inst_set_bits(inst, hi12, lo12, v); \ else \ - brw_inst_set_bits(inst, hi4, lo4, v); \ + elk_inst_set_bits(inst, hi4, lo4, v); \ } \ static inline uint64_t \ - brw_inst_##name(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ + elk_inst_##name(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ if (devinfo->ver >= 20) \ - return brw_inst_bits(inst, hi20, lo20) == 0x7 ? 0xF : \ - brw_inst_bits(inst, hi20, lo20); \ + return elk_inst_bits(inst, hi20, lo20) == 0x7 ? 0xF : \ + elk_inst_bits(inst, hi20, lo20); \ else if (devinfo->ver >= 12) \ - return brw_inst_bits(inst, hi12, lo12); \ + return elk_inst_bits(inst, hi12, lo12); \ else \ - return brw_inst_bits(inst, hi4, lo4); \ + return elk_inst_bits(inst, hi4, lo4); \ } #define FD20(name, hi4, lo4, hi12, lo12, hi20, lo20, zero20) \ static inline void \ - brw_inst_set_##name(const struct intel_device_info *devinfo, \ - brw_inst *inst, uint64_t v) \ + elk_inst_set_##name(const struct intel_device_info *devinfo, \ + elk_inst *inst, uint64_t v) \ { \ if (devinfo->ver >= 20) { \ - brw_inst_set_bits(inst, hi20, lo20, v >> 1); \ + elk_inst_set_bits(inst, hi20, lo20, v >> 1); \ if (zero20 == -1) \ assert((v & 1) == 0); \ else \ - brw_inst_set_bits(inst, zero20, zero20, v & 1); \ + elk_inst_set_bits(inst, zero20, zero20, v & 1); \ } else if (devinfo->ver >= 12) \ - brw_inst_set_bits(inst, hi12, lo12, v); \ + elk_inst_set_bits(inst, hi12, lo12, v); \ else \ - brw_inst_set_bits(inst, hi4, lo4, v); \ + elk_inst_set_bits(inst, hi4, lo4, v); \ } \ static inline uint64_t \ - brw_inst_##name(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ + elk_inst_##name(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ if (devinfo->ver >= 20) \ - return (brw_inst_bits(inst, hi20, lo20) << 1) | \ + return (elk_inst_bits(inst, hi20, lo20) << 1) | \ (zero20 == -1 ? 0 : \ - brw_inst_bits(inst, zero20, zero20)); \ + elk_inst_bits(inst, zero20, zero20)); \ else if (devinfo->ver >= 12) \ - return brw_inst_bits(inst, hi12, lo12); \ + return elk_inst_bits(inst, hi12, lo12); \ else \ - return brw_inst_bits(inst, hi4, lo4); \ + return elk_inst_bits(inst, hi4, lo4); \ } #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ @@ -192,19 +192,19 @@ brw_inst_##name(const struct intel_device_info *devinfo, \ #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ hi7, lo7, hi8, lo8, hi12, lo12, hi20, lo20) \ static inline void \ -brw_inst_set_##name(const struct intel_device_info *devinfo, \ - brw_inst *inst, uint64_t value) \ +elk_inst_set_##name(const struct intel_device_info *devinfo, \ + elk_inst *inst, uint64_t value) \ { \ BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ hi7, lo7, hi8, lo8, hi12, lo12, hi20, lo20) \ - brw_inst_set_bits(inst, high, low, value); \ + elk_inst_set_bits(inst, high, low, value); \ } \ static inline uint64_t \ -brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ +elk_inst_##name(const struct intel_device_info *devinfo, const elk_inst *inst)\ { \ BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ hi7, lo7, hi8, lo8, hi12, lo12, hi20, lo20) \ - return brw_inst_bits(inst, high, low); \ + return elk_inst_bits(inst, high, low); \ } /* A macro for fields which moved as of Gfx8+. */ @@ -226,34 +226,34 @@ FF(name, \ #define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \ static inline void \ -brw_inst_set_##name(const struct intel_device_info *devinfo, \ - brw_inst *inst, uint64_t value) \ +elk_inst_set_##name(const struct intel_device_info *devinfo, \ + elk_inst *inst, uint64_t value) \ { \ assert(assertions); \ if (devinfo->ver >= 12) { \ const unsigned k = hi12 - lo12 + 1; \ if (hi12ex != -1 && lo12ex != -1) \ - brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \ - brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \ + elk_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \ + elk_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \ } else { \ BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ hi7, lo7, hi8, lo8, -1, -1, -1, -1); \ - brw_inst_set_bits(inst, high, low, value); \ + elk_inst_set_bits(inst, high, low, value); \ } \ } \ static inline uint64_t \ -brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ +elk_inst_##name(const struct intel_device_info *devinfo, const elk_inst *inst)\ { \ assert(assertions); \ if (devinfo->ver >= 12) { \ const unsigned k = hi12 - lo12 + 1; \ return (hi12ex == -1 || lo12ex == -1 ? 0 : \ - brw_inst_bits(inst, hi12ex, lo12ex) << k) | \ - brw_inst_bits(inst, hi12, lo12); \ + elk_inst_bits(inst, hi12ex, lo12ex) << k) | \ + elk_inst_bits(inst, hi12, lo12); \ } else { \ BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ hi7, lo7, hi8, lo8, -1, -1, -1, -1); \ - return brw_inst_bits(inst, high, low); \ + return elk_inst_bits(inst, high, low); \ } \ } @@ -276,30 +276,30 @@ brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ */ #define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \ static inline void \ -brw_inst_set_##name(const struct intel_device_info *devinfo, \ - brw_inst *inst, uint64_t value) \ +elk_inst_set_##name(const struct intel_device_info *devinfo, \ + elk_inst *inst, uint64_t value) \ { \ if (devinfo->ver >= 12) { \ - brw_inst_set_bits(inst, hi12, hi12, value >> 1); \ + elk_inst_set_bits(inst, hi12, hi12, value >> 1); \ if ((value >> 1) == 0) \ - brw_inst_set_bits(inst, lo12, lo12, value & 1); \ + elk_inst_set_bits(inst, lo12, lo12, value & 1); \ } else { \ BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \ hi4, lo4, hi8, lo8, -1, -1, -1, -1); \ - brw_inst_set_bits(inst, high, low, value); \ + elk_inst_set_bits(inst, high, low, value); \ } \ } \ static inline uint64_t \ -brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ +elk_inst_##name(const struct intel_device_info *devinfo, const elk_inst *inst)\ { \ if (devinfo->ver >= 12) { \ - return (brw_inst_bits(inst, hi12, hi12) << 1) | \ - (brw_inst_bits(inst, hi12, hi12) == 0 ? \ - brw_inst_bits(inst, lo12, lo12) : 1); \ + return (elk_inst_bits(inst, hi12, hi12) << 1) | \ + (elk_inst_bits(inst, hi12, hi12) == 0 ? \ + elk_inst_bits(inst, lo12, lo12) : 1); \ } else { \ BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \ hi4, lo4, hi8, lo8, -1, -1, -1, -1); \ - return brw_inst_bits(inst, high, low); \ + return elk_inst_bits(inst, high, low); \ } \ } @@ -308,22 +308,22 @@ brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ */ #define FK(name, hi4, lo4, const12) \ static inline void \ -brw_inst_set_##name(const struct intel_device_info *devinfo, \ - brw_inst *inst, uint64_t v) \ +elk_inst_set_##name(const struct intel_device_info *devinfo, \ + elk_inst *inst, uint64_t v) \ { \ if (devinfo->ver >= 12) \ assert(v == (const12)); \ else \ - brw_inst_set_bits(inst, hi4, lo4, v); \ + elk_inst_set_bits(inst, hi4, lo4, v); \ } \ static inline uint64_t \ -brw_inst_##name(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ +elk_inst_##name(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ if (devinfo->ver >= 12) \ return (const12); \ else \ - return brw_inst_bits(inst, hi4, lo4); \ + return elk_inst_bits(inst, hi4, lo4); \ } FV20(src1_vstride, /* 4+ */ 120, 117, /* 12+ */ 119, 116, /* 20+ */ 118, 116) @@ -409,7 +409,7 @@ FF(nib_control, F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1) F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1) F20(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8) -FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) +FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ ELK_ALIGN_1) /* Bit 7 is Reserved (for future Opcode expansion) */ F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) @@ -465,7 +465,7 @@ F20(3src_qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20, /* 20+ */ 25, 2 F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1) F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1) F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31) -FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) +FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ ELK_ALIGN_1) F(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8) /* Bit 7 is Reserved (for future Opcode expansion) */ F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) @@ -473,19 +473,19 @@ F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) #define REG_TYPE(reg) \ static inline void \ -brw_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \ - brw_inst *inst, enum brw_reg_type type) \ +elk_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \ + elk_inst *inst, enum elk_reg_type type) \ { \ - unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \ - brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \ + unsigned hw_type = elk_reg_type_to_a16_hw_3src_type(devinfo, type); \ + elk_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \ } \ \ -static inline enum brw_reg_type \ -brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ +static inline enum elk_reg_type \ +elk_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ - unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \ - return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \ + unsigned hw_type = elk_inst_3src_a16_##reg##_hw_type(devinfo, inst); \ + return elk_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \ } REG_TYPE(dst) @@ -535,30 +535,30 @@ FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver #define REG_TYPE(reg) \ static inline void \ -brw_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \ - brw_inst *inst, enum brw_reg_type type) \ +elk_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \ + elk_inst *inst, enum elk_reg_type type) \ { \ UNUSED enum gfx10_align1_3src_exec_type exec_type = \ - (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ + (enum gfx10_align1_3src_exec_type) elk_inst_3src_a1_exec_type(devinfo, \ inst); \ - if (brw_reg_type_is_floating_point(type)) { \ - assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \ + if (elk_reg_type_is_floating_point(type)) { \ + assert(exec_type == ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \ } else { \ - assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \ + assert(exec_type == ELK_ALIGN1_3SRC_EXEC_TYPE_INT); \ } \ - unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \ - brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \ + unsigned hw_type = elk_reg_type_to_a1_hw_3src_type(devinfo, type); \ + elk_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \ } \ \ -static inline enum brw_reg_type \ -brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ +static inline enum elk_reg_type \ +elk_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ enum gfx10_align1_3src_exec_type exec_type = \ - (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ + (enum gfx10_align1_3src_exec_type) elk_inst_3src_a1_exec_type(devinfo, \ inst); \ - unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \ - return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \ + unsigned hw_type = elk_inst_3src_a1_##reg##_hw_type(devinfo, inst); \ + return elk_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \ } REG_TYPE(dst) @@ -572,47 +572,47 @@ REG_TYPE(src2) * @{ */ static inline uint16_t -brw_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo, - const brw_inst *insn) +elk_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo, + const elk_inst *insn) { assert(devinfo->ver >= 10); if (devinfo->ver >= 12) - return brw_inst_bits(insn, 79, 64); + return elk_inst_bits(insn, 79, 64); else - return brw_inst_bits(insn, 82, 67); + return elk_inst_bits(insn, 82, 67); } static inline uint16_t -brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo, - const brw_inst *insn) +elk_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo, + const elk_inst *insn) { assert(devinfo->ver >= 10); if (devinfo->ver >= 12) - return brw_inst_bits(insn, 127, 112); + return elk_inst_bits(insn, 127, 112); else - return brw_inst_bits(insn, 124, 109); + return elk_inst_bits(insn, 124, 109); } static inline void -brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo, - brw_inst *insn, uint16_t value) +elk_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo, + elk_inst *insn, uint16_t value) { assert(devinfo->ver >= 10); if (devinfo->ver >= 12) - brw_inst_set_bits(insn, 79, 64, value); + elk_inst_set_bits(insn, 79, 64, value); else - brw_inst_set_bits(insn, 82, 67, value); + elk_inst_set_bits(insn, 82, 67, value); } static inline void -brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo, - brw_inst *insn, uint16_t value) +elk_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo, + elk_inst *insn, uint16_t value) { assert(devinfo->ver >= 10); if (devinfo->ver >= 12) - brw_inst_set_bits(insn, 127, 112, value); + elk_inst_set_bits(insn, 127, 112, value); else - brw_inst_set_bits(insn, 124, 109, value); + elk_inst_set_bits(insn, 124, 109, value); } /** @} */ @@ -645,30 +645,30 @@ F(dpas_3src_dst_hw_type, /* 4+ */ -1, -1, /* 12+ */ 38, 36) #define REG_TYPE(reg) \ static inline void \ -brw_inst_set_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \ - brw_inst *inst, enum brw_reg_type type) \ +elk_inst_set_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \ + elk_inst *inst, enum elk_reg_type type) \ { \ UNUSED enum gfx10_align1_3src_exec_type exec_type = \ - (enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\ + (enum gfx10_align1_3src_exec_type) elk_inst_dpas_3src_exec_type(devinfo,\ inst); \ - if (brw_reg_type_is_floating_point(type)) { \ - assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \ + if (elk_reg_type_is_floating_point(type)) { \ + assert(exec_type == ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \ } else { \ - assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \ + assert(exec_type == ELK_ALIGN1_3SRC_EXEC_TYPE_INT); \ } \ - unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \ - brw_inst_set_dpas_3src_##reg##_hw_type(devinfo, inst, hw_type); \ + unsigned hw_type = elk_reg_type_to_a1_hw_3src_type(devinfo, type); \ + elk_inst_set_dpas_3src_##reg##_hw_type(devinfo, inst, hw_type); \ } \ \ -static inline enum brw_reg_type \ -brw_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ +static inline enum elk_reg_type \ +elk_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ enum gfx10_align1_3src_exec_type exec_type = \ - (enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\ + (enum gfx10_align1_3src_exec_type) elk_inst_dpas_3src_exec_type(devinfo,\ inst); \ - unsigned hw_type = brw_inst_dpas_3src_##reg##_hw_type(devinfo, inst); \ - return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \ + unsigned hw_type = elk_inst_dpas_3src_##reg##_hw_type(devinfo, inst); \ + return elk_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \ } REG_TYPE(dst) @@ -682,80 +682,80 @@ REG_TYPE(src2) * @{ */ static inline void -brw_inst_set_uip(const struct intel_device_info *devinfo, - brw_inst *inst, int32_t value) +elk_inst_set_uip(const struct intel_device_info *devinfo, + elk_inst *inst, int32_t value) { assert(devinfo->ver >= 6); if (devinfo->ver >= 12) - brw_inst_set_src1_is_imm(devinfo, inst, 1); + elk_inst_set_src1_is_imm(devinfo, inst, 1); if (devinfo->ver >= 8) { - brw_inst_set_bits(inst, 95, 64, (uint32_t)value); + elk_inst_set_bits(inst, 95, 64, (uint32_t)value); } else { assert(value <= (1 << 16) - 1); assert(value > -(1 << 16)); - brw_inst_set_bits(inst, 127, 112, (uint16_t)value); + elk_inst_set_bits(inst, 127, 112, (uint16_t)value); } } static inline int32_t -brw_inst_uip(const struct intel_device_info *devinfo, const brw_inst *inst) +elk_inst_uip(const struct intel_device_info *devinfo, const elk_inst *inst) { assert(devinfo->ver >= 6); if (devinfo->ver >= 8) { - return brw_inst_bits(inst, 95, 64); + return elk_inst_bits(inst, 95, 64); } else { - return (int16_t)brw_inst_bits(inst, 127, 112); + return (int16_t)elk_inst_bits(inst, 127, 112); } } static inline void -brw_inst_set_jip(const struct intel_device_info *devinfo, - brw_inst *inst, int32_t value) +elk_inst_set_jip(const struct intel_device_info *devinfo, + elk_inst *inst, int32_t value) { assert(devinfo->ver >= 6); if (devinfo->ver >= 12) - brw_inst_set_src0_is_imm(devinfo, inst, 1); + elk_inst_set_src0_is_imm(devinfo, inst, 1); if (devinfo->ver >= 8) { - brw_inst_set_bits(inst, 127, 96, (uint32_t)value); + elk_inst_set_bits(inst, 127, 96, (uint32_t)value); } else { assert(value <= (1 << 15) - 1); assert(value >= -(1 << 15)); - brw_inst_set_bits(inst, 111, 96, (uint16_t)value); + elk_inst_set_bits(inst, 111, 96, (uint16_t)value); } } static inline int32_t -brw_inst_jip(const struct intel_device_info *devinfo, const brw_inst *inst) +elk_inst_jip(const struct intel_device_info *devinfo, const elk_inst *inst) { assert(devinfo->ver >= 6); if (devinfo->ver >= 8) { - return brw_inst_bits(inst, 127, 96); + return elk_inst_bits(inst, 127, 96); } else { - return (int16_t)brw_inst_bits(inst, 111, 96); + return (int16_t)elk_inst_bits(inst, 111, 96); } } /** Like FC, but using int16_t to handle negative jump targets. */ #define FJ(name, high, low, assertions) \ static inline void \ -brw_inst_set_##name(const struct intel_device_info *devinfo, brw_inst *inst, int16_t v) \ +elk_inst_set_##name(const struct intel_device_info *devinfo, elk_inst *inst, int16_t v) \ { \ assert(assertions); \ (void) devinfo; \ - brw_inst_set_bits(inst, high, low, (uint16_t) v); \ + elk_inst_set_bits(inst, high, low, (uint16_t) v); \ } \ static inline int16_t \ -brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ +elk_inst_##name(const struct intel_device_info *devinfo, const elk_inst *inst)\ { \ assert(assertions); \ (void) devinfo; \ - return brw_inst_bits(inst, high, low); \ + return elk_inst_bits(inst, high, low); \ } FJ(gfx6_jump_count, 63, 48, devinfo->ver == 6) @@ -797,23 +797,23 @@ FC(send_ex_bso, /* 4+ */ -1, -1, /* 12+ */ 39, 39, devinfo->verx * separately. */ static inline void -brw_inst_set_send_desc(const struct intel_device_info *devinfo, - brw_inst *inst, uint32_t value) +elk_inst_set_send_desc(const struct intel_device_info *devinfo, + elk_inst *inst, uint32_t value) { if (devinfo->ver >= 12) { - brw_inst_set_bits(inst, 123, 122, GET_BITS(value, 31, 30)); - brw_inst_set_bits(inst, 71, 67, GET_BITS(value, 29, 25)); - brw_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20)); - brw_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11)); - brw_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0)); + elk_inst_set_bits(inst, 123, 122, GET_BITS(value, 31, 30)); + elk_inst_set_bits(inst, 71, 67, GET_BITS(value, 29, 25)); + elk_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20)); + elk_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11)); + elk_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0)); } else if (devinfo->ver >= 9) { - brw_inst_set_bits(inst, 126, 96, value); + elk_inst_set_bits(inst, 126, 96, value); assert(value >> 31 == 0); } else if (devinfo->ver >= 5) { - brw_inst_set_bits(inst, 124, 96, value); + elk_inst_set_bits(inst, 124, 96, value); assert(value >> 29 == 0); } else { - brw_inst_set_bits(inst, 119, 96, value); + elk_inst_set_bits(inst, 119, 96, value); assert(value >> 24 == 0); } } @@ -821,24 +821,24 @@ brw_inst_set_send_desc(const struct intel_device_info *devinfo, /** * Get the SEND(C) message descriptor immediate. * - * \sa brw_inst_set_send_desc(). + * \sa elk_inst_set_send_desc(). */ static inline uint32_t -brw_inst_send_desc(const struct intel_device_info *devinfo, - const brw_inst *inst) +elk_inst_send_desc(const struct intel_device_info *devinfo, + const elk_inst *inst) { if (devinfo->ver >= 12) { - return (brw_inst_bits(inst, 123, 122) << 30 | - brw_inst_bits(inst, 71, 67) << 25 | - brw_inst_bits(inst, 55, 51) << 20 | - brw_inst_bits(inst, 121, 113) << 11 | - brw_inst_bits(inst, 91, 81)); + return (elk_inst_bits(inst, 123, 122) << 30 | + elk_inst_bits(inst, 71, 67) << 25 | + elk_inst_bits(inst, 55, 51) << 20 | + elk_inst_bits(inst, 121, 113) << 11 | + elk_inst_bits(inst, 91, 81)); } else if (devinfo->ver >= 9) { - return brw_inst_bits(inst, 126, 96); + return elk_inst_bits(inst, 126, 96); } else if (devinfo->ver >= 5) { - return brw_inst_bits(inst, 124, 96); + return elk_inst_bits(inst, 124, 96); } else { - return brw_inst_bits(inst, 119, 96); + return elk_inst_bits(inst, 119, 96); } } @@ -852,22 +852,22 @@ brw_inst_send_desc(const struct intel_device_info *devinfo, * separately. */ static inline void -brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo, - brw_inst *inst, uint32_t value) +elk_inst_set_send_ex_desc(const struct intel_device_info *devinfo, + elk_inst *inst, uint32_t value) { if (devinfo->ver >= 12) { - brw_inst_set_bits(inst, 127, 124, GET_BITS(value, 31, 28)); - brw_inst_set_bits(inst, 97, 96, GET_BITS(value, 27, 26)); - brw_inst_set_bits(inst, 65, 64, GET_BITS(value, 25, 24)); - brw_inst_set_bits(inst, 47, 35, GET_BITS(value, 23, 11)); - brw_inst_set_bits(inst, 103, 99, GET_BITS(value, 10, 6)); + elk_inst_set_bits(inst, 127, 124, GET_BITS(value, 31, 28)); + elk_inst_set_bits(inst, 97, 96, GET_BITS(value, 27, 26)); + elk_inst_set_bits(inst, 65, 64, GET_BITS(value, 25, 24)); + elk_inst_set_bits(inst, 47, 35, GET_BITS(value, 23, 11)); + elk_inst_set_bits(inst, 103, 99, GET_BITS(value, 10, 6)); assert(GET_BITS(value, 5, 0) == 0); } else { assert(devinfo->ver >= 9); - brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28)); - brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24)); - brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20)); - brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16)); + elk_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28)); + elk_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24)); + elk_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20)); + elk_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16)); assert(GET_BITS(value, 15, 0) == 0); } } @@ -882,15 +882,15 @@ brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo, * separately. */ static inline void -brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo, - brw_inst *inst, uint32_t value) +elk_inst_set_sends_ex_desc(const struct intel_device_info *devinfo, + elk_inst *inst, uint32_t value) { if (devinfo->ver >= 12) { - brw_inst_set_send_ex_desc(devinfo, inst, value); + elk_inst_set_send_ex_desc(devinfo, inst, value); } else { - brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16)); + elk_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16)); assert(GET_BITS(value, 15, 10) == 0); - brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6)); + elk_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6)); assert(GET_BITS(value, 5, 0) == 0); } } @@ -898,41 +898,41 @@ brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo, /** * Get the SEND(C) message extended descriptor immediate. * - * \sa brw_inst_set_send_ex_desc(). + * \sa elk_inst_set_send_ex_desc(). */ static inline uint32_t -brw_inst_send_ex_desc(const struct intel_device_info *devinfo, - const brw_inst *inst) +elk_inst_send_ex_desc(const struct intel_device_info *devinfo, + const elk_inst *inst) { if (devinfo->ver >= 12) { - return (brw_inst_bits(inst, 127, 124) << 28 | - brw_inst_bits(inst, 97, 96) << 26 | - brw_inst_bits(inst, 65, 64) << 24 | - brw_inst_bits(inst, 47, 35) << 11 | - brw_inst_bits(inst, 103, 99) << 6); + return (elk_inst_bits(inst, 127, 124) << 28 | + elk_inst_bits(inst, 97, 96) << 26 | + elk_inst_bits(inst, 65, 64) << 24 | + elk_inst_bits(inst, 47, 35) << 11 | + elk_inst_bits(inst, 103, 99) << 6); } else { assert(devinfo->ver >= 9); - return (brw_inst_bits(inst, 94, 91) << 28 | - brw_inst_bits(inst, 88, 85) << 24 | - brw_inst_bits(inst, 83, 80) << 20 | - brw_inst_bits(inst, 67, 64) << 16); + return (elk_inst_bits(inst, 94, 91) << 28 | + elk_inst_bits(inst, 88, 85) << 24 | + elk_inst_bits(inst, 83, 80) << 20 | + elk_inst_bits(inst, 67, 64) << 16); } } /** * Get the SENDS(C) message extended descriptor immediate. * - * \sa brw_inst_set_send_ex_desc(). + * \sa elk_inst_set_send_ex_desc(). */ static inline uint32_t -brw_inst_sends_ex_desc(const struct intel_device_info *devinfo, - const brw_inst *inst) +elk_inst_sends_ex_desc(const struct intel_device_info *devinfo, + const elk_inst *inst) { if (devinfo->ver >= 12) { - return brw_inst_send_ex_desc(devinfo, inst); + return elk_inst_send_ex_desc(devinfo, inst); } else { - return (brw_inst_bits(inst, 95, 80) << 16 | - brw_inst_bits(inst, 67, 64) << 6); + return (elk_inst_bits(inst, 95, 80) << 16 | + elk_inst_bits(inst, 67, 64) << 6); } } @@ -1227,74 +1227,74 @@ F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) * @{ */ static inline int -brw_inst_imm_d(const struct intel_device_info *devinfo, const brw_inst *insn) +elk_inst_imm_d(const struct intel_device_info *devinfo, const elk_inst *insn) { (void) devinfo; - return brw_inst_bits(insn, 127, 96); + return elk_inst_bits(insn, 127, 96); } static inline unsigned -brw_inst_imm_ud(const struct intel_device_info *devinfo, const brw_inst *insn) +elk_inst_imm_ud(const struct intel_device_info *devinfo, const elk_inst *insn) { (void) devinfo; - return brw_inst_bits(insn, 127, 96); + return elk_inst_bits(insn, 127, 96); } static inline uint64_t -brw_inst_imm_uq(const struct intel_device_info *devinfo, - const brw_inst *insn) +elk_inst_imm_uq(const struct intel_device_info *devinfo, + const elk_inst *insn) { if (devinfo->ver >= 12) { - return brw_inst_bits(insn, 95, 64) << 32 | - brw_inst_bits(insn, 127, 96); + return elk_inst_bits(insn, 95, 64) << 32 | + elk_inst_bits(insn, 127, 96); } else { assert(devinfo->ver >= 8); - return brw_inst_bits(insn, 127, 64); + return elk_inst_bits(insn, 127, 64); } } static inline float -brw_inst_imm_f(const struct intel_device_info *devinfo, const brw_inst *insn) +elk_inst_imm_f(const struct intel_device_info *devinfo, const elk_inst *insn) { union { float f; uint32_t u; } ft; (void) devinfo; - ft.u = brw_inst_bits(insn, 127, 96); + ft.u = elk_inst_bits(insn, 127, 96); return ft.f; } static inline double -brw_inst_imm_df(const struct intel_device_info *devinfo, const brw_inst *insn) +elk_inst_imm_df(const struct intel_device_info *devinfo, const elk_inst *insn) { union { double d; uint64_t u; } dt; - dt.u = brw_inst_imm_uq(devinfo, insn); + dt.u = elk_inst_imm_uq(devinfo, insn); return dt.d; } static inline void -brw_inst_set_imm_d(const struct intel_device_info *devinfo, - brw_inst *insn, int value) +elk_inst_set_imm_d(const struct intel_device_info *devinfo, + elk_inst *insn, int value) { (void) devinfo; - return brw_inst_set_bits(insn, 127, 96, value); + return elk_inst_set_bits(insn, 127, 96, value); } static inline void -brw_inst_set_imm_ud(const struct intel_device_info *devinfo, - brw_inst *insn, unsigned value) +elk_inst_set_imm_ud(const struct intel_device_info *devinfo, + elk_inst *insn, unsigned value) { (void) devinfo; - return brw_inst_set_bits(insn, 127, 96, value); + return elk_inst_set_bits(insn, 127, 96, value); } static inline void -brw_inst_set_imm_f(const struct intel_device_info *devinfo, - brw_inst *insn, float value) +elk_inst_set_imm_f(const struct intel_device_info *devinfo, + elk_inst *insn, float value) { union { float f; @@ -1302,12 +1302,12 @@ brw_inst_set_imm_f(const struct intel_device_info *devinfo, } ft; (void) devinfo; ft.f = value; - brw_inst_set_bits(insn, 127, 96, ft.u); + elk_inst_set_bits(insn, 127, 96, ft.u); } static inline void -brw_inst_set_imm_df(const struct intel_device_info *devinfo, - brw_inst *insn, double value) +elk_inst_set_imm_df(const struct intel_device_info *devinfo, + elk_inst *insn, double value) { union { double d; @@ -1317,23 +1317,23 @@ brw_inst_set_imm_df(const struct intel_device_info *devinfo, dt.d = value; if (devinfo->ver >= 12) { - brw_inst_set_bits(insn, 95, 64, dt.u >> 32); - brw_inst_set_bits(insn, 127, 96, dt.u & 0xFFFFFFFF); + elk_inst_set_bits(insn, 95, 64, dt.u >> 32); + elk_inst_set_bits(insn, 127, 96, dt.u & 0xFFFFFFFF); } else { - brw_inst_set_bits(insn, 127, 64, dt.u); + elk_inst_set_bits(insn, 127, 64, dt.u); } } static inline void -brw_inst_set_imm_uq(const struct intel_device_info *devinfo, - brw_inst *insn, uint64_t value) +elk_inst_set_imm_uq(const struct intel_device_info *devinfo, + elk_inst *insn, uint64_t value) { (void) devinfo; if (devinfo->ver >= 12) { - brw_inst_set_bits(insn, 95, 64, value >> 32); - brw_inst_set_bits(insn, 127, 96, value & 0xFFFFFFFF); + elk_inst_set_bits(insn, 95, 64, value >> 32); + elk_inst_set_bits(insn, 127, 96, value & 0xFFFFFFFF); } else { - brw_inst_set_bits(insn, 127, 64, value); + elk_inst_set_bits(insn, 127, 64, value); } } @@ -1341,25 +1341,25 @@ brw_inst_set_imm_uq(const struct intel_device_info *devinfo, #define REG_TYPE(reg) \ static inline void \ -brw_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \ - brw_inst *inst, enum brw_reg_file file, \ - enum brw_reg_type type) \ +elk_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \ + elk_inst *inst, enum elk_reg_file file, \ + enum elk_reg_type type) \ { \ - assert(file <= BRW_IMMEDIATE_VALUE); \ - unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \ - brw_inst_set_##reg##_reg_file(devinfo, inst, file); \ - brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \ + assert(file <= ELK_IMMEDIATE_VALUE); \ + unsigned hw_type = elk_reg_type_to_hw_type(devinfo, file, type); \ + elk_inst_set_##reg##_reg_file(devinfo, inst, file); \ + elk_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \ } \ \ -static inline enum brw_reg_type \ -brw_inst_##reg##_type(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ +static inline enum elk_reg_type \ +elk_inst_##reg##_type(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \ - (unsigned) BRW_GENERAL_REGISTER_FILE : \ - brw_inst_##reg##_reg_file(devinfo, inst); \ - unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \ - return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \ + (unsigned) ELK_GENERAL_REGISTER_FILE : \ + elk_inst_##reg##_reg_file(devinfo, inst); \ + unsigned hw_type = elk_inst_##reg##_reg_hw_type(devinfo, inst); \ + return elk_hw_type_to_reg_type(devinfo, (enum elk_reg_file)file, hw_type); \ } REG_TYPE(dst) @@ -1369,83 +1369,83 @@ REG_TYPE(src1) /* The AddrImm fields are split into two discontiguous sections on Gfx8+ */ -#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low, \ +#define ELK_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low, \ g12_high, g12_low, g20_high, g20_low, g20_zero) \ static inline void \ -brw_inst_set_##reg##_ia1_addr_imm(const struct \ +elk_inst_set_##reg##_ia1_addr_imm(const struct \ intel_device_info *devinfo, \ - brw_inst *inst, \ + elk_inst *inst, \ unsigned value) \ { \ if (devinfo->ver >= 20) { \ assert((value & ~0x7ff) == 0); \ - brw_inst_set_bits(inst, g20_high, g20_low, value >> 1); \ + elk_inst_set_bits(inst, g20_high, g20_low, value >> 1); \ if (g20_zero == -1) \ assert((value & 1) == 0); \ else \ - brw_inst_set_bits(inst, g20_zero, g20_zero, value & 1); \ + elk_inst_set_bits(inst, g20_zero, g20_zero, value & 1); \ } else if (devinfo->ver >= 12) { \ assert((value & ~0x3ff) == 0); \ - brw_inst_set_bits(inst, g12_high, g12_low, value); \ + elk_inst_set_bits(inst, g12_high, g12_low, value); \ } else if (devinfo->ver >= 8) { \ assert((value & ~0x3ff) == 0); \ - brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \ - brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \ + elk_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \ + elk_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \ } else { \ assert((value & ~0x3ff) == 0); \ - brw_inst_set_bits(inst, g4_high, g4_low, value); \ + elk_inst_set_bits(inst, g4_high, g4_low, value); \ } \ } \ static inline unsigned \ -brw_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ +elk_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ if (devinfo->ver >= 20) { \ - return brw_inst_bits(inst, g20_high, g20_low) << 1 | \ + return elk_inst_bits(inst, g20_high, g20_low) << 1 | \ (g20_zero == -1 ? 0 : \ - brw_inst_bits(inst, g20_zero, g20_zero)); \ + elk_inst_bits(inst, g20_zero, g20_zero)); \ } else if (devinfo->ver >= 12) { \ - return brw_inst_bits(inst, g12_high, g12_low); \ + return elk_inst_bits(inst, g12_high, g12_low); \ } else if (devinfo->ver >= 8) { \ - return brw_inst_bits(inst, g8_high, g8_low) | \ - (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \ + return elk_inst_bits(inst, g8_high, g8_low) | \ + (elk_inst_bits(inst, g8_nine, g8_nine) << 9); \ } else { \ - return brw_inst_bits(inst, g4_high, g4_low); \ + return elk_inst_bits(inst, g4_high, g4_low); \ } \ } /* AddrImm for Align1 Indirect Addressing */ /* -Gen 4- ----Gfx8---- -Gfx12- ---Gfx20--- */ -BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96, 107, 98, 107, 98, -1) -BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64, 75, 66, 75, 66, 87) -BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48, 59, 50, 59, 50, 33) +ELK_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96, 107, 98, 107, 98, -1) +ELK_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64, 75, 66, 75, 66, 87) +ELK_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48, 59, 50, 59, 50, 33) -#define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \ +#define ELK_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \ static inline void \ -brw_inst_set_##reg##_ia16_addr_imm(const struct \ +elk_inst_set_##reg##_ia16_addr_imm(const struct \ intel_device_info *devinfo, \ - brw_inst *inst, unsigned value) \ + elk_inst *inst, unsigned value) \ { \ assert(devinfo->ver < 12); \ assert((value & ~0x3ff) == 0); \ if (devinfo->ver >= 8) { \ assert(GET_BITS(value, 3, 0) == 0); \ - brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \ - brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \ + elk_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \ + elk_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \ } else { \ - brw_inst_set_bits(inst, g4_high, g4_low, value); \ + elk_inst_set_bits(inst, g4_high, g4_low, value); \ } \ } \ static inline unsigned \ -brw_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \ - const brw_inst *inst) \ +elk_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \ + const elk_inst *inst) \ { \ assert(devinfo->ver < 12); \ if (devinfo->ver >= 8) { \ - return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \ - (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \ + return (elk_inst_bits(inst, g8_high, g8_low) << 4) | \ + (elk_inst_bits(inst, g8_nine, g8_nine) << 9); \ } else { \ - return brw_inst_bits(inst, g4_high, g4_low); \ + return elk_inst_bits(inst, g4_high, g4_low); \ } \ } @@ -1453,11 +1453,11 @@ brw_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \ * Compared to Align1, these are missing the low 4 bits. * -Gen 4- ----Gfx8---- */ -BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100) -BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68) -BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52) -BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68) -BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52) +ELK_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100) +ELK_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68) +ELK_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52) +ELK_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68) +ELK_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52) /** * Fetch a set of contiguous bits from the instruction. @@ -1465,7 +1465,7 @@ BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52) * Bits indices range from 0..127; fields may not cross 64-bit boundaries. */ static inline uint64_t -brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low) +elk_inst_bits(const elk_inst *inst, unsigned high, unsigned low) { assume(high < 128); assume(high >= low); @@ -1487,7 +1487,7 @@ brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low) * Bits indices range from 0..127; fields may not cross 64-bit boundaries. */ static inline void -brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value) +elk_inst_set_bits(elk_inst *inst, unsigned high, unsigned low, uint64_t value) { assume(high < 128); assume(high >= low); @@ -1505,8 +1505,8 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value) inst->data[word] = (inst->data[word] & ~mask) | (value << low); } -#undef BRW_IA16_ADDR_IMM -#undef BRW_IA1_ADDR_IMM +#undef ELK_IA16_ADDR_IMM +#undef ELK_IA1_ADDR_IMM #undef MD #undef F8 #undef FF @@ -1518,7 +1518,7 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value) typedef struct { uint64_t data; -} brw_compact_inst; +} elk_compact_inst; /** * Fetch a set of contiguous bits from the compacted instruction. @@ -1526,7 +1526,7 @@ typedef struct { * Bits indices range from 0..63. */ static inline unsigned -brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low) +elk_compact_inst_bits(const elk_compact_inst *inst, unsigned high, unsigned low) { assume(high < 64); assume(high >= low); @@ -1541,7 +1541,7 @@ brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low) * Bits indices range from 0..63. */ static inline void -brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low, +elk_compact_inst_set_bits(elk_compact_inst *inst, unsigned high, unsigned low, uint64_t value) { assume(high < 64); @@ -1556,25 +1556,25 @@ brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low, #define FC(name, high, low, gfx12_high, gfx12_low, assertions) \ static inline void \ -brw_compact_inst_set_##name(const struct \ +elk_compact_inst_set_##name(const struct \ intel_device_info *devinfo, \ - brw_compact_inst *inst, unsigned v) \ + elk_compact_inst *inst, unsigned v) \ { \ assert(assertions); \ if (devinfo->ver >= 12) \ - brw_compact_inst_set_bits(inst, gfx12_high, gfx12_low, v); \ + elk_compact_inst_set_bits(inst, gfx12_high, gfx12_low, v); \ else \ - brw_compact_inst_set_bits(inst, high, low, v); \ + elk_compact_inst_set_bits(inst, high, low, v); \ } \ static inline unsigned \ -brw_compact_inst_##name(const struct intel_device_info *devinfo, \ - const brw_compact_inst *inst) \ +elk_compact_inst_##name(const struct intel_device_info *devinfo, \ + const elk_compact_inst *inst) \ { \ assert(assertions); \ if (devinfo->ver >= 12) \ - return brw_compact_inst_bits(inst, gfx12_high, gfx12_low); \ + return elk_compact_inst_bits(inst, gfx12_high, gfx12_low); \ else \ - return brw_compact_inst_bits(inst, high, low); \ + return elk_compact_inst_bits(inst, high, low); \ } /* A simple macro for fields which stay in the same place on all generations @@ -1588,31 +1588,31 @@ brw_compact_inst_##name(const struct intel_device_info *devinfo, \ */ #define F20(name, high, low, hi8, lo8, hi12, lo12, hi20, lo20) \ static inline void \ -brw_compact_inst_set_##name(const struct \ +elk_compact_inst_set_##name(const struct \ intel_device_info *devinfo, \ - brw_compact_inst *inst, unsigned v) \ + elk_compact_inst *inst, unsigned v) \ { \ if (devinfo->ver >= 20) \ - brw_compact_inst_set_bits(inst, hi20, lo20, v); \ + elk_compact_inst_set_bits(inst, hi20, lo20, v); \ else if (devinfo->ver >= 12) \ - brw_compact_inst_set_bits(inst, hi12, lo12, v); \ + elk_compact_inst_set_bits(inst, hi12, lo12, v); \ else if (devinfo->ver >= 8) \ - brw_compact_inst_set_bits(inst, hi8, lo8, v); \ + elk_compact_inst_set_bits(inst, hi8, lo8, v); \ else \ - brw_compact_inst_set_bits(inst, high, low, v); \ + elk_compact_inst_set_bits(inst, high, low, v); \ } \ static inline unsigned \ -brw_compact_inst_##name(const struct intel_device_info *devinfo, \ - const brw_compact_inst *inst) \ +elk_compact_inst_##name(const struct intel_device_info *devinfo, \ + const elk_compact_inst *inst) \ { \ if (devinfo->ver >= 20) \ - return brw_compact_inst_bits(inst, hi20, lo20); \ + return elk_compact_inst_bits(inst, hi20, lo20); \ else if (devinfo->ver >= 12) \ - return brw_compact_inst_bits(inst, hi12, lo12); \ + return elk_compact_inst_bits(inst, hi12, lo12); \ else if (devinfo->ver >= 8) \ - return brw_compact_inst_bits(inst, hi8, lo8); \ + return elk_compact_inst_bits(inst, hi8, lo8); \ else \ - return brw_compact_inst_bits(inst, high, low); \ + return elk_compact_inst_bits(inst, high, low); \ } /* A macro for fields which gained extra discontiguous bits in Gfx20 @@ -1621,36 +1621,36 @@ brw_compact_inst_##name(const struct intel_device_info *devinfo, \ #define FD20(name, high, low, hi8, lo8, hi12, lo12, \ hi20, lo20, hi20ex, lo20ex) \ static inline void \ -brw_compact_inst_set_##name(const struct \ +elk_compact_inst_set_##name(const struct \ intel_device_info *devinfo, \ - brw_compact_inst *inst, unsigned v) \ + elk_compact_inst *inst, unsigned v) \ { \ if (devinfo->ver >= 20) { \ const unsigned k = hi20 - lo20 + 1; \ - brw_compact_inst_set_bits(inst, hi20ex, lo20ex, v >> k); \ - brw_compact_inst_set_bits(inst, hi20, lo20, v & ((1u << k) - 1)); \ + elk_compact_inst_set_bits(inst, hi20ex, lo20ex, v >> k); \ + elk_compact_inst_set_bits(inst, hi20, lo20, v & ((1u << k) - 1)); \ } else if (devinfo->ver >= 12) { \ - brw_compact_inst_set_bits(inst, hi12, lo12, v); \ + elk_compact_inst_set_bits(inst, hi12, lo12, v); \ } else if (devinfo->ver >= 8) { \ - brw_compact_inst_set_bits(inst, hi8, lo8, v); \ + elk_compact_inst_set_bits(inst, hi8, lo8, v); \ } else { \ - brw_compact_inst_set_bits(inst, high, low, v); \ + elk_compact_inst_set_bits(inst, high, low, v); \ } \ } \ static inline unsigned \ -brw_compact_inst_##name(const struct intel_device_info *devinfo, \ - const brw_compact_inst *inst) \ +elk_compact_inst_##name(const struct intel_device_info *devinfo, \ + const elk_compact_inst *inst) \ { \ if (devinfo->ver >= 20) { \ const unsigned k = hi20 - lo20 + 1; \ - return (brw_compact_inst_bits(inst, hi20ex, lo20ex) << k | \ - brw_compact_inst_bits(inst, hi20, lo20)); \ + return (elk_compact_inst_bits(inst, hi20ex, lo20ex) << k | \ + elk_compact_inst_bits(inst, hi20, lo20)); \ } else if (devinfo->ver >= 12) { \ - return brw_compact_inst_bits(inst, hi12, lo12); \ + return elk_compact_inst_bits(inst, hi12, lo12); \ } else if (devinfo->ver >= 8) { \ - return brw_compact_inst_bits(inst, hi8, lo8); \ + return elk_compact_inst_bits(inst, hi8, lo8); \ } else { \ - return brw_compact_inst_bits(inst, high, low); \ + return elk_compact_inst_bits(inst, high, low); \ } \ } @@ -1659,9 +1659,9 @@ F(src0_reg_nr, /* 4+ */ 55, 48, /* 12+ */ 47, 40) F20(dst_reg_nr, /* 4+ */ 47, 40, /* 8+ */ 47, 40, /* 12+ */ 23, 16, /* 20+ */ 39, 32) F(src1_index, /* 4+ */ 39, 35, /* 12+ */ 55, 52) F20(src0_index, /* 4+ */ 34, 30, /* 8+ */ 34, 30, /* 12+ */ 51, 48, /* 20+ */ 25, 23) -F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */ +F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as elk_inst */ FC(flag_subreg_nr, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver <= 6) -F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */ +F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as elk_inst */ FC(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->ver >= 6) FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->verx10 == 45 || devinfo->ver == 5) F20(subreg_index, /* 4+ */ 22, 18, /* 8+ */ 22, 18, /* 12+ */ 39, 35, /* 20+ */ 51, 48) @@ -1669,17 +1669,17 @@ FD20(datatype_index, /* 4+ */ 17, 13, /* 8+ */ 17, 13, /* 12+ */ 34, 30, /* 20+ F20(control_index, /* 4+ */ 12, 8, /* 8+ */ 12, 8, /* 12+ */ 28, 24, /* 20+ */ 22, 18) F20(swsb, /* 4+ */ -1, -1, /* 8+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8) F(debug_control, /* 4+ */ 7, 7, /* 12+ */ 7, 7) -F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */ +F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as elk_inst */ static inline unsigned -brw_compact_inst_imm(const struct intel_device_info *devinfo, - const brw_compact_inst *inst) +elk_compact_inst_imm(const struct intel_device_info *devinfo, + const elk_compact_inst *inst) { if (devinfo->ver >= 12) { - return brw_compact_inst_bits(inst, 63, 52); + return elk_compact_inst_bits(inst, 63, 52); } else { - return (brw_compact_inst_bits(inst, 39, 35) << 8) | - (brw_compact_inst_bits(inst, 63, 56)); + return (elk_compact_inst_bits(inst, 39, 35) << 8) | + (elk_compact_inst_bits(inst, 63, 56)); } } @@ -1712,17 +1712,17 @@ FC(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0, devinfo->ver >= 8) #undef F static inline void -brw_inst_set_opcode(const struct brw_isa_info *isa, - struct brw_inst *inst, enum opcode opcode) +elk_inst_set_opcode(const struct elk_isa_info *isa, + struct elk_inst *inst, enum elk_opcode opcode) { - brw_inst_set_hw_opcode(isa->devinfo, inst, brw_opcode_encode(isa, opcode)); + elk_inst_set_hw_opcode(isa->devinfo, inst, elk_opcode_encode(isa, opcode)); } -static inline enum opcode -brw_inst_opcode(const struct brw_isa_info *isa, - const struct brw_inst *inst) +static inline enum elk_opcode +elk_inst_opcode(const struct elk_isa_info *isa, + const struct elk_inst *inst) { - return brw_opcode_decode(isa, brw_inst_hw_opcode(isa->devinfo, inst)); + return elk_opcode_decode(isa, elk_inst_hw_opcode(isa->devinfo, inst)); } #ifdef __cplusplus diff --git a/src/intel/compiler/elk/elk_interpolation_map.c b/src/intel/compiler/elk/elk_interpolation_map.c index 0fd65cce3c3..5b9c59d87bc 100644 --- a/src/intel/compiler/elk/elk_interpolation_map.c +++ b/src/intel/compiler/elk/elk_interpolation_map.c @@ -36,7 +36,7 @@ static char const *get_qual_name(int mode) } static void -gfx4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data, +gfx4_frag_prog_set_interp_modes(struct elk_wm_prog_data *prog_data, const struct intel_vue_map *vue_map, unsigned location, unsigned slot_count, enum glsl_interp_mode interp) @@ -57,8 +57,8 @@ gfx4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data, /* Set up interpolation modes for every element in the VUE */ void -brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, nir_shader *nir, - struct brw_wm_prog_data *prog_data) +elk_setup_vue_interpolation(const struct intel_vue_map *vue_map, nir_shader *nir, + struct elk_wm_prog_data *prog_data) { /* Initialise interp_mode. INTERP_MODE_NONE == 0 */ memset(prog_data->interp_mode, 0, sizeof(prog_data->interp_mode)); @@ -102,7 +102,7 @@ brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, nir_shader *nir fprintf(stderr, "%d: %d %s ofs %d\n", i, varying, get_qual_name(prog_data->interp_mode[i]), - brw_vue_slot_to_offset(i)); + elk_vue_slot_to_offset(i)); } } } diff --git a/src/intel/compiler/elk/elk_ir.h b/src/intel/compiler/elk/elk_ir.h index f68c15cc21a..8e4e42dfcb7 100644 --- a/src/intel/compiler/elk/elk_ir.h +++ b/src/intel/compiler/elk/elk_ir.h @@ -38,27 +38,27 @@ #define MAX_VGRF_SIZE(devinfo) ((devinfo)->ver >= 20 ? 40 : 20) #ifdef __cplusplus -struct backend_reg : private brw_reg +struct elk_backend_reg : private elk_reg { - backend_reg() {} - backend_reg(const struct brw_reg ®) : brw_reg(reg), offset(0) {} + elk_backend_reg() {} + elk_backend_reg(const struct elk_reg ®) : elk_reg(reg), offset(0) {} - const brw_reg &as_brw_reg() const + const elk_reg &as_elk_reg() const { assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); assert(offset == 0); - return static_cast(*this); + return static_cast(*this); } - brw_reg &as_brw_reg() + elk_reg &as_elk_reg() { assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); assert(offset == 0); - return static_cast(*this); + return static_cast(*this); } - bool equals(const backend_reg &r) const; - bool negative_equals(const backend_reg &r) const; + bool equals(const elk_backend_reg &r) const; + bool negative_equals(const elk_backend_reg &r) const; bool is_zero() const; bool is_one() const; @@ -69,33 +69,33 @@ struct backend_reg : private brw_reg /** Offset from the start of the (virtual) register in bytes. */ uint16_t offset; - using brw_reg::type; - using brw_reg::file; - using brw_reg::negate; - using brw_reg::abs; - using brw_reg::address_mode; - using brw_reg::subnr; - using brw_reg::nr; + using elk_reg::type; + using elk_reg::file; + using elk_reg::negate; + using elk_reg::abs; + using elk_reg::address_mode; + using elk_reg::subnr; + using elk_reg::nr; - using brw_reg::swizzle; - using brw_reg::writemask; - using brw_reg::indirect_offset; - using brw_reg::vstride; - using brw_reg::width; - using brw_reg::hstride; + using elk_reg::swizzle; + using elk_reg::writemask; + using elk_reg::indirect_offset; + using elk_reg::vstride; + using elk_reg::width; + using elk_reg::hstride; - using brw_reg::df; - using brw_reg::f; - using brw_reg::d; - using brw_reg::ud; - using brw_reg::d64; - using brw_reg::u64; + using elk_reg::df; + using elk_reg::f; + using elk_reg::d; + using elk_reg::ud; + using elk_reg::d64; + using elk_reg::u64; }; -struct bblock_t; +struct elk_bblock_t; -struct backend_instruction : public exec_node { - bool is_3src(const struct brw_compiler *compiler) const; +struct elk_backend_instruction : public exec_node { + bool elk_is_3src(const struct elk_compiler *compiler) const; bool is_math() const; bool is_control_flow_begin() const; bool is_control_flow_end() const; @@ -113,9 +113,9 @@ struct backend_instruction : public exec_node { */ bool uses_indirect_addressing() const; - void remove(bblock_t *block, bool defer_later_block_ip_updates = false); - void insert_after(bblock_t *block, backend_instruction *inst); - void insert_before(bblock_t *block, backend_instruction *inst); + void remove(elk_bblock_t *block, bool defer_later_block_ip_updates = false); + void insert_after(elk_bblock_t *block, elk_backend_instruction *inst); + void insert_before(elk_bblock_t *block, elk_backend_instruction *inst); /** * True if the instruction has side effects other than writing to @@ -130,7 +130,7 @@ struct backend_instruction : public exec_node { */ bool is_volatile() const; #else -struct backend_instruction { +struct elk_backend_instruction { struct exec_node link; #endif /** @{ @@ -166,9 +166,9 @@ struct backend_instruction { uint32_t ex_desc; /**< SEND[S] extended message descriptor immediate */ unsigned size_written; /**< Data written to the destination register in bytes. */ - enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ - enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */ - enum brw_predicate predicate; + enum elk_opcode opcode; /* ELK_OPCODE_* or ELK_FS_OPCODE_* */ + enum elk_conditional_mod conditional_mod; /**< ELK_CONDITIONAL_* */ + enum elk_predicate predicate; bool predicate_inverse:1; bool writes_accumulator:1; /**< instruction implicitly writes accumulator */ bool force_writemask_all:1; @@ -177,13 +177,13 @@ struct backend_instruction { bool saturate:1; bool shadow_compare:1; bool check_tdr:1; /**< Only valid for SEND; turns it into a SENDC */ - bool send_has_side_effects:1; /**< Only valid for SHADER_OPCODE_SEND */ - bool send_is_volatile:1; /**< Only valid for SHADER_OPCODE_SEND */ - bool send_ex_desc_scratch:1; /**< Only valid for SHADER_OPCODE_SEND, use + bool send_has_side_effects:1; /**< Only valid for ELK_SHADER_OPCODE_SEND */ + bool send_is_volatile:1; /**< Only valid for ELK_SHADER_OPCODE_SEND */ + bool send_ex_desc_scratch:1; /**< Only valid for ELK_SHADER_OPCODE_SEND, use * the scratch surface offset to build * extended descriptor */ - bool send_ex_bso:1; /**< Only for SHADER_OPCODE_SEND, use extended bindless + bool send_ex_bso:1; /**< Only for ELK_SHADER_OPCODE_SEND, use extended bindless * surface offset (26bits instead of 20bits) */ bool predicate_trivial:1; /**< The predication mask applied to this diff --git a/src/intel/compiler/elk/elk_ir_analysis.h b/src/intel/compiler/elk/elk_ir_analysis.h index c9fe69be15a..a320bdc90dc 100644 --- a/src/intel/compiler/elk/elk_ir_analysis.h +++ b/src/intel/compiler/elk/elk_ir_analysis.h @@ -131,19 +131,19 @@ namespace elk { * is currently only used for validation in debug builds. */ template -class brw_analysis { +class elk_analysis { public: /** * Construct a program analysis. \p c is an arbitrary object * passed as argument to the constructor of the analysis result * object of type \p T. */ - brw_analysis(const C *c) : c(c), p(NULL) {} + elk_analysis(const C *c) : c(c), p(NULL) {} /** * Destroy a program analysis. */ - ~brw_analysis() + ~elk_analysis() { delete p; } @@ -167,7 +167,7 @@ public: const T & require() const { - return const_cast *>(this)->require(); + return const_cast *>(this)->require(); } /** diff --git a/src/intel/compiler/elk/elk_ir_fs.h b/src/intel/compiler/elk/elk_ir_fs.h index cef51228feb..45917252b93 100644 --- a/src/intel/compiler/elk/elk_ir_fs.h +++ b/src/intel/compiler/elk/elk_ir_fs.h @@ -27,21 +27,21 @@ #include "elk_shader.h" -class fs_inst; +class elk_fs_inst; -class fs_reg : public backend_reg { +class elk_fs_reg : public elk_backend_reg { public: - DECLARE_RALLOC_CXX_OPERATORS(fs_reg) + DECLARE_RALLOC_CXX_OPERATORS(elk_fs_reg) void init(); - fs_reg(); - fs_reg(struct ::brw_reg reg); - fs_reg(enum brw_reg_file file, unsigned nr); - fs_reg(enum brw_reg_file file, unsigned nr, enum brw_reg_type type); + elk_fs_reg(); + elk_fs_reg(struct ::elk_reg reg); + elk_fs_reg(enum elk_reg_file file, unsigned nr); + elk_fs_reg(enum elk_reg_file file, unsigned nr, enum elk_reg_type type); - bool equals(const fs_reg &r) const; - bool negative_equals(const fs_reg &r) const; + bool equals(const elk_fs_reg &r) const; + bool negative_equals(const elk_fs_reg &r) const; bool is_contiguous() const; /** @@ -54,23 +54,23 @@ public: uint8_t stride; }; -static inline fs_reg -negate(fs_reg reg) +static inline elk_fs_reg +negate(elk_fs_reg reg) { assert(reg.file != IMM); reg.negate = !reg.negate; return reg; } -static inline fs_reg -retype(fs_reg reg, enum brw_reg_type type) +static inline elk_fs_reg +retype(elk_fs_reg reg, enum elk_reg_type type) { reg.type = type; return reg; } -static inline fs_reg -byte_offset(fs_reg reg, unsigned delta) +static inline elk_fs_reg +byte_offset(elk_fs_reg reg, unsigned delta) { switch (reg.file) { case BAD_FILE: @@ -100,8 +100,8 @@ byte_offset(fs_reg reg, unsigned delta) return reg; } -static inline fs_reg -horiz_offset(const fs_reg ®, unsigned delta) +static inline elk_fs_reg +horiz_offset(const elk_fs_reg ®, unsigned delta) { switch (reg.file) { case BAD_FILE: @@ -136,8 +136,8 @@ horiz_offset(const fs_reg ®, unsigned delta) unreachable("Invalid register file"); } -static inline fs_reg -offset(fs_reg reg, unsigned width, unsigned delta) +static inline elk_fs_reg +offset(elk_fs_reg reg, unsigned width, unsigned delta) { switch (reg.file) { case BAD_FILE: @@ -159,15 +159,15 @@ offset(fs_reg reg, unsigned width, unsigned delta) * Get the scalar channel of \p reg given by \p idx and replicate it to all * channels of the result. */ -static inline fs_reg -component(fs_reg reg, unsigned idx) +static inline elk_fs_reg +component(elk_fs_reg reg, unsigned idx) { reg = horiz_offset(reg, idx); reg.stride = 0; if (reg.file == ARF || reg.file == FIXED_GRF) { - reg.vstride = BRW_VERTICAL_STRIDE_0; - reg.width = BRW_WIDTH_1; - reg.hstride = BRW_HORIZONTAL_STRIDE_0; + reg.vstride = ELK_VERTICAL_STRIDE_0; + reg.width = ELK_WIDTH_1; + reg.hstride = ELK_HORIZONTAL_STRIDE_0; } return reg; } @@ -181,7 +181,7 @@ component(fs_reg reg, unsigned idx) * address spaces, one for each allocation and input attribute respectively. */ static inline uint32_t -reg_space(const fs_reg &r) +reg_space(const elk_fs_reg &r) { return r.file << 16 | (r.file == VGRF || r.file == ATTR ? r.nr : 0); } @@ -191,7 +191,7 @@ reg_space(const fs_reg &r) * reg_space(). */ static inline unsigned -reg_offset(const fs_reg &r) +reg_offset(const elk_fs_reg &r) { return (r.file == VGRF || r.file == IMM || r.file == ATTR ? 0 : r.nr) * (r.file == UNIFORM ? 4 : REG_SIZE) + r.offset + @@ -204,7 +204,7 @@ reg_offset(const fs_reg &r) * one, or zero if components are tightly packed in the register file. */ static inline unsigned -reg_padding(const fs_reg &r) +reg_padding(const elk_fs_reg &r) { const unsigned stride = ((r.file != ARF && r.file != FIXED_GRF) ? r.stride : r.hstride == 0 ? 0 : @@ -214,11 +214,11 @@ reg_padding(const fs_reg &r) /* Do not call this directly. Call regions_overlap() instead. */ static inline bool -regions_overlap_MRF(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds) +regions_overlap_MRF(const elk_fs_reg &r, unsigned dr, const elk_fs_reg &s, unsigned ds) { - if (r.nr & BRW_MRF_COMPR4) { - fs_reg t = r; - t.nr &= ~BRW_MRF_COMPR4; + if (r.nr & ELK_MRF_COMPR4) { + elk_fs_reg t = r; + t.nr &= ~ELK_MRF_COMPR4; /* COMPR4 regions are translated by the hardware during decompression * into two separate half-regions 4 MRFs apart from each other. * @@ -229,7 +229,7 @@ regions_overlap_MRF(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds) */ return regions_overlap_MRF(s, ds, t, dr / 2) || regions_overlap_MRF(s, ds, byte_offset(t, 4 * REG_SIZE), dr / 2); - } else if (s.nr & BRW_MRF_COMPR4) { + } else if (s.nr & ELK_MRF_COMPR4) { return regions_overlap_MRF(s, ds, r, dr); } @@ -243,7 +243,7 @@ regions_overlap_MRF(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds) * spanning \p ds bytes. */ static inline bool -regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds) +regions_overlap(const elk_fs_reg &r, unsigned dr, const elk_fs_reg &s, unsigned ds) { if (r.file != s.file) return false; @@ -265,7 +265,7 @@ regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds) * [s.offset, s.offset + ds[. */ static inline bool -region_contained_in(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds) +region_contained_in(const elk_fs_reg &r, unsigned dr, const elk_fs_reg &s, unsigned ds) { return reg_space(r) == reg_space(s) && reg_offset(r) >= reg_offset(s) && @@ -278,15 +278,15 @@ region_contained_in(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds) * channels. */ static inline bool -is_periodic(const fs_reg ®, unsigned n) +is_periodic(const elk_fs_reg ®, unsigned n) { if (reg.file == BAD_FILE || reg.is_null()) { return true; } else if (reg.file == IMM) { - const unsigned period = (reg.type == BRW_REGISTER_TYPE_UV || - reg.type == BRW_REGISTER_TYPE_V ? 8 : - reg.type == BRW_REGISTER_TYPE_VF ? 4 : + const unsigned period = (reg.type == ELK_REGISTER_TYPE_UV || + reg.type == ELK_REGISTER_TYPE_V ? 8 : + reg.type == ELK_REGISTER_TYPE_VF ? 4 : 1); return n % period == 0; @@ -302,7 +302,7 @@ is_periodic(const fs_reg ®, unsigned n) } static inline bool -is_uniform(const fs_reg ®) +is_uniform(const elk_fs_reg ®) { return is_periodic(reg, 1); } @@ -310,8 +310,8 @@ is_uniform(const fs_reg ®) /** * Get the specified 8-component quarter of a register. */ -static inline fs_reg -quarter(const fs_reg ®, unsigned idx) +static inline elk_fs_reg +quarter(const elk_fs_reg ®, unsigned idx) { assert(idx < 4); return horiz_offset(reg, 8 * idx); @@ -321,8 +321,8 @@ quarter(const fs_reg ®, unsigned idx) * Reinterpret each channel of register \p reg as a vector of values of the * given smaller type and take the i-th subcomponent from each. */ -static inline fs_reg -subscript(fs_reg reg, brw_reg_type type, unsigned i) +static inline elk_fs_reg +subscript(elk_fs_reg reg, elk_reg_type type, unsigned i) { assert((i + 1) * type_sz(type) <= type_sz(reg.type)); @@ -349,37 +349,37 @@ subscript(fs_reg reg, brw_reg_type type, unsigned i) return byte_offset(retype(reg, type), i * type_sz(type)); } -static inline fs_reg -horiz_stride(fs_reg reg, unsigned s) +static inline elk_fs_reg +horiz_stride(elk_fs_reg reg, unsigned s) { reg.stride *= s; return reg; } -static const fs_reg reg_undef; +static const elk_fs_reg reg_undef; -class fs_inst : public backend_instruction { - fs_inst &operator=(const fs_inst &); +class elk_fs_inst : public elk_backend_instruction { + elk_fs_inst &operator=(const elk_fs_inst &); - void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst, - const fs_reg *src, unsigned sources); + void init(enum elk_opcode opcode, uint8_t exec_width, const elk_fs_reg &dst, + const elk_fs_reg *src, unsigned sources); public: - DECLARE_RALLOC_CXX_OPERATORS(fs_inst) + DECLARE_RALLOC_CXX_OPERATORS(elk_fs_inst) - fs_inst(); - fs_inst(enum opcode opcode, uint8_t exec_size); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0, const fs_reg &src1); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0, const fs_reg &src1, const fs_reg &src2); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg src[], unsigned sources); - fs_inst(const fs_inst &that); - ~fs_inst(); + elk_fs_inst(); + elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size); + elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst); + elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst, + const elk_fs_reg &src0); + elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst, + const elk_fs_reg &src0, const elk_fs_reg &src1); + elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst, + const elk_fs_reg &src0, const elk_fs_reg &src1, const elk_fs_reg &src2); + elk_fs_inst(enum elk_opcode opcode, uint8_t exec_size, const elk_fs_reg &dst, + const elk_fs_reg src[], unsigned sources); + elk_fs_inst(const elk_fs_inst &that); + ~elk_fs_inst(); void resize_sources(uint8_t num_sources); @@ -419,10 +419,10 @@ public: */ bool has_sampler_residency() const; - fs_reg dst; - fs_reg *src; + elk_fs_reg dst; + elk_fs_reg *src; - uint8_t sources; /**< Number of fs_reg sources. */ + uint8_t sources; /**< Number of elk_fs_reg sources. */ bool last_rt:1; bool pi_noperspective:1; /**< Pixel interpolator noperspective flag */ @@ -435,9 +435,9 @@ public: * Make the execution of \p inst dependent on the evaluation of a possibly * inverted predicate. */ -static inline fs_inst * -set_predicate_inv(enum brw_predicate pred, bool inverse, - fs_inst *inst) +static inline elk_fs_inst * +set_predicate_inv(enum elk_predicate pred, bool inverse, + elk_fs_inst *inst) { inst->predicate = pred; inst->predicate_inverse = inverse; @@ -447,8 +447,8 @@ set_predicate_inv(enum brw_predicate pred, bool inverse, /** * Make the execution of \p inst dependent on the evaluation of a predicate. */ -static inline fs_inst * -set_predicate(enum brw_predicate pred, fs_inst *inst) +static inline elk_fs_inst * +set_predicate(enum elk_predicate pred, elk_fs_inst *inst) { return set_predicate_inv(pred, false, inst); } @@ -457,8 +457,8 @@ set_predicate(enum brw_predicate pred, fs_inst *inst) * Write the result of evaluating the condition given by \p mod to a flag * register. */ -static inline fs_inst * -set_condmod(enum brw_conditional_mod mod, fs_inst *inst) +static inline elk_fs_inst * +set_condmod(enum elk_conditional_mod mod, elk_fs_inst *inst) { inst->conditional_mod = mod; return inst; @@ -468,8 +468,8 @@ set_condmod(enum brw_conditional_mod mod, fs_inst *inst) * Clamp the result of \p inst to the saturation range of its destination * datatype. */ -static inline fs_inst * -set_saturate(bool saturate, fs_inst *inst) +static inline elk_fs_inst * +set_saturate(bool saturate, elk_fs_inst *inst) { inst->saturate = saturate; return inst; @@ -482,7 +482,7 @@ set_saturate(bool saturate, fs_inst *inst) * UNIFORM and IMM files and 32B for all other files. */ inline unsigned -regs_written(const fs_inst *inst) +regs_written(const elk_fs_inst *inst) { assert(inst->dst.file != UNIFORM && inst->dst.file != IMM); return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + @@ -498,7 +498,7 @@ regs_written(const fs_inst *inst) * UNIFORM files and 32B for all other files. */ inline unsigned -regs_read(const fs_inst *inst, unsigned i) +regs_read(const elk_fs_inst *inst, unsigned i) { if (inst->src[i].file == IMM) return 1; @@ -510,27 +510,27 @@ regs_read(const fs_inst *inst, unsigned i) reg_size); } -static inline enum brw_reg_type -get_exec_type(const fs_inst *inst) +static inline enum elk_reg_type +get_exec_type(const elk_fs_inst *inst) { - brw_reg_type exec_type = BRW_REGISTER_TYPE_B; + elk_reg_type exec_type = ELK_REGISTER_TYPE_B; for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file != BAD_FILE && !inst->is_control_source(i)) { - const brw_reg_type t = get_exec_type(inst->src[i].type); + const elk_reg_type t = get_exec_type(inst->src[i].type); if (type_sz(t) > type_sz(exec_type)) exec_type = t; else if (type_sz(t) == type_sz(exec_type) && - brw_reg_type_is_floating_point(t)) + elk_reg_type_is_floating_point(t)) exec_type = t; } } - if (exec_type == BRW_REGISTER_TYPE_B) + if (exec_type == ELK_REGISTER_TYPE_B) exec_type = inst->dst.type; - assert(exec_type != BRW_REGISTER_TYPE_B); + assert(exec_type != ELK_REGISTER_TYPE_B); /* Promotion of the execution type to 32-bit for conversions from or to * half-float seems to be consistent with the following text from the @@ -547,23 +547,23 @@ get_exec_type(const fs_inst *inst) */ if (type_sz(exec_type) == 2 && inst->dst.type != exec_type) { - if (exec_type == BRW_REGISTER_TYPE_HF) - exec_type = BRW_REGISTER_TYPE_F; - else if (inst->dst.type == BRW_REGISTER_TYPE_HF) - exec_type = BRW_REGISTER_TYPE_D; + if (exec_type == ELK_REGISTER_TYPE_HF) + exec_type = ELK_REGISTER_TYPE_F; + else if (inst->dst.type == ELK_REGISTER_TYPE_HF) + exec_type = ELK_REGISTER_TYPE_D; } return exec_type; } static inline unsigned -get_exec_type_size(const fs_inst *inst) +get_exec_type_size(const elk_fs_inst *inst) { return type_sz(get_exec_type(inst)); } static inline bool -is_send(const fs_inst *inst) +is_send(const elk_fs_inst *inst) { return inst->mlen || inst->is_send_from_grf(); } @@ -573,13 +573,13 @@ is_send(const fs_inst *inst) * assumed to complete in-order. */ static inline bool -is_unordered(const intel_device_info *devinfo, const fs_inst *inst) +is_unordered(const intel_device_info *devinfo, const elk_fs_inst *inst) { return is_send(inst) || (devinfo->ver < 20 && inst->is_math()) || - inst->opcode == BRW_OPCODE_DPAS || + inst->opcode == ELK_OPCODE_DPAS || (devinfo->has_64bit_float_via_math_pipe && - (get_exec_type(inst) == BRW_REGISTER_TYPE_DF || - inst->dst.type == BRW_REGISTER_TYPE_DF)); + (get_exec_type(inst) == ELK_REGISTER_TYPE_DF || + inst->dst.type == ELK_REGISTER_TYPE_DF)); } /** @@ -597,19 +597,19 @@ is_unordered(const intel_device_info *devinfo, const fs_inst *inst) */ static inline bool has_dst_aligned_region_restriction(const intel_device_info *devinfo, - const fs_inst *inst, - brw_reg_type dst_type) + const elk_fs_inst *inst, + elk_reg_type dst_type) { - const brw_reg_type exec_type = get_exec_type(inst); + const elk_reg_type exec_type = get_exec_type(inst); /* Even though the hardware spec claims that "integer DWord multiply" * operations are restricted, empirical evidence and the behavior of the * simulator suggest that only 32x32-bit integer multiplication is * restricted. */ - const bool is_dword_multiply = !brw_reg_type_is_floating_point(exec_type) && - ((inst->opcode == BRW_OPCODE_MUL && + const bool is_dword_multiply = !elk_reg_type_is_floating_point(exec_type) && + ((inst->opcode == ELK_OPCODE_MUL && MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4) || - (inst->opcode == BRW_OPCODE_MAD && + (inst->opcode == ELK_OPCODE_MAD && MIN2(type_sz(inst->src[1].type), type_sz(inst->src[2].type)) >= 4)); if (type_sz(dst_type) > 4 || type_sz(exec_type) > 4 || @@ -618,7 +618,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo, intel_device_info_is_9lp(devinfo) || devinfo->verx10 >= 125; - else if (brw_reg_type_is_floating_point(dst_type)) + else if (elk_reg_type_is_floating_point(dst_type)) return devinfo->verx10 >= 125; else @@ -627,7 +627,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo, static inline bool has_dst_aligned_region_restriction(const intel_device_info *devinfo, - const fs_inst *inst) + const elk_fs_inst *inst) { return has_dst_aligned_region_restriction(devinfo, inst, inst->dst.type); } @@ -642,9 +642,9 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo, * multiple virtual registers in any order is allowed. */ inline bool -is_copy_payload(brw_reg_file file, const fs_inst *inst) +is_copy_payload(elk_reg_file file, const elk_fs_inst *inst) { - if (inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD || + if (inst->opcode != ELK_SHADER_OPCODE_LOAD_PAYLOAD || inst->is_partial_write() || inst->saturate || inst->dst.file != VGRF) return false; @@ -671,9 +671,9 @@ is_copy_payload(brw_reg_file file, const fs_inst *inst) * destination without any reordering. */ inline bool -is_identity_payload(brw_reg_file file, const fs_inst *inst) { +is_identity_payload(elk_reg_file file, const elk_fs_inst *inst) { if (is_copy_payload(file, inst)) { - fs_reg reg = inst->src[0]; + elk_fs_reg reg = inst->src[0]; for (unsigned i = 0; i < inst->sources; i++) { reg.type = inst->src[i].type; @@ -700,7 +700,7 @@ is_identity_payload(brw_reg_file file, const fs_inst *inst) { * instructions. */ inline bool -is_multi_copy_payload(const fs_inst *inst) { +is_multi_copy_payload(const elk_fs_inst *inst) { if (is_copy_payload(VGRF, inst)) { for (unsigned i = 0; i < inst->sources; i++) { if (inst->src[i].nr != inst->src[0].nr) @@ -724,7 +724,7 @@ is_multi_copy_payload(const fs_inst *inst) { * instruction. */ inline bool -is_coalescing_payload(const elk::simple_allocator &alloc, const fs_inst *inst) +is_coalescing_payload(const elk::simple_allocator &alloc, const elk_fs_inst *inst) { return is_identity_payload(VGRF, inst) && inst->src[0].offset == 0 && @@ -732,6 +732,6 @@ is_coalescing_payload(const elk::simple_allocator &alloc, const fs_inst *inst) } bool -has_bank_conflict(const struct brw_isa_info *isa, const fs_inst *inst); +elk_has_bank_conflict(const struct elk_isa_info *isa, const elk_fs_inst *inst); #endif diff --git a/src/intel/compiler/elk/elk_ir_performance.cpp b/src/intel/compiler/elk/elk_ir_performance.cpp index 4aa7c18330e..05b2dfd3744 100644 --- a/src/intel/compiler/elk/elk_ir_performance.cpp +++ b/src/intel/compiler/elk/elk_ir_performance.cpp @@ -120,17 +120,17 @@ namespace { * instructions. */ struct instruction_info { - instruction_info(const struct brw_isa_info *isa, const fs_inst *inst) : + instruction_info(const struct elk_isa_info *isa, const elk_fs_inst *inst) : isa(isa), devinfo(isa->devinfo), op(inst->opcode), td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)), tx(get_exec_type(inst)), sx(0), ss(0), - sc(has_bank_conflict(isa, inst) ? sd : 0), + sc(elk_has_bank_conflict(isa, inst) ? sd : 0), desc(inst->desc), sfid(inst->sfid) { /* We typically want the maximum source size, except for split send * messages which require the total size. */ - if (inst->opcode == SHADER_OPCODE_SEND) { + if (inst->opcode == ELK_SHADER_OPCODE_SEND) { ss = DIV_ROUND_UP(inst->size_read(2), REG_SIZE) + DIV_ROUND_UP(inst->size_read(3), REG_SIZE); } else { @@ -144,15 +144,15 @@ namespace { /* 32x32 integer multiplication has half the usual ALU throughput. * Treat it as double-precision. */ - if ((inst->opcode == BRW_OPCODE_MUL || inst->opcode == BRW_OPCODE_MAD) && - !brw_reg_type_is_floating_point(tx) && type_sz(tx) == 4 && + if ((inst->opcode == ELK_OPCODE_MUL || inst->opcode == ELK_OPCODE_MAD) && + !elk_reg_type_is_floating_point(tx) && type_sz(tx) == 4 && type_sz(inst->src[0].type) == type_sz(inst->src[1].type)) - tx = brw_int_type(8, tx == BRW_REGISTER_TYPE_D); + tx = elk_int_type(8, tx == ELK_REGISTER_TYPE_D); - rcount = inst->opcode == BRW_OPCODE_DPAS ? inst->rcount : 0; + rcount = inst->opcode == ELK_OPCODE_DPAS ? inst->rcount : 0; } - instruction_info(const struct brw_isa_info *isa, + instruction_info(const struct elk_isa_info *isa, const vec4_instruction *inst) : isa(isa), devinfo(isa->devinfo), op(inst->opcode), td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)), @@ -169,24 +169,24 @@ namespace { /* 32x32 integer multiplication has half the usual ALU throughput. * Treat it as double-precision. */ - if ((inst->opcode == BRW_OPCODE_MUL || inst->opcode == BRW_OPCODE_MAD) && - !brw_reg_type_is_floating_point(tx) && type_sz(tx) == 4 && + if ((inst->opcode == ELK_OPCODE_MUL || inst->opcode == ELK_OPCODE_MAD) && + !elk_reg_type_is_floating_point(tx) && type_sz(tx) == 4 && type_sz(inst->src[0].type) == type_sz(inst->src[1].type)) - tx = brw_int_type(8, tx == BRW_REGISTER_TYPE_D); + tx = elk_int_type(8, tx == ELK_REGISTER_TYPE_D); } /** ISA encoding information */ - const struct brw_isa_info *isa; + const struct elk_isa_info *isa; /** Device information. */ const struct intel_device_info *devinfo; /** Instruction opcode. */ - opcode op; + elk_opcode op; /** Destination type. */ - brw_reg_type td; + elk_reg_type td; /** Destination size in GRF units. */ unsigned sd; /** Execution type. */ - brw_reg_type tx; + elk_reg_type tx; /** Execution size in GRF units. */ unsigned sx; /** Source size. */ @@ -299,71 +299,71 @@ namespace { const struct intel_device_info *devinfo = info.devinfo; switch (info.op) { - case BRW_OPCODE_SYNC: - case BRW_OPCODE_SEL: - case BRW_OPCODE_NOT: - case BRW_OPCODE_AND: - case BRW_OPCODE_OR: - case BRW_OPCODE_XOR: - case BRW_OPCODE_SHR: - case BRW_OPCODE_SHL: - case BRW_OPCODE_DIM: - case BRW_OPCODE_ASR: - case BRW_OPCODE_CMPN: - case BRW_OPCODE_F16TO32: - case BRW_OPCODE_BFREV: - case BRW_OPCODE_BFI1: - case BRW_OPCODE_AVG: - case BRW_OPCODE_FRC: - case BRW_OPCODE_RNDU: - case BRW_OPCODE_RNDD: - case BRW_OPCODE_RNDE: - case BRW_OPCODE_RNDZ: - case BRW_OPCODE_MAC: - case BRW_OPCODE_MACH: - case BRW_OPCODE_LZD: - case BRW_OPCODE_FBH: - case BRW_OPCODE_FBL: - case BRW_OPCODE_CBIT: - case BRW_OPCODE_ADDC: - case BRW_OPCODE_ROR: - case BRW_OPCODE_ROL: - case BRW_OPCODE_SUBB: - case BRW_OPCODE_SAD2: - case BRW_OPCODE_SADA2: - case BRW_OPCODE_LINE: - case BRW_OPCODE_NOP: - case SHADER_OPCODE_CLUSTER_BROADCAST: - case SHADER_OPCODE_SCRATCH_HEADER: - case FS_OPCODE_DDX_COARSE: - case FS_OPCODE_DDX_FINE: - case FS_OPCODE_DDY_COARSE: - case FS_OPCODE_PIXEL_X: - case FS_OPCODE_PIXEL_Y: - case FS_OPCODE_SET_SAMPLE_ID: - case VEC4_OPCODE_MOV_BYTES: - case VEC4_OPCODE_UNPACK_UNIFORM: - case VEC4_OPCODE_DOUBLE_TO_F32: - case VEC4_OPCODE_DOUBLE_TO_D32: - case VEC4_OPCODE_DOUBLE_TO_U32: - case VEC4_OPCODE_TO_DOUBLE: - case VEC4_OPCODE_PICK_LOW_32BIT: - case VEC4_OPCODE_PICK_HIGH_32BIT: - case VEC4_OPCODE_SET_LOW_32BIT: - case VEC4_OPCODE_SET_HIGH_32BIT: - case VEC4_OPCODE_ZERO_OOB_PUSH_REGS: - case GS_OPCODE_SET_DWORD_2: - case GS_OPCODE_SET_WRITE_OFFSET: - case GS_OPCODE_SET_VERTEX_COUNT: - case GS_OPCODE_PREPARE_CHANNEL_MASKS: - case GS_OPCODE_SET_CHANNEL_MASKS: - case GS_OPCODE_GET_INSTANCE_ID: - case GS_OPCODE_SET_PRIMITIVE_ID: - case GS_OPCODE_SVB_SET_DST_INDEX: - case TCS_OPCODE_SRC0_010_IS_ZERO: - case TCS_OPCODE_GET_PRIMITIVE_ID: - case TES_OPCODE_GET_PRIMITIVE_ID: - case SHADER_OPCODE_READ_SR_REG: + case ELK_OPCODE_SYNC: + case ELK_OPCODE_SEL: + case ELK_OPCODE_NOT: + case ELK_OPCODE_AND: + case ELK_OPCODE_OR: + case ELK_OPCODE_XOR: + case ELK_OPCODE_SHR: + case ELK_OPCODE_SHL: + case ELK_OPCODE_DIM: + case ELK_OPCODE_ASR: + case ELK_OPCODE_CMPN: + case ELK_OPCODE_F16TO32: + case ELK_OPCODE_BFREV: + case ELK_OPCODE_BFI1: + case ELK_OPCODE_AVG: + case ELK_OPCODE_FRC: + case ELK_OPCODE_RNDU: + case ELK_OPCODE_RNDD: + case ELK_OPCODE_RNDE: + case ELK_OPCODE_RNDZ: + case ELK_OPCODE_MAC: + case ELK_OPCODE_MACH: + case ELK_OPCODE_LZD: + case ELK_OPCODE_FBH: + case ELK_OPCODE_FBL: + case ELK_OPCODE_CBIT: + case ELK_OPCODE_ADDC: + case ELK_OPCODE_ROR: + case ELK_OPCODE_ROL: + case ELK_OPCODE_SUBB: + case ELK_OPCODE_SAD2: + case ELK_OPCODE_SADA2: + case ELK_OPCODE_LINE: + case ELK_OPCODE_NOP: + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: + case ELK_SHADER_OPCODE_SCRATCH_HEADER: + case ELK_FS_OPCODE_DDX_COARSE: + case ELK_FS_OPCODE_DDX_FINE: + case ELK_FS_OPCODE_DDY_COARSE: + case ELK_FS_OPCODE_PIXEL_X: + case ELK_FS_OPCODE_PIXEL_Y: + case ELK_FS_OPCODE_SET_SAMPLE_ID: + case ELK_VEC4_OPCODE_MOV_BYTES: + case ELK_VEC4_OPCODE_UNPACK_UNIFORM: + case ELK_VEC4_OPCODE_DOUBLE_TO_F32: + case ELK_VEC4_OPCODE_DOUBLE_TO_D32: + case ELK_VEC4_OPCODE_DOUBLE_TO_U32: + case ELK_VEC4_OPCODE_TO_DOUBLE: + case ELK_VEC4_OPCODE_PICK_LOW_32BIT: + case ELK_VEC4_OPCODE_PICK_HIGH_32BIT: + case ELK_VEC4_OPCODE_SET_LOW_32BIT: + case ELK_VEC4_OPCODE_SET_HIGH_32BIT: + case ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS: + case ELK_GS_OPCODE_SET_DWORD_2: + case ELK_GS_OPCODE_SET_WRITE_OFFSET: + case ELK_GS_OPCODE_SET_VERTEX_COUNT: + case ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS: + case ELK_GS_OPCODE_SET_CHANNEL_MASKS: + case ELK_GS_OPCODE_GET_INSTANCE_ID: + case ELK_GS_OPCODE_SET_PRIMITIVE_ID: + case ELK_GS_OPCODE_SVB_SET_DST_INDEX: + case ELK_TCS_OPCODE_SRC0_010_IS_ZERO: + case ELK_TCS_OPCODE_GET_PRIMITIVE_ID: + case ELK_TES_OPCODE_GET_PRIMITIVE_ID: + case ELK_SHADER_OPCODE_READ_SR_REG: if (devinfo->ver >= 11) { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 10, 6 /* XXX */, 14, 0, 0); @@ -382,13 +382,13 @@ namespace { 0, 12, 8 /* XXX */, 18, 0, 0); } - case BRW_OPCODE_MOV: - case BRW_OPCODE_CMP: - case BRW_OPCODE_ADD: - case BRW_OPCODE_ADD3: - case BRW_OPCODE_MUL: - case SHADER_OPCODE_MOV_RELOC_IMM: - case VEC4_OPCODE_MOV_FOR_SCRATCH: + case ELK_OPCODE_MOV: + case ELK_OPCODE_CMP: + case ELK_OPCODE_ADD: + case ELK_OPCODE_ADD3: + case ELK_OPCODE_MUL: + case ELK_SHADER_OPCODE_MOV_RELOC_IMM: + case ELK_VEC4_OPCODE_MOV_FOR_SCRATCH: if (devinfo->ver >= 11) { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 10, 6, 14, 0, 0); @@ -400,14 +400,14 @@ namespace { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 8, 4, 12, 0, 0); } else if (devinfo->verx10 >= 75) { - if (info.tx == BRW_REGISTER_TYPE_F) + if (info.tx == ELK_REGISTER_TYPE_F) return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 12, 8 /* XXX */, 18, 0, 0); else return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 10, 6 /* XXX */, 16, 0, 0); } else if (devinfo->ver >= 7) { - if (info.tx == BRW_REGISTER_TYPE_F) + if (info.tx == ELK_REGISTER_TYPE_F) return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 14, 10 /* XXX */, 20, 0, 0); else @@ -420,9 +420,9 @@ namespace { 0, 0); } - case BRW_OPCODE_BFE: - case BRW_OPCODE_BFI2: - case BRW_OPCODE_CSEL: + case ELK_OPCODE_BFE: + case ELK_OPCODE_BFI2: + case ELK_OPCODE_CSEL: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 0, 2, 1, 0, 2, 0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0); @@ -438,7 +438,7 @@ namespace { else abort(); - case BRW_OPCODE_MAD: + case ELK_OPCODE_MAD: if (devinfo->ver >= 11) { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 1, 0, 2, 0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0); @@ -450,14 +450,14 @@ namespace { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 1, 0, 2, 0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0); } else if (devinfo->verx10 >= 75) { - if (info.tx == BRW_REGISTER_TYPE_F) + if (info.tx == ELK_REGISTER_TYPE_F) return calculate_desc(info, EU_UNIT_FPU, 0, 2, 1, 0, 2, 0, 12, 8 /* XXX */, 18, 0, 0); else return calculate_desc(info, EU_UNIT_FPU, 0, 2, 1, 0, 2, 0, 10, 6 /* XXX */, 16, 0, 0); } else if (devinfo->ver >= 7) { - if (info.tx == BRW_REGISTER_TYPE_F) + if (info.tx == ELK_REGISTER_TYPE_F) return calculate_desc(info, EU_UNIT_FPU, 0, 2, 1, 0, 2, 0, 14, 10 /* XXX */, 20, 0, 0); else @@ -472,7 +472,7 @@ namespace { abort(); } - case BRW_OPCODE_F32TO16: + case ELK_OPCODE_F32TO16: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 0, 4, 0, 0, 4, 0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0); @@ -488,10 +488,10 @@ namespace { else abort(); - case BRW_OPCODE_DP4: - case BRW_OPCODE_DPH: - case BRW_OPCODE_DP3: - case BRW_OPCODE_DP2: + case ELK_OPCODE_DP4: + case ELK_OPCODE_DPH: + case ELK_OPCODE_DP3: + case ELK_OPCODE_DP2: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0); @@ -502,14 +502,14 @@ namespace { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0); - case BRW_OPCODE_DP4A: + case ELK_OPCODE_DP4A: if (devinfo->ver >= 12) return calculate_desc(info, EU_UNIT_FPU, 0, 2, 1, 0, 2, 0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0); else abort(); - case BRW_OPCODE_DPAS: { + case ELK_OPCODE_DPAS: { unsigned ld; switch (info.rcount) { @@ -535,25 +535,25 @@ namespace { abort(); } - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: if (devinfo->ver >= 6) { switch (info.op) { - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_EM, -2, 4, 0, 0, 4, 0, 16, 0, 0, 0, 0); @@ -564,7 +564,7 @@ namespace { return calculate_desc(info, EU_UNIT_EM, 0, 2, 0, 0, 2, 0, 14, 0, 0, 0, 0); - case SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_POW: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_EM, -2, 4, 0, 0, 8, 0, 24, 0, 0, 0, 0); @@ -575,8 +575,8 @@ namespace { return calculate_desc(info, EU_UNIT_EM, 0, 2, 0, 0, 4, 0, 22, 0, 0, 0, 0); - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: return calculate_desc(info, EU_UNIT_EM, 2, 0, 0, 26, 0, 0, 28 /* XXX */, 0, 0, 0, 0); @@ -585,31 +585,31 @@ namespace { } } else { switch (info.op) { - case SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RCP: return calculate_desc(info, EU_UNIT_EM, 2, 0, 0, 0, 8, 0, 22, 0, 0, 0, 8); - case SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_RSQ: return calculate_desc(info, EU_UNIT_EM, 2, 0, 0, 0, 16, 0, 44, 0, 0, 0, 8); - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_LOG2: return calculate_desc(info, EU_UNIT_EM, 2, 0, 0, 0, 24, 0, 66, 0, 0, 0, 8); - case SHADER_OPCODE_INT_REMAINDER: - case SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_EXP2: return calculate_desc(info, EU_UNIT_EM, 2, 0, 0, 0, 32, 0, 88, 0, 0, 0, 8); - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: return calculate_desc(info, EU_UNIT_EM, 2, 0, 0, 0, 48, 0, 132, 0, 0, 0, 8); - case SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_POW: return calculate_desc(info, EU_UNIT_EM, 2, 0, 0, 0, 64, 0, 176, 0, 0, 0, 8); @@ -618,7 +618,7 @@ namespace { } } - case BRW_OPCODE_DO: + case ELK_OPCODE_DO: if (devinfo->ver >= 6) return calculate_desc(info, EU_UNIT_NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); @@ -626,13 +626,13 @@ namespace { return calculate_desc(info, EU_UNIT_NULL, 2 /* XXX */, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - case BRW_OPCODE_IF: - case BRW_OPCODE_ELSE: - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_WHILE: - case BRW_OPCODE_BREAK: - case BRW_OPCODE_CONTINUE: - case BRW_OPCODE_HALT: + case ELK_OPCODE_IF: + case ELK_OPCODE_ELSE: + case ELK_OPCODE_ENDIF: + case ELK_OPCODE_WHILE: + case ELK_OPCODE_BREAK: + case ELK_OPCODE_CONTINUE: + case ELK_OPCODE_HALT: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_NULL, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); @@ -643,7 +643,7 @@ namespace { return calculate_desc(info, EU_UNIT_NULL, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - case FS_OPCODE_LINTERP: + case ELK_FS_OPCODE_LINTERP: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_FPU, 0, 4, 0, 0, 4, 0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0); @@ -654,7 +654,7 @@ namespace { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0); - case BRW_OPCODE_LRP: + case ELK_OPCODE_LRP: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_FPU, 0, 4, 1, 0, 4, 0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0); @@ -667,7 +667,7 @@ namespace { else abort(); - case FS_OPCODE_PACK_HALF_2x16_SPLIT: + case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 20, 6, 0, 0, 6, 0, 10 /* XXX */, 6 /* XXX */, @@ -687,7 +687,7 @@ namespace { else abort(); - case SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_MOV_INDIRECT: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 34, 0, 0, 34, 0, 0, 10 /* XXX */, 6 /* XXX */, @@ -705,7 +705,7 @@ namespace { 0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */, 0, 0); - case SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_BROADCAST: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 20 /* XXX */, 0, 0, 4, 0, 0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0); @@ -721,8 +721,8 @@ namespace { else abort(); - case SHADER_OPCODE_FIND_LIVE_CHANNEL: - case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: + case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL: + case ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 2, 0, 0, 2, 0, 0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0); @@ -738,8 +738,8 @@ namespace { else abort(); - case SHADER_OPCODE_RND_MODE: - case SHADER_OPCODE_FLOAT_CONTROL_MODE: + case ELK_SHADER_OPCODE_RND_MODE: + case ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 24 /* XXX */, 0, 0, 4 /* XXX */, 0, @@ -759,7 +759,7 @@ namespace { else abort(); - case SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_SHUFFLE: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 44 /* XXX */, 0, 0, 44 /* XXX */, 0, @@ -783,7 +783,7 @@ namespace { else abort(); - case SHADER_OPCODE_SEL_EXEC: + case ELK_SHADER_OPCODE_SEL_EXEC: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 10 /* XXX */, 4 /* XXX */, 0, 0, 4 /* XXX */, @@ -805,7 +805,7 @@ namespace { 0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */, 0, 0); - case SHADER_OPCODE_QUAD_SWIZZLE: + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 0 /* XXX */, 8 /* XXX */, 0, 0, 8 /* XXX */, @@ -827,7 +827,7 @@ namespace { 0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */, 0, 0); - case FS_OPCODE_DDY_FINE: + case ELK_FS_OPCODE_DDY_FINE: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 0, 14, 0, 0, 4, 0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0); @@ -841,7 +841,7 @@ namespace { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 14, 10 /* XXX */, 20 /* XXX */, 0, 0); - case FS_OPCODE_LOAD_LIVE_CHANNELS: + case ELK_FS_OPCODE_LOAD_LIVE_CHANNELS: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 2 /* XXX */, 0, 0, 2 /* XXX */, 0, @@ -853,7 +853,7 @@ namespace { else abort(); - case VEC4_OPCODE_PACK_BYTES: + case ELK_VEC4_OPCODE_PACK_BYTES: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_FPU, 4 /* XXX */, 0, 0, 4 /* XXX */, 0, @@ -870,11 +870,11 @@ namespace { 0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */, 0, 0); - case VS_OPCODE_UNPACK_FLAGS_SIMD4X2: - case TCS_OPCODE_GET_INSTANCE_ID: - case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: - case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: - case TES_OPCODE_CREATE_INPUT_READ_HEADER: + case ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2: + case ELK_TCS_OPCODE_GET_INSTANCE_ID: + case ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: + case ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: + case ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_FPU, 22 /* XXX */, 0, 0, 6 /* XXX */, 0, @@ -891,8 +891,8 @@ namespace { 0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */, 0, 0); - case GS_OPCODE_FF_SYNC_SET_PRIMITIVES: - case TCS_OPCODE_CREATE_BARRIER_HEADER: + case ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES: + case ELK_TCS_OPCODE_CREATE_BARRIER_HEADER: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_FPU, 32 /* XXX */, 0, 0, 8 /* XXX */, 0, @@ -911,7 +911,7 @@ namespace { else abort(); - case TES_OPCODE_ADD_INDIRECT_URB_OFFSET: + case ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET: if (devinfo->ver >= 8) return calculate_desc(info, EU_UNIT_FPU, 12 /* XXX */, 0, 0, 4 /* XXX */, 0, @@ -930,42 +930,42 @@ namespace { else abort(); - case SHADER_OPCODE_TEX: - case FS_OPCODE_TXB: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_LZ: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXL_LZ: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_UMS: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_LOD: - case SHADER_OPCODE_GET_BUFFER_SIZE: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_SAMPLEINFO: - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: + case ELK_SHADER_OPCODE_TEX: + case ELK_FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL_LZ: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_UMS: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_GET_BUFFER_SIZE: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_SAMPLEINFO: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: return calculate_desc(info, EU_UNIT_SAMPLER, 2, 0, 0, 0, 16 /* XXX */, 8 /* XXX */, 750 /* XXX */, 0, 0, 2 /* XXX */, 0); - case VEC4_OPCODE_URB_READ: - case VEC4_VS_OPCODE_URB_WRITE: - case VEC4_GS_OPCODE_URB_WRITE: - case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE: - case GS_OPCODE_THREAD_END: - case GS_OPCODE_FF_SYNC: - case VEC4_TCS_OPCODE_URB_WRITE: - case TCS_OPCODE_RELEASE_INPUT: - case TCS_OPCODE_THREAD_END: + case ELK_VEC4_OPCODE_URB_READ: + case ELK_VEC4_VS_OPCODE_URB_WRITE: + case ELK_VEC4_GS_OPCODE_URB_WRITE: + case ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE: + case ELK_GS_OPCODE_THREAD_END: + case ELK_GS_OPCODE_FF_SYNC: + case ELK_VEC4_TCS_OPCODE_URB_WRITE: + case ELK_TCS_OPCODE_RELEASE_INPUT: + case ELK_TCS_OPCODE_THREAD_END: return calculate_desc(info, EU_UNIT_URB, 2, 0, 0, 0, 6 /* XXX */, 32 /* XXX */, 200 /* XXX */, 0, 0, 0, 0); - case SHADER_OPCODE_MEMORY_FENCE: - case SHADER_OPCODE_INTERLOCK: + case ELK_SHADER_OPCODE_MEMORY_FENCE: + case ELK_SHADER_OPCODE_INTERLOCK: switch (info.sfid) { case GFX6_SFID_DATAPORT_RENDER_CACHE: if (devinfo->ver >= 7) @@ -974,7 +974,7 @@ namespace { else abort(); - case BRW_SFID_URB: + case ELK_SFID_URB: case GFX7_SFID_DATAPORT_DATA_CACHE: case GFX12_SFID_SLM: case GFX12_SFID_TGM: @@ -990,13 +990,13 @@ namespace { abort(); } - case SHADER_OPCODE_GFX4_SCRATCH_READ: - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: - case SHADER_OPCODE_GFX7_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_SHADER_OPCODE_GFX7_SCRATCH_READ: return calculate_desc(info, EU_UNIT_DP_DC, 2, 0, 0, 0, 8 /* XXX */, 10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0); - case VEC4_OPCODE_UNTYPED_ATOMIC: + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: if (devinfo->ver >= 7) return calculate_desc(info, EU_UNIT_DP_DC, 2, 0, 0, 30 /* XXX */, 400 /* XXX */, @@ -1005,8 +1005,8 @@ namespace { else abort(); - case VEC4_OPCODE_UNTYPED_SURFACE_READ: - case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE: if (devinfo->ver >= 7) return calculate_desc(info, EU_UNIT_DP_DC, 2, 0, 0, 0, 20 /* XXX */, @@ -1015,13 +1015,13 @@ namespace { else abort(); - case FS_OPCODE_FB_WRITE: - case FS_OPCODE_FB_READ: - case FS_OPCODE_REP_FB_WRITE: + case ELK_FS_OPCODE_FB_WRITE: + case ELK_FS_OPCODE_FB_READ: + case ELK_FS_OPCODE_REP_FB_WRITE: return calculate_desc(info, EU_UNIT_DP_RC, 2, 0, 0, 0, 450 /* XXX */, 10 /* XXX */, 300 /* XXX */, 0, 0, 0, 0); - case GS_OPCODE_SVB_WRITE: + case ELK_GS_OPCODE_SVB_WRITE: if (devinfo->ver >= 6) return calculate_desc(info, EU_UNIT_DP_RC, 2 /* XXX */, 0, 0, 0, 450 /* XXX */, @@ -1030,25 +1030,25 @@ namespace { else abort(); - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: return calculate_desc(info, EU_UNIT_DP_CC, 2, 0, 0, 0, 16 /* XXX */, 10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0); - case VS_OPCODE_PULL_CONSTANT_LOAD: - case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: return calculate_desc(info, EU_UNIT_SAMPLER, 2, 0, 0, 0, 16, 8, 750, 0, 0, 2, 0); - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: if (devinfo->ver >= 7) return calculate_desc(info, EU_UNIT_PI, 2, 0, 0, 14 /* XXX */, 0, 0, 90 /* XXX */, 0, 0, 0, 0); else abort(); - case SHADER_OPCODE_BARRIER: + case ELK_SHADER_OPCODE_BARRIER: if (devinfo->ver >= 7) return calculate_desc(info, EU_UNIT_GATEWAY, 90 /* XXX */, 0, 0, 0 /* XXX */, 0, @@ -1056,18 +1056,18 @@ namespace { else abort(); - case CS_OPCODE_CS_TERMINATE: + case ELK_CS_OPCODE_CS_TERMINATE: if (devinfo->ver >= 7) return calculate_desc(info, EU_UNIT_SPAWNER, 2, 0, 0, 0 /* XXX */, 0, 10 /* XXX */, 0, 0, 0, 0, 0); else abort(); - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: switch (info.sfid) { case GFX6_SFID_DATAPORT_CONSTANT_CACHE: if (devinfo->ver >= 7) { - /* See FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD */ + /* See ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD */ return calculate_desc(info, EU_UNIT_DP_CC, 2, 0, 0, 0, 16 /* XXX */, 10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0); } else { @@ -1075,7 +1075,7 @@ namespace { } case GFX6_SFID_DATAPORT_RENDER_CACHE: if (devinfo->ver >= 7) { - switch (brw_dp_desc_msg_type(devinfo, info.desc)) { + switch (elk_dp_desc_msg_type(devinfo, info.desc)) { case GFX7_DATAPORT_RC_TYPED_ATOMIC_OP: return calculate_desc(info, EU_UNIT_DP_RC, 2, 0, 0, 30 /* XXX */, 450 /* XXX */, @@ -1094,7 +1094,7 @@ namespace { } else { abort(); } - case BRW_SFID_SAMPLER: { + case ELK_SFID_SAMPLER: { if (devinfo->ver >= 6) return calculate_desc(info, EU_UNIT_SAMPLER, 2, 0, 0, 0, 16, 8, 750, 0, 0, 2, 0); @@ -1104,7 +1104,7 @@ namespace { case GFX7_SFID_DATAPORT_DATA_CACHE: case HSW_SFID_DATAPORT_DATA_CACHE_1: if (devinfo->verx10 >= 75) { - switch (brw_dp_desc_msg_type(devinfo, info.desc)) { + switch (elk_dp_desc_msg_type(devinfo, info.desc)) { case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP: case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2: case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2: @@ -1121,7 +1121,7 @@ namespace { 0, 0); } } else if (devinfo->ver >= 7) { - switch (brw_dp_desc_msg_type(devinfo, info.desc)) { + switch (elk_dp_desc_msg_type(devinfo, info.desc)) { case GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP: return calculate_desc(info, EU_UNIT_DP_DC, 2, 0, 0, 30 /* XXX */, 400 /* XXX */, @@ -1185,7 +1185,7 @@ namespace { abort(); } - case BRW_SFID_URB: + case ELK_SFID_URB: return calculate_desc(info, EU_UNIT_URB, 2, 0, 0, 0, 6 /* XXX */, 32 /* XXX */, 200 /* XXX */, 0, 0, 0, 0); @@ -1193,9 +1193,9 @@ namespace { abort(); } - case SHADER_OPCODE_UNDEF: - case SHADER_OPCODE_HALT_TARGET: - case FS_OPCODE_SCHEDULING_FENCE: + case ELK_SHADER_OPCODE_UNDEF: + case ELK_SHADER_OPCODE_HALT_TARGET: + case ELK_FS_OPCODE_SCHEDULING_FENCE: return calculate_desc(info, EU_UNIT_NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); @@ -1271,10 +1271,10 @@ namespace { } /** - * Return the dependency ID of a backend_reg, offset by \p delta GRFs. + * Return the dependency ID of a elk_backend_reg, offset by \p delta GRFs. */ enum intel_eu_dependency_id - reg_dependency_id(const intel_device_info *devinfo, const backend_reg &r, + reg_dependency_id(const intel_device_info *devinfo, const elk_backend_reg &r, const int delta) { if (r.file == VGRF) { @@ -1294,19 +1294,19 @@ namespace { return intel_eu_dependency_id(EU_DEPENDENCY_ID_GRF0 + i); } else if (r.file == MRF && devinfo->ver < 7) { - const unsigned i = (r.nr & ~BRW_MRF_COMPR4) + + const unsigned i = (r.nr & ~ELK_MRF_COMPR4) + r.offset / REG_SIZE + delta; assert(i < EU_DEPENDENCY_ID_ADDR0 - EU_DEPENDENCY_ID_MRF0); return intel_eu_dependency_id(EU_DEPENDENCY_ID_MRF0 + i); - } else if (r.file == ARF && r.nr >= BRW_ARF_ADDRESS && - r.nr < BRW_ARF_ACCUMULATOR) { + } else if (r.file == ARF && r.nr >= ELK_ARF_ADDRESS && + r.nr < ELK_ARF_ACCUMULATOR) { assert(delta == 0); return EU_DEPENDENCY_ID_ADDR0; - } else if (r.file == ARF && r.nr >= BRW_ARF_ACCUMULATOR && - r.nr < BRW_ARF_FLAG) { - const unsigned i = r.nr - BRW_ARF_ACCUMULATOR + delta; + } else if (r.file == ARF && r.nr >= ELK_ARF_ACCUMULATOR && + r.nr < ELK_ARF_FLAG) { + const unsigned i = r.nr - ELK_ARF_ACCUMULATOR + delta; assert(i < EU_DEPENDENCY_ID_FLAG0 - EU_DEPENDENCY_ID_ACCUM0); return intel_eu_dependency_id(EU_DEPENDENCY_ID_ACCUM0 + i); @@ -1363,13 +1363,13 @@ namespace { */ unsigned accum_reg_of_channel(const intel_device_info *devinfo, - const backend_instruction *inst, - brw_reg_type tx, unsigned i) + const elk_backend_instruction *inst, + elk_reg_type tx, unsigned i) { assert(inst->reads_accumulator_implicitly() || inst->writes_accumulator_implicitly(devinfo)); const unsigned offset = (inst->group + i) * type_sz(tx) * - (devinfo->ver < 7 || brw_reg_type_is_floating_point(tx) ? 1 : 2); + (devinfo->ver < 7 || elk_reg_type_is_floating_point(tx) ? 1 : 2); return offset / (reg_unit(devinfo) * REG_SIZE) % 2; } @@ -1377,11 +1377,11 @@ namespace { * Model the performance behavior of an FS back-end instruction. */ void - issue_fs_inst(state &st, const struct brw_isa_info *isa, - const backend_instruction *be_inst) + issue_fs_inst(state &st, const struct elk_isa_info *isa, + const elk_backend_instruction *be_inst) { const struct intel_device_info *devinfo = isa->devinfo; - const fs_inst *inst = static_cast(be_inst); + const elk_fs_inst *inst = static_cast(be_inst); const instruction_info info(isa, inst); const perf_desc perf = instruction_desc(info); @@ -1397,14 +1397,14 @@ namespace { j <= accum_reg_of_channel(devinfo, inst, info.tx, inst->exec_size - 1); j++) stall_on_dependency( - st, reg_dependency_id(devinfo, brw_acc_reg(8), j)); + st, reg_dependency_id(devinfo, elk_acc_reg(8), j)); } if (is_send(inst) && inst->base_mrf != -1) { for (unsigned j = 0; j < inst->mlen; j++) stall_on_dependency( st, reg_dependency_id( - devinfo, brw_uvec_mrf(8, inst->base_mrf, 0), j)); + devinfo, elk_uvec_mrf(8, inst->base_mrf, 0), j)); } if (const unsigned mask = inst->flags_read(devinfo)) { @@ -1427,7 +1427,7 @@ namespace { j <= accum_reg_of_channel(devinfo, inst, info.tx, inst->exec_size - 1); j++) stall_on_dependency( - st, reg_dependency_id(devinfo, brw_acc_reg(8), j)); + st, reg_dependency_id(devinfo, elk_acc_reg(8), j)); } if (const unsigned mask = inst->flags_written(devinfo)) { @@ -1461,7 +1461,7 @@ namespace { if (is_send(inst) && inst->base_mrf != -1) { for (unsigned j = 0; j < inst->mlen; j++) mark_read_dependency(st, perf, - reg_dependency_id(devinfo, brw_uvec_mrf(8, inst->base_mrf, 0), j)); + reg_dependency_id(devinfo, elk_uvec_mrf(8, inst->base_mrf, 0), j)); } /* Mark any destination dependencies. */ @@ -1477,7 +1477,7 @@ namespace { j <= accum_reg_of_channel(devinfo, inst, info.tx, inst->exec_size - 1); j++) mark_write_dependency(st, perf, - reg_dependency_id(devinfo, brw_acc_reg(8), j)); + reg_dependency_id(devinfo, elk_acc_reg(8), j)); } if (const unsigned mask = inst->flags_written(devinfo)) { @@ -1498,8 +1498,8 @@ namespace { * Model the performance behavior of a VEC4 back-end instruction. */ void - issue_vec4_instruction(state &st, const struct brw_isa_info *isa, - const backend_instruction *be_inst) + issue_vec4_instruction(state &st, const struct elk_isa_info *isa, + const elk_backend_instruction *be_inst) { const struct intel_device_info *devinfo = isa->devinfo; const vec4_instruction *inst = @@ -1519,14 +1519,14 @@ namespace { j <= accum_reg_of_channel(devinfo, inst, info.tx, inst->exec_size - 1); j++) stall_on_dependency( - st, reg_dependency_id(devinfo, brw_acc_reg(8), j)); + st, reg_dependency_id(devinfo, elk_acc_reg(8), j)); } if (inst->base_mrf != -1) { for (unsigned j = 0; j < inst->mlen; j++) stall_on_dependency( st, reg_dependency_id( - devinfo, brw_uvec_mrf(8, inst->base_mrf, 0), j)); + devinfo, elk_uvec_mrf(8, inst->base_mrf, 0), j)); } if (inst->reads_flag()) @@ -1545,7 +1545,7 @@ namespace { j <= accum_reg_of_channel(devinfo, inst, info.tx, inst->exec_size - 1); j++) stall_on_dependency( - st, reg_dependency_id(devinfo, brw_acc_reg(8), j)); + st, reg_dependency_id(devinfo, elk_acc_reg(8), j)); } if (inst->writes_flag(devinfo)) @@ -1567,7 +1567,7 @@ namespace { if (inst->base_mrf != -1) { for (unsigned j = 0; j < inst->mlen; j++) mark_read_dependency(st, perf, - reg_dependency_id(devinfo, brw_uvec_mrf(8, inst->base_mrf, 0), j)); + reg_dependency_id(devinfo, elk_uvec_mrf(8, inst->base_mrf, 0), j)); } /* Mark any destination dependencies. */ @@ -1583,7 +1583,7 @@ namespace { j <= accum_reg_of_channel(devinfo, inst, info.tx, inst->exec_size - 1); j++) mark_write_dependency(st, perf, - reg_dependency_id(devinfo, brw_acc_reg(8), j)); + reg_dependency_id(devinfo, elk_acc_reg(8), j)); } if (inst->writes_flag(devinfo)) @@ -1608,10 +1608,10 @@ namespace { * Estimate the performance of the specified shader. */ void - calculate_performance(performance &p, const backend_shader *s, + calculate_performance(performance &p, const elk_backend_shader *s, void (*issue_instruction)( - state &, const struct brw_isa_info *, - const backend_instruction *), + state &, const struct elk_isa_info *, + const elk_backend_instruction *), unsigned dispatch_width) { /* XXX - Note that the previous version of this code used worst-case @@ -1649,21 +1649,21 @@ namespace { foreach_block(block, s->cfg) { const unsigned elapsed0 = elapsed; - foreach_inst_in_block(backend_instruction, inst, block) { + foreach_inst_in_block(elk_backend_instruction, inst, block) { const unsigned clock0 = st.unit_ready[EU_UNIT_FE]; issue_instruction(st, &s->compiler->isa, inst); - if (inst->opcode == SHADER_OPCODE_HALT_TARGET && halt_count) + if (inst->opcode == ELK_SHADER_OPCODE_HALT_TARGET && halt_count) st.weight /= discard_weight; elapsed += (st.unit_ready[EU_UNIT_FE] - clock0) * st.weight; - if (inst->opcode == BRW_OPCODE_DO) + if (inst->opcode == ELK_OPCODE_DO) st.weight *= loop_weight; - else if (inst->opcode == BRW_OPCODE_WHILE) + else if (inst->opcode == ELK_OPCODE_WHILE) st.weight /= loop_weight; - else if (inst->opcode == BRW_OPCODE_HALT && !halt_count++) + else if (inst->opcode == ELK_OPCODE_HALT && !halt_count++) st.weight *= discard_weight; } @@ -1675,7 +1675,7 @@ namespace { } } -elk::performance::performance(const fs_visitor *v) : +elk::performance::performance(const elk_fs_visitor *v) : block_latency(new unsigned[v->cfg->num_blocks]) { calculate_performance(*this, v, issue_fs_inst, v->dispatch_width); diff --git a/src/intel/compiler/elk/elk_ir_performance.h b/src/intel/compiler/elk/elk_ir_performance.h index 70400889467..c3147574d25 100644 --- a/src/intel/compiler/elk/elk_ir_performance.h +++ b/src/intel/compiler/elk/elk_ir_performance.h @@ -25,7 +25,7 @@ #ifndef ELK_IR_PERFORMANCE_H #define ELK_IR_PERFORMANCE_H -class fs_visitor; +class elk_fs_visitor; namespace elk { class vec4_visitor; @@ -35,7 +35,7 @@ namespace elk { * analysis. */ struct performance { - performance(const fs_visitor *v); + performance(const elk_fs_visitor *v); performance(const vec4_visitor *v); ~performance(); @@ -47,7 +47,7 @@ namespace elk { } bool - validate(const backend_shader *) const + validate(const elk_backend_shader *) const { return true; } diff --git a/src/intel/compiler/elk/elk_ir_vec4.h b/src/intel/compiler/elk/elk_ir_vec4.h index c0fd0298a9e..74a2813930c 100644 --- a/src/intel/compiler/elk/elk_ir_vec4.h +++ b/src/intel/compiler/elk/elk_ir_vec4.h @@ -31,16 +31,16 @@ namespace elk { class dst_reg; -class src_reg : public backend_reg +class src_reg : public elk_backend_reg { public: DECLARE_RALLOC_CXX_OPERATORS(src_reg) void init(); - src_reg(enum brw_reg_file file, int nr, const glsl_type *type); + src_reg(enum elk_reg_file file, int nr, const glsl_type *type); src_reg(); - src_reg(struct ::brw_reg reg); + src_reg(struct ::elk_reg reg); bool equals(const src_reg &r) const; bool negative_equals(const src_reg &r) const; @@ -54,7 +54,7 @@ public: }; static inline src_reg -retype(src_reg reg, enum brw_reg_type type) +retype(src_reg reg, enum elk_reg_type type) { reg.type = type; return reg; @@ -63,7 +63,7 @@ retype(src_reg reg, enum brw_reg_type type) namespace detail { static inline void -add_byte_offset(backend_reg *reg, unsigned bytes) +add_byte_offset(elk_backend_reg *reg, unsigned bytes) { switch (reg->file) { case BAD_FILE: @@ -119,15 +119,15 @@ horiz_offset(src_reg reg, unsigned delta) /** * Reswizzle a given source register. - * \sa brw_swizzle(). + * \sa elk_swizzle(). */ static inline src_reg swizzle(src_reg reg, unsigned swizzle) { if (reg.file == IMM) - reg.ud = brw_swizzle_immediate(reg.type, reg.ud, swizzle); + reg.ud = elk_swizzle_immediate(reg.type, reg.ud, swizzle); else - reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle); + reg.swizzle = elk_compose_swizzle(swizzle, reg.swizzle); return reg; } @@ -147,7 +147,7 @@ is_uniform(const src_reg ®) (!reg.reladdr || is_uniform(*reg.reladdr)); } -class dst_reg : public backend_reg +class dst_reg : public elk_backend_reg { public: DECLARE_RALLOC_CXX_OPERATORS(dst_reg) @@ -155,12 +155,12 @@ public: void init(); dst_reg(); - dst_reg(enum brw_reg_file file, int nr); - dst_reg(enum brw_reg_file file, int nr, const glsl_type *type, + dst_reg(enum elk_reg_file file, int nr); + dst_reg(enum elk_reg_file file, int nr, const glsl_type *type, unsigned writemask); - dst_reg(enum brw_reg_file file, int nr, brw_reg_type type, + dst_reg(enum elk_reg_file file, int nr, elk_reg_type type, unsigned writemask); - dst_reg(struct ::brw_reg reg); + dst_reg(struct ::elk_reg reg); dst_reg(class vec4_visitor *v, const struct glsl_type *type); explicit dst_reg(const src_reg ®); @@ -171,7 +171,7 @@ public: }; static inline dst_reg -retype(dst_reg reg, enum brw_reg_type type) +retype(dst_reg reg, enum elk_reg_type type) { reg.type = type; return reg; @@ -219,7 +219,7 @@ writemask(dst_reg reg, unsigned mask) * spaces, one for each VGRF allocation. */ static inline uint32_t -reg_space(const backend_reg &r) +reg_space(const elk_backend_reg &r) { return r.file << 16 | (r.file == VGRF ? r.nr : 0); } @@ -229,7 +229,7 @@ reg_space(const backend_reg &r) * reg_space(). */ static inline unsigned -reg_offset(const backend_reg &r) +reg_offset(const elk_backend_reg &r) { return (r.file == VGRF || r.file == IMM ? 0 : r.nr) * (r.file == UNIFORM ? 16 : REG_SIZE) + r.offset + @@ -242,21 +242,21 @@ reg_offset(const backend_reg &r) * spanning \p ds bytes. */ static inline bool -regions_overlap(const backend_reg &r, unsigned dr, - const backend_reg &s, unsigned ds) +regions_overlap(const elk_backend_reg &r, unsigned dr, + const elk_backend_reg &s, unsigned ds) { - if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) { + if (r.file == MRF && (r.nr & ELK_MRF_COMPR4)) { /* COMPR4 regions are translated by the hardware during decompression * into two separate half-regions 4 MRFs apart from each other. */ - backend_reg t0 = r; - t0.nr &= ~BRW_MRF_COMPR4; - backend_reg t1 = t0; + elk_backend_reg t0 = r; + t0.nr &= ~ELK_MRF_COMPR4; + elk_backend_reg t1 = t0; t1.offset += 4 * REG_SIZE; return regions_overlap(t0, dr / 2, s, ds) || regions_overlap(t1, dr / 2, s, ds); - } else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) { + } else if (s.file == MRF && (s.nr & ELK_MRF_COMPR4)) { return regions_overlap(s, ds, r, dr); } else { @@ -266,11 +266,11 @@ regions_overlap(const backend_reg &r, unsigned dr, } } -class vec4_instruction : public backend_instruction { +class vec4_instruction : public elk_backend_instruction { public: DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction) - vec4_instruction(enum opcode opcode, + vec4_instruction(enum elk_opcode opcode, const dst_reg &dst = dst_reg(), const src_reg &src0 = src_reg(), const src_reg &src1 = src_reg(), @@ -279,7 +279,7 @@ public: dst_reg dst; src_reg src[3]; - enum brw_urb_write_flags urb_write_flags; + enum elk_urb_write_flags urb_write_flags; unsigned sol_binding; /**< gfx6: SOL binding table index */ bool sol_final_write; /**< gfx6: send commit message */ @@ -300,30 +300,30 @@ public: bool is_align1_partial_write() { - return opcode == VEC4_OPCODE_SET_LOW_32BIT || - opcode == VEC4_OPCODE_SET_HIGH_32BIT; + return opcode == ELK_VEC4_OPCODE_SET_LOW_32BIT || + opcode == ELK_VEC4_OPCODE_SET_HIGH_32BIT; } bool reads_flag() const { - return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2; + return predicate || opcode == ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2; } bool reads_flag(unsigned c) { - if (opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2) + if (opcode == ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2) return true; switch (predicate) { - case BRW_PREDICATE_NONE: + case ELK_PREDICATE_NONE: return false; - case BRW_PREDICATE_ALIGN16_REPLICATE_X: + case ELK_PREDICATE_ALIGN16_REPLICATE_X: return c == 0; - case BRW_PREDICATE_ALIGN16_REPLICATE_Y: + case ELK_PREDICATE_ALIGN16_REPLICATE_Y: return c == 1; - case BRW_PREDICATE_ALIGN16_REPLICATE_Z: + case ELK_PREDICATE_ALIGN16_REPLICATE_Z: return c == 2; - case BRW_PREDICATE_ALIGN16_REPLICATE_W: + case ELK_PREDICATE_ALIGN16_REPLICATE_W: return c == 3; default: return true; @@ -332,31 +332,31 @@ public: bool writes_flag(const intel_device_info *devinfo) const { - return (conditional_mod && ((opcode != BRW_OPCODE_SEL || devinfo->ver <= 5) && - opcode != BRW_OPCODE_CSEL && - opcode != BRW_OPCODE_IF && - opcode != BRW_OPCODE_WHILE)); + return (conditional_mod && ((opcode != ELK_OPCODE_SEL || devinfo->ver <= 5) && + opcode != ELK_OPCODE_CSEL && + opcode != ELK_OPCODE_IF && + opcode != ELK_OPCODE_WHILE)); } bool reads_g0_implicitly() const { switch (opcode) { - case SHADER_OPCODE_TEX: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_SAMPLEINFO: - case VS_OPCODE_PULL_CONSTANT_LOAD: - case GS_OPCODE_SET_PRIMITIVE_ID: - case GS_OPCODE_GET_INSTANCE_ID: - case SHADER_OPCODE_GFX4_SCRATCH_READ: - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_SAMPLEINFO: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD: + case ELK_GS_OPCODE_SET_PRIMITIVE_ID: + case ELK_GS_OPCODE_GET_INSTANCE_ID: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: return true; default: return false; @@ -369,7 +369,7 @@ public: * inverted predicate. */ inline vec4_instruction * -set_predicate_inv(enum brw_predicate pred, bool inverse, +set_predicate_inv(enum elk_predicate pred, bool inverse, vec4_instruction *inst) { inst->predicate = pred; @@ -381,7 +381,7 @@ set_predicate_inv(enum brw_predicate pred, bool inverse, * Make the execution of \p inst dependent on the evaluation of a predicate. */ inline vec4_instruction * -set_predicate(enum brw_predicate pred, vec4_instruction *inst) +set_predicate(enum elk_predicate pred, vec4_instruction *inst) { return set_predicate_inv(pred, false, inst); } @@ -391,7 +391,7 @@ set_predicate(enum brw_predicate pred, vec4_instruction *inst) * register. */ inline vec4_instruction * -set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst) +set_condmod(enum elk_conditional_mod mod, vec4_instruction *inst) { inst->conditional_mod = mod; return inst; @@ -437,29 +437,29 @@ regs_read(const vec4_instruction *inst, unsigned i) reg_size); } -static inline enum brw_reg_type +static inline enum elk_reg_type get_exec_type(const vec4_instruction *inst) { - enum brw_reg_type exec_type = BRW_REGISTER_TYPE_B; + enum elk_reg_type exec_type = ELK_REGISTER_TYPE_B; for (int i = 0; i < 3; i++) { if (inst->src[i].file != BAD_FILE) { - const brw_reg_type t = get_exec_type(brw_reg_type(inst->src[i].type)); + const elk_reg_type t = get_exec_type(elk_reg_type(inst->src[i].type)); if (type_sz(t) > type_sz(exec_type)) exec_type = t; else if (type_sz(t) == type_sz(exec_type) && - brw_reg_type_is_floating_point(t)) + elk_reg_type_is_floating_point(t)) exec_type = t; } } - if (exec_type == BRW_REGISTER_TYPE_B) + if (exec_type == ELK_REGISTER_TYPE_B) exec_type = inst->dst.type; /* TODO: We need to handle half-float conversions. */ - assert(exec_type != BRW_REGISTER_TYPE_HF || - inst->dst.type == BRW_REGISTER_TYPE_HF); - assert(exec_type != BRW_REGISTER_TYPE_B); + assert(exec_type != ELK_REGISTER_TYPE_HF || + inst->dst.type == ELK_REGISTER_TYPE_HF); + assert(exec_type != ELK_REGISTER_TYPE_B); return exec_type; } diff --git a/src/intel/compiler/elk/elk_isa_info.h b/src/intel/compiler/elk/elk_isa_info.h index ebba0c2a847..0fe38e73282 100644 --- a/src/intel/compiler/elk/elk_isa_info.h +++ b/src/intel/compiler/elk/elk_isa_info.h @@ -30,22 +30,22 @@ extern "C" { #endif -struct opcode_desc; +struct elk_opcode_desc; -struct brw_isa_info { +struct elk_isa_info { const struct intel_device_info *devinfo; - /* A mapping from enum opcode to the corresponding opcode_desc */ - const struct opcode_desc *ir_to_descs[NUM_BRW_OPCODES]; + /* A mapping from enum elk_opcode to the corresponding opcode_desc */ + const struct elk_opcode_desc *ir_to_descs[NUM_ELK_OPCODES]; /** A mapping from a HW opcode encoding to the corresponding opcode_desc */ - const struct opcode_desc *hw_to_descs[128]; + const struct elk_opcode_desc *hw_to_descs[128]; }; -void brw_init_isa_info(struct brw_isa_info *isa, +void elk_init_isa_info(struct elk_isa_info *isa, const struct intel_device_info *devinfo); -struct opcode_desc { +struct elk_opcode_desc { unsigned ir; unsigned hw; const char *name; @@ -54,29 +54,29 @@ struct opcode_desc { int gfx_vers; }; -const struct opcode_desc * -brw_opcode_desc(const struct brw_isa_info *isa, enum opcode opcode); +const struct elk_opcode_desc * +elk_opcode_desc(const struct elk_isa_info *isa, enum elk_opcode opcode); -const struct opcode_desc * -brw_opcode_desc_from_hw(const struct brw_isa_info *isa, unsigned hw); +const struct elk_opcode_desc * +elk_opcode_desc_from_hw(const struct elk_isa_info *isa, unsigned hw); static inline unsigned -brw_opcode_encode(const struct brw_isa_info *isa, enum opcode opcode) +elk_opcode_encode(const struct elk_isa_info *isa, enum elk_opcode opcode) { - return brw_opcode_desc(isa, opcode)->hw; + return elk_opcode_desc(isa, opcode)->hw; } -static inline enum opcode -brw_opcode_decode(const struct brw_isa_info *isa, unsigned hw) +static inline enum elk_opcode +elk_opcode_decode(const struct elk_isa_info *isa, unsigned hw) { - const struct opcode_desc *desc = brw_opcode_desc_from_hw(isa, hw); - return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL; + const struct elk_opcode_desc *desc = elk_opcode_desc_from_hw(isa, hw); + return desc ? (enum elk_opcode)desc->ir : ELK_OPCODE_ILLEGAL; } static inline bool -is_3src(const struct brw_isa_info *isa, enum opcode opcode) +elk_is_3src(const struct elk_isa_info *isa, enum elk_opcode opcode) { - const struct opcode_desc *desc = brw_opcode_desc(isa, opcode); + const struct elk_opcode_desc *desc = elk_opcode_desc(isa, opcode); return desc && desc->nsrc == 3; } diff --git a/src/intel/compiler/elk/elk_lex.l b/src/intel/compiler/elk/elk_lex.l index 8a764e93627..25930c9be3b 100644 --- a/src/intel/compiler/elk/elk_lex.l +++ b/src/intel/compiler/elk/elk_lex.l @@ -51,122 +51,122 @@ extern char *input_filename; null { BEGIN(REG); return NULL_TOKEN; } /* Opcodes */ -add { yylval.integer = BRW_OPCODE_ADD; return ADD; } -add3 { yylval.integer = BRW_OPCODE_ADD3; return ADD3; } -addc { yylval.integer = BRW_OPCODE_ADDC; return ADDC; } -and { yylval.integer = BRW_OPCODE_AND; return AND; } -asr { yylval.integer = BRW_OPCODE_ASR; return ASR; } -avg { yylval.integer = BRW_OPCODE_AVG; return AVG; } -bfe { yylval.integer = BRW_OPCODE_BFE; return BFE; } -bfi1 { yylval.integer = BRW_OPCODE_BFI1; return BFI1; } -bfi2 { yylval.integer = BRW_OPCODE_BFI2; return BFI2; } -bfrev { yylval.integer = BRW_OPCODE_BFREV; return BFREV; } -brc { yylval.integer = BRW_OPCODE_BRC; return BRC; } -brd { yylval.integer = BRW_OPCODE_BRD; return BRD; } -break { yylval.integer = BRW_OPCODE_BREAK; return BREAK; } -call { yylval.integer = BRW_OPCODE_CALL; return CALL; } -calla { yylval.integer = BRW_OPCODE_CALLA; return CALLA; } -case { yylval.integer = BRW_OPCODE_CASE; return CASE; } -cbit { yylval.integer = BRW_OPCODE_CBIT; return CBIT; } -cmp { yylval.integer = BRW_OPCODE_CMP; return CMP; } -cmpn { yylval.integer = BRW_OPCODE_CMPN; return CMPN; } -cont { yylval.integer = BRW_OPCODE_CONTINUE; return CONT; } -csel { yylval.integer = BRW_OPCODE_CSEL; return CSEL; } -dim { yylval.integer = BRW_OPCODE_DIM; return DIM; } -do { yylval.integer = BRW_OPCODE_DO; return DO; } -dp2 { yylval.integer = BRW_OPCODE_DP2; return DP2; } -dp3 { yylval.integer = BRW_OPCODE_DP3; return DP3; } -dp4 { yylval.integer = BRW_OPCODE_DP4; return DP4; } -dp4a { yylval.integer = BRW_OPCODE_DP4A; return DP4A; } -dph { yylval.integer = BRW_OPCODE_DPH; return DPH; } -else { yylval.integer = BRW_OPCODE_ELSE; return ELSE; } -endif { yylval.integer = BRW_OPCODE_ENDIF; return ENDIF; } -f16to32 { yylval.integer = BRW_OPCODE_F16TO32; return F16TO32; } -f32to16 { yylval.integer = BRW_OPCODE_F32TO16; return F32TO16; } -fbh { yylval.integer = BRW_OPCODE_FBH; return FBH; } -fbl { yylval.integer = BRW_OPCODE_FBL; return FBL; } -fork { yylval.integer = BRW_OPCODE_FORK; return FORK; } -frc { yylval.integer = BRW_OPCODE_FRC; return FRC; } -goto { yylval.integer = BRW_OPCODE_GOTO; return GOTO; } -halt { yylval.integer = BRW_OPCODE_HALT; return HALT; } -if { yylval.integer = BRW_OPCODE_IF; return IF; } -iff { yylval.integer = BRW_OPCODE_IFF; return IFF; } -illegal { yylval.integer = BRW_OPCODE_ILLEGAL; return ILLEGAL; } -jmpi { yylval.integer = BRW_OPCODE_JMPI; return JMPI; } -line { yylval.integer = BRW_OPCODE_LINE; return LINE; } -lrp { yylval.integer = BRW_OPCODE_LRP; return LRP; } -lzd { yylval.integer = BRW_OPCODE_LZD; return LZD; } -mac { yylval.integer = BRW_OPCODE_MAC; return MAC; } -mach { yylval.integer = BRW_OPCODE_MACH; return MACH; } -mad { yylval.integer = BRW_OPCODE_MAD; return MAD; } -madm { yylval.integer = BRW_OPCODE_MADM; return MADM; } -mov { yylval.integer = BRW_OPCODE_MOV; return MOV; } -movi { yylval.integer = BRW_OPCODE_MOVI; return MOVI; } -mul { yylval.integer = BRW_OPCODE_MUL; return MUL; } -mrest { yylval.integer = BRW_OPCODE_MREST; return MREST; } -msave { yylval.integer = BRW_OPCODE_MSAVE; return MSAVE; } -nenop { yylval.integer = BRW_OPCODE_NENOP; return NENOP; } -nop { yylval.integer = BRW_OPCODE_NOP; return NOP; } -not { yylval.integer = BRW_OPCODE_NOT; return NOT; } -or { yylval.integer = BRW_OPCODE_OR; return OR; } -pln { yylval.integer = BRW_OPCODE_PLN; return PLN; } -pop { yylval.integer = BRW_OPCODE_POP; return POP; } -push { yylval.integer = BRW_OPCODE_PUSH; return PUSH; } -ret { yylval.integer = BRW_OPCODE_RET; return RET; } -rndd { yylval.integer = BRW_OPCODE_RNDD; return RNDD; } -rnde { yylval.integer = BRW_OPCODE_RNDE; return RNDE; } -rndu { yylval.integer = BRW_OPCODE_RNDU; return RNDU; } -rndz { yylval.integer = BRW_OPCODE_RNDZ; return RNDZ; } -rol { yylval.integer = BRW_OPCODE_ROL; return ROL; } -ror { yylval.integer = BRW_OPCODE_ROR; return ROR; } -sad2 { yylval.integer = BRW_OPCODE_SAD2; return SAD2; } -sada2 { yylval.integer = BRW_OPCODE_SADA2; return SADA2; } -sel { yylval.integer = BRW_OPCODE_SEL; return SEL; } +add { yylval.integer = ELK_OPCODE_ADD; return ADD; } +add3 { yylval.integer = ELK_OPCODE_ADD3; return ADD3; } +addc { yylval.integer = ELK_OPCODE_ADDC; return ADDC; } +and { yylval.integer = ELK_OPCODE_AND; return AND; } +asr { yylval.integer = ELK_OPCODE_ASR; return ASR; } +avg { yylval.integer = ELK_OPCODE_AVG; return AVG; } +bfe { yylval.integer = ELK_OPCODE_BFE; return BFE; } +bfi1 { yylval.integer = ELK_OPCODE_BFI1; return BFI1; } +bfi2 { yylval.integer = ELK_OPCODE_BFI2; return BFI2; } +bfrev { yylval.integer = ELK_OPCODE_BFREV; return BFREV; } +brc { yylval.integer = ELK_OPCODE_BRC; return BRC; } +brd { yylval.integer = ELK_OPCODE_BRD; return BRD; } +break { yylval.integer = ELK_OPCODE_BREAK; return BREAK; } +call { yylval.integer = ELK_OPCODE_CALL; return CALL; } +calla { yylval.integer = ELK_OPCODE_CALLA; return CALLA; } +case { yylval.integer = ELK_OPCODE_CASE; return CASE; } +cbit { yylval.integer = ELK_OPCODE_CBIT; return CBIT; } +cmp { yylval.integer = ELK_OPCODE_CMP; return CMP; } +cmpn { yylval.integer = ELK_OPCODE_CMPN; return CMPN; } +cont { yylval.integer = ELK_OPCODE_CONTINUE; return CONT; } +csel { yylval.integer = ELK_OPCODE_CSEL; return CSEL; } +dim { yylval.integer = ELK_OPCODE_DIM; return DIM; } +do { yylval.integer = ELK_OPCODE_DO; return DO; } +dp2 { yylval.integer = ELK_OPCODE_DP2; return DP2; } +dp3 { yylval.integer = ELK_OPCODE_DP3; return DP3; } +dp4 { yylval.integer = ELK_OPCODE_DP4; return DP4; } +dp4a { yylval.integer = ELK_OPCODE_DP4A; return DP4A; } +dph { yylval.integer = ELK_OPCODE_DPH; return DPH; } +else { yylval.integer = ELK_OPCODE_ELSE; return ELSE; } +endif { yylval.integer = ELK_OPCODE_ENDIF; return ENDIF; } +f16to32 { yylval.integer = ELK_OPCODE_F16TO32; return F16TO32; } +f32to16 { yylval.integer = ELK_OPCODE_F32TO16; return F32TO16; } +fbh { yylval.integer = ELK_OPCODE_FBH; return FBH; } +fbl { yylval.integer = ELK_OPCODE_FBL; return FBL; } +fork { yylval.integer = ELK_OPCODE_FORK; return FORK; } +frc { yylval.integer = ELK_OPCODE_FRC; return FRC; } +goto { yylval.integer = ELK_OPCODE_GOTO; return GOTO; } +halt { yylval.integer = ELK_OPCODE_HALT; return HALT; } +if { yylval.integer = ELK_OPCODE_IF; return IF; } +iff { yylval.integer = ELK_OPCODE_IFF; return IFF; } +illegal { yylval.integer = ELK_OPCODE_ILLEGAL; return ILLEGAL; } +jmpi { yylval.integer = ELK_OPCODE_JMPI; return JMPI; } +line { yylval.integer = ELK_OPCODE_LINE; return LINE; } +lrp { yylval.integer = ELK_OPCODE_LRP; return LRP; } +lzd { yylval.integer = ELK_OPCODE_LZD; return LZD; } +mac { yylval.integer = ELK_OPCODE_MAC; return MAC; } +mach { yylval.integer = ELK_OPCODE_MACH; return MACH; } +mad { yylval.integer = ELK_OPCODE_MAD; return MAD; } +madm { yylval.integer = ELK_OPCODE_MADM; return MADM; } +mov { yylval.integer = ELK_OPCODE_MOV; return MOV; } +movi { yylval.integer = ELK_OPCODE_MOVI; return MOVI; } +mul { yylval.integer = ELK_OPCODE_MUL; return MUL; } +mrest { yylval.integer = ELK_OPCODE_MREST; return MREST; } +msave { yylval.integer = ELK_OPCODE_MSAVE; return MSAVE; } +nenop { yylval.integer = ELK_OPCODE_NENOP; return NENOP; } +nop { yylval.integer = ELK_OPCODE_NOP; return NOP; } +not { yylval.integer = ELK_OPCODE_NOT; return NOT; } +or { yylval.integer = ELK_OPCODE_OR; return OR; } +pln { yylval.integer = ELK_OPCODE_PLN; return PLN; } +pop { yylval.integer = ELK_OPCODE_POP; return POP; } +push { yylval.integer = ELK_OPCODE_PUSH; return PUSH; } +ret { yylval.integer = ELK_OPCODE_RET; return RET; } +rndd { yylval.integer = ELK_OPCODE_RNDD; return RNDD; } +rnde { yylval.integer = ELK_OPCODE_RNDE; return RNDE; } +rndu { yylval.integer = ELK_OPCODE_RNDU; return RNDU; } +rndz { yylval.integer = ELK_OPCODE_RNDZ; return RNDZ; } +rol { yylval.integer = ELK_OPCODE_ROL; return ROL; } +ror { yylval.integer = ELK_OPCODE_ROR; return ROR; } +sad2 { yylval.integer = ELK_OPCODE_SAD2; return SAD2; } +sada2 { yylval.integer = ELK_OPCODE_SADA2; return SADA2; } +sel { yylval.integer = ELK_OPCODE_SEL; return SEL; } send { - yylval.integer = BRW_OPCODE_SEND; + yylval.integer = ELK_OPCODE_SEND; return p->devinfo->ver < 12 ? SEND_GFX4 : SEND_GFX12; } sendc { - yylval.integer = BRW_OPCODE_SENDC; + yylval.integer = ELK_OPCODE_SENDC; return p->devinfo->ver < 12 ? SENDC_GFX4 : SENDC_GFX12; } -sends { yylval.integer = BRW_OPCODE_SENDS; return SENDS; } -sendsc { yylval.integer = BRW_OPCODE_SENDSC; return SENDSC; } -shl { yylval.integer = BRW_OPCODE_SHL; return SHL; } -shr { yylval.integer = BRW_OPCODE_SHR; return SHR; } -smov { yylval.integer = BRW_OPCODE_SMOV; return SMOV; } -subb { yylval.integer = BRW_OPCODE_SUBB; return SUBB; } -wait { yylval.integer = BRW_OPCODE_WAIT; return WAIT; } -while { yylval.integer = BRW_OPCODE_WHILE; return WHILE; } -xor { yylval.integer = BRW_OPCODE_XOR; return XOR; } -sync { yylval.integer = BRW_OPCODE_SYNC; return SYNC; } +sends { yylval.integer = ELK_OPCODE_SENDS; return SENDS; } +sendsc { yylval.integer = ELK_OPCODE_SENDSC; return SENDSC; } +shl { yylval.integer = ELK_OPCODE_SHL; return SHL; } +shr { yylval.integer = ELK_OPCODE_SHR; return SHR; } +smov { yylval.integer = ELK_OPCODE_SMOV; return SMOV; } +subb { yylval.integer = ELK_OPCODE_SUBB; return SUBB; } +wait { yylval.integer = ELK_OPCODE_WAIT; return WAIT; } +while { yylval.integer = ELK_OPCODE_WHILE; return WHILE; } +xor { yylval.integer = ELK_OPCODE_XOR; return XOR; } +sync { yylval.integer = ELK_OPCODE_SYNC; return SYNC; } /* extended math functions */ -cos { yylval.integer = BRW_MATH_FUNCTION_COS; return COS; } -exp { yylval.integer = BRW_MATH_FUNCTION_EXP; return EXP; } -fdiv { yylval.integer = BRW_MATH_FUNCTION_FDIV; return FDIV; } -inv { yylval.integer = BRW_MATH_FUNCTION_INV; return INV; } +cos { yylval.integer = ELK_MATH_FUNCTION_COS; return COS; } +exp { yylval.integer = ELK_MATH_FUNCTION_EXP; return EXP; } +fdiv { yylval.integer = ELK_MATH_FUNCTION_FDIV; return FDIV; } +inv { yylval.integer = ELK_MATH_FUNCTION_INV; return INV; } invm { yylval.integer = GFX8_MATH_FUNCTION_INVM; return INVM; } intdiv { - yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT; + yylval.integer = ELK_MATH_FUNCTION_INT_DIV_QUOTIENT; return INTDIV; } intdivmod { yylval.integer = - BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER; + ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER; return INTDIVMOD; } intmod { - yylval.integer = BRW_MATH_FUNCTION_INT_DIV_REMAINDER; + yylval.integer = ELK_MATH_FUNCTION_INT_DIV_REMAINDER; return INTMOD; } -log { yylval.integer = BRW_MATH_FUNCTION_LOG; return LOG; } -pow { yylval.integer = BRW_MATH_FUNCTION_POW; return POW; } -rsq { yylval.integer = BRW_MATH_FUNCTION_RSQ; return RSQ; } +log { yylval.integer = ELK_MATH_FUNCTION_LOG; return LOG; } +pow { yylval.integer = ELK_MATH_FUNCTION_POW; return POW; } +rsq { yylval.integer = ELK_MATH_FUNCTION_RSQ; return RSQ; } rsqrtm { yylval.integer = GFX8_MATH_FUNCTION_RSQRTM; return RSQRTM; } -sin { yylval.integer = BRW_MATH_FUNCTION_SIN; return SIN; } -sqrt { yylval.integer = BRW_MATH_FUNCTION_SQRT; return SQRT; } -sincos { yylval.integer = BRW_MATH_FUNCTION_SINCOS; return SINCOS; } +sin { yylval.integer = ELK_MATH_FUNCTION_SIN; return SIN; } +sqrt { yylval.integer = ELK_MATH_FUNCTION_SQRT; return SQRT; } +sincos { yylval.integer = ELK_MATH_FUNCTION_SINCOS; return SINCOS; } /* sync instruction */ allrd { yylval.integer = TGL_SYNC_ALLRD; return ALLRD; } @@ -225,10 +225,10 @@ ugm { return UGM; } "." { BEGIN(DOTSEL); return DOT; } ";" { return SEMICOLON; } -"x" { yylval.integer = BRW_CHANNEL_X; return X; } -"y" { yylval.integer = BRW_CHANNEL_Y; return Y; } -"z" { yylval.integer = BRW_CHANNEL_Z; return Z; } -"w" { yylval.integer = BRW_CHANNEL_W; return W; } +"x" { yylval.integer = ELK_CHANNEL_X; return X; } +"y" { yylval.integer = ELK_CHANNEL_Y; return Y; } +"z" { yylval.integer = ELK_CHANNEL_Z; return Z; } +"w" { yylval.integer = ELK_CHANNEL_W; return W; } [0-9][0-9]* { yylval.integer = strtoul(yytext, NULL, 10); BEGIN(REG); @@ -264,10 +264,10 @@ EOT { return EOT; } nomask { return MASK_DISABLE; } /* Channel */ -"x" { yylval.integer = BRW_CHANNEL_X; return X; } -"y" { yylval.integer = BRW_CHANNEL_Y; return Y; } -"z" { yylval.integer = BRW_CHANNEL_Z; return Z; } -"w" { yylval.integer = BRW_CHANNEL_W; return W; } +"x" { yylval.integer = ELK_CHANNEL_X; return X; } +"y" { yylval.integer = ELK_CHANNEL_Y; return Y; } +"z" { yylval.integer = ELK_CHANNEL_Z; return Z; } +"w" { yylval.integer = ELK_CHANNEL_W; return W; } [0-9][0-9]* { yylval.integer = strtoul(yytext, NULL, 10); return INTEGER; @@ -277,18 +277,18 @@ nomask { return MASK_DISABLE; } /* Predicate Control */ -".anyv" { yylval.integer = BRW_PREDICATE_ALIGN1_ANYV; return ANYV; } -".allv" { yylval.integer = BRW_PREDICATE_ALIGN1_ALLV; return ALLV; } -".any2h" { yylval.integer = BRW_PREDICATE_ALIGN1_ANY2H; return ANY2H; } -".all2h" { yylval.integer = BRW_PREDICATE_ALIGN1_ALL2H; return ALL2H; } -".any4h" { yylval.integer = BRW_PREDICATE_ALIGN16_ANY4H; return ANY4H; } -".all4h" { yylval.integer = BRW_PREDICATE_ALIGN16_ALL4H; return ALL4H; } -".any8h" { yylval.integer = BRW_PREDICATE_ALIGN1_ANY8H; return ANY8H; } -".all8h" { yylval.integer = BRW_PREDICATE_ALIGN1_ALL8H; return ALL8H; } -".any16h" { yylval.integer = BRW_PREDICATE_ALIGN1_ANY16H; return ANY16H; } -".all16h" { yylval.integer = BRW_PREDICATE_ALIGN1_ALL16H; return ALL16H; } -".any32h" { yylval.integer = BRW_PREDICATE_ALIGN1_ANY32H; return ANY32H; } -".all32h" { yylval.integer = BRW_PREDICATE_ALIGN1_ALL32H; return ALL32H; } +".anyv" { yylval.integer = ELK_PREDICATE_ALIGN1_ANYV; return ANYV; } +".allv" { yylval.integer = ELK_PREDICATE_ALIGN1_ALLV; return ALLV; } +".any2h" { yylval.integer = ELK_PREDICATE_ALIGN1_ANY2H; return ANY2H; } +".all2h" { yylval.integer = ELK_PREDICATE_ALIGN1_ALL2H; return ALL2H; } +".any4h" { yylval.integer = ELK_PREDICATE_ALIGN16_ANY4H; return ANY4H; } +".all4h" { yylval.integer = ELK_PREDICATE_ALIGN16_ALL4H; return ALL4H; } +".any8h" { yylval.integer = ELK_PREDICATE_ALIGN1_ANY8H; return ANY8H; } +".all8h" { yylval.integer = ELK_PREDICATE_ALIGN1_ALL8H; return ALL8H; } +".any16h" { yylval.integer = ELK_PREDICATE_ALIGN1_ANY16H; return ANY16H; } +".all16h" { yylval.integer = ELK_PREDICATE_ALIGN1_ALL16H; return ALL16H; } +".any32h" { yylval.integer = ELK_PREDICATE_ALIGN1_ANY32H; return ANY32H; } +".all32h" { yylval.integer = ELK_PREDICATE_ALIGN1_ALL32H; return ALL32H; } /* Saturation */ ".sat" { return SATURATE; } @@ -375,17 +375,17 @@ sr[0-9]+ { yylval.integer = atoi(yytext + 2); return STATEREG; } "mask"[0-9]+ { yylval.integer = atoi(yytext + 4); return MASKREG; } /* Conditional modifiers */ -".e" { yylval.integer = BRW_CONDITIONAL_Z; return EQUAL; } -".g" { yylval.integer = BRW_CONDITIONAL_G; return GREATER; } -".ge" { yylval.integer = BRW_CONDITIONAL_GE; return GREATER_EQUAL; } -".l" { yylval.integer = BRW_CONDITIONAL_L; return LESS; } -".le" { yylval.integer = BRW_CONDITIONAL_LE; return LESS_EQUAL; } -".ne" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_EQUAL; } -".nz" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_ZERO; } -".o" { yylval.integer = BRW_CONDITIONAL_O; return OVERFLOW; } -".r" { yylval.integer = BRW_CONDITIONAL_R; return ROUND_INCREMENT; } -".u" { yylval.integer = BRW_CONDITIONAL_U; return UNORDERED; } -".z" { yylval.integer = BRW_CONDITIONAL_Z; return ZERO; } +".e" { yylval.integer = ELK_CONDITIONAL_Z; return EQUAL; } +".g" { yylval.integer = ELK_CONDITIONAL_G; return GREATER; } +".ge" { yylval.integer = ELK_CONDITIONAL_GE; return GREATER_EQUAL; } +".l" { yylval.integer = ELK_CONDITIONAL_L; return LESS; } +".le" { yylval.integer = ELK_CONDITIONAL_LE; return LESS_EQUAL; } +".ne" { yylval.integer = ELK_CONDITIONAL_NZ; return NOT_EQUAL; } +".nz" { yylval.integer = ELK_CONDITIONAL_NZ; return NOT_ZERO; } +".o" { yylval.integer = ELK_CONDITIONAL_O; return OVERFLOW; } +".r" { yylval.integer = ELK_CONDITIONAL_R; return ROUND_INCREMENT; } +".u" { yylval.integer = ELK_CONDITIONAL_U; return UNORDERED; } +".z" { yylval.integer = ELK_CONDITIONAL_Z; return ZERO; } /* Eat up JIP and UIP token, their values will be parsed * in numeric section diff --git a/src/intel/compiler/elk/elk_lower_logical_sends.cpp b/src/intel/compiler/elk/elk_lower_logical_sends.cpp index 4f73ce73c13..218004566bf 100644 --- a/src/intel/compiler/elk/elk_lower_logical_sends.cpp +++ b/src/intel/compiler/elk/elk_lower_logical_sends.cpp @@ -32,7 +32,7 @@ using namespace elk; static void -lower_urb_read_logical_send(const fs_builder &bld, fs_inst *inst) +lower_urb_read_logical_send(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const bool per_slot_present = @@ -41,21 +41,21 @@ lower_urb_read_logical_send(const fs_builder &bld, fs_inst *inst) assert(inst->size_written % REG_SIZE == 0); assert(inst->header_size == 0); - fs_reg payload_sources[2]; + elk_fs_reg payload_sources[2]; unsigned header_size = 0; payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_HANDLE]; if (per_slot_present) payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; - fs_reg payload = fs_reg(VGRF, bld.shader->alloc.allocate(header_size), - BRW_REGISTER_TYPE_F); + elk_fs_reg payload = elk_fs_reg(VGRF, bld.shader->alloc.allocate(header_size), + ELK_REGISTER_TYPE_F); bld.LOAD_PAYLOAD(payload, payload_sources, header_size, header_size); - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->header_size = header_size; - inst->sfid = BRW_SFID_URB; - inst->desc = brw_urb_desc(devinfo, + inst->sfid = ELK_SFID_URB; + inst->desc = elk_urb_desc(devinfo, GFX8_URB_OPCODE_SIMD8_READ, per_slot_present, false, @@ -68,14 +68,14 @@ lower_urb_read_logical_send(const fs_builder &bld, fs_inst *inst) inst->resize_sources(4); - inst->src[0] = brw_imm_ud(0); /* desc */ - inst->src[1] = brw_imm_ud(0); /* ex_desc */ + inst->src[0] = elk_imm_ud(0); /* desc */ + inst->src[1] = elk_imm_ud(0); /* ex_desc */ inst->src[2] = payload; - inst->src[3] = brw_null_reg(); + inst->src[3] = elk_null_reg(); } static void -lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst) +lower_urb_read_logical_send_xe2(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); @@ -84,12 +84,12 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst) assert(inst->header_size == 0); /* Get the logical send arguments. */ - const fs_reg handle = inst->src[URB_LOGICAL_SRC_HANDLE]; + const elk_fs_reg handle = inst->src[URB_LOGICAL_SRC_HANDLE]; /* Calculate the total number of components of the payload. */ const unsigned dst_comps = inst->size_written / (REG_SIZE * reg_unit(devinfo)); - fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg payload = bld.vgrf(ELK_REGISTER_TYPE_UD); bld.MOV(payload, handle); @@ -97,18 +97,18 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst) * Add the (OWord) offset of the write to this value. */ if (inst->offset) { - bld.ADD(payload, payload, brw_imm_ud(inst->offset * 16)); + bld.ADD(payload, payload, elk_imm_ud(inst->offset * 16)); inst->offset = 0; } - fs_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; + elk_fs_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; if (offsets.file != BAD_FILE) { - fs_reg offsets_B = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.SHL(offsets_B, offsets, brw_imm_ud(4)); /* OWords -> Bytes */ + elk_fs_reg offsets_B = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.SHL(offsets_B, offsets, elk_imm_ud(4)); /* OWords -> Bytes */ bld.ADD(payload, payload, offsets_B); } - inst->sfid = BRW_SFID_URB; + inst->sfid = ELK_SFID_URB; assert((dst_comps >= 1 && dst_comps <= 4) || dst_comps == 8); @@ -122,7 +122,7 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst) /* Update the original instruction. */ - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc); inst->ex_mlen = 0; inst->header_size = 0; @@ -131,15 +131,15 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst) inst->resize_sources(4); - inst->src[0] = brw_imm_ud(0); - inst->src[1] = brw_imm_ud(0); + inst->src[0] = elk_imm_ud(0); + inst->src[1] = elk_imm_ud(0); inst->src[2] = payload; - inst->src[3] = brw_null_reg(); + inst->src[3] = elk_null_reg(); } static void -lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst) +lower_urb_write_logical_send(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const bool per_slot_present = @@ -152,9 +152,9 @@ lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst) const unsigned length = 1 + per_slot_present + channel_mask_present + inst->components_read(URB_LOGICAL_SRC_DATA); - fs_reg *payload_sources = new fs_reg[length]; - fs_reg payload = fs_reg(VGRF, bld.shader->alloc.allocate(length), - BRW_REGISTER_TYPE_F); + elk_fs_reg *payload_sources = new elk_fs_reg[length]; + elk_fs_reg payload = elk_fs_reg(VGRF, bld.shader->alloc.allocate(length), + ELK_REGISTER_TYPE_F); unsigned header_size = 0; payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_HANDLE]; @@ -171,12 +171,12 @@ lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst) delete [] payload_sources; - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->header_size = header_size; - inst->dst = brw_null_reg(); + inst->dst = elk_null_reg(); - inst->sfid = BRW_SFID_URB; - inst->desc = brw_urb_desc(devinfo, + inst->sfid = ELK_SFID_URB; + inst->desc = elk_urb_desc(devinfo, GFX8_URB_OPCODE_SIMD8_WRITE, per_slot_present, channel_mask_present, @@ -189,29 +189,29 @@ lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst) inst->resize_sources(4); - inst->src[0] = brw_imm_ud(0); /* desc */ - inst->src[1] = brw_imm_ud(0); /* ex_desc */ + inst->src[0] = elk_imm_ud(0); /* desc */ + inst->src[1] = elk_imm_ud(0); /* ex_desc */ inst->src[2] = payload; - inst->src[3] = brw_null_reg(); + inst->src[3] = elk_null_reg(); } static void -lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst) +lower_urb_write_logical_send_xe2(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); /* Get the logical send arguments. */ - const fs_reg handle = inst->src[URB_LOGICAL_SRC_HANDLE]; - const fs_reg src = inst->components_read(URB_LOGICAL_SRC_DATA) ? - inst->src[URB_LOGICAL_SRC_DATA] : fs_reg(brw_imm_ud(0)); + const elk_fs_reg handle = inst->src[URB_LOGICAL_SRC_HANDLE]; + const elk_fs_reg src = inst->components_read(URB_LOGICAL_SRC_DATA) ? + inst->src[URB_LOGICAL_SRC_DATA] : elk_fs_reg(elk_imm_ud(0)); assert(type_sz(src.type) == 4); /* Calculate the total number of components of the payload. */ const unsigned src_comps = MAX2(1, inst->components_read(URB_LOGICAL_SRC_DATA)); const unsigned src_sz = type_sz(src.type); - fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg payload = bld.vgrf(ELK_REGISTER_TYPE_UD); bld.MOV(payload, handle); @@ -219,32 +219,32 @@ lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst) * Add the (OWord) offset of the write to this value. */ if (inst->offset) { - bld.ADD(payload, payload, brw_imm_ud(inst->offset * 16)); + bld.ADD(payload, payload, elk_imm_ud(inst->offset * 16)); inst->offset = 0; } - fs_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; + elk_fs_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS]; if (offsets.file != BAD_FILE) { - fs_reg offsets_B = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.SHL(offsets_B, offsets, brw_imm_ud(4)); /* OWords -> Bytes */ + elk_fs_reg offsets_B = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.SHL(offsets_B, offsets, elk_imm_ud(4)); /* OWords -> Bytes */ bld.ADD(payload, payload, offsets_B); } - const fs_reg cmask = inst->src[URB_LOGICAL_SRC_CHANNEL_MASK]; + const elk_fs_reg cmask = inst->src[URB_LOGICAL_SRC_CHANNEL_MASK]; unsigned mask = 0; if (cmask.file != BAD_FILE) { assert(cmask.file == IMM); - assert(cmask.type == BRW_REGISTER_TYPE_UD); + assert(cmask.type == ELK_REGISTER_TYPE_UD); mask = cmask.ud >> 16; } - fs_reg payload2 = bld.move_to_vgrf(src, src_comps); + elk_fs_reg payload2 = bld.move_to_vgrf(src, src_comps); const unsigned ex_mlen = (src_comps * src_sz * inst->exec_size) / REG_SIZE; - inst->sfid = BRW_SFID_URB; + inst->sfid = ELK_SFID_URB; - enum lsc_opcode op = mask ? LSC_OP_STORE_CMASK : LSC_OP_STORE; + enum elk_lsc_opcode op = mask ? LSC_OP_STORE_CMASK : LSC_OP_STORE; inst->desc = lsc_msg_desc_wcmask(devinfo, op, inst->exec_size, LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32, 1 /* num_coordinates */, @@ -255,7 +255,7 @@ lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst) /* Update the original instruction. */ - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc); inst->ex_mlen = ex_mlen; inst->header_size = 0; @@ -264,20 +264,20 @@ lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst) inst->resize_sources(4); - inst->src[0] = brw_imm_ud(0); - inst->src[1] = brw_imm_ud(0); + inst->src[0] = elk_imm_ud(0); + inst->src[1] = elk_imm_ud(0); inst->src[2] = payload; inst->src[3] = payload2; } static void -setup_color_payload(const fs_builder &bld, const brw_wm_prog_key *key, - fs_reg *dst, fs_reg color, unsigned components) +setup_color_payload(const fs_builder &bld, const elk_wm_prog_key *key, + elk_fs_reg *dst, elk_fs_reg color, unsigned components) { if (key->clamp_fragment_color) { - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, 4); - assert(color.type == BRW_REGISTER_TYPE_F); + elk_fs_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_F, 4); + assert(color.type == ELK_REGISTER_TYPE_F); for (unsigned i = 0; i < components; i++) set_saturate(true, @@ -291,20 +291,20 @@ setup_color_payload(const fs_builder &bld, const brw_wm_prog_key *key, } static void -lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, - const struct brw_wm_prog_data *prog_data, - const brw_wm_prog_key *key, - const fs_thread_payload &payload) +lower_fb_write_logical_send(const fs_builder &bld, elk_fs_inst *inst, + const struct elk_wm_prog_data *prog_data, + const elk_wm_prog_key *key, + const elk_fs_thread_payload &payload) { assert(inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM); const intel_device_info *devinfo = bld.shader->devinfo; - const fs_reg color0 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR0]; - const fs_reg color1 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR1]; - const fs_reg src0_alpha = inst->src[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA]; - const fs_reg src_depth = inst->src[FB_WRITE_LOGICAL_SRC_SRC_DEPTH]; - const fs_reg dst_depth = inst->src[FB_WRITE_LOGICAL_SRC_DST_DEPTH]; - const fs_reg src_stencil = inst->src[FB_WRITE_LOGICAL_SRC_SRC_STENCIL]; - fs_reg sample_mask = inst->src[FB_WRITE_LOGICAL_SRC_OMASK]; + const elk_fs_reg color0 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR0]; + const elk_fs_reg color1 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR1]; + const elk_fs_reg src0_alpha = inst->src[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA]; + const elk_fs_reg src_depth = inst->src[FB_WRITE_LOGICAL_SRC_SRC_DEPTH]; + const elk_fs_reg dst_depth = inst->src[FB_WRITE_LOGICAL_SRC_DST_DEPTH]; + const elk_fs_reg src_stencil = inst->src[FB_WRITE_LOGICAL_SRC_SRC_STENCIL]; + elk_fs_reg sample_mask = inst->src[FB_WRITE_LOGICAL_SRC_OMASK]; const unsigned components = inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].ud; @@ -313,7 +313,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, /* We can potentially have a message length of up to 15, so we have to set * base_mrf to either 0 or 1 in order to fit in m0..m15. */ - fs_reg sources[15]; + elk_fs_reg sources[15]; int header_size = 2, payload_header_size; unsigned length = 0; @@ -335,8 +335,8 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, */ if (prog_data->uses_kill) { bld.exec_all().group(1, 0) - .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW), - brw_sample_mask_reg(bld)); + .MOV(retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_UW), + elk_sample_mask_reg(bld)); } assert(length == 0); @@ -356,17 +356,17 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, */ const fs_builder ubld = bld.exec_all().group(8, 0); - fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2); + elk_fs_reg header = ubld.vgrf(ELK_REGISTER_TYPE_UD, 2); if (bld.group() < 16) { /* The header starts off as g0 and g1 for the first half */ - ubld.group(16, 0).MOV(header, retype(brw_vec8_grf(0, 0), - BRW_REGISTER_TYPE_UD)); + ubld.group(16, 0).MOV(header, retype(elk_vec8_grf(0, 0), + ELK_REGISTER_TYPE_UD)); } else { /* The header starts off as g0 and g2 for the second half */ assert(bld.group() < 32); - const fs_reg header_sources[2] = { - retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD), - retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD), + const elk_fs_reg header_sources[2] = { + retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD), + retype(elk_vec8_grf(2, 0), ELK_REGISTER_TYPE_UD), }; ubld.LOAD_PAYLOAD(header, header_sources, 2, 0); @@ -389,20 +389,20 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, if (g00_bits) { /* OR extra bits into g0.0 */ ubld.group(1, 0).OR(component(header, 0), - retype(brw_vec1_grf(0, 0), - BRW_REGISTER_TYPE_UD), - brw_imm_ud(g00_bits)); + retype(elk_vec1_grf(0, 0), + ELK_REGISTER_TYPE_UD), + elk_imm_ud(g00_bits)); } /* Set the render target index for choosing BLEND_STATE. */ if (inst->target > 0) { - ubld.group(1, 0).MOV(component(header, 2), brw_imm_ud(inst->target)); + ubld.group(1, 0).MOV(component(header, 2), elk_imm_ud(inst->target)); } if (prog_data->uses_kill) { ubld.group(1, 0).MOV(retype(component(header, 15), - BRW_REGISTER_TYPE_UW), - brw_sample_mask_reg(bld)); + ELK_REGISTER_TYPE_UW), + elk_sample_mask_reg(bld)); } assert(length == 0); @@ -415,10 +415,10 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, if (payload.aa_dest_stencil_reg[0]) { assert(inst->group < 16); - sources[length] = fs_reg(VGRF, bld.shader->alloc.allocate(1)); + sources[length] = elk_fs_reg(VGRF, bld.shader->alloc.allocate(1)); bld.group(8, 0).exec_all().annotate("FB write stencil/AA alpha") .MOV(sources[length], - fs_reg(brw_vec8_grf(payload.aa_dest_stencil_reg[0], 0))); + elk_fs_reg(elk_vec8_grf(payload.aa_dest_stencil_reg[0], 0))); length++; } @@ -426,7 +426,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, for (unsigned i = 0; i < bld.dispatch_width() / 8; i++) { const fs_builder &ubld = bld.exec_all().group(8, i) .annotate("FB write src0 alpha"); - const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_F); + const elk_fs_reg tmp = ubld.vgrf(ELK_REGISTER_TYPE_F); ubld.MOV(tmp, horiz_offset(src0_alpha, i * 8)); setup_color_payload(ubld, key, &sources[length], tmp, 1); length++; @@ -434,8 +434,8 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, } if (sample_mask.file != BAD_FILE) { - const fs_reg tmp(VGRF, bld.shader->alloc.allocate(reg_unit(devinfo)), - BRW_REGISTER_TYPE_UD); + const elk_fs_reg tmp(VGRF, bld.shader->alloc.allocate(reg_unit(devinfo)), + ELK_REGISTER_TYPE_UD); /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are * relevant. Since it's unsigned single words one vgrf is always @@ -444,11 +444,11 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, * selected the subspans for the first or second half respectively. */ assert(sample_mask.file != BAD_FILE && type_sz(sample_mask.type) == 4); - sample_mask.type = BRW_REGISTER_TYPE_UW; + sample_mask.type = ELK_REGISTER_TYPE_UW; sample_mask.stride *= 2; bld.exec_all().annotate("FB write oMask") - .MOV(horiz_offset(retype(tmp, BRW_REGISTER_TYPE_UW), + .MOV(horiz_offset(retype(tmp, ELK_REGISTER_TYPE_UW), inst->group % (16 * reg_unit(devinfo))), sample_mask); @@ -486,37 +486,37 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, */ assert(length < 15 * reg_unit(devinfo)); - sources[length] = bld.vgrf(BRW_REGISTER_TYPE_UD); + sources[length] = bld.vgrf(ELK_REGISTER_TYPE_UD); bld.exec_all().annotate("FB write OS") - .MOV(retype(sources[length], BRW_REGISTER_TYPE_UB), - subscript(src_stencil, BRW_REGISTER_TYPE_UB, 0)); + .MOV(retype(sources[length], ELK_REGISTER_TYPE_UB), + subscript(src_stencil, ELK_REGISTER_TYPE_UB, 0)); length++; } - fs_inst *load; + elk_fs_inst *load; if (devinfo->ver >= 7) { /* Send from the GRF */ - fs_reg payload = fs_reg(VGRF, -1, BRW_REGISTER_TYPE_F); + elk_fs_reg payload = elk_fs_reg(VGRF, -1, ELK_REGISTER_TYPE_F); load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size); payload.nr = bld.shader->alloc.allocate(regs_written(load)); load->dst = payload; - uint32_t msg_ctl = brw_fb_write_msg_control(inst, prog_data); + uint32_t msg_ctl = elk_fb_write_msg_control(inst, prog_data); inst->desc = (inst->group / 16) << 11 | /* rt slot group */ - brw_fb_write_desc(devinfo, inst->target, msg_ctl, inst->last_rt, + elk_fb_write_desc(devinfo, inst->target, msg_ctl, inst->last_rt, 0 /* coarse_rt_write */); - fs_reg desc = brw_imm_ud(0); - if (prog_data->coarse_pixel_dispatch == BRW_ALWAYS) { + elk_fs_reg desc = elk_imm_ud(0); + if (prog_data->coarse_pixel_dispatch == ELK_ALWAYS) { inst->desc |= (1 << 18); - } else if (prog_data->coarse_pixel_dispatch == BRW_SOMETIMES) { + } else if (prog_data->coarse_pixel_dispatch == ELK_SOMETIMES) { STATIC_ASSERT(INTEL_MSAA_FLAG_COARSE_RT_WRITES == (1 << 18)); const fs_builder &ubld = bld.exec_all().group(8, 0); - desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); + desc = ubld.vgrf(ELK_REGISTER_TYPE_UD); ubld.AND(desc, dynamic_msaa_flags(prog_data), - brw_imm_ud(INTEL_MSAA_FLAG_COARSE_RT_WRITES)); + elk_imm_ud(INTEL_MSAA_FLAG_COARSE_RT_WRITES)); desc = component(desc, 0); } @@ -532,11 +532,11 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, } inst->ex_desc = ex_desc; - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->resize_sources(3); inst->sfid = GFX6_SFID_DATAPORT_RENDER_CACHE; inst->src[0] = desc; - inst->src[1] = brw_imm_ud(0); + inst->src[1] = elk_imm_ud(0); inst->src[2] = payload; inst->mlen = regs_written(load); inst->ex_mlen = 0; @@ -545,45 +545,45 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, inst->send_has_side_effects = true; } else { /* Send from the MRF */ - load = bld.LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F), + load = bld.LOAD_PAYLOAD(elk_fs_reg(MRF, 1, ELK_REGISTER_TYPE_F), sources, length, payload_header_size); /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD * will do this for us if we just give it a COMPR4 destination. */ if (devinfo->ver < 6 && bld.dispatch_width() == 16) - load->dst.nr |= BRW_MRF_COMPR4; + load->dst.nr |= ELK_MRF_COMPR4; if (devinfo->ver < 6) { /* Set up src[0] for the implied MOV from grf0-1 */ inst->resize_sources(1); - inst->src[0] = brw_vec8_grf(0, 0); + inst->src[0] = elk_vec8_grf(0, 0); } else { inst->resize_sources(0); } inst->base_mrf = 1; - inst->opcode = FS_OPCODE_FB_WRITE; + inst->opcode = ELK_FS_OPCODE_FB_WRITE; inst->mlen = regs_written(load); inst->header_size = header_size; } } static void -lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst) +lower_fb_read_logical_send(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const fs_builder &ubld = bld.exec_all().group(8, 0); const unsigned length = 2; - const fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, length); + const elk_fs_reg header = ubld.vgrf(ELK_REGISTER_TYPE_UD, length); if (bld.group() < 16) { - ubld.group(16, 0).MOV(header, retype(brw_vec8_grf(0, 0), - BRW_REGISTER_TYPE_UD)); + ubld.group(16, 0).MOV(header, retype(elk_vec8_grf(0, 0), + ELK_REGISTER_TYPE_UD)); } else { assert(bld.group() < 32); - const fs_reg header_sources[] = { - retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD), - retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD) + const elk_fs_reg header_sources[] = { + retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD), + retype(elk_vec8_grf(2, 0), ELK_REGISTER_TYPE_UD) }; ubld.LOAD_PAYLOAD(header, header_sources, ARRAY_SIZE(header_sources), 0); @@ -597,7 +597,7 @@ lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst) * r1.1 in order to fix things up. */ ubld.group(1, 0).MOV(component(header, 9), - retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_UD)); + retype(elk_vec1_grf(1, 1), ELK_REGISTER_TYPE_UD)); } } @@ -613,29 +613,29 @@ lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst) */ ubld.group(1, 0).AND(component(header, 0), component(header, 0), - brw_imm_ud(~INTEL_MASK(14, 11))); + elk_imm_ud(~INTEL_MASK(14, 11))); inst->resize_sources(1); inst->src[0] = header; - inst->opcode = FS_OPCODE_FB_READ; + inst->opcode = ELK_FS_OPCODE_FB_READ; inst->mlen = length; inst->header_size = length; } static void -lower_sampler_logical_send_gfx4(const fs_builder &bld, fs_inst *inst, opcode op, - const fs_reg &coordinate, - const fs_reg &shadow_c, - const fs_reg &lod, const fs_reg &lod2, - const fs_reg &surface, - const fs_reg &sampler, +lower_sampler_logical_send_gfx4(const fs_builder &bld, elk_fs_inst *inst, elk_opcode op, + const elk_fs_reg &coordinate, + const elk_fs_reg &shadow_c, + const elk_fs_reg &lod, const elk_fs_reg &lod2, + const elk_fs_reg &surface, + const elk_fs_reg &sampler, unsigned coord_components, unsigned grad_components) { - const bool has_lod = (op == SHADER_OPCODE_TXL || op == FS_OPCODE_TXB || - op == SHADER_OPCODE_TXF || op == SHADER_OPCODE_TXS); - fs_reg msg_begin(MRF, 1, BRW_REGISTER_TYPE_F); - fs_reg msg_end = msg_begin; + const bool has_lod = (op == ELK_SHADER_OPCODE_TXL || op == ELK_FS_OPCODE_TXB || + op == ELK_SHADER_OPCODE_TXF || op == ELK_SHADER_OPCODE_TXS); + elk_fs_reg msg_begin(MRF, 1, ELK_REGISTER_TYPE_F); + elk_fs_reg msg_end = msg_begin; /* g0 header. */ msg_end = offset(msg_end, bld.group(8, 0), 1); @@ -651,15 +651,15 @@ lower_sampler_logical_send_gfx4(const fs_builder &bld, fs_inst *inst, opcode op, */ if (coord_components > 0 && (has_lod || shadow_c.file != BAD_FILE || - (op == SHADER_OPCODE_TEX && bld.dispatch_width() == 8))) { + (op == ELK_SHADER_OPCODE_TEX && bld.dispatch_width() == 8))) { assert(coord_components <= 3); for (unsigned i = 0; i < 3 - coord_components; i++) - bld.MOV(offset(msg_end, bld, i), brw_imm_f(0.0f)); + bld.MOV(offset(msg_end, bld, i), elk_imm_f(0.0f)); msg_end = offset(msg_end, bld, 3 - coord_components); } - if (op == SHADER_OPCODE_TXD) { + if (op == ELK_SHADER_OPCODE_TXD) { /* TXD unsupported in SIMD16 mode. */ assert(bld.dispatch_width() == 8); @@ -699,19 +699,19 @@ lower_sampler_logical_send_gfx4(const fs_builder &bld, fs_inst *inst, opcode op, assert(shadow_c.file != BAD_FILE ? bld.dispatch_width() == 8 : bld.dispatch_width() == 16); - const brw_reg_type type = - (op == SHADER_OPCODE_TXF || op == SHADER_OPCODE_TXS ? - BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_F); + const elk_reg_type type = + (op == ELK_SHADER_OPCODE_TXF || op == ELK_SHADER_OPCODE_TXS ? + ELK_REGISTER_TYPE_UD : ELK_REGISTER_TYPE_F); bld.MOV(retype(msg_end, type), lod); msg_end = offset(msg_end, bld, 1); } if (shadow_c.file != BAD_FILE) { - if (op == SHADER_OPCODE_TEX && bld.dispatch_width() == 8) { + if (op == ELK_SHADER_OPCODE_TEX && bld.dispatch_width() == 8) { /* There's no plain shadow compare message, so we use shadow * compare with a bias of 0.0. */ - bld.MOV(msg_end, brw_imm_f(0.0f)); + bld.MOV(msg_end, elk_imm_f(0.0f)); msg_end = offset(msg_end, bld, 1); } @@ -730,18 +730,18 @@ lower_sampler_logical_send_gfx4(const fs_builder &bld, fs_inst *inst, opcode op, } static void -lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op, - const fs_reg &coordinate, - const fs_reg &shadow_c, - const fs_reg &lod, const fs_reg &lod2, - const fs_reg &sample_index, - const fs_reg &surface, - const fs_reg &sampler, +lower_sampler_logical_send_gfx5(const fs_builder &bld, elk_fs_inst *inst, elk_opcode op, + const elk_fs_reg &coordinate, + const elk_fs_reg &shadow_c, + const elk_fs_reg &lod, const elk_fs_reg &lod2, + const elk_fs_reg &sample_index, + const elk_fs_reg &surface, + const elk_fs_reg &sampler, unsigned coord_components, unsigned grad_components) { - fs_reg message(MRF, 2, BRW_REGISTER_TYPE_F); - fs_reg msg_coords = message; + elk_fs_reg message(MRF, 2, ELK_REGISTER_TYPE_F); + elk_fs_reg msg_coords = message; unsigned header_size = 0; if (inst->offset != 0) { @@ -756,23 +756,23 @@ lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op, bld.MOV(retype(offset(msg_coords, bld, i), coordinate.type), offset(coordinate, bld, i)); - fs_reg msg_end = offset(msg_coords, bld, coord_components); - fs_reg msg_lod = offset(msg_coords, bld, 4); + elk_fs_reg msg_end = offset(msg_coords, bld, coord_components); + elk_fs_reg msg_lod = offset(msg_coords, bld, 4); if (shadow_c.file != BAD_FILE) { - fs_reg msg_shadow = msg_lod; + elk_fs_reg msg_shadow = msg_lod; bld.MOV(msg_shadow, shadow_c); msg_lod = offset(msg_shadow, bld, 1); msg_end = msg_lod; } switch (op) { - case SHADER_OPCODE_TXL: - case FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXL: + case ELK_FS_OPCODE_TXB: bld.MOV(msg_lod, lod); msg_end = offset(msg_lod, bld, 1); break; - case SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXD: /** * P = u, v, r * dPdx = dudx, dvdx, drdx @@ -791,22 +791,22 @@ lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op, msg_end = offset(msg_end, bld, 1); } break; - case SHADER_OPCODE_TXS: - msg_lod = retype(msg_end, BRW_REGISTER_TYPE_UD); + case ELK_SHADER_OPCODE_TXS: + msg_lod = retype(msg_end, ELK_REGISTER_TYPE_UD); bld.MOV(msg_lod, lod); msg_end = offset(msg_lod, bld, 1); break; - case SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF: msg_lod = offset(msg_coords, bld, 3); - bld.MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), lod); + bld.MOV(retype(msg_lod, ELK_REGISTER_TYPE_UD), lod); msg_end = offset(msg_lod, bld, 1); break; - case SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS: msg_lod = offset(msg_coords, bld, 3); /* lod */ - bld.MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u)); + bld.MOV(retype(msg_lod, ELK_REGISTER_TYPE_UD), elk_imm_ud(0u)); /* sample index */ - bld.MOV(retype(offset(msg_lod, bld, 1), BRW_REGISTER_TYPE_UD), sample_index); + bld.MOV(retype(offset(msg_lod, bld, 1), ELK_REGISTER_TYPE_UD), sample_index); msg_end = offset(msg_lod, bld, 2); break; default: @@ -827,7 +827,7 @@ lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op, } static bool -is_high_sampler(const struct intel_device_info *devinfo, const fs_reg &sampler) +is_high_sampler(const struct intel_device_info *devinfo, const elk_fs_reg &sampler) { if (devinfo->verx10 <= 70) return false; @@ -837,11 +837,11 @@ is_high_sampler(const struct intel_device_info *devinfo, const fs_reg &sampler) static unsigned sampler_msg_type(const intel_device_info *devinfo, - opcode opcode, bool shadow_compare, bool has_min_lod) + elk_opcode opcode, bool shadow_compare, bool has_min_lod) { assert(devinfo->ver >= 5); switch (opcode) { - case SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TEX: if (devinfo->ver >= 20 && has_min_lod) { return shadow_compare ? XE2_SAMPLER_MESSAGE_SAMPLE_COMPARE_MLOD : XE2_SAMPLER_MESSAGE_SAMPLE_MLOD; @@ -849,63 +849,63 @@ sampler_msg_type(const intel_device_info *devinfo, return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE : GFX5_SAMPLER_MESSAGE_SAMPLE; } - case FS_OPCODE_TXB: + case ELK_FS_OPCODE_TXB: return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE : GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS; - case SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL: assert(!has_min_lod); return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE : GFX5_SAMPLER_MESSAGE_SAMPLE_LOD; - case SHADER_OPCODE_TXL_LZ: + case ELK_SHADER_OPCODE_TXL_LZ: assert(!has_min_lod); return shadow_compare ? GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ : GFX9_SAMPLER_MESSAGE_SAMPLE_LZ; - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL: assert(!has_min_lod); return GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO; - case SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXD: assert(!shadow_compare || devinfo->verx10 >= 75); return shadow_compare ? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE : GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS; - case SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF: assert(!has_min_lod); return GFX5_SAMPLER_MESSAGE_SAMPLE_LD; - case SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXF_LZ: assert(!has_min_lod); assert(devinfo->ver >= 9); return GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ; - case SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_CMS_W: assert(!has_min_lod); assert(devinfo->ver >= 9); return GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W; - case SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS: assert(!has_min_lod); return devinfo->ver >= 7 ? GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS : GFX5_SAMPLER_MESSAGE_SAMPLE_LD; - case SHADER_OPCODE_TXF_UMS: + case ELK_SHADER_OPCODE_TXF_UMS: assert(!has_min_lod); assert(devinfo->ver >= 7); return GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS; - case SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXF_MCS: assert(!has_min_lod); assert(devinfo->ver >= 7); return GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS; - case SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_LOD: assert(!has_min_lod); return GFX5_SAMPLER_MESSAGE_LOD; - case SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4: assert(!has_min_lod); assert(devinfo->ver >= 7); return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C : GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4; break; - case SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_TG4_OFFSET: assert(!has_min_lod); assert(devinfo->ver >= 7); return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C : GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO; - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_SAMPLEINFO: assert(!has_min_lod); return GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO; default: @@ -917,16 +917,16 @@ sampler_msg_type(const intel_device_info *devinfo, * Emit a LOAD_PAYLOAD instruction while ensuring the sources are aligned to * the given requested_alignment_sz. */ -static fs_inst * -emit_load_payload_with_padding(const fs_builder &bld, const fs_reg &dst, - const fs_reg *src, unsigned sources, +static elk_fs_inst * +emit_load_payload_with_padding(const fs_builder &bld, const elk_fs_reg &dst, + const elk_fs_reg *src, unsigned sources, unsigned header_size, unsigned requested_alignment_sz) { unsigned length = 0; unsigned num_srcs = sources * DIV_ROUND_UP(requested_alignment_sz, bld.dispatch_width()); - fs_reg *src_comps = new fs_reg[num_srcs]; + elk_fs_reg *src_comps = new elk_fs_reg[num_srcs]; for (unsigned i = 0; i < header_size; i++) src_comps[length++] = src[i]; @@ -934,9 +934,9 @@ emit_load_payload_with_padding(const fs_builder &bld, const fs_reg &dst, for (unsigned i = header_size; i < sources; i++) { unsigned src_sz = retype(dst, src[i].type).component_size(bld.dispatch_width()); - const enum brw_reg_type padding_payload_type = - brw_reg_type_from_bit_size(type_sz(src[i].type) * 8, - BRW_REGISTER_TYPE_UD); + const enum elk_reg_type padding_payload_type = + elk_reg_type_from_bit_size(type_sz(src[i].type) * 8, + ELK_REGISTER_TYPE_UD); src_comps[length++] = src[i]; @@ -945,46 +945,46 @@ emit_load_payload_with_padding(const fs_builder &bld, const fs_reg &dst, */ if (src_sz < requested_alignment_sz) { for (unsigned j = 0; j < (requested_alignment_sz / src_sz) - 1; j++) { - src_comps[length++] = retype(fs_reg(), padding_payload_type); + src_comps[length++] = retype(elk_fs_reg(), padding_payload_type); } } } - fs_inst *inst = bld.LOAD_PAYLOAD(dst, src_comps, length, header_size); + elk_fs_inst *inst = bld.LOAD_PAYLOAD(dst, src_comps, length, header_size); delete[] src_comps; return inst; } static void -lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, - const fs_reg &coordinate, - const fs_reg &shadow_c, - fs_reg lod, const fs_reg &lod2, - const fs_reg &min_lod, - const fs_reg &sample_index, - const fs_reg &mcs, - const fs_reg &surface, - const fs_reg &sampler, - const fs_reg &surface_handle, - const fs_reg &sampler_handle, - const fs_reg &tg4_offset, +lower_sampler_logical_send_gfx7(const fs_builder &bld, elk_fs_inst *inst, elk_opcode op, + const elk_fs_reg &coordinate, + const elk_fs_reg &shadow_c, + elk_fs_reg lod, const elk_fs_reg &lod2, + const elk_fs_reg &min_lod, + const elk_fs_reg &sample_index, + const elk_fs_reg &mcs, + const elk_fs_reg &surface, + const elk_fs_reg &sampler, + const elk_fs_reg &surface_handle, + const elk_fs_reg &sampler_handle, + const elk_fs_reg &tg4_offset, unsigned payload_type_bit_size, unsigned coord_components, unsigned grad_components, bool residency) { - const brw_compiler *compiler = bld.shader->compiler; + const elk_compiler *compiler = bld.shader->compiler; const intel_device_info *devinfo = bld.shader->devinfo; - const enum brw_reg_type payload_type = - brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_F); - const enum brw_reg_type payload_unsigned_type = - brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_UD); - const enum brw_reg_type payload_signed_type = - brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_D); + const enum elk_reg_type payload_type = + elk_reg_type_from_bit_size(payload_type_bit_size, ELK_REGISTER_TYPE_F); + const enum elk_reg_type payload_unsigned_type = + elk_reg_type_from_bit_size(payload_type_bit_size, ELK_REGISTER_TYPE_UD); + const enum elk_reg_type payload_signed_type = + elk_reg_type_from_bit_size(payload_type_bit_size, ELK_REGISTER_TYPE_D); unsigned reg_width = bld.dispatch_width() / 8; unsigned header_size = 0, length = 0; - fs_reg sources[1 + MAX_SAMPLER_MESSAGE_SIZE]; + elk_fs_reg sources[1 + MAX_SAMPLER_MESSAGE_SIZE]; for (unsigned i = 0; i < ARRAY_SIZE(sources); i++) sources[i] = bld.vgrf(payload_type); @@ -992,9 +992,9 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, assert((surface.file == BAD_FILE) != (surface_handle.file == BAD_FILE)); assert((sampler.file == BAD_FILE) != (sampler_handle.file == BAD_FILE)); - if (op == SHADER_OPCODE_TG4 || op == SHADER_OPCODE_TG4_OFFSET || + if (op == ELK_SHADER_OPCODE_TG4 || op == ELK_SHADER_OPCODE_TG4_OFFSET || inst->offset != 0 || inst->eot || - op == SHADER_OPCODE_SAMPLEINFO || + op == ELK_SHADER_OPCODE_SAMPLEINFO || sampler_handle.file != BAD_FILE || is_high_sampler(devinfo, sampler) || residency) { @@ -1006,7 +1006,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, * larger sampler numbers we need to offset the Sampler State Pointer in * the header. */ - fs_reg header = retype(sources[0], BRW_REGISTER_TYPE_UD); + elk_fs_reg header = retype(sources[0], ELK_REGISTER_TYPE_UD); for (header_size = 0; header_size < reg_unit(devinfo); header_size++) sources[length++] = byte_offset(header, REG_SIZE * header_size); @@ -1027,9 +1027,9 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, /* Build the actual header */ const fs_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0); const fs_builder ubld1 = ubld.group(1, 0); - ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + ubld.MOV(header, retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); if (inst->offset) { - ubld1.MOV(component(header, 2), brw_imm_ud(inst->offset)); + ubld1.MOV(component(header, 2), elk_imm_ud(inst->offset)); } else if (bld.shader->stage != MESA_SHADER_VERTEX && bld.shader->stage != MESA_SHADER_FRAGMENT) { /* The vertex and fragment stages have g0.2 set to 0, so @@ -1037,7 +1037,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, * must set it to 0 to avoid setting undesirable bits in the * message. */ - ubld1.MOV(component(header, 2), brw_imm_ud(0)); + ubld1.MOV(component(header, 2), elk_imm_ud(0)); } if (sampler_handle.file != BAD_FILE) { @@ -1055,34 +1055,34 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, */ if (compiler->use_bindless_sampler_offset) { assert(devinfo->ver >= 11); - ubld1.OR(component(header, 3), sampler_handle, brw_imm_ud(1)); + ubld1.OR(component(header, 3), sampler_handle, elk_imm_ud(1)); } else { ubld1.MOV(component(header, 3), sampler_handle); } } else if (is_high_sampler(devinfo, sampler)) { - fs_reg sampler_state_ptr = - retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD); + elk_fs_reg sampler_state_ptr = + retype(elk_vec1_grf(0, 3), ELK_REGISTER_TYPE_UD); /* Gfx11+ sampler message headers include bits in 4:0 which conflict * with the ones included in g0.3 bits 4:0. Mask them out. */ if (devinfo->ver >= 11) { - sampler_state_ptr = ubld1.vgrf(BRW_REGISTER_TYPE_UD); + sampler_state_ptr = ubld1.vgrf(ELK_REGISTER_TYPE_UD); ubld1.AND(sampler_state_ptr, - retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(31, 5))); + retype(elk_vec1_grf(0, 3), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(31, 5))); } - if (sampler.file == BRW_IMMEDIATE_VALUE) { + if (sampler.file == ELK_IMMEDIATE_VALUE) { assert(sampler.ud >= 16); const int sampler_state_size = 16; /* 16 bytes */ ubld1.ADD(component(header, 3), sampler_state_ptr, - brw_imm_ud(16 * (sampler.ud / 16) * sampler_state_size)); + elk_imm_ud(16 * (sampler.ud / 16) * sampler_state_size)); } else { - fs_reg tmp = ubld1.vgrf(BRW_REGISTER_TYPE_UD); - ubld1.AND(tmp, sampler, brw_imm_ud(0x0f0)); - ubld1.SHL(tmp, tmp, brw_imm_ud(4)); + elk_fs_reg tmp = ubld1.vgrf(ELK_REGISTER_TYPE_UD); + ubld1.AND(tmp, sampler, elk_imm_ud(0x0f0)); + ubld1.SHL(tmp, tmp, elk_imm_ud(4)); ubld1.ADD(component(header, 3), sampler_state_ptr, tmp); } } else if (devinfo->ver >= 11) { @@ -1090,8 +1090,8 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, * with the ones included in g0.3 bits 4:0. Mask them out. */ ubld1.AND(component(header, 3), - retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(31, 5))); + retype(elk_vec1_grf(0, 3), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(31, 5))); } } @@ -1099,10 +1099,10 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, * switch-statement that emits sources based on the opcode. */ if (devinfo->ver >= 9 && lod.is_zero()) { - if (op == SHADER_OPCODE_TXL) - op = SHADER_OPCODE_TXL_LZ; - else if (op == SHADER_OPCODE_TXF) - op = SHADER_OPCODE_TXF_LZ; + if (op == ELK_SHADER_OPCODE_TXL) + op = ELK_SHADER_OPCODE_TXL_LZ; + else if (op == ELK_SHADER_OPCODE_TXF) + op = ELK_SHADER_OPCODE_TXF_LZ; } /* On Xe2 and newer platforms, min_lod is the first parameter specifically @@ -1131,12 +1131,12 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, /* Set up the LOD info */ switch (op) { - case FS_OPCODE_TXB: - case SHADER_OPCODE_TXL: + case ELK_FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXL: bld.MOV(sources[length], lod); length++; break; - case SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXD: /* TXD should have been lowered in SIMD16 mode (in SIMD32 mode in * Xe2+). */ @@ -1159,17 +1159,17 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, coordinate_done = true; break; - case SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TXS: bld.MOV(retype(sources[length], payload_unsigned_type), lod); length++; break; - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL: /* We need an LOD; just use 0 */ - bld.MOV(retype(sources[length], payload_unsigned_type), brw_imm_ud(0)); + bld.MOV(retype(sources[length], payload_unsigned_type), elk_imm_ud(0)); length++; break; - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_LZ: /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. * On Gfx9 they are u, v, lod, r */ @@ -1180,12 +1180,12 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, bld.MOV(retype(sources[length], payload_signed_type), offset(coordinate, bld, 1)); } else { - sources[length] = brw_imm_d(0); + sources[length] = elk_imm_d(0); } length++; } - if (op != SHADER_OPCODE_TXF_LZ) { + if (op != ELK_SHADER_OPCODE_TXF_LZ) { bld.MOV(retype(sources[length], payload_signed_type), lod); length++; } @@ -1197,18 +1197,18 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, coordinate_done = true; break; - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_UMS: - case SHADER_OPCODE_TXF_MCS: - if (op == SHADER_OPCODE_TXF_UMS || - op == SHADER_OPCODE_TXF_CMS || - op == SHADER_OPCODE_TXF_CMS_W) { + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_UMS: + case ELK_SHADER_OPCODE_TXF_MCS: + if (op == ELK_SHADER_OPCODE_TXF_UMS || + op == ELK_SHADER_OPCODE_TXF_CMS || + op == ELK_SHADER_OPCODE_TXF_CMS_W) { bld.MOV(retype(sources[length++], payload_unsigned_type), sample_index); } /* Data from the multisample control surface. */ - if (op == SHADER_OPCODE_TXF_CMS || op == SHADER_OPCODE_TXF_CMS_W) { + if (op == ELK_SHADER_OPCODE_TXF_CMS || op == ELK_SHADER_OPCODE_TXF_CMS_W) { unsigned num_mcs_components = 1; /* From the Gfx12HP BSpec: Render Engine - 3D and GPGPU Programs - @@ -1216,7 +1216,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, * * ld2dms_w si mcs0 mcs1 mcs2 mcs3 u v r */ - if (op == SHADER_OPCODE_TXF_CMS_W) + if (op == ELK_SHADER_OPCODE_TXF_CMS_W) num_mcs_components = 2; for (unsigned i = 0; i < num_mcs_components; ++i) { @@ -1230,8 +1230,8 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, * * ld2dms_w si mcs0 mcs1 mcs2 mcs3 u v r */ - if (devinfo->verx10 >= 125 && op == SHADER_OPCODE_TXF_CMS_W) { - fs_reg tmp = offset(mcs, bld, i); + if (devinfo->verx10 >= 125 && op == ELK_SHADER_OPCODE_TXF_CMS_W) { + elk_fs_reg tmp = offset(mcs, bld, i); bld.MOV(retype(sources[length++], payload_unsigned_type), mcs.file == IMM ? mcs : subscript(tmp, payload_unsigned_type, 0)); @@ -1254,7 +1254,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, coordinate_done = true; break; - case SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_TG4_OFFSET: /* More crazy intermixing */ for (unsigned i = 0; i < 2; i++) /* u, v */ bld.MOV(sources[length++], offset(coordinate, bld, i)); @@ -1281,7 +1281,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, if (min_lod.file != BAD_FILE && !min_lod_is_first) { /* Account for all of the missing coordinate sources */ - if (op == SHADER_OPCODE_TXD && devinfo->verx10 >= 125) { + if (op == ELK_SHADER_OPCODE_TXD && devinfo->verx10 >= 125) { /* On DG2 and newer platforms, sample_d can only be used with 1D and * 2D surfaces, so the maximum number of gradient components is 2. * In spite of this limitation, the Bspec lists a mysterious R @@ -1294,27 +1294,27 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, length += (2 - grad_components) * 2; } else { length += 4 - coord_components; - if (op == SHADER_OPCODE_TXD) + if (op == ELK_SHADER_OPCODE_TXD) length += (3 - grad_components) * 2; } bld.MOV(sources[length++], min_lod); /* Wa_14014595444: Populate MLOD as parameter 5 (twice). */ - if (devinfo->verx10 == 125 && op == FS_OPCODE_TXB && + if (devinfo->verx10 == 125 && op == ELK_FS_OPCODE_TXB && !inst->shadow_compare) bld.MOV(sources[length++], min_lod); } - const fs_reg src_payload = - fs_reg(VGRF, bld.shader->alloc.allocate(length * reg_width), - BRW_REGISTER_TYPE_F); + const elk_fs_reg src_payload = + elk_fs_reg(VGRF, bld.shader->alloc.allocate(length * reg_width), + ELK_REGISTER_TYPE_F); /* In case of 16-bit payload each component takes one full register in * both SIMD8H and SIMD16H modes. In both cases one reg can hold 16 * elements. In SIMD8H case hardware simply expects the components to be * padded (i.e., aligned on reg boundary). */ - fs_inst *load_payload_inst = + elk_fs_inst *load_payload_inst = emit_load_payload_with_padding(bld, src_payload, sources, length, header_size, REG_SIZE * reg_unit(devinfo)); unsigned mlen = load_payload_inst->size_written / REG_SIZE; @@ -1325,8 +1325,8 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, simd_mode = inst->exec_size <= 8 ? GFX10_SAMPLER_SIMD_MODE_SIMD8H : GFX10_SAMPLER_SIMD_MODE_SIMD16H; } else { - simd_mode = inst->exec_size <= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8 : - BRW_SAMPLER_SIMD_MODE_SIMD16; + simd_mode = inst->exec_size <= 8 ? ELK_SAMPLER_SIMD_MODE_SIMD8 : + ELK_SAMPLER_SIMD_MODE_SIMD16; } } else { if (payload_type_bit_size == 16) { @@ -1339,27 +1339,27 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, } /* Generate the SEND. */ - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = mlen; inst->header_size = header_size; assert(msg_type == sampler_msg_type(devinfo, op, inst->shadow_compare, min_lod.file != BAD_FILE)); - inst->sfid = BRW_SFID_SAMPLER; + inst->sfid = ELK_SFID_SAMPLER; if (surface.file == IMM && (sampler.file == IMM || sampler_handle.file != BAD_FILE)) { - inst->desc = brw_sampler_desc(devinfo, surface.ud, + inst->desc = elk_sampler_desc(devinfo, surface.ud, sampler.file == IMM ? sampler.ud % 16 : 0, msg_type, simd_mode, 0 /* return_format unused on gfx7+ */); - inst->src[0] = brw_imm_ud(0); - inst->src[1] = brw_imm_ud(0); + inst->src[0] = elk_imm_ud(0); + inst->src[1] = elk_imm_ud(0); } else if (surface_handle.file != BAD_FILE) { /* Bindless surface */ assert(devinfo->ver >= 9); - inst->desc = brw_sampler_desc(devinfo, + inst->desc = elk_sampler_desc(devinfo, GFX9_BTI_BINDLESS, sampler.file == IMM ? sampler.ud % 16 : 0, msg_type, @@ -1370,46 +1370,46 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, * header so we can leave the portion in the message descriptor 0. */ if (sampler_handle.file != BAD_FILE || sampler.file == IMM) { - inst->src[0] = brw_imm_ud(0); + inst->src[0] = elk_imm_ud(0); } else { const fs_builder ubld = bld.group(1, 0).exec_all(); - fs_reg desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); - ubld.SHL(desc, sampler, brw_imm_ud(8)); + elk_fs_reg desc = ubld.vgrf(ELK_REGISTER_TYPE_UD); + ubld.SHL(desc, sampler, elk_imm_ud(8)); inst->src[0] = component(desc, 0); } /* We assume that the driver provided the handle in the top 20 bits so * we can use the surface handle directly as the extended descriptor. */ - inst->src[1] = retype(surface_handle, BRW_REGISTER_TYPE_UD); + inst->src[1] = retype(surface_handle, ELK_REGISTER_TYPE_UD); inst->send_ex_bso = compiler->extended_bindless_surface_offset; } else { /* Immediate portion of the descriptor */ - inst->desc = brw_sampler_desc(devinfo, + inst->desc = elk_sampler_desc(devinfo, 0, /* surface */ 0, /* sampler */ msg_type, simd_mode, 0 /* return_format unused on gfx7+ */); const fs_builder ubld = bld.group(1, 0).exec_all(); - fs_reg desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg desc = ubld.vgrf(ELK_REGISTER_TYPE_UD); if (surface.equals(sampler)) { /* This case is common in GL */ - ubld.MUL(desc, surface, brw_imm_ud(0x101)); + ubld.MUL(desc, surface, elk_imm_ud(0x101)); } else { if (sampler_handle.file != BAD_FILE) { ubld.MOV(desc, surface); } else if (sampler.file == IMM) { - ubld.OR(desc, surface, brw_imm_ud(sampler.ud << 8)); + ubld.OR(desc, surface, elk_imm_ud(sampler.ud << 8)); } else { - ubld.SHL(desc, sampler, brw_imm_ud(8)); + ubld.SHL(desc, sampler, elk_imm_ud(8)); ubld.OR(desc, desc, surface); } } - ubld.AND(desc, desc, brw_imm_ud(0xfff)); + ubld.AND(desc, desc, elk_imm_ud(0xfff)); inst->src[0] = component(desc, 0); - inst->src[1] = brw_imm_ud(0); /* ex_desc */ + inst->src[1] = elk_imm_ud(0); /* ex_desc */ } inst->ex_desc = 0; @@ -1433,7 +1433,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, static unsigned get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, - opcode op, const fs_reg *src) + elk_opcode op, const elk_fs_reg *src) { unsigned src_type_size = 0; @@ -1442,7 +1442,7 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, */ for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) { if (src[i].file != BAD_FILE) { - src_type_size = brw_reg_type_to_size(src[i].type); + src_type_size = elk_reg_type_to_size(src[i].type); break; } } @@ -1456,11 +1456,11 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, * conversion. */ if (devinfo->verx10 < 125 || - (op != SHADER_OPCODE_TXF_CMS_W && - op != SHADER_OPCODE_TXF_CMS)) { + (op != ELK_SHADER_OPCODE_TXF_CMS_W && + op != ELK_SHADER_OPCODE_TXF_CMS)) { for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) { assert(src[i].file == BAD_FILE || - brw_reg_type_to_size(src[i].type) == src_type_size); + elk_reg_type_to_size(src[i].type) == src_type_size); } } #endif @@ -1477,31 +1477,31 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, * ld2dms REMOVEDBY(GEN:HAS:1406788836) */ - if (op == SHADER_OPCODE_TXF_CMS_W || - op == SHADER_OPCODE_TXF_CMS || - op == SHADER_OPCODE_TXF_UMS || - op == SHADER_OPCODE_TXF_MCS) + if (op == ELK_SHADER_OPCODE_TXF_CMS_W || + op == ELK_SHADER_OPCODE_TXF_CMS || + op == ELK_SHADER_OPCODE_TXF_UMS || + op == ELK_SHADER_OPCODE_TXF_MCS) src_type_size = 2; return src_type_size * 8; } static void -lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op) +lower_sampler_logical_send(const fs_builder &bld, elk_fs_inst *inst, elk_opcode op) { const intel_device_info *devinfo = bld.shader->devinfo; - const fs_reg coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE]; - const fs_reg shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C]; - const fs_reg lod = inst->src[TEX_LOGICAL_SRC_LOD]; - const fs_reg lod2 = inst->src[TEX_LOGICAL_SRC_LOD2]; - const fs_reg min_lod = inst->src[TEX_LOGICAL_SRC_MIN_LOD]; - const fs_reg sample_index = inst->src[TEX_LOGICAL_SRC_SAMPLE_INDEX]; - const fs_reg mcs = inst->src[TEX_LOGICAL_SRC_MCS]; - const fs_reg surface = inst->src[TEX_LOGICAL_SRC_SURFACE]; - const fs_reg sampler = inst->src[TEX_LOGICAL_SRC_SAMPLER]; - const fs_reg surface_handle = inst->src[TEX_LOGICAL_SRC_SURFACE_HANDLE]; - const fs_reg sampler_handle = inst->src[TEX_LOGICAL_SRC_SAMPLER_HANDLE]; - const fs_reg tg4_offset = inst->src[TEX_LOGICAL_SRC_TG4_OFFSET]; + const elk_fs_reg coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE]; + const elk_fs_reg shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C]; + const elk_fs_reg lod = inst->src[TEX_LOGICAL_SRC_LOD]; + const elk_fs_reg lod2 = inst->src[TEX_LOGICAL_SRC_LOD2]; + const elk_fs_reg min_lod = inst->src[TEX_LOGICAL_SRC_MIN_LOD]; + const elk_fs_reg sample_index = inst->src[TEX_LOGICAL_SRC_SAMPLE_INDEX]; + const elk_fs_reg mcs = inst->src[TEX_LOGICAL_SRC_MCS]; + const elk_fs_reg surface = inst->src[TEX_LOGICAL_SRC_SURFACE]; + const elk_fs_reg sampler = inst->src[TEX_LOGICAL_SRC_SAMPLER]; + const elk_fs_reg surface_handle = inst->src[TEX_LOGICAL_SRC_SURFACE_HANDLE]; + const elk_fs_reg sampler_handle = inst->src[TEX_LOGICAL_SRC_SAMPLER_HANDLE]; + const elk_fs_reg tg4_offset = inst->src[TEX_LOGICAL_SRC_TG4_OFFSET]; assert(inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM); const unsigned coord_components = inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud; assert(inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM); @@ -1544,7 +1544,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op) * Predicate the specified instruction on the vector mask. */ static void -emit_predicate_on_vector_mask(const fs_builder &bld, fs_inst *inst) +emit_predicate_on_vector_mask(const fs_builder &bld, elk_fs_inst *inst) { assert(bld.shader->stage == MESA_SHADER_FRAGMENT && bld.group() == inst->group && @@ -1552,73 +1552,73 @@ emit_predicate_on_vector_mask(const fs_builder &bld, fs_inst *inst) const fs_builder ubld = bld.exec_all().group(1, 0); - const fs_visitor &s = *bld.shader; - const fs_reg vector_mask = ubld.vgrf(BRW_REGISTER_TYPE_UW); + const elk_fs_visitor &s = *bld.shader; + const elk_fs_reg vector_mask = ubld.vgrf(ELK_REGISTER_TYPE_UW); ubld.UNDEF(vector_mask); - ubld.emit(SHADER_OPCODE_READ_SR_REG, vector_mask, brw_imm_ud(3)); + ubld.emit(ELK_SHADER_OPCODE_READ_SR_REG, vector_mask, elk_imm_ud(3)); const unsigned subreg = sample_mask_flag_subreg(s); - ubld.MOV(brw_flag_subreg(subreg + inst->group / 16), vector_mask); + ubld.MOV(elk_flag_subreg(subreg + inst->group / 16), vector_mask); if (inst->predicate) { - assert(inst->predicate == BRW_PREDICATE_NORMAL); + assert(inst->predicate == ELK_PREDICATE_NORMAL); assert(!inst->predicate_inverse); assert(inst->flag_subreg == 0); assert(s.devinfo->ver < 20); /* Combine the vector mask with the existing predicate by using a * vertical predication mode. */ - inst->predicate = BRW_PREDICATE_ALIGN1_ALLV; + inst->predicate = ELK_PREDICATE_ALIGN1_ALLV; } else { inst->flag_subreg = subreg; - inst->predicate = BRW_PREDICATE_NORMAL; + inst->predicate = ELK_PREDICATE_NORMAL; inst->predicate_inverse = false; } } static void -setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc, - const fs_reg &surface, const fs_reg &surface_handle) +setup_surface_descriptors(const fs_builder &bld, elk_fs_inst *inst, uint32_t desc, + const elk_fs_reg &surface, const elk_fs_reg &surface_handle) { const ASSERTED intel_device_info *devinfo = bld.shader->devinfo; - const brw_compiler *compiler = bld.shader->compiler; + const elk_compiler *compiler = bld.shader->compiler; /* We must have exactly one of surface and surface_handle */ assert((surface.file == BAD_FILE) != (surface_handle.file == BAD_FILE)); if (surface.file == IMM) { inst->desc = desc | (surface.ud & 0xff); - inst->src[0] = brw_imm_ud(0); - inst->src[1] = brw_imm_ud(0); /* ex_desc */ + inst->src[0] = elk_imm_ud(0); + inst->src[1] = elk_imm_ud(0); /* ex_desc */ } else if (surface_handle.file != BAD_FILE) { /* Bindless surface */ assert(devinfo->ver >= 9); inst->desc = desc | GFX9_BTI_BINDLESS; - inst->src[0] = brw_imm_ud(0); + inst->src[0] = elk_imm_ud(0); /* We assume that the driver provided the handle in the top 20 bits so * we can use the surface handle directly as the extended descriptor. */ - inst->src[1] = retype(surface_handle, BRW_REGISTER_TYPE_UD); + inst->src[1] = retype(surface_handle, ELK_REGISTER_TYPE_UD); inst->send_ex_bso = compiler->extended_bindless_surface_offset; } else { inst->desc = desc; const fs_builder ubld = bld.exec_all().group(1, 0); - fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD); - ubld.AND(tmp, surface, brw_imm_ud(0xff)); + elk_fs_reg tmp = ubld.vgrf(ELK_REGISTER_TYPE_UD); + ubld.AND(tmp, surface, elk_imm_ud(0xff)); inst->src[0] = component(tmp, 0); - inst->src[1] = brw_imm_ud(0); /* ex_desc */ + inst->src[1] = elk_imm_ud(0); /* ex_desc */ } } static void -setup_lsc_surface_descriptors(const fs_builder &bld, fs_inst *inst, - uint32_t desc, const fs_reg &surface) +setup_lsc_surface_descriptors(const fs_builder &bld, elk_fs_inst *inst, + uint32_t desc, const elk_fs_reg &surface) { const ASSERTED intel_device_info *devinfo = bld.shader->devinfo; - const brw_compiler *compiler = bld.shader->compiler; + const elk_compiler *compiler = bld.shader->compiler; - inst->src[0] = brw_imm_ud(0); /* desc */ + inst->src[0] = elk_imm_ud(0); /* desc */ enum lsc_addr_surface_type surf_type = lsc_msg_desc_addr_type(devinfo, desc); switch (surf_type) { @@ -1630,23 +1630,23 @@ setup_lsc_surface_descriptors(const fs_builder &bld, fs_inst *inst, /* We assume that the driver provided the handle in the top 20 bits so * we can use the surface handle directly as the extended descriptor. */ - inst->src[1] = retype(surface, BRW_REGISTER_TYPE_UD); + inst->src[1] = retype(surface, ELK_REGISTER_TYPE_UD); break; case LSC_ADDR_SURFTYPE_BTI: assert(surface.file != BAD_FILE); if (surface.file == IMM) { - inst->src[1] = brw_imm_ud(lsc_bti_ex_desc(devinfo, surface.ud)); + inst->src[1] = elk_imm_ud(lsc_bti_ex_desc(devinfo, surface.ud)); } else { const fs_builder ubld = bld.exec_all().group(1, 0); - fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD); - ubld.SHL(tmp, surface, brw_imm_ud(24)); + elk_fs_reg tmp = ubld.vgrf(ELK_REGISTER_TYPE_UD); + ubld.SHL(tmp, surface, elk_imm_ud(24)); inst->src[1] = component(tmp, 0); } break; case LSC_ADDR_SURFTYPE_FLAT: - inst->src[1] = brw_imm_ud(0); + inst->src[1] = elk_imm_ud(0); break; default: @@ -1655,19 +1655,19 @@ setup_lsc_surface_descriptors(const fs_builder &bld, fs_inst *inst, } static void -lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) +lower_surface_logical_send(const fs_builder &bld, elk_fs_inst *inst) { - const brw_compiler *compiler = bld.shader->compiler; + const elk_compiler *compiler = bld.shader->compiler; const intel_device_info *devinfo = bld.shader->devinfo; /* Get the logical send arguments. */ - const fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS]; - const fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA]; - const fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE]; - const fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE]; - const UNUSED fs_reg dims = inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS]; - const fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG]; - const fs_reg allow_sample_mask = + const elk_fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS]; + const elk_fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA]; + const elk_fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE]; + const elk_fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE]; + const UNUSED elk_fs_reg dims = inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS]; + const elk_fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG]; + const elk_fs_reg allow_sample_mask = inst->src[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK]; assert(arg.file == IMM); assert(allow_sample_mask.file == IMM); @@ -1677,23 +1677,23 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) const unsigned src_sz = inst->components_read(SURFACE_LOGICAL_SRC_DATA); const bool is_typed_access = - inst->opcode == SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL || - inst->opcode == SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL || - inst->opcode == SHADER_OPCODE_TYPED_ATOMIC_LOGICAL; + inst->opcode == ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL || + inst->opcode == ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL || + inst->opcode == ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL; const bool is_surface_access = is_typed_access || - inst->opcode == SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL || - inst->opcode == SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL || - inst->opcode == SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL; + inst->opcode == ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL || + inst->opcode == ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL || + inst->opcode == ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL; const bool is_stateless = - surface.file == IMM && (surface.ud == BRW_BTI_STATELESS || + surface.file == IMM && (surface.ud == ELK_BTI_STATELESS || surface.ud == GFX8_BTI_STATELESS_NON_COHERENT); const bool has_side_effects = inst->has_side_effects(); - fs_reg sample_mask = allow_sample_mask.ud ? brw_sample_mask_reg(bld) : - fs_reg(brw_imm_ud(0xffffffff)); + elk_fs_reg sample_mask = allow_sample_mask.ud ? elk_sample_mask_reg(bld) : + elk_fs_reg(elk_imm_ud(0xffffffff)); /* From the BDW PRM Volume 7, page 147: * @@ -1707,22 +1707,22 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) * * For all stateless A32 messages, we also need a header */ - fs_reg header; + elk_fs_reg header; if ((devinfo->ver < 9 && is_typed_access) || is_stateless) { fs_builder ubld = bld.exec_all().group(8, 0); - header = ubld.vgrf(BRW_REGISTER_TYPE_UD); + header = ubld.vgrf(ELK_REGISTER_TYPE_UD); if (is_stateless) { assert(!is_surface_access); - ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header); + ubld.emit(ELK_SHADER_OPCODE_SCRATCH_HEADER, header); } else { - ubld.MOV(header, brw_imm_d(0)); + ubld.MOV(header, elk_imm_d(0)); if (is_surface_access) ubld.group(1, 0).MOV(component(header, 7), sample_mask); } } const unsigned header_sz = header.file != BAD_FILE ? 1 : 0; - fs_reg payload, payload2; + elk_fs_reg payload, payload2; unsigned mlen, ex_mlen = 0; if (devinfo->ver >= 9 && (src.file == BAD_FILE || header.file == BAD_FILE)) { @@ -1742,8 +1742,8 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) } else { /* Allocate space for the payload. */ const unsigned sz = header_sz + addr_sz + src_sz; - payload = bld.vgrf(BRW_REGISTER_TYPE_UD, sz); - fs_reg *const components = new fs_reg[sz]; + payload = bld.vgrf(ELK_REGISTER_TYPE_UD, sz); + elk_fs_reg *const components = new elk_fs_reg[sz]; unsigned n = 0; /* Construct the payload. */ @@ -1767,26 +1767,26 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) */ if ((header.file == BAD_FILE || !is_surface_access) && sample_mask.file != BAD_FILE && sample_mask.file != IMM) - brw_emit_predicate_on_sample_mask(bld, inst); + elk_emit_predicate_on_sample_mask(bld, inst); uint32_t sfid; switch (inst->opcode) { - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: /* Byte scattered opcodes go through the normal data cache */ sfid = GFX7_SFID_DATAPORT_DATA_CACHE; break; - case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: sfid = devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE : devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE : - BRW_DATAPORT_READ_TARGET_RENDER_CACHE; + ELK_DATAPORT_READ_TARGET_RENDER_CACHE; break; - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: /* Untyped Surface messages go through the data cache but the SFID value * changed on Haswell. */ @@ -1795,9 +1795,9 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) GFX7_SFID_DATAPORT_DATA_CACHE); break; - case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: /* Typed surface messages go through the render cache on IVB and the * data cache on HSW+. */ @@ -1812,68 +1812,68 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) uint32_t desc; switch (inst->opcode) { - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: - desc = brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + desc = elk_dp_untyped_surface_rw_desc(devinfo, inst->exec_size, arg.ud, /* num_channels */ false /* write */); break; - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: - desc = brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + desc = elk_dp_untyped_surface_rw_desc(devinfo, inst->exec_size, arg.ud, /* num_channels */ true /* write */); break; - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: - desc = brw_dp_byte_scattered_rw_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + desc = elk_dp_byte_scattered_rw_desc(devinfo, inst->exec_size, arg.ud, /* bit_size */ false /* write */); break; - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: - desc = brw_dp_byte_scattered_rw_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + desc = elk_dp_byte_scattered_rw_desc(devinfo, inst->exec_size, arg.ud, /* bit_size */ true /* write */); break; - case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: assert(arg.ud == 32); /* bit_size */ - desc = brw_dp_dword_scattered_rw_desc(devinfo, inst->exec_size, + desc = elk_dp_dword_scattered_rw_desc(devinfo, inst->exec_size, false /* write */); break; - case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: assert(arg.ud == 32); /* bit_size */ - desc = brw_dp_dword_scattered_rw_desc(devinfo, inst->exec_size, + desc = elk_dp_dword_scattered_rw_desc(devinfo, inst->exec_size, true /* write */); break; - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - if (lsc_opcode_is_atomic_float((enum lsc_opcode) arg.ud)) { - desc = brw_dp_untyped_atomic_float_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + if (elk_lsc_opcode_is_atomic_float((enum elk_lsc_opcode) arg.ud)) { + desc = elk_dp_untyped_atomic_float_desc(devinfo, inst->exec_size, lsc_op_to_legacy_atomic(arg.ud), !inst->dst.is_null()); } else { - desc = brw_dp_untyped_atomic_desc(devinfo, inst->exec_size, + desc = elk_dp_untyped_atomic_desc(devinfo, inst->exec_size, lsc_op_to_legacy_atomic(arg.ud), !inst->dst.is_null()); } break; - case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: - desc = brw_dp_typed_surface_rw_desc(devinfo, inst->exec_size, inst->group, + case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + desc = elk_dp_typed_surface_rw_desc(devinfo, inst->exec_size, inst->group, arg.ud, /* num_channels */ false /* write */); break; - case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: - desc = brw_dp_typed_surface_rw_desc(devinfo, inst->exec_size, inst->group, + case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: + desc = elk_dp_typed_surface_rw_desc(devinfo, inst->exec_size, inst->group, arg.ud, /* num_channels */ true /* write */); break; - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: - desc = brw_dp_typed_atomic_desc(devinfo, inst->exec_size, inst->group, + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: + desc = elk_dp_typed_atomic_desc(devinfo, inst->exec_size, inst->group, lsc_op_to_legacy_atomic(arg.ud), !inst->dst.is_null()); break; @@ -1883,7 +1883,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) } /* Update the original instruction. */ - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = mlen; inst->ex_mlen = ex_mlen; inst->header_size = header_sz; @@ -1917,20 +1917,20 @@ lsc_bits_to_data_size(unsigned bit_size) } static void -lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) +lower_lsc_surface_logical_send(const fs_builder &bld, elk_fs_inst *inst) { - const brw_compiler *compiler = bld.shader->compiler; + const elk_compiler *compiler = bld.shader->compiler; const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); /* Get the logical send arguments. */ - const fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS]; - const fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA]; - const fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE]; - const fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE]; - const UNUSED fs_reg dims = inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS]; - const fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG]; - const fs_reg allow_sample_mask = + const elk_fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS]; + const elk_fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA]; + const elk_fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE]; + const elk_fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE]; + const UNUSED elk_fs_reg dims = inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS]; + const elk_fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG]; + const elk_fs_reg allow_sample_mask = inst->src[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK]; assert(arg.file == IMM); assert(allow_sample_mask.file == IMM); @@ -1944,7 +1944,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) const bool has_side_effects = inst->has_side_effects(); unsigned ex_mlen = 0; - fs_reg payload, payload2; + elk_fs_reg payload, payload2; payload = bld.move_to_vgrf(addr, addr_sz); if (src.file != BAD_FILE) { payload2 = bld.move_to_vgrf(src, src_comps); @@ -1952,10 +1952,10 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) } /* Predicate the instruction on the sample mask if needed */ - fs_reg sample_mask = allow_sample_mask.ud ? brw_sample_mask_reg(bld) : - fs_reg(brw_imm_ud(0xffffffff)); + elk_fs_reg sample_mask = allow_sample_mask.ud ? elk_sample_mask_reg(bld) : + elk_fs_reg(elk_imm_ud(0xffffffff)); if (sample_mask.file != BAD_FILE && sample_mask.file != IMM) - brw_emit_predicate_on_sample_mask(bld, inst); + elk_emit_predicate_on_sample_mask(bld, inst); if (surface.file == IMM && surface.ud == GFX7_BTI_SLM) inst->sfid = GFX12_SFID_SLM; @@ -1963,7 +1963,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) inst->sfid = GFX12_SFID_UGM; /* We should have exactly one of surface and surface_handle. For scratch - * messages generated by brw_fs_nir.cpp we also allow a special value to + * messages generated by elk_fs_nir.cpp we also allow a special value to * know what heap base we should use in STATE_BASE_ADDRESS (SS = Surface * State Offset, or BSS = Bindless Surface State Offset). */ @@ -1987,7 +1987,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) surf_type = LSC_ADDR_SURFTYPE_BTI; switch (inst->opcode) { - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD_CMASK, inst->exec_size, surf_type, LSC_ADDR_SIZE_A32, 1 /* num_coordinates */, @@ -1996,7 +1996,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS), true /* has_dest */); break; - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE_CMASK, inst->exec_size, surf_type, LSC_ADDR_SIZE_A32, 1 /* num_coordinates */, @@ -2005,13 +2005,13 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE(devinfo, STORE, L1STATE_L3MOCS), false /* has_dest */); break; - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: { + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: { /* Bspec: Atomic instruction -> Cache section: * * Atomic messages are always forced to "un-cacheable" in the L1 * cache. */ - enum lsc_opcode opcode = (enum lsc_opcode) arg.ud; + enum elk_lsc_opcode opcode = (enum elk_lsc_opcode) arg.ud; inst->desc = lsc_msg_desc(devinfo, opcode, inst->exec_size, surf_type, LSC_ADDR_SIZE_A32, @@ -2023,7 +2023,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) !inst->dst.is_null()); break; } - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, inst->exec_size, surf_type, LSC_ADDR_SIZE_A32, 1 /* num_coordinates */, @@ -2033,7 +2033,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS), true /* has_dest */); break; - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE, inst->exec_size, surf_type, LSC_ADDR_SIZE_A32, 1 /* num_coordinates */, @@ -2048,7 +2048,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) } /* Update the original instruction. */ - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc); inst->ex_mlen = ex_mlen; inst->header_size = 0; @@ -2060,7 +2060,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) inst->resize_sources(4); if (non_bindless) { - inst->src[0] = brw_imm_ud(0); /* desc */ + inst->src[0] = elk_imm_ud(0); /* desc */ inst->src[1] = surface_handle; /* ex_desc */ } else { setup_lsc_surface_descriptors(bld, inst, inst->desc, @@ -2074,46 +2074,46 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_lsc_block_logical_send(const fs_builder &bld, fs_inst *inst) +lower_lsc_block_logical_send(const fs_builder &bld, elk_fs_inst *inst) { - const brw_compiler *compiler = bld.shader->compiler; + const elk_compiler *compiler = bld.shader->compiler; const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); /* Get the logical send arguments. */ - const fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS]; - const fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA]; - const fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE]; - const fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE]; - const fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG]; + const elk_fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS]; + const elk_fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA]; + const elk_fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE]; + const elk_fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE]; + const elk_fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG]; assert(arg.file == IMM); assert(inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == BAD_FILE); assert(inst->src[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK].file == BAD_FILE); const bool is_stateless = - surface.file == IMM && (surface.ud == BRW_BTI_STATELESS || + surface.file == IMM && (surface.ud == ELK_BTI_STATELESS || surface.ud == GFX8_BTI_STATELESS_NON_COHERENT); const bool has_side_effects = inst->has_side_effects(); - const bool write = inst->opcode == SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL; + const bool write = inst->opcode == ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL; fs_builder ubld = bld.exec_all().group(1, 0); - fs_reg stateless_ex_desc; + elk_fs_reg stateless_ex_desc; if (is_stateless) { - stateless_ex_desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); + stateless_ex_desc = ubld.vgrf(ELK_REGISTER_TYPE_UD); ubld.AND(stateless_ex_desc, - retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(31, 10))); + retype(elk_vec1_grf(0, 5), ELK_REGISTER_TYPE_UD), + elk_imm_ud(INTEL_MASK(31, 10))); } - fs_reg data; + elk_fs_reg data; if (write) { const unsigned src_sz = inst->components_read(SURFACE_LOGICAL_SRC_DATA); - data = retype(bld.move_to_vgrf(src, src_sz), BRW_REGISTER_TYPE_UD); + data = retype(bld.move_to_vgrf(src, src_sz), ELK_REGISTER_TYPE_UD); } - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; if (surface.file == IMM && surface.ud == GFX7_BTI_SLM) inst->sfid = GFX12_SFID_SLM; else @@ -2148,7 +2148,7 @@ lower_lsc_block_logical_send(const fs_builder &bld, fs_inst *inst) inst->resize_sources(4); if (stateless_ex_desc.file != BAD_FILE) { - inst->src[0] = brw_imm_ud(0); /* desc */ + inst->src[0] = elk_imm_ud(0); /* desc */ inst->src[1] = stateless_ex_desc; /* ex_desc */ } else { setup_lsc_surface_descriptors(bld, inst, inst->desc, @@ -2160,56 +2160,56 @@ lower_lsc_block_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst) +lower_surface_block_logical_send(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->ver >= 9); /* Get the logical send arguments. */ - const fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS]; - const fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA]; - const fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE]; - const fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE]; - const fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG]; + const elk_fs_reg addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS]; + const elk_fs_reg src = inst->src[SURFACE_LOGICAL_SRC_DATA]; + const elk_fs_reg surface = inst->src[SURFACE_LOGICAL_SRC_SURFACE]; + const elk_fs_reg surface_handle = inst->src[SURFACE_LOGICAL_SRC_SURFACE_HANDLE]; + const elk_fs_reg arg = inst->src[SURFACE_LOGICAL_SRC_IMM_ARG]; assert(arg.file == IMM); assert(inst->src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == BAD_FILE); assert(inst->src[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK].file == BAD_FILE); const bool is_stateless = - surface.file == IMM && (surface.ud == BRW_BTI_STATELESS || + surface.file == IMM && (surface.ud == ELK_BTI_STATELESS || surface.ud == GFX8_BTI_STATELESS_NON_COHERENT); const bool has_side_effects = inst->has_side_effects(); const bool align_16B = - inst->opcode != SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL; + inst->opcode != ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL; - const bool write = inst->opcode == SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL; + const bool write = inst->opcode == ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL; /* The address is stored in the header. See MH_A32_GO and MH_BTS_GO. */ fs_builder ubld = bld.exec_all().group(8, 0); - fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg header = ubld.vgrf(ELK_REGISTER_TYPE_UD); if (is_stateless) - ubld.emit(SHADER_OPCODE_SCRATCH_HEADER, header); + ubld.emit(ELK_SHADER_OPCODE_SCRATCH_HEADER, header); else - ubld.MOV(header, brw_imm_d(0)); + ubld.MOV(header, elk_imm_d(0)); /* Address in OWord units when aligned to OWords. */ if (align_16B) - ubld.group(1, 0).SHR(component(header, 2), addr, brw_imm_ud(4)); + ubld.group(1, 0).SHR(component(header, 2), addr, elk_imm_ud(4)); else ubld.group(1, 0).MOV(component(header, 2), addr); - fs_reg data; + elk_fs_reg data; unsigned ex_mlen = 0; if (write) { const unsigned src_sz = inst->components_read(SURFACE_LOGICAL_SRC_DATA); - data = retype(bld.move_to_vgrf(src, src_sz), BRW_REGISTER_TYPE_UD); + data = retype(bld.move_to_vgrf(src, src_sz), ELK_REGISTER_TYPE_UD); ex_mlen = src_sz * type_sz(src.type) * inst->exec_size / REG_SIZE; } - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = 1; inst->ex_mlen = ex_mlen; inst->header_size = 1; @@ -2218,7 +2218,7 @@ lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst) inst->sfid = GFX7_SFID_DATAPORT_DATA_CACHE; - const uint32_t desc = brw_dp_oword_block_rw_desc(devinfo, align_16B, + const uint32_t desc = elk_dp_oword_block_rw_desc(devinfo, align_16B, arg.ud, write); setup_surface_descriptors(bld, inst, desc, surface, surface_handle); @@ -2228,27 +2228,27 @@ lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst) inst->src[3] = data; } -static fs_reg -emit_a64_oword_block_header(const fs_builder &bld, const fs_reg &addr) +static elk_fs_reg +emit_a64_oword_block_header(const fs_builder &bld, const elk_fs_reg &addr) { const fs_builder ubld = bld.exec_all().group(8, 0); assert(type_sz(addr.type) == 8 && addr.stride == 0); - fs_reg expanded_addr = addr; + elk_fs_reg expanded_addr = addr; if (addr.file == UNIFORM) { /* We can't do stride 1 with the UNIFORM file, it requires stride 0 */ - expanded_addr = ubld.vgrf(BRW_REGISTER_TYPE_UQ); + expanded_addr = ubld.vgrf(ELK_REGISTER_TYPE_UQ); expanded_addr.stride = 0; - ubld.MOV(expanded_addr, retype(addr, BRW_REGISTER_TYPE_UQ)); + ubld.MOV(expanded_addr, retype(addr, ELK_REGISTER_TYPE_UQ)); } - fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD); - ubld.MOV(header, brw_imm_ud(0)); + elk_fs_reg header = ubld.vgrf(ELK_REGISTER_TYPE_UD); + ubld.MOV(header, elk_imm_ud(0)); /* Use a 2-wide MOV to fill out the address */ - fs_reg addr_vec2 = expanded_addr; - addr_vec2.type = BRW_REGISTER_TYPE_UD; + elk_fs_reg addr_vec2 = expanded_addr; + addr_vec2.type = ELK_REGISTER_TYPE_UD; addr_vec2.stride = 1; ubld.group(2, 0).MOV(header, addr_vec2); @@ -2256,7 +2256,7 @@ emit_a64_oword_block_header(const fs_builder &bld, const fs_reg &addr) } static void -emit_fragment_mask(const fs_builder &bld, fs_inst *inst) +emit_fragment_mask(const fs_builder &bld, elk_fs_inst *inst) { assert(inst->src[A64_LOGICAL_ENABLE_HELPERS].file == IMM); const bool enable_helpers = inst->src[A64_LOGICAL_ENABLE_HELPERS].ud; @@ -2272,17 +2272,17 @@ emit_fragment_mask(const fs_builder &bld, fs_inst *inst) if (enable_helpers) emit_predicate_on_vector_mask(bld, inst); else if (inst->has_side_effects()) - brw_emit_predicate_on_sample_mask(bld, inst); + elk_emit_predicate_on_sample_mask(bld, inst); } static void -lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) +lower_lsc_a64_logical_send(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; /* Get the logical send arguments. */ - const fs_reg addr = inst->src[A64_LOGICAL_ADDRESS]; - const fs_reg src = inst->src[A64_LOGICAL_SRC]; + const elk_fs_reg addr = inst->src[A64_LOGICAL_ADDRESS]; + const elk_fs_reg src = inst->src[A64_LOGICAL_SRC]; const unsigned src_sz = type_sz(src.type); const unsigned dst_sz = type_sz(inst->dst.type); @@ -2291,13 +2291,13 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) const unsigned arg = inst->src[A64_LOGICAL_ARG].ud; const bool has_side_effects = inst->has_side_effects(); - fs_reg payload = retype(bld.move_to_vgrf(addr, 1), BRW_REGISTER_TYPE_UD); - fs_reg payload2 = retype(bld.move_to_vgrf(src, src_comps), - BRW_REGISTER_TYPE_UD); + elk_fs_reg payload = retype(bld.move_to_vgrf(addr, 1), ELK_REGISTER_TYPE_UD); + elk_fs_reg payload2 = retype(bld.move_to_vgrf(src, src_comps), + ELK_REGISTER_TYPE_UD); unsigned ex_mlen = src_comps * src_sz * inst->exec_size / REG_SIZE; switch (inst->opcode) { - case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD_CMASK, inst->exec_size, LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64, 1 /* num_coordinates */, @@ -2306,7 +2306,7 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS), true /* has_dest */); break; - case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE_CMASK, inst->exec_size, LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64, 1 /* num_coordinates */, @@ -2315,7 +2315,7 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE(devinfo, STORE, L1STATE_L3MOCS), false /* has_dest */); break; - case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, inst->exec_size, LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64, 1 /* num_coordinates */, @@ -2325,7 +2325,7 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS), true /* has_dest */); break; - case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE, inst->exec_size, LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64, 1 /* num_coordinates */, @@ -2335,13 +2335,13 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE(devinfo, STORE, L1STATE_L3MOCS), false /* has_dest */); break; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: { + case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: { /* Bspec: Atomic instruction -> Cache section: * * Atomic messages are always forced to "un-cacheable" in the L1 * cache. */ - enum lsc_opcode opcode = (enum lsc_opcode) arg; + enum elk_lsc_opcode opcode = (enum elk_lsc_opcode) arg; inst->desc = lsc_msg_desc(devinfo, opcode, inst->exec_size, LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A64, 1 /* num_coordinates */, @@ -2352,8 +2352,8 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) !inst->dst.is_null()); break; } - case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: - case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: inst->exec_size = 1; inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, @@ -2367,7 +2367,7 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS), true /* has_dest */); break; - case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: inst->exec_size = 1; inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE, @@ -2390,7 +2390,7 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) emit_fragment_mask(bld, inst); /* Update the original instruction. */ - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc); inst->ex_mlen = ex_mlen; inst->header_size = 0; @@ -2400,29 +2400,29 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) /* Set up SFID and descriptors */ inst->sfid = GFX12_SFID_UGM; inst->resize_sources(4); - inst->src[0] = brw_imm_ud(0); /* desc */ - inst->src[1] = brw_imm_ud(0); /* ex_desc */ + inst->src[0] = elk_imm_ud(0); /* desc */ + inst->src[1] = elk_imm_ud(0); /* ex_desc */ inst->src[2] = payload; inst->src[3] = payload2; } static void -lower_a64_logical_send(const fs_builder &bld, fs_inst *inst) +lower_a64_logical_send(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; - const fs_reg addr = inst->src[A64_LOGICAL_ADDRESS]; - const fs_reg src = inst->src[A64_LOGICAL_SRC]; + const elk_fs_reg addr = inst->src[A64_LOGICAL_ADDRESS]; + const elk_fs_reg src = inst->src[A64_LOGICAL_SRC]; const unsigned src_comps = inst->components_read(1); assert(inst->src[A64_LOGICAL_ARG].file == IMM); const unsigned arg = inst->src[A64_LOGICAL_ARG].ud; const bool has_side_effects = inst->has_side_effects(); - fs_reg payload, payload2; + elk_fs_reg payload, payload2; unsigned mlen, ex_mlen = 0, header_size = 0; - if (inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL || - inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL || - inst->opcode == SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL) { + if (inst->opcode == ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL || + inst->opcode == ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL || + inst->opcode == ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL) { assert(devinfo->ver >= 9); /* OWORD messages only take a scalar address in a header */ @@ -2430,90 +2430,90 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst) header_size = 1; payload = emit_a64_oword_block_header(bld, addr); - if (inst->opcode == SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL) { + if (inst->opcode == ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL) { ex_mlen = src_comps * type_sz(src.type) * inst->exec_size / REG_SIZE; payload2 = retype(bld.move_to_vgrf(src, src_comps), - BRW_REGISTER_TYPE_UD); + ELK_REGISTER_TYPE_UD); } } else if (devinfo->ver >= 9) { /* On Skylake and above, we have SENDS */ mlen = 2 * (inst->exec_size / 8); ex_mlen = src_comps * type_sz(src.type) * inst->exec_size / REG_SIZE; - payload = retype(bld.move_to_vgrf(addr, 1), BRW_REGISTER_TYPE_UD); + payload = retype(bld.move_to_vgrf(addr, 1), ELK_REGISTER_TYPE_UD); payload2 = retype(bld.move_to_vgrf(src, src_comps), - BRW_REGISTER_TYPE_UD); + ELK_REGISTER_TYPE_UD); } else { /* Add two because the address is 64-bit */ const unsigned dwords = 2 + src_comps; mlen = dwords * (inst->exec_size / 8); - fs_reg sources[5]; + elk_fs_reg sources[5]; sources[0] = addr; for (unsigned i = 0; i < src_comps; i++) sources[1 + i] = offset(src, bld, i); - payload = bld.vgrf(BRW_REGISTER_TYPE_UD, dwords); + payload = bld.vgrf(ELK_REGISTER_TYPE_UD, dwords); bld.LOAD_PAYLOAD(payload, sources, 1 + src_comps, 0); } uint32_t desc; switch (inst->opcode) { - case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: - desc = brw_dp_a64_untyped_surface_rw_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: + desc = elk_dp_a64_untyped_surface_rw_desc(devinfo, inst->exec_size, arg, /* num_channels */ false /* write */); break; - case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: - desc = brw_dp_a64_untyped_surface_rw_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: + desc = elk_dp_a64_untyped_surface_rw_desc(devinfo, inst->exec_size, arg, /* num_channels */ true /* write */); break; - case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: - desc = brw_dp_a64_oword_block_rw_desc(devinfo, + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: + desc = elk_dp_a64_oword_block_rw_desc(devinfo, true, /* align_16B */ arg, /* num_dwords */ false /* write */); break; - case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: - desc = brw_dp_a64_oword_block_rw_desc(devinfo, + case ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + desc = elk_dp_a64_oword_block_rw_desc(devinfo, false, /* align_16B */ arg, /* num_dwords */ false /* write */); break; - case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: - desc = brw_dp_a64_oword_block_rw_desc(devinfo, + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: + desc = elk_dp_a64_oword_block_rw_desc(devinfo, true, /* align_16B */ arg, /* num_dwords */ true /* write */); break; - case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: - desc = brw_dp_a64_byte_scattered_rw_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: + desc = elk_dp_a64_byte_scattered_rw_desc(devinfo, inst->exec_size, arg, /* bit_size */ false /* write */); break; - case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: - desc = brw_dp_a64_byte_scattered_rw_desc(devinfo, inst->exec_size, + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: + desc = elk_dp_a64_byte_scattered_rw_desc(devinfo, inst->exec_size, arg, /* bit_size */ true /* write */); break; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - if (lsc_opcode_is_atomic_float((enum lsc_opcode) arg)) { + case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: + if (elk_lsc_opcode_is_atomic_float((enum elk_lsc_opcode) arg)) { desc = - brw_dp_a64_untyped_atomic_float_desc(devinfo, inst->exec_size, + elk_dp_a64_untyped_atomic_float_desc(devinfo, inst->exec_size, type_sz(inst->dst.type) * 8, lsc_op_to_legacy_atomic(arg), !inst->dst.is_null()); } else { - desc = brw_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, + desc = elk_dp_a64_untyped_atomic_desc(devinfo, inst->exec_size, type_sz(inst->dst.type) * 8, lsc_op_to_legacy_atomic(arg), !inst->dst.is_null()); @@ -2528,7 +2528,7 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst) emit_fragment_mask(bld, inst); /* Update the original instruction. */ - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = mlen; inst->ex_mlen = ex_mlen; inst->header_size = header_size; @@ -2539,38 +2539,38 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst) inst->sfid = HSW_SFID_DATAPORT_DATA_CACHE_1; inst->desc = desc; inst->resize_sources(4); - inst->src[0] = brw_imm_ud(0); /* desc */ - inst->src[1] = brw_imm_ud(0); /* ex_desc */ + inst->src[0] = elk_imm_ud(0); /* desc */ + inst->src[1] = elk_imm_ud(0); /* ex_desc */ inst->src[2] = payload; inst->src[3] = payload2; } static void lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld, - fs_inst *inst) + elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; - ASSERTED const brw_compiler *compiler = bld.shader->compiler; + ASSERTED const elk_compiler *compiler = bld.shader->compiler; - fs_reg surface = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE]; - fs_reg surface_handle = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE_HANDLE]; - fs_reg offset_B = inst->src[PULL_VARYING_CONSTANT_SRC_OFFSET]; - fs_reg alignment_B = inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT]; + elk_fs_reg surface = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE]; + elk_fs_reg surface_handle = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE_HANDLE]; + elk_fs_reg offset_B = inst->src[PULL_VARYING_CONSTANT_SRC_OFFSET]; + elk_fs_reg alignment_B = inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT]; /* We are switching the instruction from an ALU-like instruction to a * send-from-grf instruction. Since sends can't handle strides or * source modifiers, we have to make a copy of the offset source. */ - fs_reg ubo_offset = bld.move_to_vgrf(offset_B, 1); + elk_fs_reg ubo_offset = bld.move_to_vgrf(offset_B, 1); enum lsc_addr_surface_type surf_type = surface_handle.file == BAD_FILE ? LSC_ADDR_SURFTYPE_BTI : LSC_ADDR_SURFTYPE_BSS; - assert(alignment_B.file == BRW_IMMEDIATE_VALUE); + assert(alignment_B.file == ELK_IMMEDIATE_VALUE); unsigned alignment = alignment_B.ud; - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->sfid = GFX12_SFID_UGM; inst->resize_sources(3); inst->send_ex_bso = surf_type == LSC_ADDR_SURFTYPE_BSS && @@ -2578,7 +2578,7 @@ lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld, assert(!compiler->indirect_ubos_use_sampler); - inst->src[0] = brw_imm_ud(0); + inst->src[0] = elk_imm_ud(0); inst->src[2] = ubo_offset; /* payload */ if (alignment >= 4) { @@ -2627,8 +2627,8 @@ lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld, bld.emit(*inst); /* Offset the source */ - inst->src[2] = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.ADD(inst->src[2], ubo_offset, brw_imm_ud(c * 4)); + inst->src[2] = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.ADD(inst->src[2], ubo_offset, elk_imm_ud(c * 4)); /* Offset the destination */ inst->dst = offset(inst->dst, bld, 1); @@ -2637,27 +2637,27 @@ lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld, } static void -lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) +lower_varying_pull_constant_logical_send(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; - const brw_compiler *compiler = bld.shader->compiler; + const elk_compiler *compiler = bld.shader->compiler; if (devinfo->ver >= 7) { - fs_reg surface = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE]; - fs_reg surface_handle = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE_HANDLE]; - fs_reg offset_B = inst->src[PULL_VARYING_CONSTANT_SRC_OFFSET]; + elk_fs_reg surface = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE]; + elk_fs_reg surface_handle = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE_HANDLE]; + elk_fs_reg offset_B = inst->src[PULL_VARYING_CONSTANT_SRC_OFFSET]; /* We are switching the instruction from an ALU-like instruction to a * send-from-grf instruction. Since sends can't handle strides or * source modifiers, we have to make a copy of the offset source. */ - fs_reg ubo_offset = bld.vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg ubo_offset = bld.vgrf(ELK_REGISTER_TYPE_UD); bld.MOV(ubo_offset, offset_B); - assert(inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT].file == BRW_IMMEDIATE_VALUE); + assert(inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT].file == ELK_IMMEDIATE_VALUE); unsigned alignment = inst->src[PULL_VARYING_CONSTANT_SRC_ALIGNMENT].ud; - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = inst->exec_size / 8; inst->resize_sources(3); @@ -2666,17 +2666,17 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) if (compiler->indirect_ubos_use_sampler) { const unsigned simd_mode = - inst->exec_size <= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8 : - BRW_SAMPLER_SIMD_MODE_SIMD16; - const uint32_t desc = brw_sampler_desc(devinfo, 0, 0, + inst->exec_size <= 8 ? ELK_SAMPLER_SIMD_MODE_SIMD8 : + ELK_SAMPLER_SIMD_MODE_SIMD16; + const uint32_t desc = elk_sampler_desc(devinfo, 0, 0, GFX5_SAMPLER_MESSAGE_SAMPLE_LD, simd_mode, 0); - inst->sfid = BRW_SFID_SAMPLER; + inst->sfid = ELK_SFID_SAMPLER; setup_surface_descriptors(bld, inst, desc, surface, surface_handle); } else if (alignment >= 4) { const uint32_t desc = - brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size, + elk_dp_untyped_surface_rw_desc(devinfo, inst->exec_size, 4, /* num_channels */ false /* write */); @@ -2686,7 +2686,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) setup_surface_descriptors(bld, inst, desc, surface, surface_handle); } else { const uint32_t desc = - brw_dp_byte_scattered_rw_desc(devinfo, inst->exec_size, + elk_dp_byte_scattered_rw_desc(devinfo, inst->exec_size, 32, /* bit_size */ false /* write */); @@ -2708,24 +2708,24 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) bld.emit(*inst); /* Offset the source */ - inst->src[2] = bld.vgrf(BRW_REGISTER_TYPE_UD); - bld.ADD(inst->src[2], ubo_offset, brw_imm_ud(c * 4)); + inst->src[2] = bld.vgrf(ELK_REGISTER_TYPE_UD); + bld.ADD(inst->src[2], ubo_offset, elk_imm_ud(c * 4)); /* Offset the destination */ inst->dst = offset(inst->dst, bld, 1); } } } else { - fs_reg surface = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE]; - fs_reg offset = inst->src[PULL_VARYING_CONSTANT_SRC_OFFSET]; + elk_fs_reg surface = inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE]; + elk_fs_reg offset = inst->src[PULL_VARYING_CONSTANT_SRC_OFFSET]; assert(inst->src[PULL_VARYING_CONSTANT_SRC_SURFACE_HANDLE].file == BAD_FILE); - const fs_reg payload(MRF, FIRST_PULL_LOAD_MRF(devinfo->ver), - BRW_REGISTER_TYPE_UD); + const elk_fs_reg payload(MRF, FIRST_PULL_LOAD_MRF(devinfo->ver), + ELK_REGISTER_TYPE_UD); bld.MOV(byte_offset(payload, REG_SIZE), offset); - inst->opcode = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4; + inst->opcode = ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4; inst->base_mrf = payload.nr; inst->header_size = 1; inst->mlen = 1 + inst->exec_size / 8; @@ -2736,7 +2736,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_math_logical_send(const fs_builder &bld, fs_inst *inst) +lower_math_logical_send(const fs_builder &bld, elk_fs_inst *inst) { assert(bld.shader->devinfo->ver < 6); @@ -2753,42 +2753,42 @@ lower_math_logical_send(const fs_builder &bld, fs_inst *inst) * "Operand1[7]. For the INT DIV functions, this operand is the * numerator." */ - const bool is_int_div = inst->opcode != SHADER_OPCODE_POW; - const fs_reg src0 = is_int_div ? inst->src[1] : inst->src[0]; - const fs_reg src1 = is_int_div ? inst->src[0] : inst->src[1]; + const bool is_int_div = inst->opcode != ELK_SHADER_OPCODE_POW; + const elk_fs_reg src0 = is_int_div ? inst->src[1] : inst->src[0]; + const elk_fs_reg src1 = is_int_div ? inst->src[0] : inst->src[1]; inst->resize_sources(1); inst->src[0] = src0; assert(inst->exec_size == 8); - bld.MOV(fs_reg(MRF, inst->base_mrf + 1, src1.type), src1); + bld.MOV(elk_fs_reg(MRF, inst->base_mrf + 1, src1.type), src1); } } static void -lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, - const struct brw_wm_prog_key *wm_prog_key, - const struct brw_wm_prog_data *wm_prog_data) +lower_interpolator_logical_send(const fs_builder &bld, elk_fs_inst *inst, + const struct elk_wm_prog_key *wm_prog_key, + const struct elk_wm_prog_data *wm_prog_data) { const intel_device_info *devinfo = bld.shader->devinfo; /* We have to send something */ - fs_reg payload = brw_vec8_grf(0, 0); + elk_fs_reg payload = elk_vec8_grf(0, 0); unsigned mlen = 1; unsigned mode; switch (inst->opcode) { - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: assert(inst->src[INTERP_SRC_OFFSET].file == BAD_FILE); mode = GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE; break; - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: assert(inst->src[INTERP_SRC_OFFSET].file == BAD_FILE); mode = GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET; break; - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: payload = inst->src[INTERP_SRC_OFFSET]; mlen = 2 * inst->exec_size / 8; mode = GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET; @@ -2801,9 +2801,9 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, const bool dynamic_mode = inst->src[INTERP_SRC_DYNAMIC_MODE].file != BAD_FILE; - fs_reg desc = inst->src[INTERP_SRC_MSG_DESC]; + elk_fs_reg desc = inst->src[INTERP_SRC_MSG_DESC]; uint32_t desc_imm = - brw_pixel_interp_desc(devinfo, + elk_pixel_interp_desc(devinfo, /* Leave the mode at 0 if persample_dispatch is * dynamic, it will be ORed in below. */ @@ -2812,15 +2812,15 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, false /* coarse_pixel_rate */, inst->exec_size, inst->group); - if (wm_prog_data->coarse_pixel_dispatch == BRW_ALWAYS) { + if (wm_prog_data->coarse_pixel_dispatch == ELK_ALWAYS) { desc_imm |= (1 << 15); - } else if (wm_prog_data->coarse_pixel_dispatch == BRW_SOMETIMES) { + } else if (wm_prog_data->coarse_pixel_dispatch == ELK_SOMETIMES) { STATIC_ASSERT(INTEL_MSAA_FLAG_COARSE_PI_MSG == (1 << 15)); - fs_reg orig_desc = desc; + elk_fs_reg orig_desc = desc; const fs_builder &ubld = bld.exec_all().group(8, 0); - desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); + desc = ubld.vgrf(ELK_REGISTER_TYPE_UD); ubld.AND(desc, dynamic_msaa_flags(wm_prog_data), - brw_imm_ud(INTEL_MSAA_FLAG_COARSE_PI_MSG)); + elk_imm_ud(INTEL_MSAA_FLAG_COARSE_PI_MSG)); /* And, if it's AT_OFFSET, we might have a non-trivial descriptor */ if (orig_desc.file == IMM) { @@ -2832,7 +2832,7 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, /* If persample_dispatch is dynamic, select the interpolation mode * dynamically and OR into the descriptor to complete the static part - * generated by brw_pixel_interp_desc(). + * generated by elk_pixel_interp_desc(). * * Why does this work? If you look at the SKL PRMs, Volume 7: * 3D-Media-GPGPU, Shared Functions Pixel Interpolater, you'll see that @@ -2846,11 +2846,11 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, * components of "Per Message Offset”, which will give us the pixel offset 0x0. */ if (dynamic_mode) { - fs_reg orig_desc = desc; + elk_fs_reg orig_desc = desc; const fs_builder &ubld = bld.exec_all().group(8, 0); - desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); + desc = ubld.vgrf(ELK_REGISTER_TYPE_UD); - /* The predicate should have been built in brw_fs_nir.cpp when emitting + /* The predicate should have been built in elk_fs_nir.cpp when emitting * NIR code. This guarantees that we do not have incorrect interactions * with the flag register holding the predication result. */ @@ -2858,24 +2858,24 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, /* Not using SEL here because we would generate an instruction with 2 * immediate sources which is not supported by HW. */ - set_predicate_inv(BRW_PREDICATE_NORMAL, false, - ubld.MOV(desc, brw_imm_ud(orig_desc.ud | + set_predicate_inv(ELK_PREDICATE_NORMAL, false, + ubld.MOV(desc, elk_imm_ud(orig_desc.ud | GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE << 12))); - set_predicate_inv(BRW_PREDICATE_NORMAL, true, - ubld.MOV(desc, brw_imm_ud(orig_desc.ud | + set_predicate_inv(ELK_PREDICATE_NORMAL, true, + ubld.MOV(desc, elk_imm_ud(orig_desc.ud | GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET << 12))); } else { - set_predicate_inv(BRW_PREDICATE_NORMAL, false, + set_predicate_inv(ELK_PREDICATE_NORMAL, false, ubld.OR(desc, orig_desc, - brw_imm_ud(GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE << 12))); - set_predicate_inv(BRW_PREDICATE_NORMAL, true, + elk_imm_ud(GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE << 12))); + set_predicate_inv(ELK_PREDICATE_NORMAL, true, ubld.OR(desc, orig_desc, - brw_imm_ud(GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET << 12))); + elk_imm_ud(GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET << 12))); } } assert(bld.shader->devinfo->ver >= 7); - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->sfid = GFX7_SFID_PIXEL_INTERPOLATOR; inst->desc = desc_imm; inst->ex_desc = 0; @@ -2886,25 +2886,25 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, inst->resize_sources(3); inst->src[0] = component(desc, 0); - inst->src[1] = brw_imm_ud(0); /* ex_desc */ + inst->src[1] = elk_imm_ud(0); /* ex_desc */ inst->src[2] = payload; } static void -lower_get_buffer_size(const fs_builder &bld, fs_inst *inst) +lower_get_buffer_size(const fs_builder &bld, elk_fs_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->ver >= 7); /* Since we can only execute this instruction on uniform bti/surface - * handles, brw_fs_nir.cpp should already have limited this to SIMD8. + * handles, elk_fs_nir.cpp should already have limited this to SIMD8. */ assert(inst->exec_size == (devinfo->ver < 20 ? 8 : 16)); - fs_reg surface = inst->src[GET_BUFFER_SIZE_SRC_SURFACE]; - fs_reg surface_handle = inst->src[GET_BUFFER_SIZE_SRC_SURFACE_HANDLE]; - fs_reg lod = inst->src[GET_BUFFER_SIZE_SRC_LOD]; + elk_fs_reg surface = inst->src[GET_BUFFER_SIZE_SRC_SURFACE]; + elk_fs_reg surface_handle = inst->src[GET_BUFFER_SIZE_SRC_SURFACE_HANDLE]; + elk_fs_reg lod = inst->src[GET_BUFFER_SIZE_SRC_LOD]; - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = inst->exec_size / 8; inst->resize_sources(3); inst->ex_mlen = 0; @@ -2914,124 +2914,124 @@ lower_get_buffer_size(const fs_builder &bld, fs_inst *inst) inst->src[2] = lod; const uint32_t return_format = devinfo->ver >= 8 ? - GFX8_SAMPLER_RETURN_FORMAT_32BITS : BRW_SAMPLER_RETURN_FORMAT_SINT32; + GFX8_SAMPLER_RETURN_FORMAT_32BITS : ELK_SAMPLER_RETURN_FORMAT_SINT32; - const uint32_t desc = brw_sampler_desc(devinfo, 0, 0, + const uint32_t desc = elk_sampler_desc(devinfo, 0, 0, GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO, - BRW_SAMPLER_SIMD_MODE_SIMD8, + ELK_SAMPLER_SIMD_MODE_SIMD8, return_format); - inst->dst = retype(inst->dst, BRW_REGISTER_TYPE_UW); - inst->sfid = BRW_SFID_SAMPLER; + inst->dst = retype(inst->dst, ELK_REGISTER_TYPE_UW); + inst->sfid = ELK_SFID_SAMPLER; setup_surface_descriptors(bld, inst, desc, surface, surface_handle); } bool -fs_visitor::lower_logical_sends() +elk_fs_visitor::lower_logical_sends() { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { + foreach_block_and_inst_safe(block, elk_fs_inst, inst, cfg) { const fs_builder ibld(this, block, inst); switch (inst->opcode) { - case FS_OPCODE_FB_WRITE_LOGICAL: + case ELK_FS_OPCODE_FB_WRITE_LOGICAL: assert(stage == MESA_SHADER_FRAGMENT); lower_fb_write_logical_send(ibld, inst, - brw_wm_prog_data(prog_data), - (const brw_wm_prog_key *)key, + elk_wm_prog_data(prog_data), + (const elk_wm_prog_key *)key, fs_payload()); break; - case FS_OPCODE_FB_READ_LOGICAL: + case ELK_FS_OPCODE_FB_READ_LOGICAL: lower_fb_read_logical_send(ibld, inst); break; - case SHADER_OPCODE_TEX_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TEX); + case ELK_SHADER_OPCODE_TEX_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TEX); break; - case SHADER_OPCODE_TXD_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXD); + case ELK_SHADER_OPCODE_TXD_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TXD); break; - case SHADER_OPCODE_TXF_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF); + case ELK_SHADER_OPCODE_TXF_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TXF); break; - case SHADER_OPCODE_TXL_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXL); + case ELK_SHADER_OPCODE_TXL_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TXL); break; - case SHADER_OPCODE_TXS_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXS); + case ELK_SHADER_OPCODE_TXS_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TXS); break; - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL: lower_sampler_logical_send(ibld, inst, - SHADER_OPCODE_IMAGE_SIZE_LOGICAL); + ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL); break; - case FS_OPCODE_TXB_LOGICAL: - lower_sampler_logical_send(ibld, inst, FS_OPCODE_TXB); + case ELK_FS_OPCODE_TXB_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_FS_OPCODE_TXB); break; - case SHADER_OPCODE_TXF_CMS_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS); + case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TXF_CMS); break; - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS_W); + case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TXF_CMS_W); break; - case SHADER_OPCODE_TXF_UMS_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_UMS); + case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TXF_UMS); break; - case SHADER_OPCODE_TXF_MCS_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_MCS); + case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TXF_MCS); break; - case SHADER_OPCODE_LOD_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_LOD); + case ELK_SHADER_OPCODE_LOD_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_LOD); break; - case SHADER_OPCODE_TG4_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4); + case ELK_SHADER_OPCODE_TG4_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TG4); break; - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4_OFFSET); + case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_TG4_OFFSET); break; - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: - lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_SAMPLEINFO); + case ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL: + lower_sampler_logical_send(ibld, inst, ELK_SHADER_OPCODE_SAMPLEINFO); break; - case SHADER_OPCODE_GET_BUFFER_SIZE: + case ELK_SHADER_OPCODE_GET_BUFFER_SIZE: lower_get_buffer_size(ibld, inst); break; - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: if (devinfo->has_lsc) { lower_lsc_surface_logical_send(ibld, inst); break; } - case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: lower_surface_logical_send(ibld, inst); break; - case SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: - case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL: if (devinfo->has_lsc) { lower_lsc_block_logical_send(ibld, inst); break; @@ -3039,14 +3039,14 @@ fs_visitor::lower_logical_sends() lower_surface_block_logical_send(ibld, inst); break; - case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: - case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: - case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: - case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: if (devinfo->has_lsc) { lower_lsc_a64_logical_send(ibld, inst); break; @@ -3054,23 +3054,23 @@ fs_visitor::lower_logical_sends() lower_a64_logical_send(ibld, inst); break; - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: if (devinfo->has_lsc && !compiler->indirect_ubos_use_sampler) lower_lsc_varying_pull_constant_logical_send(ibld, inst); else lower_varying_pull_constant_logical_send(ibld, inst); break; - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: /* The math opcodes are overloaded for the send-like and * expression-like instructions which seems kind of icky. Gfx6+ has * a native (but rather quirky) MATH instruction so we don't need to @@ -3086,22 +3086,22 @@ fs_visitor::lower_logical_sends() continue; } - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: lower_interpolator_logical_send(ibld, inst, - (const brw_wm_prog_key *)key, - brw_wm_prog_data(prog_data)); + (const elk_wm_prog_key *)key, + elk_wm_prog_data(prog_data)); break; - case SHADER_OPCODE_URB_READ_LOGICAL: + case ELK_SHADER_OPCODE_URB_READ_LOGICAL: if (devinfo->ver < 20) lower_urb_read_logical_send(ibld, inst); else lower_urb_read_logical_send_xe2(ibld, inst); break; - case SHADER_OPCODE_URB_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_URB_WRITE_LOGICAL: if (devinfo->ver < 20) lower_urb_write_logical_send(ibld, inst); else @@ -3139,18 +3139,18 @@ fs_visitor::lower_logical_sends() * source operand for all 8 or 16 of its channels. */ bool -fs_visitor::lower_uniform_pull_constant_loads() +elk_fs_visitor::lower_uniform_pull_constant_loads() { bool progress = false; - foreach_block_and_inst (block, fs_inst, inst, cfg) { - if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD) + foreach_block_and_inst (block, elk_fs_inst, inst, cfg) { + if (inst->opcode != ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD) continue; - const fs_reg surface = inst->src[PULL_UNIFORM_CONSTANT_SRC_SURFACE]; - const fs_reg surface_handle = inst->src[PULL_UNIFORM_CONSTANT_SRC_SURFACE_HANDLE]; - const fs_reg offset_B = inst->src[PULL_UNIFORM_CONSTANT_SRC_OFFSET]; - const fs_reg size_B = inst->src[PULL_UNIFORM_CONSTANT_SRC_SIZE]; + const elk_fs_reg surface = inst->src[PULL_UNIFORM_CONSTANT_SRC_SURFACE]; + const elk_fs_reg surface_handle = inst->src[PULL_UNIFORM_CONSTANT_SRC_SURFACE_HANDLE]; + const elk_fs_reg offset_B = inst->src[PULL_UNIFORM_CONSTANT_SRC_OFFSET]; + const elk_fs_reg size_B = inst->src[PULL_UNIFORM_CONSTANT_SRC_SIZE]; assert(surface.file == BAD_FILE || surface_handle.file == BAD_FILE); assert(offset_B.file == IMM); assert(size_B.file == IMM); @@ -3159,7 +3159,7 @@ fs_visitor::lower_uniform_pull_constant_loads() const fs_builder ubld = fs_builder(this, block, inst).group(8, 0).exec_all(); - const fs_reg payload = ubld.vgrf(BRW_REGISTER_TYPE_UD); + const elk_fs_reg payload = ubld.vgrf(ELK_REGISTER_TYPE_UD); ubld.MOV(payload, offset_B); inst->sfid = GFX12_SFID_UGM; @@ -3177,7 +3177,7 @@ fs_visitor::lower_uniform_pull_constant_loads() true /* has_dest */); /* Update the original instruction. */ - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc); inst->send_ex_bso = surface_handle.file != BAD_FILE && compiler->extended_bindless_surface_offset; @@ -3198,20 +3198,20 @@ fs_visitor::lower_uniform_pull_constant_loads() invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES); } else if (devinfo->ver >= 7) { const fs_builder ubld = fs_builder(this, block, inst).exec_all(); - fs_reg header = fs_builder(this, 8).exec_all().vgrf(BRW_REGISTER_TYPE_UD); + elk_fs_reg header = fs_builder(this, 8).exec_all().vgrf(ELK_REGISTER_TYPE_UD); ubld.group(8, 0).MOV(header, - retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); ubld.group(1, 0).MOV(component(header, 2), - brw_imm_ud(offset_B.ud / 16)); + elk_imm_ud(offset_B.ud / 16)); inst->sfid = GFX6_SFID_DATAPORT_CONSTANT_CACHE; - inst->opcode = SHADER_OPCODE_SEND; + inst->opcode = ELK_SHADER_OPCODE_SEND; inst->header_size = 1; inst->mlen = 1; uint32_t desc = - brw_dp_oword_block_rw_desc(devinfo, true /* align_16B */, + elk_dp_oword_block_rw_desc(devinfo, true /* align_16B */, size_B.ud / 4, false /* write */); inst->resize_sources(4); @@ -3219,7 +3219,7 @@ fs_visitor::lower_uniform_pull_constant_loads() setup_surface_descriptors(ubld, inst, desc, surface, surface_handle); inst->src[2] = header; - inst->src[3] = fs_reg(); /* unused for reads */ + inst->src[3] = elk_fs_reg(); /* unused for reads */ invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES); } else { diff --git a/src/intel/compiler/elk/elk_nir.c b/src/intel/compiler/elk/elk_nir.c index 40a485a170b..1a5fcf0f491 100644 --- a/src/intel/compiler/elk/elk_nir.c +++ b/src/intel/compiler/elk/elk_nir.c @@ -234,7 +234,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b, } void -brw_nir_lower_vs_inputs(nir_shader *nir, +elk_nir_lower_vs_inputs(nir_shader *nir, bool edgeflag_is_last, const uint8_t *vs_attrib_wa_flags) { @@ -246,7 +246,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, * loaded as one vec4 or dvec4 per element (or matrix column), depending on * whether it is a double-precision type or not. */ - nir_lower_io(nir, nir_var_shader_in, type_size_vec4, + nir_lower_io(nir, nir_var_shader_in, elk_type_size_vec4, nir_lower_io_lower_64bit_to_32); /* This pass needs actual constants */ @@ -254,7 +254,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, nir_io_add_const_offset_to_base(nir, nir_var_shader_in); - brw_nir_apply_attribute_workarounds(nir, vs_attrib_wa_flags); + elk_nir_apply_attribute_workarounds(nir, vs_attrib_wa_flags); /* The last step is to remap VERT_ATTRIB_* to actual registers */ @@ -365,14 +365,14 @@ brw_nir_lower_vs_inputs(nir_shader *nir, } void -brw_nir_lower_vue_inputs(nir_shader *nir, +elk_nir_lower_vue_inputs(nir_shader *nir, const struct intel_vue_map *vue_map) { nir_foreach_shader_in_variable(var, nir) var->data.driver_location = var->data.location; - /* Inputs are stored in vec4 slots, so use type_size_vec4(). */ - nir_lower_io(nir, nir_var_shader_in, type_size_vec4, + /* Inputs are stored in vec4 slots, so use elk_type_size_vec4(). */ + nir_lower_io(nir, nir_var_shader_in, elk_type_size_vec4, nir_lower_io_lower_64bit_to_32); /* This pass needs actual constants */ @@ -415,12 +415,12 @@ brw_nir_lower_vue_inputs(nir_shader *nir, } void -brw_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue_map) +elk_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue_map) { nir_foreach_shader_in_variable(var, nir) var->data.driver_location = var->data.location; - nir_lower_io(nir, nir_var_shader_in, type_size_vec4, + nir_lower_io(nir, nir_var_shader_in, elk_type_size_vec4, nir_lower_io_lower_64bit_to_32); /* This pass needs actual constants */ @@ -490,9 +490,9 @@ lower_barycentric_at_offset(nir_builder *b, nir_intrinsic_instr *intrin, } void -brw_nir_lower_fs_inputs(nir_shader *nir, +elk_nir_lower_fs_inputs(nir_shader *nir, const struct intel_device_info *devinfo, - const struct brw_wm_prog_key *key) + const struct elk_wm_prog_key *key) { nir_foreach_shader_in_variable(var, nir) { var->data.driver_location = var->data.location; @@ -521,14 +521,14 @@ brw_nir_lower_fs_inputs(nir_shader *nir, } } - nir_lower_io(nir, nir_var_shader_in, type_size_vec4, + nir_lower_io(nir, nir_var_shader_in, elk_type_size_vec4, nir_lower_io_lower_64bit_to_32); if (devinfo->ver >= 11) nir_lower_interpolation(nir, ~0); - if (key->multisample_fbo == BRW_NEVER) { + if (key->multisample_fbo == ELK_NEVER) { nir_lower_single_sampled(nir); - } else if (key->persample_interp == BRW_ALWAYS) { + } else if (key->persample_interp == ELK_ALWAYS) { nir_shader_intrinsics_pass(nir, lower_barycentric_per_sample, nir_metadata_block_index | nir_metadata_dominance, @@ -547,25 +547,25 @@ brw_nir_lower_fs_inputs(nir_shader *nir, } void -brw_nir_lower_vue_outputs(nir_shader *nir) +elk_nir_lower_vue_outputs(nir_shader *nir) { nir_foreach_shader_out_variable(var, nir) { var->data.driver_location = var->data.location; } - nir_lower_io(nir, nir_var_shader_out, type_size_vec4, + nir_lower_io(nir, nir_var_shader_out, elk_type_size_vec4, nir_lower_io_lower_64bit_to_32); } void -brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue_map, +elk_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue_map, enum tess_primitive_mode tes_primitive_mode) { nir_foreach_shader_out_variable(var, nir) { var->data.driver_location = var->data.location; } - nir_lower_io(nir, nir_var_shader_out, type_size_vec4, + nir_lower_io(nir, nir_var_shader_out, elk_type_size_vec4, nir_lower_io_lower_64bit_to_32); /* This pass needs actual constants */ @@ -582,15 +582,15 @@ brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue_map, } void -brw_nir_lower_fs_outputs(nir_shader *nir) +elk_nir_lower_fs_outputs(nir_shader *nir) { nir_foreach_shader_out_variable(var, nir) { var->data.driver_location = - SET_FIELD(var->data.index, BRW_NIR_FRAG_OUTPUT_INDEX) | - SET_FIELD(var->data.location, BRW_NIR_FRAG_OUTPUT_LOCATION); + SET_FIELD(var->data.index, ELK_NIR_FRAG_OUTPUT_INDEX) | + SET_FIELD(var->data.location, ELK_NIR_FRAG_OUTPUT_LOCATION); } - nir_lower_io(nir, nir_var_shader_out, type_size_dvec4, 0); + nir_lower_io(nir, nir_var_shader_out, elk_type_size_dvec4, 0); } #define OPT(pass, ...) ({ \ @@ -602,7 +602,7 @@ brw_nir_lower_fs_outputs(nir_shader *nir) }) void -brw_nir_optimize(nir_shader *nir, bool is_scalar, +elk_nir_optimize(nir_shader *nir, bool is_scalar, const struct intel_device_info *devinfo) { bool progress; @@ -729,7 +729,7 @@ brw_nir_optimize(nir_shader *nir, bool is_scalar, static unsigned lower_bit_size_callback(const nir_instr *instr, UNUSED void *data) { - const struct brw_compiler *compiler = (const struct brw_compiler *) data; + const struct elk_compiler *compiler = (const struct elk_compiler *) data; const struct intel_device_info *devinfo = compiler->devinfo; switch (instr->type) { @@ -888,15 +888,15 @@ lower_xehp_tg4_offset_filter(const nir_instr *instr, UNUSED const void *data) * it is not at all generator-specific. */ void -brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, - const struct brw_nir_compiler_opts *opts) +elk_preprocess_nir(const struct elk_compiler *compiler, nir_shader *nir, + const struct elk_nir_compiler_opts *opts) { const struct intel_device_info *devinfo = compiler->devinfo; UNUSED bool progress; /* Written by OPT */ const bool is_scalar = compiler->scalar_stage[nir->info.stage]; - nir_validate_ssa_dominance(nir, "before brw_preprocess_nir"); + nir_validate_ssa_dominance(nir, "before elk_preprocess_nir"); OPT(nir_lower_frexp); @@ -907,10 +907,10 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, if (nir->info.stage == MESA_SHADER_GEOMETRY) OPT(nir_lower_gs_intrinsics, 0); - /* See also brw_nir_trig_workarounds.py */ + /* See also elk_nir_trig_workarounds.py */ if (compiler->precise_trig && !(devinfo->ver >= 10 || devinfo->platform == INTEL_PLATFORM_KBL)) - OPT(brw_nir_apply_trig_workarounds); + OPT(elk_nir_apply_trig_workarounds); /* This workaround existing for performance reasons. Since it requires not * setting RENDER_SURFACE_STATE::SurfaceArray when the array length is 1, @@ -953,7 +953,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, OPT(nir_split_var_copies); OPT(nir_split_struct_vars, nir_var_function_temp); - brw_nir_optimize(nir, is_scalar, devinfo); + elk_nir_optimize(nir, is_scalar, devinfo); OPT(nir_lower_doubles, opts->softfp64, nir->options->lower_doubles_options); if (OPT(nir_lower_int64_float_conversions)) { @@ -998,7 +998,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, OPT(nir_lower_subgroups, &subgroups_options); nir_variable_mode indirect_mask = - brw_nir_no_indirect_mask(compiler, nir->info.stage); + elk_nir_no_indirect_mask(compiler, nir->info.stage); OPT(nir_lower_indirect_derefs, indirect_mask, UINT32_MAX); /* Even in cases where we can handle indirect temporaries via scratch, we @@ -1037,11 +1037,11 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, OPT(intel_nir_clamp_per_vertex_loads); /* Get rid of split copies */ - brw_nir_optimize(nir, is_scalar, devinfo); + elk_nir_optimize(nir, is_scalar, devinfo); } static bool -brw_nir_zero_inputs_instr(struct nir_builder *b, nir_intrinsic_instr *intrin, +elk_nir_zero_inputs_instr(struct nir_builder *b, nir_intrinsic_instr *intrin, void *data) { if (intrin->intrinsic != nir_intrinsic_load_deref) @@ -1072,15 +1072,15 @@ brw_nir_zero_inputs_instr(struct nir_builder *b, nir_intrinsic_instr *intrin, } static bool -brw_nir_zero_inputs(nir_shader *shader, uint64_t *zero_inputs) +elk_nir_zero_inputs(nir_shader *shader, uint64_t *zero_inputs) { - return nir_shader_intrinsics_pass(shader, brw_nir_zero_inputs_instr, + return nir_shader_intrinsics_pass(shader, elk_nir_zero_inputs_instr, nir_metadata_block_index | nir_metadata_dominance, zero_inputs); } void -brw_nir_link_shaders(const struct brw_compiler *compiler, +elk_nir_link_shaders(const struct elk_compiler *compiler, nir_shader *producer, nir_shader *consumer) { const struct intel_device_info *devinfo = compiler->devinfo; @@ -1095,12 +1095,12 @@ brw_nir_link_shaders(const struct brw_compiler *compiler, if (p_is_scalar && c_is_scalar) { NIR_PASS(_, producer, nir_lower_io_to_scalar_early, nir_var_shader_out); NIR_PASS(_, consumer, nir_lower_io_to_scalar_early, nir_var_shader_in); - brw_nir_optimize(producer, p_is_scalar, devinfo); - brw_nir_optimize(consumer, c_is_scalar, devinfo); + elk_nir_optimize(producer, p_is_scalar, devinfo); + elk_nir_optimize(consumer, c_is_scalar, devinfo); } if (nir_link_opt_varyings(producer, consumer)) - brw_nir_optimize(consumer, c_is_scalar, devinfo); + elk_nir_optimize(consumer, c_is_scalar, devinfo); NIR_PASS(_, producer, nir_remove_dead_variables, nir_var_shader_out, NULL); NIR_PASS(_, consumer, nir_remove_dead_variables, nir_var_shader_in, NULL); @@ -1123,14 +1123,14 @@ brw_nir_link_shaders(const struct brw_compiler *compiler, * varyings we have demoted here. */ NIR_PASS(_, producer, nir_lower_indirect_derefs, - brw_nir_no_indirect_mask(compiler, producer->info.stage), + elk_nir_no_indirect_mask(compiler, producer->info.stage), UINT32_MAX); NIR_PASS(_, consumer, nir_lower_indirect_derefs, - brw_nir_no_indirect_mask(compiler, consumer->info.stage), + elk_nir_no_indirect_mask(compiler, consumer->info.stage), UINT32_MAX); - brw_nir_optimize(producer, p_is_scalar, devinfo); - brw_nir_optimize(consumer, c_is_scalar, devinfo); + elk_nir_optimize(producer, p_is_scalar, devinfo); + elk_nir_optimize(consumer, c_is_scalar, devinfo); } NIR_PASS(_, producer, nir_lower_io_to_vector, nir_var_shader_out); @@ -1158,7 +1158,7 @@ brw_nir_link_shaders(const struct brw_compiler *compiler, } bool -brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, +elk_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, nir_intrinsic_instr *low, @@ -1189,7 +1189,7 @@ brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, } } else { /* We can handle at most a vec4 right now. Anything bigger would get - * immediately split by brw_nir_lower_mem_access_bit_sizes anyway. + * immediately split by elk_nir_lower_mem_access_bit_sizes anyway. */ if (num_components > 4) return false; @@ -1315,9 +1315,9 @@ get_mem_access_size_align(nir_intrinsic_op intrin, uint8_t bytes, } static void -brw_vectorize_lower_mem_access(nir_shader *nir, - const struct brw_compiler *compiler, - enum brw_robustness_flags robust_flags) +elk_vectorize_lower_mem_access(nir_shader *nir, + const struct elk_compiler *compiler, + enum elk_robustness_flags robust_flags) { bool progress = false; const bool is_scalar = compiler->scalar_stage[nir->info.stage]; @@ -1326,13 +1326,13 @@ brw_vectorize_lower_mem_access(nir_shader *nir, nir_load_store_vectorize_options options = { .modes = nir_var_mem_ubo | nir_var_mem_ssbo | nir_var_mem_global | nir_var_mem_shared, - .callback = brw_nir_should_vectorize_mem, + .callback = elk_nir_should_vectorize_mem, .robust_modes = (nir_variable_mode)0, }; - if (robust_flags & BRW_ROBUSTNESS_UBO) + if (robust_flags & ELK_ROBUSTNESS_UBO) options.robust_modes |= nir_var_mem_ubo | nir_var_mem_global; - if (robust_flags & BRW_ROBUSTNESS_SSBO) + if (robust_flags & ELK_ROBUSTNESS_SSBO) options.robust_modes |= nir_var_mem_ssbo | nir_var_mem_global; OPT(nir_opt_load_store_vectorize, &options); @@ -1405,9 +1405,9 @@ nir_shader_has_local_variables(const nir_shader *nir) * will not work. */ void -brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, +elk_postprocess_nir(nir_shader *nir, const struct elk_compiler *compiler, bool debug_enabled, - enum brw_robustness_flags robust_flags) + enum elk_robustness_flags robust_flags) { const struct intel_device_info *devinfo = compiler->devinfo; const bool is_scalar = compiler->scalar_stage[nir->info.stage]; @@ -1437,20 +1437,20 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, if (gl_shader_stage_can_set_fragment_shading_rate(nir->info.stage)) NIR_PASS(_, nir, intel_nir_lower_shading_rate_output); - brw_nir_optimize(nir, is_scalar, devinfo); + elk_nir_optimize(nir, is_scalar, devinfo); if (is_scalar && nir_shader_has_local_variables(nir)) { OPT(nir_lower_vars_to_explicit_types, nir_var_function_temp, glsl_get_natural_size_align_bytes); OPT(nir_lower_explicit_io, nir_var_function_temp, nir_address_format_32bit_offset); - brw_nir_optimize(nir, is_scalar, devinfo); + elk_nir_optimize(nir, is_scalar, devinfo); } - brw_vectorize_lower_mem_access(nir, compiler, robust_flags); + elk_vectorize_lower_mem_access(nir, compiler, robust_flags); if (OPT(nir_lower_int64)) - brw_nir_optimize(nir, is_scalar, devinfo); + elk_nir_optimize(nir, is_scalar, devinfo); if (devinfo->ver >= 6) { /* Try and fuse multiply-adds, if successful, run shrink_vectors to @@ -1481,7 +1481,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, * instruction from one of the branches of the if-statement, so now it * might be under the threshold of conversion to bcsel. * - * See brw_nir_optimize for the explanation of is_vec4_tessellation. + * See elk_nir_optimize for the explanation of is_vec4_tessellation. */ const bool is_vec4_tessellation = !is_scalar && (nir->info.stage == MESA_SHADER_TESS_CTRL || @@ -1510,7 +1510,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, if (OPT(nir_lower_fp16_casts, nir_lower_fp16_split_fp64)) { if (OPT(nir_lower_int64)) { - brw_nir_optimize(nir, is_scalar, devinfo); + elk_nir_optimize(nir, is_scalar, devinfo); } } @@ -1551,7 +1551,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, OPT(nir_lower_subgroups, &subgroups_options); if (OPT(nir_lower_int64)) - brw_nir_optimize(nir, is_scalar, devinfo); + elk_nir_optimize(nir, is_scalar, devinfo); divergence_analysis_dirty = true; } @@ -1617,7 +1617,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, * want that to be squashed by other NIR passes. */ if (devinfo->ver <= 5) - brw_nir_analyze_boolean_resolves(nir); + elk_nir_analyze_boolean_resolves(nir); nir_sweep(nir); @@ -1629,9 +1629,9 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, } static bool -brw_nir_apply_sampler_key(nir_shader *nir, - const struct brw_compiler *compiler, - const struct brw_sampler_prog_key_data *key_tex) +elk_nir_apply_sampler_key(nir_shader *nir, + const struct elk_compiler *compiler, + const struct elk_sampler_prog_key_data *key_tex) { const struct intel_device_info *devinfo = compiler->devinfo; nir_lower_tex_options tex_options = { @@ -1664,13 +1664,13 @@ get_subgroup_size(const struct shader_info *info, unsigned max_subgroup_size) switch (info->subgroup_size) { case SUBGROUP_SIZE_API_CONSTANT: /* We have to use the global constant size. */ - return BRW_SUBGROUP_SIZE; + return ELK_SUBGROUP_SIZE; case SUBGROUP_SIZE_UNIFORM: /* It has to be uniform across all invocations but can vary per stage * if we want. This gives us a bit more freedom. * - * For compute, brw_nir_apply_key is called per-dispatch-width so this + * For compute, elk_nir_apply_key is called per-dispatch-width so this * is the actual subgroup size and not a maximum. However, we only * invoke one size of any given compute shader so it's still guaranteed * to be uniform across invocations. @@ -1680,7 +1680,7 @@ get_subgroup_size(const struct shader_info *info, unsigned max_subgroup_size) case SUBGROUP_SIZE_VARYING: /* The subgroup size is allowed to be fully varying. For geometry * stages, we know it's always 8 which is max_subgroup_size so we can - * return that. For compute, brw_nir_apply_key is called once per + * return that. For compute, elk_nir_apply_key is called once per * dispatch-width so max_subgroup_size is the real subgroup size. * * For fragment, we return 0 and let it fall through to the back-end @@ -1710,21 +1710,21 @@ get_subgroup_size(const struct shader_info *info, unsigned max_subgroup_size) } unsigned -brw_nir_api_subgroup_size(const nir_shader *nir, +elk_nir_api_subgroup_size(const nir_shader *nir, unsigned hw_subgroup_size) { return get_subgroup_size(&nir->info, hw_subgroup_size); } void -brw_nir_apply_key(nir_shader *nir, - const struct brw_compiler *compiler, - const struct brw_base_prog_key *key, +elk_nir_apply_key(nir_shader *nir, + const struct elk_compiler *compiler, + const struct elk_base_prog_key *key, unsigned max_subgroup_size) { bool progress = false; - OPT(brw_nir_apply_sampler_key, compiler, &key->tex); + OPT(elk_nir_apply_sampler_key, compiler, &key->tex); const struct intel_nir_lower_texture_opts tex_opts = { .combined_lod_and_array_index = compiler->devinfo->ver >= 20, @@ -1740,16 +1740,16 @@ brw_nir_apply_key(nir_shader *nir, OPT(nir_lower_subgroups, &subgroups_options); if (key->limit_trig_input_range) - OPT(brw_nir_limit_trig_input_range_workaround); + OPT(elk_nir_limit_trig_input_range_workaround); if (progress) { const bool is_scalar = compiler->scalar_stage[nir->info.stage]; - brw_nir_optimize(nir, is_scalar, compiler->devinfo); + elk_nir_optimize(nir, is_scalar, compiler->devinfo); } } -enum brw_conditional_mod -brw_cmod_for_nir_comparison(nir_op op) +enum elk_conditional_mod +elk_cmod_for_nir_comparison(nir_op op) { switch (op) { case nir_op_flt: @@ -1758,7 +1758,7 @@ brw_cmod_for_nir_comparison(nir_op op) case nir_op_ilt32: case nir_op_ult: case nir_op_ult32: - return BRW_CONDITIONAL_L; + return ELK_CONDITIONAL_L; case nir_op_fge: case nir_op_fge32: @@ -1766,7 +1766,7 @@ brw_cmod_for_nir_comparison(nir_op op) case nir_op_ige32: case nir_op_uge: case nir_op_uge32: - return BRW_CONDITIONAL_GE; + return ELK_CONDITIONAL_GE; case nir_op_feq: case nir_op_feq32: @@ -1778,7 +1778,7 @@ brw_cmod_for_nir_comparison(nir_op op) case nir_op_b32all_iequal3: case nir_op_b32all_fequal4: case nir_op_b32all_iequal4: - return BRW_CONDITIONAL_Z; + return ELK_CONDITIONAL_Z; case nir_op_fneu: case nir_op_fneu32: @@ -1790,15 +1790,15 @@ brw_cmod_for_nir_comparison(nir_op op) case nir_op_b32any_inequal3: case nir_op_b32any_fnequal4: case nir_op_b32any_inequal4: - return BRW_CONDITIONAL_NZ; + return ELK_CONDITIONAL_NZ; default: unreachable("Unsupported NIR comparison op"); } } -enum lsc_opcode -lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic) +enum elk_lsc_opcode +elk_lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic) { switch (nir_intrinsic_atomic_op(atomic)) { case nir_atomic_op_iadd: { @@ -1849,48 +1849,48 @@ lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic) } } -enum brw_reg_type -brw_type_for_nir_type(const struct intel_device_info *devinfo, +enum elk_reg_type +elk_type_for_nir_type(const struct intel_device_info *devinfo, nir_alu_type type) { switch (type) { case nir_type_uint: case nir_type_uint32: - return BRW_REGISTER_TYPE_UD; + return ELK_REGISTER_TYPE_UD; case nir_type_bool: case nir_type_int: case nir_type_bool32: case nir_type_int32: - return BRW_REGISTER_TYPE_D; + return ELK_REGISTER_TYPE_D; case nir_type_float: case nir_type_float32: - return BRW_REGISTER_TYPE_F; + return ELK_REGISTER_TYPE_F; case nir_type_float16: - return BRW_REGISTER_TYPE_HF; + return ELK_REGISTER_TYPE_HF; case nir_type_float64: - return BRW_REGISTER_TYPE_DF; + return ELK_REGISTER_TYPE_DF; case nir_type_int64: - return devinfo->ver < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_Q; + return devinfo->ver < 8 ? ELK_REGISTER_TYPE_DF : ELK_REGISTER_TYPE_Q; case nir_type_uint64: - return devinfo->ver < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_UQ; + return devinfo->ver < 8 ? ELK_REGISTER_TYPE_DF : ELK_REGISTER_TYPE_UQ; case nir_type_int16: - return BRW_REGISTER_TYPE_W; + return ELK_REGISTER_TYPE_W; case nir_type_uint16: - return BRW_REGISTER_TYPE_UW; + return ELK_REGISTER_TYPE_UW; case nir_type_int8: - return BRW_REGISTER_TYPE_B; + return ELK_REGISTER_TYPE_B; case nir_type_uint8: - return BRW_REGISTER_TYPE_UB; + return ELK_REGISTER_TYPE_UB; default: unreachable("unknown type"); } - return BRW_REGISTER_TYPE_F; + return ELK_REGISTER_TYPE_F; } nir_shader * -brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler, - const struct brw_tcs_prog_key *key) +elk_nir_create_passthrough_tcs(void *mem_ctx, const struct elk_compiler *compiler, + const struct elk_tcs_prog_key *key) { assert(key->input_vertices > 0); @@ -1914,16 +1914,16 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile nir->info.inputs_read = inputs_read; nir->info.tess._primitive_mode = key->_tes_primitive_mode; - nir_validate_shader(nir, "in brw_nir_create_passthrough_tcs"); + nir_validate_shader(nir, "in elk_nir_create_passthrough_tcs"); - struct brw_nir_compiler_opts opts = {}; - brw_preprocess_nir(compiler, nir, &opts); + struct elk_nir_compiler_opts opts = {}; + elk_preprocess_nir(compiler, nir, &opts); return nir; } nir_def * -brw_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform, +elk_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform, nir_def *base_addr, unsigned off) { assert(load_uniform->intrinsic == nir_intrinsic_load_uniform); @@ -1967,7 +1967,7 @@ brw_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform, } const struct glsl_type * -brw_nir_get_var_type(const struct nir_shader *nir, nir_variable *var) +elk_nir_get_var_type(const struct nir_shader *nir, nir_variable *var) { const struct glsl_type *type = var->interface_type; if (!type) { diff --git a/src/intel/compiler/elk/elk_nir.h b/src/intel/compiler/elk/elk_nir.h index 62482aa8d49..309d706a4e0 100644 --- a/src/intel/compiler/elk/elk_nir.h +++ b/src/intel/compiler/elk/elk_nir.h @@ -33,27 +33,27 @@ extern "C" { #endif -extern const struct nir_shader_compiler_options brw_scalar_nir_options; -extern const struct nir_shader_compiler_options brw_vector_nir_options; +extern const struct nir_shader_compiler_options elk_scalar_nir_options; +extern const struct nir_shader_compiler_options elk_vector_nir_options; -int type_size_vec4(const struct glsl_type *type, bool bindless); -int type_size_dvec4(const struct glsl_type *type, bool bindless); +int elk_type_size_vec4(const struct glsl_type *type, bool bindless); +int elk_type_size_dvec4(const struct glsl_type *type, bool bindless); static inline int -type_size_scalar_bytes(const struct glsl_type *type, bool bindless) +elk_type_size_scalar_bytes(const struct glsl_type *type, bool bindless) { return glsl_count_dword_slots(type, bindless) * 4; } static inline int -type_size_vec4_bytes(const struct glsl_type *type, bool bindless) +elk_type_size_vec4_bytes(const struct glsl_type *type, bool bindless) { - return type_size_vec4(type, bindless) * 16; + return elk_type_size_vec4(type, bindless) * 16; } /* Flags set in the instr->pass_flags field by i965 analysis passes */ enum { - BRW_NIR_NON_BOOLEAN = 0x0, + ELK_NIR_NON_BOOLEAN = 0x0, /* Indicates that the given instruction's destination is a boolean * value but that it needs to be resolved before it can be used. @@ -63,7 +63,7 @@ enum { * "resolve" operation by replacing the value of the CMP with -(x & 1) * to sign-extend the bottom bit to 0/~0. */ - BRW_NIR_BOOLEAN_NEEDS_RESOLVE = 0x1, + ELK_NIR_BOOLEAN_NEEDS_RESOLVE = 0x1, /* Indicates that the given instruction's destination is a boolean * value that has intentionally been left unresolved. Not all boolean @@ -77,25 +77,25 @@ enum { * immediately because the AND still does an AND of the bottom bits. * Instead, we can save ourselves instructions by delaying the resolve * until after the AND. The result of the two CMP instructions is left - * as BRW_NIR_BOOLEAN_UNRESOLVED. + * as ELK_NIR_BOOLEAN_UNRESOLVED. */ - BRW_NIR_BOOLEAN_UNRESOLVED = 0x2, + ELK_NIR_BOOLEAN_UNRESOLVED = 0x2, /* Indicates a that the given instruction's destination is a boolean * value that does not need a resolve. For instance, if you AND two - * values that are BRW_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both + * values that are ELK_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both * values will be 0/~0 before we get them and the result of the AND is * also guaranteed to be 0/~0 and does not need a resolve. */ - BRW_NIR_BOOLEAN_NO_RESOLVE = 0x3, + ELK_NIR_BOOLEAN_NO_RESOLVE = 0x3, /* A mask to mask the boolean status values off of instr->pass_flags */ - BRW_NIR_BOOLEAN_MASK = 0x3, + ELK_NIR_BOOLEAN_MASK = 0x3, }; -void brw_nir_analyze_boolean_resolves(nir_shader *nir); +void elk_nir_analyze_boolean_resolves(nir_shader *nir); -struct brw_nir_compiler_opts { +struct elk_nir_compiler_opts { /* Soft floating point implementation shader */ const nir_shader *softfp64; @@ -117,7 +117,7 @@ struct brw_nir_compiler_opts { * This function should only be called on src[0] of load_ubo intrinsics. */ static inline bool -brw_nir_ubo_surface_index_is_pushable(nir_src src) +elk_nir_ubo_surface_index_is_pushable(nir_src src) { nir_intrinsic_instr *intrin = src.ssa->parent_instr->type == nir_instr_type_intrinsic ? @@ -132,12 +132,12 @@ brw_nir_ubo_surface_index_is_pushable(nir_src src) } static inline unsigned -brw_nir_ubo_surface_index_get_push_block(nir_src src) +elk_nir_ubo_surface_index_get_push_block(nir_src src) { if (nir_src_is_const(src)) return nir_src_as_uint(src); - if (!brw_nir_ubo_surface_index_is_pushable(src)) + if (!elk_nir_ubo_surface_index_is_pushable(src)) return UINT32_MAX; assert(src.ssa->parent_instr->type == nir_instr_type_intrinsic); @@ -157,7 +157,7 @@ brw_nir_ubo_surface_index_get_push_block(nir_src src) * src[1] of that intrinsic. */ static inline unsigned -brw_nir_ubo_surface_index_get_bti(nir_src src) +elk_nir_ubo_surface_index_get_bti(nir_src src) { if (nir_src_is_const(src)) return nir_src_as_uint(src); @@ -182,41 +182,41 @@ brw_nir_ubo_surface_index_get_bti(nir_src src) return nir_src_as_uint(intrin->src[1]); } -void brw_preprocess_nir(const struct brw_compiler *compiler, +void elk_preprocess_nir(const struct elk_compiler *compiler, nir_shader *nir, - const struct brw_nir_compiler_opts *opts); + const struct elk_nir_compiler_opts *opts); void -brw_nir_link_shaders(const struct brw_compiler *compiler, +elk_nir_link_shaders(const struct elk_compiler *compiler, nir_shader *producer, nir_shader *consumer); -bool brw_nir_lower_cs_intrinsics(nir_shader *nir, +bool elk_nir_lower_cs_intrinsics(nir_shader *nir, const struct intel_device_info *devinfo, - struct brw_cs_prog_data *prog_data); -bool brw_nir_lower_alpha_to_coverage(nir_shader *shader, - const struct brw_wm_prog_key *key, - const struct brw_wm_prog_data *prog_data); -void brw_nir_lower_vs_inputs(nir_shader *nir, + struct elk_cs_prog_data *prog_data); +bool elk_nir_lower_alpha_to_coverage(nir_shader *shader, + const struct elk_wm_prog_key *key, + const struct elk_wm_prog_data *prog_data); +void elk_nir_lower_vs_inputs(nir_shader *nir, bool edgeflag_is_last, const uint8_t *vs_attrib_wa_flags); -void brw_nir_lower_vue_inputs(nir_shader *nir, +void elk_nir_lower_vue_inputs(nir_shader *nir, const struct intel_vue_map *vue_map); -void brw_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue); -void brw_nir_lower_fs_inputs(nir_shader *nir, +void elk_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue); +void elk_nir_lower_fs_inputs(nir_shader *nir, const struct intel_device_info *devinfo, - const struct brw_wm_prog_key *key); -void brw_nir_lower_vue_outputs(nir_shader *nir); -void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue, + const struct elk_wm_prog_key *key); +void elk_nir_lower_vue_outputs(nir_shader *nir); +void elk_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue, enum tess_primitive_mode tes_primitive_mode); -void brw_nir_lower_fs_outputs(nir_shader *nir); +void elk_nir_lower_fs_outputs(nir_shader *nir); -bool brw_nir_lower_cmat(nir_shader *nir, unsigned subgroup_size); +bool elk_nir_lower_cmat(nir_shader *nir, unsigned subgroup_size); -bool brw_nir_lower_shading_rate_output(nir_shader *nir); +bool elk_nir_lower_shading_rate_output(nir_shader *nir); -bool brw_nir_lower_sparse_intrinsics(nir_shader *nir); +bool elk_nir_lower_sparse_intrinsics(nir_shader *nir); -struct brw_nir_lower_storage_image_opts { +struct elk_nir_lower_storage_image_opts { const struct intel_device_info *devinfo; bool lower_loads; @@ -225,71 +225,71 @@ struct brw_nir_lower_storage_image_opts { bool lower_get_size; }; -bool brw_nir_lower_storage_image(nir_shader *nir, - const struct brw_nir_lower_storage_image_opts *opts); +bool elk_nir_lower_storage_image(nir_shader *nir, + const struct elk_nir_lower_storage_image_opts *opts); -bool brw_nir_lower_mem_access_bit_sizes(nir_shader *shader, +bool elk_nir_lower_mem_access_bit_sizes(nir_shader *shader, const struct intel_device_info *devinfo); -void brw_postprocess_nir(nir_shader *nir, - const struct brw_compiler *compiler, +void elk_postprocess_nir(nir_shader *nir, + const struct elk_compiler *compiler, bool debug_enabled, - enum brw_robustness_flags robust_flags); + enum elk_robustness_flags robust_flags); -bool brw_nir_apply_attribute_workarounds(nir_shader *nir, +bool elk_nir_apply_attribute_workarounds(nir_shader *nir, const uint8_t *attrib_wa_flags); -bool brw_nir_apply_trig_workarounds(nir_shader *nir); +bool elk_nir_apply_trig_workarounds(nir_shader *nir); -bool brw_nir_limit_trig_input_range_workaround(nir_shader *nir); +bool elk_nir_limit_trig_input_range_workaround(nir_shader *nir); -void brw_nir_apply_key(nir_shader *nir, - const struct brw_compiler *compiler, - const struct brw_base_prog_key *key, +void elk_nir_apply_key(nir_shader *nir, + const struct elk_compiler *compiler, + const struct elk_base_prog_key *key, unsigned max_subgroup_size); -unsigned brw_nir_api_subgroup_size(const nir_shader *nir, +unsigned elk_nir_api_subgroup_size(const nir_shader *nir, unsigned hw_subgroup_size); -enum brw_conditional_mod brw_cmod_for_nir_comparison(nir_op op); -enum lsc_opcode lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic); -enum brw_reg_type brw_type_for_nir_type(const struct intel_device_info *devinfo, +enum elk_conditional_mod elk_cmod_for_nir_comparison(nir_op op); +enum elk_lsc_opcode elk_lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic); +enum elk_reg_type elk_type_for_nir_type(const struct intel_device_info *devinfo, nir_alu_type type); -bool brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, +bool elk_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, nir_intrinsic_instr *low, nir_intrinsic_instr *high, void *data); -void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler, +void elk_nir_analyze_ubo_ranges(const struct elk_compiler *compiler, nir_shader *nir, - struct brw_ubo_range out_ranges[4]); + struct elk_ubo_range out_ranges[4]); -void brw_nir_optimize(nir_shader *nir, bool is_scalar, +void elk_nir_optimize(nir_shader *nir, bool is_scalar, const struct intel_device_info *devinfo); -nir_shader *brw_nir_create_passthrough_tcs(void *mem_ctx, - const struct brw_compiler *compiler, - const struct brw_tcs_prog_key *key); +nir_shader *elk_nir_create_passthrough_tcs(void *mem_ctx, + const struct elk_compiler *compiler, + const struct elk_tcs_prog_key *key); -#define BRW_NIR_FRAG_OUTPUT_INDEX_SHIFT 0 -#define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0) -#define BRW_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1 -#define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1) +#define ELK_NIR_FRAG_OUTPUT_INDEX_SHIFT 0 +#define ELK_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0) +#define ELK_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1 +#define ELK_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1) -bool brw_nir_move_interpolation_to_top(nir_shader *nir); -nir_def *brw_nir_load_global_const(nir_builder *b, +bool elk_nir_move_interpolation_to_top(nir_shader *nir); +nir_def *elk_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform, nir_def *base_addr, unsigned off); -const struct glsl_type *brw_nir_get_var_type(const struct nir_shader *nir, +const struct glsl_type *elk_nir_get_var_type(const struct nir_shader *nir, nir_variable *var); -void brw_nir_adjust_payload(nir_shader *shader); +void elk_nir_adjust_payload(nir_shader *shader); #ifdef __cplusplus } diff --git a/src/intel/compiler/elk/elk_nir_analyze_boolean_resolves.c b/src/intel/compiler/elk/elk_nir_analyze_boolean_resolves.c index 32bf27b4129..d51fa0f81cd 100644 --- a/src/intel/compiler/elk/elk_nir_analyze_boolean_resolves.c +++ b/src/intel/compiler/elk/elk_nir_analyze_boolean_resolves.c @@ -27,7 +27,7 @@ * This file implements an analysis pass that determines when we have to do * a boolean resolve on Gen <= 5. Instructions that need a boolean resolve * will have the booleans portion of the instr->pass_flags field set to - * BRW_NIR_BOOLEAN_NEEDS_RESOLVE. + * ELK_NIR_BOOLEAN_NEEDS_RESOLVE. */ @@ -41,13 +41,13 @@ static uint8_t get_resolve_status_for_src(nir_src *src) { nir_instr *src_instr = src->ssa->parent_instr; - uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK; + uint8_t resolve_status = src_instr->pass_flags & ELK_NIR_BOOLEAN_MASK; /* If the source instruction needs resolve, then from the perspective * of the user, it's a true boolean. */ - if (resolve_status == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) - resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE; + if (resolve_status == ELK_NIR_BOOLEAN_NEEDS_RESOLVE) + resolve_status = ELK_NIR_BOOLEAN_NO_RESOLVE; return resolve_status; } @@ -60,14 +60,14 @@ static bool src_mark_needs_resolve(nir_src *src, void *void_state) { nir_instr *src_instr = src->ssa->parent_instr; - uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK; + uint8_t resolve_status = src_instr->pass_flags & ELK_NIR_BOOLEAN_MASK; /* If the source instruction is unresolved, then mark it as needing * to be resolved. */ - if (resolve_status == BRW_NIR_BOOLEAN_UNRESOLVED) { - src_instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK; - src_instr->pass_flags |= BRW_NIR_BOOLEAN_NEEDS_RESOLVE; + if (resolve_status == ELK_NIR_BOOLEAN_UNRESOLVED) { + src_instr->pass_flags &= ~ELK_NIR_BOOLEAN_MASK; + src_instr->pass_flags |= ELK_NIR_BOOLEAN_NEEDS_RESOLVE; } return true; @@ -116,7 +116,7 @@ analyze_boolean_resolves_block(nir_block *block) * future, this may change and we'll have to remove some of the * above cases. */ - resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE; + resolve_status = ELK_NIR_BOOLEAN_NO_RESOLVE; break; case nir_op_mov: @@ -143,12 +143,12 @@ analyze_boolean_resolves_block(nir_block *block) if (src0_status == src1_status) { resolve_status = src0_status; - } else if (src0_status == BRW_NIR_NON_BOOLEAN || - src1_status == BRW_NIR_NON_BOOLEAN) { + } else if (src0_status == ELK_NIR_NON_BOOLEAN || + src1_status == ELK_NIR_NON_BOOLEAN) { /* If one of the sources is a non-boolean then the whole * thing is a non-boolean. */ - resolve_status = BRW_NIR_NON_BOOLEAN; + resolve_status = ELK_NIR_NON_BOOLEAN; } else { /* At this point one of them is a true boolean and one is a * boolean that needs a resolve. We could either resolve the @@ -157,7 +157,7 @@ analyze_boolean_resolves_block(nir_block *block) * of one. Just set this one to BOOLEAN_NO_RESOLVE and we'll * let the code below force a resolve on the unresolved source. */ - resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE; + resolve_status = ELK_NIR_BOOLEAN_NO_RESOLVE; } break; } @@ -168,7 +168,7 @@ analyze_boolean_resolves_block(nir_block *block) * them so the result will have to be resolved before it can be * used. */ - resolve_status = BRW_NIR_BOOLEAN_UNRESOLVED; + resolve_status = ELK_NIR_BOOLEAN_UNRESOLVED; /* Even though the destination is allowed to be left * unresolved, the sources are treated as regular integers or @@ -176,25 +176,25 @@ analyze_boolean_resolves_block(nir_block *block) */ nir_foreach_src(instr, src_mark_needs_resolve, NULL); } else { - resolve_status = BRW_NIR_NON_BOOLEAN; + resolve_status = ELK_NIR_NON_BOOLEAN; } } /* Go ahead allow unresolved booleans. */ - instr->pass_flags = (instr->pass_flags & ~BRW_NIR_BOOLEAN_MASK) | + instr->pass_flags = (instr->pass_flags & ~ELK_NIR_BOOLEAN_MASK) | resolve_status; /* Finally, resolve sources if it's needed */ switch (resolve_status) { - case BRW_NIR_BOOLEAN_NEEDS_RESOLVE: - case BRW_NIR_BOOLEAN_UNRESOLVED: + case ELK_NIR_BOOLEAN_NEEDS_RESOLVE: + case ELK_NIR_BOOLEAN_UNRESOLVED: /* This instruction is either unresolved or we're doing the * resolve here; leave the sources alone. */ break; - case BRW_NIR_BOOLEAN_NO_RESOLVE: - case BRW_NIR_NON_BOOLEAN: + case ELK_NIR_BOOLEAN_NO_RESOLVE: + case ELK_NIR_NON_BOOLEAN: nir_foreach_src(instr, src_mark_needs_resolve, NULL); break; @@ -214,11 +214,11 @@ analyze_boolean_resolves_block(nir_block *block) * Since load_const instructions don't have any sources, we don't * have to worry about resolving them. */ - instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK; + instr->pass_flags &= ~ELK_NIR_BOOLEAN_MASK; if (load->value[0].u32 == NIR_TRUE || load->value[0].u32 == NIR_FALSE) { - instr->pass_flags |= BRW_NIR_BOOLEAN_NO_RESOLVE; + instr->pass_flags |= ELK_NIR_BOOLEAN_NO_RESOLVE; } else { - instr->pass_flags |= BRW_NIR_NON_BOOLEAN; + instr->pass_flags |= ELK_NIR_NON_BOOLEAN; } continue; } @@ -227,8 +227,8 @@ analyze_boolean_resolves_block(nir_block *block) /* Everything else is an unknown non-boolean value and needs to * have all sources resolved. */ - instr->pass_flags = (instr->pass_flags & ~BRW_NIR_BOOLEAN_MASK) | - BRW_NIR_NON_BOOLEAN; + instr->pass_flags = (instr->pass_flags & ~ELK_NIR_BOOLEAN_MASK) | + ELK_NIR_NON_BOOLEAN; nir_foreach_src(instr, src_mark_needs_resolve, NULL); continue; } @@ -250,7 +250,7 @@ analyze_boolean_resolves_impl(nir_function_impl *impl) } void -brw_nir_analyze_boolean_resolves(nir_shader *shader) +elk_nir_analyze_boolean_resolves(nir_shader *shader) { nir_foreach_function_impl(impl, shader) { analyze_boolean_resolves_impl(impl); diff --git a/src/intel/compiler/elk/elk_nir_analyze_ubo_ranges.c b/src/intel/compiler/elk/elk_nir_analyze_ubo_ranges.c index 855de89257b..eb213e710ff 100644 --- a/src/intel/compiler/elk/elk_nir_analyze_ubo_ranges.c +++ b/src/intel/compiler/elk/elk_nir_analyze_ubo_ranges.c @@ -46,7 +46,7 @@ struct ubo_range_entry { - struct brw_ubo_range range; + struct elk_ubo_range range; int benefit; }; @@ -141,9 +141,9 @@ analyze_ubos_block(struct ubo_analysis_state *state, nir_block *block) continue; /* Not a uniform or UBO intrinsic */ } - if (brw_nir_ubo_surface_index_is_pushable(intrin->src[0]) && + if (elk_nir_ubo_surface_index_is_pushable(intrin->src[0]) && nir_src_is_const(intrin->src[1])) { - const int block = brw_nir_ubo_surface_index_get_push_block(intrin->src[0]); + const int block = elk_nir_ubo_surface_index_get_push_block(intrin->src[0]); const unsigned byte_offset = nir_src_as_uint(intrin->src[1]); const int offset = byte_offset / 32; @@ -187,9 +187,9 @@ print_ubo_entry(FILE *file, } void -brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler, +elk_nir_analyze_ubo_ranges(const struct elk_compiler *compiler, nir_shader *nir, - struct brw_ubo_range out_ranges[4]) + struct elk_ubo_range out_ranges[4]) { void *mem_ctx = ralloc_context(NULL); diff --git a/src/intel/compiler/elk/elk_nir_attribute_workarounds.c b/src/intel/compiler/elk/elk_nir_attribute_workarounds.c index 1bb64f96520..a817a005f3c 100644 --- a/src/intel/compiler/elk/elk_nir_attribute_workarounds.c +++ b/src/intel/compiler/elk/elk_nir_attribute_workarounds.c @@ -53,34 +53,34 @@ apply_attr_wa_instr(nir_builder *b, nir_instr *instr, void *cb_data) /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes * come in as floating point conversions of the integer values. */ - if (wa_flags & BRW_ATTRIB_WA_COMPONENT_MASK) { + if (wa_flags & ELK_ATTRIB_WA_COMPONENT_MASK) { nir_def *scaled = nir_fmul_imm(b, val, 1.0f / 65536.0f); nir_def *comps[4]; for (int i = 0; i < val->num_components; i++) { - bool rescale = i < (wa_flags & BRW_ATTRIB_WA_COMPONENT_MASK); + bool rescale = i < (wa_flags & ELK_ATTRIB_WA_COMPONENT_MASK); comps[i] = nir_channel(b, rescale ? scaled : val, i); } val = nir_vec(b, comps, val->num_components); } /* Do sign recovery for 2101010 formats if required. */ - if (wa_flags & BRW_ATTRIB_WA_SIGN) { + if (wa_flags & ELK_ATTRIB_WA_SIGN) { /* sign recovery shift: <22, 22, 22, 30> */ nir_def *shift = nir_imm_ivec4(b, 22, 22, 22, 30); val = nir_ishr(b, nir_ishl(b, val, shift), shift); } /* Apply BGRA swizzle if required. */ - if (wa_flags & BRW_ATTRIB_WA_BGRA) { + if (wa_flags & ELK_ATTRIB_WA_BGRA) { val = nir_swizzle(b, val, (unsigned[4]){2,1,0,3}, 4); } - if (wa_flags & BRW_ATTRIB_WA_NORMALIZE) { + if (wa_flags & ELK_ATTRIB_WA_NORMALIZE) { /* ES 3.0 has different rules for converting signed normalized * fixed-point numbers than desktop GL. */ - if (wa_flags & BRW_ATTRIB_WA_SIGN) { + if (wa_flags & ELK_ATTRIB_WA_SIGN) { /* According to equation 2.2 of the ES 3.0 specification, * signed normalization conversion is done by: * @@ -110,8 +110,8 @@ apply_attr_wa_instr(nir_builder *b, nir_instr *instr, void *cb_data) } } - if (wa_flags & BRW_ATTRIB_WA_SCALE) { - val = (wa_flags & BRW_ATTRIB_WA_SIGN) ? nir_i2f32(b, val) + if (wa_flags & ELK_ATTRIB_WA_SCALE) { + val = (wa_flags & ELK_ATTRIB_WA_SIGN) ? nir_i2f32(b, val) : nir_u2f32(b, val); } @@ -122,7 +122,7 @@ apply_attr_wa_instr(nir_builder *b, nir_instr *instr, void *cb_data) } bool -brw_nir_apply_attribute_workarounds(nir_shader *shader, +elk_nir_apply_attribute_workarounds(nir_shader *shader, const uint8_t *attrib_wa_flags) { return nir_shader_instructions_pass(shader, apply_attr_wa_instr, diff --git a/src/intel/compiler/elk/elk_nir_lower_alpha_to_coverage.c b/src/intel/compiler/elk/elk_nir_lower_alpha_to_coverage.c index d295d40e87a..c4e2bf906bb 100644 --- a/src/intel/compiler/elk/elk_nir_lower_alpha_to_coverage.c +++ b/src/intel/compiler/elk/elk_nir_lower_alpha_to_coverage.c @@ -78,12 +78,12 @@ build_dither_mask(nir_builder *b, nir_def *color) } bool -brw_nir_lower_alpha_to_coverage(nir_shader *shader, - const struct brw_wm_prog_key *key, - const struct brw_wm_prog_data *prog_data) +elk_nir_lower_alpha_to_coverage(nir_shader *shader, + const struct elk_wm_prog_key *key, + const struct elk_wm_prog_data *prog_data) { assert(shader->info.stage == MESA_SHADER_FRAGMENT); - assert(key->alpha_to_coverage != BRW_NEVER); + assert(key->alpha_to_coverage != ELK_NEVER); nir_function_impl *impl = nir_shader_get_entrypoint(shader); @@ -113,14 +113,14 @@ brw_nir_lower_alpha_to_coverage(nir_shader *shader, assert(block->cf_node.parent == &impl->cf_node); assert(nir_cf_node_is_last(&block->cf_node)); - /* See store_output in fs_visitor::nir_emit_fs_intrinsic */ + /* See store_output in elk_fs_visitor::nir_emit_fs_intrinsic */ const unsigned store_offset = nir_src_as_uint(intrin->src[1]); const unsigned driver_location = nir_intrinsic_base(intrin) + - SET_FIELD(store_offset, BRW_NIR_FRAG_OUTPUT_LOCATION); + SET_FIELD(store_offset, ELK_NIR_FRAG_OUTPUT_LOCATION); /* Extract the FRAG_RESULT */ const unsigned location = - GET_FIELD(driver_location, BRW_NIR_FRAG_OUTPUT_LOCATION); + GET_FIELD(driver_location, ELK_NIR_FRAG_OUTPUT_LOCATION); if (location == FRAG_RESULT_SAMPLE_MASK) { assert(sample_mask_write == NULL); @@ -171,7 +171,7 @@ brw_nir_lower_alpha_to_coverage(nir_shader *shader, nir_def *dither_mask = build_dither_mask(&b, color0); dither_mask = nir_iand(&b, sample_mask, dither_mask); - if (key->alpha_to_coverage == BRW_SOMETIMES) { + if (key->alpha_to_coverage == ELK_SOMETIMES) { nir_def *push_flags = nir_load_uniform(&b, 1, 32, nir_imm_int(&b, prog_data->msaa_flags_param * 4)); nir_def *alpha_to_coverage = diff --git a/src/intel/compiler/elk/elk_nir_lower_cs_intrinsics.c b/src/intel/compiler/elk/elk_nir_lower_cs_intrinsics.c index cc1ac02fa82..07e4ff96210 100644 --- a/src/intel/compiler/elk/elk_nir_lower_cs_intrinsics.c +++ b/src/intel/compiler/elk/elk_nir_lower_cs_intrinsics.c @@ -295,9 +295,9 @@ lower_cs_intrinsics_convert_impl(struct lower_intrinsics_state *state) } bool -brw_nir_lower_cs_intrinsics(nir_shader *nir, +elk_nir_lower_cs_intrinsics(nir_shader *nir, const struct intel_device_info *devinfo, - struct brw_cs_prog_data *prog_data) + struct elk_cs_prog_data *prog_data) { assert(gl_shader_stage_uses_workgroup(nir->info.stage)); diff --git a/src/intel/compiler/elk/elk_nir_lower_storage_image.c b/src/intel/compiler/elk/elk_nir_lower_storage_image.c index fe610b2218c..b945795bd36 100644 --- a/src/intel/compiler/elk/elk_nir_lower_storage_image.c +++ b/src/intel/compiler/elk/elk_nir_lower_storage_image.c @@ -701,13 +701,13 @@ lower_image_size_instr(nir_builder *b, } static bool -brw_nir_lower_storage_image_instr(nir_builder *b, +elk_nir_lower_storage_image_instr(nir_builder *b, nir_instr *instr, void *cb_data) { if (instr->type != nir_instr_type_intrinsic) return false; - const struct brw_nir_lower_storage_image_opts *opts = cb_data; + const struct elk_nir_lower_storage_image_opts *opts = cb_data; nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); switch (intrin->intrinsic) { @@ -744,8 +744,8 @@ brw_nir_lower_storage_image_instr(nir_builder *b, } bool -brw_nir_lower_storage_image(nir_shader *shader, - const struct brw_nir_lower_storage_image_opts *opts) +elk_nir_lower_storage_image(nir_shader *shader, + const struct elk_nir_lower_storage_image_opts *opts) { bool progress = false; @@ -757,7 +757,7 @@ brw_nir_lower_storage_image(nir_shader *shader, progress |= nir_lower_image(shader, &image_options); progress |= nir_shader_instructions_pass(shader, - brw_nir_lower_storage_image_instr, + elk_nir_lower_storage_image_instr, nir_metadata_none, (void *)opts); diff --git a/src/intel/compiler/elk/elk_nir_trig_workarounds.py b/src/intel/compiler/elk/elk_nir_trig_workarounds.py index 94a318f85e8..3aee570cdb0 100644 --- a/src/intel/compiler/elk/elk_nir_trig_workarounds.py +++ b/src/intel/compiler/elk/elk_nir_trig_workarounds.py @@ -57,9 +57,9 @@ def run(): import nir_algebraic # pylint: disable=import-error print('#include "elk_nir.h"') - print(nir_algebraic.AlgebraicPass("brw_nir_apply_trig_workarounds", + print(nir_algebraic.AlgebraicPass("elk_nir_apply_trig_workarounds", TRIG_WORKAROUNDS).render()) - print(nir_algebraic.AlgebraicPass("brw_nir_limit_trig_input_range_workaround", + print(nir_algebraic.AlgebraicPass("elk_nir_limit_trig_input_range_workaround", LIMIT_TRIG_INPUT_RANGE_WORKAROUND).render()) diff --git a/src/intel/compiler/elk/elk_packed_float.c b/src/intel/compiler/elk/elk_packed_float.c index 586a6458d0b..65ed9ce0483 100644 --- a/src/intel/compiler/elk/elk_packed_float.c +++ b/src/intel/compiler/elk/elk_packed_float.c @@ -33,7 +33,7 @@ union fu { }; int -brw_float_to_vf(float f) +elk_float_to_vf(float f) { union fu fu = { .f = f }; @@ -57,7 +57,7 @@ brw_float_to_vf(float f) } float -brw_vf_to_float(unsigned char vf) +elk_vf_to_float(unsigned char vf) { union fu fu; diff --git a/src/intel/compiler/elk/elk_predicated_break.cpp b/src/intel/compiler/elk/elk_predicated_break.cpp index d5bca2aa7c5..4936ddf9e83 100644 --- a/src/intel/compiler/elk/elk_predicated_break.cpp +++ b/src/intel/compiler/elk/elk_predicated_break.cpp @@ -99,7 +99,7 @@ has_continue(const struct loop_continue_tracking *s) } bool -opt_predicated_break(backend_shader *s) +elk_opt_predicated_break(elk_backend_shader *s) { bool progress = false; struct loop_continue_tracking state = { {0, }, 0 }; @@ -108,51 +108,51 @@ opt_predicated_break(backend_shader *s) /* DO instructions, by definition, can only be found at the beginning of * basic blocks. */ - backend_instruction *const do_inst = block->start(); + elk_backend_instruction *const do_inst = block->start(); /* BREAK, CONTINUE, and WHILE instructions, by definition, can only be * found at the ends of basic blocks. */ - backend_instruction *jump_inst = block->end(); + elk_backend_instruction *jump_inst = block->end(); - if (do_inst->opcode == BRW_OPCODE_DO) + if (do_inst->opcode == ELK_OPCODE_DO) enter_loop(&state); - if (jump_inst->opcode == BRW_OPCODE_CONTINUE) + if (jump_inst->opcode == ELK_OPCODE_CONTINUE) set_continue(&state); - else if (jump_inst->opcode == BRW_OPCODE_WHILE) + else if (jump_inst->opcode == ELK_OPCODE_WHILE) exit_loop(&state); if (block->start_ip != block->end_ip) continue; - if (jump_inst->opcode != BRW_OPCODE_BREAK && - jump_inst->opcode != BRW_OPCODE_CONTINUE) + if (jump_inst->opcode != ELK_OPCODE_BREAK && + jump_inst->opcode != ELK_OPCODE_CONTINUE) continue; - backend_instruction *if_inst = block->prev()->end(); - if (if_inst->opcode != BRW_OPCODE_IF) + elk_backend_instruction *if_inst = block->prev()->end(); + if (if_inst->opcode != ELK_OPCODE_IF) continue; - backend_instruction *endif_inst = block->next()->start(); - if (endif_inst->opcode != BRW_OPCODE_ENDIF) + elk_backend_instruction *endif_inst = block->next()->start(); + if (endif_inst->opcode != ELK_OPCODE_ENDIF) continue; - bblock_t *jump_block = block; - bblock_t *if_block = jump_block->prev(); - bblock_t *endif_block = jump_block->next(); + elk_bblock_t *jump_block = block; + elk_bblock_t *if_block = jump_block->prev(); + elk_bblock_t *endif_block = jump_block->next(); jump_inst->predicate = if_inst->predicate; jump_inst->predicate_inverse = if_inst->predicate_inverse; - bblock_t *earlier_block = if_block; + elk_bblock_t *earlier_block = if_block; if (if_block->start_ip == if_block->end_ip) { earlier_block = if_block->prev(); } if_inst->remove(if_block); - bblock_t *later_block = endif_block; + elk_bblock_t *later_block = endif_block; if (endif_block->start_ip == endif_block->end_ip) { later_block = endif_block->next(); } @@ -165,7 +165,7 @@ opt_predicated_break(backend_shader *s) * problem. */ assert(earlier_block->start() == NULL || - earlier_block->start()->opcode != BRW_OPCODE_DO); + earlier_block->start()->opcode != ELK_OPCODE_DO); earlier_block->unlink_children(); earlier_block->add_successor(s->cfg->mem_ctx, jump_block, @@ -180,12 +180,12 @@ opt_predicated_break(backend_shader *s) * one. Instead, promote the link to logical. */ bool need_to_link = true; - foreach_list_typed(bblock_link, link, link, &jump_block->children) { + foreach_list_typed(elk_bblock_link, link, link, &jump_block->children) { if (link->block == later_block) { assert(later_block->starts_with_control_flow()); /* Update the link from later_block back to jump_block. */ - foreach_list_typed(bblock_link, parent_link, link, &later_block->parents) { + foreach_list_typed(elk_bblock_link, parent_link, link, &later_block->parents) { if (parent_link->block == jump_block) { parent_link->kind = bblock_link_logical; } @@ -218,12 +218,12 @@ opt_predicated_break(backend_shader *s) * could terminate prematurely. This can occur if the loop contains a * CONT instruction. */ - bblock_t *while_block = earlier_block->next(); - backend_instruction *while_inst = while_block->start(); + elk_bblock_t *while_block = earlier_block->next(); + elk_backend_instruction *while_inst = while_block->start(); - if (jump_inst->opcode == BRW_OPCODE_BREAK && - while_inst->opcode == BRW_OPCODE_WHILE && - while_inst->predicate == BRW_PREDICATE_NONE && + if (jump_inst->opcode == ELK_OPCODE_BREAK && + while_inst->opcode == ELK_OPCODE_WHILE && + while_inst->predicate == ELK_PREDICATE_NONE && !has_continue(&state)) { jump_inst->remove(earlier_block); while_inst->predicate = jump_inst->predicate; diff --git a/src/intel/compiler/elk/elk_private.h b/src/intel/compiler/elk/elk_private.h index 8763e6213cf..f83e57d2517 100644 --- a/src/intel/compiler/elk/elk_private.h +++ b/src/intel/compiler/elk/elk_private.h @@ -29,15 +29,15 @@ #include -unsigned brw_required_dispatch_width(const struct shader_info *info); +unsigned elk_required_dispatch_width(const struct shader_info *info); static constexpr int SIMD_COUNT = 3; -struct brw_simd_selection_state { +struct elk_simd_selection_state { const struct intel_device_info *devinfo; - std::variant prog_data; + std::variant prog_data; unsigned required_width; @@ -47,7 +47,7 @@ struct brw_simd_selection_state { bool spilled[SIMD_COUNT]; }; -inline int brw_simd_first_compiled(const brw_simd_selection_state &state) +inline int elk_simd_first_compiled(const elk_simd_selection_state &state) { for (int i = 0; i < SIMD_COUNT; i++) { if (state.compiled[i]) @@ -56,21 +56,21 @@ inline int brw_simd_first_compiled(const brw_simd_selection_state &state) return -1; } -inline bool brw_simd_any_compiled(const brw_simd_selection_state &state) +inline bool elk_simd_any_compiled(const elk_simd_selection_state &state) { - return brw_simd_first_compiled(state) >= 0; + return elk_simd_first_compiled(state) >= 0; } -bool brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd); +bool elk_simd_should_compile(elk_simd_selection_state &state, unsigned simd); -void brw_simd_mark_compiled(brw_simd_selection_state &state, unsigned simd, bool spilled); +void elk_simd_mark_compiled(elk_simd_selection_state &state, unsigned simd, bool spilled); -int brw_simd_select(const brw_simd_selection_state &state); +int elk_simd_select(const elk_simd_selection_state &state); -int brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo, - const struct brw_cs_prog_data *prog_data, +int elk_simd_select_for_workgroup_size(const struct intel_device_info *devinfo, + const struct elk_cs_prog_data *prog_data, const unsigned *sizes); -bool brw_should_print_shader(const nir_shader *shader, uint64_t debug_flag); +bool elk_should_print_shader(const nir_shader *shader, uint64_t debug_flag); #endif // ELK_PRIVATE_H diff --git a/src/intel/compiler/elk/elk_reg.h b/src/intel/compiler/elk/elk_reg.h index 1f0517afbd9..c12ef47ec8f 100644 --- a/src/intel/compiler/elk/elk_reg.h +++ b/src/intel/compiler/elk/elk_reg.h @@ -31,12 +31,12 @@ /** @file elk_reg.h * - * This file defines struct brw_reg, which is our representation for EU + * This file defines struct elk_reg, which is our representation for EU * registers. They're not a hardware specific format, just an abstraction * that intends to capture the full flexibility of the hardware registers. * - * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode - * the abstract brw_reg type into the actual hardware instruction encoding. + * The elk_eu_emit.c layer's elk_set_dest/elk_set_src[01] functions encode + * the abstract elk_reg type into the actual hardware instruction encoding. */ #ifndef ELK_REG_H @@ -58,7 +58,7 @@ extern "C" { struct intel_device_info; /** Size of general purpose register space in REG_SIZE units */ -#define BRW_MAX_GRF 128 +#define ELK_MAX_GRF 128 #define XE2_MAX_GRF 256 /** @@ -66,7 +66,7 @@ struct intel_device_info; * * On gfx7, MRFs are no longer used, and contiguous GRFs are used instead. We * haven't converted our compiler to be aware of this, so it asks for MRFs and - * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The + * elk_eu_emit.c quietly converts them to be accesses of the top GRFs. The * register allocators have to be careful of this to avoid corrupting the "MRF"s * with actual GRF allocations. */ @@ -76,46 +76,46 @@ struct intel_device_info; * BRW hardware swizzles. * Only defines XYZW to ensure it can be contained in 2 bits */ -#define BRW_SWIZZLE_X 0 -#define BRW_SWIZZLE_Y 1 -#define BRW_SWIZZLE_Z 2 -#define BRW_SWIZZLE_W 3 +#define ELK_SWIZZLE_X 0 +#define ELK_SWIZZLE_Y 1 +#define ELK_SWIZZLE_Z 2 +#define ELK_SWIZZLE_W 3 /** Number of message register file registers */ -#define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16) +#define ELK_MAX_MRF(gen) (gen == 6 ? 24 : 16) -#define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6)) -#define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3) +#define ELK_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6)) +#define ELK_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3) -#define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3) -#define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3) -#define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0) -#define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1) -#define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2) -#define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3) -#define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1) -#define BRW_SWIZZLE_YXYX BRW_SWIZZLE4(1,0,1,0) -#define BRW_SWIZZLE_XZXZ BRW_SWIZZLE4(0,2,0,2) -#define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3) -#define BRW_SWIZZLE_YWYW BRW_SWIZZLE4(1,3,1,3) -#define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3) -#define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3) -#define BRW_SWIZZLE_WZWZ BRW_SWIZZLE4(3,2,3,2) -#define BRW_SWIZZLE_WZYX BRW_SWIZZLE4(3,2,1,0) -#define BRW_SWIZZLE_XXZZ BRW_SWIZZLE4(0,0,2,2) -#define BRW_SWIZZLE_YYWW BRW_SWIZZLE4(1,1,3,3) -#define BRW_SWIZZLE_YXWZ BRW_SWIZZLE4(1,0,3,2) +#define ELK_SWIZZLE_NOOP ELK_SWIZZLE4(0,1,2,3) +#define ELK_SWIZZLE_XYZW ELK_SWIZZLE4(0,1,2,3) +#define ELK_SWIZZLE_XXXX ELK_SWIZZLE4(0,0,0,0) +#define ELK_SWIZZLE_YYYY ELK_SWIZZLE4(1,1,1,1) +#define ELK_SWIZZLE_ZZZZ ELK_SWIZZLE4(2,2,2,2) +#define ELK_SWIZZLE_WWWW ELK_SWIZZLE4(3,3,3,3) +#define ELK_SWIZZLE_XYXY ELK_SWIZZLE4(0,1,0,1) +#define ELK_SWIZZLE_YXYX ELK_SWIZZLE4(1,0,1,0) +#define ELK_SWIZZLE_XZXZ ELK_SWIZZLE4(0,2,0,2) +#define ELK_SWIZZLE_YZXW ELK_SWIZZLE4(1,2,0,3) +#define ELK_SWIZZLE_YWYW ELK_SWIZZLE4(1,3,1,3) +#define ELK_SWIZZLE_ZXYW ELK_SWIZZLE4(2,0,1,3) +#define ELK_SWIZZLE_ZWZW ELK_SWIZZLE4(2,3,2,3) +#define ELK_SWIZZLE_WZWZ ELK_SWIZZLE4(3,2,3,2) +#define ELK_SWIZZLE_WZYX ELK_SWIZZLE4(3,2,1,0) +#define ELK_SWIZZLE_XXZZ ELK_SWIZZLE4(0,0,2,2) +#define ELK_SWIZZLE_YYWW ELK_SWIZZLE4(1,1,3,3) +#define ELK_SWIZZLE_YXWZ ELK_SWIZZLE4(1,0,3,2) -#define BRW_SWZ_COMP_INPUT(comp) (BRW_SWIZZLE_XYZW >> ((comp)*2)) -#define BRW_SWZ_COMP_OUTPUT(comp) (BRW_SWIZZLE_XYZW << ((comp)*2)) +#define ELK_SWZ_COMP_INPUT(comp) (ELK_SWIZZLE_XYZW >> ((comp)*2)) +#define ELK_SWZ_COMP_OUTPUT(comp) (ELK_SWIZZLE_XYZW << ((comp)*2)) static inline bool -brw_is_single_value_swizzle(unsigned swiz) +elk_is_single_value_swizzle(unsigned swiz) { - return (swiz == BRW_SWIZZLE_XXXX || - swiz == BRW_SWIZZLE_YYYY || - swiz == BRW_SWIZZLE_ZZZZ || - swiz == BRW_SWIZZLE_WWWW); + return (swiz == ELK_SWIZZLE_XXXX || + swiz == ELK_SWIZZLE_YYYY || + swiz == ELK_SWIZZLE_ZZZZ || + swiz == ELK_SWIZZLE_WWWW); } /** @@ -124,13 +124,13 @@ brw_is_single_value_swizzle(unsigned swiz) * composition. */ static inline unsigned -brw_compose_swizzle(unsigned swz0, unsigned swz1) +elk_compose_swizzle(unsigned swz0, unsigned swz1) { - return BRW_SWIZZLE4( - BRW_GET_SWZ(swz1, BRW_GET_SWZ(swz0, 0)), - BRW_GET_SWZ(swz1, BRW_GET_SWZ(swz0, 1)), - BRW_GET_SWZ(swz1, BRW_GET_SWZ(swz0, 2)), - BRW_GET_SWZ(swz1, BRW_GET_SWZ(swz0, 3))); + return ELK_SWIZZLE4( + ELK_GET_SWZ(swz1, ELK_GET_SWZ(swz0, 0)), + ELK_GET_SWZ(swz1, ELK_GET_SWZ(swz0, 1)), + ELK_GET_SWZ(swz1, ELK_GET_SWZ(swz0, 2)), + ELK_GET_SWZ(swz1, ELK_GET_SWZ(swz0, 3))); } /** @@ -138,12 +138,12 @@ brw_compose_swizzle(unsigned swz0, unsigned swz1) * (AKA image). */ static inline unsigned -brw_apply_swizzle_to_mask(unsigned swz, unsigned mask) +elk_apply_swizzle_to_mask(unsigned swz, unsigned mask) { unsigned result = 0; for (unsigned i = 0; i < 4; i++) { - if (mask & (1 << BRW_GET_SWZ(swz, i))) + if (mask & (1 << ELK_GET_SWZ(swz, i))) result |= 1 << i; } @@ -156,13 +156,13 @@ brw_apply_swizzle_to_mask(unsigned swz, unsigned mask) * read from a swizzled source given the instruction writemask. */ static inline unsigned -brw_apply_inv_swizzle_to_mask(unsigned swz, unsigned mask) +elk_apply_inv_swizzle_to_mask(unsigned swz, unsigned mask) { unsigned result = 0; for (unsigned i = 0; i < 4; i++) { if (mask & (1 << i)) - result |= 1 << BRW_GET_SWZ(swz, i); + result |= 1 << ELK_GET_SWZ(swz, i); } return result; @@ -174,15 +174,15 @@ brw_apply_inv_swizzle_to_mask(unsigned swz, unsigned mask) * mask, assuming that \p mask is non-zero. The constructed swizzle will * satisfy the property that for any instruction OP and any mask: * - * brw_OP(p, brw_writemask(dst, mask), - * brw_swizzle(src, brw_swizzle_for_mask(mask))); + * elk_OP(p, elk_writemask(dst, mask), + * elk_swizzle(src, elk_swizzle_for_mask(mask))); * * will be equivalent to the same instruction without swizzle: * - * brw_OP(p, brw_writemask(dst, mask), src); + * elk_OP(p, elk_writemask(dst, mask), src); */ static inline unsigned -brw_swizzle_for_mask(unsigned mask) +elk_swizzle_for_mask(unsigned mask) { unsigned last = (mask ? ffs(mask) - 1 : 0); unsigned swz[4]; @@ -190,7 +190,7 @@ brw_swizzle_for_mask(unsigned mask) for (unsigned i = 0; i < 4; i++) last = swz[i] = (mask & (1 << i) ? i : last); - return BRW_SWIZZLE4(swz[0], swz[1], swz[2], swz[3]); + return ELK_SWIZZLE4(swz[0], swz[1], swz[2], swz[3]); } /** @@ -200,22 +200,22 @@ brw_swizzle_for_mask(unsigned mask) * those other channels are used. */ static inline unsigned -brw_swizzle_for_size(unsigned n) +elk_swizzle_for_size(unsigned n) { - return brw_swizzle_for_mask((1 << n) - 1); + return elk_swizzle_for_mask((1 << n) - 1); } /** - * Converse of brw_swizzle_for_mask(). Returns the mask of components + * Converse of elk_swizzle_for_mask(). Returns the mask of components * accessed by the specified swizzle \p swz. */ static inline unsigned -brw_mask_for_swizzle(unsigned swz) +elk_mask_for_swizzle(unsigned swz) { - return brw_apply_inv_swizzle_to_mask(swz, ~0); + return elk_apply_inv_swizzle_to_mask(swz, ~0); } -uint32_t brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz); +uint32_t elk_swizzle_immediate(enum elk_reg_type type, uint32_t x, unsigned swz); #define REG_SIZE (8*4) @@ -225,11 +225,11 @@ uint32_t brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz) * WM programs to implement shaders decomposed into "channel serial" * or "structure of array" form: */ -struct brw_reg { +struct elk_reg { union { struct { - enum brw_reg_type type:4; - enum brw_reg_file file:3; /* :2 hardware format */ + enum elk_reg_type type:4; + enum elk_reg_file file:3; /* :2 hardware format */ unsigned negate:1; /* source only */ unsigned abs:1; /* source only */ unsigned address_mode:1; /* relative addressing, hopefully! */ @@ -261,15 +261,15 @@ struct brw_reg { }; static inline unsigned -phys_nr(const struct intel_device_info *devinfo, const struct brw_reg reg) +phys_nr(const struct intel_device_info *devinfo, const struct elk_reg reg) { if (devinfo->ver >= 20) { - if (reg.file == BRW_GENERAL_REGISTER_FILE) + if (reg.file == ELK_GENERAL_REGISTER_FILE) return reg.nr / 2; - else if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE && - reg.nr >= BRW_ARF_ACCUMULATOR && - reg.nr < BRW_ARF_FLAG) - return BRW_ARF_ACCUMULATOR + (reg.nr - BRW_ARF_ACCUMULATOR) / 2; + else if (reg.file == ELK_ARCHITECTURE_REGISTER_FILE && + reg.nr >= ELK_ARF_ACCUMULATOR && + reg.nr < ELK_ARF_FLAG) + return ELK_ARF_ACCUMULATOR + (reg.nr - ELK_ARF_ACCUMULATOR) / 2; else return reg.nr; } else { @@ -278,13 +278,13 @@ phys_nr(const struct intel_device_info *devinfo, const struct brw_reg reg) } static inline unsigned -phys_subnr(const struct intel_device_info *devinfo, const struct brw_reg reg) +phys_subnr(const struct intel_device_info *devinfo, const struct elk_reg reg) { if (devinfo->ver >= 20) { - if (reg.file == BRW_GENERAL_REGISTER_FILE || - (reg.file == BRW_ARCHITECTURE_REGISTER_FILE && - reg.nr >= BRW_ARF_ACCUMULATOR && - reg.nr < BRW_ARF_FLAG)) + if (reg.file == ELK_GENERAL_REGISTER_FILE || + (reg.file == ELK_ARCHITECTURE_REGISTER_FILE && + reg.nr >= ELK_ARF_ACCUMULATOR && + reg.nr < ELK_ARF_FLAG)) return (reg.nr & 1) * REG_SIZE + reg.subnr; else return reg.subnr; @@ -294,62 +294,62 @@ phys_subnr(const struct intel_device_info *devinfo, const struct brw_reg reg) } static inline bool -brw_regs_equal(const struct brw_reg *a, const struct brw_reg *b) +elk_regs_equal(const struct elk_reg *a, const struct elk_reg *b) { return a->bits == b->bits && a->u64 == b->u64; } static inline bool -brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b) +elk_regs_negative_equal(const struct elk_reg *a, const struct elk_reg *b) { if (a->file == IMM) { if (a->bits != b->bits) return false; - switch ((enum brw_reg_type) a->type) { - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_Q: + switch ((enum elk_reg_type) a->type) { + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_Q: return a->d64 == -b->d64; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: return a->df == -b->df; - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_D: return a->d == -b->d; - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: return a->f == -b->f; - case BRW_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_VF: /* It is tempting to treat 0 as a negation of 0 (and -0 as a negation * of -0). There are occasions where 0 or -0 is used and the exact * bit pattern is desired. At the very least, changing this to allow * 0 as a negation of 0 causes some fp64 tests to fail on IVB. */ return a->ud == (b->ud ^ 0x80808080); - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UV: - case BRW_REGISTER_TYPE_V: - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_HF: /* FINISHME: Implement support for these types once there is * something in the compiler that can generate them. Until then, * they cannot be tested. */ return false; - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_NF: default: unreachable("not reached"); } } else { - struct brw_reg tmp = *a; + struct elk_reg tmp = *a; tmp.negate = !tmp.negate; - return brw_regs_equal(&tmp, b); + return elk_regs_equal(&tmp, b); } } -struct brw_indirect { +struct elk_indirect { unsigned addr_subnr:4; int addr_offset:10; unsigned pad:18; @@ -360,43 +360,43 @@ static inline unsigned type_sz(unsigned type) { switch(type) { - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_Q: - case BRW_REGISTER_TYPE_DF: - case BRW_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_NF: return 8; - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_F: - case BRW_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_VF: return 4; - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_HF: /* [U]V components are 4-bit, but HW unpacks them to 16-bit (2 bytes) */ - case BRW_REGISTER_TYPE_UV: - case BRW_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_V: return 2; - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_B: return 1; default: unreachable("not reached"); } } -static inline enum brw_reg_type -get_exec_type(const enum brw_reg_type type) +static inline enum elk_reg_type +get_exec_type(const enum elk_reg_type type) { switch (type) { - case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_V: - return BRW_REGISTER_TYPE_W; - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_UV: - return BRW_REGISTER_TYPE_UW; - case BRW_REGISTER_TYPE_VF: - return BRW_REGISTER_TYPE_F; + case ELK_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_V: + return ELK_REGISTER_TYPE_W; + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_UV: + return ELK_REGISTER_TYPE_UW; + case ELK_REGISTER_TYPE_VF: + return ELK_REGISTER_TYPE_F; default: return type; } @@ -405,65 +405,65 @@ get_exec_type(const enum brw_reg_type type) /** * Return an integer type of the requested size and signedness. */ -static inline enum brw_reg_type -brw_int_type(unsigned sz, bool is_signed) +static inline enum elk_reg_type +elk_int_type(unsigned sz, bool is_signed) { switch (sz) { case 1: - return (is_signed ? BRW_REGISTER_TYPE_B : BRW_REGISTER_TYPE_UB); + return (is_signed ? ELK_REGISTER_TYPE_B : ELK_REGISTER_TYPE_UB); case 2: - return (is_signed ? BRW_REGISTER_TYPE_W : BRW_REGISTER_TYPE_UW); + return (is_signed ? ELK_REGISTER_TYPE_W : ELK_REGISTER_TYPE_UW); case 4: - return (is_signed ? BRW_REGISTER_TYPE_D : BRW_REGISTER_TYPE_UD); + return (is_signed ? ELK_REGISTER_TYPE_D : ELK_REGISTER_TYPE_UD); case 8: - return (is_signed ? BRW_REGISTER_TYPE_Q : BRW_REGISTER_TYPE_UQ); + return (is_signed ? ELK_REGISTER_TYPE_Q : ELK_REGISTER_TYPE_UQ); default: unreachable("Not reached."); } } /** - * Construct a brw_reg. - * \param file one of the BRW_x_REGISTER_FILE values + * Construct a elk_reg. + * \param file one of the ELK_x_REGISTER_FILE values * \param nr register number/index * \param subnr register sub number * \param negate register negate modifier * \param abs register abs modifier - * \param type one of BRW_REGISTER_TYPE_x - * \param vstride one of BRW_VERTICAL_STRIDE_x - * \param width one of BRW_WIDTH_x - * \param hstride one of BRW_HORIZONTAL_STRIDE_x - * \param swizzle one of BRW_SWIZZLE_x + * \param type one of ELK_REGISTER_TYPE_x + * \param vstride one of ELK_VERTICAL_STRIDE_x + * \param width one of ELK_WIDTH_x + * \param hstride one of ELK_HORIZONTAL_STRIDE_x + * \param swizzle one of ELK_SWIZZLE_x * \param writemask WRITEMASK_X/Y/Z/W bitfield */ -static inline struct brw_reg -brw_reg(enum brw_reg_file file, +static inline struct elk_reg +elk_reg(enum elk_reg_file file, unsigned nr, unsigned subnr, unsigned negate, unsigned abs, - enum brw_reg_type type, + enum elk_reg_type type, unsigned vstride, unsigned width, unsigned hstride, unsigned swizzle, unsigned writemask) { - struct brw_reg reg; - if (file == BRW_GENERAL_REGISTER_FILE) + struct elk_reg reg; + if (file == ELK_GENERAL_REGISTER_FILE) assert(nr < XE2_MAX_GRF); - else if (file == BRW_ARCHITECTURE_REGISTER_FILE) - assert(nr <= BRW_ARF_TIMESTAMP); + else if (file == ELK_ARCHITECTURE_REGISTER_FILE) + assert(nr <= ELK_ARF_TIMESTAMP); /* Asserting on the MRF register number requires to know the hardware gen * (gfx6 has 24 MRF registers), which we don't know here, so we assert - * for that in the generators and in brw_eu_emit.c + * for that in the generators and in elk_eu_emit.c */ reg.type = type; reg.file = file; reg.negate = negate; reg.abs = abs; - reg.address_mode = BRW_ADDRESS_DIRECT; + reg.address_mode = ELK_ADDRESS_DIRECT; reg.pad0 = 0; reg.subnr = subnr * type_sz(type); reg.nr = nr; @@ -485,141 +485,141 @@ brw_reg(enum brw_reg_file file, } /** Construct float[16] register */ -static inline struct brw_reg -brw_vec16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec16_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return brw_reg(file, + return elk_reg(file, nr, subnr, 0, 0, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_16, - BRW_WIDTH_16, - BRW_HORIZONTAL_STRIDE_1, - BRW_SWIZZLE_XYZW, + ELK_REGISTER_TYPE_F, + ELK_VERTICAL_STRIDE_16, + ELK_WIDTH_16, + ELK_HORIZONTAL_STRIDE_1, + ELK_SWIZZLE_XYZW, WRITEMASK_XYZW); } /** Construct float[8] register */ -static inline struct brw_reg -brw_vec8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec8_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return brw_reg(file, + return elk_reg(file, nr, subnr, 0, 0, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_8, - BRW_WIDTH_8, - BRW_HORIZONTAL_STRIDE_1, - BRW_SWIZZLE_XYZW, + ELK_REGISTER_TYPE_F, + ELK_VERTICAL_STRIDE_8, + ELK_WIDTH_8, + ELK_HORIZONTAL_STRIDE_1, + ELK_SWIZZLE_XYZW, WRITEMASK_XYZW); } /** Construct float[4] register */ -static inline struct brw_reg -brw_vec4_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec4_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return brw_reg(file, + return elk_reg(file, nr, subnr, 0, 0, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_4, - BRW_WIDTH_4, - BRW_HORIZONTAL_STRIDE_1, - BRW_SWIZZLE_XYZW, + ELK_REGISTER_TYPE_F, + ELK_VERTICAL_STRIDE_4, + ELK_WIDTH_4, + ELK_HORIZONTAL_STRIDE_1, + ELK_SWIZZLE_XYZW, WRITEMASK_XYZW); } /** Construct float[2] register */ -static inline struct brw_reg -brw_vec2_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec2_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return brw_reg(file, + return elk_reg(file, nr, subnr, 0, 0, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_2, - BRW_WIDTH_2, - BRW_HORIZONTAL_STRIDE_1, - BRW_SWIZZLE_XYXY, + ELK_REGISTER_TYPE_F, + ELK_VERTICAL_STRIDE_2, + ELK_WIDTH_2, + ELK_HORIZONTAL_STRIDE_1, + ELK_SWIZZLE_XYXY, WRITEMASK_XY); } /** Construct float[1] register */ -static inline struct brw_reg -brw_vec1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec1_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return brw_reg(file, + return elk_reg(file, nr, subnr, 0, 0, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_0, - BRW_WIDTH_1, - BRW_HORIZONTAL_STRIDE_0, - BRW_SWIZZLE_XXXX, + ELK_REGISTER_TYPE_F, + ELK_VERTICAL_STRIDE_0, + ELK_WIDTH_1, + ELK_HORIZONTAL_STRIDE_0, + ELK_SWIZZLE_XXXX, WRITEMASK_X); } -static inline struct brw_reg -brw_vecn_reg(unsigned width, enum brw_reg_file file, +static inline struct elk_reg +elk_vecn_reg(unsigned width, enum elk_reg_file file, unsigned nr, unsigned subnr) { switch (width) { case 1: - return brw_vec1_reg(file, nr, subnr); + return elk_vec1_reg(file, nr, subnr); case 2: - return brw_vec2_reg(file, nr, subnr); + return elk_vec2_reg(file, nr, subnr); case 4: - return brw_vec4_reg(file, nr, subnr); + return elk_vec4_reg(file, nr, subnr); case 8: - return brw_vec8_reg(file, nr, subnr); + return elk_vec8_reg(file, nr, subnr); case 16: - return brw_vec16_reg(file, nr, subnr); + return elk_vec16_reg(file, nr, subnr); default: unreachable("Invalid register width"); } } -static inline struct brw_reg -retype(struct brw_reg reg, enum brw_reg_type type) +static inline struct elk_reg +retype(struct elk_reg reg, enum elk_reg_type type) { reg.type = type; return reg; } -static inline struct brw_reg -firsthalf(struct brw_reg reg) +static inline struct elk_reg +firsthalf(struct elk_reg reg) { return reg; } -static inline struct brw_reg -sechalf(struct brw_reg reg) +static inline struct elk_reg +sechalf(struct elk_reg reg) { if (reg.vstride) reg.nr++; return reg; } -static inline struct brw_reg -offset(struct brw_reg reg, unsigned delta) +static inline struct elk_reg +offset(struct elk_reg reg, unsigned delta) { reg.nr += delta; return reg; } -static inline struct brw_reg -byte_offset(struct brw_reg reg, unsigned bytes) +static inline struct elk_reg +byte_offset(struct elk_reg reg, unsigned bytes) { unsigned newoffset = reg.nr * REG_SIZE + reg.subnr + bytes; reg.nr = newoffset / REG_SIZE; @@ -627,389 +627,389 @@ byte_offset(struct brw_reg reg, unsigned bytes) return reg; } -static inline struct brw_reg -suboffset(struct brw_reg reg, unsigned delta) +static inline struct elk_reg +suboffset(struct elk_reg reg, unsigned delta) { return byte_offset(reg, delta * type_sz(reg.type)); } /** Construct unsigned word[16] register */ -static inline struct brw_reg -brw_uw16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_uw16_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); + return suboffset(retype(elk_vec16_reg(file, nr, 0), ELK_REGISTER_TYPE_UW), subnr); } /** Construct unsigned word[8] register */ -static inline struct brw_reg -brw_uw8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_uw8_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); + return suboffset(retype(elk_vec8_reg(file, nr, 0), ELK_REGISTER_TYPE_UW), subnr); } /** Construct unsigned word[1] register */ -static inline struct brw_reg -brw_uw1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_uw1_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); + return suboffset(retype(elk_vec1_reg(file, nr, 0), ELK_REGISTER_TYPE_UW), subnr); } -static inline struct brw_reg -brw_ud8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_ud8_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return retype(brw_vec8_reg(file, nr, subnr), BRW_REGISTER_TYPE_UD); + return retype(elk_vec8_reg(file, nr, subnr), ELK_REGISTER_TYPE_UD); } -static inline struct brw_reg -brw_ud1_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_ud1_reg(enum elk_reg_file file, unsigned nr, unsigned subnr) { - return retype(brw_vec1_reg(file, nr, subnr), BRW_REGISTER_TYPE_UD); + return retype(elk_vec1_reg(file, nr, subnr), ELK_REGISTER_TYPE_UD); } -static inline struct brw_reg -brw_imm_reg(enum brw_reg_type type) +static inline struct elk_reg +elk_imm_reg(enum elk_reg_type type) { - return brw_reg(BRW_IMMEDIATE_VALUE, + return elk_reg(ELK_IMMEDIATE_VALUE, 0, 0, 0, 0, type, - BRW_VERTICAL_STRIDE_0, - BRW_WIDTH_1, - BRW_HORIZONTAL_STRIDE_0, + ELK_VERTICAL_STRIDE_0, + ELK_WIDTH_1, + ELK_HORIZONTAL_STRIDE_0, 0, 0); } /** Construct float immediate register */ -static inline struct brw_reg -brw_imm_df(double df) +static inline struct elk_reg +elk_imm_df(double df) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_DF); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_DF); imm.df = df; return imm; } -static inline struct brw_reg -brw_imm_u64(uint64_t u64) +static inline struct elk_reg +elk_imm_u64(uint64_t u64) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_UQ); imm.u64 = u64; return imm; } -static inline struct brw_reg -brw_imm_f(float f) +static inline struct elk_reg +elk_imm_f(float f) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_F); imm.f = f; return imm; } /** Construct int64_t immediate register */ -static inline struct brw_reg -brw_imm_q(int64_t q) +static inline struct elk_reg +elk_imm_q(int64_t q) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_Q); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_Q); imm.d64 = q; return imm; } /** Construct int64_t immediate register */ -static inline struct brw_reg -brw_imm_uq(uint64_t uq) +static inline struct elk_reg +elk_imm_uq(uint64_t uq) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_UQ); imm.u64 = uq; return imm; } /** Construct integer immediate register */ -static inline struct brw_reg -brw_imm_d(int d) +static inline struct elk_reg +elk_imm_d(int d) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_D); imm.d = d; return imm; } /** Construct uint immediate register */ -static inline struct brw_reg -brw_imm_ud(unsigned ud) +static inline struct elk_reg +elk_imm_ud(unsigned ud) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_UD); imm.ud = ud; return imm; } /** Construct ushort immediate register */ -static inline struct brw_reg -brw_imm_uw(uint16_t uw) +static inline struct elk_reg +elk_imm_uw(uint16_t uw) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_UW); imm.ud = uw | (uw << 16); return imm; } /** Construct short immediate register */ -static inline struct brw_reg -brw_imm_w(int16_t w) +static inline struct elk_reg +elk_imm_w(int16_t w) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_W); imm.ud = (uint16_t)w | (uint32_t)(uint16_t)w << 16; return imm; } -/* brw_imm_b and brw_imm_ub aren't supported by hardware - the type +/* elk_imm_b and elk_imm_ub aren't supported by hardware - the type * numbers alias with _V and _VF below: */ /** Construct vector of eight signed half-byte values */ -static inline struct brw_reg -brw_imm_v(unsigned v) +static inline struct elk_reg +elk_imm_v(unsigned v) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_V); imm.ud = v; return imm; } /** Construct vector of eight unsigned half-byte values */ -static inline struct brw_reg -brw_imm_uv(unsigned uv) +static inline struct elk_reg +elk_imm_uv(unsigned uv) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UV); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_UV); imm.ud = uv; return imm; } /** Construct vector of four 8-bit float values */ -static inline struct brw_reg -brw_imm_vf(unsigned v) +static inline struct elk_reg +elk_imm_vf(unsigned v) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_VF); imm.ud = v; return imm; } -static inline struct brw_reg -brw_imm_vf4(unsigned v0, unsigned v1, unsigned v2, unsigned v3) +static inline struct elk_reg +elk_imm_vf4(unsigned v0, unsigned v1, unsigned v2, unsigned v3) { - struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); - imm.vstride = BRW_VERTICAL_STRIDE_0; - imm.width = BRW_WIDTH_4; - imm.hstride = BRW_HORIZONTAL_STRIDE_1; + struct elk_reg imm = elk_imm_reg(ELK_REGISTER_TYPE_VF); + imm.vstride = ELK_VERTICAL_STRIDE_0; + imm.width = ELK_WIDTH_4; + imm.hstride = ELK_HORIZONTAL_STRIDE_1; imm.ud = ((v0 << 0) | (v1 << 8) | (v2 << 16) | (v3 << 24)); return imm; } -static inline struct brw_reg -brw_address(struct brw_reg reg) +static inline struct elk_reg +elk_address(struct elk_reg reg) { - return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr); + return elk_imm_uw(reg.nr * REG_SIZE + reg.subnr); } /** Construct float[1] general-purpose register */ -static inline struct brw_reg -brw_vec1_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec1_grf(unsigned nr, unsigned subnr) { - return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_vec1_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg +static inline struct elk_reg xe2_vec1_grf(unsigned nr, unsigned subnr) { - return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return elk_vec1_reg(ELK_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); } /** Construct float[2] general-purpose register */ -static inline struct brw_reg -brw_vec2_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec2_grf(unsigned nr, unsigned subnr) { - return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_vec2_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg +static inline struct elk_reg xe2_vec2_grf(unsigned nr, unsigned subnr) { - return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return elk_vec2_reg(ELK_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); } /** Construct float[4] general-purpose register */ -static inline struct brw_reg -brw_vec4_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec4_grf(unsigned nr, unsigned subnr) { - return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_vec4_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg +static inline struct elk_reg xe2_vec4_grf(unsigned nr, unsigned subnr) { - return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return elk_vec4_reg(ELK_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); } /** Construct float[8] general-purpose register */ -static inline struct brw_reg -brw_vec8_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec8_grf(unsigned nr, unsigned subnr) { - return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_vec8_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg +static inline struct elk_reg xe2_vec8_grf(unsigned nr, unsigned subnr) { - return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return elk_vec8_reg(ELK_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); } /** Construct float[16] general-purpose register */ -static inline struct brw_reg -brw_vec16_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vec16_grf(unsigned nr, unsigned subnr) { - return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_vec16_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg +static inline struct elk_reg xe2_vec16_grf(unsigned nr, unsigned subnr) { - return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); + return elk_vec16_reg(ELK_GENERAL_REGISTER_FILE, 2 * nr + subnr / 8, subnr % 8); } -static inline struct brw_reg -brw_vecn_grf(unsigned width, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_vecn_grf(unsigned width, unsigned nr, unsigned subnr) { - return brw_vecn_reg(width, BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_vecn_reg(width, ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg +static inline struct elk_reg xe2_vecn_grf(unsigned width, unsigned nr, unsigned subnr) { - return brw_vecn_reg(width, BRW_GENERAL_REGISTER_FILE, nr + subnr / 8, subnr % 8); + return elk_vecn_reg(width, ELK_GENERAL_REGISTER_FILE, nr + subnr / 8, subnr % 8); } -static inline struct brw_reg -brw_uw1_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_uw1_grf(unsigned nr, unsigned subnr) { - return brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_uw1_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg -brw_uw8_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_uw8_grf(unsigned nr, unsigned subnr) { - return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_uw8_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg -brw_uw16_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_uw16_grf(unsigned nr, unsigned subnr) { - return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_uw16_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg -brw_ud8_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_ud8_grf(unsigned nr, unsigned subnr) { - return brw_ud8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_ud8_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } -static inline struct brw_reg -brw_ud1_grf(unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_ud1_grf(unsigned nr, unsigned subnr) { - return brw_ud1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); + return elk_ud1_reg(ELK_GENERAL_REGISTER_FILE, nr, subnr); } /** Construct null register (usually used for setting condition codes) */ -static inline struct brw_reg -brw_null_reg(void) +static inline struct elk_reg +elk_null_reg(void) { - return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0); + return elk_vec8_reg(ELK_ARCHITECTURE_REGISTER_FILE, ELK_ARF_NULL, 0); } -static inline struct brw_reg -brw_null_vec(unsigned width) +static inline struct elk_reg +elk_null_vec(unsigned width) { - return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0); + return elk_vecn_reg(width, ELK_ARCHITECTURE_REGISTER_FILE, ELK_ARF_NULL, 0); } -static inline struct brw_reg -brw_address_reg(unsigned subnr) +static inline struct elk_reg +elk_address_reg(unsigned subnr) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr); + return elk_uw1_reg(ELK_ARCHITECTURE_REGISTER_FILE, ELK_ARF_ADDRESS, subnr); } -static inline struct brw_reg -brw_tdr_reg(void) +static inline struct elk_reg +elk_tdr_reg(void) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_TDR, 0); + return elk_uw1_reg(ELK_ARCHITECTURE_REGISTER_FILE, ELK_ARF_TDR, 0); } /* If/else instructions break in align16 mode if writemask & swizzle * aren't xyzw. This goes against the convention for other scalar * regs: */ -static inline struct brw_reg -brw_ip_reg(void) +static inline struct elk_reg +elk_ip_reg(void) { - return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_IP, + return elk_reg(ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_IP, 0, 0, 0, - BRW_REGISTER_TYPE_UD, - BRW_VERTICAL_STRIDE_4, /* ? */ - BRW_WIDTH_1, - BRW_HORIZONTAL_STRIDE_0, - BRW_SWIZZLE_XYZW, /* NOTE! */ + ELK_REGISTER_TYPE_UD, + ELK_VERTICAL_STRIDE_4, /* ? */ + ELK_WIDTH_1, + ELK_HORIZONTAL_STRIDE_0, + ELK_SWIZZLE_XYZW, /* NOTE! */ WRITEMASK_XYZW); /* NOTE! */ } -static inline struct brw_reg -brw_notification_reg(void) +static inline struct elk_reg +elk_notification_reg(void) { - return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_NOTIFICATION_COUNT, + return elk_reg(ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_NOTIFICATION_COUNT, 0, 0, 0, - BRW_REGISTER_TYPE_UD, - BRW_VERTICAL_STRIDE_0, - BRW_WIDTH_1, - BRW_HORIZONTAL_STRIDE_0, - BRW_SWIZZLE_XXXX, + ELK_REGISTER_TYPE_UD, + ELK_VERTICAL_STRIDE_0, + ELK_WIDTH_1, + ELK_HORIZONTAL_STRIDE_0, + ELK_SWIZZLE_XXXX, WRITEMASK_X); } -static inline struct brw_reg -brw_cr0_reg(unsigned subnr) +static inline struct elk_reg +elk_cr0_reg(unsigned subnr) { - return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_CONTROL, subnr); + return elk_ud1_reg(ELK_ARCHITECTURE_REGISTER_FILE, ELK_ARF_CONTROL, subnr); } -static inline struct brw_reg -brw_sr0_reg(unsigned subnr) +static inline struct elk_reg +elk_sr0_reg(unsigned subnr) { - return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_STATE, subnr); + return elk_ud1_reg(ELK_ARCHITECTURE_REGISTER_FILE, ELK_ARF_STATE, subnr); } -static inline struct brw_reg -brw_acc_reg(unsigned width) +static inline struct elk_reg +elk_acc_reg(unsigned width) { - return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_ACCUMULATOR, 0); + return elk_vecn_reg(width, ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_ACCUMULATOR, 0); } -static inline struct brw_reg -brw_flag_reg(int reg, int subreg) +static inline struct elk_reg +elk_flag_reg(int reg, int subreg) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_FLAG + reg, subreg); + return elk_uw1_reg(ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_FLAG + reg, subreg); } -static inline struct brw_reg -brw_flag_subreg(unsigned subreg) +static inline struct elk_reg +elk_flag_subreg(unsigned subreg) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_FLAG + subreg / 2, subreg % 2); + return elk_uw1_reg(ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_FLAG + subreg / 2, subreg % 2); } /** @@ -1017,50 +1017,50 @@ brw_flag_subreg(unsigned subreg) * in Gfx7.5 and later hardware referred to as "channel enable" register in * the documentation. */ -static inline struct brw_reg -brw_mask_reg(unsigned subnr) +static inline struct elk_reg +elk_mask_reg(unsigned subnr) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr); + return elk_uw1_reg(ELK_ARCHITECTURE_REGISTER_FILE, ELK_ARF_MASK, subnr); } -static inline struct brw_reg -brw_vmask_reg() +static inline struct elk_reg +elk_vmask_reg() { - return brw_sr0_reg(3); + return elk_sr0_reg(3); } -static inline struct brw_reg -brw_dmask_reg() +static inline struct elk_reg +elk_dmask_reg() { - return brw_sr0_reg(2); + return elk_sr0_reg(2); } -static inline struct brw_reg -brw_mask_stack_reg(unsigned subnr) +static inline struct elk_reg +elk_mask_stack_reg(unsigned subnr) { - return suboffset(retype(brw_vec16_reg(BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_MASK_STACK, 0), - BRW_REGISTER_TYPE_UB), subnr); + return suboffset(retype(elk_vec16_reg(ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_MASK_STACK, 0), + ELK_REGISTER_TYPE_UB), subnr); } -static inline struct brw_reg -brw_mask_stack_depth_reg(unsigned subnr) +static inline struct elk_reg +elk_mask_stack_depth_reg(unsigned subnr) { - return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_MASK_STACK_DEPTH, subnr); + return elk_uw1_reg(ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_MASK_STACK_DEPTH, subnr); } -static inline struct brw_reg -brw_message_reg(unsigned nr) +static inline struct elk_reg +elk_message_reg(unsigned nr) { - return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, nr, 0); + return elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, nr, 0); } -static inline struct brw_reg -brw_uvec_mrf(unsigned width, unsigned nr, unsigned subnr) +static inline struct elk_reg +elk_uvec_mrf(unsigned width, unsigned nr, unsigned subnr) { - return retype(brw_vecn_reg(width, BRW_MESSAGE_REGISTER_FILE, nr, subnr), - BRW_REGISTER_TYPE_UD); + return retype(elk_vecn_reg(width, ELK_MESSAGE_REGISTER_FILE, nr, subnr), + ELK_REGISTER_TYPE_UD); } /* This is almost always called with a numeric constant argument, so @@ -1080,8 +1080,8 @@ static inline unsigned cvt(unsigned val) return 0; } -static inline struct brw_reg -stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride) +static inline struct elk_reg +stride(struct elk_reg reg, unsigned vstride, unsigned width, unsigned hstride) { reg.vstride = cvt(vstride); reg.width = cvt(width) - 1; @@ -1093,8 +1093,8 @@ stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride) * Multiply the vertical and horizontal stride of a register by the given * factor \a s. */ -static inline struct brw_reg -spread(struct brw_reg reg, unsigned s) +static inline struct elk_reg +spread(struct elk_reg reg, unsigned s) { if (s) { assert(util_is_power_of_two_nonzero(s)); @@ -1115,8 +1115,8 @@ spread(struct brw_reg reg, unsigned s) * Reinterpret each channel of register \p reg as a vector of values of the * given smaller type and take the i-th subcomponent from each. */ -static inline struct brw_reg -subscript(struct brw_reg reg, enum brw_reg_type type, unsigned i) +static inline struct elk_reg +subscript(struct elk_reg reg, enum elk_reg_type type, unsigned i) { unsigned scale = type_sz(reg.type) / type_sz(type); assert(scale >= 1 && i < scale); @@ -1133,104 +1133,104 @@ subscript(struct brw_reg reg, enum brw_reg_type type, unsigned i) return suboffset(retype(spread(reg, scale), type), i); } -static inline struct brw_reg -vec16(struct brw_reg reg) +static inline struct elk_reg +vec16(struct elk_reg reg) { return stride(reg, 16,16,1); } -static inline struct brw_reg -vec8(struct brw_reg reg) +static inline struct elk_reg +vec8(struct elk_reg reg) { return stride(reg, 8,8,1); } -static inline struct brw_reg -vec4(struct brw_reg reg) +static inline struct elk_reg +vec4(struct elk_reg reg) { return stride(reg, 4,4,1); } -static inline struct brw_reg -vec2(struct brw_reg reg) +static inline struct elk_reg +vec2(struct elk_reg reg) { return stride(reg, 2,2,1); } -static inline struct brw_reg -vec1(struct brw_reg reg) +static inline struct elk_reg +vec1(struct elk_reg reg) { return stride(reg, 0,1,0); } -static inline struct brw_reg -get_element(struct brw_reg reg, unsigned elt) +static inline struct elk_reg +get_element(struct elk_reg reg, unsigned elt) { return vec1(suboffset(reg, elt)); } -static inline struct brw_reg -get_element_ud(struct brw_reg reg, unsigned elt) +static inline struct elk_reg +get_element_ud(struct elk_reg reg, unsigned elt) { - return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt)); + return vec1(suboffset(retype(reg, ELK_REGISTER_TYPE_UD), elt)); } -static inline struct brw_reg -get_element_d(struct brw_reg reg, unsigned elt) +static inline struct elk_reg +get_element_d(struct elk_reg reg, unsigned elt) { - return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_D), elt)); + return vec1(suboffset(retype(reg, ELK_REGISTER_TYPE_D), elt)); } -static inline struct brw_reg -brw_swizzle(struct brw_reg reg, unsigned swz) +static inline struct elk_reg +elk_swizzle(struct elk_reg reg, unsigned swz) { - if (reg.file == BRW_IMMEDIATE_VALUE) - reg.ud = brw_swizzle_immediate(reg.type, reg.ud, swz); + if (reg.file == ELK_IMMEDIATE_VALUE) + reg.ud = elk_swizzle_immediate(reg.type, reg.ud, swz); else - reg.swizzle = brw_compose_swizzle(swz, reg.swizzle); + reg.swizzle = elk_compose_swizzle(swz, reg.swizzle); return reg; } -static inline struct brw_reg -brw_writemask(struct brw_reg reg, unsigned mask) +static inline struct elk_reg +elk_writemask(struct elk_reg reg, unsigned mask) { - assert(reg.file != BRW_IMMEDIATE_VALUE); + assert(reg.file != ELK_IMMEDIATE_VALUE); reg.writemask &= mask; return reg; } -static inline struct brw_reg -brw_set_writemask(struct brw_reg reg, unsigned mask) +static inline struct elk_reg +elk_set_writemask(struct elk_reg reg, unsigned mask) { - assert(reg.file != BRW_IMMEDIATE_VALUE); + assert(reg.file != ELK_IMMEDIATE_VALUE); reg.writemask = mask; return reg; } static inline unsigned -brw_writemask_for_size(unsigned n) +elk_writemask_for_size(unsigned n) { return (1 << n) - 1; } static inline unsigned -brw_writemask_for_component_packing(unsigned n, unsigned first_component) +elk_writemask_for_component_packing(unsigned n, unsigned first_component) { assert(first_component + n <= 4); return (((1 << n) - 1) << first_component); } -static inline struct brw_reg -negate(struct brw_reg reg) +static inline struct elk_reg +negate(struct elk_reg reg) { reg.negate ^= 1; return reg; } -static inline struct brw_reg -brw_abs(struct brw_reg reg) +static inline struct elk_reg +elk_abs(struct elk_reg reg) { reg.abs = 1; reg.negate = 0; @@ -1239,90 +1239,90 @@ brw_abs(struct brw_reg reg) /************************************************************************/ -static inline struct brw_reg -brw_vec4_indirect(unsigned subnr, int offset) +static inline struct elk_reg +elk_vec4_indirect(unsigned subnr, int offset) { - struct brw_reg reg = brw_vec4_grf(0, 0); + struct elk_reg reg = elk_vec4_grf(0, 0); reg.subnr = subnr; - reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + reg.address_mode = ELK_ADDRESS_REGISTER_INDIRECT_REGISTER; reg.indirect_offset = offset; return reg; } -static inline struct brw_reg -brw_vec1_indirect(unsigned subnr, int offset) +static inline struct elk_reg +elk_vec1_indirect(unsigned subnr, int offset) { - struct brw_reg reg = brw_vec1_grf(0, 0); + struct elk_reg reg = elk_vec1_grf(0, 0); reg.subnr = subnr; - reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + reg.address_mode = ELK_ADDRESS_REGISTER_INDIRECT_REGISTER; reg.indirect_offset = offset; return reg; } -static inline struct brw_reg -brw_VxH_indirect(unsigned subnr, int offset) +static inline struct elk_reg +elk_VxH_indirect(unsigned subnr, int offset) { - struct brw_reg reg = brw_vec1_grf(0, 0); - reg.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL; + struct elk_reg reg = elk_vec1_grf(0, 0); + reg.vstride = ELK_VERTICAL_STRIDE_ONE_DIMENSIONAL; reg.subnr = subnr; - reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + reg.address_mode = ELK_ADDRESS_REGISTER_INDIRECT_REGISTER; reg.indirect_offset = offset; return reg; } -static inline struct brw_reg -deref_4f(struct brw_indirect ptr, int offset) +static inline struct elk_reg +deref_4f(struct elk_indirect ptr, int offset) { - return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset); + return elk_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset); } -static inline struct brw_reg -deref_1f(struct brw_indirect ptr, int offset) +static inline struct elk_reg +deref_1f(struct elk_indirect ptr, int offset) { - return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset); + return elk_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset); } -static inline struct brw_reg -deref_4b(struct brw_indirect ptr, int offset) +static inline struct elk_reg +deref_4b(struct elk_indirect ptr, int offset) { - return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B); + return retype(deref_4f(ptr, offset), ELK_REGISTER_TYPE_B); } -static inline struct brw_reg -deref_1uw(struct brw_indirect ptr, int offset) +static inline struct elk_reg +deref_1uw(struct elk_indirect ptr, int offset) { - return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW); + return retype(deref_1f(ptr, offset), ELK_REGISTER_TYPE_UW); } -static inline struct brw_reg -deref_1d(struct brw_indirect ptr, int offset) +static inline struct elk_reg +deref_1d(struct elk_indirect ptr, int offset) { - return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D); + return retype(deref_1f(ptr, offset), ELK_REGISTER_TYPE_D); } -static inline struct brw_reg -deref_1ud(struct brw_indirect ptr, int offset) +static inline struct elk_reg +deref_1ud(struct elk_indirect ptr, int offset) { - return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD); + return retype(deref_1f(ptr, offset), ELK_REGISTER_TYPE_UD); } -static inline struct brw_reg -get_addr_reg(struct brw_indirect ptr) +static inline struct elk_reg +get_addr_reg(struct elk_indirect ptr) { - return brw_address_reg(ptr.addr_subnr); + return elk_address_reg(ptr.addr_subnr); } -static inline struct brw_indirect -brw_indirect_offset(struct brw_indirect ptr, int offset) +static inline struct elk_indirect +elk_indirect_offset(struct elk_indirect ptr, int offset) { ptr.addr_offset += offset; return ptr; } -static inline struct brw_indirect -brw_indirect(unsigned addr_subnr, int offset) +static inline struct elk_indirect +elk_indirect(unsigned addr_subnr, int offset) { - struct brw_indirect ptr; + struct elk_indirect ptr; ptr.addr_subnr = addr_subnr; ptr.addr_offset = offset; ptr.pad = 0; @@ -1330,8 +1330,8 @@ brw_indirect(unsigned addr_subnr, int offset) } static inline bool -region_matches(struct brw_reg reg, enum brw_vertical_stride v, - enum brw_width w, enum brw_horizontal_stride h) +region_matches(struct elk_reg reg, enum elk_vertical_stride v, + enum elk_width w, enum elk_horizontal_stride h) { return reg.vstride == v && reg.width == w && @@ -1339,34 +1339,34 @@ region_matches(struct brw_reg reg, enum brw_vertical_stride v, } #define has_scalar_region(reg) \ - region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \ - BRW_HORIZONTAL_STRIDE_0) + region_matches(reg, ELK_VERTICAL_STRIDE_0, ELK_WIDTH_1, \ + ELK_HORIZONTAL_STRIDE_0) /** * Return the size in bytes per data element of register \p reg on the * corresponding register file. */ static inline unsigned -element_sz(struct brw_reg reg) +element_sz(struct elk_reg reg) { - if (reg.file == BRW_IMMEDIATE_VALUE || has_scalar_region(reg)) { + if (reg.file == ELK_IMMEDIATE_VALUE || has_scalar_region(reg)) { return type_sz(reg.type); - } else if (reg.width == BRW_WIDTH_1 && - reg.hstride == BRW_HORIZONTAL_STRIDE_0) { - assert(reg.vstride != BRW_VERTICAL_STRIDE_0); + } else if (reg.width == ELK_WIDTH_1 && + reg.hstride == ELK_HORIZONTAL_STRIDE_0) { + assert(reg.vstride != ELK_VERTICAL_STRIDE_0); return type_sz(reg.type) << (reg.vstride - 1); } else { - assert(reg.hstride != BRW_HORIZONTAL_STRIDE_0); + assert(reg.hstride != ELK_HORIZONTAL_STRIDE_0); assert(reg.vstride == reg.hstride + reg.width); return type_sz(reg.type) << (reg.hstride - 1); } } -/* brw_packed_float.c */ -int brw_float_to_vf(float f); -float brw_vf_to_float(unsigned char vf); +/* elk_packed_float.c */ +int elk_float_to_vf(float f); +float elk_vf_to_float(unsigned char vf); #ifdef __cplusplus } diff --git a/src/intel/compiler/elk/elk_reg_type.c b/src/intel/compiler/elk/elk_reg_type.c index d2433ed7432..c8d09dd3320 100644 --- a/src/intel/compiler/elk/elk_reg_type.c +++ b/src/intel/compiler/elk/elk_reg_type.c @@ -28,16 +28,16 @@ #define INVALID (-1) enum hw_reg_type { - BRW_HW_REG_TYPE_UD = 0, - BRW_HW_REG_TYPE_D = 1, - BRW_HW_REG_TYPE_UW = 2, - BRW_HW_REG_TYPE_W = 3, - BRW_HW_REG_TYPE_F = 7, + ELK_HW_REG_TYPE_UD = 0, + ELK_HW_REG_TYPE_D = 1, + ELK_HW_REG_TYPE_UW = 2, + ELK_HW_REG_TYPE_W = 3, + ELK_HW_REG_TYPE_F = 7, GFX8_HW_REG_TYPE_UQ = 8, GFX8_HW_REG_TYPE_Q = 9, - BRW_HW_REG_TYPE_UB = 4, - BRW_HW_REG_TYPE_B = 5, + ELK_HW_REG_TYPE_UB = 4, + ELK_HW_REG_TYPE_B = 5, GFX7_HW_REG_TYPE_DF = 6, GFX8_HW_REG_TYPE_HF = 10, @@ -56,17 +56,17 @@ enum hw_reg_type { }; enum hw_imm_type { - BRW_HW_IMM_TYPE_UD = 0, - BRW_HW_IMM_TYPE_D = 1, - BRW_HW_IMM_TYPE_UW = 2, - BRW_HW_IMM_TYPE_W = 3, - BRW_HW_IMM_TYPE_F = 7, + ELK_HW_IMM_TYPE_UD = 0, + ELK_HW_IMM_TYPE_D = 1, + ELK_HW_IMM_TYPE_UW = 2, + ELK_HW_IMM_TYPE_W = 3, + ELK_HW_IMM_TYPE_F = 7, GFX8_HW_IMM_TYPE_UQ = 8, GFX8_HW_IMM_TYPE_Q = 9, - BRW_HW_IMM_TYPE_UV = 4, - BRW_HW_IMM_TYPE_VF = 5, - BRW_HW_IMM_TYPE_V = 6, + ELK_HW_IMM_TYPE_UV = 4, + ELK_HW_IMM_TYPE_VF = 5, + ELK_HW_IMM_TYPE_V = 6, GFX8_HW_IMM_TYPE_DF = 10, GFX8_HW_IMM_TYPE_HF = 11, @@ -92,120 +92,120 @@ static const struct hw_type { enum hw_reg_type reg_type; enum hw_imm_type imm_type; } gfx4_hw_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID }, - [BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F }, - [BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF }, + [ELK_REGISTER_TYPE_F] = { ELK_HW_REG_TYPE_F, ELK_HW_IMM_TYPE_F }, + [ELK_REGISTER_TYPE_VF] = { INVALID, ELK_HW_IMM_TYPE_VF }, - [BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D }, - [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, - [BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W }, - [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW }, - [BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID }, - [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID }, - [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V }, + [ELK_REGISTER_TYPE_D] = { ELK_HW_REG_TYPE_D, ELK_HW_IMM_TYPE_D }, + [ELK_REGISTER_TYPE_UD] = { ELK_HW_REG_TYPE_UD, ELK_HW_IMM_TYPE_UD }, + [ELK_REGISTER_TYPE_W] = { ELK_HW_REG_TYPE_W, ELK_HW_IMM_TYPE_W }, + [ELK_REGISTER_TYPE_UW] = { ELK_HW_REG_TYPE_UW, ELK_HW_IMM_TYPE_UW }, + [ELK_REGISTER_TYPE_B] = { ELK_HW_REG_TYPE_B, INVALID }, + [ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID }, + [ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V }, }, gfx6_hw_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID }, - [BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F }, - [BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF }, + [ELK_REGISTER_TYPE_F] = { ELK_HW_REG_TYPE_F, ELK_HW_IMM_TYPE_F }, + [ELK_REGISTER_TYPE_VF] = { INVALID, ELK_HW_IMM_TYPE_VF }, - [BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D }, - [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, - [BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W }, - [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW }, - [BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID }, - [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID }, - [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V }, - [BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV }, + [ELK_REGISTER_TYPE_D] = { ELK_HW_REG_TYPE_D, ELK_HW_IMM_TYPE_D }, + [ELK_REGISTER_TYPE_UD] = { ELK_HW_REG_TYPE_UD, ELK_HW_IMM_TYPE_UD }, + [ELK_REGISTER_TYPE_W] = { ELK_HW_REG_TYPE_W, ELK_HW_IMM_TYPE_W }, + [ELK_REGISTER_TYPE_UW] = { ELK_HW_REG_TYPE_UW, ELK_HW_IMM_TYPE_UW }, + [ELK_REGISTER_TYPE_B] = { ELK_HW_REG_TYPE_B, INVALID }, + [ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID }, + [ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V }, + [ELK_REGISTER_TYPE_UV] = { INVALID, ELK_HW_IMM_TYPE_UV }, }, gfx7_hw_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID }, - [BRW_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, INVALID }, - [BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F }, - [BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF }, + [ELK_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, INVALID }, + [ELK_REGISTER_TYPE_F] = { ELK_HW_REG_TYPE_F, ELK_HW_IMM_TYPE_F }, + [ELK_REGISTER_TYPE_VF] = { INVALID, ELK_HW_IMM_TYPE_VF }, - [BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D }, - [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, - [BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W }, - [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW }, - [BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID }, - [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID }, - [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V }, - [BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV }, + [ELK_REGISTER_TYPE_D] = { ELK_HW_REG_TYPE_D, ELK_HW_IMM_TYPE_D }, + [ELK_REGISTER_TYPE_UD] = { ELK_HW_REG_TYPE_UD, ELK_HW_IMM_TYPE_UD }, + [ELK_REGISTER_TYPE_W] = { ELK_HW_REG_TYPE_W, ELK_HW_IMM_TYPE_W }, + [ELK_REGISTER_TYPE_UW] = { ELK_HW_REG_TYPE_UW, ELK_HW_IMM_TYPE_UW }, + [ELK_REGISTER_TYPE_B] = { ELK_HW_REG_TYPE_B, INVALID }, + [ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID }, + [ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V }, + [ELK_REGISTER_TYPE_UV] = { INVALID, ELK_HW_IMM_TYPE_UV }, }, gfx8_hw_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID }, - [BRW_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, GFX8_HW_IMM_TYPE_DF }, - [BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F }, - [BRW_REGISTER_TYPE_HF] = { GFX8_HW_REG_TYPE_HF, GFX8_HW_IMM_TYPE_HF }, - [BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF }, + [ELK_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, GFX8_HW_IMM_TYPE_DF }, + [ELK_REGISTER_TYPE_F] = { ELK_HW_REG_TYPE_F, ELK_HW_IMM_TYPE_F }, + [ELK_REGISTER_TYPE_HF] = { GFX8_HW_REG_TYPE_HF, GFX8_HW_IMM_TYPE_HF }, + [ELK_REGISTER_TYPE_VF] = { INVALID, ELK_HW_IMM_TYPE_VF }, - [BRW_REGISTER_TYPE_Q] = { GFX8_HW_REG_TYPE_Q, GFX8_HW_IMM_TYPE_Q }, - [BRW_REGISTER_TYPE_UQ] = { GFX8_HW_REG_TYPE_UQ, GFX8_HW_IMM_TYPE_UQ }, - [BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D }, - [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, - [BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W }, - [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW }, - [BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID }, - [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID }, - [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V }, - [BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV }, + [ELK_REGISTER_TYPE_Q] = { GFX8_HW_REG_TYPE_Q, GFX8_HW_IMM_TYPE_Q }, + [ELK_REGISTER_TYPE_UQ] = { GFX8_HW_REG_TYPE_UQ, GFX8_HW_IMM_TYPE_UQ }, + [ELK_REGISTER_TYPE_D] = { ELK_HW_REG_TYPE_D, ELK_HW_IMM_TYPE_D }, + [ELK_REGISTER_TYPE_UD] = { ELK_HW_REG_TYPE_UD, ELK_HW_IMM_TYPE_UD }, + [ELK_REGISTER_TYPE_W] = { ELK_HW_REG_TYPE_W, ELK_HW_IMM_TYPE_W }, + [ELK_REGISTER_TYPE_UW] = { ELK_HW_REG_TYPE_UW, ELK_HW_IMM_TYPE_UW }, + [ELK_REGISTER_TYPE_B] = { ELK_HW_REG_TYPE_B, INVALID }, + [ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID }, + [ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V }, + [ELK_REGISTER_TYPE_UV] = { INVALID, ELK_HW_IMM_TYPE_UV }, }, gfx11_hw_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID }, - [BRW_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID }, - [BRW_REGISTER_TYPE_F] = { GFX11_HW_REG_TYPE_F, GFX11_HW_IMM_TYPE_F }, - [BRW_REGISTER_TYPE_HF] = { GFX11_HW_REG_TYPE_HF, GFX11_HW_IMM_TYPE_HF }, - [BRW_REGISTER_TYPE_VF] = { INVALID, GFX11_HW_IMM_TYPE_VF }, + [ELK_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID }, + [ELK_REGISTER_TYPE_F] = { GFX11_HW_REG_TYPE_F, GFX11_HW_IMM_TYPE_F }, + [ELK_REGISTER_TYPE_HF] = { GFX11_HW_REG_TYPE_HF, GFX11_HW_IMM_TYPE_HF }, + [ELK_REGISTER_TYPE_VF] = { INVALID, GFX11_HW_IMM_TYPE_VF }, - [BRW_REGISTER_TYPE_D] = { GFX11_HW_REG_TYPE_D, GFX11_HW_IMM_TYPE_D }, - [BRW_REGISTER_TYPE_UD] = { GFX11_HW_REG_TYPE_UD, GFX11_HW_IMM_TYPE_UD }, - [BRW_REGISTER_TYPE_W] = { GFX11_HW_REG_TYPE_W, GFX11_HW_IMM_TYPE_W }, - [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW }, - [BRW_REGISTER_TYPE_B] = { GFX11_HW_REG_TYPE_B, INVALID }, - [BRW_REGISTER_TYPE_UB] = { GFX11_HW_REG_TYPE_UB, INVALID }, - [BRW_REGISTER_TYPE_V] = { INVALID, GFX11_HW_IMM_TYPE_V }, - [BRW_REGISTER_TYPE_UV] = { INVALID, GFX11_HW_IMM_TYPE_UV }, + [ELK_REGISTER_TYPE_D] = { GFX11_HW_REG_TYPE_D, GFX11_HW_IMM_TYPE_D }, + [ELK_REGISTER_TYPE_UD] = { GFX11_HW_REG_TYPE_UD, GFX11_HW_IMM_TYPE_UD }, + [ELK_REGISTER_TYPE_W] = { GFX11_HW_REG_TYPE_W, GFX11_HW_IMM_TYPE_W }, + [ELK_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW }, + [ELK_REGISTER_TYPE_B] = { GFX11_HW_REG_TYPE_B, INVALID }, + [ELK_REGISTER_TYPE_UB] = { GFX11_HW_REG_TYPE_UB, INVALID }, + [ELK_REGISTER_TYPE_V] = { INVALID, GFX11_HW_IMM_TYPE_V }, + [ELK_REGISTER_TYPE_UV] = { INVALID, GFX11_HW_IMM_TYPE_UV }, }, gfx12_hw_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID }, - [BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) }, - [BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) }, - [BRW_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) }, + [ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) }, + [ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) }, + [ELK_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) }, - [BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) }, - [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) }, - [BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) }, - [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) }, - [BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID }, - [BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID }, - [BRW_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) }, - [BRW_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) }, + [ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) }, + [ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) }, + [ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) }, + [ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) }, + [ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID }, + [ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID }, + [ELK_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) }, + [ELK_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) }, }, gfx125_hw_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID }, - [BRW_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_FLOAT(3), GFX12_HW_REG_TYPE_FLOAT(3) }, - [BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) }, - [BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) }, - [BRW_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) }, + [ELK_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_FLOAT(3), GFX12_HW_REG_TYPE_FLOAT(3) }, + [ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) }, + [ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) }, + [ELK_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) }, - [BRW_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), GFX12_HW_REG_TYPE_SINT(3) }, - [BRW_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), GFX12_HW_REG_TYPE_UINT(3) }, - [BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) }, - [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) }, - [BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) }, - [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) }, - [BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID }, - [BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID }, - [BRW_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) }, - [BRW_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) }, + [ELK_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), GFX12_HW_REG_TYPE_SINT(3) }, + [ELK_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), GFX12_HW_REG_TYPE_UINT(3) }, + [ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) }, + [ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) }, + [ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) }, + [ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) }, + [ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID }, + [ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID }, + [ELK_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) }, + [ELK_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) }, }; /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so * the types were implied. IVB adds BFE and BFI2 that operate on doublewords * and unsigned doublewords, so a new field is also available in the da3src - * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select + * struct (part of struct elk_instruction.bits1 in elk_structs.h) to select * dst and shared-src types. * * CNL adds support for 3-src instructions in align1 mode, and with it support @@ -239,90 +239,90 @@ static const struct hw_3src_type { enum hw_3src_reg_type reg_type; enum gfx10_align1_3src_exec_type exec_type; } gfx6_hw_3src_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID }, - [BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, + [ELK_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, }, gfx7_hw_3src_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID }, - [BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, - [BRW_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D }, - [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, - [BRW_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF }, + [ELK_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, + [ELK_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D }, + [ELK_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, + [ELK_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF }, }, gfx8_hw_3src_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID }, - [BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, - [BRW_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D }, - [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, - [BRW_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF }, - [BRW_REGISTER_TYPE_HF] = { GFX8_3SRC_TYPE_HF }, + [ELK_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, + [ELK_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D }, + [ELK_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, + [ELK_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF }, + [ELK_REGISTER_TYPE_HF] = { GFX8_3SRC_TYPE_HF }, }, gfx10_hw_3src_align1_type[] = { -#define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, +#define E(x) ELK_ALIGN1_3SRC_EXEC_TYPE_##x + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID }, - [BRW_REGISTER_TYPE_DF] = { GFX10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) }, - [BRW_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) }, - [BRW_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) }, + [ELK_REGISTER_TYPE_DF] = { GFX10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) }, + [ELK_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) }, + [ELK_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) }, - [BRW_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) }, - [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, - [BRW_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) }, - [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) }, - [BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) }, - [BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) }, + [ELK_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) }, + [ELK_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, + [ELK_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) }, + [ELK_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) }, + [ELK_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) }, + [ELK_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) }, }, gfx11_hw_3src_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID }, - [BRW_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) }, - [BRW_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) }, - [BRW_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) }, + [ELK_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) }, + [ELK_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) }, + [ELK_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) }, - [BRW_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) }, - [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, - [BRW_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) }, - [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) }, - [BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) }, - [BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) }, + [ELK_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) }, + [ELK_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, + [ELK_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) }, + [ELK_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) }, + [ELK_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) }, + [ELK_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) }, }, gfx12_hw_3src_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID }, - [BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), }, - [BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), }, + [ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), }, + [ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), }, - [BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), }, - [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, - [BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), }, - [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), }, - [BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), }, - [BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), }, + [ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), }, + [ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, + [ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), }, + [ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), }, + [ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), }, + [ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), }, }, gfx125_hw_3src_type[] = { - [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, + [0 ... ELK_REGISTER_TYPE_LAST] = { INVALID }, - [BRW_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_UINT(3), E(FLOAT), }, - [BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), }, - [BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), }, + [ELK_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_UINT(3), E(FLOAT), }, + [ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), }, + [ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), }, - [BRW_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), E(INT), }, - [BRW_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), E(INT), }, - [BRW_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), }, - [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, - [BRW_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), }, - [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), }, - [BRW_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), }, - [BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), }, + [ELK_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), E(INT), }, + [ELK_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), E(INT), }, + [ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), }, + [ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, + [ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), }, + [ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), }, + [ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), }, + [ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), }, #undef E }; /** - * Convert a brw_reg_type enumeration value into the hardware representation. + * Convert a elk_reg_type enumeration value into the hardware representation. * * The hardware encoding may depend on whether the value is an immediate. */ unsigned -brw_reg_type_to_hw_type(const struct intel_device_info *devinfo, - enum brw_reg_file file, - enum brw_reg_type type) +elk_reg_type_to_hw_type(const struct intel_device_info *devinfo, + enum elk_reg_file file, + enum elk_reg_type type) { const struct hw_type *table; @@ -349,7 +349,7 @@ brw_reg_type_to_hw_type(const struct intel_device_info *devinfo, table = gfx4_hw_type; } - if (file == BRW_IMMEDIATE_VALUE) { + if (file == ELK_IMMEDIATE_VALUE) { assert(table[type].imm_type != (enum hw_imm_type)INVALID); return table[type].imm_type; } else { @@ -359,13 +359,13 @@ brw_reg_type_to_hw_type(const struct intel_device_info *devinfo, } /** - * Convert the hardware representation into a brw_reg_type enumeration value. + * Convert the hardware representation into a elk_reg_type enumeration value. * * The hardware encoding may depend on whether the value is an immediate. */ -enum brw_reg_type -brw_hw_type_to_reg_type(const struct intel_device_info *devinfo, - enum brw_reg_file file, unsigned hw_type) +enum elk_reg_type +elk_hw_type_to_reg_type(const struct intel_device_info *devinfo, + enum elk_reg_file file, unsigned hw_type) { const struct hw_type *table; @@ -385,14 +385,14 @@ brw_hw_type_to_reg_type(const struct intel_device_info *devinfo, table = gfx4_hw_type; } - if (file == BRW_IMMEDIATE_VALUE) { - for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) { + if (file == ELK_IMMEDIATE_VALUE) { + for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) { if (table[i].imm_type == (enum hw_imm_type)hw_type) { return i; } } } else { - for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) { + for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) { if (table[i].reg_type == (enum hw_reg_type)hw_type) { return i; } @@ -402,12 +402,12 @@ brw_hw_type_to_reg_type(const struct intel_device_info *devinfo, } /** - * Convert a brw_reg_type enumeration value into the hardware representation + * Convert a elk_reg_type enumeration value into the hardware representation * for a 3-src align16 instruction */ unsigned -brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo, - enum brw_reg_type type) +elk_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo, + enum elk_reg_type type) { const struct hw_3src_type *table; @@ -427,12 +427,12 @@ brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo, } /** - * Convert a brw_reg_type enumeration value into the hardware representation + * Convert a elk_reg_type enumeration value into the hardware representation * for a 3-src align1 instruction */ unsigned -brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo, - enum brw_reg_type type) +elk_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo, + enum elk_reg_type type) { if (devinfo->verx10 >= 125) { assert(type < ARRAY_SIZE(gfx125_hw_3src_type)); @@ -451,10 +451,10 @@ brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo, /** * Convert the hardware representation for a 3-src align16 instruction into a - * brw_reg_type enumeration value. + * elk_reg_type enumeration value. */ -enum brw_reg_type -brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, +enum elk_reg_type +elk_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, unsigned hw_type) { const struct hw_3src_type *table = NULL; @@ -467,7 +467,7 @@ brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, table = gfx6_hw_3src_type; } - for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) { + for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) { if (table[i].reg_type == hw_type) { return i; } @@ -477,10 +477,10 @@ brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, /** * Convert the hardware representation for a 3-src align1 instruction into a - * brw_reg_type enumeration value. + * elk_reg_type enumeration value. */ -enum brw_reg_type -brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, +enum elk_reg_type +elk_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, unsigned hw_type, unsigned exec_type) { const struct hw_3src_type *table = @@ -489,7 +489,7 @@ brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, devinfo->ver >= 11 ? gfx11_hw_3src_type : gfx10_hw_3src_align1_type); - for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) { + for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) { if (table[i].reg_type == hw_type && table[i].exec_type == exec_type) { return i; @@ -502,25 +502,25 @@ brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, * Return the element size given a register type. */ unsigned -brw_reg_type_to_size(enum brw_reg_type type) +elk_reg_type_to_size(enum elk_reg_type type) { static const unsigned type_size[] = { - [BRW_REGISTER_TYPE_NF] = 8, - [BRW_REGISTER_TYPE_DF] = 8, - [BRW_REGISTER_TYPE_F] = 4, - [BRW_REGISTER_TYPE_HF] = 2, - [BRW_REGISTER_TYPE_VF] = 4, + [ELK_REGISTER_TYPE_NF] = 8, + [ELK_REGISTER_TYPE_DF] = 8, + [ELK_REGISTER_TYPE_F] = 4, + [ELK_REGISTER_TYPE_HF] = 2, + [ELK_REGISTER_TYPE_VF] = 4, - [BRW_REGISTER_TYPE_Q] = 8, - [BRW_REGISTER_TYPE_UQ] = 8, - [BRW_REGISTER_TYPE_D] = 4, - [BRW_REGISTER_TYPE_UD] = 4, - [BRW_REGISTER_TYPE_W] = 2, - [BRW_REGISTER_TYPE_UW] = 2, - [BRW_REGISTER_TYPE_B] = 1, - [BRW_REGISTER_TYPE_UB] = 1, - [BRW_REGISTER_TYPE_V] = 2, - [BRW_REGISTER_TYPE_UV] = 2, + [ELK_REGISTER_TYPE_Q] = 8, + [ELK_REGISTER_TYPE_UQ] = 8, + [ELK_REGISTER_TYPE_D] = 4, + [ELK_REGISTER_TYPE_UD] = 4, + [ELK_REGISTER_TYPE_W] = 2, + [ELK_REGISTER_TYPE_UW] = 2, + [ELK_REGISTER_TYPE_B] = 1, + [ELK_REGISTER_TYPE_UB] = 1, + [ELK_REGISTER_TYPE_V] = 2, + [ELK_REGISTER_TYPE_UV] = 2, }; if (type >= ARRAY_SIZE(type_size)) return -1; @@ -529,31 +529,31 @@ brw_reg_type_to_size(enum brw_reg_type type) } /** - * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on). + * Converts a ELK_REGISTER_TYPE_* enum to a short string (F, UD, and so on). * - * This is different than reg_encoding from brw_disasm.c in that it operates + * This is different than reg_encoding from elk_disasm.c in that it operates * on the abstract enum values, rather than the generation-specific encoding. */ const char * -brw_reg_type_to_letters(enum brw_reg_type type) +elk_reg_type_to_letters(enum elk_reg_type type) { static const char letters[][3] = { - [BRW_REGISTER_TYPE_NF] = "NF", - [BRW_REGISTER_TYPE_DF] = "DF", - [BRW_REGISTER_TYPE_F] = "F", - [BRW_REGISTER_TYPE_HF] = "HF", - [BRW_REGISTER_TYPE_VF] = "VF", + [ELK_REGISTER_TYPE_NF] = "NF", + [ELK_REGISTER_TYPE_DF] = "DF", + [ELK_REGISTER_TYPE_F] = "F", + [ELK_REGISTER_TYPE_HF] = "HF", + [ELK_REGISTER_TYPE_VF] = "VF", - [BRW_REGISTER_TYPE_Q] = "Q", - [BRW_REGISTER_TYPE_UQ] = "UQ", - [BRW_REGISTER_TYPE_D] = "D", - [BRW_REGISTER_TYPE_UD] = "UD", - [BRW_REGISTER_TYPE_W] = "W", - [BRW_REGISTER_TYPE_UW] = "UW", - [BRW_REGISTER_TYPE_B] = "B", - [BRW_REGISTER_TYPE_UB] = "UB", - [BRW_REGISTER_TYPE_V] = "V", - [BRW_REGISTER_TYPE_UV] = "UV", + [ELK_REGISTER_TYPE_Q] = "Q", + [ELK_REGISTER_TYPE_UQ] = "UQ", + [ELK_REGISTER_TYPE_D] = "D", + [ELK_REGISTER_TYPE_UD] = "UD", + [ELK_REGISTER_TYPE_W] = "W", + [ELK_REGISTER_TYPE_UW] = "UW", + [ELK_REGISTER_TYPE_B] = "B", + [ELK_REGISTER_TYPE_UB] = "UB", + [ELK_REGISTER_TYPE_V] = "V", + [ELK_REGISTER_TYPE_UV] = "UV", }; if (type >= ARRAY_SIZE(letters)) return "INVALID"; diff --git a/src/intel/compiler/elk/elk_reg_type.h b/src/intel/compiler/elk/elk_reg_type.h index e81a530664f..dc31e856b2f 100644 --- a/src/intel/compiler/elk/elk_reg_type.h +++ b/src/intel/compiler/elk/elk_reg_type.h @@ -36,46 +36,46 @@ extern "C" { #define ATTRIBUTE_PURE #endif -enum brw_reg_file; +enum elk_reg_file; struct intel_device_info; /* * The ordering has been chosen so that no enum value is the same as a * compatible hardware encoding. */ -enum PACKED brw_reg_type { +enum PACKED elk_reg_type { /** Floating-point types: @{ */ - BRW_REGISTER_TYPE_NF, /* >64-bit (accumulator-only) native float (gfx11+) */ - BRW_REGISTER_TYPE_DF, /* 64-bit float (double float) */ - BRW_REGISTER_TYPE_F, /* 32-bit float */ - BRW_REGISTER_TYPE_HF, /* 16-bit float (half float) */ - BRW_REGISTER_TYPE_VF, /* 32-bit vector of 4 8-bit floats */ + ELK_REGISTER_TYPE_NF, /* >64-bit (accumulator-only) native float (gfx11+) */ + ELK_REGISTER_TYPE_DF, /* 64-bit float (double float) */ + ELK_REGISTER_TYPE_F, /* 32-bit float */ + ELK_REGISTER_TYPE_HF, /* 16-bit float (half float) */ + ELK_REGISTER_TYPE_VF, /* 32-bit vector of 4 8-bit floats */ /** @} */ /** Integer types: @{ */ - BRW_REGISTER_TYPE_Q, /* 64-bit signed integer (quad word) */ - BRW_REGISTER_TYPE_UQ, /* 64-bit unsigned integer (quad word) */ - BRW_REGISTER_TYPE_D, /* 32-bit signed integer (double word) */ - BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ - BRW_REGISTER_TYPE_W, /* 16-bit signed integer (word) */ - BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ - BRW_REGISTER_TYPE_B, /* 8-bit signed integer (byte) */ - BRW_REGISTER_TYPE_UB, /* 8-bit unsigned integer (byte) */ - BRW_REGISTER_TYPE_V, /* vector of 8 signed 4-bit integers (treated as W) */ - BRW_REGISTER_TYPE_UV, /* vector of 8 unsigned 4-bit integers (treated as UW) */ + ELK_REGISTER_TYPE_Q, /* 64-bit signed integer (quad word) */ + ELK_REGISTER_TYPE_UQ, /* 64-bit unsigned integer (quad word) */ + ELK_REGISTER_TYPE_D, /* 32-bit signed integer (double word) */ + ELK_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ + ELK_REGISTER_TYPE_W, /* 16-bit signed integer (word) */ + ELK_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ + ELK_REGISTER_TYPE_B, /* 8-bit signed integer (byte) */ + ELK_REGISTER_TYPE_UB, /* 8-bit unsigned integer (byte) */ + ELK_REGISTER_TYPE_V, /* vector of 8 signed 4-bit integers (treated as W) */ + ELK_REGISTER_TYPE_UV, /* vector of 8 unsigned 4-bit integers (treated as UW) */ /** @} */ - BRW_REGISTER_TYPE_LAST = BRW_REGISTER_TYPE_UV + ELK_REGISTER_TYPE_LAST = ELK_REGISTER_TYPE_UV }; static inline bool -brw_reg_type_is_floating_point(enum brw_reg_type type) +elk_reg_type_is_floating_point(enum elk_reg_type type) { switch (type) { - case BRW_REGISTER_TYPE_NF: - case BRW_REGISTER_TYPE_DF: - case BRW_REGISTER_TYPE_F: - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_HF: return true; default: return false; @@ -83,17 +83,17 @@ brw_reg_type_is_floating_point(enum brw_reg_type type) } static inline bool -brw_reg_type_is_integer(enum brw_reg_type type) +elk_reg_type_is_integer(enum elk_reg_type type) { switch (type) { - case BRW_REGISTER_TYPE_Q: - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: return true; default: return false; @@ -101,65 +101,65 @@ brw_reg_type_is_integer(enum brw_reg_type type) } static inline bool -brw_reg_type_is_unsigned_integer(enum brw_reg_type tp) +elk_reg_type_is_unsigned_integer(enum elk_reg_type tp) { - return tp == BRW_REGISTER_TYPE_UB || - tp == BRW_REGISTER_TYPE_UW || - tp == BRW_REGISTER_TYPE_UD || - tp == BRW_REGISTER_TYPE_UQ; + return tp == ELK_REGISTER_TYPE_UB || + tp == ELK_REGISTER_TYPE_UW || + tp == ELK_REGISTER_TYPE_UD || + tp == ELK_REGISTER_TYPE_UQ; } /* * Returns a type based on a reference_type (word, float, half-float) and a * given bit_size. */ -static inline enum brw_reg_type -brw_reg_type_from_bit_size(unsigned bit_size, - enum brw_reg_type reference_type) +static inline enum elk_reg_type +elk_reg_type_from_bit_size(unsigned bit_size, + enum elk_reg_type reference_type) { switch(reference_type) { - case BRW_REGISTER_TYPE_HF: - case BRW_REGISTER_TYPE_F: - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_DF: switch(bit_size) { case 16: - return BRW_REGISTER_TYPE_HF; + return ELK_REGISTER_TYPE_HF; case 32: - return BRW_REGISTER_TYPE_F; + return ELK_REGISTER_TYPE_F; case 64: - return BRW_REGISTER_TYPE_DF; + return ELK_REGISTER_TYPE_DF; default: unreachable("Invalid bit size"); } - case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_Q: switch(bit_size) { case 8: - return BRW_REGISTER_TYPE_B; + return ELK_REGISTER_TYPE_B; case 16: - return BRW_REGISTER_TYPE_W; + return ELK_REGISTER_TYPE_W; case 32: - return BRW_REGISTER_TYPE_D; + return ELK_REGISTER_TYPE_D; case 64: - return BRW_REGISTER_TYPE_Q; + return ELK_REGISTER_TYPE_Q; default: unreachable("Invalid bit size"); } - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_UQ: switch(bit_size) { case 8: - return BRW_REGISTER_TYPE_UB; + return ELK_REGISTER_TYPE_UB; case 16: - return BRW_REGISTER_TYPE_UW; + return ELK_REGISTER_TYPE_UW; case 32: - return BRW_REGISTER_TYPE_UD; + return ELK_REGISTER_TYPE_UD; case 64: - return BRW_REGISTER_TYPE_UQ; + return ELK_REGISTER_TYPE_UQ; default: unreachable("Invalid bit size"); } @@ -169,38 +169,38 @@ brw_reg_type_from_bit_size(unsigned bit_size, } -#define INVALID_REG_TYPE ((enum brw_reg_type)-1) +#define INVALID_REG_TYPE ((enum elk_reg_type)-1) #define INVALID_HW_REG_TYPE ((unsigned)-1) unsigned -brw_reg_type_to_hw_type(const struct intel_device_info *devinfo, - enum brw_reg_file file, enum brw_reg_type type); +elk_reg_type_to_hw_type(const struct intel_device_info *devinfo, + enum elk_reg_file file, enum elk_reg_type type); -enum brw_reg_type ATTRIBUTE_PURE -brw_hw_type_to_reg_type(const struct intel_device_info *devinfo, - enum brw_reg_file file, unsigned hw_type); +enum elk_reg_type ATTRIBUTE_PURE +elk_hw_type_to_reg_type(const struct intel_device_info *devinfo, + enum elk_reg_file file, unsigned hw_type); unsigned -brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo, - enum brw_reg_type type); +elk_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo, + enum elk_reg_type type); unsigned -brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo, - enum brw_reg_type type); +elk_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo, + enum elk_reg_type type); -enum brw_reg_type -brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, +enum elk_reg_type +elk_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, unsigned hw_type); -enum brw_reg_type -brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, +enum elk_reg_type +elk_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo, unsigned hw_type, unsigned exec_type); unsigned -brw_reg_type_to_size(enum brw_reg_type type); +elk_reg_type_to_size(enum elk_reg_type type); const char * -brw_reg_type_to_letters(enum brw_reg_type type); +elk_reg_type_to_letters(enum elk_reg_type type); #ifdef __cplusplus } diff --git a/src/intel/compiler/elk/elk_schedule_instructions.cpp b/src/intel/compiler/elk/elk_schedule_instructions.cpp index 6e08642da10..2183d5418cd 100644 --- a/src/intel/compiler/elk/elk_schedule_instructions.cpp +++ b/src/intel/compiler/elk/elk_schedule_instructions.cpp @@ -59,17 +59,17 @@ using namespace elk; static bool debug = false; -class instruction_scheduler; -struct schedule_node_child; +class elk_instruction_scheduler; +struct elk_schedule_node_child; -class schedule_node : public exec_node +class elk_schedule_node : public exec_node { public: void set_latency_gfx4(); - void set_latency_gfx7(const struct brw_isa_info *isa); + void set_latency_gfx7(const struct elk_isa_info *isa); - backend_instruction *inst; - schedule_node_child *children; + elk_backend_instruction *inst; + elk_schedule_node_child *children; int children_count; int children_cap; int initial_parent_count; @@ -88,7 +88,7 @@ public: * one that may cause earliest program termination, or NULL if none of the * successors is an exit node. */ - schedule_node *exit; + elk_schedule_node *exit; /** * How many cycles this instruction takes to issue. @@ -112,13 +112,13 @@ public: } tmp; }; -struct schedule_node_child { - schedule_node *n; +struct elk_schedule_node_child { + elk_schedule_node *n; int effective_latency; }; static inline void -reset_node_tmp(schedule_node *n) +reset_node_tmp(elk_schedule_node *n) { n->tmp.parent_count = n->initial_parent_count; n->tmp.unblocked_time = n->initial_unblocked_time; @@ -138,46 +138,46 @@ reset_node_tmp(schedule_node *n) * can unblock an exit node and lead to program termination. */ static inline int -exit_tmp_unblocked_time(const schedule_node *n) +exit_tmp_unblocked_time(const elk_schedule_node *n) { return n->exit ? n->exit->tmp.unblocked_time : INT_MAX; } static inline int -exit_initial_unblocked_time(const schedule_node *n) +exit_initial_unblocked_time(const elk_schedule_node *n) { return n->exit ? n->exit->initial_unblocked_time : INT_MAX; } void -schedule_node::set_latency_gfx4() +elk_schedule_node::set_latency_gfx4() { int chans = 8; int math_latency = 22; switch (inst->opcode) { - case SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RCP: this->latency = 1 * chans * math_latency; break; - case SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_RSQ: this->latency = 2 * chans * math_latency; break; - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_LOG2: /* full precision log. partial is 2. */ this->latency = 3 * chans * math_latency; break; - case SHADER_OPCODE_INT_REMAINDER: - case SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_EXP2: /* full precision. partial is 3, same throughput. */ this->latency = 4 * chans * math_latency; break; - case SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_POW: this->latency = 8 * chans * math_latency; break; - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: /* minimum latency, max is 12 rounds. */ this->latency = 5 * chans * math_latency; break; @@ -188,12 +188,12 @@ schedule_node::set_latency_gfx4() } void -schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) +elk_schedule_node::set_latency_gfx7(const struct elk_isa_info *isa) { const bool is_haswell = isa->devinfo->verx10 == 75; switch (inst->opcode) { - case BRW_OPCODE_MAD: + case ELK_OPCODE_MAD: /* 2 cycles * (since the last two src operands are in different register banks): * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q }; @@ -219,7 +219,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) latency = is_haswell ? 16 : 18; break; - case BRW_OPCODE_LRP: + case ELK_OPCODE_LRP: /* 2 cycles * (since the last two src operands are in different register banks): * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q }; @@ -245,13 +245,13 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) latency = 14; break; - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: /* 2 cycles: * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q }; * @@ -264,7 +264,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) latency = is_haswell ? 14 : 16; break; - case SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_POW: /* 2 cycles: * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q }; * @@ -275,12 +275,12 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) latency = is_haswell ? 22 : 24; break; - case SHADER_OPCODE_TEX: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_LZ: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXL_LZ: + case ELK_SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL_LZ: /* 18 cycles: * mov(8) g115<1>F 0F { align1 WE_normal 1Q }; * mov(8) g114<1>F 0F { align1 WE_normal 1Q }; @@ -332,7 +332,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) latency = 200; break; - case SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TXS: /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41 * cycles (n=15): * mov(8) g114<1>UD 0D { align1 WE_normal 1Q }; @@ -359,9 +359,9 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) latency = 100; break; - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: - case VS_OPCODE_PULL_CONSTANT_LOAD: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD: /* testing using varying-index pull constants: * * 16 cycles: @@ -391,7 +391,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) latency = 200; break; - case SHADER_OPCODE_GFX7_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX7_SCRATCH_READ: /* Testing a load from offset 0, that had been previously written: * * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q }; @@ -403,30 +403,30 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) latency = 50; break; - case VEC4_OPCODE_UNTYPED_ATOMIC: + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: /* See GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP */ latency = 14000; break; - case VEC4_OPCODE_UNTYPED_SURFACE_READ: - case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE: /* See also GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ */ latency = is_haswell ? 300 : 600; break; - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: switch (inst->sfid) { - case BRW_SFID_SAMPLER: { + case ELK_SFID_SAMPLER: { unsigned msg_type = (inst->desc >> 12) & 0x1f; switch (msg_type) { case GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO: case GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO: - /* See also SHADER_OPCODE_TXS */ + /* See also ELK_SHADER_OPCODE_TXS */ latency = 100; break; default: - /* See also SHADER_OPCODE_TEX */ + /* See also ELK_SHADER_OPCODE_TEX */ latency = 200; break; } @@ -434,21 +434,21 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) } case GFX6_SFID_DATAPORT_CONSTANT_CACHE: - /* See FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD */ + /* See ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD */ latency = 200; break; case GFX6_SFID_DATAPORT_RENDER_CACHE: - switch (brw_fb_desc_msg_type(isa->devinfo, inst->desc)) { + switch (elk_fb_desc_msg_type(isa->devinfo, inst->desc)) { case GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE: case GFX7_DATAPORT_RC_TYPED_SURFACE_READ: - /* See also SHADER_OPCODE_TYPED_SURFACE_READ */ + /* See also ELK_SHADER_OPCODE_TYPED_SURFACE_READ */ assert(!is_haswell); latency = 600; break; case GFX7_DATAPORT_RC_TYPED_ATOMIC_OP: - /* See also SHADER_OPCODE_TYPED_ATOMIC */ + /* See also ELK_SHADER_OPCODE_TYPED_ATOMIC */ assert(!is_haswell); latency = 14000; break; @@ -465,7 +465,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) case GFX7_SFID_DATAPORT_DATA_CACHE: switch ((inst->desc >> 14) & 0x1f) { - case BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ: + case ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ: case GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ: case GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE: /* We have no data for this but assume it's a little faster than @@ -534,7 +534,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) break; case HSW_SFID_DATAPORT_DATA_CACHE_1: - switch (brw_dp_desc_msg_type(isa->devinfo, inst->desc)) { + switch (elk_dp_desc_msg_type(isa->devinfo, inst->desc)) { case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ: case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE: case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ: @@ -608,7 +608,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) } break; - case BRW_SFID_URB: + case ELK_SFID_URB: latency = 200; break; @@ -617,7 +617,7 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) } break; - case BRW_OPCODE_DPAS: + case ELK_OPCODE_DPAS: switch (inst->rcount) { case 1: latency = 21; @@ -645,9 +645,9 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa) } } -class instruction_scheduler { +class elk_instruction_scheduler { public: - instruction_scheduler(void *mem_ctx, const backend_shader *s, int grf_count, + elk_instruction_scheduler(void *mem_ctx, const elk_backend_shader *s, int grf_count, int grf_write_scale, bool post_reg_alloc): bs(s) { @@ -656,16 +656,16 @@ public: this->grf_count = grf_count; this->post_reg_alloc = post_reg_alloc; - this->last_grf_write = linear_zalloc_array(lin_ctx, schedule_node *, grf_count * grf_write_scale); + this->last_grf_write = linear_zalloc_array(lin_ctx, elk_schedule_node *, grf_count * grf_write_scale); this->nodes_len = s->cfg->last_block()->end_ip + 1; - this->nodes = linear_zalloc_array(lin_ctx, schedule_node, this->nodes_len); + this->nodes = linear_zalloc_array(lin_ctx, elk_schedule_node, this->nodes_len); const struct intel_device_info *devinfo = bs->devinfo; - const struct brw_isa_info *isa = &bs->compiler->isa; + const struct elk_isa_info *isa = &bs->compiler->isa; - schedule_node *n = nodes; - foreach_block_and_inst(block, backend_instruction, inst, s->cfg) { + elk_schedule_node *n = nodes; + foreach_block_and_inst(block, elk_backend_instruction, inst, s->cfg) { n->inst = inst; /* We can't measure Gfx6 timings directly but expect them to be much @@ -691,33 +691,33 @@ public: current.available.make_empty(); } - void add_barrier_deps(schedule_node *n); - void add_cross_lane_deps(schedule_node *n); - void add_dep(schedule_node *before, schedule_node *after, int latency); - void add_dep(schedule_node *before, schedule_node *after); + void add_barrier_deps(elk_schedule_node *n); + void add_cross_lane_deps(elk_schedule_node *n); + void add_dep(elk_schedule_node *before, elk_schedule_node *after, int latency); + void add_dep(elk_schedule_node *before, elk_schedule_node *after); - void set_current_block(bblock_t *block); + void set_current_block(elk_bblock_t *block); void compute_delays(); void compute_exits(); - void schedule(schedule_node *chosen); - void update_children(schedule_node *chosen); + void schedule(elk_schedule_node *chosen); + void update_children(elk_schedule_node *chosen); void *mem_ctx; linear_ctx *lin_ctx; - schedule_node *nodes; + elk_schedule_node *nodes; int nodes_len; /* Current block being processed. */ struct { - bblock_t *block; + elk_bblock_t *block; /* Range of nodes in the block. End will point to first node * address after the block, i.e. the range is [start, end). */ - schedule_node *start; - schedule_node *end; + elk_schedule_node *start; + elk_schedule_node *end; int len; int scheduled; @@ -729,35 +729,35 @@ public: bool post_reg_alloc; int grf_count; - const backend_shader *bs; + const elk_backend_shader *bs; /** * Last instruction to have written the grf (or a channel in the grf, for the * scalar backend) */ - schedule_node **last_grf_write; + elk_schedule_node **last_grf_write; }; -class fs_instruction_scheduler : public instruction_scheduler +class elk_fs_instruction_scheduler : public elk_instruction_scheduler { public: - fs_instruction_scheduler(void *mem_ctx, const fs_visitor *v, int grf_count, int hw_reg_count, + elk_fs_instruction_scheduler(void *mem_ctx, const elk_fs_visitor *v, int grf_count, int hw_reg_count, int block_count, bool post_reg_alloc); void calculate_deps(); - bool is_compressed(const fs_inst *inst); - schedule_node *choose_instruction_to_schedule(); - int calculate_issue_time(backend_instruction *inst); + bool is_compressed(const elk_fs_inst *inst); + elk_schedule_node *choose_instruction_to_schedule(); + int calculate_issue_time(elk_backend_instruction *inst); - void count_reads_remaining(backend_instruction *inst); - void setup_liveness(cfg_t *cfg); - void update_register_pressure(backend_instruction *inst); - int get_register_pressure_benefit(backend_instruction *inst); + void count_reads_remaining(elk_backend_instruction *inst); + void setup_liveness(elk_cfg_t *cfg); + void update_register_pressure(elk_backend_instruction *inst); + int get_register_pressure_benefit(elk_backend_instruction *inst); void clear_last_grf_write(); void schedule_instructions(); void run(instruction_scheduler_mode mode); - const fs_visitor *v; + const elk_fs_visitor *v; unsigned hw_reg_count; int reg_pressure; instruction_scheduler_mode mode; @@ -806,10 +806,10 @@ public: }; -fs_instruction_scheduler::fs_instruction_scheduler(void *mem_ctx, const fs_visitor *v, +elk_fs_instruction_scheduler::elk_fs_instruction_scheduler(void *mem_ctx, const elk_fs_visitor *v, int grf_count, int hw_reg_count, int block_count, bool post_reg_alloc) - : instruction_scheduler(mem_ctx, v, grf_count, /* grf_write_scale */ 16, + : elk_instruction_scheduler(mem_ctx, v, grf_count, /* grf_write_scale */ 16, post_reg_alloc), v(v) { @@ -855,7 +855,7 @@ fs_instruction_scheduler::fs_instruction_scheduler(void *mem_ctx, const fs_visit foreach_block(block, v->cfg) { set_current_block(block); - for (schedule_node *n = current.start; n < current.end; n++) + for (elk_schedule_node *n = current.start; n < current.end; n++) n->issue_time = calculate_issue_time(n->inst); calculate_deps(); @@ -865,7 +865,7 @@ fs_instruction_scheduler::fs_instruction_scheduler(void *mem_ctx, const fs_visit } static bool -is_src_duplicate(fs_inst *inst, int src) +is_src_duplicate(elk_fs_inst *inst, int src) { for (int i = 0; i < src; i++) if (inst->src[i].equals(inst->src[src])) @@ -875,11 +875,11 @@ is_src_duplicate(fs_inst *inst, int src) } void -fs_instruction_scheduler::count_reads_remaining(backend_instruction *be) +elk_fs_instruction_scheduler::count_reads_remaining(elk_backend_instruction *be) { assert(reads_remaining); - fs_inst *inst = (fs_inst *)be; + elk_fs_inst *inst = (elk_fs_inst *)be; for (int i = 0; i < inst->sources; i++) { if (is_src_duplicate(inst, i)) @@ -898,7 +898,7 @@ fs_instruction_scheduler::count_reads_remaining(backend_instruction *be) } void -fs_instruction_scheduler::setup_liveness(cfg_t *cfg) +elk_fs_instruction_scheduler::setup_liveness(elk_cfg_t *cfg) { const fs_live_variables &live = v->live_analysis.require(); @@ -956,11 +956,11 @@ fs_instruction_scheduler::setup_liveness(cfg_t *cfg) } void -fs_instruction_scheduler::update_register_pressure(backend_instruction *be) +elk_fs_instruction_scheduler::update_register_pressure(elk_backend_instruction *be) { assert(reads_remaining); - fs_inst *inst = (fs_inst *)be; + elk_fs_inst *inst = (elk_fs_inst *)be; if (inst->dst.file == VGRF) { written[inst->dst.nr] = true; @@ -981,9 +981,9 @@ fs_instruction_scheduler::update_register_pressure(backend_instruction *be) } int -fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be) +elk_fs_instruction_scheduler::get_register_pressure_benefit(elk_backend_instruction *be) { - fs_inst *inst = (fs_inst *)be; + elk_fs_inst *inst = (elk_fs_inst *)be; int benefit = 0; const int block_idx = current.block->num; @@ -1017,27 +1017,27 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be) return benefit; } -class vec4_instruction_scheduler : public instruction_scheduler +class elk_vec4_instruction_scheduler : public elk_instruction_scheduler { public: - vec4_instruction_scheduler(void *mem_ctx, const vec4_visitor *v, int grf_count); + elk_vec4_instruction_scheduler(void *mem_ctx, const vec4_visitor *v, int grf_count); void calculate_deps(); - schedule_node *choose_instruction_to_schedule(); + elk_schedule_node *choose_instruction_to_schedule(); const vec4_visitor *v; void run(); }; -vec4_instruction_scheduler::vec4_instruction_scheduler(void *mem_ctx, const vec4_visitor *v, +elk_vec4_instruction_scheduler::elk_vec4_instruction_scheduler(void *mem_ctx, const vec4_visitor *v, int grf_count) - : instruction_scheduler(mem_ctx, v, grf_count, /* grf_write_scale */ 1, + : elk_instruction_scheduler(mem_ctx, v, grf_count, /* grf_write_scale */ 1, /* post_reg_alloc */ true), v(v) { } void -instruction_scheduler::set_current_block(bblock_t *block) +elk_instruction_scheduler::set_current_block(elk_bblock_t *block) { current.block = block; current.start = nodes + block->start_ip; @@ -1050,9 +1050,9 @@ instruction_scheduler::set_current_block(bblock_t *block) /** Computation of the delay member of each node. */ void -instruction_scheduler::compute_delays() +elk_instruction_scheduler::compute_delays() { - for (schedule_node *n = current.end - 1; n >= current.start; n--) { + for (elk_schedule_node *n = current.end - 1; n >= current.start; n--) { if (!n->children_count) { n->delay = n->issue_time; } else { @@ -1065,15 +1065,15 @@ instruction_scheduler::compute_delays() } void -instruction_scheduler::compute_exits() +elk_instruction_scheduler::compute_exits() { /* Calculate a lower bound of the scheduling time of each node in the * graph. This is analogous to the node's critical path but calculated * from the top instead of from the bottom of the block. */ - for (schedule_node *n = current.start; n < current.end; n++) { + for (elk_schedule_node *n = current.start; n < current.end; n++) { for (int i = 0; i < n->children_count; i++) { - schedule_node_child *child = &n->children[i]; + elk_schedule_node_child *child = &n->children[i]; child->n->initial_unblocked_time = MAX2(child->n->initial_unblocked_time, n->initial_unblocked_time + n->issue_time + child->effective_latency); @@ -1085,8 +1085,8 @@ instruction_scheduler::compute_exits() * nodes of its children which can be unblocked first according to the * optimistic unblocked time estimate calculated above. */ - for (schedule_node *n = current.end - 1; n >= current.start; n--) { - n->exit = (n->inst->opcode == BRW_OPCODE_HALT ? n : NULL); + for (elk_schedule_node *n = current.end - 1; n >= current.start; n--) { + n->exit = (n->inst->opcode == ELK_OPCODE_HALT ? n : NULL); for (int i = 0; i < n->children_count; i++) { if (exit_initial_unblocked_time(n->children[i].n) < exit_initial_unblocked_time(n)) @@ -1102,7 +1102,7 @@ instruction_scheduler::compute_exits() * schedule it @latency cycles after @before, but no guarantees there. */ void -instruction_scheduler::add_dep(schedule_node *before, schedule_node *after, +elk_instruction_scheduler::add_dep(elk_schedule_node *before, elk_schedule_node *after, int latency) { if (!before || !after) @@ -1111,7 +1111,7 @@ instruction_scheduler::add_dep(schedule_node *before, schedule_node *after, assert(before != after); for (int i = 0; i < before->children_count; i++) { - schedule_node_child *child = &before->children[i]; + elk_schedule_node_child *child = &before->children[i]; if (child->n == after) { child->effective_latency = MAX2(child->effective_latency, latency); return; @@ -1125,11 +1125,11 @@ instruction_scheduler::add_dep(schedule_node *before, schedule_node *after, before->children_cap *= 2; before->children = reralloc(mem_ctx, before->children, - schedule_node_child, + elk_schedule_node_child, before->children_cap); } - schedule_node_child *child = &before->children[before->children_count]; + elk_schedule_node_child *child = &before->children[before->children_count]; child->n = after; child->effective_latency = latency; before->children_count++; @@ -1137,7 +1137,7 @@ instruction_scheduler::add_dep(schedule_node *before, schedule_node *after, } void -instruction_scheduler::add_dep(schedule_node *before, schedule_node *after) +elk_instruction_scheduler::add_dep(elk_schedule_node *before, elk_schedule_node *after) { if (!before) return; @@ -1146,28 +1146,28 @@ instruction_scheduler::add_dep(schedule_node *before, schedule_node *after) } static bool -is_scheduling_barrier(const backend_instruction *inst) +is_scheduling_barrier(const elk_backend_instruction *inst) { - return inst->opcode == SHADER_OPCODE_HALT_TARGET || + return inst->opcode == ELK_SHADER_OPCODE_HALT_TARGET || inst->is_control_flow() || inst->has_side_effects(); } static bool -has_cross_lane_access(const fs_inst *inst) +has_cross_lane_access(const elk_fs_inst *inst) { /* FINISHME: * * This function is likely incomplete in terms of identify cross lane * accesses. */ - if (inst->opcode == SHADER_OPCODE_BROADCAST || - inst->opcode == SHADER_OPCODE_READ_SR_REG || - inst->opcode == SHADER_OPCODE_CLUSTER_BROADCAST || - inst->opcode == SHADER_OPCODE_SHUFFLE || - inst->opcode == FS_OPCODE_LOAD_LIVE_CHANNELS || - inst->opcode == SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL || - inst->opcode == SHADER_OPCODE_FIND_LIVE_CHANNEL) + if (inst->opcode == ELK_SHADER_OPCODE_BROADCAST || + inst->opcode == ELK_SHADER_OPCODE_READ_SR_REG || + inst->opcode == ELK_SHADER_OPCODE_CLUSTER_BROADCAST || + inst->opcode == ELK_SHADER_OPCODE_SHUFFLE || + inst->opcode == ELK_FS_OPCODE_LOAD_LIVE_CHANNELS || + inst->opcode == ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL || + inst->opcode == ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL) return true; for (unsigned s = 0; s < inst->sources; s++) { @@ -1186,15 +1186,15 @@ has_cross_lane_access(const fs_inst *inst) * the deps to do so. */ void -instruction_scheduler::add_barrier_deps(schedule_node *n) +elk_instruction_scheduler::add_barrier_deps(elk_schedule_node *n) { - for (schedule_node *prev = n - 1; prev >= current.start; prev--) { + for (elk_schedule_node *prev = n - 1; prev >= current.start; prev--) { add_dep(prev, n, 0); if (is_scheduling_barrier(prev->inst)) break; } - for (schedule_node *next = n + 1; next < current.end; next++) { + for (elk_schedule_node *next = n + 1; next < current.end; next++) { add_dep(n, next, 0); if (is_scheduling_barrier(next->inst)) break; @@ -1207,10 +1207,10 @@ instruction_scheduler::add_barrier_deps(schedule_node *n) * later instructions accessing uninitialized data. */ void -instruction_scheduler::add_cross_lane_deps(schedule_node *n) +elk_instruction_scheduler::add_cross_lane_deps(elk_schedule_node *n) { - for (schedule_node *prev = n - 1; prev >= current.start; prev--) { - if (has_cross_lane_access((fs_inst*)prev->inst)) + for (elk_schedule_node *prev = n - 1; prev >= current.start; prev--) { + if (has_cross_lane_access((elk_fs_inst*)prev->inst)) add_dep(prev, n, 0); } } @@ -1219,7 +1219,7 @@ instruction_scheduler::add_cross_lane_deps(schedule_node *n) * actually writes 2 MRFs. */ bool -fs_instruction_scheduler::is_compressed(const fs_inst *inst) +elk_fs_instruction_scheduler::is_compressed(const elk_fs_inst *inst) { return inst->exec_size == 16; } @@ -1236,11 +1236,11 @@ fs_instruction_scheduler::is_compressed(const fs_inst *inst) * with instructions. */ void -fs_instruction_scheduler::clear_last_grf_write() +elk_fs_instruction_scheduler::clear_last_grf_write() { if (!post_reg_alloc) { - for (schedule_node *n = current.start; n < current.end; n++) { - fs_inst *inst = (fs_inst *)n->inst; + for (elk_schedule_node *n = current.start; n < current.end; n++) { + elk_fs_inst *inst = (elk_fs_inst *)n->inst; if (inst->dst.file == VGRF) { /* Don't bother being careful with regs_written(), quicker to just clear 2 cachelines. */ @@ -1253,33 +1253,33 @@ fs_instruction_scheduler::clear_last_grf_write() } void -fs_instruction_scheduler::calculate_deps() +elk_fs_instruction_scheduler::calculate_deps() { /* Pre-register-allocation, this tracks the last write per VGRF offset. * After register allocation, reg_offsets are gone and we track individual * GRF registers. */ - schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->ver)]; - schedule_node *last_conditional_mod[8] = {}; - schedule_node *last_accumulator_write = NULL; + elk_schedule_node *last_mrf_write[ELK_MAX_MRF(v->devinfo->ver)]; + elk_schedule_node *last_conditional_mod[8] = {}; + elk_schedule_node *last_accumulator_write = NULL; /* Fixed HW registers are assumed to be separate from the virtual * GRFs, so they can be tracked separately. We don't really write * to fixed GRFs much, so don't bother tracking them on a more * granular level. */ - schedule_node *last_fixed_grf_write = NULL; + elk_schedule_node *last_fixed_grf_write = NULL; memset(last_mrf_write, 0, sizeof(last_mrf_write)); /* top-to-bottom dependencies: RAW and WAW. */ - for (schedule_node *n = current.start; n < current.end; n++) { - fs_inst *inst = (fs_inst *)n->inst; + for (elk_schedule_node *n = current.start; n < current.end; n++) { + elk_fs_inst *inst = (elk_fs_inst *)n->inst; if (is_scheduling_barrier(inst)) add_barrier_deps(n); - if (inst->opcode == BRW_OPCODE_HALT || - inst->opcode == SHADER_OPCODE_HALT_TARGET) + if (inst->opcode == ELK_OPCODE_HALT || + inst->opcode == ELK_SHADER_OPCODE_HALT_TARGET) add_cross_lane_deps(n); /* read-after-write deps. */ @@ -1347,12 +1347,12 @@ fs_instruction_scheduler::calculate_deps() } } } else if (inst->dst.file == MRF) { - int reg = inst->dst.nr & ~BRW_MRF_COMPR4; + int reg = inst->dst.nr & ~ELK_MRF_COMPR4; add_dep(last_mrf_write[reg], n); last_mrf_write[reg] = n; if (is_compressed(inst)) { - if (inst->dst.nr & BRW_MRF_COMPR4) + if (inst->dst.nr & ELK_MRF_COMPR4) reg += 4; else reg++; @@ -1409,8 +1409,8 @@ fs_instruction_scheduler::calculate_deps() last_accumulator_write = NULL; last_fixed_grf_write = NULL; - for (schedule_node *n = current.end - 1; n >= current.start; n--) { - fs_inst *inst = (fs_inst *)n->inst; + for (elk_schedule_node *n = current.end - 1; n >= current.start; n--) { + elk_fs_inst *inst = (elk_fs_inst *)n->inst; /* write-after-read deps. */ for (int i = 0; i < inst->sources; i++) { @@ -1475,12 +1475,12 @@ fs_instruction_scheduler::calculate_deps() } } } else if (inst->dst.file == MRF) { - int reg = inst->dst.nr & ~BRW_MRF_COMPR4; + int reg = inst->dst.nr & ~ELK_MRF_COMPR4; last_mrf_write[reg] = n; if (is_compressed(inst)) { - if (inst->dst.nr & BRW_MRF_COMPR4) + if (inst->dst.nr & ELK_MRF_COMPR4) reg += 4; else reg++; @@ -1524,23 +1524,23 @@ fs_instruction_scheduler::calculate_deps() } void -vec4_instruction_scheduler::calculate_deps() +elk_vec4_instruction_scheduler::calculate_deps() { - schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->ver)]; - schedule_node *last_conditional_mod = NULL; - schedule_node *last_accumulator_write = NULL; + elk_schedule_node *last_mrf_write[ELK_MAX_MRF(v->devinfo->ver)]; + elk_schedule_node *last_conditional_mod = NULL; + elk_schedule_node *last_accumulator_write = NULL; /* Fixed HW registers are assumed to be separate from the virtual * GRFs, so they can be tracked separately. We don't really write * to fixed GRFs much, so don't bother tracking them on a more * granular level. */ - schedule_node *last_fixed_grf_write = NULL; + elk_schedule_node *last_fixed_grf_write = NULL; memset(last_grf_write, 0, grf_count * sizeof(*last_grf_write)); memset(last_mrf_write, 0, sizeof(last_mrf_write)); /* top-to-bottom dependencies: RAW and WAW. */ - for (schedule_node *n = current.start; n < current.end; n++) { + for (elk_schedule_node *n = current.start; n < current.end; n++) { vec4_instruction *inst = (vec4_instruction *)n->inst; if (is_scheduling_barrier(inst)) @@ -1629,7 +1629,7 @@ vec4_instruction_scheduler::calculate_deps() last_accumulator_write = NULL; last_fixed_grf_write = NULL; - for (schedule_node *n = current.end - 1; n >= current.start; n--) { + for (elk_schedule_node *n = current.end - 1; n >= current.start; n--) { vec4_instruction *inst = (vec4_instruction *)n->inst; /* write-after-read deps. */ @@ -1696,10 +1696,10 @@ vec4_instruction_scheduler::calculate_deps() } } -schedule_node * -fs_instruction_scheduler::choose_instruction_to_schedule() +elk_schedule_node * +elk_fs_instruction_scheduler::choose_instruction_to_schedule() { - schedule_node *chosen = NULL; + elk_schedule_node *chosen = NULL; if (mode == SCHEDULE_PRE || mode == SCHEDULE_POST) { int chosen_time = 0; @@ -1708,7 +1708,7 @@ fs_instruction_scheduler::choose_instruction_to_schedule() * choose the one most likely to unblock an early program exit, or * otherwise the oldest one. */ - foreach_in_list(schedule_node, n, ¤t.available) { + foreach_in_list(elk_schedule_node, n, ¤t.available) { if (!chosen || exit_tmp_unblocked_time(n) < exit_tmp_unblocked_time(chosen) || (exit_tmp_unblocked_time(n) == exit_tmp_unblocked_time(chosen) && @@ -1726,8 +1726,8 @@ fs_instruction_scheduler::choose_instruction_to_schedule() * shaders which naturally do a better job of hiding instruction * latency. */ - foreach_in_list(schedule_node, n, ¤t.available) { - fs_inst *inst = (fs_inst *)n->inst; + foreach_in_list(elk_schedule_node, n, ¤t.available) { + elk_fs_inst *inst = (elk_fs_inst *)n->inst; if (!chosen) { chosen = n; @@ -1775,7 +1775,7 @@ fs_instruction_scheduler::choose_instruction_to_schedule() * MRFs, etc., without ever consuming the results of a send. */ if (v->devinfo->ver < 7) { - fs_inst *chosen_inst = (fs_inst *)chosen->inst; + elk_fs_inst *chosen_inst = (elk_fs_inst *)chosen->inst; /* We use size_written > 4 * exec_size as our test for the kind * of send instruction to avoid -- only sends generate many @@ -1826,16 +1826,16 @@ fs_instruction_scheduler::choose_instruction_to_schedule() return chosen; } -schedule_node * -vec4_instruction_scheduler::choose_instruction_to_schedule() +elk_schedule_node * +elk_vec4_instruction_scheduler::choose_instruction_to_schedule() { - schedule_node *chosen = NULL; + elk_schedule_node *chosen = NULL; int chosen_time = 0; /* Of the instructions ready to execute or the closest to being ready, * choose the oldest one. */ - foreach_in_list(schedule_node, n, ¤t.available) { + foreach_in_list(elk_schedule_node, n, ¤t.available) { if (!chosen || n->tmp.unblocked_time < chosen_time) { chosen = n; chosen_time = n->tmp.unblocked_time; @@ -1846,11 +1846,11 @@ vec4_instruction_scheduler::choose_instruction_to_schedule() } int -fs_instruction_scheduler::calculate_issue_time(backend_instruction *inst0) +elk_fs_instruction_scheduler::calculate_issue_time(elk_backend_instruction *inst0) { - const struct brw_isa_info *isa = &v->compiler->isa; - const fs_inst *inst = static_cast(inst0); - const unsigned overhead = v->grf_used && has_bank_conflict(isa, inst) ? + const struct elk_isa_info *isa = &v->compiler->isa; + const elk_fs_inst *inst = static_cast(inst0); + const unsigned overhead = v->grf_used && elk_has_bank_conflict(isa, inst) ? DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE) : 0; if (is_compressed(inst)) return 4 + overhead; @@ -1859,7 +1859,7 @@ fs_instruction_scheduler::calculate_issue_time(backend_instruction *inst0) } void -instruction_scheduler::schedule(schedule_node *chosen) +elk_instruction_scheduler::schedule(elk_schedule_node *chosen) { assert(current.scheduled < current.len); current.scheduled++; @@ -1888,7 +1888,7 @@ instruction_scheduler::schedule(schedule_node *chosen) } void -instruction_scheduler::update_children(schedule_node *chosen) +elk_instruction_scheduler::update_children(elk_schedule_node *chosen) { /* Now that we've scheduled a new instruction, some of its * children can be promoted to the list of instructions ready to @@ -1896,7 +1896,7 @@ instruction_scheduler::update_children(schedule_node *chosen) * DAG edge as we do so. */ for (int i = chosen->children_count - 1; i >= 0; i--) { - schedule_node_child *child = &chosen->children[i]; + elk_schedule_node_child *child = &chosen->children[i]; child->n->tmp.unblocked_time = MAX2(child->n->tmp.unblocked_time, current.time + child->effective_latency); @@ -1923,7 +1923,7 @@ instruction_scheduler::update_children(schedule_node *chosen) * is done. */ if (bs->devinfo->ver < 6 && chosen->inst->is_math()) { - foreach_in_list(schedule_node, n, ¤t.available) { + foreach_in_list(elk_schedule_node, n, ¤t.available) { if (n->inst->is_math()) n->tmp.unblocked_time = MAX2(n->tmp.unblocked_time, current.time + chosen->latency); @@ -1932,13 +1932,13 @@ instruction_scheduler::update_children(schedule_node *chosen) } void -fs_instruction_scheduler::schedule_instructions() +elk_fs_instruction_scheduler::schedule_instructions() { if (!post_reg_alloc) reg_pressure = reg_pressure_in[current.block->num]; assert(current.available.is_empty()); - for (schedule_node *n = current.start; n < current.end; n++) { + for (elk_schedule_node *n = current.start; n < current.end; n++) { reset_node_tmp(n); /* Add DAG heads to the list of available instructions. */ @@ -1949,7 +1949,7 @@ fs_instruction_scheduler::schedule_instructions() current.block->instructions.make_empty(); while (!current.available.is_empty()) { - schedule_node *chosen = choose_instruction_to_schedule(); + elk_schedule_node *chosen = choose_instruction_to_schedule(); schedule(chosen); if (!post_reg_alloc) { @@ -1964,7 +1964,7 @@ fs_instruction_scheduler::schedule_instructions() } void -fs_instruction_scheduler::run(instruction_scheduler_mode mode) +elk_fs_instruction_scheduler::run(instruction_scheduler_mode mode) { this->mode = mode; @@ -1984,7 +1984,7 @@ fs_instruction_scheduler::run(instruction_scheduler_mode mode) set_current_block(block); if (!post_reg_alloc) { - for (schedule_node *n = current.start; n < current.end; n++) + for (elk_schedule_node *n = current.start; n < current.end; n++) count_reads_remaining(n->inst); } @@ -1999,12 +1999,12 @@ fs_instruction_scheduler::run(instruction_scheduler_mode mode) } void -vec4_instruction_scheduler::run() +elk_vec4_instruction_scheduler::run() { foreach_block(block, v->cfg) { set_current_block(block); - for (schedule_node *n = current.start; n < current.end; n++) { + for (elk_schedule_node *n = current.start; n < current.end; n++) { /* We always execute as two vec4s in parallel. */ n->issue_time = 2; } @@ -2015,7 +2015,7 @@ vec4_instruction_scheduler::run() compute_exits(); assert(current.available.is_empty()); - for (schedule_node *n = current.start; n < current.end; n++) { + for (elk_schedule_node *n = current.start; n < current.end; n++) { reset_node_tmp(n); /* Add DAG heads to the list of available instructions. */ @@ -2026,25 +2026,25 @@ vec4_instruction_scheduler::run() current.block->instructions.make_empty(); while (!current.available.is_empty()) { - schedule_node *chosen = choose_instruction_to_schedule(); + elk_schedule_node *chosen = choose_instruction_to_schedule(); schedule(chosen); update_children(chosen); } } } -fs_instruction_scheduler * -fs_visitor::prepare_scheduler(void *mem_ctx) +elk_fs_instruction_scheduler * +elk_fs_visitor::prepare_scheduler(void *mem_ctx) { const int grf_count = alloc.count; - fs_instruction_scheduler *empty = rzalloc(mem_ctx, fs_instruction_scheduler); - return new (empty) fs_instruction_scheduler(mem_ctx, this, grf_count, first_non_payload_grf, + elk_fs_instruction_scheduler *empty = rzalloc(mem_ctx, elk_fs_instruction_scheduler); + return new (empty) elk_fs_instruction_scheduler(mem_ctx, this, grf_count, first_non_payload_grf, cfg->num_blocks, /* post_reg_alloc */ false); } void -fs_visitor::schedule_instructions_pre_ra(fs_instruction_scheduler *sched, +elk_fs_visitor::schedule_instructions_pre_ra(elk_fs_instruction_scheduler *sched, instruction_scheduler_mode mode) { if (mode == SCHEDULE_NONE) @@ -2056,14 +2056,14 @@ fs_visitor::schedule_instructions_pre_ra(fs_instruction_scheduler *sched, } void -fs_visitor::schedule_instructions_post_ra() +elk_fs_visitor::schedule_instructions_post_ra() { const bool post_reg_alloc = true; const int grf_count = reg_unit(devinfo) * grf_used; void *mem_ctx = ralloc_context(NULL); - fs_instruction_scheduler sched(mem_ctx, this, grf_count, first_non_payload_grf, + elk_fs_instruction_scheduler sched(mem_ctx, this, grf_count, first_non_payload_grf, cfg->num_blocks, post_reg_alloc); sched.run(SCHEDULE_POST); @@ -2077,7 +2077,7 @@ vec4_visitor::opt_schedule_instructions() { void *mem_ctx = ralloc_context(NULL); - vec4_instruction_scheduler sched(mem_ctx, this, prog_data->total_grf); + elk_vec4_instruction_scheduler sched(mem_ctx, this, prog_data->total_grf); sched.run(); ralloc_free(mem_ctx); diff --git a/src/intel/compiler/elk/elk_shader.cpp b/src/intel/compiler/elk/elk_shader.cpp index dcac281e3f1..12a64620159 100644 --- a/src/intel/compiler/elk/elk_shader.cpp +++ b/src/intel/compiler/elk/elk_shader.cpp @@ -31,88 +31,88 @@ #include "util/macros.h" #include "util/u_debug.h" -enum brw_reg_type -brw_type_for_base_type(const struct glsl_type *type) +enum elk_reg_type +elk_type_for_base_type(const struct glsl_type *type) { switch (type->base_type) { case GLSL_TYPE_FLOAT16: - return BRW_REGISTER_TYPE_HF; + return ELK_REGISTER_TYPE_HF; case GLSL_TYPE_FLOAT: - return BRW_REGISTER_TYPE_F; + return ELK_REGISTER_TYPE_F; case GLSL_TYPE_INT: case GLSL_TYPE_BOOL: case GLSL_TYPE_SUBROUTINE: - return BRW_REGISTER_TYPE_D; + return ELK_REGISTER_TYPE_D; case GLSL_TYPE_INT16: - return BRW_REGISTER_TYPE_W; + return ELK_REGISTER_TYPE_W; case GLSL_TYPE_INT8: - return BRW_REGISTER_TYPE_B; + return ELK_REGISTER_TYPE_B; case GLSL_TYPE_UINT: - return BRW_REGISTER_TYPE_UD; + return ELK_REGISTER_TYPE_UD; case GLSL_TYPE_UINT16: - return BRW_REGISTER_TYPE_UW; + return ELK_REGISTER_TYPE_UW; case GLSL_TYPE_UINT8: - return BRW_REGISTER_TYPE_UB; + return ELK_REGISTER_TYPE_UB; case GLSL_TYPE_ARRAY: - return brw_type_for_base_type(type->fields.array); + return elk_type_for_base_type(type->fields.array); case GLSL_TYPE_STRUCT: case GLSL_TYPE_INTERFACE: case GLSL_TYPE_SAMPLER: case GLSL_TYPE_TEXTURE: case GLSL_TYPE_ATOMIC_UINT: /* These should be overridden with the type of the member when - * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely + * dereferenced into. ELK_REGISTER_TYPE_UD seems like a likely * way to trip up if we don't. */ - return BRW_REGISTER_TYPE_UD; + return ELK_REGISTER_TYPE_UD; case GLSL_TYPE_IMAGE: - return BRW_REGISTER_TYPE_UD; + return ELK_REGISTER_TYPE_UD; case GLSL_TYPE_DOUBLE: - return BRW_REGISTER_TYPE_DF; + return ELK_REGISTER_TYPE_DF; case GLSL_TYPE_UINT64: - return BRW_REGISTER_TYPE_UQ; + return ELK_REGISTER_TYPE_UQ; case GLSL_TYPE_INT64: - return BRW_REGISTER_TYPE_Q; + return ELK_REGISTER_TYPE_Q; case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_COOPERATIVE_MATRIX: unreachable("not reached"); } - return BRW_REGISTER_TYPE_F; + return ELK_REGISTER_TYPE_F; } uint32_t -brw_math_function(enum opcode op) +elk_math_function(enum elk_opcode op) { switch (op) { - case SHADER_OPCODE_RCP: - return BRW_MATH_FUNCTION_INV; - case SHADER_OPCODE_RSQ: - return BRW_MATH_FUNCTION_RSQ; - case SHADER_OPCODE_SQRT: - return BRW_MATH_FUNCTION_SQRT; - case SHADER_OPCODE_EXP2: - return BRW_MATH_FUNCTION_EXP; - case SHADER_OPCODE_LOG2: - return BRW_MATH_FUNCTION_LOG; - case SHADER_OPCODE_POW: - return BRW_MATH_FUNCTION_POW; - case SHADER_OPCODE_SIN: - return BRW_MATH_FUNCTION_SIN; - case SHADER_OPCODE_COS: - return BRW_MATH_FUNCTION_COS; - case SHADER_OPCODE_INT_QUOTIENT: - return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT; - case SHADER_OPCODE_INT_REMAINDER: - return BRW_MATH_FUNCTION_INT_DIV_REMAINDER; + case ELK_SHADER_OPCODE_RCP: + return ELK_MATH_FUNCTION_INV; + case ELK_SHADER_OPCODE_RSQ: + return ELK_MATH_FUNCTION_RSQ; + case ELK_SHADER_OPCODE_SQRT: + return ELK_MATH_FUNCTION_SQRT; + case ELK_SHADER_OPCODE_EXP2: + return ELK_MATH_FUNCTION_EXP; + case ELK_SHADER_OPCODE_LOG2: + return ELK_MATH_FUNCTION_LOG; + case ELK_SHADER_OPCODE_POW: + return ELK_MATH_FUNCTION_POW; + case ELK_SHADER_OPCODE_SIN: + return ELK_MATH_FUNCTION_SIN; + case ELK_SHADER_OPCODE_COS: + return ELK_MATH_FUNCTION_COS; + case ELK_SHADER_OPCODE_INT_QUOTIENT: + return ELK_MATH_FUNCTION_INT_DIV_QUOTIENT; + case ELK_SHADER_OPCODE_INT_REMAINDER: + return ELK_MATH_FUNCTION_INT_DIV_REMAINDER; default: unreachable("not reached: unknown math function"); } } bool -brw_texture_offset(const nir_tex_instr *tex, unsigned src, +elk_texture_offset(const nir_tex_instr *tex, unsigned src, uint32_t *offset_bits_out) { if (!nir_src_is_const(tex->src[src].src)) @@ -144,394 +144,394 @@ brw_texture_offset(const nir_tex_instr *tex, unsigned src, } const char * -brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) +elk_instruction_name(const struct elk_isa_info *isa, enum elk_opcode op) { const struct intel_device_info *devinfo = isa->devinfo; switch (op) { - case 0 ... NUM_BRW_OPCODES - 1: + case 0 ... NUM_ELK_OPCODES - 1: /* The DO instruction doesn't exist on Gfx6+, but we use it to mark the * start of a loop in the IR. */ - if (devinfo->ver >= 6 && op == BRW_OPCODE_DO) + if (devinfo->ver >= 6 && op == ELK_OPCODE_DO) return "do"; /* The following conversion opcodes doesn't exist on Gfx8+, but we use * then to mark that we want to do the conversion. */ - if (devinfo->ver > 7 && op == BRW_OPCODE_F32TO16) + if (devinfo->ver > 7 && op == ELK_OPCODE_F32TO16) return "f32to16"; - if (devinfo->ver > 7 && op == BRW_OPCODE_F16TO32) + if (devinfo->ver > 7 && op == ELK_OPCODE_F16TO32) return "f16to32"; /* DPAS instructions may transiently exist on platforms that do not * support DPAS. They will eventually be lowered, but in the meantime it * must be possible to query the instruction name. */ - if (devinfo->verx10 < 125 && op == BRW_OPCODE_DPAS) + if (devinfo->verx10 < 125 && op == ELK_OPCODE_DPAS) return "dpas"; - assert(brw_opcode_desc(isa, op)->name); - return brw_opcode_desc(isa, op)->name; - case FS_OPCODE_FB_WRITE: + assert(elk_opcode_desc(isa, op)->name); + return elk_opcode_desc(isa, op)->name; + case ELK_FS_OPCODE_FB_WRITE: return "fb_write"; - case FS_OPCODE_FB_WRITE_LOGICAL: + case ELK_FS_OPCODE_FB_WRITE_LOGICAL: return "fb_write_logical"; - case FS_OPCODE_REP_FB_WRITE: + case ELK_FS_OPCODE_REP_FB_WRITE: return "rep_fb_write"; - case FS_OPCODE_FB_READ: + case ELK_FS_OPCODE_FB_READ: return "fb_read"; - case FS_OPCODE_FB_READ_LOGICAL: + case ELK_FS_OPCODE_FB_READ_LOGICAL: return "fb_read_logical"; - case SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RCP: return "rcp"; - case SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_RSQ: return "rsq"; - case SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_SQRT: return "sqrt"; - case SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_EXP2: return "exp2"; - case SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_LOG2: return "log2"; - case SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_POW: return "pow"; - case SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_QUOTIENT: return "int_quot"; - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_INT_REMAINDER: return "int_rem"; - case SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_SIN: return "sin"; - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_COS: return "cos"; - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: return "send"; - case SHADER_OPCODE_UNDEF: + case ELK_SHADER_OPCODE_UNDEF: return "undef"; - case SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TEX: return "tex"; - case SHADER_OPCODE_TEX_LOGICAL: + case ELK_SHADER_OPCODE_TEX_LOGICAL: return "tex_logical"; - case SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXD: return "txd"; - case SHADER_OPCODE_TXD_LOGICAL: + case ELK_SHADER_OPCODE_TXD_LOGICAL: return "txd_logical"; - case SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF: return "txf"; - case SHADER_OPCODE_TXF_LOGICAL: + case ELK_SHADER_OPCODE_TXF_LOGICAL: return "txf_logical"; - case SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXF_LZ: return "txf_lz"; - case SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL: return "txl"; - case SHADER_OPCODE_TXL_LOGICAL: + case ELK_SHADER_OPCODE_TXL_LOGICAL: return "txl_logical"; - case SHADER_OPCODE_TXL_LZ: + case ELK_SHADER_OPCODE_TXL_LZ: return "txl_lz"; - case SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TXS: return "txs"; - case SHADER_OPCODE_TXS_LOGICAL: + case ELK_SHADER_OPCODE_TXS_LOGICAL: return "txs_logical"; - case FS_OPCODE_TXB: + case ELK_FS_OPCODE_TXB: return "txb"; - case FS_OPCODE_TXB_LOGICAL: + case ELK_FS_OPCODE_TXB_LOGICAL: return "txb_logical"; - case SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS: return "txf_cms"; - case SHADER_OPCODE_TXF_CMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL: return "txf_cms_logical"; - case SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_CMS_W: return "txf_cms_w"; - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL: return "txf_cms_w_logical"; - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: + case ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: return "txf_cms_w_gfx12_logical"; - case SHADER_OPCODE_TXF_UMS: + case ELK_SHADER_OPCODE_TXF_UMS: return "txf_ums"; - case SHADER_OPCODE_TXF_UMS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL: return "txf_ums_logical"; - case SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXF_MCS: return "txf_mcs"; - case SHADER_OPCODE_TXF_MCS_LOGICAL: + case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL: return "txf_mcs_logical"; - case SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_LOD: return "lod"; - case SHADER_OPCODE_LOD_LOGICAL: + case ELK_SHADER_OPCODE_LOD_LOGICAL: return "lod_logical"; - case SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4: return "tg4"; - case SHADER_OPCODE_TG4_LOGICAL: + case ELK_SHADER_OPCODE_TG4_LOGICAL: return "tg4_logical"; - case SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_TG4_OFFSET: return "tg4_offset"; - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: + case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL: return "tg4_offset_logical"; - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_SAMPLEINFO: return "sampleinfo"; - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL: return "sampleinfo_logical"; - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL: return "image_size_logical"; - case VEC4_OPCODE_UNTYPED_ATOMIC: + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: return "untyped_atomic"; - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: return "untyped_atomic_logical"; - case VEC4_OPCODE_UNTYPED_SURFACE_READ: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ: return "untyped_surface_read"; - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: return "untyped_surface_read_logical"; - case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE: return "untyped_surface_write"; - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: return "untyped_surface_write_logical"; - case SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: return "unaligned_oword_block_read_logical"; - case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL: return "oword_block_write_logical"; - case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: return "a64_untyped_read_logical"; - case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL: return "a64_oword_block_read_logical"; - case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL: return "a64_unaligned_oword_block_read_logical"; - case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: return "a64_oword_block_write_logical"; - case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: return "a64_untyped_write_logical"; - case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: return "a64_byte_scattered_read_logical"; - case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: return "a64_byte_scattered_write_logical"; - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: return "a64_untyped_atomic_logical"; - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: return "typed_atomic_logical"; - case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: return "typed_surface_read_logical"; - case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: return "typed_surface_write_logical"; - case SHADER_OPCODE_MEMORY_FENCE: + case ELK_SHADER_OPCODE_MEMORY_FENCE: return "memory_fence"; - case FS_OPCODE_SCHEDULING_FENCE: + case ELK_FS_OPCODE_SCHEDULING_FENCE: return "scheduling_fence"; - case SHADER_OPCODE_INTERLOCK: + case ELK_SHADER_OPCODE_INTERLOCK: /* For an interlock we actually issue a memory fence via sendc. */ return "interlock"; - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: return "byte_scattered_read_logical"; - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: return "byte_scattered_write_logical"; - case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: return "dword_scattered_read_logical"; - case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: return "dword_scattered_write_logical"; - case SHADER_OPCODE_LOAD_PAYLOAD: + case ELK_SHADER_OPCODE_LOAD_PAYLOAD: return "load_payload"; - case FS_OPCODE_PACK: + case ELK_FS_OPCODE_PACK: return "pack"; - case SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: return "gfx4_scratch_read"; - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: return "gfx4_scratch_write"; - case SHADER_OPCODE_GFX7_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX7_SCRATCH_READ: return "gfx7_scratch_read"; - case SHADER_OPCODE_SCRATCH_HEADER: + case ELK_SHADER_OPCODE_SCRATCH_HEADER: return "scratch_header"; - case SHADER_OPCODE_URB_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_URB_WRITE_LOGICAL: return "urb_write_logical"; - case SHADER_OPCODE_URB_READ_LOGICAL: + case ELK_SHADER_OPCODE_URB_READ_LOGICAL: return "urb_read_logical"; - case SHADER_OPCODE_FIND_LIVE_CHANNEL: + case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL: return "find_live_channel"; - case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: + case ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: return "find_last_live_channel"; - case FS_OPCODE_LOAD_LIVE_CHANNELS: + case ELK_FS_OPCODE_LOAD_LIVE_CHANNELS: return "load_live_channels"; - case SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_BROADCAST: return "broadcast"; - case SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_SHUFFLE: return "shuffle"; - case SHADER_OPCODE_SEL_EXEC: + case ELK_SHADER_OPCODE_SEL_EXEC: return "sel_exec"; - case SHADER_OPCODE_QUAD_SWIZZLE: + case ELK_SHADER_OPCODE_QUAD_SWIZZLE: return "quad_swizzle"; - case SHADER_OPCODE_CLUSTER_BROADCAST: + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: return "cluster_broadcast"; - case SHADER_OPCODE_GET_BUFFER_SIZE: + case ELK_SHADER_OPCODE_GET_BUFFER_SIZE: return "get_buffer_size"; - case VEC4_OPCODE_MOV_BYTES: + case ELK_VEC4_OPCODE_MOV_BYTES: return "mov_bytes"; - case VEC4_OPCODE_PACK_BYTES: + case ELK_VEC4_OPCODE_PACK_BYTES: return "pack_bytes"; - case VEC4_OPCODE_UNPACK_UNIFORM: + case ELK_VEC4_OPCODE_UNPACK_UNIFORM: return "unpack_uniform"; - case VEC4_OPCODE_DOUBLE_TO_F32: + case ELK_VEC4_OPCODE_DOUBLE_TO_F32: return "double_to_f32"; - case VEC4_OPCODE_DOUBLE_TO_D32: + case ELK_VEC4_OPCODE_DOUBLE_TO_D32: return "double_to_d32"; - case VEC4_OPCODE_DOUBLE_TO_U32: + case ELK_VEC4_OPCODE_DOUBLE_TO_U32: return "double_to_u32"; - case VEC4_OPCODE_TO_DOUBLE: + case ELK_VEC4_OPCODE_TO_DOUBLE: return "single_to_double"; - case VEC4_OPCODE_PICK_LOW_32BIT: + case ELK_VEC4_OPCODE_PICK_LOW_32BIT: return "pick_low_32bit"; - case VEC4_OPCODE_PICK_HIGH_32BIT: + case ELK_VEC4_OPCODE_PICK_HIGH_32BIT: return "pick_high_32bit"; - case VEC4_OPCODE_SET_LOW_32BIT: + case ELK_VEC4_OPCODE_SET_LOW_32BIT: return "set_low_32bit"; - case VEC4_OPCODE_SET_HIGH_32BIT: + case ELK_VEC4_OPCODE_SET_HIGH_32BIT: return "set_high_32bit"; - case VEC4_OPCODE_MOV_FOR_SCRATCH: + case ELK_VEC4_OPCODE_MOV_FOR_SCRATCH: return "mov_for_scratch"; - case VEC4_OPCODE_ZERO_OOB_PUSH_REGS: + case ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS: return "zero_oob_push_regs"; - case FS_OPCODE_DDX_COARSE: + case ELK_FS_OPCODE_DDX_COARSE: return "ddx_coarse"; - case FS_OPCODE_DDX_FINE: + case ELK_FS_OPCODE_DDX_FINE: return "ddx_fine"; - case FS_OPCODE_DDY_COARSE: + case ELK_FS_OPCODE_DDY_COARSE: return "ddy_coarse"; - case FS_OPCODE_DDY_FINE: + case ELK_FS_OPCODE_DDY_FINE: return "ddy_fine"; - case FS_OPCODE_LINTERP: + case ELK_FS_OPCODE_LINTERP: return "linterp"; - case FS_OPCODE_PIXEL_X: + case ELK_FS_OPCODE_PIXEL_X: return "pixel_x"; - case FS_OPCODE_PIXEL_Y: + case ELK_FS_OPCODE_PIXEL_Y: return "pixel_y"; - case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: + case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: return "uniform_pull_const"; - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4: return "varying_pull_const_gfx4"; - case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: + case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: return "varying_pull_const_logical"; - case FS_OPCODE_SET_SAMPLE_ID: + case ELK_FS_OPCODE_SET_SAMPLE_ID: return "set_sample_id"; - case FS_OPCODE_PACK_HALF_2x16_SPLIT: + case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT: return "pack_half_2x16_split"; - case SHADER_OPCODE_HALT_TARGET: + case ELK_SHADER_OPCODE_HALT_TARGET: return "halt_target"; - case FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE: return "interp_sample"; - case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: return "interp_shared_offset"; - case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: + case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: return "interp_per_slot_offset"; - case VEC4_VS_OPCODE_URB_WRITE: + case ELK_VEC4_VS_OPCODE_URB_WRITE: return "vs_urb_write"; - case VS_OPCODE_PULL_CONSTANT_LOAD: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD: return "pull_constant_load"; - case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: return "pull_constant_load_gfx7"; - case VS_OPCODE_UNPACK_FLAGS_SIMD4X2: + case ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2: return "unpack_flags_simd4x2"; - case VEC4_GS_OPCODE_URB_WRITE: + case ELK_VEC4_GS_OPCODE_URB_WRITE: return "gs_urb_write"; - case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE: + case ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE: return "gs_urb_write_allocate"; - case GS_OPCODE_THREAD_END: + case ELK_GS_OPCODE_THREAD_END: return "gs_thread_end"; - case GS_OPCODE_SET_WRITE_OFFSET: + case ELK_GS_OPCODE_SET_WRITE_OFFSET: return "set_write_offset"; - case GS_OPCODE_SET_VERTEX_COUNT: + case ELK_GS_OPCODE_SET_VERTEX_COUNT: return "set_vertex_count"; - case GS_OPCODE_SET_DWORD_2: + case ELK_GS_OPCODE_SET_DWORD_2: return "set_dword_2"; - case GS_OPCODE_PREPARE_CHANNEL_MASKS: + case ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS: return "prepare_channel_masks"; - case GS_OPCODE_SET_CHANNEL_MASKS: + case ELK_GS_OPCODE_SET_CHANNEL_MASKS: return "set_channel_masks"; - case GS_OPCODE_GET_INSTANCE_ID: + case ELK_GS_OPCODE_GET_INSTANCE_ID: return "get_instance_id"; - case GS_OPCODE_FF_SYNC: + case ELK_GS_OPCODE_FF_SYNC: return "ff_sync"; - case GS_OPCODE_SET_PRIMITIVE_ID: + case ELK_GS_OPCODE_SET_PRIMITIVE_ID: return "set_primitive_id"; - case GS_OPCODE_SVB_WRITE: + case ELK_GS_OPCODE_SVB_WRITE: return "gs_svb_write"; - case GS_OPCODE_SVB_SET_DST_INDEX: + case ELK_GS_OPCODE_SVB_SET_DST_INDEX: return "gs_svb_set_dst_index"; - case GS_OPCODE_FF_SYNC_SET_PRIMITIVES: + case ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES: return "gs_ff_sync_set_primitives"; - case CS_OPCODE_CS_TERMINATE: + case ELK_CS_OPCODE_CS_TERMINATE: return "cs_terminate"; - case SHADER_OPCODE_BARRIER: + case ELK_SHADER_OPCODE_BARRIER: return "barrier"; - case SHADER_OPCODE_MULH: + case ELK_SHADER_OPCODE_MULH: return "mulh"; - case SHADER_OPCODE_ISUB_SAT: + case ELK_SHADER_OPCODE_ISUB_SAT: return "isub_sat"; - case SHADER_OPCODE_USUB_SAT: + case ELK_SHADER_OPCODE_USUB_SAT: return "usub_sat"; - case SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_MOV_INDIRECT: return "mov_indirect"; - case SHADER_OPCODE_MOV_RELOC_IMM: + case ELK_SHADER_OPCODE_MOV_RELOC_IMM: return "mov_reloc_imm"; - case VEC4_OPCODE_URB_READ: + case ELK_VEC4_OPCODE_URB_READ: return "urb_read"; - case TCS_OPCODE_GET_INSTANCE_ID: + case ELK_TCS_OPCODE_GET_INSTANCE_ID: return "tcs_get_instance_id"; - case VEC4_TCS_OPCODE_URB_WRITE: + case ELK_VEC4_TCS_OPCODE_URB_WRITE: return "tcs_urb_write"; - case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: + case ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: return "tcs_set_input_urb_offsets"; - case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: + case ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: return "tcs_set_output_urb_offsets"; - case TCS_OPCODE_GET_PRIMITIVE_ID: + case ELK_TCS_OPCODE_GET_PRIMITIVE_ID: return "tcs_get_primitive_id"; - case TCS_OPCODE_CREATE_BARRIER_HEADER: + case ELK_TCS_OPCODE_CREATE_BARRIER_HEADER: return "tcs_create_barrier_header"; - case TCS_OPCODE_SRC0_010_IS_ZERO: + case ELK_TCS_OPCODE_SRC0_010_IS_ZERO: return "tcs_src0<0,1,0>_is_zero"; - case TCS_OPCODE_RELEASE_INPUT: + case ELK_TCS_OPCODE_RELEASE_INPUT: return "tcs_release_input"; - case TCS_OPCODE_THREAD_END: + case ELK_TCS_OPCODE_THREAD_END: return "tcs_thread_end"; - case TES_OPCODE_CREATE_INPUT_READ_HEADER: + case ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER: return "tes_create_input_read_header"; - case TES_OPCODE_ADD_INDIRECT_URB_OFFSET: + case ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET: return "tes_add_indirect_urb_offset"; - case TES_OPCODE_GET_PRIMITIVE_ID: + case ELK_TES_OPCODE_GET_PRIMITIVE_ID: return "tes_get_primitive_id"; - case RT_OPCODE_TRACE_RAY_LOGICAL: + case ELK_RT_OPCODE_TRACE_RAY_LOGICAL: return "rt_trace_ray_logical"; - case SHADER_OPCODE_RND_MODE: + case ELK_SHADER_OPCODE_RND_MODE: return "rnd_mode"; - case SHADER_OPCODE_FLOAT_CONTROL_MODE: + case ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE: return "float_control_mode"; - case SHADER_OPCODE_BTD_SPAWN_LOGICAL: + case ELK_SHADER_OPCODE_BTD_SPAWN_LOGICAL: return "btd_spawn_logical"; - case SHADER_OPCODE_BTD_RETIRE_LOGICAL: + case ELK_SHADER_OPCODE_BTD_RETIRE_LOGICAL: return "btd_retire_logical"; - case SHADER_OPCODE_READ_SR_REG: + case ELK_SHADER_OPCODE_READ_SR_REG: return "read_sr_reg"; } @@ -539,7 +539,7 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) } bool -brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg) +elk_saturate_immediate(enum elk_reg_type type, struct elk_reg *reg) { union { unsigned ud; @@ -560,30 +560,30 @@ brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg) imm.df = reg->df; switch (type) { - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_Q: /* Nothing to do. */ return false; - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: sat_imm.f = SATURATE(imm.f); break; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: sat_imm.df = SATURATE(imm.df); break; - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_B: unreachable("no UB/B immediates"); - case BRW_REGISTER_TYPE_V: - case BRW_REGISTER_TYPE_UV: - case BRW_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_VF: unreachable("unimplemented: saturate vector immediate"); - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: unreachable("unimplemented: saturate HF immediate"); - case BRW_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_NF: unreachable("no NF immediates"); } @@ -602,42 +602,42 @@ brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg) } bool -brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg) +elk_negate_immediate(enum elk_reg_type type, struct elk_reg *reg) { switch (type) { - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UD: reg->d = -reg->d; return true; - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UW: { + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UW: { uint16_t value = -(int16_t)reg->ud; reg->ud = value | (uint32_t)value << 16; return true; } - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: reg->f = -reg->f; return true; - case BRW_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_VF: reg->ud ^= 0x80808080; return true; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: reg->df = -reg->df; return true; - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_Q: reg->d64 = -reg->d64; return true; - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_B: unreachable("no UB/B immediates"); - case BRW_REGISTER_TYPE_UV: - case BRW_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_V: assert(!"unimplemented: negate UV/V immediate"); - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: reg->ud ^= 0x80008000; return true; - case BRW_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_NF: unreachable("no NF immediates"); } @@ -645,56 +645,56 @@ brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg) } bool -brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg) +elk_abs_immediate(enum elk_reg_type type, struct elk_reg *reg) { switch (type) { - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_D: reg->d = abs(reg->d); return true; - case BRW_REGISTER_TYPE_W: { + case ELK_REGISTER_TYPE_W: { uint16_t value = abs((int16_t)reg->ud); reg->ud = value | (uint32_t)value << 16; return true; } - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: reg->f = fabsf(reg->f); return true; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: reg->df = fabs(reg->df); return true; - case BRW_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_VF: reg->ud &= ~0x80808080; return true; - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_Q: reg->d64 = imaxabs(reg->d64); return true; - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_B: + case ELK_REGISTER_TYPE_UB: + case ELK_REGISTER_TYPE_B: unreachable("no UB/B immediates"); - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_UV: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_UV: /* Presumably the absolute value modifier on an unsigned source is a * nop, but it would be nice to confirm. */ assert(!"unimplemented: abs unsigned immediate"); - case BRW_REGISTER_TYPE_V: + case ELK_REGISTER_TYPE_V: assert(!"unimplemented: abs V immediate"); - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: reg->ud &= ~0x80008000; return true; - case BRW_REGISTER_TYPE_NF: + case ELK_REGISTER_TYPE_NF: unreachable("no NF immediates"); } return false; } -backend_shader::backend_shader(const struct brw_compiler *compiler, - const struct brw_compile_params *params, +elk_backend_shader::elk_backend_shader(const struct elk_compiler *compiler, + const struct elk_compile_params *params, const nir_shader *shader, - struct brw_stage_prog_data *stage_prog_data, + struct elk_stage_prog_data *stage_prog_data, bool debug_enabled) : compiler(compiler), log_data(params->log_data), @@ -708,24 +708,24 @@ backend_shader::backend_shader(const struct brw_compiler *compiler, { } -backend_shader::~backend_shader() +elk_backend_shader::~elk_backend_shader() { } bool -backend_reg::equals(const backend_reg &r) const +elk_backend_reg::equals(const elk_backend_reg &r) const { - return brw_regs_equal(this, &r) && offset == r.offset; + return elk_regs_equal(this, &r) && offset == r.offset; } bool -backend_reg::negative_equals(const backend_reg &r) const +elk_backend_reg::negative_equals(const elk_backend_reg &r) const { - return brw_regs_negative_equal(this, &r) && offset == r.offset; + return elk_regs_negative_equal(this, &r) && offset == r.offset; } bool -backend_reg::is_zero() const +elk_backend_reg::is_zero() const { if (file != IMM) return false; @@ -733,22 +733,22 @@ backend_reg::is_zero() const assert(type_sz(type) > 1); switch (type) { - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: assert((d & 0xffff) == ((d >> 16) & 0xffff)); return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000; - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: return f == 0; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: return df == 0; - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UW: assert((d & 0xffff) == ((d >> 16) & 0xffff)); return (d & 0xffff) == 0; - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UD: return d == 0; - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_Q: return u64 == 0; default: return false; @@ -756,7 +756,7 @@ backend_reg::is_zero() const } bool -backend_reg::is_one() const +elk_backend_reg::is_one() const { if (file != IMM) return false; @@ -764,22 +764,22 @@ backend_reg::is_one() const assert(type_sz(type) > 1); switch (type) { - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: assert((d & 0xffff) == ((d >> 16) & 0xffff)); return (d & 0xffff) == 0x3c00; - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: return f == 1.0f; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: return df == 1.0; - case BRW_REGISTER_TYPE_W: - case BRW_REGISTER_TYPE_UW: + case ELK_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_UW: assert((d & 0xffff) == ((d >> 16) & 0xffff)); return (d & 0xffff) == 1; - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UD: return d == 1; - case BRW_REGISTER_TYPE_UQ: - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_UQ: + case ELK_REGISTER_TYPE_Q: return u64 == 1; default: return false; @@ -787,7 +787,7 @@ backend_reg::is_one() const } bool -backend_reg::is_negative_one() const +elk_backend_reg::is_negative_one() const { if (file != IMM) return false; @@ -795,19 +795,19 @@ backend_reg::is_negative_one() const assert(type_sz(type) > 1); switch (type) { - case BRW_REGISTER_TYPE_HF: + case ELK_REGISTER_TYPE_HF: assert((d & 0xffff) == ((d >> 16) & 0xffff)); return (d & 0xffff) == 0xbc00; - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: return f == -1.0; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: return df == -1.0; - case BRW_REGISTER_TYPE_W: + case ELK_REGISTER_TYPE_W: assert((d & 0xffff) == ((d >> 16) & 0xffff)); return (d & 0xffff) == 0xffff; - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_D: return d == -1; - case BRW_REGISTER_TYPE_Q: + case ELK_REGISTER_TYPE_Q: return d64 == -1; default: return false; @@ -815,34 +815,34 @@ backend_reg::is_negative_one() const } bool -backend_reg::is_null() const +elk_backend_reg::is_null() const { - return file == ARF && nr == BRW_ARF_NULL; + return file == ARF && nr == ELK_ARF_NULL; } bool -backend_reg::is_accumulator() const +elk_backend_reg::is_accumulator() const { - return file == ARF && nr == BRW_ARF_ACCUMULATOR; + return file == ARF && nr == ELK_ARF_ACCUMULATOR; } bool -backend_instruction::is_commutative() const +elk_backend_instruction::is_commutative() const { switch (opcode) { - case BRW_OPCODE_AND: - case BRW_OPCODE_OR: - case BRW_OPCODE_XOR: - case BRW_OPCODE_ADD: - case BRW_OPCODE_ADD3: - case BRW_OPCODE_MUL: - case SHADER_OPCODE_MULH: + case ELK_OPCODE_AND: + case ELK_OPCODE_OR: + case ELK_OPCODE_XOR: + case ELK_OPCODE_ADD: + case ELK_OPCODE_ADD3: + case ELK_OPCODE_MUL: + case ELK_SHADER_OPCODE_MULH: return true; - case BRW_OPCODE_SEL: + case ELK_OPCODE_SEL: /* MIN and MAX are commutative. */ - if (conditional_mod == BRW_CONDITIONAL_GE || - conditional_mod == BRW_CONDITIONAL_L) { + if (conditional_mod == ELK_CONDITIONAL_GE || + conditional_mod == ELK_CONDITIONAL_L) { return true; } FALLTHROUGH; @@ -852,33 +852,33 @@ backend_instruction::is_commutative() const } bool -backend_instruction::is_3src(const struct brw_compiler *compiler) const +elk_backend_instruction::elk_is_3src(const struct elk_compiler *compiler) const { - return ::is_3src(&compiler->isa, opcode); + return ::elk_is_3src(&compiler->isa, opcode); } bool -backend_instruction::is_math() const +elk_backend_instruction::is_math() const { - return (opcode == SHADER_OPCODE_RCP || - opcode == SHADER_OPCODE_RSQ || - opcode == SHADER_OPCODE_SQRT || - opcode == SHADER_OPCODE_EXP2 || - opcode == SHADER_OPCODE_LOG2 || - opcode == SHADER_OPCODE_SIN || - opcode == SHADER_OPCODE_COS || - opcode == SHADER_OPCODE_INT_QUOTIENT || - opcode == SHADER_OPCODE_INT_REMAINDER || - opcode == SHADER_OPCODE_POW); + return (opcode == ELK_SHADER_OPCODE_RCP || + opcode == ELK_SHADER_OPCODE_RSQ || + opcode == ELK_SHADER_OPCODE_SQRT || + opcode == ELK_SHADER_OPCODE_EXP2 || + opcode == ELK_SHADER_OPCODE_LOG2 || + opcode == ELK_SHADER_OPCODE_SIN || + opcode == ELK_SHADER_OPCODE_COS || + opcode == ELK_SHADER_OPCODE_INT_QUOTIENT || + opcode == ELK_SHADER_OPCODE_INT_REMAINDER || + opcode == ELK_SHADER_OPCODE_POW); } bool -backend_instruction::is_control_flow_begin() const +elk_backend_instruction::is_control_flow_begin() const { switch (opcode) { - case BRW_OPCODE_DO: - case BRW_OPCODE_IF: - case BRW_OPCODE_ELSE: + case ELK_OPCODE_DO: + case ELK_OPCODE_IF: + case ELK_OPCODE_ELSE: return true; default: return false; @@ -886,12 +886,12 @@ backend_instruction::is_control_flow_begin() const } bool -backend_instruction::is_control_flow_end() const +elk_backend_instruction::is_control_flow_end() const { switch (opcode) { - case BRW_OPCODE_ELSE: - case BRW_OPCODE_WHILE: - case BRW_OPCODE_ENDIF: + case ELK_OPCODE_ELSE: + case ELK_OPCODE_WHILE: + case ELK_OPCODE_ENDIF: return true; default: return false; @@ -899,16 +899,16 @@ backend_instruction::is_control_flow_end() const } bool -backend_instruction::is_control_flow() const +elk_backend_instruction::is_control_flow() const { switch (opcode) { - case BRW_OPCODE_DO: - case BRW_OPCODE_WHILE: - case BRW_OPCODE_IF: - case BRW_OPCODE_ELSE: - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_BREAK: - case BRW_OPCODE_CONTINUE: + case ELK_OPCODE_DO: + case ELK_OPCODE_WHILE: + case ELK_OPCODE_IF: + case ELK_OPCODE_ELSE: + case ELK_OPCODE_ENDIF: + case ELK_OPCODE_BREAK: + case ELK_OPCODE_CONTINUE: return true; default: return false; @@ -916,12 +916,12 @@ backend_instruction::is_control_flow() const } bool -backend_instruction::uses_indirect_addressing() const +elk_backend_instruction::uses_indirect_addressing() const { switch (opcode) { - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_CLUSTER_BROADCAST: - case SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: + case ELK_SHADER_OPCODE_MOV_INDIRECT: return true; default: return false; @@ -929,28 +929,28 @@ backend_instruction::uses_indirect_addressing() const } bool -backend_instruction::can_do_source_mods() const +elk_backend_instruction::can_do_source_mods() const { switch (opcode) { - case BRW_OPCODE_ADDC: - case BRW_OPCODE_BFE: - case BRW_OPCODE_BFI1: - case BRW_OPCODE_BFI2: - case BRW_OPCODE_BFREV: - case BRW_OPCODE_CBIT: - case BRW_OPCODE_FBH: - case BRW_OPCODE_FBL: - case BRW_OPCODE_ROL: - case BRW_OPCODE_ROR: - case BRW_OPCODE_SUBB: - case BRW_OPCODE_DP4A: - case BRW_OPCODE_DPAS: - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_CLUSTER_BROADCAST: - case SHADER_OPCODE_MOV_INDIRECT: - case SHADER_OPCODE_SHUFFLE: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_OPCODE_ADDC: + case ELK_OPCODE_BFE: + case ELK_OPCODE_BFI1: + case ELK_OPCODE_BFI2: + case ELK_OPCODE_BFREV: + case ELK_OPCODE_CBIT: + case ELK_OPCODE_FBH: + case ELK_OPCODE_FBL: + case ELK_OPCODE_ROL: + case ELK_OPCODE_ROR: + case ELK_OPCODE_SUBB: + case ELK_OPCODE_DP4A: + case ELK_OPCODE_DPAS: + case ELK_SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: + case ELK_SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_SHUFFLE: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: return false; default: return true; @@ -958,46 +958,46 @@ backend_instruction::can_do_source_mods() const } bool -backend_instruction::can_do_saturate() const +elk_backend_instruction::can_do_saturate() const { switch (opcode) { - case BRW_OPCODE_ADD: - case BRW_OPCODE_ADD3: - case BRW_OPCODE_ASR: - case BRW_OPCODE_AVG: - case BRW_OPCODE_CSEL: - case BRW_OPCODE_DP2: - case BRW_OPCODE_DP3: - case BRW_OPCODE_DP4: - case BRW_OPCODE_DPH: - case BRW_OPCODE_DP4A: - case BRW_OPCODE_F16TO32: - case BRW_OPCODE_F32TO16: - case BRW_OPCODE_LINE: - case BRW_OPCODE_LRP: - case BRW_OPCODE_MAC: - case BRW_OPCODE_MAD: - case BRW_OPCODE_MATH: - case BRW_OPCODE_MOV: - case BRW_OPCODE_MUL: - case SHADER_OPCODE_MULH: - case BRW_OPCODE_PLN: - case BRW_OPCODE_RNDD: - case BRW_OPCODE_RNDE: - case BRW_OPCODE_RNDU: - case BRW_OPCODE_RNDZ: - case BRW_OPCODE_SEL: - case BRW_OPCODE_SHL: - case BRW_OPCODE_SHR: - case FS_OPCODE_LINTERP: - case SHADER_OPCODE_COS: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_POW: - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_SQRT: + case ELK_OPCODE_ADD: + case ELK_OPCODE_ADD3: + case ELK_OPCODE_ASR: + case ELK_OPCODE_AVG: + case ELK_OPCODE_CSEL: + case ELK_OPCODE_DP2: + case ELK_OPCODE_DP3: + case ELK_OPCODE_DP4: + case ELK_OPCODE_DPH: + case ELK_OPCODE_DP4A: + case ELK_OPCODE_F16TO32: + case ELK_OPCODE_F32TO16: + case ELK_OPCODE_LINE: + case ELK_OPCODE_LRP: + case ELK_OPCODE_MAC: + case ELK_OPCODE_MAD: + case ELK_OPCODE_MATH: + case ELK_OPCODE_MOV: + case ELK_OPCODE_MUL: + case ELK_SHADER_OPCODE_MULH: + case ELK_OPCODE_PLN: + case ELK_OPCODE_RNDD: + case ELK_OPCODE_RNDE: + case ELK_OPCODE_RNDU: + case ELK_OPCODE_RNDZ: + case ELK_OPCODE_SEL: + case ELK_OPCODE_SHL: + case ELK_OPCODE_SHR: + case ELK_FS_OPCODE_LINTERP: + case ELK_SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_SQRT: return true; default: return false; @@ -1005,46 +1005,46 @@ backend_instruction::can_do_saturate() const } bool -backend_instruction::can_do_cmod() const +elk_backend_instruction::can_do_cmod() const { switch (opcode) { - case BRW_OPCODE_ADD: - case BRW_OPCODE_ADD3: - case BRW_OPCODE_ADDC: - case BRW_OPCODE_AND: - case BRW_OPCODE_ASR: - case BRW_OPCODE_AVG: - case BRW_OPCODE_CMP: - case BRW_OPCODE_CMPN: - case BRW_OPCODE_DP2: - case BRW_OPCODE_DP3: - case BRW_OPCODE_DP4: - case BRW_OPCODE_DPH: - case BRW_OPCODE_F16TO32: - case BRW_OPCODE_F32TO16: - case BRW_OPCODE_FRC: - case BRW_OPCODE_LINE: - case BRW_OPCODE_LRP: - case BRW_OPCODE_LZD: - case BRW_OPCODE_MAC: - case BRW_OPCODE_MACH: - case BRW_OPCODE_MAD: - case BRW_OPCODE_MOV: - case BRW_OPCODE_MUL: - case BRW_OPCODE_NOT: - case BRW_OPCODE_OR: - case BRW_OPCODE_PLN: - case BRW_OPCODE_RNDD: - case BRW_OPCODE_RNDE: - case BRW_OPCODE_RNDU: - case BRW_OPCODE_RNDZ: - case BRW_OPCODE_SAD2: - case BRW_OPCODE_SADA2: - case BRW_OPCODE_SHL: - case BRW_OPCODE_SHR: - case BRW_OPCODE_SUBB: - case BRW_OPCODE_XOR: - case FS_OPCODE_LINTERP: + case ELK_OPCODE_ADD: + case ELK_OPCODE_ADD3: + case ELK_OPCODE_ADDC: + case ELK_OPCODE_AND: + case ELK_OPCODE_ASR: + case ELK_OPCODE_AVG: + case ELK_OPCODE_CMP: + case ELK_OPCODE_CMPN: + case ELK_OPCODE_DP2: + case ELK_OPCODE_DP3: + case ELK_OPCODE_DP4: + case ELK_OPCODE_DPH: + case ELK_OPCODE_F16TO32: + case ELK_OPCODE_F32TO16: + case ELK_OPCODE_FRC: + case ELK_OPCODE_LINE: + case ELK_OPCODE_LRP: + case ELK_OPCODE_LZD: + case ELK_OPCODE_MAC: + case ELK_OPCODE_MACH: + case ELK_OPCODE_MAD: + case ELK_OPCODE_MOV: + case ELK_OPCODE_MUL: + case ELK_OPCODE_NOT: + case ELK_OPCODE_OR: + case ELK_OPCODE_PLN: + case ELK_OPCODE_RNDD: + case ELK_OPCODE_RNDE: + case ELK_OPCODE_RNDU: + case ELK_OPCODE_RNDZ: + case ELK_OPCODE_SAD2: + case ELK_OPCODE_SADA2: + case ELK_OPCODE_SHL: + case ELK_OPCODE_SHR: + case ELK_OPCODE_SUBB: + case ELK_OPCODE_XOR: + case ELK_FS_OPCODE_LINTERP: return true; default: return false; @@ -1052,12 +1052,12 @@ backend_instruction::can_do_cmod() const } bool -backend_instruction::reads_accumulator_implicitly() const +elk_backend_instruction::reads_accumulator_implicitly() const { switch (opcode) { - case BRW_OPCODE_MAC: - case BRW_OPCODE_MACH: - case BRW_OPCODE_SADA2: + case ELK_OPCODE_MAC: + case ELK_OPCODE_MACH: + case ELK_OPCODE_SADA2: return true; default: return false; @@ -1065,55 +1065,55 @@ backend_instruction::reads_accumulator_implicitly() const } bool -backend_instruction::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const +elk_backend_instruction::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const { return writes_accumulator || (devinfo->ver < 6 && - ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) || - (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) || - (opcode == FS_OPCODE_LINTERP && + ((opcode >= ELK_OPCODE_ADD && opcode < ELK_OPCODE_NOP) || + (opcode >= ELK_FS_OPCODE_DDX_COARSE && opcode <= ELK_FS_OPCODE_LINTERP))) || + (opcode == ELK_FS_OPCODE_LINTERP && (!devinfo->has_pln || devinfo->ver <= 6)) || (eot && intel_needs_workaround(devinfo, 14010017096)); } bool -backend_instruction::has_side_effects() const +elk_backend_instruction::has_side_effects() const { switch (opcode) { - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: return send_has_side_effects; - case BRW_OPCODE_SYNC: - case VEC4_OPCODE_UNTYPED_ATOMIC: - case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: - case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: - case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: - case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: - case SHADER_OPCODE_MEMORY_FENCE: - case SHADER_OPCODE_INTERLOCK: - case SHADER_OPCODE_URB_WRITE_LOGICAL: - case FS_OPCODE_FB_WRITE: - case FS_OPCODE_FB_WRITE_LOGICAL: - case FS_OPCODE_REP_FB_WRITE: - case SHADER_OPCODE_BARRIER: - case VEC4_TCS_OPCODE_URB_WRITE: - case TCS_OPCODE_RELEASE_INPUT: - case SHADER_OPCODE_RND_MODE: - case SHADER_OPCODE_FLOAT_CONTROL_MODE: - case FS_OPCODE_SCHEDULING_FENCE: - case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL: - case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: - case SHADER_OPCODE_BTD_SPAWN_LOGICAL: - case SHADER_OPCODE_BTD_RETIRE_LOGICAL: - case RT_OPCODE_TRACE_RAY_LOGICAL: - case VEC4_OPCODE_ZERO_OOB_PUSH_REGS: + case ELK_OPCODE_SYNC: + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: + case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_MEMORY_FENCE: + case ELK_SHADER_OPCODE_INTERLOCK: + case ELK_SHADER_OPCODE_URB_WRITE_LOGICAL: + case ELK_FS_OPCODE_FB_WRITE: + case ELK_FS_OPCODE_FB_WRITE_LOGICAL: + case ELK_FS_OPCODE_REP_FB_WRITE: + case ELK_SHADER_OPCODE_BARRIER: + case ELK_VEC4_TCS_OPCODE_URB_WRITE: + case ELK_TCS_OPCODE_RELEASE_INPUT: + case ELK_SHADER_OPCODE_RND_MODE: + case ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE: + case ELK_FS_OPCODE_SCHEDULING_FENCE: + case ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL: + case ELK_SHADER_OPCODE_BTD_SPAWN_LOGICAL: + case ELK_SHADER_OPCODE_BTD_RETIRE_LOGICAL: + case ELK_RT_OPCODE_TRACE_RAY_LOGICAL: + case ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS: return true; default: return eot; @@ -1121,20 +1121,20 @@ backend_instruction::has_side_effects() const } bool -backend_instruction::is_volatile() const +elk_backend_instruction::is_volatile() const { switch (opcode) { - case SHADER_OPCODE_SEND: + case ELK_SHADER_OPCODE_SEND: return send_is_volatile; - case VEC4_OPCODE_UNTYPED_SURFACE_READ: - case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: - case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: - case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: - case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: - case VEC4_OPCODE_URB_READ: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ: + case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: + case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: + case ELK_VEC4_OPCODE_URB_READ: return true; default: return false; @@ -1143,12 +1143,12 @@ backend_instruction::is_volatile() const #ifndef NDEBUG static bool -inst_is_in_block(const bblock_t *block, const backend_instruction *inst) +inst_is_in_block(const elk_bblock_t *block, const elk_backend_instruction *inst) { const exec_node *n = inst; /* Find the tail sentinel. If the tail sentinel is the sentinel from the - * list header in the bblock_t, then this instruction is in that basic + * list header in the elk_bblock_t, then this instruction is in that basic * block. */ while (!n->is_tail_sentinel()) @@ -1159,9 +1159,9 @@ inst_is_in_block(const bblock_t *block, const backend_instruction *inst) #endif static void -adjust_later_block_ips(bblock_t *start_block, int ip_adjustment) +adjust_later_block_ips(elk_bblock_t *start_block, int ip_adjustment) { - for (bblock_t *block_iter = start_block->next(); + for (elk_bblock_t *block_iter = start_block->next(); block_iter; block_iter = block_iter->next()) { block_iter->start_ip += ip_adjustment; @@ -1170,7 +1170,7 @@ adjust_later_block_ips(bblock_t *start_block, int ip_adjustment) } void -backend_instruction::insert_after(bblock_t *block, backend_instruction *inst) +elk_backend_instruction::insert_after(elk_bblock_t *block, elk_backend_instruction *inst) { assert(this != inst); assert(block->end_ip_delta == 0); @@ -1186,7 +1186,7 @@ backend_instruction::insert_after(bblock_t *block, backend_instruction *inst) } void -backend_instruction::insert_before(bblock_t *block, backend_instruction *inst) +elk_backend_instruction::insert_before(elk_bblock_t *block, elk_backend_instruction *inst) { assert(this != inst); assert(block->end_ip_delta == 0); @@ -1202,7 +1202,7 @@ backend_instruction::insert_before(bblock_t *block, backend_instruction *inst) } void -backend_instruction::remove(bblock_t *block, bool defer_later_block_ip_updates) +elk_backend_instruction::remove(elk_bblock_t *block, bool defer_later_block_ip_updates) { assert(inst_is_in_block(block, this) || !"Instruction not in block"); @@ -1228,7 +1228,7 @@ backend_instruction::remove(bblock_t *block, bool defer_later_block_ip_updates) } void -backend_shader::dump_instructions(const char *name) const +elk_backend_shader::dump_instructions(const char *name) const { FILE *file = stderr; if (name && __normal_user()) { @@ -1245,18 +1245,18 @@ backend_shader::dump_instructions(const char *name) const } void -backend_shader::dump_instructions_to_file(FILE *file) const +elk_backend_shader::dump_instructions_to_file(FILE *file) const { if (cfg) { int ip = 0; - foreach_block_and_inst(block, backend_instruction, inst, cfg) { + foreach_block_and_inst(block, elk_backend_instruction, inst, cfg) { if (!INTEL_DEBUG(DEBUG_OPTIMIZER)) fprintf(file, "%4d: ", ip++); dump_instruction(inst, file); } } else { int ip = 0; - foreach_in_list(backend_instruction, inst, &instructions) { + foreach_in_list(elk_backend_instruction, inst, &instructions) { if (!INTEL_DEBUG(DEBUG_OPTIMIZER)) fprintf(file, "%4d: ", ip++); dump_instruction(inst, file); @@ -1265,31 +1265,31 @@ backend_shader::dump_instructions_to_file(FILE *file) const } void -backend_shader::calculate_cfg() +elk_backend_shader::calculate_cfg() { if (this->cfg) return; - cfg = new(mem_ctx) cfg_t(this, &this->instructions); + cfg = new(mem_ctx) elk_cfg_t(this, &this->instructions); } void -backend_shader::invalidate_analysis(elk::analysis_dependency_class c) +elk_backend_shader::invalidate_analysis(elk::analysis_dependency_class c) { idom_analysis.invalidate(c); } extern "C" const unsigned * -brw_compile_tes(const struct brw_compiler *compiler, - brw_compile_tes_params *params) +elk_compile_tes(const struct elk_compiler *compiler, + elk_compile_tes_params *params) { const struct intel_device_info *devinfo = compiler->devinfo; nir_shader *nir = params->base.nir; - const struct brw_tes_prog_key *key = params->key; + const struct elk_tes_prog_key *key = params->key; const struct intel_vue_map *input_vue_map = params->input_vue_map; - struct brw_tes_prog_data *prog_data = params->prog_data; + struct elk_tes_prog_data *prog_data = params->prog_data; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL]; - const bool debug_enabled = brw_should_print_shader(nir, DEBUG_TES); + const bool debug_enabled = elk_should_print_shader(nir, DEBUG_TES); const unsigned *assembly; prog_data->base.base.stage = MESA_SHADER_TESS_EVAL; @@ -1298,13 +1298,13 @@ brw_compile_tes(const struct brw_compiler *compiler, nir->info.inputs_read = key->inputs_read; nir->info.patch_inputs_read = key->patch_inputs_read; - brw_nir_apply_key(nir, compiler, &key->base, 8); - brw_nir_lower_tes_inputs(nir, input_vue_map); - brw_nir_lower_vue_outputs(nir); - brw_postprocess_nir(nir, compiler, debug_enabled, + elk_nir_apply_key(nir, compiler, &key->base, 8); + elk_nir_lower_tes_inputs(nir, input_vue_map); + elk_nir_lower_vue_outputs(nir); + elk_postprocess_nir(nir, compiler, debug_enabled, key->base.robust_flags); - brw_compute_vue_map(devinfo, &prog_data->base.vue_map, + elk_compute_vue_map(devinfo, &prog_data->base.vue_map, nir->info.outputs_written, nir->info.separate_shader, 1); @@ -1367,15 +1367,15 @@ brw_compile_tes(const struct brw_compiler *compiler, if (unlikely(debug_enabled)) { fprintf(stderr, "TES Input "); - brw_print_vue_map(stderr, input_vue_map, MESA_SHADER_TESS_EVAL); + elk_print_vue_map(stderr, input_vue_map, MESA_SHADER_TESS_EVAL); fprintf(stderr, "TES Output "); - brw_print_vue_map(stderr, &prog_data->base.vue_map, + elk_print_vue_map(stderr, &prog_data->base.vue_map, MESA_SHADER_TESS_EVAL); } if (is_scalar) { const unsigned dispatch_width = devinfo->ver >= 20 ? 16 : 8; - fs_visitor v(compiler, ¶ms->base, &key->base, + elk_fs_visitor v(compiler, ¶ms->base, &key->base, &prog_data->base.base, nir, dispatch_width, params->base.stats != NULL, debug_enabled); if (!v.run_tes()) { @@ -1389,7 +1389,7 @@ brw_compile_tes(const struct brw_compiler *compiler, prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8; - fs_generator g(compiler, ¶ms->base, + elk_fs_generator g(compiler, ¶ms->base, &prog_data->base.base, false, MESA_SHADER_TESS_EVAL); if (unlikely(debug_enabled)) { g.enable_debug(ralloc_asprintf(params->base.mem_ctx, @@ -1417,7 +1417,7 @@ brw_compile_tes(const struct brw_compiler *compiler, if (unlikely(debug_enabled)) v.dump_instructions(); - assembly = brw_vec4_generate_assembly(compiler, ¶ms->base, nir, + assembly = elk_vec4_generate_assembly(compiler, ¶ms->base, nir, &prog_data->base, v.cfg, v.performance_analysis.require(), debug_enabled); diff --git a/src/intel/compiler/elk/elk_shader.h b/src/intel/compiler/elk/elk_shader.h index f613af7744c..ed229220136 100644 --- a/src/intel/compiler/elk/elk_shader.h +++ b/src/intel/compiler/elk/elk_shader.h @@ -43,47 +43,47 @@ enum instruction_scheduler_mode { #define UBO_START ((1 << 16) - 4) -struct backend_shader { +struct elk_backend_shader { protected: - backend_shader(const struct brw_compiler *compiler, - const struct brw_compile_params *params, + elk_backend_shader(const struct elk_compiler *compiler, + const struct elk_compile_params *params, const nir_shader *shader, - struct brw_stage_prog_data *stage_prog_data, + struct elk_stage_prog_data *stage_prog_data, bool debug_enabled); public: - virtual ~backend_shader(); + virtual ~elk_backend_shader(); - const struct brw_compiler *compiler; + const struct elk_compiler *compiler; void *log_data; /* Passed to compiler->*_log functions */ const struct intel_device_info * const devinfo; const nir_shader *nir; - struct brw_stage_prog_data * const stage_prog_data; + struct elk_stage_prog_data * const stage_prog_data; /** ralloc context for temporary data used during compile */ void *mem_ctx; /** - * List of either fs_inst or vec4_instruction (inheriting from - * backend_instruction) + * List of either elk_fs_inst or vec4_instruction (inheriting from + * elk_backend_instruction) */ exec_list instructions; - cfg_t *cfg; - brw_analysis idom_analysis; + elk_cfg_t *cfg; + elk_analysis idom_analysis; gl_shader_stage stage; bool debug_enabled; elk::simple_allocator alloc; - virtual void dump_instruction_to_file(const backend_instruction *inst, FILE *file) const = 0; + virtual void dump_instruction_to_file(const elk_backend_instruction *inst, FILE *file) const = 0; virtual void dump_instructions_to_file(FILE *file) const; /* Convenience functions based on the above. */ - void dump_instruction(const backend_instruction *inst, FILE *file = stderr) const { + void dump_instruction(const elk_backend_instruction *inst, FILE *file = stderr) const { dump_instruction_to_file(inst, file); } void dump_instructions(const char *name = nullptr) const; @@ -94,43 +94,43 @@ public: }; #else -struct backend_shader; +struct elk_backend_shader; #endif /* __cplusplus */ -enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type); -uint32_t brw_math_function(enum opcode op); -const char *brw_instruction_name(const struct brw_isa_info *isa, - enum opcode op); -bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg); -bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg); -bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg); +enum elk_reg_type elk_type_for_base_type(const struct glsl_type *type); +uint32_t elk_math_function(enum elk_opcode op); +const char *elk_instruction_name(const struct elk_isa_info *isa, + enum elk_opcode op); +bool elk_saturate_immediate(enum elk_reg_type type, struct elk_reg *reg); +bool elk_negate_immediate(enum elk_reg_type type, struct elk_reg *reg); +bool elk_abs_immediate(enum elk_reg_type type, struct elk_reg *reg); -bool opt_predicated_break(struct backend_shader *s); +bool elk_opt_predicated_break(struct elk_backend_shader *s); #ifdef __cplusplus extern "C" { #endif -/* brw_fs_reg_allocate.cpp */ -void brw_fs_alloc_reg_sets(struct brw_compiler *compiler); +/* elk_fs_reg_allocate.cpp */ +void elk_fs_alloc_reg_sets(struct elk_compiler *compiler); -/* brw_vec4_reg_allocate.cpp */ -void brw_vec4_alloc_reg_set(struct brw_compiler *compiler); +/* elk_vec4_reg_allocate.cpp */ +void elk_vec4_alloc_reg_set(struct elk_compiler *compiler); -/* brw_disasm.c */ -extern const char *const conditional_modifier[16]; -extern const char *const pred_ctrl_align16[16]; +/* elk_disasm.c */ +extern const char *const elk_conditional_modifier[16]; +extern const char *const elk_pred_ctrl_align16[16]; /* Per-thread scratch space is a power-of-two multiple of 1KB. */ static inline unsigned -brw_get_scratch_size(int size) +elk_get_scratch_size(int size) { return MAX2(1024, util_next_power_of_two(size)); } static inline nir_variable_mode -brw_nir_no_indirect_mask(const struct brw_compiler *compiler, +elk_nir_no_indirect_mask(const struct elk_compiler *compiler, gl_shader_stage stage) { const struct intel_device_info *devinfo = compiler->devinfo; @@ -158,7 +158,7 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler, /* On HSW+, we allow indirects in scalar shaders. They get implemented * using nir_lower_vars_to_explicit_types and nir_lower_explicit_io in - * brw_postprocess_nir. + * elk_postprocess_nir. * * We haven't plumbed through the indirect scratch messages on gfx6 or * earlier so doing indirects via scratch doesn't work there. On gfx7 and @@ -172,15 +172,15 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler, return indirect_mask; } -bool brw_texture_offset(const nir_tex_instr *tex, unsigned src, +bool elk_texture_offset(const nir_tex_instr *tex, unsigned src, uint32_t *offset_bits); /** * Scratch data used when compiling a GLSL geometry shader. */ -struct brw_gs_compile +struct elk_gs_compile { - struct brw_gs_prog_key key; + struct elk_gs_prog_key key; struct intel_vue_map input_vue_map; unsigned control_data_bits_per_vertex; diff --git a/src/intel/compiler/elk/elk_simd_selection.cpp b/src/intel/compiler/elk/elk_simd_selection.cpp index 30a87a8759d..ad71f02a69a 100644 --- a/src/intel/compiler/elk/elk_simd_selection.cpp +++ b/src/intel/compiler/elk/elk_simd_selection.cpp @@ -28,7 +28,7 @@ #include "util/ralloc.h" unsigned -brw_required_dispatch_width(const struct shader_info *info) +elk_required_dispatch_width(const struct shader_info *info) { if ((int)info->subgroup_size >= (int)SUBGROUP_SIZE_REQUIRE_8) { assert(gl_shader_stage_uses_workgroup(info->stage)); @@ -48,20 +48,20 @@ test_bit(unsigned mask, unsigned bit) { namespace { -struct brw_cs_prog_data * -get_cs_prog_data(brw_simd_selection_state &state) +struct elk_cs_prog_data * +get_cs_prog_data(elk_simd_selection_state &state) { - if (std::holds_alternative(state.prog_data)) - return std::get(state.prog_data); + if (std::holds_alternative(state.prog_data)) + return std::get(state.prog_data); else return nullptr; } -struct brw_stage_prog_data * -get_prog_data(brw_simd_selection_state &state) +struct elk_stage_prog_data * +get_prog_data(elk_simd_selection_state &state) { - if (std::holds_alternative(state.prog_data)) - return &std::get(state.prog_data)->base; + if (std::holds_alternative(state.prog_data)) + return &std::get(state.prog_data)->base; else return nullptr; } @@ -69,7 +69,7 @@ get_prog_data(brw_simd_selection_state &state) } bool -brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd) +elk_simd_should_compile(elk_simd_selection_state &state, unsigned simd) { assert(simd < SIMD_COUNT); assert(!state.compiled[simd]); @@ -148,7 +148,7 @@ brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd) start = DEBUG_CS_SIMD8; break; default: - unreachable("unknown shader stage in brw_simd_should_compile"); + unreachable("unknown shader stage in elk_simd_should_compile"); } const bool env_skip[] = { @@ -168,7 +168,7 @@ brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd) } void -brw_simd_mark_compiled(brw_simd_selection_state &state, unsigned simd, bool spilled) +elk_simd_mark_compiled(elk_simd_selection_state &state, unsigned simd, bool spilled) { assert(simd < SIMD_COUNT); assert(!state.compiled[simd]); @@ -190,7 +190,7 @@ brw_simd_mark_compiled(brw_simd_selection_state &state, unsigned simd, bool spil } int -brw_simd_select(const struct brw_simd_selection_state &state) +elk_simd_select(const struct elk_simd_selection_state &state) { for (int i = SIMD_COUNT - 1; i >= 0; i--) { if (state.compiled[i] && !state.spilled[i]) @@ -204,15 +204,15 @@ brw_simd_select(const struct brw_simd_selection_state &state) } int -brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo, - const struct brw_cs_prog_data *prog_data, +elk_simd_select_for_workgroup_size(const struct intel_device_info *devinfo, + const struct elk_cs_prog_data *prog_data, const unsigned *sizes) { if (!sizes || (prog_data->local_size[0] == sizes[0] && prog_data->local_size[1] == sizes[1] && prog_data->local_size[2] == sizes[2])) { - brw_simd_selection_state simd_state{ - .prog_data = const_cast(prog_data), + elk_simd_selection_state simd_state{ + .prog_data = const_cast(prog_data), }; /* Propagate the prog_data information back to the simd_state, @@ -223,17 +223,17 @@ brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo, simd_state.spilled[i] = test_bit(prog_data->prog_spilled, i); } - return brw_simd_select(simd_state); + return elk_simd_select(simd_state); } - struct brw_cs_prog_data cloned = *prog_data; + struct elk_cs_prog_data cloned = *prog_data; for (unsigned i = 0; i < 3; i++) cloned.local_size[i] = sizes[i]; cloned.prog_mask = 0; cloned.prog_spilled = 0; - brw_simd_selection_state simd_state{ + elk_simd_selection_state simd_state{ .devinfo = devinfo, .prog_data = &cloned, }; @@ -242,11 +242,11 @@ brw_simd_select_for_workgroup_size(const struct intel_device_info *devinfo, /* We are not recompiling, so use original results of prog_mask and * prog_spilled as they will already contain all possible compilations. */ - if (brw_simd_should_compile(simd_state, simd) && + if (elk_simd_should_compile(simd_state, simd) && test_bit(prog_data->prog_mask, simd)) { - brw_simd_mark_compiled(simd_state, simd, test_bit(prog_data->prog_spilled, simd)); + elk_simd_mark_compiled(simd_state, simd, test_bit(prog_data->prog_spilled, simd)); } } - return brw_simd_select(simd_state); + return elk_simd_select(simd_state); } diff --git a/src/intel/compiler/elk/elk_test_eu_compact.cpp b/src/intel/compiler/elk/elk_test_eu_compact.cpp index 09c760cac9e..6e529e56b89 100644 --- a/src/intel/compiler/elk/elk_test_eu_compact.cpp +++ b/src/intel/compiler/elk/elk_test_eu_compact.cpp @@ -42,10 +42,10 @@ get_compact_params_name(const testing::TestParamInfo p) std::stringstream ss; ss << params.verx10 << "_"; switch (params.align) { - case BRW_ALIGN_1: + case ELK_ALIGN_1: ss << "Align_1"; break; - case BRW_ALIGN_16: + case ELK_ALIGN_16: ss << "Align_16"; break; default: @@ -55,27 +55,27 @@ get_compact_params_name(const testing::TestParamInfo p) } static bool -test_compact_instruction(struct brw_codegen *p, brw_inst src) +test_compact_instruction(struct elk_codegen *p, elk_inst src) { - brw_compact_inst dst; + elk_compact_inst dst; memset(&dst, 0xd0, sizeof(dst)); - if (brw_try_compact_instruction(p->isa, &dst, &src)) { - brw_inst uncompacted; + if (elk_try_compact_instruction(p->isa, &dst, &src)) { + elk_inst uncompacted; - brw_uncompact_instruction(p->isa, &uncompacted, &dst); + elk_uncompact_instruction(p->isa, &uncompacted, &dst); if (memcmp(&uncompacted, &src, sizeof(src))) { - brw_debug_compact_uncompact(p->isa, &src, &uncompacted); + elk_debug_compact_uncompact(p->isa, &src, &uncompacted); return false; } } else { - brw_compact_inst unchanged; + elk_compact_inst unchanged; memset(&unchanged, 0xd0, sizeof(unchanged)); /* It's not supposed to change dst unless it compacted. */ if (memcmp(&unchanged, &dst, sizeof(dst))) { fprintf(stderr, "Failed to compact, but dst changed\n"); fprintf(stderr, " Instruction: "); - brw_disassemble_inst(stderr, p->isa, &src, false, 0, NULL); + elk_disassemble_inst(stderr, p->isa, &src, false, 0, NULL); return false; } } @@ -91,27 +91,27 @@ test_compact_instruction(struct brw_codegen *p, brw_inst src) * become meaningless once fuzzing twiddles a related bit. */ static void -clear_pad_bits(const struct brw_isa_info *isa, brw_inst *inst) +clear_pad_bits(const struct elk_isa_info *isa, elk_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; - if (brw_inst_opcode(isa, inst) != BRW_OPCODE_SEND && - brw_inst_opcode(isa, inst) != BRW_OPCODE_SENDC && - brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && - brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) { - brw_inst_set_bits(inst, 127, 111, 0); + if (elk_inst_opcode(isa, inst) != ELK_OPCODE_SEND && + elk_inst_opcode(isa, inst) != ELK_OPCODE_SENDC && + elk_inst_src0_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE && + elk_inst_src1_reg_file(devinfo, inst) != ELK_IMMEDIATE_VALUE) { + elk_inst_set_bits(inst, 127, 111, 0); } if (devinfo->ver == 8 && devinfo->platform != INTEL_PLATFORM_CHV && - is_3src(isa, brw_inst_opcode(isa, inst))) { - brw_inst_set_bits(inst, 105, 105, 0); - brw_inst_set_bits(inst, 84, 84, 0); - brw_inst_set_bits(inst, 36, 35, 0); + elk_is_3src(isa, elk_inst_opcode(isa, inst))) { + elk_inst_set_bits(inst, 105, 105, 0); + elk_inst_set_bits(inst, 84, 84, 0); + elk_inst_set_bits(inst, 36, 35, 0); } } static bool -skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit) +skip_bit(const struct elk_isa_info *isa, elk_inst *src, int bit) { const struct intel_device_info *devinfo = isa->devinfo; @@ -123,7 +123,7 @@ skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit) if (bit == 29) return true; - if (is_3src(isa, brw_inst_opcode(isa, src))) { + if (elk_is_3src(isa, elk_inst_opcode(isa, src))) { if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { if (bit == 127) return true; @@ -160,10 +160,10 @@ skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit) } /* sometimes these are pad bits. */ - if (brw_inst_opcode(isa, src) != BRW_OPCODE_SEND && - brw_inst_opcode(isa, src) != BRW_OPCODE_SENDC && - brw_inst_src0_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE && - brw_inst_src1_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE && + if (elk_inst_opcode(isa, src) != ELK_OPCODE_SEND && + elk_inst_opcode(isa, src) != ELK_OPCODE_SENDC && + elk_inst_src0_reg_file(devinfo, src) != ELK_IMMEDIATE_VALUE && + elk_inst_src1_reg_file(devinfo, src) != ELK_IMMEDIATE_VALUE && bit >= 121) { return true; } @@ -172,14 +172,14 @@ skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit) } static bool -test_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src) +test_fuzz_compact_instruction(struct elk_codegen *p, elk_inst src) { for (int bit0 = 0; bit0 < 128; bit0++) { if (skip_bit(p->isa, &src, bit0)) continue; for (int bit1 = 0; bit1 < 128; bit1++) { - brw_inst instr = src; + elk_inst instr = src; uint64_t *bits = instr.data; if (skip_bit(p->isa, &src, bit1)) @@ -190,7 +190,7 @@ test_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src) clear_pad_bits(p->isa, &instr); - if (!brw_validate_instruction(p->isa, &instr, 0, sizeof(brw_inst), NULL)) + if (!elk_validate_instruction(p->isa, &instr, 0, sizeof(elk_inst), NULL)) continue; if (!test_compact_instruction(p, instr)) { @@ -209,15 +209,15 @@ protected: CompactParams params = GetParam(); mem_ctx = ralloc_context(NULL); devinfo = rzalloc(mem_ctx, intel_device_info); - p = rzalloc(mem_ctx, brw_codegen); + p = rzalloc(mem_ctx, elk_codegen); devinfo->verx10 = params.verx10; devinfo->ver = devinfo->verx10 / 10; - brw_init_isa_info(&isa, devinfo); - brw_init_codegen(&isa, p, p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_access_mode(p, params.align); + elk_init_isa_info(&isa, devinfo); + elk_init_codegen(&isa, p, p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_access_mode(p, params.align); }; virtual void TearDown() { @@ -229,9 +229,9 @@ protected: }; void *mem_ctx; - struct brw_isa_info isa; + struct elk_isa_info isa; intel_device_info *devinfo; - brw_codegen *p; + elk_codegen *p; }; class Instructions : public CompactTestFixture {}; @@ -240,15 +240,15 @@ INSTANTIATE_TEST_SUITE_P( CompactTest, Instructions, testing::Values( - CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 }, - CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 }, - CompactParams{ 70, BRW_ALIGN_1 }, CompactParams{ 70, BRW_ALIGN_16 }, - CompactParams{ 75, BRW_ALIGN_1 }, CompactParams{ 75, BRW_ALIGN_16 }, - CompactParams{ 80, BRW_ALIGN_1 }, CompactParams{ 80, BRW_ALIGN_16 }, - CompactParams{ 90, BRW_ALIGN_1 }, CompactParams{ 90, BRW_ALIGN_16 }, - CompactParams{ 110, BRW_ALIGN_1 }, - CompactParams{ 120, BRW_ALIGN_1 }, - CompactParams{ 125, BRW_ALIGN_1 } + CompactParams{ 50, ELK_ALIGN_1 }, CompactParams{ 50, ELK_ALIGN_16 }, + CompactParams{ 60, ELK_ALIGN_1 }, CompactParams{ 60, ELK_ALIGN_16 }, + CompactParams{ 70, ELK_ALIGN_1 }, CompactParams{ 70, ELK_ALIGN_16 }, + CompactParams{ 75, ELK_ALIGN_1 }, CompactParams{ 75, ELK_ALIGN_16 }, + CompactParams{ 80, ELK_ALIGN_1 }, CompactParams{ 80, ELK_ALIGN_16 }, + CompactParams{ 90, ELK_ALIGN_1 }, CompactParams{ 90, ELK_ALIGN_16 }, + CompactParams{ 110, ELK_ALIGN_1 }, + CompactParams{ 120, ELK_ALIGN_1 }, + CompactParams{ 125, ELK_ALIGN_1 } ), get_compact_params_name); @@ -258,81 +258,81 @@ INSTANTIATE_TEST_SUITE_P( CompactTest, InstructionsBeforeIvyBridge, testing::Values( - CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 }, - CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 } + CompactParams{ 50, ELK_ALIGN_1 }, CompactParams{ 50, ELK_ALIGN_16 }, + CompactParams{ 60, ELK_ALIGN_1 }, CompactParams{ 60, ELK_ALIGN_16 } ), get_compact_params_name); TEST_P(Instructions, ADD_GRF_GRF_GRF) { - struct brw_reg g0 = brw_vec8_grf(0, 0); - struct brw_reg g2 = brw_vec8_grf(2, 0); - struct brw_reg g4 = brw_vec8_grf(4, 0); + struct elk_reg g0 = elk_vec8_grf(0, 0); + struct elk_reg g2 = elk_vec8_grf(2, 0); + struct elk_reg g4 = elk_vec8_grf(4, 0); - brw_ADD(p, g0, g2, g4); + elk_ADD(p, g0, g2, g4); } TEST_P(Instructions, ADD_GRF_GRF_IMM) { - struct brw_reg g0 = brw_vec8_grf(0, 0); - struct brw_reg g2 = brw_vec8_grf(2, 0); + struct elk_reg g0 = elk_vec8_grf(0, 0); + struct elk_reg g2 = elk_vec8_grf(2, 0); - brw_ADD(p, g0, g2, brw_imm_f(1.0)); + elk_ADD(p, g0, g2, elk_imm_f(1.0)); } TEST_P(Instructions, ADD_GRF_GRF_IMM_d) { - struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D); - struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D); + struct elk_reg g0 = retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_D); + struct elk_reg g2 = retype(elk_vec8_grf(2, 0), ELK_REGISTER_TYPE_D); - brw_ADD(p, g0, g2, brw_imm_d(1)); + elk_ADD(p, g0, g2, elk_imm_d(1)); } TEST_P(Instructions, MOV_GRF_GRF) { - struct brw_reg g0 = brw_vec8_grf(0, 0); - struct brw_reg g2 = brw_vec8_grf(2, 0); + struct elk_reg g0 = elk_vec8_grf(0, 0); + struct elk_reg g2 = elk_vec8_grf(2, 0); - brw_MOV(p, g0, g2); + elk_MOV(p, g0, g2); } TEST_P(InstructionsBeforeIvyBridge, ADD_MRF_GRF_GRF) { - struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0); - struct brw_reg g2 = brw_vec8_grf(2, 0); - struct brw_reg g4 = brw_vec8_grf(4, 0); + struct elk_reg m6 = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 6, 0); + struct elk_reg g2 = elk_vec8_grf(2, 0); + struct elk_reg g4 = elk_vec8_grf(4, 0); - brw_ADD(p, m6, g2, g4); + elk_ADD(p, m6, g2, g4); } TEST_P(Instructions, ADD_vec1_GRF_GRF_GRF) { - struct brw_reg g0 = brw_vec1_grf(0, 0); - struct brw_reg g2 = brw_vec1_grf(2, 0); - struct brw_reg g4 = brw_vec1_grf(4, 0); + struct elk_reg g0 = elk_vec1_grf(0, 0); + struct elk_reg g2 = elk_vec1_grf(2, 0); + struct elk_reg g4 = elk_vec1_grf(4, 0); - brw_ADD(p, g0, g2, g4); + elk_ADD(p, g0, g2, g4); } TEST_P(InstructionsBeforeIvyBridge, PLN_MRF_GRF_GRF) { - struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0); - struct brw_reg interp = brw_vec1_grf(2, 0); - struct brw_reg g4 = brw_vec8_grf(4, 0); + struct elk_reg m6 = elk_vec8_reg(ELK_MESSAGE_REGISTER_FILE, 6, 0); + struct elk_reg interp = elk_vec1_grf(2, 0); + struct elk_reg g4 = elk_vec8_grf(4, 0); - brw_PLN(p, m6, interp, g4); + elk_PLN(p, m6, interp, g4); } TEST_P(Instructions, f0_0_MOV_GRF_GRF) { - struct brw_reg g0 = brw_vec8_grf(0, 0); - struct brw_reg g2 = brw_vec8_grf(2, 0); + struct elk_reg g0 = elk_vec8_grf(0, 0); + struct elk_reg g2 = elk_vec8_grf(2, 0); - brw_push_insn_state(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); - brw_MOV(p, g0, g2); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL); + elk_MOV(p, g0, g2); + elk_pop_insn_state(p); } /* The handling of f0.1 vs f0.0 changes between gfx6 and gfx7. Explicitly test @@ -341,12 +341,12 @@ TEST_P(Instructions, f0_0_MOV_GRF_GRF) */ TEST_P(Instructions, f0_1_MOV_GRF_GRF) { - struct brw_reg g0 = brw_vec8_grf(0, 0); - struct brw_reg g2 = brw_vec8_grf(2, 0); + struct elk_reg g0 = elk_vec8_grf(0, 0); + struct elk_reg g2 = elk_vec8_grf(2, 0); - brw_push_insn_state(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); - brw_inst *mov = brw_MOV(p, g0, g2); - brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NORMAL); + elk_inst *mov = elk_MOV(p, g0, g2); + elk_inst_set_flag_subreg_nr(p->devinfo, mov, 1); + elk_pop_insn_state(p); } diff --git a/src/intel/compiler/elk/elk_test_eu_validate.cpp b/src/intel/compiler/elk/elk_test_eu_validate.cpp index 39743e8f4cd..00f87e79ebb 100644 --- a/src/intel/compiler/elk/elk_test_eu_validate.cpp +++ b/src/intel/compiler/elk/elk_test_eu_validate.cpp @@ -68,14 +68,14 @@ public: validation_test(); virtual ~validation_test(); - struct brw_isa_info isa; - struct brw_codegen *p; + struct elk_isa_info isa; + struct elk_codegen *p; struct intel_device_info devinfo; }; validation_test::validation_test() { - p = rzalloc(NULL, struct brw_codegen); + p = rzalloc(NULL, struct elk_codegen); memset(&devinfo, 0, sizeof(devinfo)); } @@ -91,9 +91,9 @@ void validation_test::SetUp() intel_get_device_info_from_pci_id(devid, &devinfo); - brw_init_isa_info(&isa, &devinfo); + elk_init_isa_info(&isa, &devinfo); - brw_init_codegen(&isa, p, p); + elk_init_codegen(&isa, p, p); } struct gfx_name { @@ -111,21 +111,21 @@ INSTANTIATE_TEST_SUITE_P( ); static bool -validate(struct brw_codegen *p) +validate(struct elk_codegen *p) { const bool print = getenv("TEST_DEBUG"); - struct disasm_info *disasm = disasm_initialize(p->isa, NULL); + struct elk_disasm_info *disasm = elk_disasm_initialize(p->isa, NULL); if (print) { - disasm_new_inst_group(disasm, 0); - disasm_new_inst_group(disasm, p->next_insn_offset); + elk_disasm_new_inst_group(disasm, 0); + elk_disasm_new_inst_group(disasm, p->next_insn_offset); } - bool ret = brw_validate_instructions(p->isa, p->store, 0, + bool ret = elk_validate_instructions(p->isa, p->store, 0, p->next_insn_offset, disasm); if (print) { - dump_assembly(p->store, 0, p->next_insn_offset, disasm, NULL); + elk_dump_assembly(p->store, 0, p->next_insn_offset, disasm, NULL); } ralloc_free(disasm); @@ -133,13 +133,13 @@ validate(struct brw_codegen *p) } #define last_inst (&p->store[p->nr_insn - 1]) -#define g0 brw_vec8_grf(0, 0) -#define acc0 brw_acc_reg(8) -#define null brw_null_reg() -#define zero brw_imm_f(0.0f) +#define g0 elk_vec8_grf(0, 0) +#define acc0 elk_acc_reg(8) +#define null elk_null_reg() +#define zero elk_imm_f(0.0f) static void -clear_instructions(struct brw_codegen *p) +clear_instructions(struct elk_codegen *p) { p->next_insn_offset = 0; p->nr_insn = 0; @@ -147,21 +147,21 @@ clear_instructions(struct brw_codegen *p) TEST_P(validation_test, sanity) { - brw_ADD(p, g0, g0, g0); + elk_ADD(p, g0, g0, g0); EXPECT_TRUE(validate(p)); } TEST_P(validation_test, src0_null_reg) { - brw_MOV(p, g0, null); + elk_MOV(p, g0, null); EXPECT_FALSE(validate(p)); } TEST_P(validation_test, src1_null_reg) { - brw_ADD(p, g0, g0, null); + elk_ADD(p, g0, g0, null); EXPECT_FALSE(validate(p)); } @@ -169,9 +169,9 @@ TEST_P(validation_test, src1_null_reg) TEST_P(validation_test, math_src0_null_reg) { if (devinfo.ver >= 6) { - gfx6_math(p, g0, BRW_MATH_FUNCTION_SIN, null, null); + elk_gfx6_math(p, g0, ELK_MATH_FUNCTION_SIN, null, null); } else { - gfx4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, null, BRW_MATH_PRECISION_FULL); + elk_gfx4_math(p, g0, ELK_MATH_FUNCTION_SIN, 0, null, ELK_MATH_PRECISION_FULL); } EXPECT_FALSE(validate(p)); @@ -180,11 +180,11 @@ TEST_P(validation_test, math_src0_null_reg) TEST_P(validation_test, math_src1_null_reg) { if (devinfo.ver >= 6) { - gfx6_math(p, g0, BRW_MATH_FUNCTION_POW, g0, null); + elk_gfx6_math(p, g0, ELK_MATH_FUNCTION_POW, g0, null); EXPECT_FALSE(validate(p)); } else { /* Math instructions on Gfx4/5 are actually SEND messages with payloads. - * src1 is an immediate message descriptor set by gfx4_math. + * src1 is an immediate message descriptor set by elk_gfx4_math. */ } } @@ -196,7 +196,7 @@ TEST_P(validation_test, opcode46) * reserved on Gen 7 * "goto" on Gfx8+ */ - brw_next_insn(p, brw_opcode_decode(&isa, 46)); + elk_next_insn(p, elk_opcode_decode(&isa, 46)); if (devinfo.ver == 7) { EXPECT_FALSE(validate(p)); @@ -208,35 +208,35 @@ TEST_P(validation_test, opcode46) TEST_P(validation_test, invalid_exec_size_encoding) { const struct { - enum brw_execution_size exec_size; + enum elk_execution_size exec_size; bool expected_result; } test_case[] = { - { BRW_EXECUTE_1, true }, - { BRW_EXECUTE_2, true }, - { BRW_EXECUTE_4, true }, - { BRW_EXECUTE_8, true }, - { BRW_EXECUTE_16, true }, - { BRW_EXECUTE_32, true }, + { ELK_EXECUTE_1, true }, + { ELK_EXECUTE_2, true }, + { ELK_EXECUTE_4, true }, + { ELK_EXECUTE_8, true }, + { ELK_EXECUTE_16, true }, + { ELK_EXECUTE_32, true }, - { (enum brw_execution_size)((int)BRW_EXECUTE_32 + 1), false }, - { (enum brw_execution_size)((int)BRW_EXECUTE_32 + 2), false }, + { (enum elk_execution_size)((int)ELK_EXECUTE_32 + 1), false }, + { (enum elk_execution_size)((int)ELK_EXECUTE_32 + 2), false }, }; for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) { - brw_MOV(p, g0, g0); + elk_MOV(p, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, test_case[i].exec_size); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); + elk_inst_set_exec_size(&devinfo, last_inst, test_case[i].exec_size); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); - if (test_case[i].exec_size == BRW_EXECUTE_1) { - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); + if (test_case[i].exec_size == ELK_EXECUTE_1) { + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_0); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); } else { - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_2); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_2); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); } EXPECT_EQ(test_case[i].expected_result, validate(p)); @@ -251,8 +251,8 @@ TEST_P(validation_test, invalid_file_encoding) if (devinfo.ver >= 12) return; - brw_MOV(p, g0, g0); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_MESSAGE_REGISTER_FILE, BRW_REGISTER_TYPE_F); + elk_MOV(p, g0, g0); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_MESSAGE_REGISTER_FILE, ELK_REGISTER_TYPE_F); if (devinfo.ver > 6) { EXPECT_FALSE(validate(p)); @@ -263,11 +263,11 @@ TEST_P(validation_test, invalid_file_encoding) clear_instructions(p); if (devinfo.ver < 6) { - gfx4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, g0, BRW_MATH_PRECISION_FULL); + elk_gfx4_math(p, g0, ELK_MATH_FUNCTION_SIN, 0, g0, ELK_MATH_PRECISION_FULL); } else { - gfx6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); + elk_gfx6_math(p, g0, ELK_MATH_FUNCTION_SIN, g0, null); } - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_MESSAGE_REGISTER_FILE, BRW_REGISTER_TYPE_F); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_MESSAGE_REGISTER_FILE, ELK_REGISTER_TYPE_F); if (devinfo.ver > 6) { EXPECT_FALSE(validate(p)); @@ -278,13 +278,13 @@ TEST_P(validation_test, invalid_file_encoding) TEST_P(validation_test, invalid_type_encoding) { - enum brw_reg_file files[2] = { - BRW_GENERAL_REGISTER_FILE, - BRW_IMMEDIATE_VALUE, + enum elk_reg_file files[2] = { + ELK_GENERAL_REGISTER_FILE, + ELK_IMMEDIATE_VALUE, }; for (unsigned i = 0; i < ARRAY_SIZE(files); i++) { - const enum brw_reg_file file = files[i]; + const enum elk_reg_file file = files[i]; const int num_bits = devinfo.ver >= 8 ? 4 : 3; const int num_encodings = 1 << num_bits; @@ -295,34 +295,34 @@ TEST_P(validation_test, invalid_type_encoding) BITSET_DECLARE(invalid_encodings, num_encodings); const struct { - enum brw_reg_type type; + enum elk_reg_type type; bool expected_result; } test_case[] = { - { BRW_REGISTER_TYPE_NF, devinfo.ver == 11 && file != IMM }, - { BRW_REGISTER_TYPE_DF, devinfo.has_64bit_float && (devinfo.ver >= 8 || file != IMM) }, - { BRW_REGISTER_TYPE_F, true }, - { BRW_REGISTER_TYPE_HF, devinfo.ver >= 8 }, - { BRW_REGISTER_TYPE_VF, file == IMM }, - { BRW_REGISTER_TYPE_Q, devinfo.has_64bit_int }, - { BRW_REGISTER_TYPE_UQ, devinfo.has_64bit_int }, - { BRW_REGISTER_TYPE_D, true }, - { BRW_REGISTER_TYPE_UD, true }, - { BRW_REGISTER_TYPE_W, true }, - { BRW_REGISTER_TYPE_UW, true }, - { BRW_REGISTER_TYPE_B, file == FIXED_GRF }, - { BRW_REGISTER_TYPE_UB, file == FIXED_GRF }, - { BRW_REGISTER_TYPE_V, file == IMM }, - { BRW_REGISTER_TYPE_UV, devinfo.ver >= 6 && file == IMM }, + { ELK_REGISTER_TYPE_NF, devinfo.ver == 11 && file != IMM }, + { ELK_REGISTER_TYPE_DF, devinfo.has_64bit_float && (devinfo.ver >= 8 || file != IMM) }, + { ELK_REGISTER_TYPE_F, true }, + { ELK_REGISTER_TYPE_HF, devinfo.ver >= 8 }, + { ELK_REGISTER_TYPE_VF, file == IMM }, + { ELK_REGISTER_TYPE_Q, devinfo.has_64bit_int }, + { ELK_REGISTER_TYPE_UQ, devinfo.has_64bit_int }, + { ELK_REGISTER_TYPE_D, true }, + { ELK_REGISTER_TYPE_UD, true }, + { ELK_REGISTER_TYPE_W, true }, + { ELK_REGISTER_TYPE_UW, true }, + { ELK_REGISTER_TYPE_B, file == FIXED_GRF }, + { ELK_REGISTER_TYPE_UB, file == FIXED_GRF }, + { ELK_REGISTER_TYPE_V, file == IMM }, + { ELK_REGISTER_TYPE_UV, devinfo.ver >= 6 && file == IMM }, }; /* Initially assume all hardware encodings are invalid */ BITSET_ONES(invalid_encodings); - brw_set_default_exec_size(p, BRW_EXECUTE_4); + elk_set_default_exec_size(p, ELK_EXECUTE_4); for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) { if (test_case[i].expected_result) { - unsigned hw_type = brw_reg_type_to_hw_type(&devinfo, file, test_case[i].type); + unsigned hw_type = elk_reg_type_to_hw_type(&devinfo, file, test_case[i].type); if (hw_type != INVALID_REG_TYPE) { /* ... and remove valid encodings from the set */ assert(BITSET_TEST(invalid_encodings, hw_type)); @@ -330,31 +330,31 @@ TEST_P(validation_test, invalid_type_encoding) } if (file == FIXED_GRF) { - struct brw_reg g = retype(g0, test_case[i].type); - brw_MOV(p, g, g); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + struct elk_reg g = retype(g0, test_case[i].type); + elk_MOV(p, g, g); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); } else { - enum brw_reg_type t; + enum elk_reg_type t; switch (test_case[i].type) { - case BRW_REGISTER_TYPE_V: - t = BRW_REGISTER_TYPE_W; + case ELK_REGISTER_TYPE_V: + t = ELK_REGISTER_TYPE_W; break; - case BRW_REGISTER_TYPE_UV: - t = BRW_REGISTER_TYPE_UW; + case ELK_REGISTER_TYPE_UV: + t = ELK_REGISTER_TYPE_UW; break; - case BRW_REGISTER_TYPE_VF: - t = BRW_REGISTER_TYPE_F; + case ELK_REGISTER_TYPE_VF: + t = ELK_REGISTER_TYPE_F; break; default: t = test_case[i].type; break; } - struct brw_reg g = retype(g0, t); - brw_MOV(p, g, retype(brw_imm_w(0), test_case[i].type)); + struct elk_reg g = retype(g0, t); + elk_MOV(p, g, retype(elk_imm_w(0), test_case[i].type)); } EXPECT_TRUE(validate(p)); @@ -364,21 +364,21 @@ TEST_P(validation_test, invalid_type_encoding) } /* The remaining encodings in invalid_encodings do not have a mapping - * from BRW_REGISTER_TYPE_* and must be invalid. Verify that invalid + * from ELK_REGISTER_TYPE_* and must be invalid. Verify that invalid * encodings are rejected by the validator. */ int e; BITSET_FOREACH_SET(e, invalid_encodings, num_encodings) { if (file == FIXED_GRF) { - brw_MOV(p, g0, g0); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_MOV(p, g0, g0); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); } else { - brw_MOV(p, g0, brw_imm_w(0)); + elk_MOV(p, g0, elk_imm_w(0)); } - brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, e); - brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, e); + elk_inst_set_dst_reg_hw_type(&devinfo, last_inst, e); + elk_inst_set_src0_reg_hw_type(&devinfo, last_inst, e); EXPECT_FALSE(validate(p)); @@ -403,36 +403,36 @@ TEST_P(validation_test, invalid_type_encoding_3src_a16) BITSET_DECLARE(invalid_encodings, num_encodings); const struct { - enum brw_reg_type type; + enum elk_reg_type type; bool expected_result; } test_case[] = { - { BRW_REGISTER_TYPE_DF, devinfo.ver >= 7 }, - { BRW_REGISTER_TYPE_F, true }, - { BRW_REGISTER_TYPE_HF, devinfo.ver >= 8 }, - { BRW_REGISTER_TYPE_D, devinfo.ver >= 7 }, - { BRW_REGISTER_TYPE_UD, devinfo.ver >= 7 }, + { ELK_REGISTER_TYPE_DF, devinfo.ver >= 7 }, + { ELK_REGISTER_TYPE_F, true }, + { ELK_REGISTER_TYPE_HF, devinfo.ver >= 8 }, + { ELK_REGISTER_TYPE_D, devinfo.ver >= 7 }, + { ELK_REGISTER_TYPE_UD, devinfo.ver >= 7 }, }; /* Initially assume all hardware encodings are invalid */ BITSET_ONES(invalid_encodings); - brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_set_default_exec_size(p, BRW_EXECUTE_4); + elk_set_default_access_mode(p, ELK_ALIGN_16); + elk_set_default_exec_size(p, ELK_EXECUTE_4); for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) { if (test_case[i].expected_result) { - unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(&devinfo, test_case[i].type); + unsigned hw_type = elk_reg_type_to_a16_hw_3src_type(&devinfo, test_case[i].type); if (hw_type != INVALID_HW_REG_TYPE) { /* ... and remove valid encodings from the set */ assert(BITSET_TEST(invalid_encodings, hw_type)); BITSET_CLEAR(invalid_encodings, hw_type); } - struct brw_reg g = retype(g0, test_case[i].type); - if (!brw_reg_type_is_integer(test_case[i].type)) { - brw_MAD(p, g, g, g, g); + struct elk_reg g = retype(g0, test_case[i].type); + if (!elk_reg_type_is_integer(test_case[i].type)) { + elk_MAD(p, g, g, g, g); } else { - brw_BFE(p, g, g, g, g); + elk_BFE(p, g, g, g, g); } EXPECT_TRUE(validate(p)); @@ -442,20 +442,20 @@ TEST_P(validation_test, invalid_type_encoding_3src_a16) } /* The remaining encodings in invalid_encodings do not have a mapping - * from BRW_REGISTER_TYPE_* and must be invalid. Verify that invalid + * from ELK_REGISTER_TYPE_* and must be invalid. Verify that invalid * encodings are rejected by the validator. */ int e; BITSET_FOREACH_SET(e, invalid_encodings, num_encodings) { for (unsigned i = 0; i < 2; i++) { if (i == 0) { - brw_MAD(p, g0, g0, g0, g0); + elk_MAD(p, g0, g0, g0, g0); } else { - brw_BFE(p, g0, g0, g0, g0); + elk_BFE(p, g0, g0, g0, g0); } - brw_inst_set_3src_a16_dst_hw_type(&devinfo, last_inst, e); - brw_inst_set_3src_a16_src_hw_type(&devinfo, last_inst, e); + elk_inst_set_3src_a16_dst_hw_type(&devinfo, last_inst, e); + elk_inst_set_3src_a16_src_hw_type(&devinfo, last_inst, e); EXPECT_FALSE(validate(p)); @@ -483,36 +483,36 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1) BITSET_DECLARE(invalid_encodings, num_encodings); const struct { - enum brw_reg_type type; + enum elk_reg_type type; unsigned exec_type; bool expected_result; } test_case[] = { -#define E(x) ((unsigned)BRW_ALIGN1_3SRC_EXEC_TYPE_##x) - { BRW_REGISTER_TYPE_NF, E(FLOAT), devinfo.ver == 11 }, - { BRW_REGISTER_TYPE_DF, E(FLOAT), devinfo.has_64bit_float }, - { BRW_REGISTER_TYPE_F, E(FLOAT), true }, - { BRW_REGISTER_TYPE_HF, E(FLOAT), true }, - { BRW_REGISTER_TYPE_D, E(INT), true }, - { BRW_REGISTER_TYPE_UD, E(INT), true }, - { BRW_REGISTER_TYPE_W, E(INT), true }, - { BRW_REGISTER_TYPE_UW, E(INT), true }, +#define E(x) ((unsigned)ELK_ALIGN1_3SRC_EXEC_TYPE_##x) + { ELK_REGISTER_TYPE_NF, E(FLOAT), devinfo.ver == 11 }, + { ELK_REGISTER_TYPE_DF, E(FLOAT), devinfo.has_64bit_float }, + { ELK_REGISTER_TYPE_F, E(FLOAT), true }, + { ELK_REGISTER_TYPE_HF, E(FLOAT), true }, + { ELK_REGISTER_TYPE_D, E(INT), true }, + { ELK_REGISTER_TYPE_UD, E(INT), true }, + { ELK_REGISTER_TYPE_W, E(INT), true }, + { ELK_REGISTER_TYPE_UW, E(INT), true }, /* There are no ternary instructions that can operate on B-type sources * on Gfx11-12. Src1/Src2 cannot be B-typed either. */ - { BRW_REGISTER_TYPE_B, E(INT), false }, - { BRW_REGISTER_TYPE_UB, E(INT), false }, + { ELK_REGISTER_TYPE_B, E(INT), false }, + { ELK_REGISTER_TYPE_UB, E(INT), false }, }; /* Initially assume all hardware encodings are invalid */ BITSET_ONES(invalid_encodings); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_exec_size(p, BRW_EXECUTE_4); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_exec_size(p, ELK_EXECUTE_4); for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) { if (test_case[i].expected_result) { - unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(&devinfo, test_case[i].type); + unsigned hw_type = elk_reg_type_to_a1_hw_3src_type(&devinfo, test_case[i].type); unsigned hw_exec_type = hw_type | (test_case[i].exec_type << 3); if (hw_type != INVALID_HW_REG_TYPE) { /* ... and remove valid encodings from the set */ @@ -520,11 +520,11 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1) BITSET_CLEAR(invalid_encodings, hw_exec_type); } - struct brw_reg g = retype(g0, test_case[i].type); - if (!brw_reg_type_is_integer(test_case[i].type)) { - brw_MAD(p, g, g, g, g); + struct elk_reg g = retype(g0, test_case[i].type); + if (!elk_reg_type_is_integer(test_case[i].type)) { + elk_MAD(p, g, g, g, g); } else { - brw_BFE(p, g, g, g, g); + elk_BFE(p, g, g, g, g); } EXPECT_TRUE(validate(p)); @@ -534,7 +534,7 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1) } /* The remaining encodings in invalid_encodings do not have a mapping - * from BRW_REGISTER_TYPE_* and must be invalid. Verify that invalid + * from ELK_REGISTER_TYPE_* and must be invalid. Verify that invalid * encodings are rejected by the validator. */ int e; @@ -544,19 +544,19 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1) for (unsigned i = 0; i < 2; i++) { if (i == 0) { - brw_MAD(p, g0, g0, g0, g0); - brw_inst_set_3src_a1_exec_type(&devinfo, last_inst, BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); + elk_MAD(p, g0, g0, g0, g0); + elk_inst_set_3src_a1_exec_type(&devinfo, last_inst, ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT); } else { - brw_CSEL(p, g0, g0, g0, g0); - brw_inst_set_3src_cond_modifier(&devinfo, last_inst, BRW_CONDITIONAL_NZ); - brw_inst_set_3src_a1_exec_type(&devinfo, last_inst, BRW_ALIGN1_3SRC_EXEC_TYPE_INT); + elk_CSEL(p, g0, g0, g0, g0); + elk_inst_set_3src_cond_modifier(&devinfo, last_inst, ELK_CONDITIONAL_NZ); + elk_inst_set_3src_a1_exec_type(&devinfo, last_inst, ELK_ALIGN1_3SRC_EXEC_TYPE_INT); } - brw_inst_set_3src_a1_exec_type(&devinfo, last_inst, exec_type); - brw_inst_set_3src_a1_dst_hw_type (&devinfo, last_inst, hw_type); - brw_inst_set_3src_a1_src0_hw_type(&devinfo, last_inst, hw_type); - brw_inst_set_3src_a1_src1_hw_type(&devinfo, last_inst, hw_type); - brw_inst_set_3src_a1_src2_hw_type(&devinfo, last_inst, hw_type); + elk_inst_set_3src_a1_exec_type(&devinfo, last_inst, exec_type); + elk_inst_set_3src_a1_dst_hw_type (&devinfo, last_inst, hw_type); + elk_inst_set_3src_a1_src0_hw_type(&devinfo, last_inst, hw_type); + elk_inst_set_3src_a1_src1_hw_type(&devinfo, last_inst, hw_type); + elk_inst_set_3src_a1_src2_hw_type(&devinfo, last_inst, hw_type); EXPECT_FALSE(validate(p)); @@ -579,16 +579,16 @@ TEST_P(validation_test, 3src_inst_access_mode) unsigned mode; bool expected_result; } test_case[] = { - { BRW_ALIGN_1, devinfo.ver >= 10 }, - { BRW_ALIGN_16, devinfo.ver <= 10 }, + { ELK_ALIGN_1, devinfo.ver >= 10 }, + { ELK_ALIGN_16, devinfo.ver <= 10 }, }; for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) { if (devinfo.ver < 10) - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); - brw_MAD(p, g0, g0, g0, g0); - brw_inst_set_access_mode(&devinfo, last_inst, test_case[i].mode); + elk_MAD(p, g0, g0, g0, g0); + elk_inst_set_access_mode(&devinfo, last_inst, test_case[i].mode); EXPECT_EQ(test_case[i].expected_result, validate(p)); @@ -602,20 +602,20 @@ TEST_P(validation_test, 3src_inst_access_mode) */ TEST_P(validation_test, dest_stride_must_be_equal_to_the_ratio_of_exec_size_to_dest_size) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); EXPECT_TRUE(validate(p)); } @@ -626,30 +626,30 @@ TEST_P(validation_test, dest_stride_must_be_equal_to_the_ratio_of_exec_size_to_d */ TEST_P(validation_test, dst_subreg_must_be_aligned_to_exec_type_size) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 2); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 2); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 8); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_4); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 8); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); EXPECT_TRUE(validate(p)); } @@ -657,15 +657,15 @@ TEST_P(validation_test, dst_subreg_must_be_aligned_to_exec_type_size) /* ExecSize must be greater than or equal to Width. */ TEST_P(validation_test, exec_size_less_than_width) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_16); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_16); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_16); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_16); EXPECT_FALSE(validate(p)); } @@ -675,15 +675,15 @@ TEST_P(validation_test, exec_size_less_than_width) */ TEST_P(validation_test, vertical_stride_is_width_by_horizontal_stride) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); EXPECT_FALSE(validate(p)); } @@ -693,19 +693,19 @@ TEST_P(validation_test, vertical_stride_is_width_by_horizontal_stride) */ TEST_P(validation_test, horizontal_stride_must_be_0_if_width_is_1) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_0); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_0); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); EXPECT_FALSE(validate(p)); } @@ -713,23 +713,23 @@ TEST_P(validation_test, horizontal_stride_must_be_0_if_width_is_1) /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */ TEST_P(validation_test, scalar_region_must_be_0_1_0) { - struct brw_reg g0_0 = brw_vec1_grf(0, 0); + struct elk_reg g0_0 = elk_vec1_grf(0, 0); - brw_ADD(p, g0, g0, g0_0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_1); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_1); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); + elk_ADD(p, g0, g0, g0_0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_1); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_1); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0_0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_1); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_1); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); + elk_ADD(p, g0, g0_0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_1); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_1); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); EXPECT_FALSE(validate(p)); } @@ -739,19 +739,19 @@ TEST_P(validation_test, scalar_region_must_be_0_1_0) */ TEST_P(validation_test, zero_stride_implies_0_1_0) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_0); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_2); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_0); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_2); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); EXPECT_FALSE(validate(p)); } @@ -759,8 +759,8 @@ TEST_P(validation_test, zero_stride_implies_0_1_0) /* Dst.HorzStride must not be 0. */ TEST_P(validation_test, dst_horizontal_stride_0) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); EXPECT_FALSE(validate(p)); @@ -770,46 +770,46 @@ TEST_P(validation_test, dst_horizontal_stride_0) if (devinfo.ver >= 11) return; - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); EXPECT_FALSE(validate(p)); } -/* VertStride must be used to cross BRW_GENERAL_REGISTER_FILE register boundaries. This rule implies - * that elements within a 'Width' cannot cross BRW_GENERAL_REGISTER_FILE boundaries. +/* VertStride must be used to cross ELK_GENERAL_REGISTER_FILE register boundaries. This rule implies + * that elements within a 'Width' cannot cross ELK_GENERAL_REGISTER_FILE boundaries. */ TEST_P(validation_test, must_not_cross_grf_boundary_in_a_width) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 4); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 4); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 4); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 4); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); EXPECT_FALSE(validate(p)); } @@ -821,17 +821,17 @@ TEST_P(validation_test, dst_hstride_on_align16_must_be_1) if (devinfo.ver >= 11) return; - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); EXPECT_TRUE(validate(p)); } @@ -844,24 +844,24 @@ TEST_P(validation_test, vstride_on_align16_must_be_0_or_4) return; const struct { - enum brw_vertical_stride vstride; + enum elk_vertical_stride vstride; bool expected_result; } vstride[] = { - { BRW_VERTICAL_STRIDE_0, true }, - { BRW_VERTICAL_STRIDE_1, false }, - { BRW_VERTICAL_STRIDE_2, devinfo.verx10 >= 75 }, - { BRW_VERTICAL_STRIDE_4, true }, - { BRW_VERTICAL_STRIDE_8, false }, - { BRW_VERTICAL_STRIDE_16, false }, - { BRW_VERTICAL_STRIDE_32, false }, - { BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, false }, + { ELK_VERTICAL_STRIDE_0, true }, + { ELK_VERTICAL_STRIDE_1, false }, + { ELK_VERTICAL_STRIDE_2, devinfo.verx10 >= 75 }, + { ELK_VERTICAL_STRIDE_4, true }, + { ELK_VERTICAL_STRIDE_8, false }, + { ELK_VERTICAL_STRIDE_16, false }, + { ELK_VERTICAL_STRIDE_32, false }, + { ELK_VERTICAL_STRIDE_ONE_DIMENSIONAL, false }, }; - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); for (unsigned i = 0; i < ARRAY_SIZE(vstride); i++) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_src0_vstride(&devinfo, last_inst, vstride[i].vstride); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src0_vstride(&devinfo, last_inst, vstride[i].vstride); EXPECT_EQ(vstride[i].expected_result, validate(p)); @@ -869,8 +869,8 @@ TEST_P(validation_test, vstride_on_align16_must_be_0_or_4) } for (unsigned i = 0; i < ARRAY_SIZE(vstride); i++) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_src1_vstride(&devinfo, last_inst, vstride[i].vstride); + elk_ADD(p, g0, g0, g0); + elk_inst_set_src1_vstride(&devinfo, last_inst, vstride[i].vstride); EXPECT_EQ(vstride[i].expected_result, validate(p)); @@ -878,71 +878,71 @@ TEST_P(validation_test, vstride_on_align16_must_be_0_or_4) } } -/* In Direct Addressing mode, a source cannot span more than 2 adjacent BRW_GENERAL_REGISTER_FILE +/* In Direct Addressing mode, a source cannot span more than 2 adjacent ELK_GENERAL_REGISTER_FILE * registers. */ TEST_P(validation_test, source_cannot_span_more_than_2_registers) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_32); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_16); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_8); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 2); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_16); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_8); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 2); EXPECT_TRUE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); EXPECT_TRUE(validate(p)); } -/* A destination cannot span more than 2 adjacent BRW_GENERAL_REGISTER_FILE registers. */ +/* A destination cannot span more than 2 adjacent ELK_GENERAL_REGISTER_FILE registers. */ TEST_P(validation_test, destination_cannot_span_more_than_2_registers) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_32); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_8); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 6); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_8); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 6); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_4); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_16); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_16); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); EXPECT_TRUE(validate(p)); } @@ -950,59 +950,59 @@ TEST_P(validation_test, destination_cannot_span_more_than_2_registers) TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one) { /* Writes to dest are to the lower OWord */ - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_16); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); EXPECT_TRUE(validate(p)); clear_instructions(p); /* Writes to dest are to the upper OWord */ - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 16); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_16); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); EXPECT_TRUE(validate(p)); clear_instructions(p); /* Writes to dest are evenly split between OWords */ - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_16); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_8); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); EXPECT_TRUE(validate(p)); clear_instructions(p); /* Writes to dest are uneven between OWords */ - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 10); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_4); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 10); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_16); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_2); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); if (devinfo.ver >= 9) { EXPECT_TRUE(validate(p)); @@ -1013,8 +1013,8 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one) TEST_P(validation_test, dst_elements_must_be_evenly_split_between_registers) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4); + elk_ADD(p, g0, g0, g0); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4); if (devinfo.ver >= 9 && devinfo.verx10 < 125) { EXPECT_TRUE(validate(p)); @@ -1024,22 +1024,22 @@ TEST_P(validation_test, dst_elements_must_be_evenly_split_between_registers) clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); EXPECT_TRUE(validate(p)); clear_instructions(p); if (devinfo.ver >= 6) { - gfx6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); + elk_gfx6_math(p, g0, ELK_MATH_FUNCTION_SIN, g0, null); EXPECT_TRUE(validate(p)); clear_instructions(p); - gfx6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4); + elk_gfx6_math(p, g0, ELK_MATH_FUNCTION_SIN, g0, null); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4); EXPECT_FALSE(validate(p)); } @@ -1047,16 +1047,16 @@ TEST_P(validation_test, dst_elements_must_be_evenly_split_between_registers) TEST_P(validation_test, two_src_two_dst_source_offsets_must_be_same) { - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4); - brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 16); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_4); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_4); + elk_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 16); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_2); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); if (devinfo.ver <= 7 || devinfo.verx10 >= 125) { EXPECT_FALSE(validate(p)); @@ -1066,15 +1066,15 @@ TEST_P(validation_test, two_src_two_dst_source_offsets_must_be_same) clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_8); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_4); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_4); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_8); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_2); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); if (devinfo.verx10 >= 125) EXPECT_FALSE(validate(p)); @@ -1084,15 +1084,15 @@ TEST_P(validation_test, two_src_two_dst_source_offsets_must_be_same) TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src) { - brw_MOV(p, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 8); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_MOV(p, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 8); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); if (devinfo.ver <= 7) { EXPECT_FALSE(validate(p)); @@ -1102,12 +1102,12 @@ TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src) clear_instructions(p); - brw_MOV(p, g0, g0); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 16); - brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 8); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_MOV(p, g0, g0); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 16); + elk_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 8); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_2); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_2); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); if (devinfo.ver <= 7 || devinfo.verx10 >= 125) { EXPECT_FALSE(validate(p)); @@ -1118,30 +1118,30 @@ TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src) TEST_P(validation_test, one_src_two_dst) { - struct brw_reg g0_0 = brw_vec1_grf(0, 0); + struct elk_reg g0_0 = elk_vec1_grf(0, 0); - brw_ADD(p, g0, g0_0, g0_0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); + elk_ADD(p, g0, g0_0, g0_0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); EXPECT_TRUE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); EXPECT_TRUE(validate(p)); clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); if (devinfo.ver >= 8) { EXPECT_TRUE(validate(p)); @@ -1151,11 +1151,11 @@ TEST_P(validation_test, one_src_two_dst) clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_D); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); if (devinfo.ver >= 8) { EXPECT_TRUE(validate(p)); @@ -1165,15 +1165,15 @@ TEST_P(validation_test, one_src_two_dst) clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_0); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); if (devinfo.ver >= 8) { EXPECT_TRUE(validate(p)); @@ -1183,15 +1183,15 @@ TEST_P(validation_test, one_src_two_dst) clear_instructions(p); - brw_ADD(p, g0, g0, g0); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0); - brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); + elk_ADD(p, g0, g0, g0); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_16); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_dst_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_0); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_1); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_0); + elk_inst_set_src1_file_type(&devinfo, last_inst, ELK_GENERAL_REGISTER_FILE, ELK_REGISTER_TYPE_W); if (devinfo.ver >= 8) { EXPECT_TRUE(validate(p)); @@ -1203,83 +1203,83 @@ TEST_P(validation_test, one_src_two_dst) TEST_P(validation_test, packed_byte_destination) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src_type; + enum elk_reg_type dst_type; + enum elk_reg_type src_type; bool neg, abs, sat; bool expected_result; } move[] = { - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UB, 0, 0, 0, true }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_B , 0, 0, 0, true }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_B , 0, 0, 0, true }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_UB, 0, 0, 0, true }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_UB, 0, 0, 0, true }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_B , 0, 0, 0, true }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_B , 0, 0, 0, true }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_UB, 0, 0, 0, true }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UB, 1, 0, 0, false }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_B , 1, 0, 0, false }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_B , 1, 0, 0, false }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_UB, 1, 0, 0, false }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_UB, 1, 0, 0, false }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_B , 1, 0, 0, false }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_B , 1, 0, 0, false }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_UB, 1, 0, 0, false }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UB, 0, 1, 0, false }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_B , 0, 1, 0, false }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_B , 0, 1, 0, false }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_UB, 0, 1, 0, false }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_UB, 0, 1, 0, false }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_B , 0, 1, 0, false }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_B , 0, 1, 0, false }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_UB, 0, 1, 0, false }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UB, 0, 0, 1, false }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_B , 0, 0, 1, false }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_B , 0, 0, 1, false }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_UB, 0, 0, 1, false }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_UB, 0, 0, 1, false }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_B , 0, 0, 1, false }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_B , 0, 0, 1, false }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_UB, 0, 0, 1, false }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UW, 0, 0, 0, false }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_W , 0, 0, 0, false }, - { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UD, 0, 0, 0, false }, - { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_D , 0, 0, 0, false }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_UW, 0, 0, 0, false }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_W , 0, 0, 0, false }, + { ELK_REGISTER_TYPE_UB, ELK_REGISTER_TYPE_UD, 0, 0, 0, false }, + { ELK_REGISTER_TYPE_B , ELK_REGISTER_TYPE_D , 0, 0, 0, false }, }; for (unsigned i = 0; i < ARRAY_SIZE(move); i++) { - brw_MOV(p, retype(g0, move[i].dst_type), retype(g0, move[i].src_type)); - brw_inst_set_src0_negate(&devinfo, last_inst, move[i].neg); - brw_inst_set_src0_abs(&devinfo, last_inst, move[i].abs); - brw_inst_set_saturate(&devinfo, last_inst, move[i].sat); + elk_MOV(p, retype(g0, move[i].dst_type), retype(g0, move[i].src_type)); + elk_inst_set_src0_negate(&devinfo, last_inst, move[i].neg); + elk_inst_set_src0_abs(&devinfo, last_inst, move[i].abs); + elk_inst_set_saturate(&devinfo, last_inst, move[i].sat); EXPECT_EQ(move[i].expected_result, validate(p)); clear_instructions(p); } - brw_SEL(p, retype(g0, BRW_REGISTER_TYPE_UB), - retype(g0, BRW_REGISTER_TYPE_UB), - retype(g0, BRW_REGISTER_TYPE_UB)); - brw_inst_set_pred_control(&devinfo, last_inst, BRW_PREDICATE_NORMAL); + elk_SEL(p, retype(g0, ELK_REGISTER_TYPE_UB), + retype(g0, ELK_REGISTER_TYPE_UB), + retype(g0, ELK_REGISTER_TYPE_UB)); + elk_inst_set_pred_control(&devinfo, last_inst, ELK_PREDICATE_NORMAL); EXPECT_FALSE(validate(p)); clear_instructions(p); - brw_SEL(p, retype(g0, BRW_REGISTER_TYPE_B), - retype(g0, BRW_REGISTER_TYPE_B), - retype(g0, BRW_REGISTER_TYPE_B)); - brw_inst_set_pred_control(&devinfo, last_inst, BRW_PREDICATE_NORMAL); + elk_SEL(p, retype(g0, ELK_REGISTER_TYPE_B), + retype(g0, ELK_REGISTER_TYPE_B), + retype(g0, ELK_REGISTER_TYPE_B)); + elk_inst_set_pred_control(&devinfo, last_inst, ELK_PREDICATE_NORMAL); EXPECT_FALSE(validate(p)); } TEST_P(validation_test, byte_destination_relaxed_alignment) { - brw_SEL(p, retype(g0, BRW_REGISTER_TYPE_B), - retype(g0, BRW_REGISTER_TYPE_W), - retype(g0, BRW_REGISTER_TYPE_W)); - brw_inst_set_pred_control(&devinfo, last_inst, BRW_PREDICATE_NORMAL); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + elk_SEL(p, retype(g0, ELK_REGISTER_TYPE_B), + retype(g0, ELK_REGISTER_TYPE_W), + retype(g0, ELK_REGISTER_TYPE_W)); + elk_inst_set_pred_control(&devinfo, last_inst, ELK_PREDICATE_NORMAL); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); EXPECT_TRUE(validate(p)); clear_instructions(p); - brw_SEL(p, retype(g0, BRW_REGISTER_TYPE_B), - retype(g0, BRW_REGISTER_TYPE_W), - retype(g0, BRW_REGISTER_TYPE_W)); - brw_inst_set_pred_control(&devinfo, last_inst, BRW_PREDICATE_NORMAL); - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 1); + elk_SEL(p, retype(g0, ELK_REGISTER_TYPE_B), + retype(g0, ELK_REGISTER_TYPE_W), + retype(g0, ELK_REGISTER_TYPE_W)); + elk_inst_set_pred_control(&devinfo, last_inst, ELK_PREDICATE_NORMAL); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 1); if (devinfo.verx10 >= 45) { EXPECT_TRUE(validate(p)); @@ -1291,16 +1291,16 @@ TEST_P(validation_test, byte_destination_relaxed_alignment) TEST_P(validation_test, byte_64bit_conversion) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src_type; + enum elk_reg_type dst_type; + enum elk_reg_type src_type; unsigned dst_stride; bool expected_result; } inst[] = { #define INST(dst_type, src_type, dst_stride, expected_result) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ expected_result, \ } @@ -1333,16 +1333,16 @@ TEST_P(validation_test, byte_64bit_conversion) for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { if (!devinfo.has_64bit_float && - inst[i].src_type == BRW_REGISTER_TYPE_DF) + inst[i].src_type == ELK_REGISTER_TYPE_DF) continue; if (!devinfo.has_64bit_int && - (inst[i].src_type == BRW_REGISTER_TYPE_Q || - inst[i].src_type == BRW_REGISTER_TYPE_UQ)) + (inst[i].src_type == ELK_REGISTER_TYPE_Q || + inst[i].src_type == ELK_REGISTER_TYPE_UQ)) continue; - brw_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type)); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type)); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); EXPECT_EQ(inst[i].expected_result, validate(p)); clear_instructions(p); @@ -1352,8 +1352,8 @@ TEST_P(validation_test, byte_64bit_conversion) TEST_P(validation_test, half_float_conversion) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src_type; + enum elk_reg_type dst_type; + enum elk_reg_type src_type; unsigned dst_stride; unsigned dst_subnr; bool expected_result_bdw; @@ -1364,9 +1364,9 @@ TEST_P(validation_test, half_float_conversion) expected_result_bdw, expected_result_chv_gfx9, \ expected_result_gfx125) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ dst_subnr, \ expected_result_bdw, \ expected_result_chv_gfx9, \ @@ -1428,32 +1428,32 @@ TEST_P(validation_test, half_float_conversion) for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { if (!devinfo.has_64bit_float && - (inst[i].dst_type == BRW_REGISTER_TYPE_DF || - inst[i].src_type == BRW_REGISTER_TYPE_DF)) + (inst[i].dst_type == ELK_REGISTER_TYPE_DF || + inst[i].src_type == ELK_REGISTER_TYPE_DF)) continue; if (!devinfo.has_64bit_int && - (inst[i].dst_type == BRW_REGISTER_TYPE_Q || - inst[i].dst_type == BRW_REGISTER_TYPE_UQ || - inst[i].src_type == BRW_REGISTER_TYPE_Q || - inst[i].src_type == BRW_REGISTER_TYPE_UQ)) + (inst[i].dst_type == ELK_REGISTER_TYPE_Q || + inst[i].dst_type == ELK_REGISTER_TYPE_UQ || + inst[i].src_type == ELK_REGISTER_TYPE_Q || + inst[i].src_type == ELK_REGISTER_TYPE_UQ)) continue; - brw_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type)); + elk_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type)); - brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4); + elk_inst_set_exec_size(&devinfo, last_inst, ELK_EXECUTE_4); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subnr); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subnr); - if (inst[i].src_type == BRW_REGISTER_TYPE_B) { - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); + if (inst[i].src_type == ELK_REGISTER_TYPE_B) { + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_2); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_2); } else { - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); } if (devinfo.verx10 >= 125) { @@ -1474,9 +1474,9 @@ TEST_P(validation_test, half_float_conversion) TEST_P(validation_test, mixed_float_source_indirect_addressing) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; unsigned dst_stride; bool dst_indirect; bool src0_indirect; @@ -1487,10 +1487,10 @@ TEST_P(validation_test, mixed_float_source_indirect_addressing) dst_stride, dst_indirect, src0_indirect, expected_result, \ gfx125_expected_result) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ dst_indirect, \ src0_indirect, \ expected_result, \ @@ -1523,13 +1523,13 @@ TEST_P(validation_test, mixed_float_source_indirect_addressing) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD(p, retype(g0, inst[i].dst_type), + elk_ADD(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_dst_address_mode(&devinfo, last_inst, inst[i].dst_indirect); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_src0_address_mode(&devinfo, last_inst, inst[i].src0_indirect); + elk_inst_set_dst_address_mode(&devinfo, last_inst, inst[i].dst_indirect); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_src0_address_mode(&devinfo, last_inst, inst[i].src0_indirect); if (devinfo.verx10 >= 125) { EXPECT_EQ(inst[i].gfx125_expected_result, validate(p)); @@ -1545,9 +1545,9 @@ TEST_P(validation_test, mixed_float_align1_simd16) { static const struct { unsigned exec_size; - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; unsigned dst_stride; bool expected_result; bool gfx125_expected_result; @@ -1555,11 +1555,11 @@ TEST_P(validation_test, mixed_float_align1_simd16) #define INST(exec_size, dst_type, src0_type, src1_type, \ dst_stride, expected_result, gfx125_expected_result) \ { \ - BRW_EXECUTE_##exec_size, \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_EXECUTE_##exec_size, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ expected_result, \ gfx125_expected_result, \ } @@ -1583,13 +1583,13 @@ TEST_P(validation_test, mixed_float_align1_simd16) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD(p, retype(g0, inst[i].dst_type), + elk_ADD(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); if (devinfo.verx10 >= 125) { EXPECT_EQ(inst[i].gfx125_expected_result, validate(p)); @@ -1604,9 +1604,9 @@ TEST_P(validation_test, mixed_float_align1_simd16) TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; unsigned dst_stride; bool read_acc; unsigned subnr; @@ -1618,10 +1618,10 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0) expected_result_bdw, expected_result_chv_skl, \ expected_result_gfx125) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ read_acc, \ subnr, \ expected_result_bdw, \ @@ -1657,13 +1657,13 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD(p, retype(g0, inst[i].dst_type), + elk_ADD(p, retype(g0, inst[i].dst_type), retype(inst[i].read_acc ? acc0 : g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].subnr); + elk_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].subnr); if (devinfo.verx10 >= 125) EXPECT_EQ(inst[i].expected_result_gfx125, validate(p)); @@ -1681,9 +1681,9 @@ TEST_P(validation_test, mixed_float_fp16_dest_with_acc) static const struct { unsigned exec_size; unsigned opcode; - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; unsigned dst_stride; bool read_acc; bool expected_result_bdw; @@ -1694,12 +1694,12 @@ TEST_P(validation_test, mixed_float_fp16_dest_with_acc) dst_stride, read_acc,expected_result_bdw, \ expected_result_chv_skl, expected_result_gfx125) \ { \ - BRW_EXECUTE_##exec_size, \ - BRW_OPCODE_##opcode, \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_EXECUTE_##exec_size, \ + ELK_OPCODE_##opcode, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ read_acc, \ expected_result_bdw, \ expected_result_chv_skl, \ @@ -1737,20 +1737,20 @@ TEST_P(validation_test, mixed_float_fp16_dest_with_acc) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - if (inst[i].opcode == BRW_OPCODE_MAC) { - brw_MAC(p, retype(g0, inst[i].dst_type), + if (inst[i].opcode == ELK_OPCODE_MAC) { + elk_MAC(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); } else { - assert(inst[i].opcode == BRW_OPCODE_ADD); - brw_ADD(p, retype(g0, inst[i].dst_type), + assert(inst[i].opcode == ELK_OPCODE_ADD); + elk_ADD(p, retype(g0, inst[i].dst_type), retype(inst[i].read_acc ? acc0: g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); } - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); if (devinfo.verx10 >= 125) EXPECT_EQ(inst[i].expected_result_gfx125, validate(p)); @@ -1766,9 +1766,9 @@ TEST_P(validation_test, mixed_float_fp16_dest_with_acc) TEST_P(validation_test, mixed_float_align1_math_strided_fp16_inputs) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; unsigned dst_stride; unsigned src0_stride; unsigned src1_stride; @@ -1779,12 +1779,12 @@ TEST_P(validation_test, mixed_float_align1_math_strided_fp16_inputs) dst_stride, src0_stride, src1_stride, expected_result, \ expected_result_125) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ - BRW_HORIZONTAL_STRIDE_##src0_stride, \ - BRW_HORIZONTAL_STRIDE_##src1_stride, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_HORIZONTAL_STRIDE_##src0_stride, \ + ELK_HORIZONTAL_STRIDE_##src1_stride, \ expected_result, \ expected_result_125, \ } @@ -1809,20 +1809,20 @@ TEST_P(validation_test, mixed_float_align1_math_strided_fp16_inputs) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - gfx6_math(p, retype(g0, inst[i].dst_type), - BRW_MATH_FUNCTION_POW, + elk_gfx6_math(p, retype(g0, inst[i].dst_type), + ELK_MATH_FUNCTION_POW, retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src0_stride); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src0_stride); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src1_hstride(&devinfo, last_inst, inst[i].src1_stride); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src1_hstride(&devinfo, last_inst, inst[i].src1_stride); if (devinfo.verx10 >= 125) EXPECT_EQ(inst[i].expected_result_gfx125, validate(p)); @@ -1837,9 +1837,9 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst) { static const struct { unsigned exec_size; - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; unsigned dst_stride; unsigned dst_subnr; bool expected_result_bdw; @@ -1850,11 +1850,11 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst) expected_result_bdw, expected_result_chv_skl, \ expected_result_gfx125) \ { \ - BRW_EXECUTE_##exec_size, \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_EXECUTE_##exec_size, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ dst_subnr, \ expected_result_bdw, \ expected_result_chv_skl, \ @@ -1890,22 +1890,22 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD(p, retype(g0, inst[i].dst_type), + elk_ADD(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subnr); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subnr); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src0_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src0_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4); - brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src1_width(&devinfo, last_inst, ELK_WIDTH_4); + elk_inst_set_src1_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); if (devinfo.verx10 >= 125) EXPECT_EQ(inst[i].expected_result_gfx125, validate(p)); @@ -1921,9 +1921,9 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst) TEST_P(validation_test, mixed_float_align16_packed_data) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; unsigned src0_vstride; unsigned src1_vstride; bool expected_result; @@ -1931,11 +1931,11 @@ TEST_P(validation_test, mixed_float_align16_packed_data) #define INST(dst_type, src0_type, src1_type, \ src0_vstride, src1_vstride, expected_result) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_VERTICAL_STRIDE_##src0_vstride, \ - BRW_VERTICAL_STRIDE_##src1_vstride, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_VERTICAL_STRIDE_##src0_vstride, \ + ELK_VERTICAL_STRIDE_##src1_vstride, \ expected_result, \ } @@ -1960,15 +1960,15 @@ TEST_P(validation_test, mixed_float_align16_packed_data) if (devinfo.ver < 8 || devinfo.ver >= 11) return; - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD(p, retype(g0, inst[i].dst_type), + elk_ADD(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src0_vstride); - brw_inst_set_src1_vstride(&devinfo, last_inst, inst[i].src1_vstride); + elk_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src0_vstride); + elk_inst_set_src1_vstride(&devinfo, last_inst, inst[i].src1_vstride); EXPECT_EQ(inst[i].expected_result, validate(p)); @@ -1980,17 +1980,17 @@ TEST_P(validation_test, mixed_float_align16_no_simd16) { static const struct { unsigned exec_size; - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; bool expected_result; } inst[] = { #define INST(exec_size, dst_type, src0_type, src1_type, expected_result) \ { \ - BRW_EXECUTE_##exec_size, \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ + ELK_EXECUTE_##exec_size, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ expected_result, \ } @@ -2011,17 +2011,17 @@ TEST_P(validation_test, mixed_float_align16_no_simd16) if (devinfo.ver < 8 || devinfo.ver >= 11) return; - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD(p, retype(g0, inst[i].dst_type), + elk_ADD(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); EXPECT_EQ(inst[i].expected_result, validate(p)); @@ -2032,17 +2032,17 @@ TEST_P(validation_test, mixed_float_align16_no_simd16) TEST_P(validation_test, mixed_float_align16_no_acc_read) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; bool read_acc; bool expected_result; } inst[] = { #define INST(dst_type, src0_type, src1_type, read_acc, expected_result) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ read_acc, \ expected_result, \ } @@ -2062,15 +2062,15 @@ TEST_P(validation_test, mixed_float_align16_no_acc_read) if (devinfo.ver < 8 || devinfo.ver >= 11) return; - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD(p, retype(g0, inst[i].dst_type), + elk_ADD(p, retype(g0, inst[i].dst_type), retype(inst[i].read_acc ? acc0 : g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); - brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); + elk_inst_set_src0_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); + elk_inst_set_src1_vstride(&devinfo, last_inst, ELK_VERTICAL_STRIDE_4); EXPECT_EQ(inst[i].expected_result, validate(p)); @@ -2081,9 +2081,9 @@ TEST_P(validation_test, mixed_float_align16_no_acc_read) TEST_P(validation_test, mixed_float_align16_math_packed_format) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; unsigned src0_vstride; unsigned src1_vstride; bool expected_result; @@ -2091,11 +2091,11 @@ TEST_P(validation_test, mixed_float_align16_math_packed_format) #define INST(dst_type, src0_type, src1_type, \ src0_vstride, src1_vstride, expected_result) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_VERTICAL_STRIDE_##src0_vstride, \ - BRW_VERTICAL_STRIDE_##src1_vstride, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_VERTICAL_STRIDE_##src0_vstride, \ + ELK_VERTICAL_STRIDE_##src1_vstride, \ expected_result, \ } @@ -2117,16 +2117,16 @@ TEST_P(validation_test, mixed_float_align16_math_packed_format) if (devinfo.ver < 9 || devinfo.ver >= 11) return; - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - gfx6_math(p, retype(g0, inst[i].dst_type), - BRW_MATH_FUNCTION_POW, + elk_gfx6_math(p, retype(g0, inst[i].dst_type), + ELK_MATH_FUNCTION_POW, retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); - brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src0_vstride); - brw_inst_set_src1_vstride(&devinfo, last_inst, inst[i].src1_vstride); + elk_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src0_vstride); + elk_inst_set_src1_vstride(&devinfo, last_inst, inst[i].src1_vstride); EXPECT_EQ(inst[i].expected_result, validate(p)); @@ -2137,34 +2137,34 @@ TEST_P(validation_test, mixed_float_align16_math_packed_format) TEST_P(validation_test, vector_immediate_destination_alignment) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src_type; + enum elk_reg_type dst_type; + enum elk_reg_type src_type; unsigned subnr; unsigned exec_size; bool expected_result; } move[] = { - { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF, 0, BRW_EXECUTE_4, true }, - { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF, 16, BRW_EXECUTE_4, true }, - { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF, 1, BRW_EXECUTE_4, false }, + { ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_VF, 0, ELK_EXECUTE_4, true }, + { ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_VF, 16, ELK_EXECUTE_4, true }, + { ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_VF, 1, ELK_EXECUTE_4, false }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V, 0, BRW_EXECUTE_8, true }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V, 16, BRW_EXECUTE_8, true }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V, 1, BRW_EXECUTE_8, false }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_V, 0, ELK_EXECUTE_8, true }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_V, 16, ELK_EXECUTE_8, true }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_V, 1, ELK_EXECUTE_8, false }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, 0, BRW_EXECUTE_8, true }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, 16, BRW_EXECUTE_8, true }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, 1, BRW_EXECUTE_8, false }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_UV, 0, ELK_EXECUTE_8, true }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_UV, 16, ELK_EXECUTE_8, true }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_UV, 1, ELK_EXECUTE_8, false }, }; for (unsigned i = 0; i < ARRAY_SIZE(move); i++) { /* UV type is Gfx6+ */ if (devinfo.ver < 6 && - move[i].src_type == BRW_REGISTER_TYPE_UV) + move[i].src_type == ELK_REGISTER_TYPE_UV) continue; - brw_MOV(p, retype(g0, move[i].dst_type), retype(zero, move[i].src_type)); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, move[i].subnr); - brw_inst_set_exec_size(&devinfo, last_inst, move[i].exec_size); + elk_MOV(p, retype(g0, move[i].dst_type), retype(zero, move[i].src_type)); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, move[i].subnr); + elk_inst_set_exec_size(&devinfo, last_inst, move[i].exec_size); EXPECT_EQ(move[i].expected_result, validate(p)); @@ -2175,37 +2175,37 @@ TEST_P(validation_test, vector_immediate_destination_alignment) TEST_P(validation_test, vector_immediate_destination_stride) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src_type; + enum elk_reg_type dst_type; + enum elk_reg_type src_type; unsigned stride; bool expected_result; } move[] = { - { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_1, true }, - { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_2, false }, - { BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_1, true }, - { BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_2, false }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_2, true }, - { BRW_REGISTER_TYPE_B, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_4, true }, + { ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_VF, ELK_HORIZONTAL_STRIDE_1, true }, + { ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_VF, ELK_HORIZONTAL_STRIDE_2, false }, + { ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_VF, ELK_HORIZONTAL_STRIDE_1, true }, + { ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_VF, ELK_HORIZONTAL_STRIDE_2, false }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_VF, ELK_HORIZONTAL_STRIDE_2, true }, + { ELK_REGISTER_TYPE_B, ELK_REGISTER_TYPE_VF, ELK_HORIZONTAL_STRIDE_4, true }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V, BRW_HORIZONTAL_STRIDE_1, true }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V, BRW_HORIZONTAL_STRIDE_2, false }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V, BRW_HORIZONTAL_STRIDE_4, false }, - { BRW_REGISTER_TYPE_B, BRW_REGISTER_TYPE_V, BRW_HORIZONTAL_STRIDE_2, true }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_V, ELK_HORIZONTAL_STRIDE_1, true }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_V, ELK_HORIZONTAL_STRIDE_2, false }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_V, ELK_HORIZONTAL_STRIDE_4, false }, + { ELK_REGISTER_TYPE_B, ELK_REGISTER_TYPE_V, ELK_HORIZONTAL_STRIDE_2, true }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, BRW_HORIZONTAL_STRIDE_1, true }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, BRW_HORIZONTAL_STRIDE_2, false }, - { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, BRW_HORIZONTAL_STRIDE_4, false }, - { BRW_REGISTER_TYPE_B, BRW_REGISTER_TYPE_UV, BRW_HORIZONTAL_STRIDE_2, true }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_UV, ELK_HORIZONTAL_STRIDE_1, true }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_UV, ELK_HORIZONTAL_STRIDE_2, false }, + { ELK_REGISTER_TYPE_W, ELK_REGISTER_TYPE_UV, ELK_HORIZONTAL_STRIDE_4, false }, + { ELK_REGISTER_TYPE_B, ELK_REGISTER_TYPE_UV, ELK_HORIZONTAL_STRIDE_2, true }, }; for (unsigned i = 0; i < ARRAY_SIZE(move); i++) { /* UV type is Gfx6+ */ if (devinfo.ver < 6 && - move[i].src_type == BRW_REGISTER_TYPE_UV) + move[i].src_type == ELK_REGISTER_TYPE_UV) continue; - brw_MOV(p, retype(g0, move[i].dst_type), retype(zero, move[i].src_type)); - brw_inst_set_dst_hstride(&devinfo, last_inst, move[i].stride); + elk_MOV(p, retype(g0, move[i].dst_type), retype(zero, move[i].src_type)); + elk_inst_set_dst_hstride(&devinfo, last_inst, move[i].stride); EXPECT_EQ(move[i].expected_result, validate(p)); @@ -2216,14 +2216,14 @@ TEST_P(validation_test, vector_immediate_destination_stride) TEST_P(validation_test, qword_low_power_align1_regioning_restrictions) { static const struct { - enum opcode opcode; + enum elk_opcode opcode; unsigned exec_size; - enum brw_reg_type dst_type; + enum elk_reg_type dst_type; unsigned dst_subreg; unsigned dst_stride; - enum brw_reg_type src_type; + enum elk_reg_type src_type; unsigned src_subreg; unsigned src_vstride; unsigned src_width; @@ -2234,16 +2234,16 @@ TEST_P(validation_test, qword_low_power_align1_regioning_restrictions) #define INST(opcode, exec_size, dst_type, dst_subreg, dst_stride, src_type, \ src_subreg, src_vstride, src_width, src_hstride, expected_result) \ { \ - BRW_OPCODE_##opcode, \ - BRW_EXECUTE_##exec_size, \ - BRW_REGISTER_TYPE_##dst_type, \ + ELK_OPCODE_##opcode, \ + ELK_EXECUTE_##exec_size, \ + ELK_REGISTER_TYPE_##dst_type, \ dst_subreg, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ - BRW_REGISTER_TYPE_##src_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_REGISTER_TYPE_##src_type, \ src_subreg, \ - BRW_VERTICAL_STRIDE_##src_vstride, \ - BRW_WIDTH_##src_width, \ - BRW_HORIZONTAL_STRIDE_##src_hstride, \ + ELK_VERTICAL_STRIDE_##src_vstride, \ + ELK_WIDTH_##src_width, \ + ELK_HORIZONTAL_STRIDE_##src_hstride, \ expected_result, \ } @@ -2360,36 +2360,36 @@ TEST_P(validation_test, qword_low_power_align1_regioning_restrictions) for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { if (!devinfo.has_64bit_float && - (inst[i].dst_type == BRW_REGISTER_TYPE_DF || - inst[i].src_type == BRW_REGISTER_TYPE_DF)) + (inst[i].dst_type == ELK_REGISTER_TYPE_DF || + inst[i].src_type == ELK_REGISTER_TYPE_DF)) continue; if (!devinfo.has_64bit_int && - (inst[i].dst_type == BRW_REGISTER_TYPE_Q || - inst[i].dst_type == BRW_REGISTER_TYPE_UQ || - inst[i].src_type == BRW_REGISTER_TYPE_Q || - inst[i].src_type == BRW_REGISTER_TYPE_UQ)) + (inst[i].dst_type == ELK_REGISTER_TYPE_Q || + inst[i].dst_type == ELK_REGISTER_TYPE_UQ || + inst[i].src_type == ELK_REGISTER_TYPE_Q || + inst[i].src_type == ELK_REGISTER_TYPE_UQ)) continue; - if (inst[i].opcode == BRW_OPCODE_MOV) { - brw_MOV(p, retype(g0, inst[i].dst_type), + if (inst[i].opcode == ELK_OPCODE_MOV) { + elk_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type)); } else { - assert(inst[i].opcode == BRW_OPCODE_MUL); - brw_MUL(p, retype(g0, inst[i].dst_type), + assert(inst[i].opcode == ELK_OPCODE_MUL); + elk_MUL(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type), retype(zero, inst[i].src_type)); } - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); - brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subreg); - brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].src_subreg); + elk_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subreg); + elk_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].src_subreg); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src_vstride); - brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); - brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); + elk_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src_vstride); + elk_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); + elk_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); if (devinfo.platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(&devinfo)) { @@ -2405,14 +2405,14 @@ TEST_P(validation_test, qword_low_power_align1_regioning_restrictions) TEST_P(validation_test, qword_low_power_no_indirect_addressing) { static const struct { - enum opcode opcode; + enum elk_opcode opcode; unsigned exec_size; - enum brw_reg_type dst_type; + enum elk_reg_type dst_type; bool dst_is_indirect; unsigned dst_stride; - enum brw_reg_type src_type; + enum elk_reg_type src_type; bool src_is_indirect; unsigned src_vstride; unsigned src_width; @@ -2424,16 +2424,16 @@ TEST_P(validation_test, qword_low_power_no_indirect_addressing) src_type, src_is_indirect, src_vstride, src_width, src_hstride, \ expected_result) \ { \ - BRW_OPCODE_##opcode, \ - BRW_EXECUTE_##exec_size, \ - BRW_REGISTER_TYPE_##dst_type, \ + ELK_OPCODE_##opcode, \ + ELK_EXECUTE_##exec_size, \ + ELK_REGISTER_TYPE_##dst_type, \ dst_is_indirect, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ - BRW_REGISTER_TYPE_##src_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_REGISTER_TYPE_##src_type, \ src_is_indirect, \ - BRW_VERTICAL_STRIDE_##src_vstride, \ - BRW_WIDTH_##src_width, \ - BRW_HORIZONTAL_STRIDE_##src_hstride, \ + ELK_VERTICAL_STRIDE_##src_vstride, \ + ELK_WIDTH_##src_width, \ + ELK_HORIZONTAL_STRIDE_##src_hstride, \ expected_result, \ } @@ -2493,36 +2493,36 @@ TEST_P(validation_test, qword_low_power_no_indirect_addressing) for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { if (!devinfo.has_64bit_float && - (inst[i].dst_type == BRW_REGISTER_TYPE_DF || - inst[i].src_type == BRW_REGISTER_TYPE_DF)) + (inst[i].dst_type == ELK_REGISTER_TYPE_DF || + inst[i].src_type == ELK_REGISTER_TYPE_DF)) continue; if (!devinfo.has_64bit_int && - (inst[i].dst_type == BRW_REGISTER_TYPE_Q || - inst[i].dst_type == BRW_REGISTER_TYPE_UQ || - inst[i].src_type == BRW_REGISTER_TYPE_Q || - inst[i].src_type == BRW_REGISTER_TYPE_UQ)) + (inst[i].dst_type == ELK_REGISTER_TYPE_Q || + inst[i].dst_type == ELK_REGISTER_TYPE_UQ || + inst[i].src_type == ELK_REGISTER_TYPE_Q || + inst[i].src_type == ELK_REGISTER_TYPE_UQ)) continue; - if (inst[i].opcode == BRW_OPCODE_MOV) { - brw_MOV(p, retype(g0, inst[i].dst_type), + if (inst[i].opcode == ELK_OPCODE_MOV) { + elk_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type)); } else { - assert(inst[i].opcode == BRW_OPCODE_MUL); - brw_MUL(p, retype(g0, inst[i].dst_type), + assert(inst[i].opcode == ELK_OPCODE_MUL); + elk_MUL(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type), retype(zero, inst[i].src_type)); } - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); - brw_inst_set_dst_address_mode(&devinfo, last_inst, inst[i].dst_is_indirect); - brw_inst_set_src0_address_mode(&devinfo, last_inst, inst[i].src_is_indirect); + elk_inst_set_dst_address_mode(&devinfo, last_inst, inst[i].dst_is_indirect); + elk_inst_set_src0_address_mode(&devinfo, last_inst, inst[i].src_is_indirect); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src_vstride); - brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); - brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); + elk_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src_vstride); + elk_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); + elk_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); if (devinfo.platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(&devinfo)) { @@ -2538,15 +2538,15 @@ TEST_P(validation_test, qword_low_power_no_indirect_addressing) TEST_P(validation_test, qword_low_power_no_64bit_arf) { static const struct { - enum opcode opcode; + enum elk_opcode opcode; unsigned exec_size; - struct brw_reg dst; - enum brw_reg_type dst_type; + struct elk_reg dst; + enum elk_reg_type dst_type; unsigned dst_stride; - struct brw_reg src; - enum brw_reg_type src_type; + struct elk_reg src; + enum elk_reg_type src_type; unsigned src_vstride; unsigned src_width; unsigned src_hstride; @@ -2558,16 +2558,16 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf) src, src_type, src_vstride, src_width, src_hstride, \ acc_wr, expected_result) \ { \ - BRW_OPCODE_##opcode, \ - BRW_EXECUTE_##exec_size, \ + ELK_OPCODE_##opcode, \ + ELK_EXECUTE_##exec_size, \ dst, \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ src, \ - BRW_REGISTER_TYPE_##src_type, \ - BRW_VERTICAL_STRIDE_##src_vstride, \ - BRW_WIDTH_##src_width, \ - BRW_HORIZONTAL_STRIDE_##src_hstride, \ + ELK_REGISTER_TYPE_##src_type, \ + ELK_VERTICAL_STRIDE_##src_vstride, \ + ELK_WIDTH_##src_width, \ + ELK_HORIZONTAL_STRIDE_##src_hstride, \ acc_wr, \ expected_result, \ } @@ -2642,35 +2642,35 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf) for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { if (!devinfo.has_64bit_float && - (inst[i].dst_type == BRW_REGISTER_TYPE_DF || - inst[i].src_type == BRW_REGISTER_TYPE_DF)) + (inst[i].dst_type == ELK_REGISTER_TYPE_DF || + inst[i].src_type == ELK_REGISTER_TYPE_DF)) continue; if (!devinfo.has_64bit_int && - (inst[i].dst_type == BRW_REGISTER_TYPE_Q || - inst[i].dst_type == BRW_REGISTER_TYPE_UQ || - inst[i].src_type == BRW_REGISTER_TYPE_Q || - inst[i].src_type == BRW_REGISTER_TYPE_UQ)) + (inst[i].dst_type == ELK_REGISTER_TYPE_Q || + inst[i].dst_type == ELK_REGISTER_TYPE_UQ || + inst[i].src_type == ELK_REGISTER_TYPE_Q || + inst[i].src_type == ELK_REGISTER_TYPE_UQ)) continue; - if (inst[i].opcode == BRW_OPCODE_MOV) { - brw_MOV(p, retype(inst[i].dst, inst[i].dst_type), + if (inst[i].opcode == ELK_OPCODE_MOV) { + elk_MOV(p, retype(inst[i].dst, inst[i].dst_type), retype(inst[i].src, inst[i].src_type)); } else { - assert(inst[i].opcode == BRW_OPCODE_MUL); - brw_MUL(p, retype(inst[i].dst, inst[i].dst_type), + assert(inst[i].opcode == ELK_OPCODE_MUL); + elk_MUL(p, retype(inst[i].dst, inst[i].dst_type), retype(inst[i].src, inst[i].src_type), retype(zero, inst[i].src_type)); - brw_inst_set_opcode(&isa, last_inst, inst[i].opcode); + elk_inst_set_opcode(&isa, last_inst, inst[i].opcode); } - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); - brw_inst_set_acc_wr_control(&devinfo, last_inst, inst[i].acc_wr); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_acc_wr_control(&devinfo, last_inst, inst[i].acc_wr); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src_vstride); - brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); - brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); + elk_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src_vstride); + elk_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); + elk_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); /* Note: The Broadwell PRM also lists the restriction that destination * of DWord multiplication cannot be the accumulator. @@ -2678,9 +2678,9 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf) if (devinfo.platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(&devinfo) || (devinfo.ver == 8 && - inst[i].opcode == BRW_OPCODE_MUL && - brw_inst_dst_reg_file(&devinfo, last_inst) == BRW_ARCHITECTURE_REGISTER_FILE && - brw_inst_dst_da_reg_nr(&devinfo, last_inst) != BRW_ARF_NULL)) { + inst[i].opcode == ELK_OPCODE_MUL && + elk_inst_dst_reg_file(&devinfo, last_inst) == ELK_ARCHITECTURE_REGISTER_FILE && + elk_inst_dst_da_reg_nr(&devinfo, last_inst) != ELK_ARF_NULL)) { EXPECT_EQ(inst[i].expected_result, validate(p)); } else { EXPECT_TRUE(validate(p)); @@ -2693,9 +2693,9 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf) return; /* MAC implicitly reads the accumulator */ - brw_MAC(p, retype(g0, BRW_REGISTER_TYPE_DF), - retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF), - retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF)); + elk_MAC(p, retype(g0, ELK_REGISTER_TYPE_DF), + retype(stride(g0, 4, 4, 1), ELK_REGISTER_TYPE_DF), + retype(stride(g0, 4, 4, 1), ELK_REGISTER_TYPE_DF)); if (devinfo.platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(&devinfo)) { EXPECT_FALSE(validate(p)); @@ -2707,20 +2707,20 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf) TEST_P(validation_test, align16_64_bit_integer) { static const struct { - enum opcode opcode; + enum elk_opcode opcode; unsigned exec_size; - enum brw_reg_type dst_type; - enum brw_reg_type src_type; + enum elk_reg_type dst_type; + enum elk_reg_type src_type; bool expected_result; } inst[] = { #define INST(opcode, exec_size, dst_type, src_type, expected_result) \ { \ - BRW_OPCODE_##opcode, \ - BRW_EXECUTE_##exec_size, \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src_type, \ + ELK_OPCODE_##opcode, \ + ELK_EXECUTE_##exec_size, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src_type, \ expected_result, \ } @@ -2758,19 +2758,19 @@ TEST_P(validation_test, align16_64_bit_integer) if (devinfo.ver >= 11) return; - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - if (inst[i].opcode == BRW_OPCODE_MOV) { - brw_MOV(p, retype(g0, inst[i].dst_type), + if (inst[i].opcode == ELK_OPCODE_MOV) { + elk_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type)); } else { - assert(inst[i].opcode == BRW_OPCODE_ADD); - brw_ADD(p, retype(g0, inst[i].dst_type), + assert(inst[i].opcode == ELK_OPCODE_ADD); + elk_ADD(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type), retype(g0, inst[i].src_type)); } - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); EXPECT_EQ(inst[i].expected_result, validate(p)); @@ -2781,13 +2781,13 @@ TEST_P(validation_test, align16_64_bit_integer) TEST_P(validation_test, qword_low_power_no_depctrl) { static const struct { - enum opcode opcode; + enum elk_opcode opcode; unsigned exec_size; - enum brw_reg_type dst_type; + enum elk_reg_type dst_type; unsigned dst_stride; - enum brw_reg_type src_type; + enum elk_reg_type src_type; unsigned src_vstride; unsigned src_width; unsigned src_hstride; @@ -2801,14 +2801,14 @@ TEST_P(validation_test, qword_low_power_no_depctrl) src_type, src_vstride, src_width, src_hstride, \ no_dd_check, no_dd_clear, expected_result) \ { \ - BRW_OPCODE_##opcode, \ - BRW_EXECUTE_##exec_size, \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_HORIZONTAL_STRIDE_##dst_stride, \ - BRW_REGISTER_TYPE_##src_type, \ - BRW_VERTICAL_STRIDE_##src_vstride, \ - BRW_WIDTH_##src_width, \ - BRW_HORIZONTAL_STRIDE_##src_hstride, \ + ELK_OPCODE_##opcode, \ + ELK_EXECUTE_##exec_size, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_HORIZONTAL_STRIDE_##dst_stride, \ + ELK_REGISTER_TYPE_##src_type, \ + ELK_VERTICAL_STRIDE_##src_vstride, \ + ELK_WIDTH_##src_width, \ + ELK_HORIZONTAL_STRIDE_##src_hstride, \ no_dd_check, \ no_dd_clear, \ expected_result, \ @@ -2868,36 +2868,36 @@ TEST_P(validation_test, qword_low_power_no_depctrl) for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { if (!devinfo.has_64bit_float && - (inst[i].dst_type == BRW_REGISTER_TYPE_DF || - inst[i].src_type == BRW_REGISTER_TYPE_DF)) + (inst[i].dst_type == ELK_REGISTER_TYPE_DF || + inst[i].src_type == ELK_REGISTER_TYPE_DF)) continue; if (!devinfo.has_64bit_int && - (inst[i].dst_type == BRW_REGISTER_TYPE_Q || - inst[i].dst_type == BRW_REGISTER_TYPE_UQ || - inst[i].src_type == BRW_REGISTER_TYPE_Q || - inst[i].src_type == BRW_REGISTER_TYPE_UQ)) + (inst[i].dst_type == ELK_REGISTER_TYPE_Q || + inst[i].dst_type == ELK_REGISTER_TYPE_UQ || + inst[i].src_type == ELK_REGISTER_TYPE_Q || + inst[i].src_type == ELK_REGISTER_TYPE_UQ)) continue; - if (inst[i].opcode == BRW_OPCODE_MOV) { - brw_MOV(p, retype(g0, inst[i].dst_type), + if (inst[i].opcode == ELK_OPCODE_MOV) { + elk_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type)); } else { - assert(inst[i].opcode == BRW_OPCODE_MUL); - brw_MUL(p, retype(g0, inst[i].dst_type), + assert(inst[i].opcode == ELK_OPCODE_MUL); + elk_MUL(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type), retype(zero, inst[i].src_type)); } - brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); + elk_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); - brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); + elk_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src_vstride); - brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); - brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); + elk_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src_vstride); + elk_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); + elk_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); - brw_inst_set_no_dd_check(&devinfo, last_inst, inst[i].no_dd_check); - brw_inst_set_no_dd_clear(&devinfo, last_inst, inst[i].no_dd_clear); + elk_inst_set_no_dd_check(&devinfo, last_inst, inst[i].no_dd_check); + elk_inst_set_no_dd_clear(&devinfo, last_inst, inst[i].no_dd_clear); if (devinfo.platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(&devinfo)) { @@ -2913,12 +2913,12 @@ TEST_P(validation_test, qword_low_power_no_depctrl) TEST_P(validation_test, gfx11_no_byte_src_1_2) { static const struct { - enum opcode opcode; + enum elk_opcode opcode; unsigned access_mode; - enum brw_reg_type dst_type; + enum elk_reg_type dst_type; struct { - enum brw_reg_type type; + enum elk_reg_type type; unsigned vstride; unsigned width; unsigned hstride; @@ -2933,24 +2933,24 @@ TEST_P(validation_test, gfx11_no_byte_src_1_2) src2_type, \ gfx_ver, expected_result) \ { \ - BRW_OPCODE_##opcode, \ - BRW_ALIGN_##access_mode, \ - BRW_REGISTER_TYPE_##dst_type, \ + ELK_OPCODE_##opcode, \ + ELK_ALIGN_##access_mode, \ + ELK_REGISTER_TYPE_##dst_type, \ { \ { \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_VERTICAL_STRIDE_##src0_vstride, \ - BRW_WIDTH_##src0_width, \ - BRW_HORIZONTAL_STRIDE_##src0_hstride, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_VERTICAL_STRIDE_##src0_vstride, \ + ELK_WIDTH_##src0_width, \ + ELK_HORIZONTAL_STRIDE_##src0_hstride, \ }, \ { \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_VERTICAL_STRIDE_##src1_vstride, \ - BRW_WIDTH_##src1_width, \ - BRW_HORIZONTAL_STRIDE_##src1_hstride, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_VERTICAL_STRIDE_##src1_vstride, \ + ELK_WIDTH_##src1_width, \ + ELK_HORIZONTAL_STRIDE_##src1_hstride, \ }, \ { \ - BRW_REGISTER_TYPE_##src2_type, \ + ELK_REGISTER_TYPE_##src2_type, \ }, \ }, \ gfx_ver, \ @@ -2981,49 +2981,49 @@ TEST_P(validation_test, gfx11_no_byte_src_1_2) if (devinfo.ver != inst[i].gfx_ver) continue; - brw_push_insn_state(p); + elk_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_set_default_access_mode(p, inst[i].access_mode); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_set_default_access_mode(p, inst[i].access_mode); switch (inst[i].opcode) { - case BRW_OPCODE_MOV: - brw_MOV(p, retype(g0, inst[i].dst_type), + case ELK_OPCODE_MOV: + elk_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].srcs[0].type)); - brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].srcs[0].vstride); - brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); + elk_inst_set_src0_vstride(&devinfo, last_inst, inst[i].srcs[0].vstride); + elk_inst_set_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); break; - case BRW_OPCODE_ADD: - brw_ADD(p, retype(g0, inst[i].dst_type), + case ELK_OPCODE_ADD: + elk_ADD(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].srcs[0].type), retype(g0, inst[i].srcs[1].type)); - brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].srcs[0].vstride); - brw_inst_set_src0_width(&devinfo, last_inst, inst[i].srcs[0].width); - brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); - brw_inst_set_src1_vstride(&devinfo, last_inst, inst[i].srcs[1].vstride); - brw_inst_set_src1_width(&devinfo, last_inst, inst[i].srcs[1].width); - brw_inst_set_src1_hstride(&devinfo, last_inst, inst[i].srcs[1].hstride); + elk_inst_set_src0_vstride(&devinfo, last_inst, inst[i].srcs[0].vstride); + elk_inst_set_src0_width(&devinfo, last_inst, inst[i].srcs[0].width); + elk_inst_set_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); + elk_inst_set_src1_vstride(&devinfo, last_inst, inst[i].srcs[1].vstride); + elk_inst_set_src1_width(&devinfo, last_inst, inst[i].srcs[1].width); + elk_inst_set_src1_hstride(&devinfo, last_inst, inst[i].srcs[1].hstride); break; - case BRW_OPCODE_MAD: - brw_MAD(p, retype(g0, inst[i].dst_type), + case ELK_OPCODE_MAD: + elk_MAD(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].srcs[0].type), retype(g0, inst[i].srcs[1].type), retype(g0, inst[i].srcs[2].type)); - brw_inst_set_3src_a1_src0_vstride(&devinfo, last_inst, inst[i].srcs[0].vstride); - brw_inst_set_3src_a1_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); - brw_inst_set_3src_a1_src1_vstride(&devinfo, last_inst, inst[i].srcs[0].vstride); - brw_inst_set_3src_a1_src1_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); + elk_inst_set_3src_a1_src0_vstride(&devinfo, last_inst, inst[i].srcs[0].vstride); + elk_inst_set_3src_a1_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); + elk_inst_set_3src_a1_src1_vstride(&devinfo, last_inst, inst[i].srcs[0].vstride); + elk_inst_set_3src_a1_src1_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); break; default: unreachable("invalid opcode"); } - brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); + elk_inst_set_dst_hstride(&devinfo, last_inst, ELK_HORIZONTAL_STRIDE_1); - brw_inst_set_src0_width(&devinfo, last_inst, inst[i].srcs[0].width); - brw_inst_set_src1_width(&devinfo, last_inst, inst[i].srcs[1].width); + elk_inst_set_src0_width(&devinfo, last_inst, inst[i].srcs[0].width); + elk_inst_set_src1_width(&devinfo, last_inst, inst[i].srcs[1].width); - brw_pop_insn_state(p); + elk_pop_insn_state(p); EXPECT_EQ(inst[i].expected_result, validate(p)); @@ -3034,18 +3034,18 @@ TEST_P(validation_test, gfx11_no_byte_src_1_2) TEST_P(validation_test, add3_source_types) { static const struct { - enum brw_reg_type dst_type; - enum brw_reg_type src0_type; - enum brw_reg_type src1_type; - enum brw_reg_type src2_type; + enum elk_reg_type dst_type; + enum elk_reg_type src0_type; + enum elk_reg_type src1_type; + enum elk_reg_type src2_type; bool expected_result; } inst[] = { #define INST(dst_type, src0_type, src1_type, src2_type, expected_result) \ { \ - BRW_REGISTER_TYPE_##dst_type, \ - BRW_REGISTER_TYPE_##src0_type, \ - BRW_REGISTER_TYPE_##src1_type, \ - BRW_REGISTER_TYPE_##src2_type, \ + ELK_REGISTER_TYPE_##dst_type, \ + ELK_REGISTER_TYPE_##src0_type, \ + ELK_REGISTER_TYPE_##src1_type, \ + ELK_REGISTER_TYPE_##src2_type, \ expected_result, \ } @@ -3071,7 +3071,7 @@ TEST_P(validation_test, add3_source_types) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD3(p, + elk_ADD3(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type), @@ -3086,15 +3086,15 @@ TEST_P(validation_test, add3_source_types) TEST_P(validation_test, add3_immediate_types) { static const struct { - enum brw_reg_type reg_type; - enum brw_reg_type imm_type; + enum elk_reg_type reg_type; + enum elk_reg_type imm_type; unsigned imm_src; bool expected_result; } inst[] = { #define INST(reg_type, imm_type, imm_src, expected_result) \ { \ - BRW_REGISTER_TYPE_##reg_type, \ - BRW_REGISTER_TYPE_##imm_type, \ + ELK_REGISTER_TYPE_##reg_type, \ + ELK_REGISTER_TYPE_##imm_type, \ imm_src, \ expected_result, \ } @@ -3124,12 +3124,12 @@ TEST_P(validation_test, add3_immediate_types) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - brw_ADD3(p, + elk_ADD3(p, retype(g0, inst[i].reg_type), - inst[i].imm_src == 0 ? retype(brw_imm_d(0x1234), inst[i].imm_type) + inst[i].imm_src == 0 ? retype(elk_imm_d(0x1234), inst[i].imm_type) : retype(g0, inst[i].reg_type), retype(g0, inst[i].reg_type), - inst[i].imm_src == 2 ? retype(brw_imm_d(0x2143), inst[i].imm_type) + inst[i].imm_src == 2 ? retype(elk_imm_d(0x2143), inst[i].imm_type) : retype(g0, inst[i].reg_type)); EXPECT_EQ(inst[i].expected_result, validate(p)); @@ -3143,23 +3143,23 @@ TEST_P(validation_test, dpas_sdepth) if (devinfo.verx10 < 125) return; - static const enum gfx12_systolic_depth depth[] = { - BRW_SYSTOLIC_DEPTH_16, - BRW_SYSTOLIC_DEPTH_2, - BRW_SYSTOLIC_DEPTH_4, - BRW_SYSTOLIC_DEPTH_8, + static const enum elk_gfx12_systolic_depth depth[] = { + ELK_SYSTOLIC_DEPTH_16, + ELK_SYSTOLIC_DEPTH_2, + ELK_SYSTOLIC_DEPTH_4, + ELK_SYSTOLIC_DEPTH_8, }; for (unsigned i = 0; i < ARRAY_SIZE(depth); i++) { - brw_DPAS(p, + elk_DPAS(p, depth[i], 8, - retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_F), + retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_F), null, - retype(brw_vec8_grf(16, 0), BRW_REGISTER_TYPE_HF), - retype(brw_vec8_grf(32, 0), BRW_REGISTER_TYPE_HF)); + retype(elk_vec8_grf(16, 0), ELK_REGISTER_TYPE_HF), + retype(elk_vec8_grf(32, 0), ELK_REGISTER_TYPE_HF)); - const bool expected_result = depth[i] == BRW_SYSTOLIC_DEPTH_8; + const bool expected_result = depth[i] == ELK_SYSTOLIC_DEPTH_8; EXPECT_EQ(expected_result, validate(p)) << "Encoded systolic depth value is: " << depth[i]; @@ -3173,27 +3173,27 @@ TEST_P(validation_test, dpas_exec_size) if (devinfo.verx10 < 125) return; - static const enum brw_execution_size test_vectors[] = { - BRW_EXECUTE_1, - BRW_EXECUTE_2, - BRW_EXECUTE_4, - BRW_EXECUTE_8, - BRW_EXECUTE_16, - BRW_EXECUTE_32, + static const enum elk_execution_size test_vectors[] = { + ELK_EXECUTE_1, + ELK_EXECUTE_2, + ELK_EXECUTE_4, + ELK_EXECUTE_8, + ELK_EXECUTE_16, + ELK_EXECUTE_32, }; for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) { - brw_set_default_exec_size(p, test_vectors[i]); + elk_set_default_exec_size(p, test_vectors[i]); - brw_DPAS(p, - BRW_SYSTOLIC_DEPTH_8, + elk_DPAS(p, + ELK_SYSTOLIC_DEPTH_8, 8, - retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_F), + retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_F), null, - retype(brw_vec8_grf(16, 0), BRW_REGISTER_TYPE_HF), - retype(brw_vec8_grf(32, 0), BRW_REGISTER_TYPE_HF)); + retype(elk_vec8_grf(16, 0), ELK_REGISTER_TYPE_HF), + retype(elk_vec8_grf(32, 0), ELK_REGISTER_TYPE_HF)); - const bool expected_result = test_vectors[i] == BRW_EXECUTE_8; + const bool expected_result = test_vectors[i] == ELK_EXECUTE_8; EXPECT_EQ(expected_result, validate(p)) << "Exec size = " << (1u << test_vectors[i]); @@ -3201,7 +3201,7 @@ TEST_P(validation_test, dpas_exec_size) clear_instructions(p); } - brw_set_default_exec_size(p, BRW_EXECUTE_8); + elk_set_default_exec_size(p, ELK_EXECUTE_8); } TEST_P(validation_test, dpas_sub_byte_precision) @@ -3210,114 +3210,114 @@ TEST_P(validation_test, dpas_sub_byte_precision) return; static const struct { - brw_reg_type dst_type; - brw_reg_type src0_type; - brw_reg_type src1_type; + elk_reg_type dst_type; + elk_reg_type src0_type; + elk_reg_type src1_type; enum gfx12_sub_byte_precision src1_prec; - brw_reg_type src2_type; + elk_reg_type src2_type; enum gfx12_sub_byte_precision src2_prec; bool expected_result; } test_vectors[] = { { - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_NONE, true, }, { - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_4BIT, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_4BIT, false, }, { - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_2BIT, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_2BIT, false, }, { - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_4BIT, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_4BIT, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_NONE, false, }, { - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_2BIT, - BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_2BIT, + ELK_REGISTER_TYPE_HF, ELK_SUB_BYTE_PRECISION_NONE, false, }, { - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_NONE, true, }, { - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_4BIT, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_4BIT, true, }, { - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_2BIT, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_2BIT, true, }, { - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE, - BRW_REGISTER_TYPE_UB, (enum gfx12_sub_byte_precision) 3, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_UB, (enum gfx12_sub_byte_precision) 3, false, }, { - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_4BIT, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_4BIT, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_NONE, true, }, { - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_2BIT, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_2BIT, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_NONE, true, }, { - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UD, - BRW_REGISTER_TYPE_UB, (enum gfx12_sub_byte_precision) 3, - BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UD, + ELK_REGISTER_TYPE_UB, (enum gfx12_sub_byte_precision) 3, + ELK_REGISTER_TYPE_UB, ELK_SUB_BYTE_PRECISION_NONE, false, }, }; for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) { - brw_inst *inst = - brw_DPAS(p, - BRW_SYSTOLIC_DEPTH_8, + elk_inst *inst = + elk_DPAS(p, + ELK_SYSTOLIC_DEPTH_8, 8, - retype(brw_vec8_grf(0, 0), test_vectors[i].dst_type), - retype(brw_vec8_grf(16, 0), test_vectors[i].src0_type), - retype(brw_vec8_grf(32, 0), test_vectors[i].src1_type), - retype(brw_vec8_grf(48, 0), test_vectors[i].src2_type)); + retype(elk_vec8_grf(0, 0), test_vectors[i].dst_type), + retype(elk_vec8_grf(16, 0), test_vectors[i].src0_type), + retype(elk_vec8_grf(32, 0), test_vectors[i].src1_type), + retype(elk_vec8_grf(48, 0), test_vectors[i].src2_type)); - brw_inst_set_dpas_3src_src1_subbyte(&devinfo, inst, + elk_inst_set_dpas_3src_src1_subbyte(&devinfo, inst, test_vectors[i].src1_prec); - brw_inst_set_dpas_3src_src2_subbyte(&devinfo, inst, + elk_inst_set_dpas_3src_src2_subbyte(&devinfo, inst, test_vectors[i].src2_prec); EXPECT_EQ(test_vectors[i].expected_result, validate(p)) << @@ -3333,15 +3333,15 @@ TEST_P(validation_test, dpas_types) return; #define TV(a, b, c, d, r) \ - { BRW_REGISTER_TYPE_ ## a, BRW_REGISTER_TYPE_ ## b, \ - BRW_REGISTER_TYPE_ ## c, BRW_REGISTER_TYPE_ ## d, \ + { ELK_REGISTER_TYPE_ ## a, ELK_REGISTER_TYPE_ ## b, \ + ELK_REGISTER_TYPE_ ## c, ELK_REGISTER_TYPE_ ## d, \ r } static const struct { - brw_reg_type dst_type; - brw_reg_type src0_type; - brw_reg_type src1_type; - brw_reg_type src2_type; + elk_reg_type dst_type; + elk_reg_type src0_type; + elk_reg_type src1_type; + elk_reg_type src2_type; bool expected_result; } test_vectors[] = { TV( F, F, HF, HF, true), @@ -3400,13 +3400,13 @@ TEST_P(validation_test, dpas_types) #undef TV for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) { - brw_DPAS(p, - BRW_SYSTOLIC_DEPTH_8, + elk_DPAS(p, + ELK_SYSTOLIC_DEPTH_8, 8, - retype(brw_vec8_grf(0, 0), test_vectors[i].dst_type), - retype(brw_vec8_grf(16, 0), test_vectors[i].src0_type), - retype(brw_vec8_grf(32, 0), test_vectors[i].src1_type), - retype(brw_vec8_grf(48, 0), test_vectors[i].src2_type)); + retype(elk_vec8_grf(0, 0), test_vectors[i].dst_type), + retype(elk_vec8_grf(16, 0), test_vectors[i].src0_type), + retype(elk_vec8_grf(32, 0), test_vectors[i].src1_type), + retype(elk_vec8_grf(48, 0), test_vectors[i].src2_type)); EXPECT_EQ(test_vectors[i].expected_result, validate(p)) << "test vector index = " << i; @@ -3421,17 +3421,17 @@ TEST_P(validation_test, dpas_src_subreg_nr) return; #define TV(dt, od, t0, o0, t1, o1, o2, r) { \ - BRW_REGISTER_TYPE_ ## dt, od, \ - BRW_REGISTER_TYPE_ ## t0, o0, \ - BRW_REGISTER_TYPE_ ## t1, o1, o2, \ + ELK_REGISTER_TYPE_ ## dt, od, \ + ELK_REGISTER_TYPE_ ## t0, o0, \ + ELK_REGISTER_TYPE_ ## t1, o1, o2, \ r } static const struct { - brw_reg_type dst_type; + elk_reg_type dst_type; unsigned dst_subnr; - brw_reg_type src0_type; + elk_reg_type src0_type; unsigned src0_subnr; - brw_reg_type src1_src2_type; + elk_reg_type src1_src2_type; unsigned src1_subnr; unsigned src2_subnr; bool expected_result; @@ -3491,7 +3491,7 @@ TEST_P(validation_test, dpas_src_subreg_nr) /* These meet the requirements, but they specify a subnr that is part of * the next register. It is currently not possible to specify a subnr of - * 32 for the B and UB values because brw_reg::subnr is only 5 bits. + * 32 for the B and UB values because elk_reg::subnr is only 5 bits. */ TV( F, 16, F, 0, HF, 0, 0, false), TV( F, 0, F, 16, HF, 0, 0, false), @@ -3504,14 +3504,14 @@ TEST_P(validation_test, dpas_src_subreg_nr) #undef TV for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) { - struct brw_reg dst = - retype(brw_vec8_grf( 0, 0), test_vectors[i].dst_type); - struct brw_reg src0 = - retype(brw_vec8_grf(16, 0), test_vectors[i].src0_type); - struct brw_reg src1 = - retype(brw_vec8_grf(32, 0), test_vectors[i].src1_src2_type); - struct brw_reg src2 = - retype(brw_vec8_grf(48, 0), test_vectors[i].src1_src2_type); + struct elk_reg dst = + retype(elk_vec8_grf( 0, 0), test_vectors[i].dst_type); + struct elk_reg src0 = + retype(elk_vec8_grf(16, 0), test_vectors[i].src0_type); + struct elk_reg src1 = + retype(elk_vec8_grf(32, 0), test_vectors[i].src1_src2_type); + struct elk_reg src2 = + retype(elk_vec8_grf(48, 0), test_vectors[i].src1_src2_type); /* subnr for DPAS is in units of datatype precision instead of bytes as * it is for every other instruction. Set the value by hand instead of @@ -3522,7 +3522,7 @@ TEST_P(validation_test, dpas_src_subreg_nr) src1.subnr = test_vectors[i].src1_subnr; src2.subnr = test_vectors[i].src2_subnr; - brw_DPAS(p, BRW_SYSTOLIC_DEPTH_8, 8, dst, src0, src1, src2); + elk_DPAS(p, ELK_SYSTOLIC_DEPTH_8, 8, dst, src0, src1, src2); EXPECT_EQ(test_vectors[i].expected_result, validate(p)) << "test vector index = " << i; diff --git a/src/intel/compiler/elk/elk_test_fs_cmod_propagation.cpp b/src/intel/compiler/elk/elk_test_fs_cmod_propagation.cpp index 7c35541e9e0..7d09320c8ff 100644 --- a/src/intel/compiler/elk/elk_test_fs_cmod_propagation.cpp +++ b/src/intel/compiler/elk/elk_test_fs_cmod_propagation.cpp @@ -33,35 +33,35 @@ protected: cmod_propagation_test(); ~cmod_propagation_test() override; - struct brw_compiler *compiler; - struct brw_compile_params params; + struct elk_compiler *compiler; + struct elk_compile_params params; struct intel_device_info *devinfo; void *ctx; - struct brw_wm_prog_data *prog_data; + struct elk_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; - fs_visitor *v; + elk_fs_visitor *v; fs_builder bld; - void test_mov_prop(enum brw_conditional_mod cmod, - enum brw_reg_type add_type, - enum brw_reg_type mov_dst_type, + void test_mov_prop(enum elk_conditional_mod cmod, + enum elk_reg_type add_type, + enum elk_reg_type mov_dst_type, bool expected_cmod_prop_progress); - void test_saturate_prop(enum brw_conditional_mod before, - enum opcode op, - enum brw_reg_type add_type, - enum brw_reg_type op_type, + void test_saturate_prop(enum elk_conditional_mod before, + enum elk_opcode op, + enum elk_reg_type add_type, + enum elk_reg_type op_type, bool expected_cmod_prop_progress); }; -class cmod_propagation_fs_visitor : public fs_visitor +class cmod_propagation_fs_visitor : public elk_fs_visitor { public: - cmod_propagation_fs_visitor(struct brw_compiler *compiler, - struct brw_compile_params *params, - struct brw_wm_prog_data *prog_data, + cmod_propagation_fs_visitor(struct elk_compiler *compiler, + struct elk_compile_params *params, + struct elk_wm_prog_data *prog_data, nir_shader *shader) - : fs_visitor(compiler, params, NULL, + : elk_fs_visitor(compiler, params, NULL, &prog_data->base, shader, 8, false, false) {} }; @@ -70,14 +70,14 @@ cmod_propagation_test::cmod_propagation_test() : bld(NULL, 0) { ctx = ralloc_context(NULL); - compiler = rzalloc(ctx, struct brw_compiler); + compiler = rzalloc(ctx, struct elk_compiler); devinfo = rzalloc(ctx, struct intel_device_info); compiler->devinfo = devinfo; params = {}; params.mem_ctx = ctx; - prog_data = ralloc(ctx, struct brw_wm_prog_data); + prog_data = ralloc(ctx, struct elk_wm_prog_data); nir_shader *shader = nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL); @@ -98,18 +98,18 @@ cmod_propagation_test::~cmod_propagation_test() ctx = NULL; } -static fs_inst * -instruction(bblock_t *block, int num) +static elk_fs_inst * +instruction(elk_bblock_t *block, int num) { - fs_inst *inst = (fs_inst *)block->start(); + elk_fs_inst *inst = (elk_fs_inst *)block->start(); for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; + inst = (elk_fs_inst *)inst->next; } return inst; } static bool -cmod_propagation(fs_visitor *v) +cmod_propagation(elk_fs_visitor *v) { const bool print = getenv("TEST_DEBUG"); @@ -130,12 +130,12 @@ cmod_propagation(fs_visitor *v) TEST_F(cmod_propagation_test, basic) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -147,7 +147,7 @@ TEST_F(cmod_propagation_test, basic) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -155,18 +155,18 @@ TEST_F(cmod_propagation_test, basic) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, basic_other_flag) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE) + bld.CMP(bld.null_reg_f(), dest, zero, ELK_CONDITIONAL_GE) ->flag_subreg = 1; /* = Before = @@ -179,7 +179,7 @@ TEST_F(cmod_propagation_test, basic_other_flag) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -187,19 +187,19 @@ TEST_F(cmod_propagation_test, basic_other_flag) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(1, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_nonzero) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg nonzero(brw_imm_f(1.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg nonzero(elk_imm_f(1.0f)); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), dest, nonzero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest, nonzero, ELK_CONDITIONAL_GE); /* = Before = * @@ -211,7 +211,7 @@ TEST_F(cmod_propagation_test, cmp_nonzero) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -219,18 +219,18 @@ TEST_F(cmod_propagation_test, cmp_nonzero) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, non_cmod_instruction) { - fs_reg dest = v->vgrf(glsl_uint_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg zero(brw_imm_ud(0u)); + elk_fs_reg dest = v->vgrf(glsl_uint_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg zero(elk_imm_ud(0u)); bld.FBL(dest, src0); - bld.CMP(bld.null_reg_ud(), dest, zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_ud(), dest, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -242,7 +242,7 @@ TEST_F(cmod_propagation_test, non_cmod_instruction) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -250,17 +250,17 @@ TEST_F(cmod_propagation_test, non_cmod_instruction) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_FBL, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_FBL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, non_cmod_livechannel) { - fs_reg dest = v->vgrf(glsl_uint_type()); - fs_reg zero(brw_imm_d(0)); - bld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, dest)->exec_size = 32; - bld.CMP(bld.null_reg_d(), dest, zero, BRW_CONDITIONAL_Z)->exec_size = 32; + elk_fs_reg dest = v->vgrf(glsl_uint_type()); + elk_fs_reg zero(elk_imm_d(0)); + bld.emit(ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, dest)->exec_size = 32; + bld.CMP(bld.null_reg_d(), dest, zero, ELK_CONDITIONAL_Z)->exec_size = 32; /* = Before = * @@ -273,7 +273,7 @@ TEST_F(cmod_propagation_test, non_cmod_livechannel) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -281,21 +281,21 @@ TEST_F(cmod_propagation_test, non_cmod_livechannel) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(SHADER_OPCODE_FIND_LIVE_CHANNEL, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, intervening_flag_write) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE); - bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), src2, zero, ELK_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -308,7 +308,7 @@ TEST_F(cmod_propagation_test, intervening_flag_write) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -316,24 +316,24 @@ TEST_F(cmod_propagation_test, intervening_flag_write) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, intervening_mismatch_flag_write) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE) + bld.CMP(bld.null_reg_f(), src2, zero, ELK_CONDITIONAL_GE) ->flag_subreg = 1; - bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -347,7 +347,7 @@ TEST_F(cmod_propagation_test, intervening_mismatch_flag_write) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -355,25 +355,25 @@ TEST_F(cmod_propagation_test, intervening_mismatch_flag_write) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, intervening_flag_read) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest0, src0, src1); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); - bld.CMP(bld.null_reg_f(), dest0, zero, BRW_CONDITIONAL_GE); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); + bld.CMP(bld.null_reg_f(), dest0, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -386,7 +386,7 @@ TEST_F(cmod_propagation_test, intervening_flag_read) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -394,25 +394,25 @@ TEST_F(cmod_propagation_test, intervening_flag_read) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, intervening_mismatch_flag_read) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest0, src0, src1); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) ->flag_subreg = 1; - bld.CMP(bld.null_reg_f(), dest0, zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest0, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -426,7 +426,7 @@ TEST_F(cmod_propagation_test, intervening_mismatch_flag_read) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -434,25 +434,25 @@ TEST_F(cmod_propagation_test, intervening_mismatch_flag_read) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, intervening_dest_write) { - fs_reg dest = v->vgrf(glsl_vec4_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_vec2_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest = v->vgrf(glsl_vec4_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_vec2_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(offset(dest, bld, 2), src0, src1); - bld.emit(SHADER_OPCODE_TEX, dest, src2) + bld.emit(ELK_SHADER_OPCODE_TEX, dest, src2) ->size_written = 4 * REG_SIZE; - bld.CMP(bld.null_reg_f(), offset(dest, bld, 2), zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), offset(dest, bld, 2), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -465,7 +465,7 @@ TEST_F(cmod_propagation_test, intervening_dest_write) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -473,25 +473,25 @@ TEST_F(cmod_propagation_test, intervening_dest_write) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, intervening_flag_read_same_value) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); - set_condmod(BRW_CONDITIONAL_GE, bld.ADD(dest0, src0, src1)); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); - bld.CMP(bld.null_reg_f(), dest0, zero, BRW_CONDITIONAL_GE); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); + set_condmod(ELK_CONDITIONAL_GE, bld.ADD(dest0, src0, src1)); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); + bld.CMP(bld.null_reg_f(), dest0, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -505,7 +505,7 @@ TEST_F(cmod_propagation_test, intervening_flag_read_same_value) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -513,21 +513,21 @@ TEST_F(cmod_propagation_test, intervening_flag_read_same_value) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, negate) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); dest.negate = true; - bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -539,7 +539,7 @@ TEST_F(cmod_propagation_test, negate) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -547,17 +547,17 @@ TEST_F(cmod_propagation_test, negate) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, movnz) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - bld.CMP(dest, src0, src1, BRW_CONDITIONAL_GE); - set_condmod(BRW_CONDITIONAL_NZ, + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + bld.CMP(dest, src0, src1, ELK_CONDITIONAL_GE); + set_condmod(ELK_CONDITIONAL_NZ, bld.MOV(bld.null_reg_f(), dest)); /* = Before = @@ -570,7 +570,7 @@ TEST_F(cmod_propagation_test, movnz) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -578,19 +578,19 @@ TEST_F(cmod_propagation_test, movnz) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, different_types_cmod_with_zero) { - fs_reg dest = v->vgrf(glsl_int_type()); - fs_reg src0 = v->vgrf(glsl_int_type()); - fs_reg src1 = v->vgrf(glsl_int_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest = v->vgrf(glsl_int_type()); + elk_fs_reg src0 = v->vgrf(glsl_int_type()); + elk_fs_reg src1 = v->vgrf(glsl_int_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), retype(dest, BRW_REGISTER_TYPE_F), zero, - BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), retype(dest, ELK_REGISTER_TYPE_F), zero, + ELK_CONDITIONAL_GE); /* = Before = * @@ -602,7 +602,7 @@ TEST_F(cmod_propagation_test, different_types_cmod_with_zero) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -610,20 +610,20 @@ TEST_F(cmod_propagation_test, different_types_cmod_with_zero) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, andnz_one) { - fs_reg dest = v->vgrf(glsl_int_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); - fs_reg one(brw_imm_d(1)); + elk_fs_reg dest = v->vgrf(glsl_int_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); + elk_fs_reg one(elk_imm_d(1)); - bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); - set_condmod(BRW_CONDITIONAL_NZ, + bld.CMP(retype(dest, ELK_REGISTER_TYPE_F), src0, zero, ELK_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_NZ, bld.AND(bld.null_reg_d(), dest, one)); /* = Before = @@ -635,7 +635,7 @@ TEST_F(cmod_propagation_test, andnz_one) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -643,21 +643,21 @@ TEST_F(cmod_propagation_test, andnz_one) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); - EXPECT_TRUE(retype(dest, BRW_REGISTER_TYPE_F) + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_TRUE(retype(dest, ELK_REGISTER_TYPE_F) .equals(instruction(block0, 0)->dst)); } TEST_F(cmod_propagation_test, andnz_non_one) { - fs_reg dest = v->vgrf(glsl_int_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); - fs_reg nonone(brw_imm_d(38)); + elk_fs_reg dest = v->vgrf(glsl_int_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); + elk_fs_reg nonone(elk_imm_d(38)); - bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); - set_condmod(BRW_CONDITIONAL_NZ, + bld.CMP(retype(dest, ELK_REGISTER_TYPE_F), src0, zero, ELK_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_NZ, bld.AND(bld.null_reg_d(), dest, nonone)); /* = Before = @@ -669,7 +669,7 @@ TEST_F(cmod_propagation_test, andnz_non_one) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -677,20 +677,20 @@ TEST_F(cmod_propagation_test, andnz_non_one) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_AND, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_cmpnz) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0)); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0)); - bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); - bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_NZ); + bld.CMP(dst0, src0, zero, ELK_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_f(), dst0, zero, ELK_CONDITIONAL_NZ); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f @@ -701,23 +701,23 @@ TEST_F(cmod_propagation_test, cmp_cmpnz) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_cmpg) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0)); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0)); - bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); - bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_G); + bld.CMP(dst0, src0, zero, ELK_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_f(), dst0, zero, ELK_CONDITIONAL_G); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f @@ -728,25 +728,25 @@ TEST_F(cmod_propagation_test, cmp_cmpg) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_G, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, plnnz_cmpnz) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0)); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0)); - set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); - bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_NZ); + set_condmod(ELK_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); + bld.CMP(bld.null_reg_f(), dst0, zero, ELK_CONDITIONAL_NZ); /* = Before = * 0: pln.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f @@ -757,23 +757,23 @@ TEST_F(cmod_propagation_test, plnnz_cmpnz) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_PLN, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_PLN, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, plnnz_cmpz) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0)); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0)); - set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); - bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_Z); + set_condmod(ELK_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); + bld.CMP(bld.null_reg_f(), dst0, zero, ELK_CONDITIONAL_Z); /* = Before = * 0: pln.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f @@ -784,25 +784,25 @@ TEST_F(cmod_propagation_test, plnnz_cmpz) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_PLN, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_PLN, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, plnnz_sel_cmpz) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0)); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0)); - set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dst1, src0, zero)); - bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_Z); + set_condmod(ELK_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dst1, src0, zero)); + bld.CMP(bld.null_reg_f(), dst0, zero, ELK_CONDITIONAL_Z); /* = Before = * 0: pln.nz.f0.0(8) vgrf0:F, vgrf2:F, 0f @@ -814,28 +814,28 @@ TEST_F(cmod_propagation_test, plnnz_sel_cmpz) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_PLN, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_PLN, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_cmpg_D) { - fs_reg dst0 = v->vgrf(glsl_int_type()); - fs_reg src0 = v->vgrf(glsl_int_type()); - fs_reg zero(brw_imm_d(0)); - fs_reg one(brw_imm_d(1)); + elk_fs_reg dst0 = v->vgrf(glsl_int_type()); + elk_fs_reg src0 = v->vgrf(glsl_int_type()); + elk_fs_reg zero(elk_imm_d(0)); + elk_fs_reg one(elk_imm_d(1)); - bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); - bld.CMP(bld.null_reg_d(), dst0, zero, BRW_CONDITIONAL_G); + bld.CMP(dst0, src0, zero, ELK_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_d(), dst0, zero, ELK_CONDITIONAL_G); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:D, vgrf1:D, 0d @@ -846,25 +846,25 @@ TEST_F(cmod_propagation_test, cmp_cmpg_D) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_G, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_cmpg_UD) { - fs_reg dst0 = v->vgrf(glsl_uint_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg zero(brw_imm_ud(0)); + elk_fs_reg dst0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg zero(elk_imm_ud(0)); - bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); - bld.CMP(bld.null_reg_ud(), dst0, zero, BRW_CONDITIONAL_G); + bld.CMP(dst0, src0, zero, ELK_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_ud(), dst0, zero, ELK_CONDITIONAL_G); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:UD, vgrf1:UD, 0u @@ -875,23 +875,23 @@ TEST_F(cmod_propagation_test, cmp_cmpg_UD) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_cmpl_D) { - fs_reg dst0 = v->vgrf(glsl_int_type()); - fs_reg src0 = v->vgrf(glsl_int_type()); - fs_reg zero(brw_imm_d(0)); + elk_fs_reg dst0 = v->vgrf(glsl_int_type()); + elk_fs_reg src0 = v->vgrf(glsl_int_type()); + elk_fs_reg zero(elk_imm_d(0)); - bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); - bld.CMP(bld.null_reg_d(), dst0, zero, BRW_CONDITIONAL_L); + bld.CMP(dst0, src0, zero, ELK_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_d(), dst0, zero, ELK_CONDITIONAL_L); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:D, vgrf1:D, 0d @@ -902,23 +902,23 @@ TEST_F(cmod_propagation_test, cmp_cmpl_D) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_cmpl_UD) { - fs_reg dst0 = v->vgrf(glsl_uint_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg zero(brw_imm_ud(0)); + elk_fs_reg dst0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg zero(elk_imm_ud(0)); - bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); - bld.CMP(bld.null_reg_ud(), dst0, zero, BRW_CONDITIONAL_L); + bld.CMP(dst0, src0, zero, ELK_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_ud(), dst0, zero, ELK_CONDITIONAL_L); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:UD, vgrf1:UD, 0u @@ -929,26 +929,26 @@ TEST_F(cmod_propagation_test, cmp_cmpl_UD) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, andz_one) { - fs_reg dest = v->vgrf(glsl_int_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); - fs_reg one(brw_imm_d(1)); + elk_fs_reg dest = v->vgrf(glsl_int_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); + elk_fs_reg one(elk_imm_d(1)); - bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); - set_condmod(BRW_CONDITIONAL_Z, + bld.CMP(retype(dest, ELK_REGISTER_TYPE_F), src0, zero, ELK_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_Z, bld.AND(bld.null_reg_d(), dest, one)); /* = Before = @@ -960,7 +960,7 @@ TEST_F(cmod_propagation_test, andz_one) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -968,19 +968,19 @@ TEST_F(cmod_propagation_test, andz_one) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_AND, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, add_not_merge_with_compare) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* The addition and the implicit subtraction in the compare do not compute * related values. @@ -993,7 +993,7 @@ TEST_F(cmod_propagation_test, add_not_merge_with_compare) * (no changes) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1001,19 +1001,19 @@ TEST_F(cmod_propagation_test, add_not_merge_with_compare) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_merge_with_compare) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest, src0, negate(src1)); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* = Before = * 0: add(8) dest:F src0:F -src1:F @@ -1023,7 +1023,7 @@ TEST_F(cmod_propagation_test, subtract_merge_with_compare) * 0: add.l.f0(8) dest:F src0:F -src1:F */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1031,19 +1031,19 @@ TEST_F(cmod_propagation_test, subtract_merge_with_compare) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_immediate_merge_with_compare) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg one(brw_imm_f(1.0f)); - fs_reg negative_one(brw_imm_f(-1.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg one(elk_imm_f(1.0f)); + elk_fs_reg negative_one(elk_imm_f(-1.0f)); bld.ADD(dest, src0, negative_one); - bld.CMP(bld.null_reg_f(), src0, one, BRW_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_f(), src0, one, ELK_CONDITIONAL_NZ); /* = Before = * 0: add(8) dest:F src0:F -1.0f @@ -1053,7 +1053,7 @@ TEST_F(cmod_propagation_test, subtract_immediate_merge_with_compare) * 0: add.nz.f0(8) dest:F src0:F -1.0f */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1061,19 +1061,19 @@ TEST_F(cmod_propagation_test, subtract_immediate_merge_with_compare) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_add) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest0, src0, negate(src1)); bld.ADD(dest1, src0, src1); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F @@ -1085,7 +1085,7 @@ TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_add) * 1: add(8) dest1:F src0:F src1:F */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1093,21 +1093,21 @@ TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_add) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_partial_write) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest0, src0, negate(src1)); - set_predicate(BRW_PREDICATE_NORMAL, bld.ADD(dest1, src0, negate(src1))); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + set_predicate(ELK_PREDICATE_NORMAL, bld.ADD(dest1, src0, negate(src1))); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F @@ -1118,7 +1118,7 @@ TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_partia * (no changes) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1126,23 +1126,23 @@ TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_partia EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 1)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_add) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest0, src0, negate(src1)); - set_condmod(BRW_CONDITIONAL_EQ, bld.ADD(dest1, src0, src1)); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_EQ, bld.ADD(dest1, src0, src1)); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F @@ -1153,7 +1153,7 @@ TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_add) * (no changes) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1161,21 +1161,21 @@ TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_add) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, add_merge_with_compare) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), src0, negate(src1), BRW_CONDITIONAL_L); + bld.CMP(bld.null_reg_f(), src0, negate(src1), ELK_CONDITIONAL_L); /* = Before = * 0: add(8) dest:F src0:F src1:F @@ -1185,7 +1185,7 @@ TEST_F(cmod_propagation_test, add_merge_with_compare) * 0: add.l.f0(8) dest:F src0:F src1:F */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1193,17 +1193,17 @@ TEST_F(cmod_propagation_test, add_merge_with_compare) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, negative_subtract_merge_with_compare) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest, src1, negate(src0)); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* The result of the subtract is the negatiion of the result of the * implicit subtract in the compare, so the condition must change. @@ -1216,7 +1216,7 @@ TEST_F(cmod_propagation_test, negative_subtract_merge_with_compare) * 0: add.g.f0(8) dest:F src0:F -src1:F */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1224,21 +1224,21 @@ TEST_F(cmod_propagation_test, negative_subtract_merge_with_compare) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_G, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_delete_compare) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); - set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))); - set_predicate(BRW_PREDICATE_NORMAL, bld.MOV(dest1, src2)); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))); + set_predicate(ELK_PREDICATE_NORMAL, bld.MOV(dest1, src2)); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* = Before = * 0: add.l.f0(8) dest0:F src0:F -src1:F @@ -1250,7 +1250,7 @@ TEST_F(cmod_propagation_test, subtract_delete_compare) * 1: (+f0) mov(0) dest1:F src2:F */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1258,10 +1258,10 @@ TEST_F(cmod_propagation_test, subtract_delete_compare) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, subtract_delete_compare_other_flag) @@ -1269,16 +1269,16 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_other_flag) /* This test is the same as subtract_delete_compare but it explicitly used * flag f0.1 for the subtraction and the comparison. */ - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); - set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))) + set_condmod(ELK_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))) ->flag_subreg = 1; - set_predicate(BRW_PREDICATE_NORMAL, bld.MOV(dest1, src2)); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L) + set_predicate(ELK_PREDICATE_NORMAL, bld.MOV(dest1, src2)); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L) ->flag_subreg = 1; /* = Before = @@ -1291,7 +1291,7 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_other_flag) * 1: (+f0) mov(0) dest1:F src2:F */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1299,21 +1299,21 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_other_flag) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(1, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, subtract_to_mismatch_flag) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); - set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L) + set_condmod(ELK_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L) ->flag_subreg = 1; /* = Before = @@ -1324,7 +1324,7 @@ TEST_F(cmod_propagation_test, subtract_to_mismatch_flag) * No changes */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1332,25 +1332,25 @@ TEST_F(cmod_propagation_test, subtract_to_mismatch_flag) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_mismatch_flag_write) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest0, src0, negate(src1)); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L) + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L) ->flag_subreg = 1; - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F @@ -1371,7 +1371,7 @@ TEST_F(cmod_propagation_test, * changes its strategy, this test will also need to change. */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1379,28 +1379,28 @@ TEST_F(cmod_propagation_test, EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_mismatch_flag_read) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest0, src0, negate(src1)); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) ->flag_subreg = 1; - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F @@ -1412,7 +1412,7 @@ TEST_F(cmod_propagation_test, * 1: (+f0.1) sel(8) dest1 src2 0.0f */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1420,24 +1420,24 @@ TEST_F(cmod_propagation_test, EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, subtract_delete_compare_derp) { - fs_reg dest0 = v->vgrf(glsl_float_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest0 = v->vgrf(glsl_float_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); - set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest0, src0, negate(src1))); - set_predicate(BRW_PREDICATE_NORMAL, bld.ADD(dest1, negate(src0), src1)); - bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_L, bld.ADD(dest0, src0, negate(src1))); + set_predicate(ELK_PREDICATE_NORMAL, bld.ADD(dest1, negate(src0), src1)); + bld.CMP(bld.null_reg_f(), src0, src1, ELK_CONDITIONAL_L); /* = Before = * 0: add.l.f0(8) dest0:F src0:F -src1:F @@ -1449,7 +1449,7 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_derp) * 1: (+f0) add(0) dest1:F -src0:F src1:F */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1457,21 +1457,21 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_derp) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, signed_unsigned_comparison_mismatch) { - fs_reg dest0 = v->vgrf(glsl_int_type()); - fs_reg src0 = v->vgrf(glsl_int_type()); - src0.type = BRW_REGISTER_TYPE_W; + elk_fs_reg dest0 = v->vgrf(glsl_int_type()); + elk_fs_reg src0 = v->vgrf(glsl_int_type()); + src0.type = ELK_REGISTER_TYPE_W; - bld.ASR(dest0, negate(src0), brw_imm_d(15)); - bld.CMP(bld.null_reg_ud(), retype(dest0, BRW_REGISTER_TYPE_UD), - brw_imm_ud(0u), BRW_CONDITIONAL_LE); + bld.ASR(dest0, negate(src0), elk_imm_d(15)); + bld.CMP(bld.null_reg_ud(), retype(dest0, ELK_REGISTER_TYPE_UD), + elk_imm_ud(0u), ELK_CONDITIONAL_LE); /* = Before = * 0: asr(8) dest:D -src0:W 15D @@ -1481,7 +1481,7 @@ TEST_F(cmod_propagation_test, signed_unsigned_comparison_mismatch) * (no changes) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1489,20 +1489,20 @@ TEST_F(cmod_propagation_test, signed_unsigned_comparison_mismatch) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ASR, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ASR, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_LE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, ior_f2i_nz) { - fs_reg dest = bld.vgrf(BRW_REGISTER_TYPE_D); - fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_D); - fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_D); + elk_fs_reg dest = bld.vgrf(ELK_REGISTER_TYPE_D); + elk_fs_reg src0 = bld.vgrf(ELK_REGISTER_TYPE_D); + elk_fs_reg src1 = bld.vgrf(ELK_REGISTER_TYPE_D); bld.OR(dest, src0, src1); - bld.MOV(bld.null_reg_d(), retype(dest, BRW_REGISTER_TYPE_F)) - ->conditional_mod = BRW_CONDITIONAL_NZ; + bld.MOV(bld.null_reg_d(), retype(dest, ELK_REGISTER_TYPE_F)) + ->conditional_mod = ELK_CONDITIONAL_NZ; /* = Before = * 0: or(8) dest:D src0:D src1:D @@ -1516,7 +1516,7 @@ TEST_F(cmod_propagation_test, ior_f2i_nz) * zero, but after the float-to-integer conversion, the value is zero. */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1524,46 +1524,46 @@ TEST_F(cmod_propagation_test, ior_f2i_nz) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); - EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_OR, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); /* This is ASSERT_EQ because if end_ip is 0, the instruction(block0, 1) * calls will not work properly, and the test will give weird results. */ ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } void -cmod_propagation_test::test_mov_prop(enum brw_conditional_mod cmod, - enum brw_reg_type add_type, - enum brw_reg_type mov_dst_type, +cmod_propagation_test::test_mov_prop(enum elk_conditional_mod cmod, + enum elk_reg_type add_type, + enum elk_reg_type mov_dst_type, bool expected_cmod_prop_progress) { - fs_reg dest = bld.vgrf(add_type); - fs_reg src0 = bld.vgrf(add_type); - fs_reg src1 = bld.vgrf(add_type); + elk_fs_reg dest = bld.vgrf(add_type); + elk_fs_reg src0 = bld.vgrf(add_type); + elk_fs_reg src1 = bld.vgrf(add_type); bld.ADD(dest, src0, src1); bld.MOV(retype(bld.null_reg_ud(), mov_dst_type), dest) ->conditional_mod = cmod; v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(expected_cmod_prop_progress, cmod_propagation(v)); - const enum brw_conditional_mod add_cmod = - expected_cmod_prop_progress ? cmod : BRW_CONDITIONAL_NONE; + const enum elk_conditional_mod add_cmod = + expected_cmod_prop_progress ? cmod : ELK_CONDITIONAL_NONE; EXPECT_EQ(0, block0->start_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(add_cmod, instruction(block0, 0)->conditional_mod); if (expected_cmod_prop_progress) { @@ -1574,7 +1574,7 @@ cmod_propagation_test::test_mov_prop(enum brw_conditional_mod cmod, */ ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_EQ(cmod, instruction(block0, 1)->conditional_mod); } } @@ -1588,9 +1588,9 @@ TEST_F(cmod_propagation_test, fadd_fmov_nz) * = After = * 0: add.nz(8) dest:F src0:F src1:F */ - test_mov_prop(BRW_CONDITIONAL_NZ, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, + test_mov_prop(ELK_CONDITIONAL_NZ, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, true); } @@ -1603,9 +1603,9 @@ TEST_F(cmod_propagation_test, fadd_fmov_z) * = After = * 0: add.z(8) dest:F src0:F src1:F */ - test_mov_prop(BRW_CONDITIONAL_Z, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, + test_mov_prop(ELK_CONDITIONAL_Z, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, true); } @@ -1618,9 +1618,9 @@ TEST_F(cmod_propagation_test, fadd_fmov_l) * = After = * 0: add.l(8) dest:F src0:F src1:F */ - test_mov_prop(BRW_CONDITIONAL_L, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, + test_mov_prop(ELK_CONDITIONAL_L, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, true); } @@ -1633,9 +1633,9 @@ TEST_F(cmod_propagation_test, fadd_fmov_g) * = After = * 0: add.g(8) dest:F src0:F src1:F */ - test_mov_prop(BRW_CONDITIONAL_G, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, + test_mov_prop(ELK_CONDITIONAL_G, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, true); } @@ -1648,9 +1648,9 @@ TEST_F(cmod_propagation_test, fadd_fmov_le) * = After = * 0: add.le(8) dest:F src0:F src1:F */ - test_mov_prop(BRW_CONDITIONAL_LE, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, + test_mov_prop(ELK_CONDITIONAL_LE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, true); } @@ -1663,9 +1663,9 @@ TEST_F(cmod_propagation_test, fadd_fmov_ge) * = After = * 0: add.ge(8) dest:F src0:F src1:F */ - test_mov_prop(BRW_CONDITIONAL_GE, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_F, + test_mov_prop(ELK_CONDITIONAL_GE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_F, true); } @@ -1678,9 +1678,9 @@ TEST_F(cmod_propagation_test, iadd_imov_nz) * = After = * 0: add.nz(8) dest:D src0:D src1:D */ - test_mov_prop(BRW_CONDITIONAL_NZ, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_NZ, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_D, true); } @@ -1693,9 +1693,9 @@ TEST_F(cmod_propagation_test, iadd_imov_z) * = After = * 0: add.z(8) dest:D src0:D src1:D */ - test_mov_prop(BRW_CONDITIONAL_Z, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_Z, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_D, true); } @@ -1708,9 +1708,9 @@ TEST_F(cmod_propagation_test, iadd_imov_l) * = After = * 0: add.l(8) dest:D src0:D src1:D */ - test_mov_prop(BRW_CONDITIONAL_L, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_L, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_D, true); } @@ -1723,9 +1723,9 @@ TEST_F(cmod_propagation_test, iadd_imov_g) * = After = * 0: add.g(8) dest:D src0:D src1:D */ - test_mov_prop(BRW_CONDITIONAL_G, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_G, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_D, true); } @@ -1738,9 +1738,9 @@ TEST_F(cmod_propagation_test, iadd_imov_le) * = After = * 0: add.le(8) dest:D src0:D src1:D */ - test_mov_prop(BRW_CONDITIONAL_LE, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_LE, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_D, true); } @@ -1753,9 +1753,9 @@ TEST_F(cmod_propagation_test, iadd_imov_ge) * = After = * 0: add.ge(8) dest:D src0:D src1:D */ - test_mov_prop(BRW_CONDITIONAL_GE, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_GE, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_D, true); } @@ -1768,9 +1768,9 @@ TEST_F(cmod_propagation_test, iadd_umov_nz) * = After = * 0: add.nz(8) dest:D src0:D src1:D */ - test_mov_prop(BRW_CONDITIONAL_NZ, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_NZ, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_UD, true); } @@ -1783,9 +1783,9 @@ TEST_F(cmod_propagation_test, iadd_umov_z) * = After = * 0: add.z(8) dest:D src0:D src1:D */ - test_mov_prop(BRW_CONDITIONAL_Z, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_Z, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_UD, true); } @@ -1806,9 +1806,9 @@ TEST_F(cmod_propagation_test, iadd_umov_l) * contradiction, and earlier optimization passes should have eliminated * it. */ - test_mov_prop(BRW_CONDITIONAL_L, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_L, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_UD, false); } @@ -1824,9 +1824,9 @@ TEST_F(cmod_propagation_test, iadd_umov_g) * In spite of the type conversion, this could be made to work by * propagating NZ instead of G to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_G, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_G, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_UD, false); } @@ -1842,9 +1842,9 @@ TEST_F(cmod_propagation_test, iadd_umov_le) * In spite of the type conversion, this could be made to work by * propagating Z instead of LE to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_LE, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_LE, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_UD, false); } @@ -1865,9 +1865,9 @@ TEST_F(cmod_propagation_test, iadd_umov_ge) * to zero is a tautology, and earlier optimization passes should have * eliminated it. */ - test_mov_prop(BRW_CONDITIONAL_GE, - BRW_REGISTER_TYPE_D, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_GE, + ELK_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_UD, false); } @@ -1888,9 +1888,9 @@ TEST_F(cmod_propagation_test, fadd_f2u_nz) * the flag, but mov.nz would not because the 0.5 would get rounded down to * zero. */ - test_mov_prop(BRW_CONDITIONAL_NZ, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_NZ, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_UD, false); } @@ -1908,9 +1908,9 @@ TEST_F(cmod_propagation_test, fadd_f2u_z) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the Z back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_Z, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_Z, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_UD, false); } @@ -1928,9 +1928,9 @@ TEST_F(cmod_propagation_test, fadd_f2u_l) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the L back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_L, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_L, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_UD, false); } @@ -1948,9 +1948,9 @@ TEST_F(cmod_propagation_test, fadd_f2u_g) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the G back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_G, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_G, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_UD, false); } @@ -1968,9 +1968,9 @@ TEST_F(cmod_propagation_test, fadd_f2u_le) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the LE back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_LE, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_LE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_UD, false); } @@ -1988,9 +1988,9 @@ TEST_F(cmod_propagation_test, fadd_f2u_ge) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the GE back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_GE, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_UD, + test_mov_prop(ELK_CONDITIONAL_GE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_UD, false); } @@ -2006,9 +2006,9 @@ TEST_F(cmod_propagation_test, fadd_f2i_nz) * dest is NaN, the conversion will also clamp it to zero. It is not safe * to propagate the NZ back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_NZ, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_NZ, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_D, false); } @@ -2026,9 +2026,9 @@ TEST_F(cmod_propagation_test, fadd_f2i_z) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the Z back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_Z, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_Z, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_D, false); } @@ -2046,9 +2046,9 @@ TEST_F(cmod_propagation_test, fadd_f2i_l) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the L back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_L, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_L, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_D, false); } @@ -2066,9 +2066,9 @@ TEST_F(cmod_propagation_test, fadd_f2i_g) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the G back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_G, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_G, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_D, false); } @@ -2086,9 +2086,9 @@ TEST_F(cmod_propagation_test, fadd_f2i_le) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the LE back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_LE, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_LE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_D, false); } @@ -2106,28 +2106,28 @@ TEST_F(cmod_propagation_test, fadd_f2i_ge) * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the GE back to the ADD. */ - test_mov_prop(BRW_CONDITIONAL_GE, - BRW_REGISTER_TYPE_F, - BRW_REGISTER_TYPE_D, + test_mov_prop(ELK_CONDITIONAL_GE, + ELK_REGISTER_TYPE_F, + ELK_REGISTER_TYPE_D, false); } void -cmod_propagation_test::test_saturate_prop(enum brw_conditional_mod before, - enum opcode op, - enum brw_reg_type add_type, - enum brw_reg_type op_type, +cmod_propagation_test::test_saturate_prop(enum elk_conditional_mod before, + enum elk_opcode op, + enum elk_reg_type add_type, + enum elk_reg_type op_type, bool expected_cmod_prop_progress) { - fs_reg dest = bld.vgrf(add_type); - fs_reg src0 = bld.vgrf(add_type); - fs_reg src1 = bld.vgrf(add_type); - fs_reg zero(brw_imm_ud(0)); + elk_fs_reg dest = bld.vgrf(add_type); + elk_fs_reg src0 = bld.vgrf(add_type); + elk_fs_reg src1 = bld.vgrf(add_type); + elk_fs_reg zero(elk_imm_ud(0)); bld.ADD(dest, src0, src1)->saturate = true; - assert(op == BRW_OPCODE_CMP || op == BRW_OPCODE_MOV); - if (op == BRW_OPCODE_CMP) { + assert(op == ELK_OPCODE_CMP || op == ELK_OPCODE_MOV); + if (op == ELK_OPCODE_CMP) { bld.CMP(bld.vgrf(op_type, 0), retype(dest, op_type), retype(zero, op_type), @@ -2138,7 +2138,7 @@ cmod_propagation_test::test_saturate_prop(enum brw_conditional_mod before, } v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -2146,7 +2146,7 @@ cmod_propagation_test::test_saturate_prop(enum brw_conditional_mod before, EXPECT_EQ(expected_cmod_prop_progress, cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(add_type, instruction(block0, 0)->dst.type); EXPECT_EQ(add_type, instruction(block0, 0)->src[0].type); EXPECT_EQ(add_type, instruction(block0, 0)->src[1].type); @@ -2156,7 +2156,7 @@ cmod_propagation_test::test_saturate_prop(enum brw_conditional_mod before, EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(before, instruction(block0, 0)->conditional_mod); } else { - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); /* This is ASSERT_EQ because if end_ip is 0, the instruction(block0, 1) * calls will not work properly, and the test will give weird results. @@ -2183,8 +2183,8 @@ TEST_F(cmod_propagation_test, float_saturate_nz_cmp) * = After = * 0: add.sat.nz.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_NZ, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2201,8 +2201,8 @@ TEST_F(cmod_propagation_test, float_saturate_nz_mov) * = After = * 0: add.sat.nz.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_NZ, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2219,8 +2219,8 @@ TEST_F(cmod_propagation_test, float_saturate_z_cmp) * = After = * 0: add.sat.z.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_Z, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2237,8 +2237,8 @@ TEST_F(cmod_propagation_test, float_saturate_z_mov) * = After = * 0: add.sat.z.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_Z, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2255,8 +2255,8 @@ TEST_F(cmod_propagation_test, float_saturate_g_cmp) * = After = * 0: add.sat.g.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_G, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_G, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2273,8 +2273,8 @@ TEST_F(cmod_propagation_test, float_saturate_g_mov) * = After = * 0: add.sat.g.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_G, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_G, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2291,8 +2291,8 @@ TEST_F(cmod_propagation_test, float_saturate_le_cmp) * = After = * 0: add.sat.le.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_LE, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_LE, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2309,8 +2309,8 @@ TEST_F(cmod_propagation_test, float_saturate_le_mov) * = After = * 0: add.sat.le.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_LE, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_LE, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2327,8 +2327,8 @@ TEST_F(cmod_propagation_test, float_saturate_l_cmp) * = After = * 0: add.sat.l.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_L, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_L, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2345,8 +2345,8 @@ TEST_F(cmod_propagation_test, float_saturate_l_mov) * = After = * 0: add.sat.l.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_L, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_L, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2363,8 +2363,8 @@ TEST_F(cmod_propagation_test, float_saturate_ge_cmp) * = After = * 0: add.sat.ge.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_GE, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_GE, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2381,8 +2381,8 @@ TEST_F(cmod_propagation_test, float_saturate_ge_mov) * = After = * 0: add.sat.ge.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_GE, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, + test_saturate_prop(ELK_CONDITIONAL_GE, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_F, ELK_REGISTER_TYPE_F, true); } @@ -2396,8 +2396,8 @@ TEST_F(cmod_propagation_test, int_saturate_nz_cmp) * = After = * 0: add.sat.nz.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_NZ, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2411,8 +2411,8 @@ TEST_F(cmod_propagation_test, uint_saturate_nz_cmp) * = After = * 0: add.sat.nz.f0(8) dest:UD src0:UD src1:UD */ - test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_UD, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_NZ, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_UD, ELK_REGISTER_TYPE_D, true); } @@ -2426,8 +2426,8 @@ TEST_F(cmod_propagation_test, int_saturate_nz_mov) * = After = * 0: add.sat.nz.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_NZ, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2441,8 +2441,8 @@ TEST_F(cmod_propagation_test, int_saturate_z_cmp) * = After = * 0: add.sat.z.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_Z, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2456,8 +2456,8 @@ TEST_F(cmod_propagation_test, uint_saturate_z_cmp) * = After = * 0: add.sat.z.f0(8) dest:UD src0:UD src1:UD */ - test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_UD, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_Z, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_UD, ELK_REGISTER_TYPE_D, true); } @@ -2474,8 +2474,8 @@ TEST_F(cmod_propagation_test, int_saturate_z_mov) * = After = * 0: add.sat.z.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_Z, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2489,8 +2489,8 @@ TEST_F(cmod_propagation_test, int_saturate_g_cmp) * = After = * 0: add.sat.g.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_G, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_G, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2504,8 +2504,8 @@ TEST_F(cmod_propagation_test, int_saturate_g_mov) * = After = * 0: add.sat.g.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_G, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_G, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2519,8 +2519,8 @@ TEST_F(cmod_propagation_test, int_saturate_le_cmp) * = After = * 0: add.sat.le.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_LE, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_LE, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2534,8 +2534,8 @@ TEST_F(cmod_propagation_test, int_saturate_le_mov) * = After = * 0: add.sat.le.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_LE, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_LE, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2549,8 +2549,8 @@ TEST_F(cmod_propagation_test, int_saturate_l_cmp) * = After = * 0: add.sat.l.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_L, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_L, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2564,8 +2564,8 @@ TEST_F(cmod_propagation_test, int_saturate_l_mov) * = After = * 0: add.sat.l.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_L, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_L, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2579,8 +2579,8 @@ TEST_F(cmod_propagation_test, int_saturate_ge_cmp) * = After = * 0: add.sat.ge.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_GE, BRW_OPCODE_CMP, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_GE, ELK_OPCODE_CMP, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2594,8 +2594,8 @@ TEST_F(cmod_propagation_test, int_saturate_ge_mov) * = After = * 0: add.sat.ge.f0(8) dest src0 src1 */ - test_saturate_prop(BRW_CONDITIONAL_GE, BRW_OPCODE_MOV, - BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, + test_saturate_prop(ELK_CONDITIONAL_GE, ELK_OPCODE_MOV, + ELK_REGISTER_TYPE_D, ELK_REGISTER_TYPE_D, true); } @@ -2604,11 +2604,11 @@ TEST_F(cmod_propagation_test, not_to_or) /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ - fs_reg dest = v->vgrf(glsl_uint_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg src1 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest = v->vgrf(glsl_uint_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src1 = v->vgrf(glsl_uint_type()); bld.OR(dest, src0, src1); - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); /* = Before = * @@ -2620,7 +2620,7 @@ TEST_F(cmod_propagation_test, not_to_or) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -2628,8 +2628,8 @@ TEST_F(cmod_propagation_test, not_to_or) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_OR, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_and) @@ -2637,11 +2637,11 @@ TEST_F(cmod_propagation_test, not_to_and) /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ - fs_reg dest = v->vgrf(glsl_uint_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg src1 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest = v->vgrf(glsl_uint_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src1 = v->vgrf(glsl_uint_type()); bld.AND(dest, src0, src1); - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); /* = Before = * @@ -2653,7 +2653,7 @@ TEST_F(cmod_propagation_test, not_to_and) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -2661,8 +2661,8 @@ TEST_F(cmod_propagation_test, not_to_and) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_AND, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_uadd) @@ -2675,11 +2675,11 @@ TEST_F(cmod_propagation_test, not_to_uadd) * restriction is just the the destination type of the ALU instruction is * the same as the source type of the NOT instruction. */ - fs_reg dest = v->vgrf(glsl_uint_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg src1 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest = v->vgrf(glsl_uint_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src1 = v->vgrf(glsl_uint_type()); bld.ADD(dest, src0, src1); - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); /* = Before = * @@ -2691,7 +2691,7 @@ TEST_F(cmod_propagation_test, not_to_uadd) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -2699,10 +2699,10 @@ TEST_F(cmod_propagation_test, not_to_uadd) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_NOT, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_fadd_to_ud) @@ -2715,11 +2715,11 @@ TEST_F(cmod_propagation_test, not_to_fadd_to_ud) * restriction is just the the destination type of the ALU instruction is * the same as the source type of the NOT instruction. */ - fs_reg dest = v->vgrf(glsl_uint_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_uint_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest, src0, src1); - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); /* = Before = * @@ -2731,7 +2731,7 @@ TEST_F(cmod_propagation_test, not_to_fadd_to_ud) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -2739,10 +2739,10 @@ TEST_F(cmod_propagation_test, not_to_fadd_to_ud) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_NOT, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_fadd) @@ -2755,13 +2755,13 @@ TEST_F(cmod_propagation_test, not_to_fadd) * restriction is just the the destination type of the ALU instruction is * the same as the source type of the NOT instruction. */ - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dest, src0, src1); - set_condmod(BRW_CONDITIONAL_NZ, + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), - retype(dest, BRW_REGISTER_TYPE_UD))); + retype(dest, ELK_REGISTER_TYPE_UD))); /* = Before = * @@ -2773,7 +2773,7 @@ TEST_F(cmod_propagation_test, not_to_fadd) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -2781,10 +2781,10 @@ TEST_F(cmod_propagation_test, not_to_fadd) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_NOT, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_compatible_value) @@ -2792,15 +2792,15 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_compatible_value) /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ - fs_reg dest0 = v->vgrf(glsl_uint_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg src1 = v->vgrf(glsl_uint_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); - set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest0, src0, src1)); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); + elk_fs_reg dest0 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src1 = v->vgrf(glsl_uint_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); + set_condmod(ELK_CONDITIONAL_Z, bld.OR(dest0, src0, src1)); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * @@ -2814,7 +2814,7 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_compatible_value) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -2822,10 +2822,10 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_compatible_value) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_OR, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, @@ -2834,16 +2834,16 @@ TEST_F(cmod_propagation_test, /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ - fs_reg dest0 = v->vgrf(glsl_uint_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg src1 = v->vgrf(glsl_uint_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); - set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest0, src0, src1)) + elk_fs_reg dest0 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src1 = v->vgrf(glsl_uint_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); + set_condmod(ELK_CONDITIONAL_Z, bld.OR(dest0, src0, src1)) ->flag_subreg = 1; - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * @@ -2856,7 +2856,7 @@ TEST_F(cmod_propagation_test, */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -2864,13 +2864,13 @@ TEST_F(cmod_propagation_test, EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_OR, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); EXPECT_EQ(1, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); - EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_NOT, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 2)->conditional_mod); EXPECT_EQ(0, instruction(block0, 2)->flag_subreg); } @@ -2879,15 +2879,15 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_incompatible_value /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ - fs_reg dest0 = v->vgrf(glsl_uint_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg src1 = v->vgrf(glsl_uint_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); - set_condmod(BRW_CONDITIONAL_NZ, bld.OR(dest0, src0, src1)); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); + elk_fs_reg dest0 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src1 = v->vgrf(glsl_uint_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); + set_condmod(ELK_CONDITIONAL_NZ, bld.OR(dest0, src0, src1)); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * @@ -2900,7 +2900,7 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_incompatible_value */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -2908,12 +2908,12 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_incompatible_value EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); - EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_OR, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_NOT, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_write) @@ -2921,15 +2921,15 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_write) /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ - fs_reg dest0 = v->vgrf(glsl_uint_type()); - fs_reg dest1 = v->vgrf(glsl_uint_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg src1 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest0 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest1 = v->vgrf(glsl_uint_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src1 = v->vgrf(glsl_uint_type()); bld.OR(dest0, src0, src1); - set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest1, src0, src1)) + set_condmod(ELK_CONDITIONAL_Z, bld.OR(dest1, src0, src1)) ->flag_subreg = 1; - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * @@ -2943,7 +2943,7 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_write) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -2951,11 +2951,11 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_write) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_OR, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_OR, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 1)->conditional_mod); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } @@ -2964,17 +2964,17 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_read) /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ - fs_reg dest0 = v->vgrf(glsl_uint_type()); - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_uint_type()); - fs_reg src1 = v->vgrf(glsl_uint_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest0 = v->vgrf(glsl_uint_type()); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_uint_type()); + elk_fs_reg src1 = v->vgrf(glsl_uint_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.OR(dest0, src0, src1); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) ->flag_subreg = 1; - set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); + set_condmod(ELK_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * @@ -2988,7 +2988,7 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_read) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -2996,23 +2996,23 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_read) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_OR, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, cmp_to_add_float_e) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg neg10(brw_imm_f(-10.0f)); - fs_reg pos10(brw_imm_f(10.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg neg10(elk_imm_f(-10.0f)); + elk_fs_reg pos10(elk_imm_f(10.0f)); bld.ADD(dest, src0, neg10)->saturate = true; - bld.CMP(bld.null_reg_f(), src0, pos10, BRW_CONDITIONAL_EQ); + bld.CMP(bld.null_reg_f(), src0, pos10, ELK_CONDITIONAL_EQ); /* = Before = * 0: add.sat(8) vgrf0:F, vgrf1:F, -10f @@ -3023,26 +3023,26 @@ TEST_F(cmod_propagation_test, cmp_to_add_float_e) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_to_add_float_g) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg neg10(brw_imm_f(-10.0f)); - fs_reg pos10(brw_imm_f(10.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg neg10(elk_imm_f(-10.0f)); + elk_fs_reg pos10(elk_imm_f(10.0f)); bld.ADD(dest, src0, neg10)->saturate = true; - bld.CMP(bld.null_reg_f(), src0, pos10, BRW_CONDITIONAL_G); + bld.CMP(bld.null_reg_f(), src0, pos10, ELK_CONDITIONAL_G); /* = Before = * 0: add.sat(8) vgrf0:F, vgrf1:F, -10f @@ -3053,24 +3053,24 @@ TEST_F(cmod_propagation_test, cmp_to_add_float_g) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_G, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_to_add_float_le) { - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg neg10(brw_imm_f(-10.0f)); - fs_reg pos10(brw_imm_f(10.0f)); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg neg10(elk_imm_f(-10.0f)); + elk_fs_reg pos10(elk_imm_f(10.0f)); bld.ADD(dest, src0, neg10)->saturate = true; - bld.CMP(bld.null_reg_f(), src0, pos10, BRW_CONDITIONAL_LE); + bld.CMP(bld.null_reg_f(), src0, pos10, ELK_CONDITIONAL_LE); /* = Before = * 0: add.sat(8) vgrf0:F, vgrf1:F, -10f @@ -3081,27 +3081,27 @@ TEST_F(cmod_propagation_test, cmp_to_add_float_le) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, prop_across_sel_gfx7) { - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg dest2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg src3 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg src3 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest1, src0, src1); - bld.emit_minmax(dest2, src2, src3, BRW_CONDITIONAL_GE); - bld.CMP(bld.null_reg_f(), dest1, zero, BRW_CONDITIONAL_GE); + bld.emit_minmax(dest2, src2, src3, ELK_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest1, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -3115,7 +3115,7 @@ TEST_F(cmod_propagation_test, prop_across_sel_gfx7) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -3123,10 +3123,10 @@ TEST_F(cmod_propagation_test, prop_across_sel_gfx7) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, prop_across_sel_gfx5) @@ -3134,16 +3134,16 @@ TEST_F(cmod_propagation_test, prop_across_sel_gfx5) devinfo->ver = 5; devinfo->verx10 = devinfo->ver * 10; - fs_reg dest1 = v->vgrf(glsl_float_type()); - fs_reg dest2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); - fs_reg src3 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); + elk_fs_reg dest1 = v->vgrf(glsl_float_type()); + elk_fs_reg dest2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg src3 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); bld.ADD(dest1, src0, src1); - bld.emit_minmax(dest2, src2, src3, BRW_CONDITIONAL_GE); - bld.CMP(bld.null_reg_f(), dest1, zero, BRW_CONDITIONAL_GE); + bld.emit_minmax(dest2, src2, src3, ELK_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest1, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -3161,7 +3161,7 @@ TEST_F(cmod_propagation_test, prop_across_sel_gfx5) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -3169,12 +3169,12 @@ TEST_F(cmod_propagation_test, prop_across_sel_gfx5) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, prop_into_sel_gfx5) @@ -3182,12 +3182,12 @@ TEST_F(cmod_propagation_test, prop_into_sel_gfx5) devinfo->ver = 5; devinfo->verx10 = devinfo->ver * 10; - fs_reg dest = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg zero(brw_imm_f(0.0f)); - bld.emit_minmax(dest, src0, src1, BRW_CONDITIONAL_GE); - bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); + elk_fs_reg dest = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg zero(elk_imm_f(0.0f)); + bld.emit_minmax(dest, src0, src1, ELK_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), dest, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -3204,7 +3204,7 @@ TEST_F(cmod_propagation_test, prop_into_sel_gfx5) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -3212,8 +3212,8 @@ TEST_F(cmod_propagation_test, prop_into_sel_gfx5) EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } diff --git a/src/intel/compiler/elk/elk_test_fs_combine_constants.cpp b/src/intel/compiler/elk/elk_test_fs_combine_constants.cpp index 83e10f9ef62..f657723632a 100644 --- a/src/intel/compiler/elk/elk_test_fs_combine_constants.cpp +++ b/src/intel/compiler/elk/elk_test_fs_combine_constants.cpp @@ -20,7 +20,7 @@ struct FSCombineConstantsTest : public ::testing::Test { compiler = {}; compiler.devinfo = &devinfo; - brw_init_isa_info(&compiler.isa, &devinfo); + elk_init_isa_info(&compiler.isa, &devinfo); params = {}; params.mem_ctx = mem_ctx; @@ -29,7 +29,7 @@ struct FSCombineConstantsTest : public ::testing::Test { nir_shader *nir = nir_shader_create(mem_ctx, MESA_SHADER_COMPUTE, NULL, NULL); - shader = new fs_visitor(&compiler, ¶ms, NULL, + shader = new elk_fs_visitor(&compiler, ¶ms, NULL, &prog_data.base, nir, 8, false, false); } @@ -40,15 +40,15 @@ struct FSCombineConstantsTest : public ::testing::Test { } void *mem_ctx; - brw_compiler compiler; - brw_compile_params params; + elk_compiler compiler; + elk_compile_params params; intel_device_info devinfo; - struct brw_wm_prog_data prog_data; + struct elk_wm_prog_data prog_data; struct gl_shader_program *shader_prog; - fs_visitor *shader; + elk_fs_visitor *shader; - bool opt_combine_constants(fs_visitor *s) { + bool opt_combine_constants(elk_fs_visitor *s) { const bool print = getenv("TEST_DEBUG"); if (print) { @@ -68,7 +68,7 @@ struct FSCombineConstantsTest : public ::testing::Test { }; static fs_builder -make_builder(fs_visitor *s) +make_builder(elk_fs_visitor *s) { return fs_builder(s, s->dispatch_width).at_end(); } @@ -77,9 +77,9 @@ TEST_F(FSCombineConstantsTest, Simple) { fs_builder bld = make_builder(shader); - fs_reg r = brw_vec8_grf(1, 0); - fs_reg imm_a = brw_imm_ud(1); - fs_reg imm_b = brw_imm_ud(2); + elk_fs_reg r = elk_vec8_grf(1, 0); + elk_fs_reg imm_a = elk_imm_ud(1); + elk_fs_reg imm_b = elk_imm_ud(2); bld.SEL(r, imm_a, imm_b); shader->calculate_cfg(); @@ -88,24 +88,24 @@ TEST_F(FSCombineConstantsTest, Simple) ASSERT_TRUE(progress); ASSERT_EQ(shader->cfg->num_blocks, 1); - bblock_t *block = cfg_first_block(shader->cfg); + elk_bblock_t *block = cfg_first_block(shader->cfg); ASSERT_NE(block, nullptr); /* We can do better but for now sanity check that * there's a MOV and a SEL. */ - ASSERT_EQ(bblock_start(block)->opcode, BRW_OPCODE_MOV); - ASSERT_EQ(bblock_end(block)->opcode, BRW_OPCODE_SEL); + ASSERT_EQ(bblock_start(block)->opcode, ELK_OPCODE_MOV); + ASSERT_EQ(bblock_end(block)->opcode, ELK_OPCODE_SEL); } TEST_F(FSCombineConstantsTest, DoContainingDo) { fs_builder bld = make_builder(shader); - fs_reg r1 = brw_vec8_grf(1, 0); - fs_reg r2 = brw_vec8_grf(2, 0); - fs_reg imm_a = brw_imm_ud(1); - fs_reg imm_b = brw_imm_ud(2); + elk_fs_reg r1 = elk_vec8_grf(1, 0); + elk_fs_reg r2 = elk_vec8_grf(2, 0); + elk_fs_reg imm_a = elk_imm_ud(1); + elk_fs_reg imm_b = elk_imm_ud(2); bld.DO(); bld.DO(); diff --git a/src/intel/compiler/elk/elk_test_fs_copy_propagation.cpp b/src/intel/compiler/elk/elk_test_fs_copy_propagation.cpp index de17e4a210c..7854998629f 100644 --- a/src/intel/compiler/elk/elk_test_fs_copy_propagation.cpp +++ b/src/intel/compiler/elk/elk_test_fs_copy_propagation.cpp @@ -33,24 +33,24 @@ protected: copy_propagation_test(); ~copy_propagation_test() override; - struct brw_compiler *compiler; - struct brw_compile_params params; + struct elk_compiler *compiler; + struct elk_compile_params params; struct intel_device_info *devinfo; void *ctx; - struct brw_wm_prog_data *prog_data; + struct elk_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; - fs_visitor *v; + elk_fs_visitor *v; fs_builder bld; }; -class copy_propagation_fs_visitor : public fs_visitor +class copy_propagation_fs_visitor : public elk_fs_visitor { public: - copy_propagation_fs_visitor(struct brw_compiler *compiler, - struct brw_compile_params *params, - struct brw_wm_prog_data *prog_data, + copy_propagation_fs_visitor(struct elk_compiler *compiler, + struct elk_compile_params *params, + struct elk_wm_prog_data *prog_data, nir_shader *shader) - : fs_visitor(compiler, params, NULL, + : elk_fs_visitor(compiler, params, NULL, &prog_data->base, shader, 8, false, false) {} }; @@ -59,14 +59,14 @@ copy_propagation_test::copy_propagation_test() : bld(NULL, 0) { ctx = ralloc_context(NULL); - compiler = rzalloc(ctx, struct brw_compiler); + compiler = rzalloc(ctx, struct elk_compiler); devinfo = rzalloc(ctx, struct intel_device_info); compiler->devinfo = devinfo; params = {}; params.mem_ctx = ctx; - prog_data = ralloc(ctx, struct brw_wm_prog_data); + prog_data = ralloc(ctx, struct elk_wm_prog_data); nir_shader *shader = nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL); @@ -87,18 +87,18 @@ copy_propagation_test::~copy_propagation_test() ctx = NULL; } -static fs_inst * -instruction(bblock_t *block, int num) +static elk_fs_inst * +instruction(elk_bblock_t *block, int num) { - fs_inst *inst = (fs_inst *)block->start(); + elk_fs_inst *inst = (elk_fs_inst *)block->start(); for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; + inst = (elk_fs_inst *)inst->next; } return inst; } static bool -copy_propagation(fs_visitor *v) +copy_propagation(elk_fs_visitor *v) { const bool print = getenv("TEST_DEBUG"); @@ -119,10 +119,10 @@ copy_propagation(fs_visitor *v) TEST_F(copy_propagation_test, basic) { - fs_reg vgrf0 = v->vgrf(glsl_float_type()); - fs_reg vgrf1 = v->vgrf(glsl_float_type()); - fs_reg vgrf2 = v->vgrf(glsl_float_type()); - fs_reg vgrf3 = v->vgrf(glsl_float_type()); + elk_fs_reg vgrf0 = v->vgrf(glsl_float_type()); + elk_fs_reg vgrf1 = v->vgrf(glsl_float_type()); + elk_fs_reg vgrf2 = v->vgrf(glsl_float_type()); + elk_fs_reg vgrf3 = v->vgrf(glsl_float_type()); bld.MOV(vgrf0, vgrf2); bld.ADD(vgrf1, vgrf0, vgrf3); @@ -137,7 +137,7 @@ TEST_F(copy_propagation_test, basic) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -146,13 +146,13 @@ TEST_F(copy_propagation_test, basic) EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - fs_inst *mov = instruction(block0, 0); - EXPECT_EQ(BRW_OPCODE_MOV, mov->opcode); + elk_fs_inst *mov = instruction(block0, 0); + EXPECT_EQ(ELK_OPCODE_MOV, mov->opcode); EXPECT_TRUE(mov->dst.equals(vgrf0)); EXPECT_TRUE(mov->src[0].equals(vgrf2)); - fs_inst *add = instruction(block0, 1); - EXPECT_EQ(BRW_OPCODE_ADD, add->opcode); + elk_fs_inst *add = instruction(block0, 1); + EXPECT_EQ(ELK_OPCODE_ADD, add->opcode); EXPECT_TRUE(add->dst.equals(vgrf1)); EXPECT_TRUE(add->src[0].equals(vgrf2)); EXPECT_TRUE(add->src[1].equals(vgrf3)); @@ -160,46 +160,46 @@ TEST_F(copy_propagation_test, basic) TEST_F(copy_propagation_test, maxmax_sat_imm) { - fs_reg vgrf0 = v->vgrf(glsl_float_type()); - fs_reg vgrf1 = v->vgrf(glsl_float_type()); - fs_reg vgrf2 = v->vgrf(glsl_float_type()); + elk_fs_reg vgrf0 = v->vgrf(glsl_float_type()); + elk_fs_reg vgrf1 = v->vgrf(glsl_float_type()); + elk_fs_reg vgrf2 = v->vgrf(glsl_float_type()); static const struct { - enum brw_conditional_mod conditional_mod; + enum elk_conditional_mod conditional_mod; float immediate; bool expected_result; } test[] = { /* conditional mod, imm, expected_result */ - { BRW_CONDITIONAL_GE , 0.1f, false }, - { BRW_CONDITIONAL_L , 0.1f, false }, - { BRW_CONDITIONAL_GE , 0.5f, false }, - { BRW_CONDITIONAL_L , 0.5f, false }, - { BRW_CONDITIONAL_GE , 0.9f, false }, - { BRW_CONDITIONAL_L , 0.9f, false }, - { BRW_CONDITIONAL_GE , -1.5f, false }, - { BRW_CONDITIONAL_L , -1.5f, false }, - { BRW_CONDITIONAL_GE , 1.5f, false }, - { BRW_CONDITIONAL_L , 1.5f, false }, + { ELK_CONDITIONAL_GE , 0.1f, false }, + { ELK_CONDITIONAL_L , 0.1f, false }, + { ELK_CONDITIONAL_GE , 0.5f, false }, + { ELK_CONDITIONAL_L , 0.5f, false }, + { ELK_CONDITIONAL_GE , 0.9f, false }, + { ELK_CONDITIONAL_L , 0.9f, false }, + { ELK_CONDITIONAL_GE , -1.5f, false }, + { ELK_CONDITIONAL_L , -1.5f, false }, + { ELK_CONDITIONAL_GE , 1.5f, false }, + { ELK_CONDITIONAL_L , 1.5f, false }, - { BRW_CONDITIONAL_NONE, 0.5f, false }, - { BRW_CONDITIONAL_Z , 0.5f, false }, - { BRW_CONDITIONAL_NZ , 0.5f, false }, - { BRW_CONDITIONAL_G , 0.5f, false }, - { BRW_CONDITIONAL_LE , 0.5f, false }, - { BRW_CONDITIONAL_R , 0.5f, false }, - { BRW_CONDITIONAL_O , 0.5f, false }, - { BRW_CONDITIONAL_U , 0.5f, false }, + { ELK_CONDITIONAL_NONE, 0.5f, false }, + { ELK_CONDITIONAL_Z , 0.5f, false }, + { ELK_CONDITIONAL_NZ , 0.5f, false }, + { ELK_CONDITIONAL_G , 0.5f, false }, + { ELK_CONDITIONAL_LE , 0.5f, false }, + { ELK_CONDITIONAL_R , 0.5f, false }, + { ELK_CONDITIONAL_O , 0.5f, false }, + { ELK_CONDITIONAL_U , 0.5f, false }, }; for (unsigned i = 0; i < sizeof(test) / sizeof(test[0]); i++) { - fs_inst *mov = set_saturate(true, bld.MOV(vgrf0, vgrf1)); - fs_inst *sel = set_condmod(test[i].conditional_mod, + elk_fs_inst *mov = set_saturate(true, bld.MOV(vgrf0, vgrf1)); + elk_fs_inst *sel = set_condmod(test[i].conditional_mod, bld.SEL(vgrf2, vgrf0, - brw_imm_f(test[i].immediate))); + elk_imm_f(test[i].immediate))); v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -208,12 +208,12 @@ TEST_F(copy_propagation_test, maxmax_sat_imm) EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MOV, mov->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, mov->opcode); EXPECT_TRUE(mov->saturate); EXPECT_TRUE(mov->dst.equals(vgrf0)); EXPECT_TRUE(mov->src[0].equals(vgrf1)); - EXPECT_EQ(BRW_OPCODE_SEL, sel->opcode); + EXPECT_EQ(ELK_OPCODE_SEL, sel->opcode); EXPECT_EQ(test[i].conditional_mod, sel->conditional_mod); EXPECT_EQ(test[i].expected_result, sel->saturate); EXPECT_TRUE(sel->dst.equals(vgrf2)); @@ -222,7 +222,7 @@ TEST_F(copy_propagation_test, maxmax_sat_imm) } else { EXPECT_TRUE(sel->src[0].equals(vgrf0)); } - EXPECT_TRUE(sel->src[1].equals(brw_imm_f(test[i].immediate))); + EXPECT_TRUE(sel->src[1].equals(elk_imm_f(test[i].immediate))); delete v->cfg; v->cfg = NULL; diff --git a/src/intel/compiler/elk/elk_test_fs_saturate_propagation.cpp b/src/intel/compiler/elk/elk_test_fs_saturate_propagation.cpp index dab4007af6e..2428458fb83 100644 --- a/src/intel/compiler/elk/elk_test_fs_saturate_propagation.cpp +++ b/src/intel/compiler/elk/elk_test_fs_saturate_propagation.cpp @@ -33,24 +33,24 @@ protected: saturate_propagation_test(); ~saturate_propagation_test() override; - struct brw_compiler *compiler; - struct brw_compile_params params; + struct elk_compiler *compiler; + struct elk_compile_params params; struct intel_device_info *devinfo; void *ctx; - struct brw_wm_prog_data *prog_data; + struct elk_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; - fs_visitor *v; + elk_fs_visitor *v; fs_builder bld; }; -class saturate_propagation_fs_visitor : public fs_visitor +class saturate_propagation_fs_visitor : public elk_fs_visitor { public: - saturate_propagation_fs_visitor(struct brw_compiler *compiler, - struct brw_compile_params *params, - struct brw_wm_prog_data *prog_data, + saturate_propagation_fs_visitor(struct elk_compiler *compiler, + struct elk_compile_params *params, + struct elk_wm_prog_data *prog_data, nir_shader *shader) - : fs_visitor(compiler, params, NULL, + : elk_fs_visitor(compiler, params, NULL, &prog_data->base, shader, 16, false, false) {} }; @@ -59,14 +59,14 @@ saturate_propagation_test::saturate_propagation_test() : bld(NULL, 0) { ctx = ralloc_context(NULL); - compiler = rzalloc(ctx, struct brw_compiler); + compiler = rzalloc(ctx, struct elk_compiler); devinfo = rzalloc(ctx, struct intel_device_info); compiler->devinfo = devinfo; params = {}; params.mem_ctx = ctx; - prog_data = ralloc(ctx, struct brw_wm_prog_data); + prog_data = ralloc(ctx, struct elk_wm_prog_data); nir_shader *shader = nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL); @@ -88,18 +88,18 @@ saturate_propagation_test::~saturate_propagation_test() } -static fs_inst * -instruction(bblock_t *block, int num) +static elk_fs_inst * +instruction(elk_bblock_t *block, int num) { - fs_inst *inst = (fs_inst *)block->start(); + elk_fs_inst *inst = (elk_fs_inst *)block->start(); for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; + inst = (elk_fs_inst *)inst->next; } return inst; } static bool -saturate_propagation(fs_visitor *v) +saturate_propagation(elk_fs_visitor *v) { const bool print = false; @@ -120,10 +120,10 @@ saturate_propagation(fs_visitor *v) TEST_F(saturate_propagation_test, basic) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dst0, src0, src1); set_saturate(true, bld.MOV(dst1, dst0)); @@ -138,7 +138,7 @@ TEST_F(saturate_propagation_test, basic) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -146,19 +146,19 @@ TEST_F(saturate_propagation_test, basic) EXPECT_TRUE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_TRUE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, other_non_saturated_use) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg dst2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dst0, src0, src1); set_saturate(true, bld.MOV(dst1, dst0)); bld.ADD(dst2, dst0, src0); @@ -174,7 +174,7 @@ TEST_F(saturate_propagation_test, other_non_saturated_use) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -182,21 +182,21 @@ TEST_F(saturate_propagation_test, other_non_saturated_use) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->saturate); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 2)->opcode); } TEST_F(saturate_propagation_test, predicated_instruction) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dst0, src0, src1) - ->predicate = BRW_PREDICATE_NORMAL; + ->predicate = ELK_PREDICATE_NORMAL; set_saturate(true, bld.MOV(dst1, dst0)); /* = Before = @@ -209,7 +209,7 @@ TEST_F(saturate_propagation_test, predicated_instruction) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -217,17 +217,17 @@ TEST_F(saturate_propagation_test, predicated_instruction) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, neg_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); bld.RNDU(dst0, src0); dst0.negate = true; set_saturate(true, bld.MOV(dst1, dst0)); @@ -242,7 +242,7 @@ TEST_F(saturate_propagation_test, neg_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -250,18 +250,18 @@ TEST_F(saturate_propagation_test, neg_mov_sat) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_RNDU, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_RNDU, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, add_neg_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dst0, src0, src1); dst0.negate = true; set_saturate(true, bld.MOV(dst1, dst0)); @@ -277,7 +277,7 @@ TEST_F(saturate_propagation_test, add_neg_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -285,20 +285,20 @@ TEST_F(saturate_propagation_test, add_neg_mov_sat) EXPECT_TRUE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_TRUE(instruction(block0, 0)->saturate); EXPECT_TRUE(instruction(block0, 0)->src[0].negate); EXPECT_TRUE(instruction(block0, 0)->src[1].negate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = brw_imm_f(1.0f); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = elk_imm_f(1.0f); bld.ADD(dst0, src0, src1); dst0.negate = true; set_saturate(true, bld.MOV(dst1, dst0)); @@ -314,7 +314,7 @@ TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -322,20 +322,20 @@ TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat) EXPECT_TRUE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_TRUE(instruction(block0, 0)->saturate); EXPECT_TRUE(instruction(block0, 0)->src[0].negate); EXPECT_EQ(instruction(block0, 0)->src[1].f, -1.0f); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, mul_neg_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.MUL(dst0, src0, src1); dst0.negate = true; set_saturate(true, bld.MOV(dst1, dst0)); @@ -351,7 +351,7 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -359,21 +359,21 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat) EXPECT_TRUE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode); EXPECT_TRUE(instruction(block0, 0)->saturate); EXPECT_TRUE(instruction(block0, 0)->src[0].negate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 1)->saturate); EXPECT_FALSE(instruction(block0, 1)->src[0].negate); } TEST_F(saturate_propagation_test, mad_neg_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); bld.MAD(dst0, src0, src1, src2); dst0.negate = true; set_saturate(true, bld.MOV(dst1, dst0)); @@ -389,7 +389,7 @@ TEST_F(saturate_propagation_test, mad_neg_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -397,27 +397,27 @@ TEST_F(saturate_propagation_test, mad_neg_mov_sat) EXPECT_TRUE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_MAD, instruction(block0, 0)->opcode); EXPECT_TRUE(instruction(block0, 0)->saturate); EXPECT_TRUE(instruction(block0, 0)->src[0].negate); EXPECT_TRUE(instruction(block0, 0)->src[1].negate); EXPECT_FALSE(instruction(block0, 0)->src[2].negate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 1)->saturate); EXPECT_FALSE(instruction(block0, 1)->src[0].negate); } TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = brw_imm_f(1.0f); - fs_reg src1 = brw_imm_f(-2.0f); - fs_reg src2 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = elk_imm_f(1.0f); + elk_fs_reg src1 = elk_imm_f(-2.0f); + elk_fs_reg src2 = v->vgrf(glsl_float_type()); /* The builder for MAD tries to be helpful and not put immediates as direct * sources. We want to test specifically that case. */ - fs_inst *mad = bld.MAD(dst0, src2, src2, src2); + elk_fs_inst *mad = bld.MAD(dst0, src2, src2, src2); mad->src[0]= src0; mad->src[1] = src1; dst0.negate = true; @@ -434,7 +434,7 @@ TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -442,22 +442,22 @@ TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat) EXPECT_TRUE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_MAD, instruction(block0, 0)->opcode); EXPECT_TRUE(instruction(block0, 0)->saturate); EXPECT_EQ(instruction(block0, 0)->src[0].f, -1.0f); EXPECT_EQ(instruction(block0, 0)->src[1].f, 2.0f); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 1)->saturate); EXPECT_FALSE(instruction(block0, 1)->src[0].negate); } TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg dst2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.MUL(dst0, src0, src1); set_saturate(true, bld.MOV(dst1, dst0)); dst0.negate = true; @@ -474,7 +474,7 @@ TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -482,23 +482,23 @@ TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); EXPECT_FALSE(instruction(block0, 0)->src[1].negate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode); EXPECT_TRUE(instruction(block0, 2)->src[0].negate); EXPECT_TRUE(instruction(block0, 2)->saturate); } TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg dst2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.MUL(dst0, src0, src1); dst0.negate = true; set_saturate(true, bld.MOV(dst1, dst0)); @@ -515,7 +515,7 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -523,23 +523,23 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); EXPECT_FALSE(instruction(block0, 0)->src[1].negate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->src[0].negate); EXPECT_TRUE(instruction(block0, 1)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode); EXPECT_TRUE(instruction(block0, 2)->src[0].negate); EXPECT_TRUE(instruction(block0, 2)->saturate); } TEST_F(saturate_propagation_test, abs_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dst0, src0, src1); dst0.abs = true; set_saturate(true, bld.MOV(dst1, dst0)); @@ -554,7 +554,7 @@ TEST_F(saturate_propagation_test, abs_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -562,19 +562,19 @@ TEST_F(saturate_propagation_test, abs_mov_sat) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, producer_saturates) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg dst2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); set_saturate(true, bld.ADD(dst0, src0, src1)); set_saturate(true, bld.MOV(dst1, dst0)); bld.MOV(dst2, dst0); @@ -592,7 +592,7 @@ TEST_F(saturate_propagation_test, producer_saturates) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -600,19 +600,19 @@ TEST_F(saturate_propagation_test, producer_saturates) EXPECT_TRUE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_TRUE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, intervening_saturating_copy) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg dst2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dst0, src0, src1); set_saturate(true, bld.MOV(dst1, dst0)); set_saturate(true, bld.MOV(dst2, dst0)); @@ -630,7 +630,7 @@ TEST_F(saturate_propagation_test, intervening_saturating_copy) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -638,23 +638,23 @@ TEST_F(saturate_propagation_test, intervening_saturating_copy) EXPECT_TRUE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_TRUE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 1)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode); EXPECT_FALSE(instruction(block0, 2)->saturate); } TEST_F(saturate_propagation_test, intervening_dest_write) { - fs_reg dst0 = v->vgrf(glsl_vec4_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); - fs_reg src2 = v->vgrf(glsl_vec2_type()); + elk_fs_reg dst0 = v->vgrf(glsl_vec4_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg src2 = v->vgrf(glsl_vec2_type()); bld.ADD(offset(dst0, bld, 2), src0, src1); - bld.emit(SHADER_OPCODE_TEX, dst0, src2) + bld.emit(ELK_SHADER_OPCODE_TEX, dst0, src2) ->size_written = 8 * REG_SIZE; set_saturate(true, bld.MOV(dst1, offset(dst0, bld, 2))); @@ -669,7 +669,7 @@ TEST_F(saturate_propagation_test, intervening_dest_write) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -677,21 +677,21 @@ TEST_F(saturate_propagation_test, intervening_dest_write) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); - EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode); EXPECT_TRUE(instruction(block0, 2)->saturate); } TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg dst2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.MUL(dst0, src0, src1); dst0.negate = true; set_saturate(true, bld.MOV(dst1, dst0)); @@ -709,7 +709,7 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -717,22 +717,22 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); EXPECT_FALSE(instruction(block0, 0)->src[1].negate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->saturate); EXPECT_TRUE(instruction(block0, 1)->src[0].negate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode); EXPECT_TRUE(instruction(block0, 2)->saturate); } TEST_F(saturate_propagation_test, smaller_exec_size_consumer) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.ADD(dst0, src0, src1); set_saturate(true, bld.group(8, 0).MOV(dst1, dst0)); @@ -746,7 +746,7 @@ TEST_F(saturate_propagation_test, smaller_exec_size_consumer) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -754,18 +754,18 @@ TEST_F(saturate_propagation_test, smaller_exec_size_consumer) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, larger_exec_size_consumer) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.group(8, 0).ADD(dst0, src0, src1); set_saturate(true, bld.MOV(dst1, dst0)); @@ -779,7 +779,7 @@ TEST_F(saturate_propagation_test, larger_exec_size_consumer) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -787,21 +787,21 @@ TEST_F(saturate_propagation_test, larger_exec_size_consumer) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_TRUE(instruction(block0, 1)->saturate); } TEST_F(saturate_propagation_test, offset_source_barrier) { - fs_reg dst0 = v->vgrf(glsl_float_type()); - fs_reg dst1 = v->vgrf(glsl_float_type()); - fs_reg dst2 = v->vgrf(glsl_float_type()); - fs_reg src0 = v->vgrf(glsl_float_type()); - fs_reg src1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst0 = v->vgrf(glsl_float_type()); + elk_fs_reg dst1 = v->vgrf(glsl_float_type()); + elk_fs_reg dst2 = v->vgrf(glsl_float_type()); + elk_fs_reg src0 = v->vgrf(glsl_float_type()); + elk_fs_reg src1 = v->vgrf(glsl_float_type()); bld.group(16, 0).ADD(dst0, src0, src1); - bld.group(1, 0).ADD(dst1, component(dst0, 8), brw_imm_f(1.0f)); + bld.group(1, 0).ADD(dst1, component(dst0, 8), elk_imm_f(1.0f)); set_saturate(true, bld.group(16, 0).MOV(dst2, dst0)); /* = Before = @@ -815,7 +815,7 @@ TEST_F(saturate_propagation_test, offset_source_barrier) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -823,10 +823,10 @@ TEST_F(saturate_propagation_test, offset_source_barrier) EXPECT_FALSE(saturate_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_FALSE(instruction(block0, 0)->saturate); EXPECT_FALSE(instruction(block0, 1)->saturate); - EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_OPCODE_MOV, instruction(block0, 2)->opcode); EXPECT_TRUE(instruction(block0, 2)->saturate); } diff --git a/src/intel/compiler/elk/elk_test_predicated_break.cpp b/src/intel/compiler/elk/elk_test_predicated_break.cpp index f939db8a47f..48305c1c5c4 100644 --- a/src/intel/compiler/elk/elk_test_predicated_break.cpp +++ b/src/intel/compiler/elk/elk_test_predicated_break.cpp @@ -17,16 +17,16 @@ class PredicatedBreakTest : public ::testing::Test { public: bool debug; void *mem_ctx; - brw_compiler compiler; - brw_compile_params params; + elk_compiler compiler; + elk_compile_params params; intel_device_info devinfo; - struct brw_wm_prog_data prog_data; + struct elk_wm_prog_data prog_data; struct gl_shader_program *shader_prog; - fs_visitor *shader_a; - fs_visitor *shader_b; + elk_fs_visitor *shader_a; + elk_fs_visitor *shader_b; - bool opt_predicated_break(fs_visitor *s); + bool elk_opt_predicated_break(elk_fs_visitor *s); }; void @@ -42,7 +42,7 @@ PredicatedBreakTest::SetUp() compiler = {}; compiler.devinfo = &devinfo; - brw_init_isa_info(&compiler.isa, &devinfo); + elk_init_isa_info(&compiler.isa, &devinfo); params = {}; params.mem_ctx = mem_ctx; @@ -51,10 +51,10 @@ PredicatedBreakTest::SetUp() nir_shader *nir = nir_shader_create(mem_ctx, MESA_SHADER_FRAGMENT, NULL, NULL); - shader_a = new fs_visitor(&compiler, ¶ms, NULL, + shader_a = new elk_fs_visitor(&compiler, ¶ms, NULL, &prog_data.base, nir, 8, false, false); - shader_b = new fs_visitor(&compiler, ¶ms, NULL, + shader_b = new elk_fs_visitor(&compiler, ¶ms, NULL, &prog_data.base, nir, 8, false, false); } @@ -68,7 +68,7 @@ PredicatedBreakTest::TearDown() } bool -PredicatedBreakTest::opt_predicated_break(fs_visitor *s) +PredicatedBreakTest::elk_opt_predicated_break(elk_fs_visitor *s) { const bool print = getenv("TEST_DEBUG"); @@ -77,7 +77,7 @@ PredicatedBreakTest::opt_predicated_break(fs_visitor *s) s->cfg->dump(); } - bool ret = ::opt_predicated_break(s); + bool ret = ::elk_opt_predicated_break(s); if (print) { fprintf(stderr, "\n= After =\n"); @@ -88,14 +88,14 @@ PredicatedBreakTest::opt_predicated_break(fs_visitor *s) } static fs_builder -make_builder(fs_visitor *s) +make_builder(elk_fs_visitor *s) { return fs_builder(s, s->dispatch_width).at_end(); } static testing::AssertionResult shaders_match(const char *a_expr, const char *b_expr, - fs_visitor *a, fs_visitor *b) + elk_fs_visitor *a, elk_fs_visitor *b) { /* Using the CFG string dump for this. Not ideal but it is * convenient that covers some CFG information, helping to @@ -140,13 +140,13 @@ TEST_F(PredicatedBreakTest, TopBreakWithoutContinue) fs_builder a = make_builder(shader_a); fs_builder b = make_builder(shader_b); - fs_reg r1 = brw_vec8_grf(1, 0); - fs_reg r2 = brw_vec8_grf(2, 0); - fs_reg r3 = brw_vec8_grf(3, 0); + elk_fs_reg r1 = elk_vec8_grf(1, 0); + elk_fs_reg r2 = elk_vec8_grf(2, 0); + elk_fs_reg r3 = elk_vec8_grf(3, 0); a.DO(); - a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - a.IF(BRW_PREDICATE_NORMAL); + a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + a.IF(ELK_PREDICATE_NORMAL); a.BREAK(); a.ENDIF(); a.ADD(r1, r2, r3); @@ -155,12 +155,12 @@ TEST_F(PredicatedBreakTest, TopBreakWithoutContinue) shader_a->calculate_cfg(); /* The IF/ENDIF around the BREAK is expected to be removed. */ - bool progress = opt_predicated_break(shader_a); + bool progress = elk_opt_predicated_break(shader_a); EXPECT_TRUE(progress); b.DO(); - b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - b.BREAK()->predicate = BRW_PREDICATE_NORMAL; + b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + b.BREAK()->predicate = ELK_PREDICATE_NORMAL; b.ADD(r1, r2, r3); b.WHILE(); b.NOP(); @@ -174,18 +174,18 @@ TEST_F(PredicatedBreakTest, TopBreakWithContinue) fs_builder a = make_builder(shader_a); fs_builder b = make_builder(shader_b); - fs_reg r1 = brw_vec8_grf(1, 0); - fs_reg r2 = brw_vec8_grf(2, 0); - fs_reg r3 = brw_vec8_grf(3, 0); + elk_fs_reg r1 = elk_vec8_grf(1, 0); + elk_fs_reg r2 = elk_vec8_grf(2, 0); + elk_fs_reg r3 = elk_vec8_grf(3, 0); a.DO(); - a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - a.IF(BRW_PREDICATE_NORMAL); + a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + a.IF(ELK_PREDICATE_NORMAL); a.BREAK(); a.ENDIF(); a.ADD(r1, r2, r3); - a.CMP(r1, r2, r3, BRW_CONDITIONAL_GE); - a.IF(BRW_PREDICATE_NORMAL); + a.CMP(r1, r2, r3, ELK_CONDITIONAL_GE); + a.IF(ELK_PREDICATE_NORMAL); a.CONTINUE(); a.ENDIF(); a.MUL(r1, r2, r3); @@ -196,15 +196,15 @@ TEST_F(PredicatedBreakTest, TopBreakWithContinue) /* The IF/ENDIF around the BREAK and the CONTINUE are expected to be * removed. */ - bool progress = opt_predicated_break(shader_a); + bool progress = elk_opt_predicated_break(shader_a); EXPECT_TRUE(progress); b.DO(); - b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - b.BREAK()->predicate = BRW_PREDICATE_NORMAL; + b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + b.BREAK()->predicate = ELK_PREDICATE_NORMAL; b.ADD(r1, r2, r3); - b.CMP(r1, r2, r3, BRW_CONDITIONAL_GE); - b.CONTINUE()->predicate = BRW_PREDICATE_NORMAL; + b.CMP(r1, r2, r3, ELK_CONDITIONAL_GE); + b.CONTINUE()->predicate = ELK_PREDICATE_NORMAL; b.MUL(r1, r2, r3); b.WHILE(); b.NOP(); @@ -218,14 +218,14 @@ TEST_F(PredicatedBreakTest, DISABLED_BottomBreakWithoutContinue) fs_builder a = make_builder(shader_a); fs_builder b = make_builder(shader_b); - fs_reg r1 = brw_vec8_grf(1, 0); - fs_reg r2 = brw_vec8_grf(2, 0); - fs_reg r3 = brw_vec8_grf(3, 0); + elk_fs_reg r1 = elk_vec8_grf(1, 0); + elk_fs_reg r2 = elk_vec8_grf(2, 0); + elk_fs_reg r3 = elk_vec8_grf(3, 0); a.DO(); a.ADD(r1, r2, r3); - a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - a.IF(BRW_PREDICATE_NORMAL); + a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + a.IF(ELK_PREDICATE_NORMAL); a.BREAK(); a.ENDIF(); a.WHILE(); @@ -235,14 +235,14 @@ TEST_F(PredicatedBreakTest, DISABLED_BottomBreakWithoutContinue) /* BREAK is the only way to exit the loop, so expect to remove the * IF/BREAK/ENDIF and add a predicate to WHILE. */ - bool progress = opt_predicated_break(shader_a); + bool progress = elk_opt_predicated_break(shader_a); EXPECT_TRUE(progress); b.DO(); b.ADD(r1, r2, r3); - b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); + b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); auto w = b.WHILE(); - w->predicate = BRW_PREDICATE_NORMAL; + w->predicate = ELK_PREDICATE_NORMAL; w->predicate_inverse = true; b.NOP(); shader_b->calculate_cfg(); @@ -256,19 +256,19 @@ TEST_F(PredicatedBreakTest, BottomBreakWithContinue) fs_builder a = make_builder(shader_a); fs_builder b = make_builder(shader_b); - fs_reg r1 = brw_vec8_grf(1, 0); - fs_reg r2 = brw_vec8_grf(2, 0); - fs_reg r3 = brw_vec8_grf(3, 0); + elk_fs_reg r1 = elk_vec8_grf(1, 0); + elk_fs_reg r2 = elk_vec8_grf(2, 0); + elk_fs_reg r3 = elk_vec8_grf(3, 0); a.DO(); a.ADD(r1, r2, r3); - a.CMP(r1, r2, r3, BRW_CONDITIONAL_GE); - a.IF(BRW_PREDICATE_NORMAL); + a.CMP(r1, r2, r3, ELK_CONDITIONAL_GE); + a.IF(ELK_PREDICATE_NORMAL); a.CONTINUE(); a.ENDIF(); a.MUL(r1, r2, r3); - a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - a.IF(BRW_PREDICATE_NORMAL); + a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + a.IF(ELK_PREDICATE_NORMAL); a.BREAK(); a.ENDIF(); a.WHILE(); @@ -278,16 +278,16 @@ TEST_F(PredicatedBreakTest, BottomBreakWithContinue) /* With a CONTINUE, the BREAK can't be removed, but still remove the * IF/ENDIF around both of them. */ - bool progress = opt_predicated_break(shader_a); + bool progress = elk_opt_predicated_break(shader_a); EXPECT_TRUE(progress); b.DO(); b.ADD(r1, r2, r3); - b.CMP(r1, r2, r3, BRW_CONDITIONAL_GE); - b.CONTINUE()->predicate = BRW_PREDICATE_NORMAL; + b.CMP(r1, r2, r3, ELK_CONDITIONAL_GE); + b.CONTINUE()->predicate = ELK_PREDICATE_NORMAL; b.MUL(r1, r2, r3); - b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - b.BREAK()->predicate = BRW_PREDICATE_NORMAL; + b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + b.BREAK()->predicate = ELK_PREDICATE_NORMAL; b.WHILE(); b.NOP(); shader_b->calculate_cfg(); @@ -300,19 +300,19 @@ TEST_F(PredicatedBreakTest, TwoBreaks) fs_builder a = make_builder(shader_a); fs_builder b = make_builder(shader_b); - fs_reg r1 = brw_vec8_grf(1, 0); - fs_reg r2 = brw_vec8_grf(2, 0); - fs_reg r3 = brw_vec8_grf(3, 0); + elk_fs_reg r1 = elk_vec8_grf(1, 0); + elk_fs_reg r2 = elk_vec8_grf(2, 0); + elk_fs_reg r3 = elk_vec8_grf(3, 0); a.DO(); a.ADD(r1, r2, r3); - a.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - a.IF(BRW_PREDICATE_NORMAL); + a.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + a.IF(ELK_PREDICATE_NORMAL); a.BREAK(); a.ENDIF(); a.MUL(r1, r2, r3); - a.CMP(r1, r2, r3, BRW_CONDITIONAL_GE); - a.IF(BRW_PREDICATE_NORMAL); + a.CMP(r1, r2, r3, ELK_CONDITIONAL_GE); + a.IF(ELK_PREDICATE_NORMAL); a.BREAK(); a.ENDIF(); a.AND(r1, r2, r3); @@ -321,16 +321,16 @@ TEST_F(PredicatedBreakTest, TwoBreaks) shader_a->calculate_cfg(); /* The IF/ENDIF around the breaks are expected to be removed. */ - bool progress = opt_predicated_break(shader_a); + bool progress = elk_opt_predicated_break(shader_a); EXPECT_TRUE(progress); b.DO(); b.ADD(r1, r2, r3); - b.CMP(r1, r2, r3, BRW_CONDITIONAL_NZ); - b.BREAK()->predicate = BRW_PREDICATE_NORMAL; + b.CMP(r1, r2, r3, ELK_CONDITIONAL_NZ); + b.BREAK()->predicate = ELK_PREDICATE_NORMAL; b.MUL(r1, r2, r3); - b.CMP(r1, r2, r3, BRW_CONDITIONAL_GE); - b.BREAK()->predicate = BRW_PREDICATE_NORMAL; + b.CMP(r1, r2, r3, ELK_CONDITIONAL_GE); + b.BREAK()->predicate = ELK_PREDICATE_NORMAL; b.AND(r1, r2, r3); b.WHILE(); b.NOP(); /* There's always going to be something after a WHILE. */ diff --git a/src/intel/compiler/elk/elk_test_simd_selection.cpp b/src/intel/compiler/elk/elk_test_simd_selection.cpp index 34b7847c292..63fbb7624a7 100644 --- a/src/intel/compiler/elk/elk_test_simd_selection.cpp +++ b/src/intel/compiler/elk/elk_test_simd_selection.cpp @@ -44,7 +44,7 @@ protected: SIMDSelectionTest() : mem_ctx(ralloc_context(NULL)) , devinfo(rzalloc(mem_ctx, intel_device_info)) - , prog_data(rzalloc(mem_ctx, struct brw_cs_prog_data)) + , prog_data(rzalloc(mem_ctx, struct elk_cs_prog_data)) , simd_state{ .devinfo = devinfo, .prog_data = prog_data, @@ -59,8 +59,8 @@ protected: void *mem_ctx; intel_device_info *devinfo; - struct brw_cs_prog_data *prog_data; - brw_simd_selection_state simd_state; + struct elk_cs_prog_data *prog_data; + elk_simd_selection_state simd_state; }; class SIMDSelectionCS : public SIMDSelectionTest { @@ -77,13 +77,13 @@ protected: TEST_F(SIMDSelectionCS, DefaultsToSIMD16) { - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, not_spilled); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, not_spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), SIMD16); + ASSERT_EQ(elk_simd_select(simd_state), SIMD16); } TEST_F(SIMDSelectionCS, TooBigFor16) @@ -92,12 +92,12 @@ TEST_F(SIMDSelectionCS, TooBigFor16) prog_data->local_size[1] = 32; prog_data->local_size[2] = 1; - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, spilled); - ASSERT_EQ(brw_simd_select(simd_state), SIMD32); + ASSERT_EQ(elk_simd_select(simd_state), SIMD32); } TEST_F(SIMDSelectionCS, WorkgroupSize1) @@ -106,12 +106,12 @@ TEST_F(SIMDSelectionCS, WorkgroupSize1) prog_data->local_size[1] = 1; prog_data->local_size[2] = 1; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), SIMD8); + ASSERT_EQ(elk_simd_select(simd_state), SIMD8); } TEST_F(SIMDSelectionCS, WorkgroupSize8) @@ -120,12 +120,12 @@ TEST_F(SIMDSelectionCS, WorkgroupSize8) prog_data->local_size[1] = 1; prog_data->local_size[2] = 1; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), SIMD8); + ASSERT_EQ(elk_simd_select(simd_state), SIMD8); } TEST_F(SIMDSelectionCS, WorkgroupSizeVariable) @@ -134,23 +134,23 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariable) prog_data->local_size[1] = 0; prog_data->local_size[2] = 0; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, not_spilled); ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD16 | 1u << SIMD32); const unsigned wg_8_1_1[] = { 8, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8); const unsigned wg_16_1_1[] = { 16, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16); const unsigned wg_32_1_1[] = { 32, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16); } TEST_F(SIMDSelectionCS, WorkgroupSizeVariableSpilled) @@ -159,23 +159,23 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariableSpilled) prog_data->local_size[1] = 0; prog_data->local_size[2] = 0; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, spilled); ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD16 | 1u << SIMD32); const unsigned wg_8_1_1[] = { 8, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8); const unsigned wg_16_1_1[] = { 16, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8); const unsigned wg_32_1_1[] = { 32, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8); } TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8) @@ -184,22 +184,22 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8) prog_data->local_size[1] = 0; prog_data->local_size[2] = 0; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, not_spilled); ASSERT_EQ(prog_data->prog_mask, 1u << SIMD16 | 1u << SIMD32); const unsigned wg_8_1_1[] = { 8, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD16); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD16); const unsigned wg_16_1_1[] = { 16, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16); const unsigned wg_32_1_1[] = { 32, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16); } TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD16) @@ -208,22 +208,22 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD16) prog_data->local_size[1] = 0; prog_data->local_size[2] = 0; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, not_spilled); ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD32); const unsigned wg_8_1_1[] = { 8, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8); const unsigned wg_16_1_1[] = { 16, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8); const unsigned wg_32_1_1[] = { 32, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8); } TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8NoSIMD16) @@ -232,167 +232,167 @@ TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8NoSIMD16) prog_data->local_size[1] = 0; prog_data->local_size[2] = 0; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, not_spilled); ASSERT_EQ(prog_data->prog_mask, 1u << SIMD32); const unsigned wg_8_1_1[] = { 8, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD32); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD32); const unsigned wg_16_1_1[] = { 16, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD32); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD32); const unsigned wg_32_1_1[] = { 32, 1, 1 }; - ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD32); + ASSERT_EQ(elk_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD32); } TEST_F(SIMDSelectionCS, SpillAtSIMD8) { - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, spilled); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), SIMD8); + ASSERT_EQ(elk_simd_select(simd_state), SIMD8); } TEST_F(SIMDSelectionCS, SpillAtSIMD16) { - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, spilled); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), SIMD8); + ASSERT_EQ(elk_simd_select(simd_state), SIMD8); } TEST_F(SIMDSelectionCS, EnvironmentVariable32) { intel_debug |= DEBUG_DO32; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, not_spilled); - ASSERT_EQ(brw_simd_select(simd_state), SIMD32); + ASSERT_EQ(elk_simd_select(simd_state), SIMD32); } TEST_F(SIMDSelectionCS, EnvironmentVariable32ButSpills) { intel_debug |= DEBUG_DO32; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, not_spilled); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, spilled); - ASSERT_EQ(brw_simd_select(simd_state), SIMD16); + ASSERT_EQ(elk_simd_select(simd_state), SIMD16); } TEST_F(SIMDSelectionCS, Require8) { simd_state.required_width = 8; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), SIMD8); + ASSERT_EQ(elk_simd_select(simd_state), SIMD8); } TEST_F(SIMDSelectionCS, Require8ErrorWhenNotCompile) { simd_state.required_width = 8; - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), -1); + ASSERT_EQ(elk_simd_select(simd_state), -1); } TEST_F(SIMDSelectionCS, Require16) { simd_state.required_width = 16; - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, not_spilled); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, not_spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), SIMD16); + ASSERT_EQ(elk_simd_select(simd_state), SIMD16); } TEST_F(SIMDSelectionCS, Require16ErrorWhenNotCompile) { simd_state.required_width = 16; - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), -1); + ASSERT_EQ(elk_simd_select(simd_state), -1); } TEST_F(SIMDSelectionCS, Require32) { simd_state.required_width = 32; - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, not_spilled); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, not_spilled); - ASSERT_EQ(brw_simd_select(simd_state), SIMD32); + ASSERT_EQ(elk_simd_select(simd_state), SIMD32); } TEST_F(SIMDSelectionCS, Require32ErrorWhenNotCompile) { simd_state.required_width = 32; - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_FALSE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); - ASSERT_EQ(brw_simd_select(simd_state), -1); + ASSERT_EQ(elk_simd_select(simd_state), -1); } TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD8) { - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - brw_simd_mark_compiled(simd_state, SIMD8, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + elk_simd_mark_compiled(simd_state, SIMD8, not_spilled); - ASSERT_TRUE(brw_simd_any_compiled(simd_state)); - ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD8); + ASSERT_TRUE(elk_simd_any_compiled(simd_state)); + ASSERT_EQ(elk_simd_first_compiled(simd_state), SIMD8); } TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD16) { - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - brw_simd_mark_compiled(simd_state, SIMD16, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + elk_simd_mark_compiled(simd_state, SIMD16, not_spilled); - ASSERT_TRUE(brw_simd_any_compiled(simd_state)); - ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD16); + ASSERT_TRUE(elk_simd_any_compiled(simd_state)); + ASSERT_EQ(elk_simd_first_compiled(simd_state), SIMD16); } TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD32) { - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16)); - ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32)); - brw_simd_mark_compiled(simd_state, SIMD32, not_spilled); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD8)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD16)); + ASSERT_TRUE(elk_simd_should_compile(simd_state, SIMD32)); + elk_simd_mark_compiled(simd_state, SIMD32, not_spilled); - ASSERT_TRUE(brw_simd_any_compiled(simd_state)); - ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD32); + ASSERT_TRUE(elk_simd_any_compiled(simd_state)); + ASSERT_EQ(elk_simd_first_compiled(simd_state), SIMD32); } diff --git a/src/intel/compiler/elk/elk_test_vec4_cmod_propagation.cpp b/src/intel/compiler/elk/elk_test_vec4_cmod_propagation.cpp index d636ca7df7f..c0ab51c1201 100644 --- a/src/intel/compiler/elk/elk_test_vec4_cmod_propagation.cpp +++ b/src/intel/compiler/elk/elk_test_vec4_cmod_propagation.cpp @@ -35,22 +35,22 @@ class cmod_propagation_vec4_test : public ::testing::Test { virtual void TearDown(); public: - struct brw_compiler *compiler; - struct brw_compile_params params; + struct elk_compiler *compiler; + struct elk_compile_params params; struct intel_device_info *devinfo; void *ctx; struct gl_shader_program *shader_prog; - struct brw_vue_prog_data *prog_data; + struct elk_vue_prog_data *prog_data; vec4_visitor *v; }; class cmod_propagation_vec4_visitor : public vec4_visitor { public: - cmod_propagation_vec4_visitor(struct brw_compiler *compiler, - struct brw_compile_params *params, + cmod_propagation_vec4_visitor(struct elk_compiler *compiler, + struct elk_compile_params *params, nir_shader *shader, - struct brw_vue_prog_data *prog_data) + struct elk_vue_prog_data *prog_data) : vec4_visitor(compiler, params, NULL, prog_data, shader, false, false) { @@ -99,14 +99,14 @@ protected: void cmod_propagation_vec4_test::SetUp() { ctx = ralloc_context(NULL); - compiler = rzalloc(ctx, struct brw_compiler); + compiler = rzalloc(ctx, struct elk_compiler); devinfo = rzalloc(ctx, struct intel_device_info); compiler->devinfo = devinfo; params = {}; params.mem_ctx = ctx; - prog_data = ralloc(ctx, struct brw_vue_prog_data); + prog_data = ralloc(ctx, struct elk_vue_prog_data); nir_shader *shader = nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL); @@ -126,7 +126,7 @@ void cmod_propagation_vec4_test::TearDown() } static vec4_instruction * -instruction(bblock_t *block, int num) +instruction(elk_bblock_t *block, int num) { vec4_instruction *inst = (vec4_instruction *)block->start(); for (int i = 0; i < num; i++) { @@ -161,12 +161,12 @@ TEST_F(cmod_propagation_vec4_test, basic) dst_reg dest = dst_reg(v, glsl_float_type()); src_reg src0 = src_reg(v, glsl_float_type()); src_reg src1 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); dst_reg dest_null = bld.null_reg_f(); dest_null.writemask = WRITEMASK_X; bld.ADD(dest, src0, src1); - bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE); + bld.CMP(dest_null, src_reg(dest), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -178,7 +178,7 @@ TEST_F(cmod_propagation_vec4_test, basic) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -187,8 +187,8 @@ TEST_F(cmod_propagation_vec4_test, basic) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask) @@ -197,11 +197,11 @@ TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask) dst_reg dest = dst_reg(v, glsl_float_type()); src_reg src0 = src_reg(v, glsl_float_type()); src_reg src1 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); dst_reg dest_null = bld.null_reg_f(); bld.ADD(dest, src0, src1); - bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE); + bld.CMP(dest_null, src_reg(dest), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -213,7 +213,7 @@ TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -222,10 +222,10 @@ TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, andz_one) @@ -233,11 +233,11 @@ TEST_F(cmod_propagation_vec4_test, andz_one) const vec4_builder bld = vec4_builder(v).at_end(); dst_reg dest = dst_reg(v, glsl_int_type()); src_reg src0 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); - src_reg one(brw_imm_d(1)); + src_reg zero(elk_imm_f(0.0f)); + src_reg one(elk_imm_d(1)); - bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); - set_condmod(BRW_CONDITIONAL_Z, + bld.CMP(retype(dest, ELK_REGISTER_TYPE_F), src0, zero, ELK_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_Z, bld.AND(bld.null_reg_d(), src_reg(dest), one)); /* = Before = @@ -249,7 +249,7 @@ TEST_F(cmod_propagation_vec4_test, andz_one) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -258,10 +258,10 @@ TEST_F(cmod_propagation_vec4_test, andz_one) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_AND, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, non_cmod_instruction) @@ -269,9 +269,9 @@ TEST_F(cmod_propagation_vec4_test, non_cmod_instruction) const vec4_builder bld = vec4_builder(v).at_end(); dst_reg dest = dst_reg(v, glsl_uint_type()); src_reg src0 = src_reg(v, glsl_uint_type()); - src_reg zero(brw_imm_ud(0u)); + src_reg zero(elk_imm_ud(0u)); bld.FBL(dest, src0); - bld.CMP(bld.null_reg_ud(), src_reg(dest), zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_ud(), src_reg(dest), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -283,7 +283,7 @@ TEST_F(cmod_propagation_vec4_test, non_cmod_instruction) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -292,9 +292,9 @@ TEST_F(cmod_propagation_vec4_test, non_cmod_instruction) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_FBL, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_FBL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, intervening_flag_write) @@ -304,10 +304,10 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_write) src_reg src0 = src_reg(v, glsl_float_type()); src_reg src1 = src_reg(v, glsl_float_type()); src_reg src2 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE); - bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), src2, zero, ELK_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), src_reg(dest), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -320,7 +320,7 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_write) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -329,11 +329,11 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_write) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, intervening_flag_read) @@ -344,10 +344,10 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read) src_reg src0 = src_reg(v, glsl_float_type()); src_reg src1 = src_reg(v, glsl_float_type()); src_reg src2 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); bld.ADD(dest0, src0, src1); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); - bld.CMP(bld.null_reg_f(), src_reg(dest0), zero, BRW_CONDITIONAL_GE); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); + bld.CMP(bld.null_reg_f(), src_reg(dest0), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -360,7 +360,7 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -369,11 +369,11 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, intervening_dest_write) @@ -383,11 +383,11 @@ TEST_F(cmod_propagation_vec4_test, intervening_dest_write) src_reg src0 = src_reg(v, glsl_float_type()); src_reg src1 = src_reg(v, glsl_float_type()); src_reg src2 = src_reg(v, glsl_vec2_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); bld.ADD(offset(dest, 8, 2), src0, src1); - bld.emit(SHADER_OPCODE_TEX, dest, src2) + bld.emit(ELK_SHADER_OPCODE_TEX, dest, src2) ->size_written = 4 * REG_SIZE; - bld.CMP(bld.null_reg_f(), offset(src_reg(dest), 8, 2), zero, BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), offset(src_reg(dest), 8, 2), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -400,7 +400,7 @@ TEST_F(cmod_propagation_vec4_test, intervening_dest_write) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -409,12 +409,12 @@ TEST_F(cmod_propagation_vec4_test, intervening_dest_write) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value) @@ -425,13 +425,13 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value) src_reg src0 = src_reg(v, glsl_float_type()); src_reg src1 = src_reg(v, glsl_float_type()); src_reg src2 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); dst_reg dest_null = bld.null_reg_f(); dest_null.writemask = WRITEMASK_X; - set_condmod(BRW_CONDITIONAL_GE, bld.ADD(dest0, src0, src1)); - set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); - bld.CMP(dest_null, src_reg(dest0), zero, BRW_CONDITIONAL_GE); + set_condmod(ELK_CONDITIONAL_GE, bld.ADD(dest0, src0, src1)); + set_predicate(ELK_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); + bld.CMP(dest_null, src_reg(dest0), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -445,7 +445,7 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -453,10 +453,10 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value) EXPECT_TRUE(cmod_propagation(v)); ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_vec4_test, negate) @@ -465,13 +465,13 @@ TEST_F(cmod_propagation_vec4_test, negate) dst_reg dest = dst_reg(v, glsl_float_type()); src_reg src0 = src_reg(v, glsl_float_type()); src_reg src1 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); src_reg tmp_src = src_reg(dest); tmp_src.negate = true; dst_reg dest_null = bld.null_reg_f(); dest_null.writemask = WRITEMASK_X; - bld.CMP(dest_null, tmp_src, zero, BRW_CONDITIONAL_GE); + bld.CMP(dest_null, tmp_src, zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -483,7 +483,7 @@ TEST_F(cmod_propagation_vec4_test, negate) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -491,8 +491,8 @@ TEST_F(cmod_propagation_vec4_test, negate) EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, movnz) @@ -504,8 +504,8 @@ TEST_F(cmod_propagation_vec4_test, movnz) dst_reg dest_null = bld.null_reg_f(); dest_null.writemask = WRITEMASK_X; - bld.CMP(dest, src0, src1, BRW_CONDITIONAL_L); - set_condmod(BRW_CONDITIONAL_NZ, + bld.CMP(dest, src0, src1, ELK_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_NZ, bld.MOV(dest_null, src_reg(dest))); /* = Before = @@ -518,7 +518,7 @@ TEST_F(cmod_propagation_vec4_test, movnz) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -527,8 +527,8 @@ TEST_F(cmod_propagation_vec4_test, movnz) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero) @@ -537,10 +537,10 @@ TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero) dst_reg dest = dst_reg(v, glsl_int_type()); src_reg src0 = src_reg(v, glsl_int_type()); src_reg src1 = src_reg(v, glsl_int_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); bld.ADD(dest, src0, src1); - bld.CMP(bld.null_reg_f(), retype(src_reg(dest), BRW_REGISTER_TYPE_F), zero, - BRW_CONDITIONAL_GE); + bld.CMP(bld.null_reg_f(), retype(src_reg(dest), ELK_REGISTER_TYPE_F), zero, + ELK_CONDITIONAL_GE); /* = Before = * @@ -552,7 +552,7 @@ TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -561,9 +561,9 @@ TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, andnz_non_one) @@ -571,11 +571,11 @@ TEST_F(cmod_propagation_vec4_test, andnz_non_one) const vec4_builder bld = vec4_builder(v).at_end(); dst_reg dest = dst_reg(v, glsl_int_type()); src_reg src0 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); - src_reg nonone(brw_imm_d(38)); + src_reg zero(elk_imm_f(0.0f)); + src_reg nonone(elk_imm_d(38)); - bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); - set_condmod(BRW_CONDITIONAL_NZ, + bld.CMP(retype(dest, ELK_REGISTER_TYPE_F), src0, zero, ELK_CONDITIONAL_L); + set_condmod(ELK_CONDITIONAL_NZ, bld.AND(bld.null_reg_d(), src_reg(dest), nonone)); /* = Before = @@ -587,7 +587,7 @@ TEST_F(cmod_propagation_vec4_test, andnz_non_one) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -596,10 +596,10 @@ TEST_F(cmod_propagation_vec4_test, andnz_non_one) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_AND, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } /* Note that basic is using glsl_type:float types, while this one is using @@ -610,10 +610,10 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4) dst_reg dest = dst_reg(v, glsl_vec4_type()); src_reg src0 = src_reg(v, glsl_vec4_type()); src_reg src1 = src_reg(v, glsl_vec4_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); bld.MUL(dest, src0, src1); - bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_f(), src_reg(dest), zero, ELK_CONDITIONAL_NZ); /* = Before = * 0: mul dest.xyzw src0.xyzw src1.xyzw @@ -624,7 +624,7 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -633,8 +633,8 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask) @@ -644,11 +644,11 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask) dest.writemask = WRITEMASK_X; src_reg src0 = src_reg(v, glsl_vec4_type()); src_reg src1 = src_reg(v, glsl_vec4_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); dst_reg dest_null = bld.null_reg_f(); bld.MUL(dest, src0, src1); - bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_NZ); + bld.CMP(dest_null, src_reg(dest), zero, ELK_CONDITIONAL_NZ); /* = Before = * 0: mul dest.x src0 src1 @@ -659,7 +659,7 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -668,10 +668,10 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4) @@ -682,16 +682,16 @@ TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4) src_reg src0 = src_reg(v, glsl_vec4_type()); src_reg src1 = src_reg(v, glsl_vec4_type()); src_reg src2 = src_reg(v, glsl_vec4_type()); - src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX; + src0.swizzle = src1.swizzle = src2.swizzle = ELK_SWIZZLE_XXXX; src2.negate = true; - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); src_reg tmp(dest); - tmp.swizzle = BRW_SWIZZLE_XXXX; + tmp.swizzle = ELK_SWIZZLE_XXXX; dst_reg dest_null = bld.null_reg_f(); dest_null.writemask = WRITEMASK_X; bld.MAD(dest, src0, src1, src2); - bld.CMP(dest_null, tmp, zero, BRW_CONDITIONAL_L); + bld.CMP(dest_null, tmp, zero, ELK_CONDITIONAL_L); /* = Before = * @@ -703,7 +703,7 @@ TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -712,8 +712,8 @@ TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_MAD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4) @@ -724,15 +724,15 @@ TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4) src_reg src0 = src_reg(v, glsl_vec4_type()); src_reg src1 = src_reg(v, glsl_vec4_type()); src_reg src2 = src_reg(v, glsl_vec4_type()); - src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX; + src0.swizzle = src1.swizzle = src2.swizzle = ELK_SWIZZLE_XXXX; src2.negate = true; - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); src_reg tmp(dest); - tmp.swizzle = BRW_SWIZZLE_XXXX; + tmp.swizzle = ELK_SWIZZLE_XXXX; dst_reg dest_null = bld.null_reg_f(); bld.MAD(dest, src0, src1, src2); - bld.CMP(dest_null, tmp, zero, BRW_CONDITIONAL_L); + bld.CMP(dest_null, tmp, zero, ELK_CONDITIONAL_L); /* = Before = * @@ -744,7 +744,7 @@ TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -753,10 +753,10 @@ TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_MAD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4) @@ -765,16 +765,16 @@ TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4) dst_reg dest = dst_reg(v, glsl_ivec4_type()); dest.writemask = WRITEMASK_X; src_reg src0 = src_reg(v, glsl_ivec4_type()); - src0.swizzle = BRW_SWIZZLE_XXXX; + src0.swizzle = ELK_SWIZZLE_XXXX; src0.file = UNIFORM; - src_reg nonone = retype(brw_imm_d(16), BRW_REGISTER_TYPE_D); + src_reg nonone = retype(elk_imm_d(16), ELK_REGISTER_TYPE_D); src_reg mov_src = src_reg(dest); - mov_src.swizzle = BRW_SWIZZLE_XXXX; + mov_src.swizzle = ELK_SWIZZLE_XXXX; dst_reg dest_null = bld.null_reg_d(); dest_null.writemask = WRITEMASK_X; - bld.CMP(dest, src0, nonone, BRW_CONDITIONAL_GE); - set_condmod(BRW_CONDITIONAL_NZ, + bld.CMP(dest, src0, nonone, ELK_CONDITIONAL_GE); + set_condmod(ELK_CONDITIONAL_NZ, bld.MOV(dest_null, mov_src)); /* = Before = @@ -787,7 +787,7 @@ TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -796,8 +796,8 @@ TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4) @@ -806,12 +806,12 @@ TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4) dst_reg dest = dst_reg(v, glsl_vec4_type()); src_reg src0 = src_reg(v, glsl_vec4_type()); src_reg src1 = src_reg(v, glsl_vec4_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); src_reg cmp_src = src_reg(dest); - cmp_src.swizzle = BRW_SWIZZLE4(0,1,3,2); + cmp_src.swizzle = ELK_SWIZZLE4(0,1,3,2); bld.MUL(dest, src0, src1); - bld.CMP(bld.null_reg_f(), cmp_src, zero, BRW_CONDITIONAL_NZ); + bld.CMP(bld.null_reg_f(), cmp_src, zero, ELK_CONDITIONAL_NZ); /* = Before = * 0: mul dest src0 src1 @@ -822,7 +822,7 @@ TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -831,10 +831,10 @@ TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_MUL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask) @@ -846,7 +846,7 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask) dst_reg dest_null = bld.null_reg_f(); bld.ADD(dest, src0, src1); - vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE); + vec4_instruction *inst = bld.CMP(dest_null, src0, src1, ELK_CONDITIONAL_GE); inst->src[1].negate = true; /* = Before = @@ -859,7 +859,7 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -868,8 +868,8 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(0, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask) @@ -881,7 +881,7 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask) dst_reg dest_null = bld.null_reg_f(); bld.ADD(dest, src0, src1); - vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE); + vec4_instruction *inst = bld.CMP(dest_null, src0, src1, ELK_CONDITIONAL_GE); inst->src[1].negate = true; /* = Before = @@ -894,7 +894,7 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -903,10 +903,10 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7) @@ -918,14 +918,14 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7) src_reg src1 = src_reg(v, glsl_float_type()); src_reg src2 = src_reg(v, glsl_float_type()); src_reg src3 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); dst_reg dest_null = bld.null_reg_f(); dest_null.writemask = WRITEMASK_X; bld.ADD(dest1, src0, src1); bld.SEL(dest2, src2, src3) - ->conditional_mod = BRW_CONDITIONAL_GE; - bld.CMP(dest_null, src_reg(dest1), zero, BRW_CONDITIONAL_GE); + ->conditional_mod = ELK_CONDITIONAL_GE; + bld.CMP(dest_null, src_reg(dest1), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -939,7 +939,7 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -948,10 +948,10 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5) @@ -966,14 +966,14 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5) src_reg src1 = src_reg(v, glsl_float_type()); src_reg src2 = src_reg(v, glsl_float_type()); src_reg src3 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); dst_reg dest_null = bld.null_reg_f(); dest_null.writemask = WRITEMASK_X; bld.ADD(dest1, src0, src1); bld.SEL(dest2, src2, src3) - ->conditional_mod = BRW_CONDITIONAL_GE; - bld.CMP(dest_null, src_reg(dest1), zero, BRW_CONDITIONAL_GE); + ->conditional_mod = ELK_CONDITIONAL_GE; + bld.CMP(dest_null, src_reg(dest1), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -991,7 +991,7 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); @@ -1000,12 +1000,12 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(2, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_ADD, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 2)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5) @@ -1017,13 +1017,13 @@ TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5) dst_reg dest = dst_reg(v, glsl_float_type()); src_reg src0 = src_reg(v, glsl_float_type()); src_reg src1 = src_reg(v, glsl_float_type()); - src_reg zero(brw_imm_f(0.0f)); + src_reg zero(elk_imm_f(0.0f)); dst_reg dest_null = bld.null_reg_f(); dest_null.writemask = WRITEMASK_X; bld.SEL(dest, src0, src1) - ->conditional_mod = BRW_CONDITIONAL_GE; - bld.CMP(dest_null, src_reg(dest), zero, BRW_CONDITIONAL_GE); + ->conditional_mod = ELK_CONDITIONAL_GE; + bld.CMP(dest_null, src_reg(dest), zero, ELK_CONDITIONAL_GE); /* = Before = * @@ -1040,7 +1040,7 @@ TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5) */ v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; + elk_bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); @@ -1049,8 +1049,8 @@ TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5) ASSERT_EQ(0, block0->start_ip); ASSERT_EQ(1, block0->end_ip); - EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 0)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); - EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); - EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_SEL, instruction(block0, 0)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); + EXPECT_EQ(ELK_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(ELK_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } diff --git a/src/intel/compiler/elk/elk_test_vec4_copy_propagation.cpp b/src/intel/compiler/elk/elk_test_vec4_copy_propagation.cpp index 8e55cf2b34a..85bd0db9fab 100644 --- a/src/intel/compiler/elk/elk_test_vec4_copy_propagation.cpp +++ b/src/intel/compiler/elk/elk_test_vec4_copy_propagation.cpp @@ -31,22 +31,22 @@ class copy_propagation_vec4_test : public ::testing::Test { virtual void TearDown(); public: - struct brw_compiler *compiler; - struct brw_compile_params params; + struct elk_compiler *compiler; + struct elk_compile_params params; struct intel_device_info *devinfo; void *ctx; struct gl_shader_program *shader_prog; - struct brw_vue_prog_data *prog_data; + struct elk_vue_prog_data *prog_data; vec4_visitor *v; }; class copy_propagation_vec4_visitor : public vec4_visitor { public: - copy_propagation_vec4_visitor(struct brw_compiler *compiler, - struct brw_compile_params *params, + copy_propagation_vec4_visitor(struct elk_compiler *compiler, + struct elk_compile_params *params, nir_shader *shader, - struct brw_vue_prog_data *prog_data) + struct elk_vue_prog_data *prog_data) : vec4_visitor(compiler, params, NULL, prog_data, shader, false /* no_spills */, false) { @@ -89,14 +89,14 @@ protected: void copy_propagation_vec4_test::SetUp() { ctx = ralloc_context(NULL); - compiler = rzalloc(ctx, struct brw_compiler); + compiler = rzalloc(ctx, struct elk_compiler); devinfo = rzalloc(ctx, struct intel_device_info); compiler->devinfo = devinfo; params = {}; params.mem_ctx = ctx; - prog_data = ralloc(ctx, struct brw_vue_prog_data); + prog_data = ralloc(ctx, struct elk_vue_prog_data); nir_shader *shader = nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL); @@ -143,25 +143,25 @@ TEST_F(copy_propagation_vec4_test, test_swizzle_swizzle) v->emit(v->ADD(a, src_reg(a), src_reg(a))); - v->emit(v->MOV(b, swizzle(src_reg(a), BRW_SWIZZLE4(BRW_SWIZZLE_Y, - BRW_SWIZZLE_Z, - BRW_SWIZZLE_W, - BRW_SWIZZLE_X)))); + v->emit(v->MOV(b, swizzle(src_reg(a), ELK_SWIZZLE4(ELK_SWIZZLE_Y, + ELK_SWIZZLE_Z, + ELK_SWIZZLE_W, + ELK_SWIZZLE_X)))); vec4_instruction *test_mov = - v->MOV(c, swizzle(src_reg(b), BRW_SWIZZLE4(BRW_SWIZZLE_Y, - BRW_SWIZZLE_Z, - BRW_SWIZZLE_W, - BRW_SWIZZLE_X))); + v->MOV(c, swizzle(src_reg(b), ELK_SWIZZLE4(ELK_SWIZZLE_Y, + ELK_SWIZZLE_Z, + ELK_SWIZZLE_W, + ELK_SWIZZLE_X))); v->emit(test_mov); copy_propagation(v); EXPECT_EQ(test_mov->src[0].nr, a.nr); - EXPECT_EQ(test_mov->src[0].swizzle, BRW_SWIZZLE4(BRW_SWIZZLE_Z, - BRW_SWIZZLE_W, - BRW_SWIZZLE_X, - BRW_SWIZZLE_Y)); + EXPECT_EQ(test_mov->src[0].swizzle, ELK_SWIZZLE4(ELK_SWIZZLE_Z, + ELK_SWIZZLE_W, + ELK_SWIZZLE_X, + ELK_SWIZZLE_Y)); } TEST_F(copy_propagation_vec4_test, test_swizzle_writemask) @@ -170,26 +170,26 @@ TEST_F(copy_propagation_vec4_test, test_swizzle_writemask) dst_reg b = dst_reg(v, glsl_vec4_type()); dst_reg c = dst_reg(v, glsl_vec4_type()); - v->emit(v->MOV(b, swizzle(src_reg(a), BRW_SWIZZLE4(BRW_SWIZZLE_X, - BRW_SWIZZLE_Y, - BRW_SWIZZLE_X, - BRW_SWIZZLE_Z)))); + v->emit(v->MOV(b, swizzle(src_reg(a), ELK_SWIZZLE4(ELK_SWIZZLE_X, + ELK_SWIZZLE_Y, + ELK_SWIZZLE_X, + ELK_SWIZZLE_Z)))); - v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), brw_imm_f(1.0f))); + v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), elk_imm_f(1.0f))); vec4_instruction *test_mov = - v->MOV(c, swizzle(src_reg(b), BRW_SWIZZLE4(BRW_SWIZZLE_W, - BRW_SWIZZLE_W, - BRW_SWIZZLE_W, - BRW_SWIZZLE_W))); + v->MOV(c, swizzle(src_reg(b), ELK_SWIZZLE4(ELK_SWIZZLE_W, + ELK_SWIZZLE_W, + ELK_SWIZZLE_W, + ELK_SWIZZLE_W))); v->emit(test_mov); copy_propagation(v); /* should not copy propagate */ EXPECT_EQ(test_mov->src[0].nr, b.nr); - EXPECT_EQ(test_mov->src[0].swizzle, BRW_SWIZZLE4(BRW_SWIZZLE_W, - BRW_SWIZZLE_W, - BRW_SWIZZLE_W, - BRW_SWIZZLE_W)); + EXPECT_EQ(test_mov->src[0].swizzle, ELK_SWIZZLE4(ELK_SWIZZLE_W, + ELK_SWIZZLE_W, + ELK_SWIZZLE_W, + ELK_SWIZZLE_W)); } diff --git a/src/intel/compiler/elk/elk_test_vec4_dead_code_eliminate.cpp b/src/intel/compiler/elk/elk_test_vec4_dead_code_eliminate.cpp index 7ec4e563f4d..49df35d588f 100644 --- a/src/intel/compiler/elk/elk_test_vec4_dead_code_eliminate.cpp +++ b/src/intel/compiler/elk/elk_test_vec4_dead_code_eliminate.cpp @@ -31,22 +31,22 @@ class dead_code_eliminate_vec4_test : public ::testing::Test { virtual void TearDown(); public: - struct brw_compiler *compiler; - struct brw_compile_params params; + struct elk_compiler *compiler; + struct elk_compile_params params; struct intel_device_info *devinfo; void *ctx; struct gl_shader_program *shader_prog; - struct brw_vue_prog_data *prog_data; + struct elk_vue_prog_data *prog_data; vec4_visitor *v; }; class dead_code_eliminate_vec4_visitor : public vec4_visitor { public: - dead_code_eliminate_vec4_visitor(struct brw_compiler *compiler, - struct brw_compile_params *params, + dead_code_eliminate_vec4_visitor(struct elk_compiler *compiler, + struct elk_compile_params *params, nir_shader *shader, - struct brw_vue_prog_data *prog_data) + struct elk_vue_prog_data *prog_data) : vec4_visitor(compiler, params, NULL, prog_data, shader, false /* no_spills */, false) { @@ -89,14 +89,14 @@ protected: void dead_code_eliminate_vec4_test::SetUp() { ctx = ralloc_context(NULL); - compiler = rzalloc(ctx, struct brw_compiler); + compiler = rzalloc(ctx, struct elk_compiler); devinfo = rzalloc(ctx, struct intel_device_info); compiler->devinfo = devinfo; params = {}; params.mem_ctx = ctx; - prog_data = ralloc(ctx, struct brw_vue_prog_data); + prog_data = ralloc(ctx, struct elk_vue_prog_data); nir_shader *shader = nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL); @@ -151,21 +151,21 @@ TEST_F(dead_code_eliminate_vec4_test, some_dead_channels_all_flags_used) * (+f0.x) sel(8) g6<1>UD g3<4>UD g6<4>UD */ vec4_instruction *test_cmp = - bld.CMP(dst_reg(r4), r2, r1, BRW_CONDITIONAL_L); + bld.CMP(dst_reg(r4), r2, r1, ELK_CONDITIONAL_L); - test_cmp->src[0].swizzle = BRW_SWIZZLE_WWWW; - test_cmp->src[1].swizzle = BRW_SWIZZLE_XXXX; + test_cmp->src[0].swizzle = ELK_SWIZZLE_WWWW; + test_cmp->src[1].swizzle = ELK_SWIZZLE_XXXX; vec4_instruction *test_mov = bld.MOV(dst_reg(r5), r4); test_mov->dst.writemask = WRITEMASK_X; - test_mov->src[0].swizzle = BRW_SWIZZLE_XXXX; + test_mov->src[0].swizzle = ELK_SWIZZLE_XXXX; vec4_instruction *test_sel = bld.SEL(dst_reg(r6), r3, r6); - set_predicate(BRW_PREDICATE_NORMAL, test_sel); + set_predicate(ELK_PREDICATE_NORMAL, test_sel); /* The scratch write is here just to make r5 and r6 be live so that the * whole program doesn't get eliminated by DCE. diff --git a/src/intel/compiler/elk/elk_test_vec4_register_coalesce.cpp b/src/intel/compiler/elk/elk_test_vec4_register_coalesce.cpp index 160674dbcfa..353c1157c3b 100644 --- a/src/intel/compiler/elk/elk_test_vec4_register_coalesce.cpp +++ b/src/intel/compiler/elk/elk_test_vec4_register_coalesce.cpp @@ -33,12 +33,12 @@ class register_coalesce_vec4_test : public ::testing::Test { virtual void TearDown(); public: - struct brw_compiler *compiler; - struct brw_compile_params params; + struct elk_compiler *compiler; + struct elk_compile_params params; struct intel_device_info *devinfo; void *ctx; struct gl_shader_program *shader_prog; - struct brw_vue_prog_data *prog_data; + struct elk_vue_prog_data *prog_data; vec4_visitor *v; }; @@ -46,10 +46,10 @@ public: class register_coalesce_vec4_visitor : public vec4_visitor { public: - register_coalesce_vec4_visitor(struct brw_compiler *compiler, - struct brw_compile_params *params, + register_coalesce_vec4_visitor(struct elk_compiler *compiler, + struct elk_compile_params *params, nir_shader *shader, - struct brw_vue_prog_data *prog_data) + struct elk_vue_prog_data *prog_data) : vec4_visitor(compiler, params, NULL, prog_data, shader, false /* no_spills */, false) { @@ -92,11 +92,11 @@ protected: void register_coalesce_vec4_test::SetUp() { ctx = ralloc_context(NULL); - compiler = rzalloc(ctx, struct brw_compiler); + compiler = rzalloc(ctx, struct elk_compiler); devinfo = rzalloc(ctx, struct intel_device_info); compiler->devinfo = devinfo; - prog_data = ralloc(ctx, struct brw_vue_prog_data); + prog_data = ralloc(ctx, struct elk_vue_prog_data); params = {}; params.mem_ctx = ctx; @@ -146,9 +146,9 @@ TEST_F(register_coalesce_vec4_test, test_compute_to_mrf) dst_reg m0 = dst_reg(MRF, 0); m0.writemask = WRITEMASK_X; - m0.type = BRW_REGISTER_TYPE_F; + m0.type = ELK_REGISTER_TYPE_F; - vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); + vec4_instruction *mul = v->emit(v->MUL(temp, something, elk_imm_f(1.0f))); v->emit(v->MOV(m0, src_reg(temp))); register_coalesce(v); @@ -165,17 +165,17 @@ TEST_F(register_coalesce_vec4_test, test_multiple_use) dst_reg m0 = dst_reg(MRF, 0); m0.writemask = WRITEMASK_X; - m0.type = BRW_REGISTER_TYPE_F; + m0.type = ELK_REGISTER_TYPE_F; dst_reg m1 = dst_reg(MRF, 1); m1.writemask = WRITEMASK_XYZW; - m1.type = BRW_REGISTER_TYPE_F; + m1.type = ELK_REGISTER_TYPE_F; src_reg src = src_reg(temp); - vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); - src.swizzle = BRW_SWIZZLE_XXXX; + vec4_instruction *mul = v->emit(v->MUL(temp, something, elk_imm_f(1.0f))); + src.swizzle = ELK_SWIZZLE_XXXX; v->emit(v->MOV(m0, src)); - src.swizzle = BRW_SWIZZLE_XYZW; + src.swizzle = ELK_SWIZZLE_XYZW; v->emit(v->MOV(m1, src)); register_coalesce(v); @@ -191,7 +191,7 @@ TEST_F(register_coalesce_vec4_test, test_dp4_mrf) dst_reg m0 = dst_reg(MRF, 0); m0.writemask = WRITEMASK_Y; - m0.type = BRW_REGISTER_TYPE_F; + m0.type = ELK_REGISTER_TYPE_F; dst_reg temp = dst_reg(v, glsl_float_type()); diff --git a/src/intel/compiler/elk/elk_test_vf_float_conversions.cpp b/src/intel/compiler/elk/elk_test_vf_float_conversions.cpp index 25252d4840f..f9a2f9606b3 100644 --- a/src/intel/compiler/elk/elk_test_vf_float_conversions.cpp +++ b/src/intel/compiler/elk/elk_test_vf_float_conversions.cpp @@ -67,7 +67,7 @@ TEST_F(vf_float_conversion_test, test_vf_to_float) if (vf > 127) expected = -expected; - EXPECT_EQ(f2u(expected), f2u(brw_vf_to_float(vf))); + EXPECT_EQ(f2u(expected), f2u(elk_vf_to_float(vf))); } } @@ -78,7 +78,7 @@ TEST_F(vf_float_conversion_test, test_float_to_vf) if (vf > 127) f = -f; - EXPECT_EQ(vf, brw_float_to_vf(f)); + EXPECT_EQ(vf, elk_float_to_vf(f)); } } @@ -87,24 +87,24 @@ TEST_F(vf_float_conversion_test, test_special_case_0) /* ±0.0f are special cased to the VFs that would otherwise correspond * to ±0.125f. Make sure we can't convert these values to VF. */ - EXPECT_EQ(brw_float_to_vf(+0.125f), -1); - EXPECT_EQ(brw_float_to_vf(-0.125f), -1); + EXPECT_EQ(elk_float_to_vf(+0.125f), -1); + EXPECT_EQ(elk_float_to_vf(-0.125f), -1); - EXPECT_EQ(f2u(brw_vf_to_float(brw_float_to_vf(+0.0f))), f2u(+0.0f)); - EXPECT_EQ(f2u(brw_vf_to_float(brw_float_to_vf(-0.0f))), f2u(-0.0f)); + EXPECT_EQ(f2u(elk_vf_to_float(elk_float_to_vf(+0.0f))), f2u(+0.0f)); + EXPECT_EQ(f2u(elk_vf_to_float(elk_float_to_vf(-0.0f))), f2u(-0.0f)); } TEST_F(vf_float_conversion_test, test_nonrepresentable_float_input) { - EXPECT_EQ(brw_float_to_vf(+32.0f), -1); - EXPECT_EQ(brw_float_to_vf(-32.0f), -1); + EXPECT_EQ(elk_float_to_vf(+32.0f), -1); + EXPECT_EQ(elk_float_to_vf(-32.0f), -1); - EXPECT_EQ(brw_float_to_vf(+16.5f), -1); - EXPECT_EQ(brw_float_to_vf(-16.5f), -1); + EXPECT_EQ(elk_float_to_vf(+16.5f), -1); + EXPECT_EQ(elk_float_to_vf(-16.5f), -1); - EXPECT_EQ(brw_float_to_vf(+8.25f), -1); - EXPECT_EQ(brw_float_to_vf(-8.25f), -1); + EXPECT_EQ(elk_float_to_vf(+8.25f), -1); + EXPECT_EQ(elk_float_to_vf(-8.25f), -1); - EXPECT_EQ(brw_float_to_vf(+4.125f), -1); - EXPECT_EQ(brw_float_to_vf(-4.125f), -1); + EXPECT_EQ(elk_float_to_vf(+4.125f), -1); + EXPECT_EQ(elk_float_to_vf(-4.125f), -1); } diff --git a/src/intel/compiler/elk/elk_vec4.cpp b/src/intel/compiler/elk/elk_vec4.cpp index 7bfa4a1e9e8..f35335a7bf1 100644 --- a/src/intel/compiler/elk/elk_vec4.cpp +++ b/src/intel/compiler/elk/elk_vec4.cpp @@ -44,21 +44,21 @@ src_reg::init() { memset((void*)this, 0, sizeof(*this)); this->file = BAD_FILE; - this->type = BRW_REGISTER_TYPE_UD; + this->type = ELK_REGISTER_TYPE_UD; } -src_reg::src_reg(enum brw_reg_file file, int nr, const glsl_type *type) +src_reg::src_reg(enum elk_reg_file file, int nr, const glsl_type *type) { init(); this->file = file; this->nr = nr; if (type && (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type))) - this->swizzle = brw_swizzle_for_size(type->vector_elements); + this->swizzle = elk_swizzle_for_size(type->vector_elements); else - this->swizzle = BRW_SWIZZLE_XYZW; + this->swizzle = ELK_SWIZZLE_XYZW; if (type) - this->type = brw_type_for_base_type(type); + this->type = elk_type_for_base_type(type); } /** Generic unset register constructor. */ @@ -67,18 +67,18 @@ src_reg::src_reg() init(); } -src_reg::src_reg(struct ::brw_reg reg) : - backend_reg(reg) +src_reg::src_reg(struct ::elk_reg reg) : + elk_backend_reg(reg) { this->offset = 0; this->reladdr = NULL; } src_reg::src_reg(const dst_reg ®) : - backend_reg(reg) + elk_backend_reg(reg) { this->reladdr = reg.reladdr; - this->swizzle = brw_swizzle_for_mask(reg.writemask); + this->swizzle = elk_swizzle_for_mask(reg.writemask); } void @@ -86,7 +86,7 @@ dst_reg::init() { memset((void*)this, 0, sizeof(*this)); this->file = BAD_FILE; - this->type = BRW_REGISTER_TYPE_UD; + this->type = ELK_REGISTER_TYPE_UD; this->writemask = WRITEMASK_XYZW; } @@ -95,7 +95,7 @@ dst_reg::dst_reg() init(); } -dst_reg::dst_reg(enum brw_reg_file file, int nr) +dst_reg::dst_reg(enum elk_reg_file file, int nr) { init(); @@ -103,18 +103,18 @@ dst_reg::dst_reg(enum brw_reg_file file, int nr) this->nr = nr; } -dst_reg::dst_reg(enum brw_reg_file file, int nr, const glsl_type *type, +dst_reg::dst_reg(enum elk_reg_file file, int nr, const glsl_type *type, unsigned writemask) { init(); this->file = file; this->nr = nr; - this->type = brw_type_for_base_type(type); + this->type = elk_type_for_base_type(type); this->writemask = writemask; } -dst_reg::dst_reg(enum brw_reg_file file, int nr, brw_reg_type type, +dst_reg::dst_reg(enum elk_reg_file file, int nr, elk_reg_type type, unsigned writemask) { init(); @@ -125,24 +125,24 @@ dst_reg::dst_reg(enum brw_reg_file file, int nr, brw_reg_type type, this->writemask = writemask; } -dst_reg::dst_reg(struct ::brw_reg reg) : - backend_reg(reg) +dst_reg::dst_reg(struct ::elk_reg reg) : + elk_backend_reg(reg) { this->offset = 0; this->reladdr = NULL; } dst_reg::dst_reg(const src_reg ®) : - backend_reg(reg) + elk_backend_reg(reg) { - this->writemask = brw_mask_for_swizzle(reg.swizzle); + this->writemask = elk_mask_for_swizzle(reg.swizzle); this->reladdr = reg.reladdr; } bool dst_reg::equals(const dst_reg &r) const { - return (this->backend_reg::equals(r) && + return (this->elk_backend_reg::equals(r) && (reladdr == r.reladdr || (reladdr && r.reladdr && reladdr->equals(*r.reladdr)))); } @@ -151,14 +151,14 @@ bool vec4_instruction::is_send_from_grf() const { switch (opcode) { - case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: - case VEC4_OPCODE_UNTYPED_ATOMIC: - case VEC4_OPCODE_UNTYPED_SURFACE_READ: - case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: - case VEC4_OPCODE_URB_READ: - case VEC4_TCS_OPCODE_URB_WRITE: - case TCS_OPCODE_RELEASE_INPUT: - case SHADER_OPCODE_BARRIER: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE: + case ELK_VEC4_OPCODE_URB_READ: + case ELK_VEC4_TCS_OPCODE_URB_WRITE: + case ELK_TCS_OPCODE_RELEASE_INPUT: + case ELK_SHADER_OPCODE_BARRIER: return true; default: return false; @@ -188,9 +188,9 @@ bool vec4_instruction::has_source_and_destination_hazard() const { switch (opcode) { - case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: - case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: - case TES_OPCODE_ADD_INDIRECT_URB_OFFSET: + case ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: + case ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: + case ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET: return true; default: /* 8-wide compressed DF operations are executed as two 4-wide operations, @@ -207,14 +207,14 @@ unsigned vec4_instruction::size_read(unsigned arg) const { switch (opcode) { - case VEC4_OPCODE_UNTYPED_ATOMIC: - case VEC4_OPCODE_UNTYPED_SURFACE_READ: - case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: - case VEC4_TCS_OPCODE_URB_WRITE: + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE: + case ELK_VEC4_TCS_OPCODE_URB_WRITE: if (arg == 0) return mlen * REG_SIZE; break; - case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: if (arg == 1) return mlen * REG_SIZE; break; @@ -243,7 +243,7 @@ vec4_instruction::can_do_source_mods(const struct intel_device_info *devinfo) if (is_send_from_grf()) return false; - if (!backend_instruction::can_do_source_mods()) + if (!elk_backend_instruction::can_do_source_mods()) return false; return true; @@ -252,7 +252,7 @@ vec4_instruction::can_do_source_mods(const struct intel_device_info *devinfo) bool vec4_instruction::can_do_cmod() { - if (!backend_instruction::can_do_cmod()) + if (!elk_backend_instruction::can_do_cmod()) return false; /* The accumulator result appears to get used for the conditional modifier @@ -262,7 +262,7 @@ vec4_instruction::can_do_cmod() */ for (unsigned i = 0; i < 3; i++) { if (src[i].file != BAD_FILE && - brw_reg_type_is_unsigned_integer(src[i].type) && src[i].negate) + elk_reg_type_is_unsigned_integer(src[i].type) && src[i].negate) return false; } @@ -273,39 +273,39 @@ bool vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo) { switch (opcode) { - case SHADER_OPCODE_GFX4_SCRATCH_READ: - case VEC4_OPCODE_DOUBLE_TO_F32: - case VEC4_OPCODE_DOUBLE_TO_D32: - case VEC4_OPCODE_DOUBLE_TO_U32: - case VEC4_OPCODE_TO_DOUBLE: - case VEC4_OPCODE_PICK_LOW_32BIT: - case VEC4_OPCODE_PICK_HIGH_32BIT: - case VEC4_OPCODE_SET_LOW_32BIT: - case VEC4_OPCODE_SET_HIGH_32BIT: - case VS_OPCODE_PULL_CONSTANT_LOAD: - case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: - case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: - case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: - case TES_OPCODE_CREATE_INPUT_READ_HEADER: - case TES_OPCODE_ADD_INDIRECT_URB_OFFSET: - case VEC4_OPCODE_URB_READ: - case SHADER_OPCODE_MOV_INDIRECT: - case SHADER_OPCODE_TEX: - case FS_OPCODE_TXB: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_LZ: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_UMS: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXL_LZ: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_LOD: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_VEC4_OPCODE_DOUBLE_TO_F32: + case ELK_VEC4_OPCODE_DOUBLE_TO_D32: + case ELK_VEC4_OPCODE_DOUBLE_TO_U32: + case ELK_VEC4_OPCODE_TO_DOUBLE: + case ELK_VEC4_OPCODE_PICK_LOW_32BIT: + case ELK_VEC4_OPCODE_PICK_HIGH_32BIT: + case ELK_VEC4_OPCODE_SET_LOW_32BIT: + case ELK_VEC4_OPCODE_SET_HIGH_32BIT: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: + case ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: + case ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: + case ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER: + case ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET: + case ELK_VEC4_OPCODE_URB_READ: + case ELK_SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_TEX: + case ELK_FS_OPCODE_TXB: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_LZ: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_UMS: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXL_LZ: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_LOD: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_SAMPLEINFO: return false; default: /* The MATH instruction on Gfx6 only executes in align1 mode, which does @@ -323,10 +323,10 @@ vec4_instruction::can_change_types() const { return dst.type == src[0].type && !src[0].abs && !src[0].negate && !saturate && - (opcode == BRW_OPCODE_MOV || - (opcode == BRW_OPCODE_SEL && + (opcode == ELK_OPCODE_MOV || + (opcode == ELK_OPCODE_SEL && dst.type == src[1].type && - predicate != BRW_PREDICATE_NONE && + predicate != ELK_PREDICATE_NONE && !src[1].abs && !src[1].negate)); } @@ -344,47 +344,47 @@ vec4_instruction::implied_mrf_writes() const return 0; switch (opcode) { - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: return 1; - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: - case SHADER_OPCODE_POW: - case TCS_OPCODE_THREAD_END: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_POW: + case ELK_TCS_OPCODE_THREAD_END: return 2; - case VEC4_VS_OPCODE_URB_WRITE: + case ELK_VEC4_VS_OPCODE_URB_WRITE: return 1; - case VS_OPCODE_PULL_CONSTANT_LOAD: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD: return 2; - case SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: return 2; - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: return 3; - case VEC4_GS_OPCODE_URB_WRITE: - case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE: - case GS_OPCODE_THREAD_END: + case ELK_VEC4_GS_OPCODE_URB_WRITE: + case ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE: + case ELK_GS_OPCODE_THREAD_END: return 0; - case GS_OPCODE_FF_SYNC: + case ELK_GS_OPCODE_FF_SYNC: return 1; - case VEC4_TCS_OPCODE_URB_WRITE: + case ELK_VEC4_TCS_OPCODE_URB_WRITE: return 0; - case SHADER_OPCODE_TEX: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_SAMPLEINFO: - case SHADER_OPCODE_GET_BUFFER_SIZE: + case ELK_SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_GET_BUFFER_SIZE: return header_size; default: unreachable("not reached"); @@ -394,14 +394,14 @@ vec4_instruction::implied_mrf_writes() const bool src_reg::equals(const src_reg &r) const { - return (this->backend_reg::equals(r) && + return (this->elk_backend_reg::equals(r) && !reladdr && !r.reladdr); } bool src_reg::negative_equals(const src_reg &r) const { - return this->backend_reg::negative_equals(r) && + return this->elk_backend_reg::negative_equals(r) && !reladdr && !r.reladdr; } @@ -412,36 +412,36 @@ vec4_visitor::opt_vector_float() foreach_block(block, cfg) { unsigned last_reg = ~0u, last_offset = ~0u; - enum brw_reg_file last_reg_file = BAD_FILE; + enum elk_reg_file last_reg_file = BAD_FILE; uint8_t imm[4] = { 0 }; int inst_count = 0; vec4_instruction *imm_inst[4]; unsigned writemask = 0; - enum brw_reg_type dest_type = BRW_REGISTER_TYPE_F; + enum elk_reg_type dest_type = ELK_REGISTER_TYPE_F; foreach_inst_in_block_safe(vec4_instruction, inst, block) { int vf = -1; - enum brw_reg_type need_type = BRW_REGISTER_TYPE_LAST; + enum elk_reg_type need_type = ELK_REGISTER_TYPE_LAST; /* Look for unconditional MOVs from an immediate with a partial * writemask. Skip type-conversion MOVs other than integer 0, * where the type doesn't matter. See if the immediate can be * represented as a VF. */ - if (inst->opcode == BRW_OPCODE_MOV && + if (inst->opcode == ELK_OPCODE_MOV && inst->src[0].file == IMM && - inst->predicate == BRW_PREDICATE_NONE && + inst->predicate == ELK_PREDICATE_NONE && inst->dst.writemask != WRITEMASK_XYZW && type_sz(inst->src[0].type) < 8 && (inst->src[0].type == inst->dst.type || inst->src[0].d == 0)) { - vf = brw_float_to_vf(inst->src[0].d); - need_type = BRW_REGISTER_TYPE_D; + vf = elk_float_to_vf(inst->src[0].d); + need_type = ELK_REGISTER_TYPE_D; if (vf == -1) { - vf = brw_float_to_vf(inst->src[0].f); - need_type = BRW_REGISTER_TYPE_F; + vf = elk_float_to_vf(inst->src[0].f); + need_type = ELK_REGISTER_TYPE_F; } } else { last_reg = ~0u; @@ -459,7 +459,7 @@ vec4_visitor::opt_vector_float() if (inst_count > 1) { unsigned vf; memcpy(&vf, imm, sizeof(vf)); - vec4_instruction *mov = MOV(imm_inst[0]->dst, brw_imm_vf(vf)); + vec4_instruction *mov = MOV(imm_inst[0]->dst, elk_imm_vf(vf)); mov->dst.type = dest_type; mov->dst.writemask = writemask; inst->insert_before(block, mov); @@ -474,7 +474,7 @@ vec4_visitor::opt_vector_float() inst_count = 0; last_reg = ~0u;; writemask = 0; - dest_type = BRW_REGISTER_TYPE_F; + dest_type = ELK_REGISTER_TYPE_F; for (int i = 0; i < 4; i++) { imm[i] = 0; @@ -539,33 +539,33 @@ vec4_visitor::opt_reduce_swizzle() /* Determine which channels of the sources are read. */ switch (inst->opcode) { - case VEC4_OPCODE_PACK_BYTES: - case BRW_OPCODE_DP4: - case BRW_OPCODE_DPH: /* FINISHME: DPH reads only three channels of src0, + case ELK_VEC4_OPCODE_PACK_BYTES: + case ELK_OPCODE_DP4: + case ELK_OPCODE_DPH: /* FINISHME: DPH reads only three channels of src0, * but all four of src1. */ - swizzle = brw_swizzle_for_size(4); + swizzle = elk_swizzle_for_size(4); break; - case BRW_OPCODE_DP3: - swizzle = brw_swizzle_for_size(3); + case ELK_OPCODE_DP3: + swizzle = elk_swizzle_for_size(3); break; - case BRW_OPCODE_DP2: - swizzle = brw_swizzle_for_size(2); + case ELK_OPCODE_DP2: + swizzle = elk_swizzle_for_size(2); break; - case VEC4_OPCODE_TO_DOUBLE: - case VEC4_OPCODE_DOUBLE_TO_F32: - case VEC4_OPCODE_DOUBLE_TO_D32: - case VEC4_OPCODE_DOUBLE_TO_U32: - case VEC4_OPCODE_PICK_LOW_32BIT: - case VEC4_OPCODE_PICK_HIGH_32BIT: - case VEC4_OPCODE_SET_LOW_32BIT: - case VEC4_OPCODE_SET_HIGH_32BIT: - swizzle = brw_swizzle_for_size(4); + case ELK_VEC4_OPCODE_TO_DOUBLE: + case ELK_VEC4_OPCODE_DOUBLE_TO_F32: + case ELK_VEC4_OPCODE_DOUBLE_TO_D32: + case ELK_VEC4_OPCODE_DOUBLE_TO_U32: + case ELK_VEC4_OPCODE_PICK_LOW_32BIT: + case ELK_VEC4_OPCODE_PICK_HIGH_32BIT: + case ELK_VEC4_OPCODE_SET_LOW_32BIT: + case ELK_VEC4_OPCODE_SET_HIGH_32BIT: + swizzle = elk_swizzle_for_size(4); break; default: - swizzle = brw_swizzle_for_mask(inst->dst.writemask); + swizzle = elk_swizzle_for_mask(inst->dst.writemask); break; } @@ -577,7 +577,7 @@ vec4_visitor::opt_reduce_swizzle() continue; const unsigned new_swizzle = - brw_compose_swizzle(swizzle, inst->src[i].swizzle); + elk_compose_swizzle(swizzle, inst->src[i].swizzle); if (inst->src[i].swizzle != new_swizzle) { inst->src[i].swizzle = new_swizzle; progress = true; @@ -633,7 +633,7 @@ vec4_visitor::opt_algebraic() foreach_block_and_inst(block, vec4_instruction, inst, cfg) { switch (inst->opcode) { - case BRW_OPCODE_MOV: + case ELK_OPCODE_MOV: if (inst->src[0].file != IMM) break; @@ -646,59 +646,59 @@ vec4_visitor::opt_algebraic() * Other mixed-size-but-same-base-type cases may also be possible. */ if (inst->dst.type != inst->src[0].type && - inst->dst.type != BRW_REGISTER_TYPE_DF && - inst->src[0].type != BRW_REGISTER_TYPE_F) + inst->dst.type != ELK_REGISTER_TYPE_DF && + inst->src[0].type != ELK_REGISTER_TYPE_F) assert(!"unimplemented: saturate mixed types"); - if (brw_saturate_immediate(inst->src[0].type, - &inst->src[0].as_brw_reg())) { + if (elk_saturate_immediate(inst->src[0].type, + &inst->src[0].as_elk_reg())) { inst->saturate = false; progress = true; } } break; - case BRW_OPCODE_OR: + case ELK_OPCODE_OR: if (inst->src[1].is_zero()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->src[1] = src_reg(); progress = true; } break; - case VEC4_OPCODE_UNPACK_UNIFORM: + case ELK_VEC4_OPCODE_UNPACK_UNIFORM: if (inst->src[0].file != UNIFORM) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; progress = true; } break; - case BRW_OPCODE_ADD: + case ELK_OPCODE_ADD: if (inst->src[1].is_zero()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->src[1] = src_reg(); progress = true; } break; - case BRW_OPCODE_MUL: + case ELK_OPCODE_MUL: if (inst->src[1].file != IMM) continue; - if (brw_reg_type_is_floating_point(inst->src[1].type)) + if (elk_reg_type_is_floating_point(inst->src[1].type)) break; if (inst->src[1].is_zero()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; switch (inst->src[0].type) { - case BRW_REGISTER_TYPE_F: - inst->src[0] = brw_imm_f(0.0f); + case ELK_REGISTER_TYPE_F: + inst->src[0] = elk_imm_f(0.0f); break; - case BRW_REGISTER_TYPE_D: - inst->src[0] = brw_imm_d(0); + case ELK_REGISTER_TYPE_D: + inst->src[0] = elk_imm_d(0); break; - case BRW_REGISTER_TYPE_UD: - inst->src[0] = brw_imm_ud(0u); + case ELK_REGISTER_TYPE_UD: + inst->src[0] = elk_imm_ud(0u); break; default: unreachable("not reached"); @@ -706,20 +706,20 @@ vec4_visitor::opt_algebraic() inst->src[1] = src_reg(); progress = true; } else if (inst->src[1].is_one()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->src[1] = src_reg(); progress = true; } else if (inst->src[1].is_negative_one()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->src[0].negate = !inst->src[0].negate; inst->src[1] = src_reg(); progress = true; } break; - case SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_BROADCAST: if (is_uniform(inst->src[0]) || inst->src[1].is_zero()) { - inst->opcode = BRW_OPCODE_MOV; + inst->opcode = ELK_OPCODE_MOV; inst->src[1] = src_reg(); inst->force_writemask_all = true; progress = true; @@ -743,8 +743,8 @@ bool vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst) { #define IS_DWORD(reg) \ - (reg.type == BRW_REGISTER_TYPE_UD || \ - reg.type == BRW_REGISTER_TYPE_D) + (reg.type == ELK_REGISTER_TYPE_UD || \ + reg.type == ELK_REGISTER_TYPE_D) #define IS_64BIT(reg) (reg.file != BAD_FILE && type_sz(reg.type) == 8) @@ -797,10 +797,10 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst) void vec4_visitor::opt_set_dependency_control() { - vec4_instruction *last_grf_write[BRW_MAX_GRF]; - uint8_t grf_channels_written[BRW_MAX_GRF]; - vec4_instruction *last_mrf_write[BRW_MAX_GRF]; - uint8_t mrf_channels_written[BRW_MAX_GRF]; + vec4_instruction *last_grf_write[ELK_MAX_GRF]; + uint8_t grf_channels_written[ELK_MAX_GRF]; + vec4_instruction *last_mrf_write[ELK_MAX_GRF]; + uint8_t mrf_channels_written[ELK_MAX_GRF]; assert(prog_data->total_grf || !"Must be called after register allocation"); @@ -872,7 +872,7 @@ vec4_instruction::can_reswizzle(const struct intel_device_info *devinfo, /* Gfx6 MATH instructions can not execute in align16 mode, so swizzles * are not allowed. */ - if (devinfo->ver == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW) + if (devinfo->ver == 6 && is_math() && swizzle != ELK_SWIZZLE_XYZW) return false; /* If we write to the flag register changing the swizzle would change @@ -921,19 +921,19 @@ vec4_instruction::reswizzle(int dst_writemask, int swizzle) /* Destination write mask doesn't correspond to source swizzle for the dot * product and pack_bytes instructions. */ - if (opcode != BRW_OPCODE_DP4 && opcode != BRW_OPCODE_DPH && - opcode != BRW_OPCODE_DP3 && opcode != BRW_OPCODE_DP2 && - opcode != VEC4_OPCODE_PACK_BYTES) { + if (opcode != ELK_OPCODE_DP4 && opcode != ELK_OPCODE_DPH && + opcode != ELK_OPCODE_DP3 && opcode != ELK_OPCODE_DP2 && + opcode != ELK_VEC4_OPCODE_PACK_BYTES) { for (int i = 0; i < 3; i++) { if (src[i].file == BAD_FILE) continue; if (src[i].file == IMM) { - assert(src[i].type != BRW_REGISTER_TYPE_V && - src[i].type != BRW_REGISTER_TYPE_UV); + assert(src[i].type != ELK_REGISTER_TYPE_V && + src[i].type != ELK_REGISTER_TYPE_UV); /* Vector immediate types need to be reswizzled. */ - if (src[i].type == BRW_REGISTER_TYPE_VF) { + if (src[i].type == ELK_REGISTER_TYPE_VF) { const unsigned imm[] = { (src[i].ud >> 0) & 0x0ff, (src[i].ud >> 8) & 0x0ff, @@ -941,16 +941,16 @@ vec4_instruction::reswizzle(int dst_writemask, int swizzle) (src[i].ud >> 24) & 0x0ff, }; - src[i] = brw_imm_vf4(imm[BRW_GET_SWZ(swizzle, 0)], - imm[BRW_GET_SWZ(swizzle, 1)], - imm[BRW_GET_SWZ(swizzle, 2)], - imm[BRW_GET_SWZ(swizzle, 3)]); + src[i] = elk_imm_vf4(imm[ELK_GET_SWZ(swizzle, 0)], + imm[ELK_GET_SWZ(swizzle, 1)], + imm[ELK_GET_SWZ(swizzle, 2)], + imm[ELK_GET_SWZ(swizzle, 3)]); } continue; } - src[i].swizzle = brw_compose_swizzle(swizzle, src[i].swizzle); + src[i].swizzle = elk_compose_swizzle(swizzle, src[i].swizzle); } } @@ -958,7 +958,7 @@ vec4_instruction::reswizzle(int dst_writemask, int swizzle) * written components. */ dst.writemask = dst_writemask & - brw_apply_swizzle_to_mask(swizzle, dst.writemask); + elk_apply_swizzle_to_mask(swizzle, dst.writemask); } /* @@ -977,7 +977,7 @@ vec4_visitor::opt_register_coalesce() int ip = next_ip; next_ip++; - if (inst->opcode != BRW_OPCODE_MOV || + if (inst->opcode != ELK_OPCODE_MOV || (inst->dst.file != VGRF && inst->dst.file != MRF) || inst->predicate || inst->src[0].file != VGRF || @@ -995,7 +995,7 @@ vec4_visitor::opt_register_coalesce() if ((inst->dst.writemask & (1 << c)) == 0) continue; - if (BRW_GET_SWZ(inst->src[0].swizzle, c) != c) { + if (ELK_GET_SWZ(inst->src[0].swizzle, c) != c) { is_nop_mov = false; break; } @@ -1022,7 +1022,7 @@ vec4_visitor::opt_register_coalesce() * channels we've seen initialized. */ const unsigned chans_needed = - brw_apply_inv_swizzle_to_mask(inst->src[0].swizzle, + elk_apply_inv_swizzle_to_mask(inst->src[0].swizzle, inst->dst.writemask); unsigned chans_remaining = chans_needed; @@ -1053,13 +1053,13 @@ vec4_visitor::opt_register_coalesce() } } - /* VS_OPCODE_UNPACK_FLAGS_SIMD4X2 generates a bunch of mov(1) + /* ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2 generates a bunch of mov(1) * instructions, and this optimization pass is not capable of * handling that. Bail on these instructions and hope that some * later optimization pass can do the right thing after they are * expanded. */ - if (scan_inst->opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2) + if (scan_inst->opcode == ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2) break; /* This doesn't handle saturation on the instruction we @@ -1069,7 +1069,7 @@ vec4_visitor::opt_register_coalesce() */ if (inst->saturate && inst->dst.type != scan_inst->dst.type && - !(scan_inst->opcode == BRW_OPCODE_MOV && + !(scan_inst->opcode == ELK_OPCODE_MOV && scan_inst->dst.type == scan_inst->src[0].type)) break; @@ -1208,7 +1208,7 @@ vec4_visitor::eliminate_find_live_channel() bool progress = false; unsigned depth = 0; - if (!brw_stage_has_packed_dispatch(devinfo, stage, 0, stage_prog_data)) { + if (!elk_stage_has_packed_dispatch(devinfo, stage, 0, stage_prog_data)) { /* The optimization below assumes that channel zero is live on thread * dispatch, which may not be the case if the fixed function dispatches * threads sparsely. @@ -1218,20 +1218,20 @@ vec4_visitor::eliminate_find_live_channel() foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { switch (inst->opcode) { - case BRW_OPCODE_IF: - case BRW_OPCODE_DO: + case ELK_OPCODE_IF: + case ELK_OPCODE_DO: depth++; break; - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_WHILE: + case ELK_OPCODE_ENDIF: + case ELK_OPCODE_WHILE: depth--; break; - case SHADER_OPCODE_FIND_LIVE_CHANNEL: + case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL: if (depth == 0) { - inst->opcode = BRW_OPCODE_MOV; - inst->src[0] = brw_imm_d(0); + inst->opcode = ELK_OPCODE_MOV; + inst->src[0] = elk_imm_d(0); inst->force_writemask_all = true; progress = true; } @@ -1323,7 +1323,7 @@ vec4_visitor::split_virtual_grfs() } void -vec4_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE *file) const +vec4_visitor::dump_instruction_to_file(const elk_backend_instruction *be_inst, FILE *file) const { const vec4_instruction *inst = (const vec4_instruction *)be_inst; @@ -1332,20 +1332,20 @@ vec4_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE inst->predicate_inverse ? '-' : '+', inst->flag_subreg / 2, inst->flag_subreg % 2, - pred_ctrl_align16[inst->predicate]); + elk_pred_ctrl_align16[inst->predicate]); } - fprintf(file, "%s(%d)", brw_instruction_name(&compiler->isa, inst->opcode), + fprintf(file, "%s(%d)", elk_instruction_name(&compiler->isa, inst->opcode), inst->exec_size); if (inst->saturate) fprintf(file, ".sat"); if (inst->conditional_mod) { - fprintf(file, "%s", conditional_modifier[inst->conditional_mod]); + fprintf(file, "%s", elk_conditional_modifier[inst->conditional_mod]); if (!inst->predicate && - (devinfo->ver < 5 || (inst->opcode != BRW_OPCODE_SEL && - inst->opcode != BRW_OPCODE_CSEL && - inst->opcode != BRW_OPCODE_IF && - inst->opcode != BRW_OPCODE_WHILE))) { + (devinfo->ver < 5 || (inst->opcode != ELK_OPCODE_SEL && + inst->opcode != ELK_OPCODE_CSEL && + inst->opcode != ELK_OPCODE_IF && + inst->opcode != ELK_OPCODE_WHILE))) { fprintf(file, ".f%d.%d", inst->flag_subreg / 2, inst->flag_subreg % 2); } } @@ -1363,16 +1363,16 @@ vec4_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE break; case ARF: switch (inst->dst.nr) { - case BRW_ARF_NULL: + case ELK_ARF_NULL: fprintf(file, "null"); break; - case BRW_ARF_ADDRESS: + case ELK_ARF_ADDRESS: fprintf(file, "a0.%d", inst->dst.subnr); break; - case BRW_ARF_ACCUMULATOR: + case ELK_ARF_ACCUMULATOR: fprintf(file, "acc%d", inst->dst.subnr); break; - case BRW_ARF_FLAG: + case ELK_ARF_FLAG: fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr); break; default: @@ -1406,7 +1406,7 @@ vec4_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE if (inst->dst.writemask & 8) fprintf(file, "w"); } - fprintf(file, ":%s", brw_reg_type_to_letters(inst->dst.type)); + fprintf(file, ":%s", elk_reg_type_to_letters(inst->dst.type)); if (inst->src[0].file != BAD_FILE) fprintf(file, ", "); @@ -1431,24 +1431,24 @@ vec4_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE break; case IMM: switch (inst->src[i].type) { - case BRW_REGISTER_TYPE_F: + case ELK_REGISTER_TYPE_F: fprintf(file, "%fF", inst->src[i].f); break; - case BRW_REGISTER_TYPE_DF: + case ELK_REGISTER_TYPE_DF: fprintf(file, "%fDF", inst->src[i].df); break; - case BRW_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_D: fprintf(file, "%dD", inst->src[i].d); break; - case BRW_REGISTER_TYPE_UD: + case ELK_REGISTER_TYPE_UD: fprintf(file, "%uU", inst->src[i].ud); break; - case BRW_REGISTER_TYPE_VF: + case ELK_REGISTER_TYPE_VF: fprintf(file, "[%-gF, %-gF, %-gF, %-gF]", - brw_vf_to_float((inst->src[i].ud >> 0) & 0xff), - brw_vf_to_float((inst->src[i].ud >> 8) & 0xff), - brw_vf_to_float((inst->src[i].ud >> 16) & 0xff), - brw_vf_to_float((inst->src[i].ud >> 24) & 0xff)); + elk_vf_to_float((inst->src[i].ud >> 0) & 0xff), + elk_vf_to_float((inst->src[i].ud >> 8) & 0xff), + elk_vf_to_float((inst->src[i].ud >> 16) & 0xff), + elk_vf_to_float((inst->src[i].ud >> 24) & 0xff)); break; default: fprintf(file, "???"); @@ -1457,16 +1457,16 @@ vec4_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE break; case ARF: switch (inst->src[i].nr) { - case BRW_ARF_NULL: + case ELK_ARF_NULL: fprintf(file, "null"); break; - case BRW_ARF_ADDRESS: + case ELK_ARF_ADDRESS: fprintf(file, "a0.%d", inst->src[i].subnr); break; - case BRW_ARF_ACCUMULATOR: + case ELK_ARF_ACCUMULATOR: fprintf(file, "acc%d", inst->src[i].subnr); break; - case BRW_ARF_FLAG: + case ELK_ARF_FLAG: fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr); break; default: @@ -1493,7 +1493,7 @@ vec4_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE static const char *chans[4] = {"x", "y", "z", "w"}; fprintf(file, "."); for (int c = 0; c < 4; c++) { - fprintf(file, "%s", chans[BRW_GET_SWZ(inst->src[i].swizzle, c)]); + fprintf(file, "%s", chans[ELK_GET_SWZ(inst->src[i].swizzle, c)]); } } @@ -1501,7 +1501,7 @@ vec4_visitor::dump_instruction_to_file(const backend_instruction *be_inst, FILE fprintf(file, "|"); if (inst->src[i].file != IMM) { - fprintf(file, ":%s", brw_reg_type_to_letters(inst->src[i].type)); + fprintf(file, ":%s", elk_reg_type_to_letters(inst->src[i].type)); } if (i < 2 && inst->src[i + 1].file != BAD_FILE) @@ -1528,7 +1528,7 @@ vec4_vs_visitor::setup_attributes(int payload_reg) int grf = payload_reg + inst->src[i].nr + inst->src[i].offset / REG_SIZE; - struct brw_reg reg = brw_vec8_grf(grf, 0); + struct elk_reg reg = elk_vec8_grf(grf, 0); reg.swizzle = inst->src[i].swizzle; reg.type = inst->src[i].type; reg.abs = inst->src[i].abs; @@ -1548,7 +1548,7 @@ vec4_visitor::setup_push_ranges() * which is the limit on gfx6. * * If changing this value, note the limitation about total_regs in - * brw_curbe.c. + * elk_curbe.c. */ const unsigned max_push_length = 32; @@ -1557,7 +1557,7 @@ vec4_visitor::setup_push_ranges() /* Shrink UBO push ranges so it all fits in max_push_length */ for (unsigned i = 0; i < 4; i++) { - struct brw_ubo_range *range = &prog_data->base.ubo_ranges[i]; + struct elk_ubo_range *range = &prog_data->base.ubo_ranges[i]; if (push_length + range->length > max_push_length) range->length = max_push_length - push_length; @@ -1585,10 +1585,10 @@ vec4_visitor::setup_uniforms(int reg) * matter what, or the GPU would hang. */ if (devinfo->ver < 6 && push_length == 0) { - brw_stage_prog_data_add_params(stage_prog_data, 4); + elk_stage_prog_data_add_params(stage_prog_data, 4); for (unsigned int i = 0; i < 4; i++) { unsigned int slot = this->uniforms * 4 + i; - stage_prog_data->param[slot] = BRW_PARAM_BUILTIN_ZERO; + stage_prog_data->param[slot] = ELK_PARAM_BUILTIN_ZERO; } push_length = 1; } @@ -1627,14 +1627,14 @@ vec4_visitor::lower_minmax() foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { const vec4_builder ibld(this, block, inst); - if (inst->opcode == BRW_OPCODE_SEL && - inst->predicate == BRW_PREDICATE_NONE) { + if (inst->opcode == ELK_OPCODE_SEL && + inst->predicate == ELK_PREDICATE_NONE) { /* If src1 is an immediate value that is not NaN, then it can't be * NaN. In that case, emit CMP because it is much better for cmod * propagation. Likewise if src1 is not float. Gfx4 and Gfx5 don't * support HF or DF, so it is not necessary to check for those. */ - if (inst->src[1].type != BRW_REGISTER_TYPE_F || + if (inst->src[1].type != ELK_REGISTER_TYPE_F || (inst->src[1].file == IMM && !isnan(inst->src[1].f))) { ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1], inst->conditional_mod); @@ -1642,8 +1642,8 @@ vec4_visitor::lower_minmax() ibld.CMPN(ibld.null_reg_d(), inst->src[0], inst->src[1], inst->conditional_mod); } - inst->predicate = BRW_PREDICATE_NORMAL; - inst->conditional_mod = BRW_CONDITIONAL_NONE; + inst->predicate = ELK_PREDICATE_NORMAL; + inst->conditional_mod = ELK_CONDITIONAL_NONE; progress = true; } @@ -1660,16 +1660,16 @@ vec4_visitor::get_timestamp() { assert(devinfo->ver == 7); - src_reg ts = src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, - BRW_ARF_TIMESTAMP, + src_reg ts = src_reg(elk_reg(ELK_ARCHITECTURE_REGISTER_FILE, + ELK_ARF_TIMESTAMP, 0, 0, 0, - BRW_REGISTER_TYPE_UD, - BRW_VERTICAL_STRIDE_0, - BRW_WIDTH_4, - BRW_HORIZONTAL_STRIDE_4, - BRW_SWIZZLE_XYZW, + ELK_REGISTER_TYPE_UD, + ELK_VERTICAL_STRIDE_0, + ELK_WIDTH_4, + ELK_HORIZONTAL_STRIDE_4, + ELK_SWIZZLE_XYZW, WRITEMASK_XYZW)); dst_reg dst = dst_reg(this, glsl_uvec4_type()); @@ -1687,14 +1687,14 @@ static bool is_align1_df(vec4_instruction *inst) { switch (inst->opcode) { - case VEC4_OPCODE_DOUBLE_TO_F32: - case VEC4_OPCODE_DOUBLE_TO_D32: - case VEC4_OPCODE_DOUBLE_TO_U32: - case VEC4_OPCODE_TO_DOUBLE: - case VEC4_OPCODE_PICK_LOW_32BIT: - case VEC4_OPCODE_PICK_HIGH_32BIT: - case VEC4_OPCODE_SET_LOW_32BIT: - case VEC4_OPCODE_SET_HIGH_32BIT: + case ELK_VEC4_OPCODE_DOUBLE_TO_F32: + case ELK_VEC4_OPCODE_DOUBLE_TO_D32: + case ELK_VEC4_OPCODE_DOUBLE_TO_U32: + case ELK_VEC4_OPCODE_TO_DOUBLE: + case ELK_VEC4_OPCODE_PICK_LOW_32BIT: + case ELK_VEC4_OPCODE_PICK_HIGH_32BIT: + case ELK_VEC4_OPCODE_SET_LOW_32BIT: + case ELK_VEC4_OPCODE_SET_HIGH_32BIT: return true; default: return false; @@ -1711,7 +1711,7 @@ vec4_visitor::fixup_3src_null_dest() bool progress = false; foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) { - if (inst->is_3src(compiler) && inst->dst.is_null()) { + if (inst->elk_is_3src(compiler) && inst->dst.is_null()) { const unsigned size_written = type_sz(inst->dst.type); const unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE); @@ -1732,10 +1732,10 @@ vec4_visitor::convert_to_hw_regs() foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (int i = 0; i < 3; i++) { class src_reg &src = inst->src[i]; - struct brw_reg reg; + struct elk_reg reg; switch (src.file) { case VGRF: { - reg = byte_offset(brw_vecn_grf(4, src.nr, 0), src.offset); + reg = byte_offset(elk_vecn_grf(4, src.nr, 0), src.offset); reg.type = src.type; reg.abs = src.abs; reg.negate = src.negate; @@ -1744,13 +1744,13 @@ vec4_visitor::convert_to_hw_regs() case UNIFORM: { if (src.nr >= UBO_START) { - reg = byte_offset(brw_vec4_grf( + reg = byte_offset(elk_vec4_grf( prog_data->base.dispatch_grf_start_reg + ubo_push_start[src.nr - UBO_START] + src.offset / 32, 0), src.offset % 32); } else { - reg = byte_offset(brw_vec4_grf( + reg = byte_offset(elk_vec4_grf( prog_data->base.dispatch_grf_start_reg + src.nr / 2, src.nr % 2 * 4), src.offset); @@ -1767,7 +1767,7 @@ vec4_visitor::convert_to_hw_regs() case FIXED_GRF: if (type_sz(src.type) == 8) { - reg = src.as_brw_reg(); + reg = src.as_elk_reg(); break; } FALLTHROUGH; @@ -1777,7 +1777,7 @@ vec4_visitor::convert_to_hw_regs() case BAD_FILE: /* Probably unused. */ - reg = brw_null_reg(); + reg = elk_null_reg(); reg = retype(reg, src.type); break; @@ -1804,45 +1804,45 @@ vec4_visitor::convert_to_hw_regs() src.vstride = src.width + src.hstride; } - if (inst->is_3src(compiler)) { + if (inst->elk_is_3src(compiler)) { /* 3-src instructions with scalar sources support arbitrary subnr, * but don't actually use swizzles. Convert swizzle into subnr. * Skip this for double-precision instructions: RepCtrl=1 is not * allowed for them and needs special handling. */ for (int i = 0; i < 3; i++) { - if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0 && + if (inst->src[i].vstride == ELK_VERTICAL_STRIDE_0 && type_sz(inst->src[i].type) < 8) { - assert(brw_is_single_value_swizzle(inst->src[i].swizzle)); - inst->src[i].subnr += 4 * BRW_GET_SWZ(inst->src[i].swizzle, 0); + assert(elk_is_single_value_swizzle(inst->src[i].swizzle)); + inst->src[i].subnr += 4 * ELK_GET_SWZ(inst->src[i].swizzle, 0); } } } dst_reg &dst = inst->dst; - struct brw_reg reg; + struct elk_reg reg; switch (inst->dst.file) { case VGRF: - reg = byte_offset(brw_vec8_grf(dst.nr, 0), dst.offset); + reg = byte_offset(elk_vec8_grf(dst.nr, 0), dst.offset); reg.type = dst.type; reg.writemask = dst.writemask; break; case MRF: - reg = byte_offset(brw_message_reg(dst.nr), dst.offset); - assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver)); + reg = byte_offset(elk_message_reg(dst.nr), dst.offset); + assert((reg.nr & ~ELK_MRF_COMPR4) < ELK_MAX_MRF(devinfo->ver)); reg.type = dst.type; reg.writemask = dst.writemask; break; case ARF: case FIXED_GRF: - reg = dst.as_brw_reg(); + reg = dst.as_elk_reg(); break; case BAD_FILE: - reg = brw_null_reg(); + reg = elk_null_reg(); reg = retype(reg, dst.type); break; @@ -1883,8 +1883,8 @@ get_lowered_simd_width(const struct intel_device_info *devinfo, { /* Do not split some instructions that require special handling */ switch (inst->opcode) { - case SHADER_OPCODE_GFX4_SCRATCH_READ: - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: return inst->exec_size; default: break; @@ -1900,7 +1900,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo, /* Align16 8-wide double-precision SEL does not work well. Verified * empirically. */ - if (inst->opcode == BRW_OPCODE_SEL && type_sz(inst->dst.type) == 8) + if (inst->opcode == ELK_OPCODE_SEL && type_sz(inst->dst.type) == 8) lowered_width = MIN2(lowered_width, 4); /* HSW PRM, 3D Media GPGPU Engine, Region Alignment Rules for Direct @@ -2064,21 +2064,21 @@ vec4_visitor::lower_simd_width() return progress; } -static brw_predicate -scalarize_predicate(brw_predicate predicate, unsigned writemask) +static elk_predicate +scalarize_predicate(elk_predicate predicate, unsigned writemask) { - if (predicate != BRW_PREDICATE_NORMAL) + if (predicate != ELK_PREDICATE_NORMAL) return predicate; switch (writemask) { case WRITEMASK_X: - return BRW_PREDICATE_ALIGN16_REPLICATE_X; + return ELK_PREDICATE_ALIGN16_REPLICATE_X; case WRITEMASK_Y: - return BRW_PREDICATE_ALIGN16_REPLICATE_Y; + return ELK_PREDICATE_ALIGN16_REPLICATE_Y; case WRITEMASK_Z: - return BRW_PREDICATE_ALIGN16_REPLICATE_Z; + return ELK_PREDICATE_ALIGN16_REPLICATE_Z; case WRITEMASK_W: - return BRW_PREDICATE_ALIGN16_REPLICATE_W; + return ELK_PREDICATE_ALIGN16_REPLICATE_W; default: unreachable("invalid writemask"); } @@ -2091,14 +2091,14 @@ static bool is_gfx7_supported_64bit_swizzle(vec4_instruction *inst, unsigned arg) { switch (inst->src[arg].swizzle) { - case BRW_SWIZZLE_XXXX: - case BRW_SWIZZLE_YYYY: - case BRW_SWIZZLE_ZZZZ: - case BRW_SWIZZLE_WWWW: - case BRW_SWIZZLE_XYXY: - case BRW_SWIZZLE_YXYX: - case BRW_SWIZZLE_ZWZW: - case BRW_SWIZZLE_WZWZ: + case ELK_SWIZZLE_XXXX: + case ELK_SWIZZLE_YYYY: + case ELK_SWIZZLE_ZZZZ: + case ELK_SWIZZLE_WWWW: + case ELK_SWIZZLE_XYXY: + case ELK_SWIZZLE_YXYX: + case ELK_SWIZZLE_ZWZW: + case ELK_SWIZZLE_WZWZ: return true; default: return false; @@ -2132,14 +2132,14 @@ vec4_visitor::is_supported_64bit_region(vec4_instruction *inst, unsigned arg) if ((is_uniform(src) || (stage_uses_interleaved_attributes(stage, prog_data->dispatch_mode) && src.file == ATTR)) && - (brw_mask_for_swizzle(src.swizzle) & 12)) + (elk_mask_for_swizzle(src.swizzle) & 12)) return false; switch (src.swizzle) { - case BRW_SWIZZLE_XYZW: - case BRW_SWIZZLE_XXZZ: - case BRW_SWIZZLE_YYWW: - case BRW_SWIZZLE_YXWZ: + case ELK_SWIZZLE_XYZW: + case ELK_SWIZZLE_XXZZ: + case ELK_SWIZZLE_YYWW: + case ELK_SWIZZLE_YXWZ: return true; default: return devinfo->ver == 7 && is_gfx7_supported_64bit_swizzle(inst, arg); @@ -2197,13 +2197,13 @@ vec4_visitor::scalarize_df() vec4_instruction *scalar_inst = new(mem_ctx) vec4_instruction(*inst); for (unsigned i = 0; i < 3; i++) { - unsigned swz = BRW_GET_SWZ(inst->src[i].swizzle, chan); - scalar_inst->src[i].swizzle = BRW_SWIZZLE4(swz, swz, swz, swz); + unsigned swz = ELK_GET_SWZ(inst->src[i].swizzle, chan); + scalar_inst->src[i].swizzle = ELK_SWIZZLE4(swz, swz, swz, swz); } scalar_inst->dst.writemask = chan_mask; - if (inst->predicate != BRW_PREDICATE_NONE) { + if (inst->predicate != ELK_PREDICATE_NONE) { scalar_inst->predicate = scalarize_predicate(inst->predicate, chan_mask); } @@ -2227,7 +2227,7 @@ vec4_visitor::lower_64bit_mad_to_mul_add() bool progress = false; foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { - if (inst->opcode != BRW_OPCODE_MAD) + if (inst->opcode != ELK_OPCODE_MAD) continue; if (type_sz(inst->dst.type) != 8) @@ -2239,14 +2239,14 @@ vec4_visitor::lower_64bit_mad_to_mul_add() * from the original mad into the add and mul instructions */ vec4_instruction *mul = new(mem_ctx) vec4_instruction(*inst); - mul->opcode = BRW_OPCODE_MUL; + mul->opcode = ELK_OPCODE_MUL; mul->dst = mul_dst; mul->src[0] = inst->src[1]; mul->src[1] = inst->src[2]; mul->src[2].file = BAD_FILE; vec4_instruction *add = new(mem_ctx) vec4_instruction(*inst); - add->opcode = BRW_OPCODE_ADD; + add->opcode = ELK_OPCODE_ADD; add->src[0] = src_reg(mul_dst); add->src[1] = inst->src[0]; add->src[2].file = BAD_FILE; @@ -2277,12 +2277,12 @@ vec4_visitor::lower_64bit_mad_to_mul_add() * given Vec4 IR source. */ void -vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, +vec4_visitor::apply_logical_swizzle(struct elk_reg *hw_reg, vec4_instruction *inst, int arg) { src_reg reg = inst->src[arg]; - if (reg.file == BAD_FILE || reg.file == BRW_IMMEDIATE_VALUE) + if (reg.file == BAD_FILE || reg.file == ELK_IMMEDIATE_VALUE) return; /* If this is not a 64-bit operand or this is a scalar instruction we don't @@ -2294,13 +2294,13 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, } /* Take the 64-bit logical swizzle channel and translate it to 32-bit */ - assert(brw_is_single_value_swizzle(reg.swizzle) || + assert(elk_is_single_value_swizzle(reg.swizzle) || is_supported_64bit_region(inst, arg)); /* Apply the region <2, 2, 1> for GRF or <0, 2, 1> for uniforms, as align16 * HW can only do 32-bit swizzle channels. */ - hw_reg->width = BRW_WIDTH_2; + hw_reg->width = ELK_WIDTH_2; if (is_supported_64bit_region(inst, arg) && !is_gfx7_supported_64bit_swizzle(inst, arg)) { @@ -2308,9 +2308,9 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, * components, when expanded to 32-bit swizzles, match the semantics * of the original 64-bit swizzle with 2-wide row regioning. */ - unsigned swizzle0 = BRW_GET_SWZ(reg.swizzle, 0); - unsigned swizzle1 = BRW_GET_SWZ(reg.swizzle, 1); - hw_reg->swizzle = BRW_SWIZZLE4(swizzle0 * 2, swizzle0 * 2 + 1, + unsigned swizzle0 = ELK_GET_SWZ(reg.swizzle, 0); + unsigned swizzle1 = ELK_GET_SWZ(reg.swizzle, 1); + hw_reg->swizzle = ELK_SWIZZLE4(swizzle0 * 2, swizzle0 * 2 + 1, swizzle1 * 2, swizzle1 * 2 + 1); } else { /* If we got here then we have one of the following: @@ -2322,8 +2322,8 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, * swizzles. If the latter, they are never cross-dvec2 channels. For * these we always need to activate the gfx7 vstride=0 exploit. */ - unsigned swizzle0 = BRW_GET_SWZ(reg.swizzle, 0); - unsigned swizzle1 = BRW_GET_SWZ(reg.swizzle, 1); + unsigned swizzle0 = ELK_GET_SWZ(reg.swizzle, 0); + unsigned swizzle1 = ELK_GET_SWZ(reg.swizzle, 1); assert((swizzle0 < 2) == (swizzle1 < 2)); /* To gain access to Z/W components we need to select the second half @@ -2337,7 +2337,7 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, /* All gfx7-specific supported swizzles require the vstride=0 exploit */ if (devinfo->ver == 7 && is_gfx7_supported_64bit_swizzle(inst, arg)) - hw_reg->vstride = BRW_VERTICAL_STRIDE_0; + hw_reg->vstride = ELK_VERTICAL_STRIDE_0; /* Any 64-bit source with an offset at 16B is intended to address the * second half of a register and needs a vertical stride of 0 so we: @@ -2348,10 +2348,10 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, */ if (hw_reg->subnr % REG_SIZE == 16) { assert(devinfo->ver == 7); - hw_reg->vstride = BRW_VERTICAL_STRIDE_0; + hw_reg->vstride = ELK_VERTICAL_STRIDE_0; } - hw_reg->swizzle = BRW_SWIZZLE4(swizzle0 * 2, swizzle0 * 2 + 1, + hw_reg->swizzle = ELK_SWIZZLE4(swizzle0 * 2, swizzle0 * 2 + 1, swizzle1 * 2, swizzle1 * 2 + 1); } } @@ -2359,7 +2359,7 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, void vec4_visitor::invalidate_analysis(elk::analysis_dependency_class c) { - backend_shader::invalidate_analysis(c); + elk_backend_shader::invalidate_analysis(c); live_analysis.invalidate(c); } @@ -2373,12 +2373,12 @@ vec4_visitor::run() const unsigned mask_param = stage_prog_data->push_reg_mask_param; src_reg mask = src_reg(dst_reg(UNIFORM, mask_param / 4)); assert(mask_param % 2 == 0); /* Should be 64-bit-aligned */ - mask.swizzle = BRW_SWIZZLE4((mask_param + 0) % 4, + mask.swizzle = ELK_SWIZZLE4((mask_param + 0) % 4, (mask_param + 1) % 4, (mask_param + 0) % 4, (mask_param + 1) % 4); - emit(VEC4_OPCODE_ZERO_OOB_PUSH_REGS, + emit(ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS, dst_reg(VGRF, alloc.allocate(3)), mask); } @@ -2415,7 +2415,7 @@ vec4_visitor::run() _mesa_shader_stage_to_abbrev(stage), \ nir->info.name, iteration, pass_num); \ \ - backend_shader::dump_instructions(filename); \ + elk_backend_shader::dump_instructions(filename); \ } \ \ cfg->validate(_mesa_shader_stage_to_abbrev(stage)); \ @@ -2429,7 +2429,7 @@ vec4_visitor::run() snprintf(filename, 64, "%s-%s-00-00-start", _mesa_shader_stage_to_abbrev(stage), nir->info.name); - backend_shader::dump_instructions(filename); + elk_backend_shader::dump_instructions(filename); } bool progress; @@ -2440,10 +2440,10 @@ vec4_visitor::run() pass_num = 0; iteration++; - OPT(opt_predicated_break, this); + OPT(elk_opt_predicated_break, this); OPT(opt_reduce_swizzle); OPT(dead_code_eliminate); - OPT(dead_control_flow_eliminate, this); + OPT(elk_dead_control_flow_eliminate, this); OPT(opt_copy_propagation); OPT(opt_cmod_propagation); OPT(opt_cse); @@ -2511,7 +2511,7 @@ vec4_visitor::run() bool allocated_without_spills = reg_allocate(); if (!allocated_without_spills) { - brw_shader_perf_log(compiler, log_data, + elk_shader_perf_log(compiler, log_data, "%s shader triggered register spilling. " "Try reducing the number of live vec4 values " "to improve performance.\n", @@ -2537,7 +2537,7 @@ vec4_visitor::run() if (last_scratch > 0) { prog_data->base.total_scratch = - brw_get_scratch_size(last_scratch * REG_SIZE); + elk_get_scratch_size(last_scratch * REG_SIZE); } return !failed; @@ -2548,14 +2548,14 @@ vec4_visitor::run() extern "C" { const unsigned * -brw_compile_vs(const struct brw_compiler *compiler, - struct brw_compile_vs_params *params) +elk_compile_vs(const struct elk_compiler *compiler, + struct elk_compile_vs_params *params) { struct nir_shader *nir = params->base.nir; - const struct brw_vs_prog_key *key = params->key; - struct brw_vs_prog_data *prog_data = params->prog_data; + const struct elk_vs_prog_key *key = params->key; + struct elk_vs_prog_data *prog_data = params->prog_data; const bool debug_enabled = - brw_should_print_shader(nir, params->base.debug_flag ? + elk_should_print_shader(nir, params->base.debug_flag ? params->base.debug_flag : DEBUG_VS); prog_data->base.base.stage = MESA_SHADER_VERTEX; @@ -2563,16 +2563,16 @@ brw_compile_vs(const struct brw_compiler *compiler, prog_data->base.base.total_scratch = 0; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX]; - brw_nir_apply_key(nir, compiler, &key->base, 8); + elk_nir_apply_key(nir, compiler, &key->base, 8); const unsigned *assembly = NULL; prog_data->inputs_read = nir->info.inputs_read; prog_data->double_inputs_read = nir->info.vs.double_inputs; - brw_nir_lower_vs_inputs(nir, params->edgeflag_is_last, key->gl_attrib_wa_flags); - brw_nir_lower_vue_outputs(nir); - brw_postprocess_nir(nir, compiler, debug_enabled, + elk_nir_lower_vs_inputs(nir, params->edgeflag_is_last, key->gl_attrib_wa_flags); + elk_nir_lower_vue_outputs(nir); + elk_postprocess_nir(nir, compiler, debug_enabled, key->base.robust_flags); prog_data->base.clip_distance_mask = @@ -2645,14 +2645,14 @@ brw_compile_vs(const struct brw_compiler *compiler, if (unlikely(debug_enabled)) { fprintf(stderr, "VS Output "); - brw_print_vue_map(stderr, &prog_data->base.vue_map, MESA_SHADER_VERTEX); + elk_print_vue_map(stderr, &prog_data->base.vue_map, MESA_SHADER_VERTEX); } if (is_scalar) { const unsigned dispatch_width = compiler->devinfo->ver >= 20 ? 16 : 8; prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8; - fs_visitor v(compiler, ¶ms->base, &key->base, + elk_fs_visitor v(compiler, ¶ms->base, &key->base, &prog_data->base.base, nir, dispatch_width, params->base.stats != NULL, debug_enabled); if (!v.run_vs()) { @@ -2665,7 +2665,7 @@ brw_compile_vs(const struct brw_compiler *compiler, prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(compiler->devinfo); - fs_generator g(compiler, ¶ms->base, + elk_fs_generator g(compiler, ¶ms->base, &prog_data->base.base, v.runtime_check_aads_emit, MESA_SHADER_VERTEX); if (unlikely(debug_enabled)) { @@ -2694,7 +2694,7 @@ brw_compile_vs(const struct brw_compiler *compiler, return NULL; } - assembly = brw_vec4_generate_assembly(compiler, ¶ms->base, + assembly = elk_vec4_generate_assembly(compiler, ¶ms->base, nir, &prog_data->base, v.cfg, v.performance_analysis.require(), diff --git a/src/intel/compiler/elk/elk_vec4.h b/src/intel/compiler/elk/elk_vec4.h index 66389e4af3a..b0589dfe244 100644 --- a/src/intel/compiler/elk/elk_vec4.h +++ b/src/intel/compiler/elk/elk_vec4.h @@ -42,11 +42,11 @@ extern "C" { #endif const unsigned * -brw_vec4_generate_assembly(const struct brw_compiler *compiler, - const struct brw_compile_params *params, +elk_vec4_generate_assembly(const struct elk_compiler *compiler, + const struct elk_compile_params *params, const nir_shader *nir, - struct brw_vue_prog_data *prog_data, - const struct cfg_t *cfg, + struct elk_vue_prog_data *prog_data, + const struct elk_cfg_t *cfg, const elk::performance &perf, bool debug_enabled); @@ -60,39 +60,39 @@ namespace elk { * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and * fixed-function) into VS IR. */ -class vec4_visitor : public backend_shader +class vec4_visitor : public elk_backend_shader { public: - vec4_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const struct brw_sampler_prog_key_data *key, - struct brw_vue_prog_data *prog_data, + vec4_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const struct elk_sampler_prog_key_data *key, + struct elk_vue_prog_data *prog_data, const nir_shader *shader, bool no_spills, bool debug_enabled); dst_reg dst_null_f() { - return dst_reg(brw_null_reg()); + return dst_reg(elk_null_reg()); } dst_reg dst_null_df() { - return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF)); + return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_DF)); } dst_reg dst_null_d() { - return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_D)); } dst_reg dst_null_ud() { - return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); + return dst_reg(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD)); } - const struct brw_sampler_prog_key_data * const key_tex; - struct brw_vue_prog_data * const prog_data; + const struct elk_sampler_prog_key_data * const key_tex; + struct elk_vue_prog_data * const prog_data; char *fail_msg; bool failed; @@ -107,8 +107,8 @@ public: unsigned ubo_push_start[4]; unsigned push_length; unsigned int max_grf; - brw_analysis live_analysis; - brw_analysis performance_analysis; + elk_analysis live_analysis; + elk_analysis performance_analysis; /* Regs for vertex results. Generated at ir_variable visiting time * for the ir->location's used. @@ -138,7 +138,7 @@ public: bool dead_code_eliminate(); bool opt_cmod_propagation(); bool opt_copy_propagation(bool do_constant_prop = true); - bool opt_cse_local(bblock_t *block, const vec4_live_variables &live); + bool opt_cse_local(elk_bblock_t *block, const vec4_live_variables &live); bool opt_cse(); bool opt_algebraic(); bool opt_register_coalesce(); @@ -153,22 +153,22 @@ public: bool lower_simd_width(); bool scalarize_df(); bool lower_64bit_mad_to_mul_add(); - void apply_logical_swizzle(struct brw_reg *hw_reg, + void apply_logical_swizzle(struct elk_reg *hw_reg, vec4_instruction *inst, int arg); vec4_instruction *emit(vec4_instruction *inst); - vec4_instruction *emit(enum opcode opcode); - vec4_instruction *emit(enum opcode opcode, const dst_reg &dst); - vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, + vec4_instruction *emit(enum elk_opcode opcode); + vec4_instruction *emit(enum elk_opcode opcode, const dst_reg &dst); + vec4_instruction *emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0); - vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, + vec4_instruction *emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1); - vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, + vec4_instruction *emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2); - vec4_instruction *emit_before(bblock_t *block, + vec4_instruction *emit_before(elk_bblock_t *block, vec4_instruction *inst, vec4_instruction *new_inst); @@ -197,10 +197,10 @@ public: EMIT2(SHR) EMIT2(ASR) vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1, - enum brw_conditional_mod condition); + enum elk_conditional_mod condition); vec4_instruction *IF(src_reg src0, src_reg src1, - enum brw_conditional_mod condition); - vec4_instruction *IF(enum brw_predicate predicate); + enum elk_conditional_mod condition); + vec4_instruction *IF(enum elk_predicate predicate); EMIT1(SCRATCH_READ) EMIT2(SCRATCH_WRITE) EMIT3(LRP) @@ -221,7 +221,7 @@ public: #undef EMIT2 #undef EMIT3 - vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst, + vec4_instruction *emit_minmax(enum elk_conditional_mod conditionalmod, dst_reg dst, src_reg src0, src_reg src1); /** @@ -235,7 +235,7 @@ public: src_reg fix_3src_operand(const src_reg &src); - vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0, + vec4_instruction *emit_math(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1 = src_reg()); src_reg fix_math_operand(const src_reg &src); @@ -255,20 +255,20 @@ public: vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying, int comp); virtual void emit_urb_slot(dst_reg reg, int varying); - src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst, + src_reg get_scratch_offset(elk_bblock_t *block, vec4_instruction *inst, src_reg *reladdr, int reg_offset); - void emit_scratch_read(bblock_t *block, vec4_instruction *inst, + void emit_scratch_read(elk_bblock_t *block, vec4_instruction *inst, dst_reg dst, src_reg orig_src, int base_offset); - void emit_scratch_write(bblock_t *block, vec4_instruction *inst, + void emit_scratch_write(elk_bblock_t *block, vec4_instruction *inst, int base_offset); void emit_pull_constant_load_reg(dst_reg dst, src_reg surf_index, src_reg offset, - bblock_t *before_block, + elk_bblock_t *before_block, vec4_instruction *before_inst); - src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block, + src_reg emit_resolve_reladdr(int scratch_loc[], elk_bblock_t *block, vec4_instruction *inst, src_reg src); void resolve_ud_negate(src_reg *reg); @@ -279,9 +279,9 @@ public: src_reg get_timestamp(); - virtual void dump_instruction_to_file(const backend_instruction *inst, FILE *file) const; + virtual void dump_instruction_to_file(const elk_backend_instruction *inst, FILE *file) const; - bool optimize_predicate(nir_alu_instr *instr, enum brw_predicate *predicate); + bool optimize_predicate(nir_alu_instr *instr, enum elk_predicate *predicate); void emit_conversion_from_double(dst_reg dst, src_reg src); void emit_conversion_to_double(dst_reg dst, src_reg src); @@ -289,7 +289,7 @@ public: vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src, bool for_write, bool for_scratch = false, - bblock_t *block = NULL, + elk_bblock_t *block = NULL, vec4_instruction *ref = NULL); virtual void emit_nir_code(); @@ -309,10 +309,10 @@ public: virtual void nir_emit_undef(nir_undef_instr *instr); virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr); - dst_reg get_nir_def(const nir_def &def, enum brw_reg_type type); + dst_reg get_nir_def(const nir_def &def, enum elk_reg_type type); dst_reg get_nir_def(const nir_def &def, nir_alu_type type); dst_reg get_nir_def(const nir_def &def); - src_reg get_nir_src(const nir_src &src, enum brw_reg_type type, + src_reg get_nir_src(const nir_src &src, enum elk_reg_type type, unsigned num_components = 4); src_reg get_nir_src(const nir_src &src, nir_alu_type type, unsigned num_components = 4); diff --git a/src/intel/compiler/elk/elk_vec4_builder.h b/src/intel/compiler/elk/elk_vec4_builder.h index 3d4005b8815..0d6111f0222 100644 --- a/src/intel/compiler/elk/elk_vec4_builder.h +++ b/src/intel/compiler/elk/elk_vec4_builder.h @@ -51,7 +51,7 @@ namespace elk { /** * Construct a vec4_builder that inserts instructions into \p shader. */ - vec4_builder(backend_shader *shader, unsigned dispatch_width = 8) : + vec4_builder(elk_backend_shader *shader, unsigned dispatch_width = 8) : shader(shader), block(NULL), cursor(NULL), _dispatch_width(dispatch_width), _group(0), force_writemask_all(false), @@ -65,7 +65,7 @@ namespace elk { * execution controls and debug annotation are initialized from the * instruction passed as argument. */ - vec4_builder(backend_shader *shader, bblock_t *block, instruction *inst) : + vec4_builder(elk_backend_shader *shader, elk_bblock_t *block, instruction *inst) : shader(shader), block(block), cursor(inst), _dispatch_width(inst->exec_size), _group(inst->group), force_writemask_all(inst->force_writemask_all) @@ -80,7 +80,7 @@ namespace elk { * from this. */ vec4_builder - at(bblock_t *block, exec_node *cursor) const + at(elk_bblock_t *block, exec_node *cursor) const { vec4_builder bld = *this; bld.block = block; @@ -169,7 +169,7 @@ namespace elk { * components in this IR). */ dst_reg - vgrf(enum brw_reg_type type, unsigned n = 1) const + vgrf(enum elk_reg_type type, unsigned n = 1) const { assert(dispatch_width() <= 32); @@ -187,8 +187,8 @@ namespace elk { dst_reg null_reg_f() const { - return dst_reg(retype(brw_null_vec(dispatch_width()), - BRW_REGISTER_TYPE_F)); + return dst_reg(retype(elk_null_vec(dispatch_width()), + ELK_REGISTER_TYPE_F)); } /** @@ -197,8 +197,8 @@ namespace elk { dst_reg null_reg_d() const { - return dst_reg(retype(brw_null_vec(dispatch_width()), - BRW_REGISTER_TYPE_D)); + return dst_reg(retype(elk_null_vec(dispatch_width()), + ELK_REGISTER_TYPE_D)); } /** @@ -207,8 +207,8 @@ namespace elk { dst_reg null_reg_ud() const { - return dst_reg(retype(brw_null_vec(dispatch_width()), - BRW_REGISTER_TYPE_UD)); + return dst_reg(retype(elk_null_vec(dispatch_width()), + ELK_REGISTER_TYPE_UD)); } /** @@ -224,7 +224,7 @@ namespace elk { * Create and insert a nullary control instruction into the program. */ instruction * - emit(enum opcode opcode) const + emit(enum elk_opcode opcode) const { return emit(instruction(opcode)); } @@ -233,7 +233,7 @@ namespace elk { * Create and insert a nullary instruction into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst) const + emit(enum elk_opcode opcode, const dst_reg &dst) const { return emit(instruction(opcode, dst)); } @@ -242,16 +242,16 @@ namespace elk { * Create and insert a unary instruction into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const + emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0) const { switch (opcode) { - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: return fix_math_instruction( emit(instruction(opcode, dst, fix_math_operand(src0)))); @@ -265,13 +265,13 @@ namespace elk { * Create and insert a binary instruction into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, + emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1) const { switch (opcode) { - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: return fix_math_instruction( emit(instruction(opcode, dst, fix_math_operand(src0), @@ -286,14 +286,14 @@ namespace elk { * Create and insert a ternary instruction into the program. */ instruction * - emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, + emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) const { switch (opcode) { - case BRW_OPCODE_BFE: - case BRW_OPCODE_BFI2: - case BRW_OPCODE_MAD: - case BRW_OPCODE_LRP: + case ELK_OPCODE_BFE: + case ELK_OPCODE_BFI2: + case ELK_OPCODE_MAD: + case ELK_OPCODE_LRP: return emit(instruction(opcode, dst, fix_3src_operand(src0), fix_3src_operand(src1), @@ -333,9 +333,9 @@ namespace elk { */ instruction * emit_minmax(const dst_reg &dst, const src_reg &src0, - const src_reg &src1, brw_conditional_mod mod) const + const src_reg &src1, elk_conditional_mod mod) const { - assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L); + assert(mod == ELK_CONDITIONAL_GE || mod == ELK_CONDITIONAL_L); return set_condmod(mod, SEL(dst, fix_unsigned_negate(src0), fix_unsigned_negate(src1))); @@ -349,11 +349,11 @@ namespace elk { { const vec4_builder ubld = exec_all(); const dst_reg chan_index = - writemask(vgrf(BRW_REGISTER_TYPE_UD), WRITEMASK_X); + writemask(vgrf(ELK_REGISTER_TYPE_UD), WRITEMASK_X); const dst_reg dst = vgrf(src.type); - ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index); - ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, src_reg(chan_index)); + ubld.emit(ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index); + ubld.emit(ELK_SHADER_OPCODE_BROADCAST, dst, src, src_reg(chan_index)); return src_reg(dst); } @@ -366,21 +366,21 @@ namespace elk { instruction * \ op(const dst_reg &dst, const src_reg &src0) const \ { \ - return emit(BRW_OPCODE_##op, dst, src0); \ + return emit(ELK_OPCODE_##op, dst, src0); \ } #define ALU2(op) \ instruction * \ op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \ { \ - return emit(BRW_OPCODE_##op, dst, src0, src1); \ + return emit(ELK_OPCODE_##op, dst, src0, src1); \ } #define ALU2_ACC(op) \ instruction * \ op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \ { \ - instruction *inst = emit(BRW_OPCODE_##op, dst, src0, src1); \ + instruction *inst = emit(ELK_OPCODE_##op, dst, src0, src1); \ inst->writes_accumulator = true; \ return inst; \ } @@ -390,7 +390,7 @@ namespace elk { op(const dst_reg &dst, const src_reg &src0, const src_reg &src1, \ const src_reg &src2) const \ { \ - return emit(BRW_OPCODE_##op, dst, src0, src1, src2); \ + return emit(ELK_OPCODE_##op, dst, src0, src1, src2); \ } ALU2(ADD) @@ -449,7 +449,7 @@ namespace elk { */ instruction * CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, - brw_conditional_mod condition) const + elk_conditional_mod condition) const { /* Take the instruction: * @@ -464,7 +464,7 @@ namespace elk { * instruction. */ return set_condmod(condition, - emit(BRW_OPCODE_CMP, retype(dst, src0.type), + emit(ELK_OPCODE_CMP, retype(dst, src0.type), fix_unsigned_negate(src0), fix_unsigned_negate(src1))); } @@ -474,7 +474,7 @@ namespace elk { */ instruction * CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, - brw_conditional_mod condition) const + elk_conditional_mod condition) const { /* Take the instruction: * @@ -489,7 +489,7 @@ namespace elk { * instruction. */ return set_condmod(condition, - emit(BRW_OPCODE_CMPN, retype(dst, src0.type), + emit(ELK_OPCODE_CMPN, retype(dst, src0.type), fix_unsigned_negate(src0), fix_unsigned_negate(src1))); } @@ -498,9 +498,9 @@ namespace elk { * Gfx4 predicated IF. */ instruction * - IF(brw_predicate predicate) const + IF(elk_predicate predicate) const { - return set_predicate(predicate, emit(BRW_OPCODE_IF)); + return set_predicate(predicate, emit(ELK_OPCODE_IF)); } /** @@ -508,11 +508,11 @@ namespace elk { */ instruction * IF(const src_reg &src0, const src_reg &src1, - brw_conditional_mod condition) const + elk_conditional_mod condition) const { assert(shader->devinfo->ver == 6); return set_condmod(condition, - emit(BRW_OPCODE_IF, + emit(ELK_OPCODE_IF, null_reg_d(), fix_unsigned_negate(src0), fix_unsigned_negate(src1))); @@ -529,21 +529,21 @@ namespace elk { * we need to reorder the operands. */ assert(shader->devinfo->ver >= 6 && shader->devinfo->ver <= 9); - return emit(BRW_OPCODE_LRP, dst, a, y, x); + return emit(ELK_OPCODE_LRP, dst, a, y, x); } - backend_shader *shader; + elk_backend_shader *shader; protected: /** * Workaround for negation of UD registers. See comment in - * fs_generator::generate_code() for the details. + * elk_fs_generator::generate_code() for the details. */ src_reg fix_unsigned_negate(const src_reg &src) const { - if (src.type == BRW_REGISTER_TYPE_UD && src.negate) { - dst_reg temp = vgrf(BRW_REGISTER_TYPE_UD); + if (src.type == ELK_REGISTER_TYPE_UD && src.negate) { + dst_reg temp = vgrf(ELK_REGISTER_TYPE_UD); MOV(temp, src); return src_reg(temp); } else { @@ -572,11 +572,11 @@ namespace elk { if (src.file != UNIFORM && src.file != IMM) return src; - if (src.file == UNIFORM && brw_is_single_value_swizzle(src.swizzle)) + if (src.file == UNIFORM && elk_is_single_value_swizzle(src.swizzle)) return src; const dst_reg expanded = vgrf(src.type); - emit(VEC4_OPCODE_UNPACK_UNIFORM, expanded, src); + emit(ELK_VEC4_OPCODE_UNPACK_UNIFORM, expanded, src); return src_reg(expanded); } @@ -628,7 +628,7 @@ namespace elk { return inst; } - bblock_t *block; + elk_bblock_t *block; exec_node *cursor; unsigned _dispatch_width; diff --git a/src/intel/compiler/elk/elk_vec4_cmod_propagation.cpp b/src/intel/compiler/elk/elk_vec4_cmod_propagation.cpp index 30a8da19f4e..d628499cdda 100644 --- a/src/intel/compiler/elk/elk_vec4_cmod_propagation.cpp +++ b/src/intel/compiler/elk/elk_vec4_cmod_propagation.cpp @@ -24,8 +24,8 @@ /** @file elk_vec4_cmod_propagation.cpp * - * Really similar to brw_fs_cmod_propagation but adapted to vec4 needs. Check - * brw_fs_cmod_propagation for further details on the rationale behind this + * Really similar to elk_fs_cmod_propagation but adapted to vec4 needs. Check + * elk_fs_cmod_propagation for further details on the rationale behind this * optimization. */ @@ -42,12 +42,12 @@ writemasks_incompatible(const vec4_instruction *earlier, return (earlier->dst.writemask != WRITEMASK_X && earlier->dst.writemask != WRITEMASK_XYZW) || (earlier->dst.writemask == WRITEMASK_XYZW && - later->src[0].swizzle != BRW_SWIZZLE_XYZW) || + later->src[0].swizzle != ELK_SWIZZLE_XYZW) || (later->dst.writemask & ~earlier->dst.writemask) != 0; } static bool -opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) +opt_cmod_propagation_local(elk_bblock_t *block, vec4_visitor *v) { bool progress = false; UNUSED int ip = block->end_ip + 1; @@ -55,10 +55,10 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) { ip--; - if ((inst->opcode != BRW_OPCODE_AND && - inst->opcode != BRW_OPCODE_CMP && - inst->opcode != BRW_OPCODE_MOV) || - inst->predicate != BRW_PREDICATE_NONE || + if ((inst->opcode != ELK_OPCODE_AND && + inst->opcode != ELK_OPCODE_CMP && + inst->opcode != ELK_OPCODE_MOV) || + inst->predicate != ELK_PREDICATE_NONE || !inst->dst.is_null() || (inst->src[0].file != VGRF && inst->src[0].file != ATTR && inst->src[0].file != UNIFORM)) @@ -68,17 +68,17 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) * with a value other than zero. */ if (inst->src[0].abs && - (inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero())) + (inst->opcode != ELK_OPCODE_CMP || inst->src[1].is_zero())) continue; - if (inst->opcode == BRW_OPCODE_AND && + if (inst->opcode == ELK_OPCODE_AND && !(inst->src[1].is_one() && - inst->conditional_mod == BRW_CONDITIONAL_NZ && + inst->conditional_mod == ELK_CONDITIONAL_NZ && !inst->src[0].negate)) continue; - if (inst->opcode == BRW_OPCODE_MOV && - inst->conditional_mod != BRW_CONDITIONAL_NZ) + if (inst->opcode == ELK_OPCODE_MOV && + inst->conditional_mod != ELK_CONDITIONAL_NZ) continue; bool read_flag = false; @@ -87,10 +87,10 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) * with a second source that is not zero can only match with an ADD * instruction. */ - if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) { + if (inst->opcode == ELK_OPCODE_CMP && !inst->src[1].is_zero()) { bool negate; - if (scan_inst->opcode != BRW_OPCODE_ADD) + if (scan_inst->opcode != ELK_OPCODE_ADD) goto not_match; if (writemasks_incompatible(scan_inst, inst)) @@ -128,12 +128,12 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) */ /* Otherwise, try propagating the conditional. */ - const enum brw_conditional_mod cond = - negate ? brw_swap_cmod(inst->conditional_mod) + const enum elk_conditional_mod cond = + negate ? elk_swap_cmod(inst->conditional_mod) : inst->conditional_mod; if (scan_inst->can_do_cmod() && - ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) || + ((!read_flag && scan_inst->conditional_mod == ELK_CONDITIONAL_NONE) || scan_inst->conditional_mod == cond)) { scan_inst->conditional_mod = cond; inst->remove(block); @@ -144,7 +144,7 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) if (regions_overlap(inst->src[0], inst->size_read(0), scan_inst->dst, scan_inst->size_written)) { - if ((scan_inst->predicate && scan_inst->opcode != BRW_OPCODE_SEL) || + if ((scan_inst->predicate && scan_inst->opcode != ELK_OPCODE_SEL) || scan_inst->dst.offset != inst->src[0].offset || scan_inst->exec_size != inst->exec_size || scan_inst->group != inst->group) { @@ -154,19 +154,19 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) /* If scan_inst is a CMP that produces a single value and inst is * a CMP.NZ that consumes only that value, remove inst. */ - if (inst->conditional_mod == BRW_CONDITIONAL_NZ && - (inst->src[0].type == BRW_REGISTER_TYPE_D || - inst->src[0].type == BRW_REGISTER_TYPE_UD) && - (inst->opcode == BRW_OPCODE_CMP || - inst->opcode == BRW_OPCODE_MOV) && - scan_inst->opcode == BRW_OPCODE_CMP && - ((inst->src[0].swizzle == BRW_SWIZZLE_XXXX && + if (inst->conditional_mod == ELK_CONDITIONAL_NZ && + (inst->src[0].type == ELK_REGISTER_TYPE_D || + inst->src[0].type == ELK_REGISTER_TYPE_UD) && + (inst->opcode == ELK_OPCODE_CMP || + inst->opcode == ELK_OPCODE_MOV) && + scan_inst->opcode == ELK_OPCODE_CMP && + ((inst->src[0].swizzle == ELK_SWIZZLE_XXXX && scan_inst->dst.writemask == WRITEMASK_X) || - (inst->src[0].swizzle == BRW_SWIZZLE_YYYY && + (inst->src[0].swizzle == ELK_SWIZZLE_YYYY && scan_inst->dst.writemask == WRITEMASK_Y) || - (inst->src[0].swizzle == BRW_SWIZZLE_ZZZZ && + (inst->src[0].swizzle == ELK_SWIZZLE_ZZZZ && scan_inst->dst.writemask == WRITEMASK_Z) || - (inst->src[0].swizzle == BRW_SWIZZLE_WWWW && + (inst->src[0].swizzle == ELK_SWIZZLE_WWWW && scan_inst->dst.writemask == WRITEMASK_W))) { if (inst->dst.writemask != scan_inst->dst.writemask) { src_reg temp(v, glsl_vec4_type(), 1); @@ -185,7 +185,7 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) * The added MOV will most likely be removed later. In the * worst case, it should be cheaper to schedule. */ - temp.swizzle = brw_swizzle_for_mask(inst->dst.writemask); + temp.swizzle = elk_swizzle_for_mask(inst->dst.writemask); temp.type = scan_inst->src[0].type; vec4_instruction *mov = v->MOV(scan_inst->dst, temp); @@ -203,33 +203,33 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) unsigned src1_chan; switch (scan_inst->dst.writemask) { case WRITEMASK_X: - src0_chan = BRW_GET_SWZ(scan_inst->src[0].swizzle, 0); - src1_chan = BRW_GET_SWZ(scan_inst->src[1].swizzle, 0); + src0_chan = ELK_GET_SWZ(scan_inst->src[0].swizzle, 0); + src1_chan = ELK_GET_SWZ(scan_inst->src[1].swizzle, 0); break; case WRITEMASK_Y: - src0_chan = BRW_GET_SWZ(scan_inst->src[0].swizzle, 1); - src1_chan = BRW_GET_SWZ(scan_inst->src[1].swizzle, 1); + src0_chan = ELK_GET_SWZ(scan_inst->src[0].swizzle, 1); + src1_chan = ELK_GET_SWZ(scan_inst->src[1].swizzle, 1); break; case WRITEMASK_Z: - src0_chan = BRW_GET_SWZ(scan_inst->src[0].swizzle, 2); - src1_chan = BRW_GET_SWZ(scan_inst->src[1].swizzle, 2); + src0_chan = ELK_GET_SWZ(scan_inst->src[0].swizzle, 2); + src1_chan = ELK_GET_SWZ(scan_inst->src[1].swizzle, 2); break; case WRITEMASK_W: - src0_chan = BRW_GET_SWZ(scan_inst->src[0].swizzle, 3); - src1_chan = BRW_GET_SWZ(scan_inst->src[1].swizzle, 3); + src0_chan = ELK_GET_SWZ(scan_inst->src[0].swizzle, 3); + src1_chan = ELK_GET_SWZ(scan_inst->src[1].swizzle, 3); break; default: unreachable("Impossible writemask"); } - scan_inst->src[0].swizzle = BRW_SWIZZLE4(src0_chan, + scan_inst->src[0].swizzle = ELK_SWIZZLE4(src0_chan, src0_chan, src0_chan, src0_chan); /* There's no swizzle on immediate value sources. */ if (scan_inst->src[1].file != IMM) { - scan_inst->src[1].swizzle = BRW_SWIZZLE4(src1_chan, + scan_inst->src[1].swizzle = ELK_SWIZZLE4(src1_chan, src1_chan, src1_chan, src1_chan); @@ -250,10 +250,10 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) break; /* CMP's result is the same regardless of dest type. */ - if (inst->conditional_mod == BRW_CONDITIONAL_NZ && - scan_inst->opcode == BRW_OPCODE_CMP && - (inst->dst.type == BRW_REGISTER_TYPE_D || - inst->dst.type == BRW_REGISTER_TYPE_UD)) { + if (inst->conditional_mod == ELK_CONDITIONAL_NZ && + scan_inst->opcode == ELK_OPCODE_CMP && + (inst->dst.type == ELK_REGISTER_TYPE_D || + inst->dst.type == ELK_REGISTER_TYPE_UD)) { inst->remove(block); progress = true; break; @@ -262,13 +262,13 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) /* If the AND wasn't handled by the previous case, it isn't safe * to remove it. */ - if (inst->opcode == BRW_OPCODE_AND) + if (inst->opcode == ELK_OPCODE_AND) break; /* Comparisons operate differently for ints and floats */ if (scan_inst->dst.type != inst->dst.type && - (scan_inst->dst.type == BRW_REGISTER_TYPE_F || - inst->dst.type == BRW_REGISTER_TYPE_F)) + (scan_inst->dst.type == ELK_REGISTER_TYPE_F || + inst->dst.type == ELK_REGISTER_TYPE_F)) break; /* If the instruction generating inst's source also wrote the @@ -276,7 +276,7 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) * is redundant - the appropriate value is already in the flag * register. Delete inst. */ - if (inst->conditional_mod == BRW_CONDITIONAL_NZ && + if (inst->conditional_mod == ELK_CONDITIONAL_NZ && !inst->src[0].negate && scan_inst->writes_flag(v->devinfo)) { inst->remove(block); @@ -292,8 +292,8 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) * different results because they are evaluated based on different * inputs. */ - if (scan_inst->opcode == BRW_OPCODE_CMP || - scan_inst->opcode == BRW_OPCODE_CMPN) + if (scan_inst->opcode == ELK_OPCODE_CMP || + scan_inst->opcode == ELK_OPCODE_CMPN) break; /* From the Sky Lake PRM Vol. 7 "Assigning Conditional Mods": @@ -317,17 +317,17 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v) * * We just disallow cmod propagation on all integer multiplies. */ - if (!brw_reg_type_is_floating_point(scan_inst->dst.type) && - scan_inst->opcode == BRW_OPCODE_MUL) + if (!elk_reg_type_is_floating_point(scan_inst->dst.type) && + scan_inst->opcode == ELK_OPCODE_MUL) break; /* Otherwise, try propagating the conditional. */ - enum brw_conditional_mod cond = - inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod) + enum elk_conditional_mod cond = + inst->src[0].negate ? elk_swap_cmod(inst->conditional_mod) : inst->conditional_mod; if (scan_inst->can_do_cmod() && - ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) || + ((!read_flag && scan_inst->conditional_mod == ELK_CONDITIONAL_NONE) || scan_inst->conditional_mod == cond)) { scan_inst->conditional_mod = cond; inst->remove(block); diff --git a/src/intel/compiler/elk/elk_vec4_copy_propagation.cpp b/src/intel/compiler/elk/elk_vec4_copy_propagation.cpp index 61c873333b6..5b3b785f2a0 100644 --- a/src/intel/compiler/elk/elk_vec4_copy_propagation.cpp +++ b/src/intel/compiler/elk/elk_vec4_copy_propagation.cpp @@ -43,24 +43,24 @@ struct copy_entry { static bool is_direct_copy(vec4_instruction *inst) { - return (inst->opcode == BRW_OPCODE_MOV && + return (inst->opcode == ELK_OPCODE_MOV && !inst->predicate && inst->dst.file == VGRF && inst->dst.offset % REG_SIZE == 0 && !inst->dst.reladdr && !inst->src[0].reladdr && (inst->dst.type == inst->src[0].type || - (inst->dst.type == BRW_REGISTER_TYPE_F && - inst->src[0].type == BRW_REGISTER_TYPE_VF))); + (inst->dst.type == ELK_REGISTER_TYPE_F && + inst->src[0].type == ELK_REGISTER_TYPE_VF))); } static bool is_dominated_by_previous_instruction(vec4_instruction *inst) { - return (inst->opcode != BRW_OPCODE_DO && - inst->opcode != BRW_OPCODE_WHILE && - inst->opcode != BRW_OPCODE_ELSE && - inst->opcode != BRW_OPCODE_ENDIF); + return (inst->opcode != ELK_OPCODE_DO && + inst->opcode != ELK_OPCODE_WHILE && + inst->opcode != ELK_OPCODE_ELSE && + inst->opcode != ELK_OPCODE_ENDIF); } static bool @@ -75,7 +75,7 @@ is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch) return regions_overlap(*src, REG_SIZE, inst->dst, inst->size_written) && (inst->dst.offset != src->offset || - inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch))); + inst->dst.writemask & (1 << ELK_GET_SWZ(src->swizzle, ch))); } /** @@ -97,12 +97,12 @@ get_copy_value(const copy_entry &entry, unsigned readmask) if (src.file == IMM) { swz[i] = i; } else { - swz[i] = BRW_GET_SWZ(src.swizzle, i); + swz[i] = ELK_GET_SWZ(src.swizzle, i); /* Overwrite the original swizzle so the src_reg::equals call * below doesn't care about it, the correct swizzle will be * calculated once the swizzles of all components are known. */ - src.swizzle = BRW_SWIZZLE_XYZW; + src.swizzle = ELK_SWIZZLE_XYZW; } if (value.file == BAD_FILE) { @@ -117,8 +117,8 @@ get_copy_value(const copy_entry &entry, unsigned readmask) } return swizzle(value, - brw_compose_swizzle(brw_swizzle_for_mask(readmask), - BRW_SWIZZLE4(swz[0], swz[1], + elk_compose_swizzle(elk_swizzle_for_mask(readmask), + ELK_SWIZZLE4(swz[0], swz[1], swz[2], swz[3]))); } @@ -135,7 +135,7 @@ try_constant_propagate(vec4_instruction *inst, */ src_reg value = get_copy_value(*entry, - brw_apply_inv_swizzle_to_mask(inst->src[arg].swizzle, + elk_apply_inv_swizzle_to_mask(inst->src[arg].swizzle, WRITEMASK_XYZW)); if (value.file != IMM) @@ -148,68 +148,68 @@ try_constant_propagate(vec4_instruction *inst, if (type_sz(value.type) == 8 || type_sz(inst->src[arg].type) == 8) return false; - if (value.type == BRW_REGISTER_TYPE_VF) { + if (value.type == ELK_REGISTER_TYPE_VF) { /* The result of bit-casting the component values of a vector float * cannot in general be represented as an immediate. */ - if (inst->src[arg].type != BRW_REGISTER_TYPE_F) + if (inst->src[arg].type != ELK_REGISTER_TYPE_F) return false; } else { value.type = inst->src[arg].type; } if (inst->src[arg].abs) { - if (!brw_abs_immediate(value.type, &value.as_brw_reg())) + if (!elk_abs_immediate(value.type, &value.as_elk_reg())) return false; } if (inst->src[arg].negate) { - if (!brw_negate_immediate(value.type, &value.as_brw_reg())) + if (!elk_negate_immediate(value.type, &value.as_elk_reg())) return false; } value = swizzle(value, inst->src[arg].swizzle); switch (inst->opcode) { - case BRW_OPCODE_MOV: - case SHADER_OPCODE_BROADCAST: + case ELK_OPCODE_MOV: + case ELK_SHADER_OPCODE_BROADCAST: inst->src[arg] = value; return true; - case VEC4_OPCODE_UNTYPED_ATOMIC: + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: if (arg == 1) { inst->src[arg] = value; return true; } break; - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: break; - case BRW_OPCODE_DP2: - case BRW_OPCODE_DP3: - case BRW_OPCODE_DP4: - case BRW_OPCODE_DPH: - case BRW_OPCODE_BFI1: - case BRW_OPCODE_ASR: - case BRW_OPCODE_SHL: - case BRW_OPCODE_SHR: - case BRW_OPCODE_SUBB: + case ELK_OPCODE_DP2: + case ELK_OPCODE_DP3: + case ELK_OPCODE_DP4: + case ELK_OPCODE_DPH: + case ELK_OPCODE_BFI1: + case ELK_OPCODE_ASR: + case ELK_OPCODE_SHL: + case ELK_OPCODE_SHR: + case ELK_OPCODE_SUBB: if (arg == 1) { inst->src[arg] = value; return true; } break; - case BRW_OPCODE_MACH: - case BRW_OPCODE_MUL: - case SHADER_OPCODE_MULH: - case BRW_OPCODE_ADD: - case BRW_OPCODE_OR: - case BRW_OPCODE_AND: - case BRW_OPCODE_XOR: - case BRW_OPCODE_ADDC: + case ELK_OPCODE_MACH: + case ELK_OPCODE_MUL: + case ELK_SHADER_OPCODE_MULH: + case ELK_OPCODE_ADD: + case ELK_OPCODE_OR: + case ELK_OPCODE_AND: + case ELK_OPCODE_XOR: + case ELK_OPCODE_ADDC: if (arg == 1) { inst->src[arg] = value; return true; @@ -217,17 +217,17 @@ try_constant_propagate(vec4_instruction *inst, /* Fit this constant in by commuting the operands. Exception: we * can't do this for 32-bit integer MUL/MACH because it's asymmetric. */ - if ((inst->opcode == BRW_OPCODE_MUL || - inst->opcode == BRW_OPCODE_MACH) && - (inst->src[1].type == BRW_REGISTER_TYPE_D || - inst->src[1].type == BRW_REGISTER_TYPE_UD)) + if ((inst->opcode == ELK_OPCODE_MUL || + inst->opcode == ELK_OPCODE_MACH) && + (inst->src[1].type == ELK_REGISTER_TYPE_D || + inst->src[1].type == ELK_REGISTER_TYPE_UD)) break; inst->src[0] = inst->src[1]; inst->src[1] = value; return true; } break; - case GS_OPCODE_SET_WRITE_OFFSET: + case ELK_GS_OPCODE_SET_WRITE_OFFSET: /* This is just a multiply by a constant with special strides. * The generator will handle immediates in both arguments (generating * a single MOV of the product). So feel free to propagate in src0. @@ -235,15 +235,15 @@ try_constant_propagate(vec4_instruction *inst, inst->src[arg] = value; return true; - case BRW_OPCODE_CMP: + case ELK_OPCODE_CMP: if (arg == 1) { inst->src[arg] = value; return true; } else if (arg == 0 && inst->src[1].file != IMM) { - enum brw_conditional_mod new_cmod; + enum elk_conditional_mod new_cmod; - new_cmod = brw_swap_cmod(inst->conditional_mod); - if (new_cmod != BRW_CONDITIONAL_NONE) { + new_cmod = elk_swap_cmod(inst->conditional_mod); + if (new_cmod != ELK_CONDITIONAL_NONE) { /* Fit this constant in by swapping the operands and * flipping the test. */ @@ -255,7 +255,7 @@ try_constant_propagate(vec4_instruction *inst, } break; - case BRW_OPCODE_SEL: + case ELK_OPCODE_SEL: if (arg == 1) { inst->src[arg] = value; return true; @@ -266,7 +266,7 @@ try_constant_propagate(vec4_instruction *inst, /* If this was predicated, flipping operands means * we also need to flip the predicate. */ - if (inst->conditional_mod == BRW_CONDITIONAL_NONE) { + if (inst->conditional_mod == ELK_CONDITIONAL_NONE) { inst->predicate_inverse = !inst->predicate_inverse; } return true; @@ -284,14 +284,14 @@ static bool is_align1_opcode(unsigned opcode) { switch (opcode) { - case VEC4_OPCODE_DOUBLE_TO_F32: - case VEC4_OPCODE_DOUBLE_TO_D32: - case VEC4_OPCODE_DOUBLE_TO_U32: - case VEC4_OPCODE_TO_DOUBLE: - case VEC4_OPCODE_PICK_LOW_32BIT: - case VEC4_OPCODE_PICK_HIGH_32BIT: - case VEC4_OPCODE_SET_LOW_32BIT: - case VEC4_OPCODE_SET_HIGH_32BIT: + case ELK_VEC4_OPCODE_DOUBLE_TO_F32: + case ELK_VEC4_OPCODE_DOUBLE_TO_D32: + case ELK_VEC4_OPCODE_DOUBLE_TO_U32: + case ELK_VEC4_OPCODE_TO_DOUBLE: + case ELK_VEC4_OPCODE_PICK_LOW_32BIT: + case ELK_VEC4_OPCODE_PICK_HIGH_32BIT: + case ELK_VEC4_OPCODE_SET_LOW_32BIT: + case ELK_VEC4_OPCODE_SET_HIGH_32BIT: return true; default: return false; @@ -299,7 +299,7 @@ is_align1_opcode(unsigned opcode) } static bool -try_copy_propagate(const struct brw_compiler *compiler, +try_copy_propagate(const struct elk_compiler *compiler, vec4_instruction *inst, int arg, const copy_entry *entry, int attributes_per_reg) { @@ -310,7 +310,7 @@ try_copy_propagate(const struct brw_compiler *compiler, */ src_reg value = get_copy_value(*entry, - brw_apply_inv_swizzle_to_mask(inst->src[arg].swizzle, + elk_apply_inv_swizzle_to_mask(inst->src[arg].swizzle, WRITEMASK_XYZW)); /* Check that we can propagate that value */ @@ -355,7 +355,7 @@ try_copy_propagate(const struct brw_compiler *compiler, return false; /* Reject cases that would violate register regioning restrictions. */ - if ((value.file == UNIFORM || value.swizzle != BRW_SWIZZLE_XYZW) && + if ((value.file == UNIFORM || value.swizzle != ELK_SWIZZLE_XYZW) && ((devinfo->ver == 6 && inst->is_math()) || inst->is_send_from_grf() || inst->uses_indirect_addressing())) { @@ -368,24 +368,24 @@ try_copy_propagate(const struct brw_compiler *compiler, return false; if (has_source_modifiers && - (inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE || - inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT)) + (inst->opcode == ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE || + inst->opcode == ELK_VEC4_OPCODE_PICK_HIGH_32BIT)) return false; - unsigned composed_swizzle = brw_compose_swizzle(inst->src[arg].swizzle, + unsigned composed_swizzle = elk_compose_swizzle(inst->src[arg].swizzle, value.swizzle); /* Instructions that operate on vectors in ALIGN1 mode will ignore swizzles * so copy-propagation won't be safe if the composed swizzle is anything * other than the identity. */ - if (is_align1_opcode(inst->opcode) && composed_swizzle != BRW_SWIZZLE_XYZW) + if (is_align1_opcode(inst->opcode) && composed_swizzle != ELK_SWIZZLE_XYZW) return false; - if (inst->is_3src(compiler) && + if (inst->elk_is_3src(compiler) && (value.file == UNIFORM || (value.file == ATTR && attributes_per_reg != 1)) && - !brw_is_single_value_swizzle(composed_swizzle)) + !elk_is_single_value_swizzle(composed_swizzle)) return false; if (inst->is_send_from_grf()) @@ -396,7 +396,7 @@ try_copy_propagate(const struct brw_compiler *compiler, * instead. See also resolve_ud_negate(). */ if (value.negate && - value.type == BRW_REGISTER_TYPE_UD) + value.type == ELK_REGISTER_TYPE_UD) return false; /* Don't report progress if this is a noop. */ @@ -404,7 +404,7 @@ try_copy_propagate(const struct brw_compiler *compiler, return false; const unsigned dst_saturate_mask = inst->dst.writemask & - brw_apply_swizzle_to_mask(inst->src[arg].swizzle, entry->saturatemask); + elk_apply_swizzle_to_mask(inst->src[arg].swizzle, entry->saturatemask); if (dst_saturate_mask) { /* We either saturate all or nothing. */ @@ -415,11 +415,11 @@ try_copy_propagate(const struct brw_compiler *compiler, * and 1.0, otherwise skip copy propagate altogether. */ switch(inst->opcode) { - case BRW_OPCODE_SEL: + case ELK_OPCODE_SEL: if (arg != 0 || - inst->src[0].type != BRW_REGISTER_TYPE_F || + inst->src[0].type != ELK_REGISTER_TYPE_F || inst->src[1].file != IMM || - inst->src[1].type != BRW_REGISTER_TYPE_F || + inst->src[1].type != ELK_REGISTER_TYPE_F || inst->src[1].f < 0.0 || inst->src[1].f > 1.0) { return false; diff --git a/src/intel/compiler/elk/elk_vec4_cse.cpp b/src/intel/compiler/elk/elk_vec4_cse.cpp index 47ea7caadb8..994afc2c1fa 100644 --- a/src/intel/compiler/elk/elk_vec4_cse.cpp +++ b/src/intel/compiler/elk/elk_vec4_cse.cpp @@ -49,45 +49,45 @@ static bool is_expression(const vec4_instruction *const inst) { switch (inst->opcode) { - case BRW_OPCODE_MOV: - case BRW_OPCODE_SEL: - case BRW_OPCODE_NOT: - case BRW_OPCODE_AND: - case BRW_OPCODE_OR: - case BRW_OPCODE_XOR: - case BRW_OPCODE_SHR: - case BRW_OPCODE_SHL: - case BRW_OPCODE_ASR: - case BRW_OPCODE_CMP: - case BRW_OPCODE_CMPN: - case BRW_OPCODE_ADD: - case BRW_OPCODE_MUL: - case SHADER_OPCODE_MULH: - case BRW_OPCODE_FRC: - case BRW_OPCODE_RNDU: - case BRW_OPCODE_RNDD: - case BRW_OPCODE_RNDE: - case BRW_OPCODE_RNDZ: - case BRW_OPCODE_LINE: - case BRW_OPCODE_PLN: - case BRW_OPCODE_MAD: - case BRW_OPCODE_LRP: - case VEC4_OPCODE_UNPACK_UNIFORM: - case SHADER_OPCODE_FIND_LIVE_CHANNEL: - case SHADER_OPCODE_BROADCAST: - case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: - case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: + case ELK_OPCODE_MOV: + case ELK_OPCODE_SEL: + case ELK_OPCODE_NOT: + case ELK_OPCODE_AND: + case ELK_OPCODE_OR: + case ELK_OPCODE_XOR: + case ELK_OPCODE_SHR: + case ELK_OPCODE_SHL: + case ELK_OPCODE_ASR: + case ELK_OPCODE_CMP: + case ELK_OPCODE_CMPN: + case ELK_OPCODE_ADD: + case ELK_OPCODE_MUL: + case ELK_SHADER_OPCODE_MULH: + case ELK_OPCODE_FRC: + case ELK_OPCODE_RNDU: + case ELK_OPCODE_RNDD: + case ELK_OPCODE_RNDE: + case ELK_OPCODE_RNDZ: + case ELK_OPCODE_LINE: + case ELK_OPCODE_PLN: + case ELK_OPCODE_MAD: + case ELK_OPCODE_LRP: + case ELK_VEC4_OPCODE_UNPACK_UNIFORM: + case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL: + case ELK_SHADER_OPCODE_BROADCAST: + case ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: + case ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: return true; - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: return inst->mlen == 0; default: return false; @@ -100,13 +100,13 @@ operands_match(const vec4_instruction *a, const vec4_instruction *b) const src_reg *xs = a->src; const src_reg *ys = b->src; - if (a->opcode == BRW_OPCODE_MAD) { + if (a->opcode == ELK_OPCODE_MAD) { return xs[0].equals(ys[0]) && ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) || (xs[2].equals(ys[1]) && xs[1].equals(ys[2]))); - } else if (a->opcode == BRW_OPCODE_MOV && + } else if (a->opcode == ELK_OPCODE_MOV && xs[0].file == IMM && - xs[0].type == BRW_REGISTER_TYPE_VF) { + xs[0].type == ELK_REGISTER_TYPE_VF) { src_reg tmp_x = xs[0]; src_reg tmp_y = ys[0]; @@ -163,7 +163,7 @@ instructions_match(vec4_instruction *a, vec4_instruction *b) } bool -vec4_visitor::opt_cse_local(bblock_t *block, const vec4_live_variables &live) +vec4_visitor::opt_cse_local(elk_bblock_t *block, const vec4_live_variables &live) { bool progress = false; exec_list aeb; @@ -190,10 +190,10 @@ vec4_visitor::opt_cse_local(bblock_t *block, const vec4_live_variables &live) } if (!found) { - if (inst->opcode != BRW_OPCODE_MOV || - (inst->opcode == BRW_OPCODE_MOV && + if (inst->opcode != ELK_OPCODE_MOV || + (inst->opcode == ELK_OPCODE_MOV && inst->src[0].file == IMM && - inst->src[0].type == BRW_REGISTER_TYPE_VF)) { + inst->src[0].type == ELK_REGISTER_TYPE_VF)) { /* Our first sighting of this expression. Create an entry. */ aeb_entry *entry = ralloc(cse_ctx, aeb_entry); entry->tmp = src_reg(); /* file will be BAD_FILE */ diff --git a/src/intel/compiler/elk/elk_vec4_dead_code_eliminate.cpp b/src/intel/compiler/elk/elk_vec4_dead_code_eliminate.cpp index 5de07c25524..634bd927d73 100644 --- a/src/intel/compiler/elk/elk_vec4_dead_code_eliminate.cpp +++ b/src/intel/compiler/elk/elk_vec4_dead_code_eliminate.cpp @@ -105,7 +105,7 @@ vec4_visitor::dead_code_eliminate() */ if (dest_mask == 0) { progress = true; - inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type)); + inst->dst = dst_reg(retype(elk_null_reg(), inst->dst.type)); } } else { for (int c = 0; c < 4; c++) { @@ -115,9 +115,9 @@ vec4_visitor::dead_code_eliminate() if (inst->dst.writemask == 0) { if (inst->writes_accumulator) { - inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type)); + inst->dst = dst_reg(retype(elk_null_reg(), inst->dst.type)); } else { - inst->opcode = BRW_OPCODE_NOP; + inst->opcode = ELK_OPCODE_NOP; break; } } @@ -132,7 +132,7 @@ vec4_visitor::dead_code_eliminate() combined_live |= BITSET_TEST(flag_live, c); if (!combined_live) { - inst->opcode = BRW_OPCODE_NOP; + inst->opcode = ELK_OPCODE_NOP; progress = true; } } @@ -154,7 +154,7 @@ vec4_visitor::dead_code_eliminate() BITSET_CLEAR(flag_live, c); } - if (inst->opcode == BRW_OPCODE_NOP) { + if (inst->opcode == ELK_OPCODE_NOP) { inst->remove(block); continue; } diff --git a/src/intel/compiler/elk/elk_vec4_generator.cpp b/src/intel/compiler/elk/elk_vec4_generator.cpp index 4d508fd1e9c..03ff460e637 100644 --- a/src/intel/compiler/elk/elk_vec4_generator.cpp +++ b/src/intel/compiler/elk/elk_vec4_generator.cpp @@ -30,53 +30,53 @@ using namespace elk; static void -generate_math1_gfx4(struct brw_codegen *p, +generate_math1_gfx4(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src) + struct elk_reg dst, + struct elk_reg src) { - gfx4_math(p, + elk_gfx4_math(p, dst, - brw_math_function(inst->opcode), + elk_math_function(inst->opcode), inst->base_mrf, src, - BRW_MATH_PRECISION_FULL); + ELK_MATH_PRECISION_FULL); } static void -check_gfx6_math_src_arg(struct brw_reg src) +check_gfx6_math_src_arg(struct elk_reg src) { /* Source swizzles are ignored. */ assert(!src.abs); assert(!src.negate); - assert(src.swizzle == BRW_SWIZZLE_XYZW); + assert(src.swizzle == ELK_SWIZZLE_XYZW); } static void -generate_math_gfx6(struct brw_codegen *p, +generate_math_gfx6(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1) + struct elk_reg dst, + struct elk_reg src0, + struct elk_reg src1) { /* Can't do writemask because math can't be align16. */ assert(dst.writemask == WRITEMASK_XYZW); /* Source swizzles are ignored. */ check_gfx6_math_src_arg(src0); - if (src1.file == BRW_GENERAL_REGISTER_FILE) + if (src1.file == ELK_GENERAL_REGISTER_FILE) check_gfx6_math_src_arg(src1); - brw_set_default_access_mode(p, BRW_ALIGN_1); - gfx6_math(p, dst, brw_math_function(inst->opcode), src0, src1); - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_gfx6_math(p, dst, elk_math_function(inst->opcode), src0, src1); + elk_set_default_access_mode(p, ELK_ALIGN_16); } static void -generate_math2_gfx4(struct brw_codegen *p, +generate_math2_gfx4(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1) + struct elk_reg dst, + struct elk_reg src0, + struct elk_reg src1) { /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13 * "Message Payload": @@ -87,88 +87,88 @@ generate_math2_gfx4(struct brw_codegen *p, * "Operand1[7]. For the INT DIV functions, this operand is the * numerator." */ - bool is_int_div = inst->opcode != SHADER_OPCODE_POW; - struct brw_reg &op0 = is_int_div ? src1 : src0; - struct brw_reg &op1 = is_int_div ? src0 : src1; + bool is_int_div = inst->opcode != ELK_SHADER_OPCODE_POW; + struct elk_reg &op0 = is_int_div ? src1 : src0; + struct elk_reg &op1 = is_int_div ? src0 : src1; - brw_push_insn_state(p); - brw_set_default_saturate(p, false); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); - brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_saturate(p, false); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); + elk_MOV(p, retype(elk_message_reg(inst->base_mrf + 1), op1.type), op1); + elk_pop_insn_state(p); - gfx4_math(p, + elk_gfx4_math(p, dst, - brw_math_function(inst->opcode), + elk_math_function(inst->opcode), inst->base_mrf, op0, - BRW_MATH_PRECISION_FULL); + ELK_MATH_PRECISION_FULL); } static void -generate_tex(struct brw_codegen *p, - struct brw_vue_prog_data *prog_data, +generate_tex(struct elk_codegen *p, + struct elk_vue_prog_data *prog_data, gl_shader_stage stage, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg surface_index, - struct brw_reg sampler_index) + struct elk_reg dst, + struct elk_reg src, + struct elk_reg surface_index, + struct elk_reg sampler_index) { const struct intel_device_info *devinfo = p->devinfo; int msg_type = -1; if (devinfo->ver >= 5) { switch (inst->opcode) { - case SHADER_OPCODE_TEX: - case SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TXL: if (inst->shadow_compare) { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; } else { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD; } break; - case SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXD: if (inst->shadow_compare) { - /* Gfx7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */ + /* Gfx7.5+. Otherwise, lowered by elk_lower_texture_gradients(). */ assert(devinfo->verx10 == 75); msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE; } else { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS; } break; - case SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF: msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD; break; - case SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS: if (devinfo->ver >= 7) msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS; else msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD; break; - case SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXF_MCS: assert(devinfo->ver >= 7); msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS; break; - case SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TXS: msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO; break; - case SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4: if (inst->shadow_compare) { msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C; } else { msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4; } break; - case SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_TG4_OFFSET: if (inst->shadow_compare) { msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C; } else { msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO; } break; - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_SAMPLEINFO: msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO; break; default: @@ -176,27 +176,27 @@ generate_tex(struct brw_codegen *p, } } else { switch (inst->opcode) { - case SHADER_OPCODE_TEX: - case SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TXL: if (inst->shadow_compare) { - msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE; + msg_type = ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE; assert(inst->mlen == 3); } else { - msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD; + msg_type = ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD; assert(inst->mlen == 2); } break; - case SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXD: /* There is no sample_d_c message; comparisons are done manually. */ - msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS; + msg_type = ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS; assert(inst->mlen == 4); break; - case SHADER_OPCODE_TXF: - msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD; + case ELK_SHADER_OPCODE_TXF: + msg_type = ELK_SAMPLER_MESSAGE_SIMD4X2_LD; assert(inst->mlen == 2); break; - case SHADER_OPCODE_TXS: - msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO; + case ELK_SHADER_OPCODE_TXS: + msg_type = ELK_SAMPLER_MESSAGE_SIMD4X2_RESINFO; assert(inst->mlen == 2); break; default: @@ -206,7 +206,7 @@ generate_tex(struct brw_codegen *p, assert(msg_type != -1); - assert(sampler_index.type == BRW_REGISTER_TYPE_UD); + assert(sampler_index.type == ELK_REGISTER_TYPE_UD); /* Load the message header if present. If there's a texture offset, we need * to set it up explicitly and load the offset bitfield. Otherwise, we can @@ -215,18 +215,18 @@ generate_tex(struct brw_codegen *p, if (inst->header_size != 0) { if (devinfo->ver < 6 && !inst->offset) { /* Set up an implied move from g0 to the MRF. */ - src = brw_vec8_grf(0, 0); + src = elk_vec8_grf(0, 0); } else { - struct brw_reg header = - retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD); + struct elk_reg header = + retype(elk_message_reg(inst->base_mrf), ELK_REGISTER_TYPE_UD); uint32_t dw2 = 0; /* Explicitly set up the message header by copying g0 to the MRF. */ - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, header, retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_1); if (inst->offset) /* Set the texel offset bits in DWord 2. */ @@ -240,25 +240,25 @@ generate_tex(struct brw_codegen *p, if (dw2 || stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_GEOMETRY) { - brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2)); + elk_MOV(p, get_element_ud(header, 2), elk_imm_ud(dw2)); } - brw_adjust_sampler_state_pointer(p, header, sampler_index); - brw_pop_insn_state(p); + elk_adjust_sampler_state_pointer(p, header, sampler_index); + elk_pop_insn_state(p); } } uint32_t return_format; switch (dst.type) { - case BRW_REGISTER_TYPE_D: - return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32; + case ELK_REGISTER_TYPE_D: + return_format = ELK_SAMPLER_RETURN_FORMAT_SINT32; break; - case BRW_REGISTER_TYPE_UD: - return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; + case ELK_REGISTER_TYPE_UD: + return_format = ELK_SAMPLER_RETURN_FORMAT_UINT32; break; default: - return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; + return_format = ELK_SAMPLER_RETURN_FORMAT_FLOAT32; break; } @@ -270,15 +270,15 @@ generate_tex(struct brw_codegen *p, * the time regasrdless. Since we can really only do non-UINT32 on gfx4, * just stomp it to UINT32 all the time. */ - if (inst->opcode == SHADER_OPCODE_TXS) - return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; + if (inst->opcode == ELK_SHADER_OPCODE_TXS) + return_format = ELK_SAMPLER_RETURN_FORMAT_UINT32; - if (surface_index.file == BRW_IMMEDIATE_VALUE && - sampler_index.file == BRW_IMMEDIATE_VALUE) { + if (surface_index.file == ELK_IMMEDIATE_VALUE && + sampler_index.file == ELK_IMMEDIATE_VALUE) { uint32_t surface = surface_index.ud; uint32_t sampler = sampler_index.ud; - brw_SAMPLE(p, + elk_SAMPLE(p, dst, inst->base_mrf, src, @@ -288,45 +288,45 @@ generate_tex(struct brw_codegen *p, 1, /* response length */ inst->mlen, inst->header_size != 0, - BRW_SAMPLER_SIMD_MODE_SIMD4X2, + ELK_SAMPLER_SIMD_MODE_SIMD4X2, return_format); } else { /* Non-constant sampler index. */ - struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD)); - struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD)); - struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD)); + struct elk_reg addr = vec1(retype(elk_address_reg(0), ELK_REGISTER_TYPE_UD)); + struct elk_reg surface_reg = vec1(retype(surface_index, ELK_REGISTER_TYPE_UD)); + struct elk_reg sampler_reg = vec1(retype(sampler_index, ELK_REGISTER_TYPE_UD)); - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_access_mode(p, ELK_ALIGN_1); - if (brw_regs_equal(&surface_reg, &sampler_reg)) { - brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101)); + if (elk_regs_equal(&surface_reg, &sampler_reg)) { + elk_MUL(p, addr, sampler_reg, elk_imm_uw(0x101)); } else { - if (sampler_reg.file == BRW_IMMEDIATE_VALUE) { - brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8)); + if (sampler_reg.file == ELK_IMMEDIATE_VALUE) { + elk_OR(p, addr, surface_reg, elk_imm_ud(sampler_reg.ud << 8)); } else { - brw_SHL(p, addr, sampler_reg, brw_imm_ud(8)); - brw_OR(p, addr, addr, surface_reg); + elk_SHL(p, addr, sampler_reg, elk_imm_ud(8)); + elk_OR(p, addr, addr, surface_reg); } } - brw_AND(p, addr, addr, brw_imm_ud(0xfff)); + elk_AND(p, addr, addr, elk_imm_ud(0xfff)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); if (inst->base_mrf != -1) - gfx6_resolve_implied_move(p, &src, inst->base_mrf); + elk_gfx6_resolve_implied_move(p, &src, inst->base_mrf); /* dst = send(offset, a0.0 | ) */ - brw_send_indirect_message( - p, BRW_SFID_SAMPLER, dst, src, addr, - brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) | - brw_sampler_desc(devinfo, + elk_send_indirect_message( + p, ELK_SFID_SAMPLER, dst, src, addr, + elk_message_desc(devinfo, inst->mlen, 1, inst->header_size) | + elk_sampler_desc(devinfo, 0 /* surface */, 0 /* sampler */, msg_type, - BRW_SAMPLER_SIMD_MODE_SIMD4X2, + ELK_SAMPLER_SIMD_MODE_SIMD4X2, return_format), false /* EOT */); @@ -337,79 +337,79 @@ generate_tex(struct brw_codegen *p, } static void -generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst) +generate_vs_urb_write(struct elk_codegen *p, vec4_instruction *inst) { - brw_urb_WRITE(p, - brw_null_reg(), /* dest */ + elk_urb_WRITE(p, + elk_null_reg(), /* dest */ inst->base_mrf, /* starting mrf reg nr */ - brw_vec8_grf(0, 0), /* src */ + elk_vec8_grf(0, 0), /* src */ inst->urb_write_flags, inst->mlen, 0, /* response len */ inst->offset, /* urb destination offset */ - BRW_URB_SWIZZLE_INTERLEAVE); + ELK_URB_SWIZZLE_INTERLEAVE); } static void -generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst) +generate_gs_urb_write(struct elk_codegen *p, vec4_instruction *inst) { - struct brw_reg src = brw_message_reg(inst->base_mrf); - brw_urb_WRITE(p, - brw_null_reg(), /* dest */ + struct elk_reg src = elk_message_reg(inst->base_mrf); + elk_urb_WRITE(p, + elk_null_reg(), /* dest */ inst->base_mrf, /* starting mrf reg nr */ src, inst->urb_write_flags, inst->mlen, 0, /* response len */ inst->offset, /* urb destination offset */ - BRW_URB_SWIZZLE_INTERLEAVE); + ELK_URB_SWIZZLE_INTERLEAVE); } static void -generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst) +generate_gs_urb_write_allocate(struct elk_codegen *p, vec4_instruction *inst) { - struct brw_reg src = brw_message_reg(inst->base_mrf); + struct elk_reg src = elk_message_reg(inst->base_mrf); /* We pass the temporary passed in src0 as the writeback register */ - brw_urb_WRITE(p, - inst->src[0].as_brw_reg(), /* dest */ + elk_urb_WRITE(p, + inst->src[0].as_elk_reg(), /* dest */ inst->base_mrf, /* starting mrf reg nr */ src, - BRW_URB_WRITE_ALLOCATE_COMPLETE, + ELK_URB_WRITE_ALLOCATE_COMPLETE, inst->mlen, 1, /* response len */ inst->offset, /* urb destination offset */ - BRW_URB_SWIZZLE_INTERLEAVE); + ELK_URB_SWIZZLE_INTERLEAVE); /* Now put allocated urb handle in dst.0 */ - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0), - get_element_ud(inst->src[0].as_brw_reg(), 0)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, get_element_ud(inst->dst.as_elk_reg(), 0), + get_element_ud(inst->src[0].as_elk_reg(), 0)); + elk_pop_insn_state(p); } static void -generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst) +generate_gs_thread_end(struct elk_codegen *p, vec4_instruction *inst) { - struct brw_reg src = brw_message_reg(inst->base_mrf); - brw_urb_WRITE(p, - brw_null_reg(), /* dest */ + struct elk_reg src = elk_message_reg(inst->base_mrf); + elk_urb_WRITE(p, + elk_null_reg(), /* dest */ inst->base_mrf, /* starting mrf reg nr */ src, - BRW_URB_WRITE_EOT | inst->urb_write_flags, + ELK_URB_WRITE_EOT | inst->urb_write_flags, inst->mlen, 0, /* response len */ 0, /* urb destination offset */ - BRW_URB_SWIZZLE_INTERLEAVE); + ELK_URB_SWIZZLE_INTERLEAVE); } static void -generate_gs_set_write_offset(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1) +generate_gs_set_write_offset(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src0, + struct elk_reg src1) { /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message * Header: M0.3): @@ -429,33 +429,33 @@ generate_gs_set_write_offset(struct brw_codegen *p, * * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all } */ - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); assert(p->devinfo->ver >= 7 && - src1.file == BRW_IMMEDIATE_VALUE && - src1.type == BRW_REGISTER_TYPE_UD && + src1.file == ELK_IMMEDIATE_VALUE && + src1.type == ELK_REGISTER_TYPE_UD && src1.ud <= USHRT_MAX); - if (src0.file == BRW_IMMEDIATE_VALUE) { - brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3), - brw_imm_ud(src0.ud * src1.ud)); + if (src0.file == ELK_IMMEDIATE_VALUE) { + elk_MOV(p, suboffset(stride(dst, 2, 2, 1), 3), + elk_imm_ud(src0.ud * src1.ud)); } else { - if (src1.file == BRW_IMMEDIATE_VALUE) { - src1 = brw_imm_uw(src1.ud); + if (src1.file == ELK_IMMEDIATE_VALUE) { + src1 = elk_imm_uw(src1.ud); } - brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4), - retype(src1, BRW_REGISTER_TYPE_UW)); + elk_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4), + retype(src1, ELK_REGISTER_TYPE_UW)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_gs_set_vertex_count(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src) +generate_gs_set_vertex_count(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src) { - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); /* If we think of the src and dst registers as composed of 8 DWORDs each, * we want to pick up the contents of DWORDs 0 and 4 from src, truncate @@ -470,38 +470,38 @@ generate_gs_set_vertex_count(struct brw_codegen *p, * * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask } */ - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_MOV(p, - suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4), - stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0)); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_MOV(p, + suboffset(stride(retype(dst, ELK_REGISTER_TYPE_UW), 2, 2, 1), 4), + stride(retype(src, ELK_REGISTER_TYPE_UW), 8, 1, 0)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_gs_svb_write(struct brw_codegen *p, +generate_gs_svb_write(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1) + struct elk_reg dst, + struct elk_reg src0, + struct elk_reg src1) { int binding = inst->sol_binding; bool final_write = inst->sol_final_write; - brw_push_insn_state(p); - brw_set_default_exec_size(p, BRW_EXECUTE_4); + elk_push_insn_state(p); + elk_set_default_exec_size(p, ELK_EXECUTE_4); /* Copy Vertex data into M0.x */ - brw_MOV(p, stride(dst, 4, 4, 1), - stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1)); - brw_pop_insn_state(p); + elk_MOV(p, stride(dst, 4, 4, 1), + stride(retype(src0, ELK_REGISTER_TYPE_UD), 4, 4, 1)); + elk_pop_insn_state(p); - brw_push_insn_state(p); + elk_push_insn_state(p); /* Send SVB Write */ - brw_svb_write(p, - final_write ? src1 : brw_null_reg(), /* dest == src1 */ + elk_svb_write(p, + final_write ? src1 : elk_null_reg(), /* dest == src1 */ 1, /* msg_reg_nr */ dst, /* src0 == previous dst */ - BRW_GFX6_SOL_BINDING_START + binding, /* binding_table_index */ + ELK_GFX6_SOL_BINDING_START + binding, /* binding_table_index */ final_write); /* send_commit_msg */ /* Finally, wait for the write commit to occur so that we can proceed to @@ -515,40 +515,40 @@ generate_gs_svb_write(struct brw_codegen *p, * source is sufficient to wait for the write commit to occur. */ if (final_write) { - brw_MOV(p, src1, src1); + elk_MOV(p, src1, src1); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_gs_svb_set_destination_index(struct brw_codegen *p, +generate_gs_svb_set_destination_index(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src) + struct elk_reg dst, + struct elk_reg src) { int vertex = inst->sol_vertex; - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex)); + elk_pop_insn_state(p); } static void -generate_gs_set_dword_2(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src) +generate_gs_set_dword_2(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src) { - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0)); + elk_pop_insn_state(p); } static void -generate_gs_prepare_channel_masks(struct brw_codegen *p, - struct brw_reg dst) +generate_gs_prepare_channel_masks(struct elk_codegen *p, + struct elk_reg dst) { /* We want to left shift just DWORD 4 (the x component belonging to the * second geometry shader invocation) by 4 bits. So generate the @@ -557,17 +557,17 @@ generate_gs_prepare_channel_masks(struct brw_codegen *p, * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all } */ dst = suboffset(vec1(dst), 4); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_SHL(p, dst, dst, brw_imm_ud(4)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_SHL(p, dst, dst, elk_imm_ud(4)); + elk_pop_insn_state(p); } static void -generate_gs_set_channel_masks(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src) +generate_gs_set_channel_masks(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src) { /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message * Header: M0.5): @@ -614,87 +614,87 @@ generate_gs_set_channel_masks(struct brw_codegen *p, * * Note: this relies on the source register having zeros in (a) bits 7:4 of * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the - * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which + * source register was prepared by ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS (which * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to - * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to + * the execution of ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to * contain valid channel mask values (which are in the range 0x0-0xf). */ - dst = retype(dst, BRW_REGISTER_TYPE_UB); - src = retype(src, BRW_REGISTER_TYPE_UB); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16)); - brw_pop_insn_state(p); + dst = retype(dst, ELK_REGISTER_TYPE_UB); + src = retype(src, ELK_REGISTER_TYPE_UB); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16)); + elk_pop_insn_state(p); } static void -generate_gs_get_instance_id(struct brw_codegen *p, - struct brw_reg dst) +generate_gs_get_instance_id(struct elk_codegen *p, + struct elk_reg dst) { /* We want to right shift R0.0 & R0.1 by GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT * and store into dst.0 & dst.4. So generate the instruction: * * shr(8) dst<1> R0<1,4,0> GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q } */ - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - dst = retype(dst, BRW_REGISTER_TYPE_UD); - struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); - brw_SHR(p, dst, stride(r0, 1, 4, 0), - brw_imm_ud(GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + dst = retype(dst, ELK_REGISTER_TYPE_UD); + struct elk_reg r0(retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); + elk_SHR(p, dst, stride(r0, 1, 4, 0), + elk_imm_ud(GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT)); + elk_pop_insn_state(p); } static void -generate_gs_ff_sync_set_primitives(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1, - struct brw_reg src2) +generate_gs_ff_sync_set_primitives(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg src0, + struct elk_reg src1, + struct elk_reg src2) { - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); /* Save src0 data in 16:31 bits of dst.0 */ - brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0), - brw_imm_ud(0xffffu)); - brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16)); + elk_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0), + elk_imm_ud(0xffffu)); + elk_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), elk_imm_ud(16)); /* Save src1 data in 0:15 bits of dst.0 */ - brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0), - brw_imm_ud(0xffffu)); - brw_OR(p, suboffset(vec1(dst), 0), + elk_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0), + elk_imm_ud(0xffffu)); + elk_OR(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), suboffset(vec1(src2), 0)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_gs_ff_sync(struct brw_codegen *p, +generate_gs_ff_sync(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1) + struct elk_reg dst, + struct elk_reg src0, + struct elk_reg src1) { /* This opcode uses an implied MRF register for: * - the header of the ff_sync message. And as such it is expected to be * initialized to r0 before calling here. * - the destination where we will write the allocated URB handle. */ - struct brw_reg header = - retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD); + struct elk_reg header = + retype(elk_message_reg(inst->base_mrf), ELK_REGISTER_TYPE_UD); /* Overwrite dword 0 of the header (SO vertices to write) and * dword 1 (number of primitives written). */ - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0)); - brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0)); + elk_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0)); + elk_pop_insn_state(p); /* Allocate URB handle in dst */ - brw_ff_sync(p, + elk_ff_sync(p, dst, 0, header, @@ -703,34 +703,34 @@ generate_gs_ff_sync(struct brw_codegen *p, 0 /* eot */); /* Now put allocated urb handle in header.0 */ - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0)); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0)); /* src1 is not an immediate when we use transform feedback */ - if (src1.file != BRW_IMMEDIATE_VALUE) { - brw_set_default_exec_size(p, BRW_EXECUTE_4); - brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1)); + if (src1.file != ELK_IMMEDIATE_VALUE) { + elk_set_default_exec_size(p, ELK_EXECUTE_4); + elk_MOV(p, elk_vec4_grf(src1.nr, 0), elk_vec4_grf(dst.nr, 1)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst) +generate_gs_set_primitive_id(struct elk_codegen *p, struct elk_reg dst) { /* In gfx6, PrimitiveID is delivered in R0.1 of the payload */ - struct brw_reg src = brw_vec8_grf(0, 0); - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1)); - brw_pop_insn_state(p); + struct elk_reg src = elk_vec8_grf(0, 0); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1)); + elk_pop_insn_state(p); } static void -generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst) +generate_tcs_get_instance_id(struct elk_codegen *p, struct elk_reg dst) { const struct intel_device_info *devinfo = p->devinfo; const bool ivb = devinfo->platform == INTEL_PLATFORM_IVB || @@ -742,43 +742,43 @@ generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst) * as necessary. So we assign (2i + 1, 2i) as the thread counts. We * shift right by one less to accomplish the multiplication by two. */ - dst = retype(dst, BRW_REGISTER_TYPE_UD); - struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + dst = retype(dst, ELK_REGISTER_TYPE_UD); + struct elk_reg r0(retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17); const int shift = ivb ? 16 : 17; - brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask)); - brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0), - brw_imm_ud(shift - 1)); - brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1)); + elk_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), elk_imm_ud(mask)); + elk_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0), + elk_imm_ud(shift - 1)); + elk_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), elk_imm_ud(1)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_tcs_urb_write(struct brw_codegen *p, +generate_tcs_urb_write(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg urb_header) + struct elk_reg urb_header) { const struct intel_device_info *devinfo = p->devinfo; - brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); - brw_set_dest(p, send, brw_null_reg()); - brw_set_src0(p, send, urb_header); - brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true)); + elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND); + elk_set_dest(p, send, elk_null_reg()); + elk_set_src0(p, send, urb_header); + elk_set_desc(p, send, elk_message_desc(devinfo, inst->mlen, 0, true)); - brw_inst_set_sfid(devinfo, send, BRW_SFID_URB); - brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD); - brw_inst_set_urb_global_offset(devinfo, send, inst->offset); - if (inst->urb_write_flags & BRW_URB_WRITE_EOT) { - brw_inst_set_eot(devinfo, send, 1); + elk_inst_set_sfid(devinfo, send, ELK_SFID_URB); + elk_inst_set_urb_opcode(devinfo, send, ELK_URB_OPCODE_WRITE_OWORD); + elk_inst_set_urb_global_offset(devinfo, send, inst->offset); + if (inst->urb_write_flags & ELK_URB_WRITE_EOT) { + elk_inst_set_eot(devinfo, send, 1); } else { - brw_inst_set_urb_per_slot_offset(devinfo, send, 1); - brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE); + elk_inst_set_urb_per_slot_offset(devinfo, send, 1); + elk_inst_set_urb_swizzle_control(devinfo, send, ELK_URB_SWIZZLE_INTERLEAVE); } /* what happens to swizzles? */ @@ -786,10 +786,10 @@ generate_tcs_urb_write(struct brw_codegen *p, static void -generate_tcs_input_urb_offsets(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg vertex, - struct brw_reg offset) +generate_tcs_input_urb_offsets(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg vertex, + struct elk_reg offset) { /* Generates an URB read/write message header for HS/DS operation. * Inputs are a vertex index, and a byte offset from the beginning of @@ -797,27 +797,27 @@ generate_tcs_input_urb_offsets(struct brw_codegen *p, /* If `vertex` is not an immediate, we clobber a0.0 */ - assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE); - assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D); + assert(vertex.file == ELK_IMMEDIATE_VALUE || vertex.file == ELK_GENERAL_REGISTER_FILE); + assert(vertex.type == ELK_REGISTER_TYPE_UD || vertex.type == ELK_REGISTER_TYPE_D); - assert(dst.file == BRW_GENERAL_REGISTER_FILE); + assert(dst.file == ELK_GENERAL_REGISTER_FILE); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, dst, brw_imm_ud(0)); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, dst, elk_imm_ud(0)); /* m0.5 bits 8-15 are channel enables */ - brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00)); + elk_MOV(p, get_element_ud(dst, 5), elk_imm_ud(0xff00)); /* m0.0-0.1: URB handles */ - if (vertex.file == BRW_IMMEDIATE_VALUE) { + if (vertex.file == ELK_IMMEDIATE_VALUE) { uint32_t vertex_index = vertex.ud; - struct brw_reg index_reg = brw_vec1_grf( + struct elk_reg index_reg = elk_vec1_grf( 1 + (vertex_index >> 3), vertex_index & 7); - brw_MOV(p, vec2(get_element_ud(dst, 0)), - retype(index_reg, BRW_REGISTER_TYPE_UD)); + elk_MOV(p, vec2(get_element_ud(dst, 0)), + retype(index_reg, ELK_REGISTER_TYPE_UD)); } else { /* Use indirect addressing. ICP Handles are DWords (single channels * of a register) and start at g1.0. @@ -829,201 +829,201 @@ generate_tcs_input_urb_offsets(struct brw_codegen *p, * Indirect addressing works in terms of bytes, so we then multiply * the DWord offset by 4 (by shifting left by 2). */ - struct brw_reg addr = brw_address_reg(0); + struct elk_reg addr = elk_address_reg(0); /* bottom half: m0.0 = g[1.0 + vertex.0]UD */ - brw_ADD(p, addr, retype(get_element_ud(vertex, 0), BRW_REGISTER_TYPE_UW), - brw_imm_uw(0x8)); - brw_SHL(p, addr, addr, brw_imm_uw(2)); - brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0)); + elk_ADD(p, addr, retype(get_element_ud(vertex, 0), ELK_REGISTER_TYPE_UW), + elk_imm_uw(0x8)); + elk_SHL(p, addr, addr, elk_imm_uw(2)); + elk_MOV(p, get_element_ud(dst, 0), deref_1ud(elk_indirect(0, 0), 0)); /* top half: m0.1 = g[1.0 + vertex.4]UD */ - brw_ADD(p, addr, retype(get_element_ud(vertex, 4), BRW_REGISTER_TYPE_UW), - brw_imm_uw(0x8)); - brw_SHL(p, addr, addr, brw_imm_uw(2)); - brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0)); + elk_ADD(p, addr, retype(get_element_ud(vertex, 4), ELK_REGISTER_TYPE_UW), + elk_imm_uw(0x8)); + elk_SHL(p, addr, addr, elk_imm_uw(2)); + elk_MOV(p, get_element_ud(dst, 1), deref_1ud(elk_indirect(0, 0), 0)); } /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */ if (offset.file != ARF) - brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0)); + elk_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_tcs_output_urb_offsets(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg write_mask, - struct brw_reg offset) +generate_tcs_output_urb_offsets(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg write_mask, + struct elk_reg offset) { /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */ - assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE); + assert(dst.file == ELK_GENERAL_REGISTER_FILE || dst.file == ELK_MESSAGE_REGISTER_FILE); - assert(write_mask.file == BRW_IMMEDIATE_VALUE); - assert(write_mask.type == BRW_REGISTER_TYPE_UD); + assert(write_mask.file == ELK_IMMEDIATE_VALUE); + assert(write_mask.type == ELK_REGISTER_TYPE_UD); - brw_push_insn_state(p); + elk_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, dst, brw_imm_ud(0)); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, dst, elk_imm_ud(0)); unsigned mask = write_mask.ud; /* m0.5 bits 15:12 and 11:8 are channel enables */ - brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12))); + elk_MOV(p, get_element_ud(dst, 5), elk_imm_ud((mask << 8) | (mask << 12))); /* HS patch URB handle is delivered in r0.0 */ - struct brw_reg urb_handle = brw_vec1_grf(0, 0); + struct elk_reg urb_handle = elk_vec1_grf(0, 0); /* m0.0-0.1: URB handles */ - brw_MOV(p, vec2(get_element_ud(dst, 0)), - retype(urb_handle, BRW_REGISTER_TYPE_UD)); + elk_MOV(p, vec2(get_element_ud(dst, 0)), + retype(urb_handle, ELK_REGISTER_TYPE_UD)); /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */ if (offset.file != ARF) - brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0)); + elk_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_tes_create_input_read_header(struct brw_codegen *p, - struct brw_reg dst) +generate_tes_create_input_read_header(struct elk_codegen *p, + struct elk_reg dst) { - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); /* Initialize the register to 0 */ - brw_MOV(p, dst, brw_imm_ud(0)); + elk_MOV(p, dst, elk_imm_ud(0)); /* Enable all the channels in m0.5 bits 15:8 */ - brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00)); + elk_MOV(p, get_element_ud(dst, 5), elk_imm_ud(0xff00)); /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety, * mask out irrelevant "Reserved" bits, as they're not marked MBZ. */ - brw_AND(p, vec2(get_element_ud(dst, 0)), - retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD), - brw_imm_ud(0x1fff)); - brw_pop_insn_state(p); + elk_AND(p, vec2(get_element_ud(dst, 0)), + retype(elk_vec1_grf(1, 3), ELK_REGISTER_TYPE_UD), + elk_imm_ud(0x1fff)); + elk_pop_insn_state(p); } static void -generate_tes_add_indirect_urb_offset(struct brw_codegen *p, - struct brw_reg dst, - struct brw_reg header, - struct brw_reg offset) +generate_tes_add_indirect_urb_offset(struct elk_codegen *p, + struct elk_reg dst, + struct elk_reg header, + struct elk_reg offset) { - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); - brw_MOV(p, dst, header); + elk_MOV(p, dst, header); /* Uniforms will have a stride <0;4,1>, and we need to convert to <0;1,0>. * Other values get <4;1,0>. */ - struct brw_reg restrided_offset; - if (offset.vstride == BRW_VERTICAL_STRIDE_0 && - offset.width == BRW_WIDTH_4 && - offset.hstride == BRW_HORIZONTAL_STRIDE_1) { + struct elk_reg restrided_offset; + if (offset.vstride == ELK_VERTICAL_STRIDE_0 && + offset.width == ELK_WIDTH_4 && + offset.hstride == ELK_HORIZONTAL_STRIDE_1) { restrided_offset = stride(offset, 0, 1, 0); } else { restrided_offset = stride(offset, 4, 1, 0); } /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */ - brw_MOV(p, vec2(get_element_ud(dst, 3)), restrided_offset); + elk_MOV(p, vec2(get_element_ud(dst, 3)), restrided_offset); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_vec4_urb_read(struct brw_codegen *p, +generate_vec4_urb_read(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg header) + struct elk_reg dst, + struct elk_reg header) { const struct intel_device_info *devinfo = p->devinfo; - assert(header.file == BRW_GENERAL_REGISTER_FILE); - assert(header.type == BRW_REGISTER_TYPE_UD); + assert(header.file == ELK_GENERAL_REGISTER_FILE); + assert(header.type == ELK_REGISTER_TYPE_UD); - brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); - brw_set_dest(p, send, dst); - brw_set_src0(p, send, header); + elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND); + elk_set_dest(p, send, dst); + elk_set_src0(p, send, header); - brw_set_desc(p, send, brw_message_desc(devinfo, 1, 1, true)); + elk_set_desc(p, send, elk_message_desc(devinfo, 1, 1, true)); - brw_inst_set_sfid(devinfo, send, BRW_SFID_URB); - brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD); - brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE); - brw_inst_set_urb_per_slot_offset(devinfo, send, 1); + elk_inst_set_sfid(devinfo, send, ELK_SFID_URB); + elk_inst_set_urb_opcode(devinfo, send, ELK_URB_OPCODE_READ_OWORD); + elk_inst_set_urb_swizzle_control(devinfo, send, ELK_URB_SWIZZLE_INTERLEAVE); + elk_inst_set_urb_per_slot_offset(devinfo, send, 1); - brw_inst_set_urb_global_offset(devinfo, send, inst->offset); + elk_inst_set_urb_global_offset(devinfo, send, inst->offset); } static void -generate_tcs_release_input(struct brw_codegen *p, - struct brw_reg header, - struct brw_reg vertex, - struct brw_reg is_unpaired) +generate_tcs_release_input(struct elk_codegen *p, + struct elk_reg header, + struct elk_reg vertex, + struct elk_reg is_unpaired) { const struct intel_device_info *devinfo = p->devinfo; - assert(vertex.file == BRW_IMMEDIATE_VALUE); - assert(vertex.type == BRW_REGISTER_TYPE_UD); + assert(vertex.file == ELK_IMMEDIATE_VALUE); + assert(vertex.type == ELK_REGISTER_TYPE_UD); /* m0.0-0.1: URB handles */ - struct brw_reg urb_handles = - retype(brw_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7), - BRW_REGISTER_TYPE_UD); + struct elk_reg urb_handles = + retype(elk_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7), + ELK_REGISTER_TYPE_UD); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, header, brw_imm_ud(0)); - brw_MOV(p, vec2(get_element_ud(header, 0)), urb_handles); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, header, elk_imm_ud(0)); + elk_MOV(p, vec2(get_element_ud(header, 0)), urb_handles); + elk_pop_insn_state(p); - brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); - brw_set_dest(p, send, brw_null_reg()); - brw_set_src0(p, send, header); - brw_set_desc(p, send, brw_message_desc(devinfo, 1, 0, true)); + elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND); + elk_set_dest(p, send, elk_null_reg()); + elk_set_src0(p, send, header); + elk_set_desc(p, send, elk_message_desc(devinfo, 1, 0, true)); - brw_inst_set_sfid(devinfo, send, BRW_SFID_URB); - brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD); - brw_inst_set_urb_complete(devinfo, send, 1); - brw_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ? - BRW_URB_SWIZZLE_NONE : - BRW_URB_SWIZZLE_INTERLEAVE); + elk_inst_set_sfid(devinfo, send, ELK_SFID_URB); + elk_inst_set_urb_opcode(devinfo, send, ELK_URB_OPCODE_READ_OWORD); + elk_inst_set_urb_complete(devinfo, send, 1); + elk_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ? + ELK_URB_SWIZZLE_NONE : + ELK_URB_SWIZZLE_INTERLEAVE); } static void -generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst) +generate_tcs_thread_end(struct elk_codegen *p, vec4_instruction *inst) { - struct brw_reg header = brw_message_reg(inst->base_mrf); + struct elk_reg header = elk_message_reg(inst->base_mrf); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, header, brw_imm_ud(0)); - brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8)); - brw_MOV(p, get_element_ud(header, 0), - retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)); - brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_MOV(p, header, elk_imm_ud(0)); + elk_MOV(p, get_element_ud(header, 5), elk_imm_ud(WRITEMASK_X << 8)); + elk_MOV(p, get_element_ud(header, 0), + retype(elk_vec1_grf(0, 0), ELK_REGISTER_TYPE_UD)); + elk_MOV(p, elk_message_reg(inst->base_mrf + 1), elk_imm_ud(0u)); + elk_pop_insn_state(p); - brw_urb_WRITE(p, - brw_null_reg(), /* dest */ + elk_urb_WRITE(p, + elk_null_reg(), /* dest */ inst->base_mrf, /* starting mrf reg nr */ header, - BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD | - BRW_URB_WRITE_USE_CHANNEL_MASKS, + ELK_URB_WRITE_EOT | ELK_URB_WRITE_OWORD | + ELK_URB_WRITE_USE_CHANNEL_MASKS, inst->mlen, 0, /* response len */ 0, /* urb destination offset */ @@ -1031,59 +1031,59 @@ generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst) } static void -generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst) +generate_tes_get_primitive_id(struct elk_codegen *p, struct elk_reg dst) { - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_MOV(p, dst, retype(elk_vec1_grf(1, 7), ELK_REGISTER_TYPE_D)); + elk_pop_insn_state(p); } static void -generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst) +generate_tcs_get_primitive_id(struct elk_codegen *p, struct elk_reg dst) { - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD)); - brw_pop_insn_state(p); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_MOV(p, dst, retype(elk_vec1_grf(0, 1), ELK_REGISTER_TYPE_UD)); + elk_pop_insn_state(p); } static void -generate_tcs_create_barrier_header(struct brw_codegen *p, - struct brw_vue_prog_data *prog_data, - struct brw_reg dst) +generate_tcs_create_barrier_header(struct elk_codegen *p, + struct elk_vue_prog_data *prog_data, + struct elk_reg dst) { const struct intel_device_info *devinfo = p->devinfo; const bool ivb = devinfo->platform == INTEL_PLATFORM_IVB || devinfo->platform == INTEL_PLATFORM_BYT; - struct brw_reg m0_2 = get_element_ud(dst, 2); - unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances; + struct elk_reg m0_2 = get_element_ud(dst, 2); + unsigned instances = ((struct elk_tcs_prog_data *) prog_data)->instances; - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); /* Zero the message header */ - brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u)); + elk_MOV(p, retype(dst, ELK_REGISTER_TYPE_UD), elk_imm_ud(0u)); /* Copy "Barrier ID" from r0.2, bits 16:13 (Gfx7.5+) or 15:12 (Gfx7) */ - brw_AND(p, m0_2, - retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), - brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13))); + elk_AND(p, m0_2, + retype(elk_vec1_grf(0, 2), ELK_REGISTER_TYPE_UD), + elk_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13))); /* Shift it up to bits 27:24. */ - brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(ivb ? 12 : 11)); + elk_SHL(p, m0_2, get_element_ud(dst, 2), elk_imm_ud(ivb ? 12 : 11)); /* Set the Barrier Count and the enable bit */ - brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15))); + elk_OR(p, m0_2, m0_2, elk_imm_ud(instances << 9 | (1 << 15))); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_oword_dual_block_offsets(struct brw_codegen *p, - struct brw_reg m1, - struct brw_reg index) +generate_oword_dual_block_offsets(struct elk_codegen *p, + struct elk_reg m1, + struct elk_reg index) { int second_vertex_offset; @@ -1092,63 +1092,63 @@ generate_oword_dual_block_offsets(struct brw_codegen *p, else second_vertex_offset = 16; - m1 = retype(m1, BRW_REGISTER_TYPE_D); + m1 = retype(m1, ELK_REGISTER_TYPE_D); /* Set up M1 (message payload). Only the block offsets in M1.0 and * M1.4 are used, and the rest are ignored. */ - struct brw_reg m1_0 = suboffset(vec1(m1), 0); - struct brw_reg m1_4 = suboffset(vec1(m1), 4); - struct brw_reg index_0 = suboffset(vec1(index), 0); - struct brw_reg index_4 = suboffset(vec1(index), 4); + struct elk_reg m1_0 = suboffset(vec1(m1), 0); + struct elk_reg m1_4 = suboffset(vec1(m1), 4); + struct elk_reg index_0 = suboffset(vec1(index), 0); + struct elk_reg index_4 = suboffset(vec1(index), 4); - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_access_mode(p, ELK_ALIGN_1); - brw_MOV(p, m1_0, index_0); + elk_MOV(p, m1_0, index_0); - if (index.file == BRW_IMMEDIATE_VALUE) { + if (index.file == ELK_IMMEDIATE_VALUE) { index_4.ud += second_vertex_offset; - brw_MOV(p, m1_4, index_4); + elk_MOV(p, m1_4, index_4); } else { - brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); + elk_ADD(p, m1_4, index_4, elk_imm_d(second_vertex_offset)); } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_unpack_flags(struct brw_codegen *p, - struct brw_reg dst) +generate_unpack_flags(struct elk_codegen *p, + struct elk_reg dst) { - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_access_mode(p, ELK_ALIGN_1); - struct brw_reg flags = brw_flag_reg(0, 0); - struct brw_reg dst_0 = suboffset(vec1(dst), 0); - struct brw_reg dst_4 = suboffset(vec1(dst), 4); + struct elk_reg flags = elk_flag_reg(0, 0); + struct elk_reg dst_0 = suboffset(vec1(dst), 0); + struct elk_reg dst_4 = suboffset(vec1(dst), 4); - brw_AND(p, dst_0, flags, brw_imm_ud(0x0f)); - brw_AND(p, dst_4, flags, brw_imm_ud(0xf0)); - brw_SHR(p, dst_4, dst_4, brw_imm_ud(4)); + elk_AND(p, dst_0, flags, elk_imm_ud(0x0f)); + elk_AND(p, dst_4, flags, elk_imm_ud(0xf0)); + elk_SHR(p, dst_4, dst_4, elk_imm_ud(4)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_scratch_read(struct brw_codegen *p, +generate_scratch_read(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg index) + struct elk_reg dst, + struct elk_reg index) { const struct intel_device_info *devinfo = p->devinfo; - struct brw_reg header = brw_vec8_grf(0, 0); + struct elk_reg header = elk_vec8_grf(0, 0); - gfx6_resolve_implied_move(p, &header, inst->base_mrf); + elk_gfx6_resolve_implied_move(p, &header, inst->base_mrf); - generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1), + generate_oword_dual_block_offsets(p, elk_message_reg(inst->base_mrf + 1), index); uint32_t msg_type; @@ -1158,62 +1158,62 @@ generate_scratch_read(struct brw_codegen *p, else if (devinfo->verx10 >= 45) msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; else - msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; + msg_type = ELK_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; const unsigned target_cache = devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE : devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE : - BRW_SFID_DATAPORT_READ; + ELK_SFID_DATAPORT_READ; /* Each of the 8 channel enables is considered for whether each * dword is written. */ - brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); - brw_inst_set_sfid(devinfo, send, target_cache); - brw_set_dest(p, send, dst); - brw_set_src0(p, send, header); + elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND); + elk_inst_set_sfid(devinfo, send, target_cache); + elk_set_dest(p, send, dst); + elk_set_src0(p, send, header); if (devinfo->ver < 6) - brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf); - brw_set_desc(p, send, - brw_message_desc(devinfo, 2, 1, true) | - brw_dp_read_desc(devinfo, - brw_scratch_surface_idx(p), - BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, - msg_type, BRW_DATAPORT_READ_TARGET_RENDER_CACHE)); + elk_inst_set_cond_modifier(devinfo, send, inst->base_mrf); + elk_set_desc(p, send, + elk_message_desc(devinfo, 2, 1, true) | + elk_dp_read_desc(devinfo, + elk_scratch_surface_idx(p), + ELK_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, + msg_type, ELK_DATAPORT_READ_TARGET_RENDER_CACHE)); } static void -generate_scratch_write(struct brw_codegen *p, +generate_scratch_write(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg index) + struct elk_reg dst, + struct elk_reg src, + struct elk_reg index) { const struct intel_device_info *devinfo = p->devinfo; const unsigned target_cache = (devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE : devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE : - BRW_SFID_DATAPORT_WRITE); - struct brw_reg header = brw_vec8_grf(0, 0); + ELK_SFID_DATAPORT_WRITE); + struct elk_reg header = elk_vec8_grf(0, 0); bool write_commit; /* If the instruction is predicated, we'll predicate the send, not * the header setup. */ - brw_push_insn_state(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - brw_set_default_flag_reg(p, 0, 0); + elk_push_insn_state(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); + elk_set_default_flag_reg(p, 0, 0); - gfx6_resolve_implied_move(p, &header, inst->base_mrf); + elk_gfx6_resolve_implied_move(p, &header, inst->base_mrf); - generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1), + generate_oword_dual_block_offsets(p, elk_message_reg(inst->base_mrf + 1), index); - brw_MOV(p, - retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), - retype(src, BRW_REGISTER_TYPE_D)); + elk_MOV(p, + retype(elk_message_reg(inst->base_mrf + 2), ELK_REGISTER_TYPE_D), + retype(src, ELK_REGISTER_TYPE_D)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); uint32_t msg_type; @@ -1222,9 +1222,9 @@ generate_scratch_write(struct brw_codegen *p, else if (devinfo->ver == 6) msg_type = GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; else - msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; + msg_type = ELK_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; - brw_set_default_predicate_control(p, inst->predicate); + elk_set_default_predicate_control(p, inst->predicate); /* Pre-gfx6, we have to specify write commits to ensure ordering * between reads and writes within a thread. Afterwards, that's @@ -1248,53 +1248,53 @@ generate_scratch_write(struct brw_codegen *p, /* Each of the 8 channel enables is considered for whether each * dword is written. */ - brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); - brw_inst_set_sfid(p->devinfo, send, target_cache); - brw_set_dest(p, send, dst); - brw_set_src0(p, send, header); + elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND); + elk_inst_set_sfid(p->devinfo, send, target_cache); + elk_set_dest(p, send, dst); + elk_set_src0(p, send, header); if (devinfo->ver < 6) - brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf); - brw_set_desc(p, send, - brw_message_desc(devinfo, 3, write_commit, true) | - brw_dp_write_desc(devinfo, - brw_scratch_surface_idx(p), - BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, + elk_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf); + elk_set_desc(p, send, + elk_message_desc(devinfo, 3, write_commit, true) | + elk_dp_write_desc(devinfo, + elk_scratch_surface_idx(p), + ELK_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, msg_type, write_commit)); } static void -generate_pull_constant_load(struct brw_codegen *p, +generate_pull_constant_load(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg index, - struct brw_reg offset) + struct elk_reg dst, + struct elk_reg index, + struct elk_reg offset) { const struct intel_device_info *devinfo = p->devinfo; const unsigned target_cache = (devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_SAMPLER_CACHE : - BRW_SFID_DATAPORT_READ); - assert(index.file == BRW_IMMEDIATE_VALUE && - index.type == BRW_REGISTER_TYPE_UD); + ELK_SFID_DATAPORT_READ); + assert(index.file == ELK_IMMEDIATE_VALUE && + index.type == ELK_REGISTER_TYPE_UD); uint32_t surf_index = index.ud; - struct brw_reg header = brw_vec8_grf(0, 0); + struct elk_reg header = elk_vec8_grf(0, 0); - gfx6_resolve_implied_move(p, &header, inst->base_mrf); + elk_gfx6_resolve_implied_move(p, &header, inst->base_mrf); if (devinfo->ver >= 6) { - if (offset.file == BRW_IMMEDIATE_VALUE) { - brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), - BRW_REGISTER_TYPE_D), - brw_imm_d(offset.ud >> 4)); + if (offset.file == ELK_IMMEDIATE_VALUE) { + elk_MOV(p, retype(elk_message_reg(inst->base_mrf + 1), + ELK_REGISTER_TYPE_D), + elk_imm_d(offset.ud >> 4)); } else { - brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1), - BRW_REGISTER_TYPE_D), - offset, brw_imm_d(4)); + elk_SHR(p, retype(elk_message_reg(inst->base_mrf + 1), + ELK_REGISTER_TYPE_D), + offset, elk_imm_d(4)); } } else { - brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), - BRW_REGISTER_TYPE_D), + elk_MOV(p, retype(elk_message_reg(inst->base_mrf + 1), + ELK_REGISTER_TYPE_D), offset); } @@ -1305,37 +1305,37 @@ generate_pull_constant_load(struct brw_codegen *p, else if (devinfo->verx10 >= 45) msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; else - msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; + msg_type = ELK_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; /* Each of the 8 channel enables is considered for whether each * dword is written. */ - brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); - brw_inst_set_sfid(devinfo, send, target_cache); - brw_set_dest(p, send, dst); - brw_set_src0(p, send, header); + elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND); + elk_inst_set_sfid(devinfo, send, target_cache); + elk_set_dest(p, send, dst); + elk_set_src0(p, send, header); if (devinfo->ver < 6) - brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf); - brw_set_desc(p, send, - brw_message_desc(devinfo, 2, 1, true) | - brw_dp_read_desc(devinfo, surf_index, - BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, + elk_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf); + elk_set_desc(p, send, + elk_message_desc(devinfo, 2, 1, true) | + elk_dp_read_desc(devinfo, surf_index, + ELK_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, msg_type, - BRW_DATAPORT_READ_TARGET_DATA_CACHE)); + ELK_DATAPORT_READ_TARGET_DATA_CACHE)); } static void -generate_get_buffer_size(struct brw_codegen *p, +generate_get_buffer_size(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg surf_index) + struct elk_reg dst, + struct elk_reg src, + struct elk_reg surf_index) { assert(p->devinfo->ver >= 7); - assert(surf_index.type == BRW_REGISTER_TYPE_UD && - surf_index.file == BRW_IMMEDIATE_VALUE); + assert(surf_index.type == ELK_REGISTER_TYPE_UD && + surf_index.file == ELK_IMMEDIATE_VALUE); - brw_SAMPLE(p, + elk_SAMPLE(p, dst, inst->base_mrf, src, @@ -1345,70 +1345,70 @@ generate_get_buffer_size(struct brw_codegen *p, 1, /* response length */ inst->mlen, inst->header_size > 0, - BRW_SAMPLER_SIMD_MODE_SIMD4X2, - BRW_SAMPLER_RETURN_FORMAT_SINT32); + ELK_SAMPLER_SIMD_MODE_SIMD4X2, + ELK_SAMPLER_RETURN_FORMAT_SINT32); } static void -generate_pull_constant_load_gfx7(struct brw_codegen *p, +generate_pull_constant_load_gfx7(struct elk_codegen *p, vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg surf_index, - struct brw_reg offset) + struct elk_reg dst, + struct elk_reg surf_index, + struct elk_reg offset) { const struct intel_device_info *devinfo = p->devinfo; - assert(surf_index.type == BRW_REGISTER_TYPE_UD); + assert(surf_index.type == ELK_REGISTER_TYPE_UD); - if (surf_index.file == BRW_IMMEDIATE_VALUE) { + if (surf_index.file == ELK_IMMEDIATE_VALUE) { - brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND); - brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER); - brw_set_dest(p, insn, dst); - brw_set_src0(p, insn, offset); - brw_set_desc(p, insn, - brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) | - brw_sampler_desc(devinfo, surf_index.ud, + elk_inst *insn = elk_next_insn(p, ELK_OPCODE_SEND); + elk_inst_set_sfid(devinfo, insn, ELK_SFID_SAMPLER); + elk_set_dest(p, insn, dst); + elk_set_src0(p, insn, offset); + elk_set_desc(p, insn, + elk_message_desc(devinfo, inst->mlen, 1, inst->header_size) | + elk_sampler_desc(devinfo, surf_index.ud, 0, /* LD message ignores sampler unit */ GFX5_SAMPLER_MESSAGE_SAMPLE_LD, - BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0)); + ELK_SAMPLER_SIMD_MODE_SIMD4X2, 0)); } else { - struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD)); + struct elk_reg addr = vec1(retype(elk_address_reg(0), ELK_REGISTER_TYPE_UD)); - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_push_insn_state(p); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); + elk_set_default_access_mode(p, ELK_ALIGN_1); /* a0.0 = surf_index & 0xff */ - brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND); - brw_inst_set_exec_size(devinfo, insn_and, BRW_EXECUTE_1); - brw_set_dest(p, insn_and, addr); - brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD))); - brw_set_src1(p, insn_and, brw_imm_ud(0x0ff)); + elk_inst *insn_and = elk_next_insn(p, ELK_OPCODE_AND); + elk_inst_set_exec_size(devinfo, insn_and, ELK_EXECUTE_1); + elk_set_dest(p, insn_and, addr); + elk_set_src0(p, insn_and, vec1(retype(surf_index, ELK_REGISTER_TYPE_UD))); + elk_set_src1(p, insn_and, elk_imm_ud(0x0ff)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); /* dst = send(offset, a0.0 | ) */ - brw_send_indirect_message( - p, BRW_SFID_SAMPLER, dst, offset, addr, - brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) | - brw_sampler_desc(devinfo, + elk_send_indirect_message( + p, ELK_SFID_SAMPLER, dst, offset, addr, + elk_message_desc(devinfo, inst->mlen, 1, inst->header_size) | + elk_sampler_desc(devinfo, 0 /* surface */, 0 /* sampler */, GFX5_SAMPLER_MESSAGE_SAMPLE_LD, - BRW_SAMPLER_SIMD_MODE_SIMD4X2, + ELK_SAMPLER_SIMD_MODE_SIMD4X2, 0), false /* EOT */); } } static void -generate_mov_indirect(struct brw_codegen *p, +generate_mov_indirect(struct elk_codegen *p, vec4_instruction *, - struct brw_reg dst, struct brw_reg reg, - struct brw_reg indirect) + struct elk_reg dst, struct elk_reg reg, + struct elk_reg indirect) { - assert(indirect.type == BRW_REGISTER_TYPE_UD); + assert(indirect.type == ELK_REGISTER_TYPE_UD); assert(p->devinfo->ver >= 6); unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2); @@ -1416,120 +1416,120 @@ generate_mov_indirect(struct brw_codegen *p, /* This instruction acts in align1 mode */ assert(dst.writemask == WRITEMASK_XYZW); - if (indirect.file == BRW_IMMEDIATE_VALUE) { + if (indirect.file == ELK_IMMEDIATE_VALUE) { imm_byte_offset += indirect.ud; reg.nr = imm_byte_offset / REG_SIZE; reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2; unsigned shift = (imm_byte_offset / 4) % 4; - reg.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift); + reg.swizzle += ELK_SWIZZLE4(shift, shift, shift, shift); - brw_MOV(p, dst, reg); + elk_MOV(p, dst, reg); } else { - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); - struct brw_reg addr = vec8(brw_address_reg(0)); + struct elk_reg addr = vec8(elk_address_reg(0)); /* We need to move the indirect value into the address register. In * order to make things make some sense, we want to respect at least the * X component of the swizzle. In order to do that, we need to convert * the subnr (probably 0) to an align1 subnr and add in the swizzle. */ - assert(brw_is_single_value_swizzle(indirect.swizzle)); - indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0)); + assert(elk_is_single_value_swizzle(indirect.swizzle)); + indirect.subnr = (indirect.subnr * 4 + ELK_GET_SWZ(indirect.swizzle, 0)); /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of * the indirect and splat it out to all four channels of the given half * of a0. */ indirect.subnr *= 2; - indirect = stride(retype(indirect, BRW_REGISTER_TYPE_UW), 8, 4, 0); - brw_ADD(p, addr, indirect, brw_imm_uw(imm_byte_offset)); + indirect = stride(retype(indirect, ELK_REGISTER_TYPE_UW), 8, 4, 0); + elk_ADD(p, addr, indirect, elk_imm_uw(imm_byte_offset)); /* Now we need to incorporate the swizzle from the source register */ - if (reg.swizzle != BRW_SWIZZLE_XXXX) { - uint32_t uv_swiz = BRW_GET_SWZ(reg.swizzle, 0) << 2 | - BRW_GET_SWZ(reg.swizzle, 1) << 6 | - BRW_GET_SWZ(reg.swizzle, 2) << 10 | - BRW_GET_SWZ(reg.swizzle, 3) << 14; + if (reg.swizzle != ELK_SWIZZLE_XXXX) { + uint32_t uv_swiz = ELK_GET_SWZ(reg.swizzle, 0) << 2 | + ELK_GET_SWZ(reg.swizzle, 1) << 6 | + ELK_GET_SWZ(reg.swizzle, 2) << 10 | + ELK_GET_SWZ(reg.swizzle, 3) << 14; uv_swiz |= uv_swiz << 16; - brw_ADD(p, addr, addr, brw_imm_uv(uv_swiz)); + elk_ADD(p, addr, addr, elk_imm_uv(uv_swiz)); } - brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), reg.type)); + elk_MOV(p, dst, retype(elk_VxH_indirect(0, 0), reg.type)); - brw_pop_insn_state(p); + elk_pop_insn_state(p); } } static void -generate_zero_oob_push_regs(struct brw_codegen *p, - struct brw_stage_prog_data *prog_data, - struct brw_reg scratch, - struct brw_reg bit_mask_in) +generate_zero_oob_push_regs(struct elk_codegen *p, + struct elk_stage_prog_data *prog_data, + struct elk_reg scratch, + struct elk_reg bit_mask_in) { const uint64_t want_zero = prog_data->zero_push_reg; assert(want_zero); - assert(bit_mask_in.file == BRW_GENERAL_REGISTER_FILE); - assert(BRW_GET_SWZ(bit_mask_in.swizzle, 1) == - BRW_GET_SWZ(bit_mask_in.swizzle, 0) + 1); - bit_mask_in.subnr += BRW_GET_SWZ(bit_mask_in.swizzle, 0) * 4; - bit_mask_in.type = BRW_REGISTER_TYPE_W; + assert(bit_mask_in.file == ELK_GENERAL_REGISTER_FILE); + assert(ELK_GET_SWZ(bit_mask_in.swizzle, 1) == + ELK_GET_SWZ(bit_mask_in.swizzle, 0) + 1); + bit_mask_in.subnr += ELK_GET_SWZ(bit_mask_in.swizzle, 0) * 4; + bit_mask_in.type = ELK_REGISTER_TYPE_W; /* Scratch should be 3 registers in the GRF */ - assert(scratch.file == BRW_GENERAL_REGISTER_FILE); + assert(scratch.file == ELK_GENERAL_REGISTER_FILE); scratch = vec8(scratch); - struct brw_reg mask_w16 = retype(scratch, BRW_REGISTER_TYPE_W); - struct brw_reg mask_d16 = retype(byte_offset(scratch, REG_SIZE), - BRW_REGISTER_TYPE_D); + struct elk_reg mask_w16 = retype(scratch, ELK_REGISTER_TYPE_W); + struct elk_reg mask_d16 = retype(byte_offset(scratch, REG_SIZE), + ELK_REGISTER_TYPE_D); - brw_push_insn_state(p); - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); + elk_push_insn_state(p); + elk_set_default_access_mode(p, ELK_ALIGN_1); + elk_set_default_mask_control(p, ELK_MASK_DISABLE); for (unsigned i = 0; i < 64; i++) { if (i % 16 == 0 && (want_zero & BITFIELD64_RANGE(i, 16))) { - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_SHL(p, suboffset(mask_w16, 8), + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_SHL(p, suboffset(mask_w16, 8), vec1(byte_offset(bit_mask_in, i / 8)), - brw_imm_v(0x01234567)); - brw_SHL(p, mask_w16, suboffset(mask_w16, 8), brw_imm_w(8)); + elk_imm_v(0x01234567)); + elk_SHL(p, mask_w16, suboffset(mask_w16, 8), elk_imm_w(8)); - brw_set_default_exec_size(p, BRW_EXECUTE_16); - brw_ASR(p, mask_d16, mask_w16, brw_imm_w(15)); + elk_set_default_exec_size(p, ELK_EXECUTE_16); + elk_ASR(p, mask_d16, mask_w16, elk_imm_w(15)); } if (want_zero & BITFIELD64_BIT(i)) { unsigned push_start = prog_data->dispatch_grf_start_reg; - struct brw_reg push_reg = - retype(brw_vec8_grf(push_start + i, 0), BRW_REGISTER_TYPE_D); + struct elk_reg push_reg = + retype(elk_vec8_grf(push_start + i, 0), ELK_REGISTER_TYPE_D); - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_AND(p, push_reg, push_reg, vec1(suboffset(mask_d16, i))); + elk_set_default_exec_size(p, ELK_EXECUTE_8); + elk_AND(p, push_reg, push_reg, vec1(suboffset(mask_d16, i))); } } - brw_pop_insn_state(p); + elk_pop_insn_state(p); } static void -generate_code(struct brw_codegen *p, - const struct brw_compiler *compiler, - const struct brw_compile_params *params, +generate_code(struct elk_codegen *p, + const struct elk_compiler *compiler, + const struct elk_compile_params *params, const nir_shader *nir, - struct brw_vue_prog_data *prog_data, - const struct cfg_t *cfg, + struct elk_vue_prog_data *prog_data, + const struct elk_cfg_t *cfg, const performance &perf, - struct brw_compile_stats *stats, + struct elk_compile_stats *stats, bool debug_enabled) { const struct intel_device_info *devinfo = p->devinfo; const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage); - struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg); + struct elk_disasm_info *elk_disasm_info = elk_disasm_initialize(p->isa, cfg); /* `send_count` explicitly does not include spills or fills, as we'd * like to use it as a metric for intentional memory access or other @@ -1541,22 +1541,22 @@ generate_code(struct brw_codegen *p, int loop_count = 0, send_count = 0; foreach_block_and_inst (block, vec4_instruction, inst, cfg) { - struct brw_reg src[3], dst; + struct elk_reg src[3], dst; if (unlikely(debug_enabled)) - disasm_annotate(disasm_info, inst, p->next_insn_offset); + elk_disasm_annotate(elk_disasm_info, inst, p->next_insn_offset); for (unsigned int i = 0; i < 3; i++) { - src[i] = inst->src[i].as_brw_reg(); + src[i] = inst->src[i].as_elk_reg(); } - dst = inst->dst.as_brw_reg(); + dst = inst->dst.as_elk_reg(); - brw_set_default_predicate_control(p, inst->predicate); - brw_set_default_predicate_inverse(p, inst->predicate_inverse); - brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2); - brw_set_default_saturate(p, inst->saturate); - brw_set_default_mask_control(p, inst->force_writemask_all); - brw_set_default_acc_write_control(p, inst->writes_accumulator); + elk_set_default_predicate_control(p, inst->predicate); + elk_set_default_predicate_inverse(p, inst->predicate_inverse); + elk_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2); + elk_set_default_saturate(p, inst->saturate); + elk_set_default_mask_control(p, inst->force_writemask_all); + elk_set_default_acc_write_control(p, inst->writes_accumulator); assert(inst->group % inst->exec_size == 0); assert(inst->group % 4 == 0); @@ -1566,232 +1566,232 @@ generate_code(struct brw_codegen *p, * double the exec_size. */ const bool is_df = (get_exec_type_size(inst) == 8 || - inst->dst.type == BRW_REGISTER_TYPE_DF) && - inst->opcode != VEC4_OPCODE_PICK_LOW_32BIT && - inst->opcode != VEC4_OPCODE_PICK_HIGH_32BIT && - inst->opcode != VEC4_OPCODE_SET_LOW_32BIT && - inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT; + inst->dst.type == ELK_REGISTER_TYPE_DF) && + inst->opcode != ELK_VEC4_OPCODE_PICK_LOW_32BIT && + inst->opcode != ELK_VEC4_OPCODE_PICK_HIGH_32BIT && + inst->opcode != ELK_VEC4_OPCODE_SET_LOW_32BIT && + inst->opcode != ELK_VEC4_OPCODE_SET_HIGH_32BIT; unsigned exec_size = inst->exec_size; if (devinfo->verx10 == 70 && is_df) exec_size *= 2; - brw_set_default_exec_size(p, cvt(exec_size) - 1); + elk_set_default_exec_size(p, cvt(exec_size) - 1); if (!inst->force_writemask_all) - brw_set_default_group(p, inst->group); + elk_set_default_group(p, inst->group); - assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->ver)); - assert(inst->mlen <= BRW_MAX_MSG_LENGTH); + assert(inst->base_mrf + inst->mlen <= ELK_MAX_MRF(devinfo->ver)); + assert(inst->mlen <= ELK_MAX_MSG_LENGTH); unsigned pre_emit_nr_insn = p->nr_insn; switch (inst->opcode) { - case VEC4_OPCODE_UNPACK_UNIFORM: - case BRW_OPCODE_MOV: - case VEC4_OPCODE_MOV_FOR_SCRATCH: - brw_MOV(p, dst, src[0]); + case ELK_VEC4_OPCODE_UNPACK_UNIFORM: + case ELK_OPCODE_MOV: + case ELK_VEC4_OPCODE_MOV_FOR_SCRATCH: + elk_MOV(p, dst, src[0]); break; - case BRW_OPCODE_ADD: - brw_ADD(p, dst, src[0], src[1]); + case ELK_OPCODE_ADD: + elk_ADD(p, dst, src[0], src[1]); break; - case BRW_OPCODE_MUL: - brw_MUL(p, dst, src[0], src[1]); + case ELK_OPCODE_MUL: + elk_MUL(p, dst, src[0], src[1]); break; - case BRW_OPCODE_MACH: - brw_MACH(p, dst, src[0], src[1]); + case ELK_OPCODE_MACH: + elk_MACH(p, dst, src[0], src[1]); break; - case BRW_OPCODE_MAD: + case ELK_OPCODE_MAD: assert(devinfo->ver >= 6); - brw_MAD(p, dst, src[0], src[1], src[2]); + elk_MAD(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_FRC: - brw_FRC(p, dst, src[0]); + case ELK_OPCODE_FRC: + elk_FRC(p, dst, src[0]); break; - case BRW_OPCODE_RNDD: - brw_RNDD(p, dst, src[0]); + case ELK_OPCODE_RNDD: + elk_RNDD(p, dst, src[0]); break; - case BRW_OPCODE_RNDE: - brw_RNDE(p, dst, src[0]); + case ELK_OPCODE_RNDE: + elk_RNDE(p, dst, src[0]); break; - case BRW_OPCODE_RNDZ: - brw_RNDZ(p, dst, src[0]); + case ELK_OPCODE_RNDZ: + elk_RNDZ(p, dst, src[0]); break; - case BRW_OPCODE_AND: - brw_AND(p, dst, src[0], src[1]); + case ELK_OPCODE_AND: + elk_AND(p, dst, src[0], src[1]); break; - case BRW_OPCODE_OR: - brw_OR(p, dst, src[0], src[1]); + case ELK_OPCODE_OR: + elk_OR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_XOR: - brw_XOR(p, dst, src[0], src[1]); + case ELK_OPCODE_XOR: + elk_XOR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_NOT: - brw_NOT(p, dst, src[0]); + case ELK_OPCODE_NOT: + elk_NOT(p, dst, src[0]); break; - case BRW_OPCODE_ASR: - brw_ASR(p, dst, src[0], src[1]); + case ELK_OPCODE_ASR: + elk_ASR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_SHR: - brw_SHR(p, dst, src[0], src[1]); + case ELK_OPCODE_SHR: + elk_SHR(p, dst, src[0], src[1]); break; - case BRW_OPCODE_SHL: - brw_SHL(p, dst, src[0], src[1]); + case ELK_OPCODE_SHL: + elk_SHL(p, dst, src[0], src[1]); break; - case BRW_OPCODE_CMP: - brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); + case ELK_OPCODE_CMP: + elk_CMP(p, dst, inst->conditional_mod, src[0], src[1]); break; - case BRW_OPCODE_CMPN: - brw_CMPN(p, dst, inst->conditional_mod, src[0], src[1]); + case ELK_OPCODE_CMPN: + elk_CMPN(p, dst, inst->conditional_mod, src[0], src[1]); break; - case BRW_OPCODE_SEL: - brw_SEL(p, dst, src[0], src[1]); + case ELK_OPCODE_SEL: + elk_SEL(p, dst, src[0], src[1]); break; - case BRW_OPCODE_DPH: - brw_DPH(p, dst, src[0], src[1]); + case ELK_OPCODE_DPH: + elk_DPH(p, dst, src[0], src[1]); break; - case BRW_OPCODE_DP4: - brw_DP4(p, dst, src[0], src[1]); + case ELK_OPCODE_DP4: + elk_DP4(p, dst, src[0], src[1]); break; - case BRW_OPCODE_DP3: - brw_DP3(p, dst, src[0], src[1]); + case ELK_OPCODE_DP3: + elk_DP3(p, dst, src[0], src[1]); break; - case BRW_OPCODE_DP2: - brw_DP2(p, dst, src[0], src[1]); + case ELK_OPCODE_DP2: + elk_DP2(p, dst, src[0], src[1]); break; - case BRW_OPCODE_F32TO16: + case ELK_OPCODE_F32TO16: assert(devinfo->ver >= 7); - brw_F32TO16(p, dst, src[0]); + elk_F32TO16(p, dst, src[0]); break; - case BRW_OPCODE_F16TO32: + case ELK_OPCODE_F16TO32: assert(devinfo->ver >= 7); - brw_F16TO32(p, dst, src[0]); + elk_F16TO32(p, dst, src[0]); break; - case BRW_OPCODE_LRP: + case ELK_OPCODE_LRP: assert(devinfo->ver >= 6); - brw_LRP(p, dst, src[0], src[1], src[2]); + elk_LRP(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_BFREV: + case ELK_OPCODE_BFREV: assert(devinfo->ver >= 7); - brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD), - retype(src[0], BRW_REGISTER_TYPE_UD)); + elk_BFREV(p, retype(dst, ELK_REGISTER_TYPE_UD), + retype(src[0], ELK_REGISTER_TYPE_UD)); break; - case BRW_OPCODE_FBH: + case ELK_OPCODE_FBH: assert(devinfo->ver >= 7); - brw_FBH(p, retype(dst, src[0].type), src[0]); + elk_FBH(p, retype(dst, src[0].type), src[0]); break; - case BRW_OPCODE_FBL: + case ELK_OPCODE_FBL: assert(devinfo->ver >= 7); - brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), - retype(src[0], BRW_REGISTER_TYPE_UD)); + elk_FBL(p, retype(dst, ELK_REGISTER_TYPE_UD), + retype(src[0], ELK_REGISTER_TYPE_UD)); break; - case BRW_OPCODE_LZD: - brw_LZD(p, dst, src[0]); + case ELK_OPCODE_LZD: + elk_LZD(p, dst, src[0]); break; - case BRW_OPCODE_CBIT: + case ELK_OPCODE_CBIT: assert(devinfo->ver >= 7); - brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), - retype(src[0], BRW_REGISTER_TYPE_UD)); + elk_CBIT(p, retype(dst, ELK_REGISTER_TYPE_UD), + retype(src[0], ELK_REGISTER_TYPE_UD)); break; - case BRW_OPCODE_ADDC: + case ELK_OPCODE_ADDC: assert(devinfo->ver >= 7); - brw_ADDC(p, dst, src[0], src[1]); + elk_ADDC(p, dst, src[0], src[1]); break; - case BRW_OPCODE_SUBB: + case ELK_OPCODE_SUBB: assert(devinfo->ver >= 7); - brw_SUBB(p, dst, src[0], src[1]); + elk_SUBB(p, dst, src[0], src[1]); break; - case BRW_OPCODE_MAC: - brw_MAC(p, dst, src[0], src[1]); + case ELK_OPCODE_MAC: + elk_MAC(p, dst, src[0], src[1]); break; - case BRW_OPCODE_BFE: + case ELK_OPCODE_BFE: assert(devinfo->ver >= 7); - brw_BFE(p, dst, src[0], src[1], src[2]); + elk_BFE(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_BFI1: + case ELK_OPCODE_BFI1: assert(devinfo->ver >= 7); - brw_BFI1(p, dst, src[0], src[1]); + elk_BFI1(p, dst, src[0], src[1]); break; - case BRW_OPCODE_BFI2: + case ELK_OPCODE_BFI2: assert(devinfo->ver >= 7); - brw_BFI2(p, dst, src[0], src[1], src[2]); + elk_BFI2(p, dst, src[0], src[1], src[2]); break; - case BRW_OPCODE_IF: + case ELK_OPCODE_IF: if (!inst->src[0].is_null()) { /* The instruction has an embedded compare (only allowed on gfx6) */ assert(devinfo->ver == 6); - gfx6_IF(p, inst->conditional_mod, src[0], src[1]); + elk_gfx6_IF(p, inst->conditional_mod, src[0], src[1]); } else { - brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8); - brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate); + elk_inst *if_inst = elk_IF(p, ELK_EXECUTE_8); + elk_inst_set_pred_control(p->devinfo, if_inst, inst->predicate); } break; - case BRW_OPCODE_ELSE: - brw_ELSE(p); + case ELK_OPCODE_ELSE: + elk_ELSE(p); break; - case BRW_OPCODE_ENDIF: - brw_ENDIF(p); + case ELK_OPCODE_ENDIF: + elk_ENDIF(p); break; - case BRW_OPCODE_DO: - brw_DO(p, BRW_EXECUTE_8); + case ELK_OPCODE_DO: + elk_DO(p, ELK_EXECUTE_8); break; - case BRW_OPCODE_BREAK: - brw_BREAK(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + case ELK_OPCODE_BREAK: + elk_BREAK(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); break; - case BRW_OPCODE_CONTINUE: - brw_CONT(p); - brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + case ELK_OPCODE_CONTINUE: + elk_CONT(p); + elk_set_default_predicate_control(p, ELK_PREDICATE_NONE); break; - case BRW_OPCODE_WHILE: - brw_WHILE(p); + case ELK_OPCODE_WHILE: + elk_WHILE(p); loop_count++; break; - case SHADER_OPCODE_RCP: - case SHADER_OPCODE_RSQ: - case SHADER_OPCODE_SQRT: - case SHADER_OPCODE_EXP2: - case SHADER_OPCODE_LOG2: - case SHADER_OPCODE_SIN: - case SHADER_OPCODE_COS: - assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); + case ELK_SHADER_OPCODE_RCP: + case ELK_SHADER_OPCODE_RSQ: + case ELK_SHADER_OPCODE_SQRT: + case ELK_SHADER_OPCODE_EXP2: + case ELK_SHADER_OPCODE_LOG2: + case ELK_SHADER_OPCODE_SIN: + case ELK_SHADER_OPCODE_COS: + assert(inst->conditional_mod == ELK_CONDITIONAL_NONE); if (devinfo->ver >= 7) { - gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], - brw_null_reg()); + elk_gfx6_math(p, dst, elk_math_function(inst->opcode), src[0], + elk_null_reg()); } else if (devinfo->ver == 6) { - generate_math_gfx6(p, inst, dst, src[0], brw_null_reg()); + generate_math_gfx6(p, inst, dst, src[0], elk_null_reg()); } else { generate_math1_gfx4(p, inst, dst, src[0]); send_count++; } break; - case SHADER_OPCODE_POW: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: - assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); + case ELK_SHADER_OPCODE_POW: + case ELK_SHADER_OPCODE_INT_QUOTIENT: + case ELK_SHADER_OPCODE_INT_REMAINDER: + assert(inst->conditional_mod == ELK_CONDITIONAL_NONE); if (devinfo->ver >= 7) { - gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]); + elk_gfx6_math(p, dst, elk_math_function(inst->opcode), src[0], src[1]); } else if (devinfo->ver == 6) { generate_math_gfx6(p, inst, dst, src[0], src[1]); } else { @@ -1800,273 +1800,273 @@ generate_code(struct brw_codegen *p, } break; - case SHADER_OPCODE_TEX: - case SHADER_OPCODE_TXD: - case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_TXF_CMS_W: - case SHADER_OPCODE_TXF_MCS: - case SHADER_OPCODE_TXL: - case SHADER_OPCODE_TXS: - case SHADER_OPCODE_TG4: - case SHADER_OPCODE_TG4_OFFSET: - case SHADER_OPCODE_SAMPLEINFO: + case ELK_SHADER_OPCODE_TEX: + case ELK_SHADER_OPCODE_TXD: + case ELK_SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS_W: + case ELK_SHADER_OPCODE_TXF_MCS: + case ELK_SHADER_OPCODE_TXL: + case ELK_SHADER_OPCODE_TXS: + case ELK_SHADER_OPCODE_TG4: + case ELK_SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_SAMPLEINFO: generate_tex(p, prog_data, nir->info.stage, inst, dst, src[0], src[1], src[2]); send_count++; break; - case SHADER_OPCODE_GET_BUFFER_SIZE: + case ELK_SHADER_OPCODE_GET_BUFFER_SIZE: generate_get_buffer_size(p, inst, dst, src[0], src[1]); send_count++; break; - case VEC4_VS_OPCODE_URB_WRITE: + case ELK_VEC4_VS_OPCODE_URB_WRITE: generate_vs_urb_write(p, inst); send_count++; break; - case SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: generate_scratch_read(p, inst, dst, src[0]); fill_count++; break; - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: generate_scratch_write(p, inst, dst, src[0], src[1]); spill_count++; break; - case VS_OPCODE_PULL_CONSTANT_LOAD: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD: generate_pull_constant_load(p, inst, dst, src[0], src[1]); send_count++; break; - case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: + case ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7: generate_pull_constant_load_gfx7(p, inst, dst, src[0], src[1]); send_count++; break; - case VEC4_GS_OPCODE_URB_WRITE: + case ELK_VEC4_GS_OPCODE_URB_WRITE: generate_gs_urb_write(p, inst); send_count++; break; - case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE: + case ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE: generate_gs_urb_write_allocate(p, inst); send_count++; break; - case GS_OPCODE_SVB_WRITE: + case ELK_GS_OPCODE_SVB_WRITE: generate_gs_svb_write(p, inst, dst, src[0], src[1]); send_count++; break; - case GS_OPCODE_SVB_SET_DST_INDEX: + case ELK_GS_OPCODE_SVB_SET_DST_INDEX: generate_gs_svb_set_destination_index(p, inst, dst, src[0]); break; - case GS_OPCODE_THREAD_END: + case ELK_GS_OPCODE_THREAD_END: generate_gs_thread_end(p, inst); send_count++; break; - case GS_OPCODE_SET_WRITE_OFFSET: + case ELK_GS_OPCODE_SET_WRITE_OFFSET: generate_gs_set_write_offset(p, dst, src[0], src[1]); break; - case GS_OPCODE_SET_VERTEX_COUNT: + case ELK_GS_OPCODE_SET_VERTEX_COUNT: generate_gs_set_vertex_count(p, dst, src[0]); break; - case GS_OPCODE_FF_SYNC: + case ELK_GS_OPCODE_FF_SYNC: generate_gs_ff_sync(p, inst, dst, src[0], src[1]); send_count++; break; - case GS_OPCODE_FF_SYNC_SET_PRIMITIVES: + case ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES: generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]); break; - case GS_OPCODE_SET_PRIMITIVE_ID: + case ELK_GS_OPCODE_SET_PRIMITIVE_ID: generate_gs_set_primitive_id(p, dst); break; - case GS_OPCODE_SET_DWORD_2: + case ELK_GS_OPCODE_SET_DWORD_2: generate_gs_set_dword_2(p, dst, src[0]); break; - case GS_OPCODE_PREPARE_CHANNEL_MASKS: + case ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS: generate_gs_prepare_channel_masks(p, dst); break; - case GS_OPCODE_SET_CHANNEL_MASKS: + case ELK_GS_OPCODE_SET_CHANNEL_MASKS: generate_gs_set_channel_masks(p, dst, src[0]); break; - case GS_OPCODE_GET_INSTANCE_ID: + case ELK_GS_OPCODE_GET_INSTANCE_ID: generate_gs_get_instance_id(p, dst); break; - case VEC4_OPCODE_UNTYPED_ATOMIC: - assert(src[2].file == BRW_IMMEDIATE_VALUE); - brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen, + case ELK_VEC4_OPCODE_UNTYPED_ATOMIC: + assert(src[2].file == ELK_IMMEDIATE_VALUE); + elk_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen, !inst->dst.is_null(), inst->header_size); send_count++; break; - case VEC4_OPCODE_UNTYPED_SURFACE_READ: + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ: assert(!inst->header_size); - assert(src[2].file == BRW_IMMEDIATE_VALUE); - brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen, + assert(src[2].file == ELK_IMMEDIATE_VALUE); + elk_untyped_surface_read(p, dst, src[0], src[1], inst->mlen, src[2].ud); send_count++; break; - case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: - assert(src[2].file == BRW_IMMEDIATE_VALUE); - brw_untyped_surface_write(p, src[0], src[1], inst->mlen, + case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE: + assert(src[2].file == ELK_IMMEDIATE_VALUE); + elk_untyped_surface_write(p, src[0], src[1], inst->mlen, src[2].ud, inst->header_size); send_count++; break; - case SHADER_OPCODE_MEMORY_FENCE: - brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND, - brw_message_target(inst->sfid), + case ELK_SHADER_OPCODE_MEMORY_FENCE: + elk_memory_fence(p, dst, src[0], ELK_OPCODE_SEND, + elk_message_target(inst->sfid), inst->desc, /* commit_enable */ false, /* bti */ 0); send_count++; break; - case SHADER_OPCODE_FIND_LIVE_CHANNEL: - brw_find_live_channel(p, dst, false); + case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL: + elk_find_live_channel(p, dst, false); break; - case SHADER_OPCODE_BROADCAST: + case ELK_SHADER_OPCODE_BROADCAST: assert(inst->force_writemask_all); - brw_broadcast(p, dst, src[0], src[1]); + elk_broadcast(p, dst, src[0], src[1]); break; - case VS_OPCODE_UNPACK_FLAGS_SIMD4X2: + case ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2: generate_unpack_flags(p, dst); break; - case VEC4_OPCODE_MOV_BYTES: { + case ELK_VEC4_OPCODE_MOV_BYTES: { /* Moves the low byte from each channel, using an Align1 access mode * and a <4,1,0> source region. */ - assert(src[0].type == BRW_REGISTER_TYPE_UB || - src[0].type == BRW_REGISTER_TYPE_B); + assert(src[0].type == ELK_REGISTER_TYPE_UB || + src[0].type == ELK_REGISTER_TYPE_B); - brw_set_default_access_mode(p, BRW_ALIGN_1); - src[0].vstride = BRW_VERTICAL_STRIDE_4; - src[0].width = BRW_WIDTH_1; - src[0].hstride = BRW_HORIZONTAL_STRIDE_0; - brw_MOV(p, dst, src[0]); - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_1); + src[0].vstride = ELK_VERTICAL_STRIDE_4; + src[0].width = ELK_WIDTH_1; + src[0].hstride = ELK_HORIZONTAL_STRIDE_0; + elk_MOV(p, dst, src[0]); + elk_set_default_access_mode(p, ELK_ALIGN_16); break; } - case VEC4_OPCODE_DOUBLE_TO_F32: - case VEC4_OPCODE_DOUBLE_TO_D32: - case VEC4_OPCODE_DOUBLE_TO_U32: { + case ELK_VEC4_OPCODE_DOUBLE_TO_F32: + case ELK_VEC4_OPCODE_DOUBLE_TO_D32: + case ELK_VEC4_OPCODE_DOUBLE_TO_U32: { assert(type_sz(src[0].type) == 8); assert(type_sz(dst.type) == 8); - brw_reg_type dst_type; + elk_reg_type dst_type; switch (inst->opcode) { - case VEC4_OPCODE_DOUBLE_TO_F32: - dst_type = BRW_REGISTER_TYPE_F; + case ELK_VEC4_OPCODE_DOUBLE_TO_F32: + dst_type = ELK_REGISTER_TYPE_F; break; - case VEC4_OPCODE_DOUBLE_TO_D32: - dst_type = BRW_REGISTER_TYPE_D; + case ELK_VEC4_OPCODE_DOUBLE_TO_D32: + dst_type = ELK_REGISTER_TYPE_D; break; - case VEC4_OPCODE_DOUBLE_TO_U32: - dst_type = BRW_REGISTER_TYPE_UD; + case ELK_VEC4_OPCODE_DOUBLE_TO_U32: + dst_type = ELK_REGISTER_TYPE_UD; break; default: unreachable("Not supported conversion"); } dst = retype(dst, dst_type); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_1); /* When converting from DF->F, we set destination's stride as 2 as an * alignment requirement. But in IVB/BYT, each DF implicitly writes * two floats, being the first one the converted value. So we don't * need to explicitly set stride 2, but 1. */ - struct brw_reg spread_dst; + struct elk_reg spread_dst; if (devinfo->verx10 == 70) spread_dst = stride(dst, 8, 4, 1); else spread_dst = stride(dst, 8, 4, 2); - brw_MOV(p, spread_dst, src[0]); + elk_MOV(p, spread_dst, src[0]); - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); break; } - case VEC4_OPCODE_TO_DOUBLE: { + case ELK_VEC4_OPCODE_TO_DOUBLE: { assert(type_sz(src[0].type) == 4); assert(type_sz(dst.type) == 8); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_1); - brw_MOV(p, dst, src[0]); + elk_MOV(p, dst, src[0]); - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); break; } - case VEC4_OPCODE_PICK_LOW_32BIT: - case VEC4_OPCODE_PICK_HIGH_32BIT: { + case ELK_VEC4_OPCODE_PICK_LOW_32BIT: + case ELK_VEC4_OPCODE_PICK_HIGH_32BIT: { /* Stores the low/high 32-bit of each 64-bit element in src[0] into * dst using ALIGN1 mode and a <8,4,2>:UD region on the source. */ assert(type_sz(src[0].type) == 8); assert(type_sz(dst.type) == 4); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_1); - dst = retype(dst, BRW_REGISTER_TYPE_UD); - dst.hstride = BRW_HORIZONTAL_STRIDE_1; + dst = retype(dst, ELK_REGISTER_TYPE_UD); + dst.hstride = ELK_HORIZONTAL_STRIDE_1; - src[0] = retype(src[0], BRW_REGISTER_TYPE_UD); - if (inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT) + src[0] = retype(src[0], ELK_REGISTER_TYPE_UD); + if (inst->opcode == ELK_VEC4_OPCODE_PICK_HIGH_32BIT) src[0] = suboffset(src[0], 1); src[0] = spread(src[0], 2); - brw_MOV(p, dst, src[0]); + elk_MOV(p, dst, src[0]); - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); break; } - case VEC4_OPCODE_SET_LOW_32BIT: - case VEC4_OPCODE_SET_HIGH_32BIT: { + case ELK_VEC4_OPCODE_SET_LOW_32BIT: + case ELK_VEC4_OPCODE_SET_HIGH_32BIT: { /* Reads consecutive 32-bit elements from src[0] and writes * them to the low/high 32-bit of each 64-bit element in dst. */ assert(type_sz(src[0].type) == 4); assert(type_sz(dst.type) == 8); - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_1); - dst = retype(dst, BRW_REGISTER_TYPE_UD); - if (inst->opcode == VEC4_OPCODE_SET_HIGH_32BIT) + dst = retype(dst, ELK_REGISTER_TYPE_UD); + if (inst->opcode == ELK_VEC4_OPCODE_SET_HIGH_32BIT) dst = suboffset(dst, 1); - dst.hstride = BRW_HORIZONTAL_STRIDE_2; + dst.hstride = ELK_HORIZONTAL_STRIDE_2; - src[0] = retype(src[0], BRW_REGISTER_TYPE_UD); - brw_MOV(p, dst, src[0]); + src[0] = retype(src[0], ELK_REGISTER_TYPE_UD); + elk_MOV(p, dst, src[0]); - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); break; } - case VEC4_OPCODE_PACK_BYTES: { + case ELK_VEC4_OPCODE_PACK_BYTES: { /* Is effectively: * * mov(8) dst<16,4,1>:UB src<4,1,0>:UB @@ -2082,118 +2082,118 @@ generate_code(struct brw_codegen *p, assert(util_is_power_of_two_nonzero(dst.writemask)); unsigned offset = __builtin_ctz(dst.writemask); - dst.type = BRW_REGISTER_TYPE_UB; + dst.type = ELK_REGISTER_TYPE_UB; - brw_set_default_access_mode(p, BRW_ALIGN_1); + elk_set_default_access_mode(p, ELK_ALIGN_1); - src[0].type = BRW_REGISTER_TYPE_UB; - src[0].vstride = BRW_VERTICAL_STRIDE_4; - src[0].width = BRW_WIDTH_1; - src[0].hstride = BRW_HORIZONTAL_STRIDE_0; + src[0].type = ELK_REGISTER_TYPE_UB; + src[0].vstride = ELK_VERTICAL_STRIDE_4; + src[0].width = ELK_WIDTH_1; + src[0].hstride = ELK_HORIZONTAL_STRIDE_0; dst.subnr = offset * 4; - struct brw_inst *insn = brw_MOV(p, dst, src[0]); - brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4); - brw_inst_set_no_dd_clear(p->devinfo, insn, true); - brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check); + struct elk_inst *insn = elk_MOV(p, dst, src[0]); + elk_inst_set_exec_size(p->devinfo, insn, ELK_EXECUTE_4); + elk_inst_set_no_dd_clear(p->devinfo, insn, true); + elk_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check); src[0].subnr = 16; dst.subnr = 16 + offset * 4; - insn = brw_MOV(p, dst, src[0]); - brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4); - brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear); - brw_inst_set_no_dd_check(p->devinfo, insn, true); + insn = elk_MOV(p, dst, src[0]); + elk_inst_set_exec_size(p->devinfo, insn, ELK_EXECUTE_4); + elk_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear); + elk_inst_set_no_dd_check(p->devinfo, insn, true); - brw_set_default_access_mode(p, BRW_ALIGN_16); + elk_set_default_access_mode(p, ELK_ALIGN_16); break; } - case VEC4_OPCODE_ZERO_OOB_PUSH_REGS: + case ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS: generate_zero_oob_push_regs(p, &prog_data->base, dst, src[0]); break; - case VEC4_TCS_OPCODE_URB_WRITE: + case ELK_VEC4_TCS_OPCODE_URB_WRITE: generate_tcs_urb_write(p, inst, src[0]); send_count++; break; - case VEC4_OPCODE_URB_READ: + case ELK_VEC4_OPCODE_URB_READ: generate_vec4_urb_read(p, inst, dst, src[0]); send_count++; break; - case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: + case ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS: generate_tcs_input_urb_offsets(p, dst, src[0], src[1]); break; - case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: + case ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: generate_tcs_output_urb_offsets(p, dst, src[0], src[1]); break; - case TCS_OPCODE_GET_INSTANCE_ID: + case ELK_TCS_OPCODE_GET_INSTANCE_ID: generate_tcs_get_instance_id(p, dst); break; - case TCS_OPCODE_GET_PRIMITIVE_ID: + case ELK_TCS_OPCODE_GET_PRIMITIVE_ID: generate_tcs_get_primitive_id(p, dst); break; - case TCS_OPCODE_CREATE_BARRIER_HEADER: + case ELK_TCS_OPCODE_CREATE_BARRIER_HEADER: generate_tcs_create_barrier_header(p, prog_data, dst); break; - case TES_OPCODE_CREATE_INPUT_READ_HEADER: + case ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER: generate_tes_create_input_read_header(p, dst); break; - case TES_OPCODE_ADD_INDIRECT_URB_OFFSET: + case ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET: generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]); break; - case TES_OPCODE_GET_PRIMITIVE_ID: + case ELK_TES_OPCODE_GET_PRIMITIVE_ID: generate_tes_get_primitive_id(p, dst); break; - case TCS_OPCODE_SRC0_010_IS_ZERO: - /* If src_reg had stride like fs_reg, we wouldn't need this. */ - brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0)); + case ELK_TCS_OPCODE_SRC0_010_IS_ZERO: + /* If src_reg had stride like elk_fs_reg, we wouldn't need this. */ + elk_MOV(p, elk_null_reg(), stride(src[0], 0, 1, 0)); break; - case TCS_OPCODE_RELEASE_INPUT: + case ELK_TCS_OPCODE_RELEASE_INPUT: generate_tcs_release_input(p, dst, src[0], src[1]); send_count++; break; - case TCS_OPCODE_THREAD_END: + case ELK_TCS_OPCODE_THREAD_END: generate_tcs_thread_end(p, inst); send_count++; break; - case SHADER_OPCODE_BARRIER: - brw_barrier(p, src[0]); - brw_WAIT(p); + case ELK_SHADER_OPCODE_BARRIER: + elk_barrier(p, src[0]); + elk_WAIT(p); send_count++; break; - case SHADER_OPCODE_MOV_INDIRECT: + case ELK_SHADER_OPCODE_MOV_INDIRECT: generate_mov_indirect(p, inst, dst, src[0], src[1]); break; - case BRW_OPCODE_DIM: + case ELK_OPCODE_DIM: assert(devinfo->verx10 == 75); - assert(src[0].type == BRW_REGISTER_TYPE_DF); - assert(dst.type == BRW_REGISTER_TYPE_DF); - brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F)); + assert(src[0].type == ELK_REGISTER_TYPE_DF); + assert(dst.type == ELK_REGISTER_TYPE_DF); + elk_DIM(p, dst, retype(src[0], ELK_REGISTER_TYPE_F)); break; - case SHADER_OPCODE_RND_MODE: { - assert(src[0].file == BRW_IMMEDIATE_VALUE); + case ELK_SHADER_OPCODE_RND_MODE: { + assert(src[0].file == ELK_IMMEDIATE_VALUE); /* * Changes the floating point rounding mode updating the control * register field defined at cr0.0[5-6] bits. */ - enum brw_rnd_mode mode = - (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT); - brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK); + enum elk_rnd_mode mode = + (enum elk_rnd_mode) (src[0].d << ELK_CR0_RND_MODE_SHIFT); + elk_float_controls_mode(p, mode, ELK_CR0_RND_MODE_MASK); } break; @@ -2201,7 +2201,7 @@ generate_code(struct brw_codegen *p, unreachable("Unsupported opcode"); } - if (inst->opcode == VEC4_OPCODE_PACK_BYTES) { + if (inst->opcode == ELK_VEC4_OPCODE_PACK_BYTES) { /* Handled dependency hints in the generator. */ assert(!inst->conditional_mod); @@ -2210,34 +2210,34 @@ generate_code(struct brw_codegen *p, !"conditional_mod, no_dd_check, or no_dd_clear set for IR " "emitting more than 1 instruction"); - brw_inst *last = &p->store[pre_emit_nr_insn]; + elk_inst *last = &p->store[pre_emit_nr_insn]; if (inst->conditional_mod) - brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod); - brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear); - brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check); + elk_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod); + elk_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear); + elk_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check); } } - brw_set_uip_jip(p, 0); + elk_set_uip_jip(p, 0); /* end of program sentinel */ - disasm_new_inst_group(disasm_info, p->next_insn_offset); + elk_disasm_new_inst_group(elk_disasm_info, p->next_insn_offset); #ifndef NDEBUG bool validated = #else if (unlikely(debug_enabled)) #endif - brw_validate_instructions(&compiler->isa, p->store, + elk_validate_instructions(&compiler->isa, p->store, 0, p->next_insn_offset, - disasm_info); + elk_disasm_info); int before_size = p->next_insn_offset; - brw_compact_instructions(p, 0, disasm_info); + elk_compact_instructions(p, 0, elk_disasm_info); int after_size = p->next_insn_offset; - bool dump_shader_bin = brw_should_dump_shader_bin(); + bool dump_shader_bin = elk_should_dump_shader_bin(); unsigned char sha1[21]; char sha1buf[41]; @@ -2247,7 +2247,7 @@ generate_code(struct brw_codegen *p, } if (unlikely(dump_shader_bin)) - brw_dump_shader_bin(p->store, 0, p->next_insn_offset, sha1buf); + elk_dump_shader_bin(p->store, 0, p->next_insn_offset, sha1buf); if (unlikely(debug_enabled)) { fprintf(stderr, "Native code for %s %s shader %s (src_hash 0x%08x) (sha1 %s):\n", @@ -2261,18 +2261,18 @@ generate_code(struct brw_codegen *p, spill_count, fill_count, send_count, before_size, after_size, 100.0f * (before_size - after_size) / before_size); - /* overriding the shader makes disasm_info invalid */ - if (!brw_try_override_assembly(p, 0, sha1buf)) { - dump_assembly(p->store, 0, p->next_insn_offset, - disasm_info, perf.block_latency); + /* overriding the shader makes elk_disasm_info invalid */ + if (!elk_try_override_assembly(p, 0, sha1buf)) { + elk_dump_assembly(p->store, 0, p->next_insn_offset, + elk_disasm_info, perf.block_latency); } else { fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf); } } - ralloc_free(disasm_info); + ralloc_free(elk_disasm_info); assert(validated); - brw_shader_debug_log(compiler, params->log_data, + elk_shader_debug_log(compiler, params->log_data, "%s vec4 shader: %d inst, %d loops, %u cycles, " "%d:%d spills:fills, %u sends, " "compacted %d to %d bytes.\n", @@ -2292,17 +2292,17 @@ generate_code(struct brw_codegen *p, } extern "C" const unsigned * -brw_vec4_generate_assembly(const struct brw_compiler *compiler, - const struct brw_compile_params *params, +elk_vec4_generate_assembly(const struct elk_compiler *compiler, + const struct elk_compile_params *params, const nir_shader *nir, - struct brw_vue_prog_data *prog_data, - const struct cfg_t *cfg, + struct elk_vue_prog_data *prog_data, + const struct elk_cfg_t *cfg, const performance &perf, bool debug_enabled) { - struct brw_codegen *p = rzalloc(params->mem_ctx, struct brw_codegen); - brw_init_codegen(&compiler->isa, p, params->mem_ctx); - brw_set_default_access_mode(p, BRW_ALIGN_16); + struct elk_codegen *p = rzalloc(params->mem_ctx, struct elk_codegen); + elk_init_codegen(&compiler->isa, p, params->mem_ctx); + elk_set_default_access_mode(p, ELK_ALIGN_16); generate_code(p, compiler, params, nir, prog_data, cfg, perf, @@ -2312,8 +2312,8 @@ brw_vec4_generate_assembly(const struct brw_compiler *compiler, if (nir->constant_data_size > 0) { prog_data->base.const_data_size = nir->constant_data_size; prog_data->base.const_data_offset = - brw_append_data(p, nir->constant_data, nir->constant_data_size, 32); + elk_append_data(p, nir->constant_data, nir->constant_data_size, 32); } - return brw_get_program(p, &prog_data->base.program_size); + return elk_get_program(p, &prog_data->base.program_size); } diff --git a/src/intel/compiler/elk/elk_vec4_gs_nir.cpp b/src/intel/compiler/elk/elk_vec4_gs_nir.cpp index 3f586997655..e9ce534467a 100644 --- a/src/intel/compiler/elk/elk_vec4_gs_nir.cpp +++ b/src/intel/compiler/elk/elk_vec4_gs_nir.cpp @@ -48,10 +48,10 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) src = src_reg(ATTR, input_array_stride * vertex + nir_intrinsic_base(instr) + offset_reg, type); - src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr)); + src.swizzle = ELK_SWZ_COMP_INPUT(nir_intrinsic_component(instr)); dest = get_nir_def(instr->def, src.type); - dest.writemask = brw_writemask_for_size(instr->num_components); + dest.writemask = elk_writemask_for_size(instr->num_components); emit(MOV(dest, src)); break; } @@ -61,33 +61,33 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) case nir_intrinsic_emit_vertex_with_counter: this->vertex_count = - retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD); + retype(get_nir_src(instr->src[0], 1), ELK_REGISTER_TYPE_UD); gs_emit_vertex(nir_intrinsic_stream_id(instr)); break; case nir_intrinsic_end_primitive_with_counter: this->vertex_count = - retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD); + retype(get_nir_src(instr->src[0], 1), ELK_REGISTER_TYPE_UD); gs_end_primitive(); break; case nir_intrinsic_set_vertex_and_primitive_count: this->vertex_count = - retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD); + retype(get_nir_src(instr->src[0], 1), ELK_REGISTER_TYPE_UD); break; case nir_intrinsic_load_primitive_id: assert(gs_prog_data->include_primitive_id); - dest = get_nir_def(instr->def, BRW_REGISTER_TYPE_D); - emit(MOV(dest, retype(brw_vec4_grf(1, 0), BRW_REGISTER_TYPE_D))); + dest = get_nir_def(instr->def, ELK_REGISTER_TYPE_D); + emit(MOV(dest, retype(elk_vec4_grf(1, 0), ELK_REGISTER_TYPE_D))); break; case nir_intrinsic_load_invocation_id: { - dest = get_nir_def(instr->def, BRW_REGISTER_TYPE_D); + dest = get_nir_def(instr->def, ELK_REGISTER_TYPE_D); if (gs_prog_data->invocations > 1) - emit(GS_OPCODE_GET_INSTANCE_ID, dest); + emit(ELK_GS_OPCODE_GET_INSTANCE_ID, dest); else - emit(MOV(dest, brw_imm_ud(0))); + emit(MOV(dest, elk_imm_ud(0))); break; } diff --git a/src/intel/compiler/elk/elk_vec4_gs_visitor.cpp b/src/intel/compiler/elk/elk_vec4_gs_visitor.cpp index 44d7240655b..7df5935d1e0 100644 --- a/src/intel/compiler/elk/elk_vec4_gs_visitor.cpp +++ b/src/intel/compiler/elk/elk_vec4_gs_visitor.cpp @@ -39,10 +39,10 @@ namespace elk { -vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - struct brw_gs_compile *c, - struct brw_gs_prog_data *prog_data, +vec4_gs_visitor::vec4_gs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + struct elk_gs_compile *c, + struct elk_gs_prog_data *prog_data, const nir_shader *shader, bool no_spills, bool debug_enabled) @@ -55,16 +55,16 @@ vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler *compiler, } -static inline struct brw_reg -attribute_to_hw_reg(int attr, brw_reg_type type, bool interleaved) +static inline struct elk_reg +attribute_to_hw_reg(int attr, elk_reg_type type, bool interleaved) { - struct brw_reg reg; + struct elk_reg reg; unsigned width = REG_SIZE / 2 / MAX2(4, type_sz(type)); if (interleaved) { - reg = stride(brw_vecn_grf(width, attr / 2, (attr % 2) * 4), 0, width, 1); + reg = stride(elk_vecn_grf(width, attr / 2, (attr % 2) * 4), 0, width, 1); } else { - reg = brw_vecn_grf(width, attr, 0); + reg = elk_vecn_grf(width, attr, 0); } reg.type = type; @@ -88,7 +88,7 @@ vec4_gs_visitor::setup_varying_inputs(int payload_reg, int attributes_per_reg) { /* For geometry shaders there are N copies of the input attributes, where N - * is the number of input vertices. attribute_map[BRW_VARYING_SLOT_COUNT * + * is the number of input vertices. attribute_map[ELK_VARYING_SLOT_COUNT * * i + j] represents attribute j for vertex i. * * Note that GS inputs are read from the VUE 256 bits (2 vec4's) at a time, @@ -108,11 +108,11 @@ vec4_gs_visitor::setup_varying_inputs(int payload_reg, int grf = payload_reg * attributes_per_reg + inst->src[i].nr + inst->src[i].offset / REG_SIZE; - struct brw_reg reg = + struct elk_reg reg = attribute_to_hw_reg(grf, inst->src[i].type, attributes_per_reg > 1); reg.swizzle = inst->src[i].swizzle; if (inst->src[i].abs) - reg = brw_abs(reg); + reg = elk_abs(reg); if (inst->src[i].negate) reg = negate(reg); @@ -166,8 +166,8 @@ vec4_gs_visitor::emit_prolog() * the shader. */ this->current_annotation = "clear r0.2"; - dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD)); - vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u)); + dst_reg r0(retype(elk_vec4_grf(0, 0), ELK_REGISTER_TYPE_UD)); + vec4_instruction *inst = emit(ELK_GS_OPCODE_SET_DWORD_2, r0, elk_imm_ud(0u)); inst->force_writemask_all = true; /* Create a virtual register to hold the vertex count */ @@ -175,7 +175,7 @@ vec4_gs_visitor::emit_prolog() /* Initialize the vertex_count register to 0 */ this->current_annotation = "initialize vertex_count"; - inst = emit(MOV(dst_reg(this->vertex_count), brw_imm_ud(0u))); + inst = emit(MOV(dst_reg(this->vertex_count), elk_imm_ud(0u))); inst->force_writemask_all = true; if (c->control_data_header_size_bits > 0) { @@ -190,7 +190,7 @@ vec4_gs_visitor::emit_prolog() */ if (c->control_data_header_size_bits <= 32) { this->current_annotation = "initialize control data bits"; - inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u))); + inst = emit(MOV(dst_reg(this->control_data_bits), elk_imm_ud(0u))); inst->force_writemask_all = true; } } @@ -218,11 +218,11 @@ vec4_gs_visitor::emit_thread_end() current_annotation = "thread end"; dst_reg mrf_reg(MRF, base_mrf); - src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + src_reg r0(retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); vec4_instruction *inst = emit(MOV(mrf_reg, r0)); inst->force_writemask_all = true; - emit(GS_OPCODE_SET_VERTEX_COUNT, mrf_reg, this->vertex_count); - inst = emit(GS_OPCODE_THREAD_END); + emit(ELK_GS_OPCODE_SET_VERTEX_COUNT, mrf_reg, this->vertex_count); + inst = emit(ELK_GS_OPCODE_THREAD_END); inst->base_mrf = base_mrf; inst->mlen = 1; } @@ -240,12 +240,12 @@ vec4_gs_visitor::emit_urb_write_header(int mrf) * values. */ dst_reg mrf_reg(MRF, mrf); - src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + src_reg r0(retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); this->current_annotation = "URB write header"; vec4_instruction *inst = emit(MOV(mrf_reg, r0)); inst->force_writemask_all = true; - emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, this->vertex_count, - brw_imm_ud(gs_prog_data->output_vertex_size_hwords)); + emit(ELK_GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, this->vertex_count, + elk_imm_ud(gs_prog_data->output_vertex_size_hwords)); } @@ -258,10 +258,10 @@ vec4_gs_visitor::emit_urb_write_opcode(bool complete) */ (void) complete; - vec4_instruction *inst = emit(VEC4_GS_OPCODE_URB_WRITE); + vec4_instruction *inst = emit(ELK_VEC4_GS_OPCODE_URB_WRITE); inst->offset = gs_prog_data->control_data_header_size_hwords; - inst->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET; + inst->urb_write_flags = ELK_URB_WRITE_PER_SLOT_OFFSET; return inst; } @@ -299,11 +299,11 @@ vec4_gs_visitor::emit_control_data_bits() * channel masking. But that's not a problem since in this case the * hardware only pays attention to the first DWORD. */ - enum brw_urb_write_flags urb_write_flags = BRW_URB_WRITE_OWORD; + enum elk_urb_write_flags urb_write_flags = ELK_URB_WRITE_OWORD; if (c->control_data_header_size_bits > 32) - urb_write_flags = urb_write_flags | BRW_URB_WRITE_USE_CHANNEL_MASKS; + urb_write_flags = urb_write_flags | ELK_URB_WRITE_USE_CHANNEL_MASKS; if (c->control_data_header_size_bits > 128) - urb_write_flags = urb_write_flags | BRW_URB_WRITE_PER_SLOT_OFFSET; + urb_write_flags = urb_write_flags | ELK_URB_WRITE_PER_SLOT_OFFSET; /* If we are using either channel masks or a per-slot offset, then we * need to figure out which DWORD we are trying to write to, using the @@ -320,11 +320,11 @@ vec4_gs_visitor::emit_control_data_bits() if (urb_write_flags) { src_reg prev_count(this, glsl_uint_type()); emit(ADD(dst_reg(prev_count), this->vertex_count, - brw_imm_ud(0xffffffffu))); + elk_imm_ud(0xffffffffu))); unsigned log2_bits_per_vertex = util_last_bit(c->control_data_bits_per_vertex); emit(SHR(dst_reg(dword_index), prev_count, - brw_imm_ud(6 - log2_bits_per_vertex))); + elk_imm_ud(6 - log2_bits_per_vertex))); } /* Start building the URB write message. The first MRF gets a copy of @@ -332,47 +332,47 @@ vec4_gs_visitor::emit_control_data_bits() */ int base_mrf = 1; dst_reg mrf_reg(MRF, base_mrf); - src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + src_reg r0(retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UD)); vec4_instruction *inst = emit(MOV(mrf_reg, r0)); inst->force_writemask_all = true; - if (urb_write_flags & BRW_URB_WRITE_PER_SLOT_OFFSET) { + if (urb_write_flags & ELK_URB_WRITE_PER_SLOT_OFFSET) { /* Set the per-slot offset to dword_index / 4, to that we'll write to * the appropriate OWORD within the control data header. */ src_reg per_slot_offset(this, glsl_uint_type()); - emit(SHR(dst_reg(per_slot_offset), dword_index, brw_imm_ud(2u))); - emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset, - brw_imm_ud(1u)); + emit(SHR(dst_reg(per_slot_offset), dword_index, elk_imm_ud(2u))); + emit(ELK_GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset, + elk_imm_ud(1u)); } - if (urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS) { + if (urb_write_flags & ELK_URB_WRITE_USE_CHANNEL_MASKS) { /* Set the channel masks to 1 << (dword_index % 4), so that we'll * write to the appropriate DWORD within the OWORD. We need to do * this computation with force_writemask_all, otherwise garbage data * from invocation 0 might clobber the mask for invocation 1 when - * GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks + * ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks * together. */ src_reg channel(this, glsl_uint_type()); - inst = emit(AND(dst_reg(channel), dword_index, brw_imm_ud(3u))); + inst = emit(AND(dst_reg(channel), dword_index, elk_imm_ud(3u))); inst->force_writemask_all = true; src_reg one(this, glsl_uint_type()); - inst = emit(MOV(dst_reg(one), brw_imm_ud(1u))); + inst = emit(MOV(dst_reg(one), elk_imm_ud(1u))); inst->force_writemask_all = true; src_reg channel_mask(this, glsl_uint_type()); inst = emit(SHL(dst_reg(channel_mask), one, channel)); inst->force_writemask_all = true; - emit(GS_OPCODE_PREPARE_CHANNEL_MASKS, dst_reg(channel_mask), + emit(ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS, dst_reg(channel_mask), channel_mask); - emit(GS_OPCODE_SET_CHANNEL_MASKS, mrf_reg, channel_mask); + emit(ELK_GS_OPCODE_SET_CHANNEL_MASKS, mrf_reg, channel_mask); } /* Store the control data bits in the message payload and send it. */ dst_reg mrf_reg2(MRF, base_mrf + 1); inst = emit(MOV(mrf_reg2, this->control_data_bits)); inst->force_writemask_all = true; - inst = emit(VEC4_GS_OPCODE_URB_WRITE); + inst = emit(ELK_VEC4_GS_OPCODE_URB_WRITE); inst->urb_write_flags = urb_write_flags; inst->base_mrf = base_mrf; inst->mlen = 2; @@ -401,11 +401,11 @@ vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id) /* reg::sid = stream_id */ src_reg sid(this, glsl_uint_type()); - emit(MOV(dst_reg(sid), brw_imm_ud(stream_id))); + emit(MOV(dst_reg(sid), elk_imm_ud(stream_id))); /* reg:shift_count = 2 * (vertex_count - 1) */ src_reg shift_count(this, glsl_uint_type()); - emit(SHL(dst_reg(shift_count), this->vertex_count, brw_imm_ud(1u))); + emit(SHL(dst_reg(shift_count), this->vertex_count, elk_imm_ud(1u))); /* Note: we're relying on the fact that the GEN SHL instruction only pays * attention to the lower 5 bits of its second source argument, so on this @@ -464,19 +464,19 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id) */ vec4_instruction *inst = emit(AND(dst_null_ud(), this->vertex_count, - brw_imm_ud(32 / c->control_data_bits_per_vertex - 1))); - inst->conditional_mod = BRW_CONDITIONAL_Z; + elk_imm_ud(32 / c->control_data_bits_per_vertex - 1))); + inst->conditional_mod = ELK_CONDITIONAL_Z; - emit(IF(BRW_PREDICATE_NORMAL)); + emit(IF(ELK_PREDICATE_NORMAL)); { /* If vertex_count is 0, then no control data bits have been * accumulated yet, so we skip emitting them. */ - emit(CMP(dst_null_ud(), this->vertex_count, brw_imm_ud(0u), - BRW_CONDITIONAL_NEQ)); - emit(IF(BRW_PREDICATE_NORMAL)); + emit(CMP(dst_null_ud(), this->vertex_count, elk_imm_ud(0u), + ELK_CONDITIONAL_NEQ)); + emit(IF(ELK_PREDICATE_NORMAL)); emit_control_data_bits(); - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); /* Reset control_data_bits to 0 so we can start accumulating a new * batch. @@ -485,10 +485,10 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id) * effect of any call to EndPrimitive() that the shader may have * made before outputting its first vertex. */ - inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u))); + inst = emit(MOV(dst_reg(this->control_data_bits), elk_imm_ud(0u))); inst->force_writemask_all = true; } - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); } this->current_annotation = "emit vertex: vertex data"; @@ -549,9 +549,9 @@ vec4_gs_visitor::gs_end_primitive() /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */ src_reg one(this, glsl_uint_type()); - emit(MOV(dst_reg(one), brw_imm_ud(1u))); + emit(MOV(dst_reg(one), elk_imm_ud(1u))); src_reg prev_count(this, glsl_uint_type()); - emit(ADD(dst_reg(prev_count), this->vertex_count, brw_imm_ud(0xffffffffu))); + emit(ADD(dst_reg(prev_count), this->vertex_count, elk_imm_ud(0xffffffffu))); src_reg mask(this, glsl_uint_type()); /* Note: we're relying on the fact that the GEN SHL instruction only pays * attention to the lower 5 bits of its second source argument, so on this @@ -582,19 +582,19 @@ static const GLuint gl_prim_to_hw_prim[MESA_PRIM_TRIANGLE_STRIP_ADJACENCY+1] = { } /* namespace elk */ extern "C" const unsigned * -brw_compile_gs(const struct brw_compiler *compiler, - struct brw_compile_gs_params *params) +elk_compile_gs(const struct elk_compiler *compiler, + struct elk_compile_gs_params *params) { nir_shader *nir = params->base.nir; - const struct brw_gs_prog_key *key = params->key; - struct brw_gs_prog_data *prog_data = params->prog_data; + const struct elk_gs_prog_key *key = params->key; + struct elk_gs_prog_data *prog_data = params->prog_data; - struct brw_gs_compile c; + struct elk_gs_compile c; memset(&c, 0, sizeof(c)); c.key = *key; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_GEOMETRY]; - const bool debug_enabled = brw_should_print_shader(nir, DEBUG_GS); + const bool debug_enabled = elk_should_print_shader(nir, DEBUG_GS); prog_data->base.base.stage = MESA_SHADER_GEOMETRY; prog_data->base.base.ray_queries = nir->info.ray_queries; @@ -609,14 +609,14 @@ brw_compile_gs(const struct brw_compiler *compiler, * locations, so we can rely on rendezvous-by-location making this work. */ GLbitfield64 inputs_read = nir->info.inputs_read; - brw_compute_vue_map(compiler->devinfo, + elk_compute_vue_map(compiler->devinfo, &c.input_vue_map, inputs_read, nir->info.separate_shader, 1); - brw_nir_apply_key(nir, compiler, &key->base, 8); - brw_nir_lower_vue_inputs(nir, &c.input_vue_map); - brw_nir_lower_vue_outputs(nir); - brw_postprocess_nir(nir, compiler, debug_enabled, + elk_nir_apply_key(nir, compiler, &key->base, 8); + elk_nir_lower_vue_inputs(nir, &c.input_vue_map); + elk_nir_lower_vue_outputs(nir); + elk_postprocess_nir(nir, compiler, debug_enabled, key->base.robust_flags); prog_data->base.clip_distance_mask = @@ -813,13 +813,13 @@ brw_compile_gs(const struct brw_compiler *compiler, */ if (unlikely(debug_enabled)) { fprintf(stderr, "GS Input "); - brw_print_vue_map(stderr, &c.input_vue_map, MESA_SHADER_GEOMETRY); + elk_print_vue_map(stderr, &c.input_vue_map, MESA_SHADER_GEOMETRY); fprintf(stderr, "GS Output "); - brw_print_vue_map(stderr, &prog_data->base.vue_map, MESA_SHADER_GEOMETRY); + elk_print_vue_map(stderr, &prog_data->base.vue_map, MESA_SHADER_GEOMETRY); } if (is_scalar) { - fs_visitor v(compiler, ¶ms->base, &c, prog_data, nir, + elk_fs_visitor v(compiler, ¶ms->base, &c, prog_data, nir, params->base.stats != NULL, debug_enabled); if (v.run_gs()) { prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8; @@ -828,7 +828,7 @@ brw_compile_gs(const struct brw_compiler *compiler, prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(compiler->devinfo); - fs_generator g(compiler, ¶ms->base, + elk_fs_generator g(compiler, ¶ms->base, &prog_data->base.base, false, MESA_SHADER_GEOMETRY); if (unlikely(debug_enabled)) { const char *label = @@ -875,7 +875,7 @@ brw_compile_gs(const struct brw_compiler *compiler, if (v.run()) { /* Success! Backup is not needed */ ralloc_free(param); - return brw_vec4_generate_assembly(compiler, ¶ms->base, + return elk_vec4_generate_assembly(compiler, ¶ms->base, nir, &prog_data->base, v.cfg, v.performance_analysis.require(), @@ -940,7 +940,7 @@ brw_compile_gs(const struct brw_compiler *compiler, params->base.error_str = ralloc_strdup(params->base.mem_ctx, gs->fail_msg); } else { - ret = brw_vec4_generate_assembly(compiler, ¶ms->base, nir, + ret = elk_vec4_generate_assembly(compiler, ¶ms->base, nir, &prog_data->base, gs->cfg, gs->performance_analysis.require(), debug_enabled); diff --git a/src/intel/compiler/elk/elk_vec4_gs_visitor.h b/src/intel/compiler/elk/elk_vec4_gs_visitor.h index 6d3682edf86..0ddb29f0199 100644 --- a/src/intel/compiler/elk/elk_vec4_gs_visitor.h +++ b/src/intel/compiler/elk/elk_vec4_gs_visitor.h @@ -40,10 +40,10 @@ namespace elk { class vec4_gs_visitor : public vec4_visitor { public: - vec4_gs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - struct brw_gs_compile *c, - struct brw_gs_prog_data *prog_data, + vec4_gs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + struct elk_gs_compile *c, + struct elk_gs_prog_data *prog_data, const nir_shader *shader, bool no_spills, bool debug_enabled); @@ -65,8 +65,8 @@ protected: src_reg vertex_count; src_reg control_data_bits; - const struct brw_gs_compile * const c; - struct brw_gs_prog_data * const gs_prog_data; + const struct elk_gs_compile * const c; + struct elk_gs_prog_data * const gs_prog_data; }; } /* namespace elk */ diff --git a/src/intel/compiler/elk/elk_vec4_live_variables.cpp b/src/intel/compiler/elk/elk_vec4_live_variables.cpp index 0df6402b777..47abda667fb 100644 --- a/src/intel/compiler/elk/elk_vec4_live_variables.cpp +++ b/src/intel/compiler/elk/elk_vec4_live_variables.cpp @@ -112,7 +112,7 @@ vec4_live_variables::setup_def_use() * things that screen off preceding definitions of a * variable, and thus qualify for being in def[]. */ - if ((!inst->predicate || inst->opcode == BRW_OPCODE_SEL) && + if ((!inst->predicate || inst->opcode == ELK_OPCODE_SEL) && !BITSET_TEST(bd->use, v)) BITSET_SET(bd->def, v); } @@ -151,7 +151,7 @@ vec4_live_variables::compute_live_variables() struct block_data *bd = &block_data[block->num]; /* Update liveout */ - foreach_list_typed(bblock_link, child_link, link, &block->children) { + foreach_list_typed(elk_bblock_link, child_link, link, &block->children) { struct block_data *child_bd = &block_data[child_link->block->num]; for (int i = 0; i < bitset_words; i++) { @@ -215,7 +215,7 @@ vec4_live_variables::compute_start_end() } } -vec4_live_variables::vec4_live_variables(const backend_shader *s) +vec4_live_variables::vec4_live_variables(const elk_backend_shader *s) : alloc(s->alloc), cfg(s->cfg) { mem_ctx = ralloc_context(NULL); @@ -270,7 +270,7 @@ check_register_live_range(const vec4_live_variables *live, int ip, } bool -vec4_live_variables::validate(const backend_shader *s) const +vec4_live_variables::validate(const elk_backend_shader *s) const { unsigned ip = 0; diff --git a/src/intel/compiler/elk/elk_vec4_live_variables.h b/src/intel/compiler/elk/elk_vec4_live_variables.h index ed806ab76f0..b764eb51814 100644 --- a/src/intel/compiler/elk/elk_vec4_live_variables.h +++ b/src/intel/compiler/elk/elk_vec4_live_variables.h @@ -32,7 +32,7 @@ #include "elk_ir_analysis.h" #include "util/bitset.h" -struct backend_shader; +struct elk_backend_shader; namespace elk { @@ -64,11 +64,11 @@ public: BITSET_WORD flag_liveout[1]; }; - vec4_live_variables(const backend_shader *s); + vec4_live_variables(const elk_backend_shader *s); ~vec4_live_variables(); bool - validate(const backend_shader *s) const; + validate(const elk_backend_shader *s) const; analysis_dependency_class dependency_class() const @@ -103,7 +103,7 @@ protected: void compute_start_end(); const simple_allocator &alloc; - cfg_t *cfg; + elk_cfg_t *cfg; void *mem_ctx; }; @@ -118,7 +118,7 @@ var_from_reg(const simple_allocator &alloc, const src_reg ®, const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4); unsigned result = 8 * alloc.offsets[reg.nr] + reg.offset / 4 + - (BRW_GET_SWZ(reg.swizzle, c) + k / csize * 4) * csize + k % csize; + (ELK_GET_SWZ(reg.swizzle, c) + k / csize * 4) * csize + k % csize; /* Do not exceed the limit for this register */ assert(result < 8 * (alloc.offsets[reg.nr] + alloc.sizes[reg.nr])); return result; diff --git a/src/intel/compiler/elk/elk_vec4_nir.cpp b/src/intel/compiler/elk/elk_vec4_nir.cpp index c7f3894360c..50da9acaf43 100644 --- a/src/intel/compiler/elk/elk_vec4_nir.cpp +++ b/src/intel/compiler/elk/elk_vec4_nir.cpp @@ -91,33 +91,33 @@ void vec4_visitor::nir_emit_if(nir_if *if_stmt) { /* First, put the condition in f0 */ - src_reg condition = get_nir_src(if_stmt->condition, BRW_REGISTER_TYPE_D, 1); + src_reg condition = get_nir_src(if_stmt->condition, ELK_REGISTER_TYPE_D, 1); vec4_instruction *inst = emit(MOV(dst_null_d(), condition)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; + inst->conditional_mod = ELK_CONDITIONAL_NZ; /* We can just predicate based on the X channel, as the condition only * goes on its own line */ - emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X)); + emit(IF(ELK_PREDICATE_ALIGN16_REPLICATE_X)); nir_emit_cf_list(&if_stmt->then_list); if (!nir_cf_list_is_empty_block(&if_stmt->else_list)) { - emit(BRW_OPCODE_ELSE); + emit(ELK_OPCODE_ELSE); nir_emit_cf_list(&if_stmt->else_list); } - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); } void vec4_visitor::nir_emit_loop(nir_loop *loop) { assert(!nir_loop_has_continue_construct(loop)); - emit(BRW_OPCODE_DO); + emit(ELK_OPCODE_DO); nir_emit_cf_list(&loop->body); - emit(BRW_OPCODE_WHILE); + emit(ELK_OPCODE_WHILE); } void @@ -170,13 +170,13 @@ dst_reg_for_nir_reg(vec4_visitor *v, nir_def *handle, nir_intrinsic_instr *decl = nir_reg_get_decl(handle); dst_reg reg = v->nir_ssa_values[handle->index]; if (nir_intrinsic_bit_size(decl) == 64) - reg.type = BRW_REGISTER_TYPE_DF; + reg.type = ELK_REGISTER_TYPE_DF; reg = offset(reg, 8, base_offset); if (indirect) { reg.reladdr = new(v->mem_ctx) src_reg(v->get_nir_src(*indirect, - BRW_REGISTER_TYPE_D, + ELK_REGISTER_TYPE_D, 1)); } return reg; @@ -190,7 +190,7 @@ vec4_visitor::get_nir_def(const nir_def &def) dst_reg dst = dst_reg(VGRF, alloc.allocate(DIV_ROUND_UP(def.bit_size, 32))); if (def.bit_size == 64) - dst.type = BRW_REGISTER_TYPE_DF; + dst.type = ELK_REGISTER_TYPE_DF; nir_ssa_values[def.index] = dst; return dst; } else { @@ -207,7 +207,7 @@ vec4_visitor::get_nir_def(const nir_def &def) } dst_reg -vec4_visitor::get_nir_def(const nir_def &def, enum brw_reg_type type) +vec4_visitor::get_nir_def(const nir_def &def, enum elk_reg_type type) { return retype(get_nir_def(def), type); } @@ -215,11 +215,11 @@ vec4_visitor::get_nir_def(const nir_def &def, enum brw_reg_type type) dst_reg vec4_visitor::get_nir_def(const nir_def &def, nir_alu_type type) { - return get_nir_def(def, brw_type_for_nir_type(devinfo, type)); + return get_nir_def(def, elk_type_for_nir_type(devinfo, type)); } src_reg -vec4_visitor::get_nir_src(const nir_src &src, enum brw_reg_type type, +vec4_visitor::get_nir_src(const nir_src &src, enum elk_reg_type type, unsigned num_components) { nir_intrinsic_instr *load_reg = nir_load_reg_for_def(src.ssa); @@ -240,7 +240,7 @@ vec4_visitor::get_nir_src(const nir_src &src, enum brw_reg_type type, reg = retype(reg, type); src_reg reg_as_src = src_reg(reg); - reg_as_src.swizzle = brw_swizzle_for_size(num_components); + reg_as_src.swizzle = elk_swizzle_for_size(num_components); return reg_as_src; } @@ -248,7 +248,7 @@ src_reg vec4_visitor::get_nir_src(const nir_src &src, nir_alu_type type, unsigned num_components) { - return get_nir_src(src, brw_type_for_nir_type(devinfo, type), + return get_nir_src(src, elk_type_for_nir_type(devinfo, type), num_components); } @@ -264,7 +264,7 @@ vec4_visitor::get_nir_src_imm(const nir_src &src) { assert(nir_src_num_components(src) == 1); assert(nir_src_bit_size(src) == 32); - return nir_src_is_const(src) ? src_reg(brw_imm_d(nir_src_as_int(src))) : + return nir_src_is_const(src) ? src_reg(elk_imm_d(nir_src_as_int(src))) : get_nir_src(src, 1); } @@ -274,7 +274,7 @@ vec4_visitor::get_indirect_offset(nir_intrinsic_instr *instr) nir_src *offset_src = nir_get_io_offset_src(instr); if (nir_src_is_const(*offset_src)) { - /* The only constant offset we should find is 0. brw_nir.c's + /* The only constant offset we should find is 0. elk_nir.c's * add_const_offset_to_base() will fold other constant offsets * into the base index. */ @@ -282,11 +282,11 @@ vec4_visitor::get_indirect_offset(nir_intrinsic_instr *instr) return src_reg(); } - return get_nir_src(*offset_src, BRW_REGISTER_TYPE_UD, 1); + return get_nir_src(*offset_src, ELK_REGISTER_TYPE_UD, 1); } static src_reg -setup_imm_df(const vec4_builder &bld, double v) +elk_setup_imm_df(const vec4_builder &bld, double v) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->ver == 7); @@ -296,9 +296,9 @@ setup_imm_df(const vec4_builder &bld, double v) */ if (devinfo->verx10 == 75) { const vec4_builder ubld = bld.exec_all(); - const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_DF); - ubld.DIM(dst, brw_imm_df(v)); - return swizzle(src_reg(dst), BRW_SWIZZLE_XXXX); + const dst_reg dst = bld.vgrf(ELK_REGISTER_TYPE_DF); + ubld.DIM(dst, elk_imm_df(v)); + return swizzle(src_reg(dst), ELK_SWIZZLE_XXXX); } /* gfx7 does not support DF immediates */ @@ -319,14 +319,14 @@ setup_imm_df(const vec4_builder &bld, double v) * XXXX so any access to the VGRF only reads the constant data in these * channels. */ - const dst_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 2); + const dst_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD, 2); for (unsigned n = 0; n < 2; n++) { const vec4_builder ubld = bld.exec_all().group(4, n); - ubld.MOV(writemask(offset(tmp, 8, n), WRITEMASK_X), brw_imm_ud(di.i1)); - ubld.MOV(writemask(offset(tmp, 8, n), WRITEMASK_Y), brw_imm_ud(di.i2)); + ubld.MOV(writemask(offset(tmp, 8, n), WRITEMASK_X), elk_imm_ud(di.i1)); + ubld.MOV(writemask(offset(tmp, 8, n), WRITEMASK_Y), elk_imm_ud(di.i2)); } - return swizzle(src_reg(retype(tmp, BRW_REGISTER_TYPE_DF)), BRW_SWIZZLE_XXXX); + return swizzle(src_reg(retype(tmp, ELK_REGISTER_TYPE_DF)), ELK_SWIZZLE_XXXX); } void @@ -336,14 +336,14 @@ vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr) if (instr->def.bit_size == 64) { reg = dst_reg(VGRF, alloc.allocate(2)); - reg.type = BRW_REGISTER_TYPE_DF; + reg.type = ELK_REGISTER_TYPE_DF; } else { reg = dst_reg(VGRF, alloc.allocate(1)); - reg.type = BRW_REGISTER_TYPE_D; + reg.type = ELK_REGISTER_TYPE_D; } const vec4_builder ibld = vec4_builder(this).at_end(); - unsigned remaining = brw_writemask_for_size(instr->def.num_components); + unsigned remaining = elk_writemask_for_size(instr->def.num_components); /* @FIXME: consider emitting vector operations to save some MOVs in * cases where the components are representable in 8 bits. @@ -366,16 +366,16 @@ vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr) reg.writemask = writemask; if (instr->def.bit_size == 64) { - emit(MOV(reg, setup_imm_df(ibld, instr->value[i].f64))); + emit(MOV(reg, elk_setup_imm_df(ibld, instr->value[i].f64))); } else { - emit(MOV(reg, brw_imm_d(instr->value[i].i32))); + emit(MOV(reg, elk_imm_d(instr->value[i].i32))); } remaining &= ~writemask; } /* Set final writemask */ - reg.writemask = brw_writemask_for_size(instr->def.num_components); + reg.writemask = elk_writemask_for_size(instr->def.num_components); nir_ssa_values[instr->def.index] = reg; } @@ -387,7 +387,7 @@ vec4_visitor::get_nir_ssbo_intrinsic_index(nir_intrinsic_instr *instr) const unsigned src = instr->intrinsic == nir_intrinsic_store_ssbo ? 1 : 0; if (nir_src_is_const(instr->src[src])) { - return brw_imm_ud(nir_src_as_uint(instr->src[src])); + return elk_imm_ud(nir_src_as_uint(instr->src[src])); } else { return emit_uniformize(get_nir_src(instr->src[src])); } @@ -409,7 +409,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) const unsigned num_regs = array_elems * DIV_ROUND_UP(bit_size, 32); dst_reg reg(VGRF, alloc.allocate(num_regs)); if (bit_size == 64) - reg.type = BRW_REGISTER_TYPE_DF; + reg.type = ELK_REGISTER_TYPE_DF; nir_ssa_values[instr->def.index] = reg; break; @@ -434,7 +434,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) src = retype(src, dest.type); /* Swizzle source based on component layout qualifier */ - src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr)); + src.swizzle = ELK_SWZ_COMP_INPUT(nir_intrinsic_component(instr)); emit(MOV(dest, src)); break; } @@ -443,7 +443,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) assert(nir_src_bit_size(instr->src[0]) == 32); unsigned store_offset = nir_src_as_uint(instr->src[1]); int varying = nir_intrinsic_base(instr) + store_offset; - src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F, + src = get_nir_src(instr->src[0], ELK_REGISTER_TYPE_F, instr->num_components); unsigned c = nir_intrinsic_component(instr); @@ -459,14 +459,14 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) dst_reg result_dst = get_nir_def(instr->def); vec4_instruction *inst = new(mem_ctx) - vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE, result_dst); + vec4_instruction(ELK_SHADER_OPCODE_GET_BUFFER_SIZE, result_dst); inst->base_mrf = 2; inst->mlen = 1; /* always at least one */ - inst->src[1] = brw_imm_ud(ssbo_index); + inst->src[1] = elk_imm_ud(ssbo_index); /* MRF for the first parameter */ - src_reg lod = brw_imm_d(0); + src_reg lod = elk_imm_d(0); int param_base = inst->base_mrf; int writemask = WRITEMASK_X; emit(MOV(dst_reg(MRF, param_base, glsl_int_type(), writemask), lod)); @@ -478,17 +478,17 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) case nir_intrinsic_store_ssbo: { assert(devinfo->ver == 7); - /* brw_nir_lower_mem_access_bit_sizes takes care of this */ + /* elk_nir_lower_mem_access_bit_sizes takes care of this */ assert(nir_src_bit_size(instr->src[0]) == 32); assert(nir_intrinsic_write_mask(instr) == (1u << instr->num_components) - 1); src_reg surf_index = get_nir_ssbo_intrinsic_index(instr); src_reg offset_reg = retype(get_nir_src_imm(instr->src[2]), - BRW_REGISTER_TYPE_UD); + ELK_REGISTER_TYPE_UD); /* Value */ - src_reg val_reg = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F, 4); + src_reg val_reg = get_nir_src(instr->src[0], ELK_REGISTER_TYPE_F, 4); /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped * writes will use SIMD8 mode. In order to hide this and keep symmetry across @@ -533,19 +533,19 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) emit_untyped_write(bld, surf_index, offset_reg, val_reg, 1 /* dims */, instr->num_components /* size */, - BRW_PREDICATE_NONE); + ELK_PREDICATE_NONE); break; } case nir_intrinsic_load_ssbo: { assert(devinfo->ver == 7); - /* brw_nir_lower_mem_access_bit_sizes takes care of this */ + /* elk_nir_lower_mem_access_bit_sizes takes care of this */ assert(instr->def.bit_size == 32); src_reg surf_index = get_nir_ssbo_intrinsic_index(instr); src_reg offset_reg = retype(get_nir_src_imm(instr->src[1]), - BRW_REGISTER_TYPE_UD); + ELK_REGISTER_TYPE_UD); /* Read the vector */ const vec4_builder bld = vec4_builder(this).at_end() @@ -553,17 +553,17 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) src_reg read_result = emit_untyped_read(bld, surf_index, offset_reg, 1 /* dims */, 4 /* size*/, - BRW_PREDICATE_NONE); + ELK_PREDICATE_NONE); dst_reg dest = get_nir_def(instr->def); read_result.type = dest.type; - read_result.swizzle = brw_swizzle_for_size(instr->num_components); + read_result.swizzle = elk_swizzle_for_size(instr->num_components); emit(MOV(dest, read_result)); break; } case nir_intrinsic_ssbo_atomic: case nir_intrinsic_ssbo_atomic_swap: - nir_emit_ssbo_atomic(lsc_op_to_legacy_atomic(lsc_aop_for_nir_intrinsic(instr)), instr); + nir_emit_ssbo_atomic(lsc_op_to_legacy_atomic(elk_lsc_aop_for_nir_intrinsic(instr)), instr); break; case nir_intrinsic_load_vertex_id: @@ -575,7 +575,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) case nir_intrinsic_load_base_instance: case nir_intrinsic_load_draw_id: case nir_intrinsic_load_invocation_id: - unreachable("should be lowered by brw_nir_lower_vs_inputs()"); + unreachable("should be lowered by elk_nir_lower_vs_inputs()"); case nir_intrinsic_load_uniform: { /* Offsets are in bytes but they should always be multiples of 4 */ @@ -603,13 +603,13 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) /* Offsets are in bytes but they should always be multiples of 4 */ assert(load_offset % 4 == 0); - src.swizzle = brw_swizzle_for_size(instr->num_components); - dest.writemask = brw_writemask_for_size(instr->num_components); + src.swizzle = elk_swizzle_for_size(instr->num_components); + dest.writemask = elk_writemask_for_size(instr->num_components); unsigned offset = load_offset + shift * type_size; src.offset = ROUND_DOWN_TO(offset, 16); shift = (offset % 16) / type_size; assert(shift + instr->num_components <= 4); - src.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift); + src.swizzle += ELK_SWIZZLE4(shift, shift, shift, shift); emit(MOV(dest, src)); } else { @@ -618,13 +618,13 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) */ assert(shift == 0); - src_reg indirect = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1); + src_reg indirect = get_nir_src(instr->src[0], ELK_REGISTER_TYPE_UD, 1); /* MOV_INDIRECT is going to stomp the whole thing anyway */ dest.writemask = WRITEMASK_XYZW; - emit(SHADER_OPCODE_MOV_INDIRECT, dest, src, - indirect, brw_imm_ud(nir_intrinsic_range(instr))); + emit(ELK_SHADER_OPCODE_MOV_INDIRECT, dest, src, + indirect, elk_imm_ud(nir_intrinsic_range(instr))); } break; } @@ -639,7 +639,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) * as an immediate. */ const unsigned index = nir_src_as_uint(instr->src[0]); - surf_index = brw_imm_ud(index); + surf_index = elk_imm_ud(index); } else { /* The block index is not a constant. Evaluate the index expression * per-channel and add the base UBO index; we have to select a value @@ -656,7 +656,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) if (nir_src_is_const(instr->src[1])) { unsigned load_offset = nir_src_as_uint(instr->src[1]); unsigned aligned_offset = load_offset & ~15; - offset_reg = brw_imm_ud(aligned_offset); + offset_reg = elk_imm_ud(aligned_offset); /* See if we've selected this as a push constant candidate */ if (nir_src_is_const(instr->src[0])) { @@ -664,7 +664,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) const unsigned offset_256b = aligned_offset / 32; for (int i = 0; i < 4; i++) { - const struct brw_ubo_range *range = &prog_data->base.ubo_ranges[i]; + const struct elk_ubo_range *range = &prog_data->base.ubo_ranges[i]; if (range->block == ubo_block && offset_256b >= range->start && offset_256b < range->start + range->length) { @@ -694,14 +694,14 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) prog_data->base.has_ubo_pull = true; } else { src_reg temp = src_reg(this, glsl_dvec4_type()); - src_reg temp_float = retype(temp, BRW_REGISTER_TYPE_F); + src_reg temp_float = retype(temp, ELK_REGISTER_TYPE_F); emit_pull_constant_load_reg(dst_reg(temp_float), surf_index, offset_reg, NULL, NULL); if (offset_reg.file == IMM) offset_reg.ud += 16; else - emit(ADD(dst_reg(offset_reg), offset_reg, brw_imm_ud(16u))); + emit(ADD(dst_reg(offset_reg), offset_reg, elk_imm_ud(16u))); emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float, REG_SIZE)), surf_index, offset_reg, NULL, NULL); prog_data->base.has_ubo_pull = true; @@ -710,12 +710,12 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) shuffle_64bit_data(dst_reg(packed_consts), temp, false); } - packed_consts.swizzle = brw_swizzle_for_size(instr->num_components); + packed_consts.swizzle = elk_swizzle_for_size(instr->num_components); if (nir_src_is_const(instr->src[1])) { unsigned load_offset = nir_src_as_uint(instr->src[1]); unsigned type_size = type_sz(dest.type); packed_consts.swizzle += - BRW_SWIZZLE4(load_offset % 16 / type_size, + ELK_SWIZZLE4(load_offset % 16 / type_size, load_offset % 16 / type_size, load_offset % 16 / type_size, load_offset % 16 / type_size); @@ -731,9 +731,9 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) break; const vec4_builder bld = vec4_builder(this).at_end().annotate(current_annotation, base_ir); - const dst_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); + const dst_reg tmp = bld.vgrf(ELK_REGISTER_TYPE_UD); vec4_instruction *fence = - bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp, brw_vec8_grf(0, 0)); + bld.emit(ELK_SHADER_OPCODE_MEMORY_FENCE, tmp, elk_vec8_grf(0, 0)); fence->sfid = GFX7_SFID_DATAPORT_DATA_CACHE; break; } @@ -741,7 +741,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) case nir_intrinsic_shader_clock: { /* We cannot do anything if there is an event, so ignore it for now */ const src_reg shader_clock = get_timestamp(); - const enum brw_reg_type type = brw_type_for_base_type(glsl_uvec2_type()); + const enum elk_reg_type type = elk_type_for_base_type(glsl_uvec2_type()); dest = get_nir_def(instr->def, type); emit(MOV(dest, shader_clock)); @@ -763,10 +763,10 @@ vec4_visitor::nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr) src_reg surface = get_nir_ssbo_intrinsic_index(instr); src_reg offset = get_nir_src(instr->src[1], 1); src_reg data1; - if (op != BRW_AOP_INC && op != BRW_AOP_DEC && op != BRW_AOP_PREDEC) + if (op != ELK_AOP_INC && op != ELK_AOP_DEC && op != ELK_AOP_PREDEC) data1 = get_nir_src(instr->src[2], 1); src_reg data2; - if (op == BRW_AOP_CMPWR) + if (op == ELK_AOP_CMPWR) data2 = get_nir_src(instr->src[3], 1); /* Emit the actual atomic operation operation */ @@ -777,20 +777,20 @@ vec4_visitor::nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr) data1, data2, 1 /* dims */, 1 /* rsize */, op, - BRW_PREDICATE_NONE); + ELK_PREDICATE_NONE); dest.type = atomic_result.type; bld.MOV(dest, atomic_result); } static unsigned -brw_swizzle_for_nir_swizzle(uint8_t swizzle[4]) +elk_swizzle_for_nir_swizzle(uint8_t swizzle[4]) { - return BRW_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]); + return ELK_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]); } bool vec4_visitor::optimize_predicate(nir_alu_instr *instr, - enum brw_predicate *predicate) + enum elk_predicate *predicate) { if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu) return false; @@ -805,7 +805,7 @@ vec4_visitor::optimize_predicate(nir_alu_instr *instr, case nir_op_b32any_inequal3: case nir_op_b32any_fnequal4: case nir_op_b32any_inequal4: - *predicate = BRW_PREDICATE_ALIGN16_ANY4H; + *predicate = ELK_PREDICATE_ALIGN16_ANY4H; break; case nir_op_b32all_fequal2: case nir_op_b32all_iequal2: @@ -813,14 +813,14 @@ vec4_visitor::optimize_predicate(nir_alu_instr *instr, case nir_op_b32all_iequal3: case nir_op_b32all_fequal4: case nir_op_b32all_iequal4: - *predicate = BRW_PREDICATE_ALIGN16_ALL4H; + *predicate = ELK_PREDICATE_ALIGN16_ALL4H; break; default: return false; } unsigned size_swizzle = - brw_swizzle_for_size(nir_op_infos[cmp_instr->op].input_sizes[0]); + elk_swizzle_for_size(nir_op_infos[cmp_instr->op].input_sizes[0]); src_reg op[2]; assert(nir_op_infos[cmp_instr->op].num_inputs == 2); @@ -830,12 +830,12 @@ vec4_visitor::optimize_predicate(nir_alu_instr *instr, type = (nir_alu_type) (((unsigned) type) | bit_size); op[i] = get_nir_src(cmp_instr->src[i].src, type, 4); unsigned base_swizzle = - brw_swizzle_for_nir_swizzle(cmp_instr->src[i].swizzle); - op[i].swizzle = brw_compose_swizzle(size_swizzle, base_swizzle); + elk_swizzle_for_nir_swizzle(cmp_instr->src[i].swizzle); + op[i].swizzle = elk_compose_swizzle(size_swizzle, base_swizzle); } emit(CMP(dst_null_d(), op[0], op[1], - brw_cmod_for_nir_comparison(cmp_instr->op))); + elk_cmod_for_nir_comparison(cmp_instr->op))); return true; } @@ -843,16 +843,16 @@ vec4_visitor::optimize_predicate(nir_alu_instr *instr, void vec4_visitor::emit_conversion_from_double(dst_reg dst, src_reg src) { - enum opcode op; + enum elk_opcode op; switch (dst.type) { - case BRW_REGISTER_TYPE_D: - op = VEC4_OPCODE_DOUBLE_TO_D32; + case ELK_REGISTER_TYPE_D: + op = ELK_VEC4_OPCODE_DOUBLE_TO_D32; break; - case BRW_REGISTER_TYPE_UD: - op = VEC4_OPCODE_DOUBLE_TO_U32; + case ELK_REGISTER_TYPE_UD: + op = ELK_VEC4_OPCODE_DOUBLE_TO_U32; break; - case BRW_REGISTER_TYPE_F: - op = VEC4_OPCODE_DOUBLE_TO_F32; + case ELK_REGISTER_TYPE_F: + op = ELK_VEC4_OPCODE_DOUBLE_TO_F32; break; default: unreachable("Unknown conversion"); @@ -863,7 +863,7 @@ vec4_visitor::emit_conversion_from_double(dst_reg dst, src_reg src) dst_reg temp2 = dst_reg(this, glsl_dvec4_type()); emit(op, temp2, src_reg(temp)); - emit(VEC4_OPCODE_PICK_LOW_32BIT, retype(temp2, dst.type), src_reg(temp2)); + emit(ELK_VEC4_OPCODE_PICK_LOW_32BIT, retype(temp2, dst.type), src_reg(temp2)); emit(MOV(dst, src_reg(retype(temp2, dst.type)))); } @@ -873,7 +873,7 @@ vec4_visitor::emit_conversion_to_double(dst_reg dst, src_reg src) dst_reg tmp_dst = dst_reg(src_reg(this, glsl_dvec4_type())); src_reg tmp_src = retype(src_reg(this, glsl_vec4_type()), src.type); emit(MOV(dst_reg(tmp_src), src)); - emit(VEC4_OPCODE_TO_DOUBLE, tmp_dst, tmp_src); + emit(ELK_VEC4_OPCODE_TO_DOUBLE, tmp_dst, tmp_src); emit(MOV(dst, src_reg(tmp_dst))); } @@ -921,11 +921,11 @@ try_immediate_source(const nir_alu_instr *instr, src_reg *op, return -1; } - const enum brw_reg_type old_type = op[idx].type; + const enum elk_reg_type old_type = op[idx].type; switch (old_type) { - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_UD: { + case ELK_REGISTER_TYPE_D: + case ELK_REGISTER_TYPE_UD: { int first_comp = -1; int d = 0; @@ -950,11 +950,11 @@ try_immediate_source(const nir_alu_instr *instr, src_reg *op, if (op[idx].negate) d = -d; - op[idx] = retype(src_reg(brw_imm_d(d)), old_type); + op[idx] = retype(src_reg(elk_imm_d(d)), old_type); break; } - case BRW_REGISTER_TYPE_F: { + case ELK_REGISTER_TYPE_F: { int first_comp = -1; float f[NIR_MAX_VEC_COMPONENTS] = { 0.0f }; bool is_scalar = true; @@ -978,7 +978,7 @@ try_immediate_source(const nir_alu_instr *instr, src_reg *op, if (op[idx].negate) f[first_comp] = -f[first_comp]; - op[idx] = src_reg(brw_imm_f(f[first_comp])); + op[idx] = src_reg(elk_imm_f(f[first_comp])); assert(op[idx].type == old_type); } else { uint8_t vf_values[4] = { 0, 0, 0, 0 }; @@ -991,14 +991,14 @@ try_immediate_source(const nir_alu_instr *instr, src_reg *op, if (op[idx].negate) f[i] = -f[i]; - const int vf = brw_float_to_vf(f[i]); + const int vf = elk_float_to_vf(f[i]); if (vf == -1) return -1; vf_values[i] = vf; } - op[idx] = src_reg(brw_imm_vf4(vf_values[0], vf_values[1], + op[idx] = src_reg(elk_imm_vf4(vf_values[0], vf_values[1], vf_values[2], vf_values[3])); } break; @@ -1065,10 +1065,10 @@ vec4_visitor::fix_float_operands(src_reg op[3], nir_alu_instr *instr) } static bool -const_src_fits_in_16_bits(const nir_src &src, brw_reg_type type) +const_src_fits_in_16_bits(const nir_src &src, elk_reg_type type) { assert(nir_src_is_const(src)); - if (brw_reg_type_is_unsigned_integer(type)) { + if (elk_reg_type_is_unsigned_integer(type)) { return nir_src_comp_as_uint(src, 0) <= UINT16_MAX; } else { const int64_t c = nir_src_comp_as_int(src, 0); @@ -1092,7 +1092,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) (nir_op_infos[instr->op].input_types[i] | nir_src_bit_size(instr->src[i].src)); op[i] = get_nir_src(instr->src[i].src, src_type, 4); - op[i].swizzle = brw_swizzle_for_nir_swizzle(instr->src[i].swizzle); + op[i].swizzle = elk_swizzle_for_nir_swizzle(instr->src[i].swizzle); } #ifndef NDEBUG @@ -1195,7 +1195,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) else emit(MUL(dst, op[0], op[1])); } else { - struct brw_reg acc = retype(brw_acc_reg(8), dst.type); + struct elk_reg acc = retype(elk_acc_reg(8), dst.type); emit(MUL(acc, op[0], op[1])); emit(MACH(dst_null_d(), op[0], op[1])); @@ -1207,7 +1207,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_imul_high: case nir_op_umul_high: { assert(instr->def.bit_size < 64); - struct brw_reg acc = retype(brw_acc_reg(8), dst.type); + struct elk_reg acc = retype(elk_acc_reg(8), dst.type); emit(MUL(acc, op[0], op[1])); emit(MACH(dst, op[0], op[1])); @@ -1215,29 +1215,29 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) } case nir_op_frcp: - inst = emit_math(SHADER_OPCODE_RCP, dst, op[0]); + inst = emit_math(ELK_SHADER_OPCODE_RCP, dst, op[0]); break; case nir_op_fexp2: - inst = emit_math(SHADER_OPCODE_EXP2, dst, op[0]); + inst = emit_math(ELK_SHADER_OPCODE_EXP2, dst, op[0]); break; case nir_op_flog2: - inst = emit_math(SHADER_OPCODE_LOG2, dst, op[0]); + inst = emit_math(ELK_SHADER_OPCODE_LOG2, dst, op[0]); break; case nir_op_fsin: - inst = emit_math(SHADER_OPCODE_SIN, dst, op[0]); + inst = emit_math(ELK_SHADER_OPCODE_SIN, dst, op[0]); break; case nir_op_fcos: - inst = emit_math(SHADER_OPCODE_COS, dst, op[0]); + inst = emit_math(ELK_SHADER_OPCODE_COS, dst, op[0]); break; case nir_op_idiv: case nir_op_udiv: assert(instr->def.bit_size < 64); - emit_math(SHADER_OPCODE_INT_QUOTIENT, dst, op[0], op[1]); + emit_math(ELK_SHADER_OPCODE_INT_QUOTIENT, dst, op[0], op[1]); break; case nir_op_umod: @@ -1247,16 +1247,16 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) * remainder. */ assert(instr->def.bit_size < 64); - emit_math(SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]); + emit_math(ELK_SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]); break; case nir_op_imod: { /* Get a regular C-style remainder. If a % b == 0, set the predicate. */ - inst = emit_math(SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]); + inst = emit_math(ELK_SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]); /* Math instructions don't support conditional mod */ inst = emit(MOV(dst_null_d(), src_reg(dst))); - inst->conditional_mod = BRW_CONDITIONAL_NZ; + inst->conditional_mod = ELK_CONDITIONAL_NZ; /* Now, we need to determine if signs of the sources are different. * When we XOR the sources, the top bit is 0 if they are the same and 1 @@ -1269,15 +1269,15 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) */ src_reg tmp = src_reg(this, glsl_ivec4_type()); inst = emit(XOR(dst_reg(tmp), op[0], op[1])); - inst->predicate = BRW_PREDICATE_NORMAL; - inst->conditional_mod = BRW_CONDITIONAL_L; + inst->predicate = ELK_PREDICATE_NORMAL; + inst->conditional_mod = ELK_CONDITIONAL_L; /* If the result of the initial remainder operation is non-zero and the * two sources have different signs, add in a copy of op[1] to get the * final integer modulus value. */ inst = emit(ADD(dst, src_reg(dst), op[1])); - inst->predicate = BRW_PREDICATE_NORMAL; + inst->predicate = ELK_PREDICATE_NORMAL; break; } @@ -1285,20 +1285,20 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) unreachable("not reached: should be handled by ldexp_to_arith()"); case nir_op_fsqrt: - inst = emit_math(SHADER_OPCODE_SQRT, dst, op[0]); + inst = emit_math(ELK_SHADER_OPCODE_SQRT, dst, op[0]); break; case nir_op_frsq: - inst = emit_math(SHADER_OPCODE_RSQ, dst, op[0]); + inst = emit_math(ELK_SHADER_OPCODE_RSQ, dst, op[0]); break; case nir_op_fpow: - inst = emit_math(SHADER_OPCODE_POW, dst, op[0], op[1]); + inst = emit_math(ELK_SHADER_OPCODE_POW, dst, op[0], op[1]); break; case nir_op_uadd_carry: { assert(instr->def.bit_size < 64); - struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD); + struct elk_reg acc = retype(elk_acc_reg(8), ELK_REGISTER_TYPE_UD); emit(ADDC(dst_null_ud(), op[0], op[1])); emit(MOV(dst, src_reg(acc))); @@ -1307,7 +1307,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_usub_borrow: { assert(instr->def.bit_size < 64); - struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD); + struct elk_reg acc = retype(elk_acc_reg(8), ELK_REGISTER_TYPE_UD); emit(SUBB(dst_null_ud(), op[0], op[1])); emit(MOV(dst, src_reg(acc))); @@ -1317,16 +1317,16 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_ftrunc: inst = emit(RNDZ(dst, op[0])); if (devinfo->ver < 6) { - inst->conditional_mod = BRW_CONDITIONAL_R; - inst = emit(ADD(dst, src_reg(dst), brw_imm_f(1.0f))); - inst->predicate = BRW_PREDICATE_NORMAL; + inst->conditional_mod = ELK_CONDITIONAL_R; + inst = emit(ADD(dst, src_reg(dst), elk_imm_f(1.0f))); + inst->predicate = ELK_PREDICATE_NORMAL; inst = emit(MOV(dst, src_reg(dst))); /* for potential saturation */ } break; case nir_op_fceil: { src_reg tmp = src_reg(this, glsl_float_type()); - tmp.swizzle = brw_swizzle_for_size(nir_src_num_components(instr->src[0].src)); + tmp.swizzle = elk_swizzle_for_size(nir_src_num_components(instr->src[0].src)); op[0].negate = !op[0].negate; emit(RNDD(dst_reg(tmp), op[0])); @@ -1346,9 +1346,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_fround_even: inst = emit(RNDE(dst, op[0])); if (devinfo->ver < 6) { - inst->conditional_mod = BRW_CONDITIONAL_R; - inst = emit(ADD(dst, src_reg(dst), brw_imm_f(1.0f))); - inst->predicate = BRW_PREDICATE_NORMAL; + inst->conditional_mod = ELK_CONDITIONAL_R; + inst = emit(ADD(dst, src_reg(dst), elk_imm_f(1.0f))); + inst->predicate = ELK_PREDICATE_NORMAL; inst = emit(MOV(dst, src_reg(dst))); /* for potential saturation */ } break; @@ -1362,18 +1362,18 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) /* Check for denormal */ src_reg abs_src0 = op[0]; abs_src0.abs = true; - emit(CMP(dst_null_f(), abs_src0, brw_imm_f(ldexpf(1.0, -14)), - BRW_CONDITIONAL_L)); + emit(CMP(dst_null_f(), abs_src0, elk_imm_f(ldexpf(1.0, -14)), + ELK_CONDITIONAL_L)); /* Get the appropriately signed zero */ - emit(AND(retype(dst_reg(zero), BRW_REGISTER_TYPE_UD), - retype(op[0], BRW_REGISTER_TYPE_UD), - brw_imm_ud(0x80000000))); + emit(AND(retype(dst_reg(zero), ELK_REGISTER_TYPE_UD), + retype(op[0], ELK_REGISTER_TYPE_UD), + elk_imm_ud(0x80000000))); /* Do the actual F32 -> F16 -> F32 conversion */ emit(F32TO16(dst_reg(tmp16), op[0])); emit(F16TO32(dst_reg(tmp32), tmp16)); /* Select that or zero based on normal status */ - inst = emit(BRW_OPCODE_SEL, dst, zero, tmp32); - inst->predicate = BRW_PREDICATE_NORMAL; + inst = emit(ELK_OPCODE_SEL, dst, zero, tmp32); + inst->predicate = ELK_PREDICATE_NORMAL; break; } @@ -1383,7 +1383,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) FALLTHROUGH; case nir_op_fmin: try_immediate_source(instr, op, true); - inst = emit_minmax(BRW_CONDITIONAL_L, dst, op[0], op[1]); + inst = emit_minmax(ELK_CONDITIONAL_L, dst, op[0], op[1]); break; case nir_op_imax: @@ -1392,7 +1392,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) FALLTHROUGH; case nir_op_fmax: try_immediate_source(instr, op, true); - inst = emit_minmax(BRW_CONDITIONAL_GE, dst, op[0], op[1]); + inst = emit_minmax(ELK_CONDITIONAL_GE, dst, op[0], op[1]); break; case nir_op_fddx: @@ -1415,15 +1415,15 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_fge32: case nir_op_feq32: case nir_op_fneu32: { - enum brw_conditional_mod conditional_mod = - brw_cmod_for_nir_comparison(instr->op); + enum elk_conditional_mod conditional_mod = + elk_cmod_for_nir_comparison(instr->op); if (nir_src_bit_size(instr->src[0].src) < 64) { /* If the order of the sources is changed due to an immediate value, * then the condition must also be changed. */ if (try_immediate_source(instr, op, true) == 0) - conditional_mod = brw_swap_cmod(conditional_mod); + conditional_mod = elk_swap_cmod(conditional_mod); emit(CMP(dst, op[0], op[1], conditional_mod)); } else { @@ -1435,7 +1435,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) dst_reg temp = dst_reg(this, glsl_dvec4_type()); emit(CMP(temp, op[0], op[1], conditional_mod)); dst_reg result = dst_reg(this, glsl_bvec4_type()); - emit(VEC4_OPCODE_PICK_LOW_32BIT, result, src_reg(temp)); + emit(ELK_VEC4_OPCODE_PICK_LOW_32BIT, result, src_reg(temp)); emit(MOV(dst, src_reg(result))); } break; @@ -1450,13 +1450,13 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_b32all_fequal3: case nir_op_b32all_fequal4: { unsigned swiz = - brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]); + elk_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]); emit(CMP(dst_null_d(), swizzle(op[0], swiz), swizzle(op[1], swiz), - brw_cmod_for_nir_comparison(instr->op))); - emit(MOV(dst, brw_imm_d(0))); - inst = emit(MOV(dst, brw_imm_d(~0))); - inst->predicate = BRW_PREDICATE_ALIGN16_ALL4H; + elk_cmod_for_nir_comparison(instr->op))); + emit(MOV(dst, elk_imm_d(0))); + inst = emit(MOV(dst, elk_imm_d(~0))); + inst->predicate = ELK_PREDICATE_ALIGN16_ALL4H; break; } @@ -1469,14 +1469,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_b32any_fnequal3: case nir_op_b32any_fnequal4: { unsigned swiz = - brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]); + elk_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]); emit(CMP(dst_null_d(), swizzle(op[0], swiz), swizzle(op[1], swiz), - brw_cmod_for_nir_comparison(instr->op))); + elk_cmod_for_nir_comparison(instr->op))); - emit(MOV(dst, brw_imm_d(0))); - inst = emit(MOV(dst, brw_imm_d(~0))); - inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H; + emit(MOV(dst, elk_imm_d(0))); + inst = emit(MOV(dst, elk_imm_d(~0))); + inst->predicate = ELK_PREDICATE_ALIGN16_ANY4H; break; } @@ -1507,7 +1507,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_b2f32: case nir_op_b2f64: if (instr->def.bit_size > 32) { - assert(dst.type == BRW_REGISTER_TYPE_DF); + assert(dst.type == ELK_REGISTER_TYPE_DF); emit_conversion_to_double(dst, negate(op[0])); } else { emit(MOV(dst, negate(op[0]))); @@ -1531,13 +1531,13 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_pack_uvec2_to_uint: { dst_reg tmp1 = dst_reg(this, glsl_uint_type()); tmp1.writemask = WRITEMASK_X; - op[0].swizzle = BRW_SWIZZLE_YYYY; - emit(SHL(tmp1, op[0], src_reg(brw_imm_ud(16u)))); + op[0].swizzle = ELK_SWIZZLE_YYYY; + emit(SHL(tmp1, op[0], src_reg(elk_imm_ud(16u)))); dst_reg tmp2 = dst_reg(this, glsl_uint_type()); tmp2.writemask = WRITEMASK_X; - op[0].swizzle = BRW_SWIZZLE_XXXX; - emit(AND(tmp2, op[0], src_reg(brw_imm_ud(0xffffu)))); + op[0].swizzle = ELK_SWIZZLE_XXXX; + emit(AND(tmp2, op[0], src_reg(elk_imm_ud(0xffffu)))); emit(OR(dst, src_reg(tmp1), src_reg(tmp2))); break; @@ -1546,18 +1546,18 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_pack_64_2x32_split: { dst_reg result = dst_reg(this, glsl_dvec4_type()); dst_reg tmp = dst_reg(this, glsl_uvec4_type()); - emit(MOV(tmp, retype(op[0], BRW_REGISTER_TYPE_UD))); - emit(VEC4_OPCODE_SET_LOW_32BIT, result, src_reg(tmp)); - emit(MOV(tmp, retype(op[1], BRW_REGISTER_TYPE_UD))); - emit(VEC4_OPCODE_SET_HIGH_32BIT, result, src_reg(tmp)); + emit(MOV(tmp, retype(op[0], ELK_REGISTER_TYPE_UD))); + emit(ELK_VEC4_OPCODE_SET_LOW_32BIT, result, src_reg(tmp)); + emit(MOV(tmp, retype(op[1], ELK_REGISTER_TYPE_UD))); + emit(ELK_VEC4_OPCODE_SET_HIGH_32BIT, result, src_reg(tmp)); emit(MOV(dst, src_reg(result))); break; } case nir_op_unpack_64_2x32_split_x: case nir_op_unpack_64_2x32_split_y: { - enum opcode oper = (instr->op == nir_op_unpack_64_2x32_split_x) ? - VEC4_OPCODE_PICK_LOW_32BIT : VEC4_OPCODE_PICK_HIGH_32BIT; + enum elk_opcode oper = (instr->op == nir_op_unpack_64_2x32_split_x) ? + ELK_VEC4_OPCODE_PICK_LOW_32BIT : ELK_VEC4_OPCODE_PICK_HIGH_32BIT; dst_reg tmp = dst_reg(this, glsl_dvec4_type()); emit(MOV(tmp, op[0])); dst_reg tmp2 = dst_reg(this, glsl_uvec4_type()); @@ -1575,7 +1575,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) * rest of components to avoid regressions. In the vec4_visitor IR code path * this is not needed because the operand has already the correct swizzle. */ - op[0].swizzle = brw_compose_swizzle(BRW_SWIZZLE_XXXX, op[0].swizzle); + op[0].swizzle = elk_compose_swizzle(ELK_SWIZZLE_XXXX, op[0].swizzle); emit_unpack_half_2x16(dst, op[0]); break; @@ -1623,17 +1623,17 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) vec4_builder bld = vec4_builder(this).at_end(); src_reg src(dst); - emit(FBH(retype(dst, BRW_REGISTER_TYPE_UD), op[0])); + emit(FBH(retype(dst, ELK_REGISTER_TYPE_UD), op[0])); /* FBH counts from the MSB side, while GLSL's findMSB() wants the count * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then * subtract the result from 31 to convert the MSB count into an LSB * count. */ - bld.CMP(dst_null_d(), src, brw_imm_d(-1), BRW_CONDITIONAL_NZ); + bld.CMP(dst_null_d(), src, elk_imm_d(-1), ELK_CONDITIONAL_NZ); - inst = bld.ADD(dst, src, brw_imm_d(31)); - inst->predicate = BRW_PREDICATE_NORMAL; + inst = bld.ADD(dst, src, elk_imm_d(31)); + inst->predicate = ELK_PREDICATE_NORMAL; inst->src[0].negate = true; break; } @@ -1688,15 +1688,15 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not * zero. */ - emit(CMP(dst_null_f(), op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ)); + emit(CMP(dst_null_f(), op[0], elk_imm_f(0.0f), ELK_CONDITIONAL_NZ)); - op[0].type = BRW_REGISTER_TYPE_UD; - dst.type = BRW_REGISTER_TYPE_UD; - emit(AND(dst, op[0], brw_imm_ud(0x80000000u))); + op[0].type = ELK_REGISTER_TYPE_UD; + dst.type = ELK_REGISTER_TYPE_UD; + emit(AND(dst, op[0], elk_imm_ud(0x80000000u))); - inst = emit(OR(dst, src_reg(dst), brw_imm_ud(0x3f800000u))); - inst->predicate = BRW_PREDICATE_NORMAL; - dst.type = BRW_REGISTER_TYPE_F; + inst = emit(OR(dst, src_reg(dst), elk_imm_ud(0x3f800000u))); + inst->predicate = ELK_PREDICATE_NORMAL; + dst.type = ELK_REGISTER_TYPE_F; } else { /* For doubles we do the same but we need to consider: * @@ -1713,22 +1713,22 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) src_reg value = op[0]; value.abs = true; inst = emit(MOV(dst_null_df(), value)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; + inst->conditional_mod = ELK_CONDITIONAL_NZ; /* AND each high 32-bit channel with 0x80000000u */ dst_reg tmp = dst_reg(this, glsl_uvec4_type()); - emit(VEC4_OPCODE_PICK_HIGH_32BIT, tmp, op[0]); - emit(AND(tmp, src_reg(tmp), brw_imm_ud(0x80000000u))); + emit(ELK_VEC4_OPCODE_PICK_HIGH_32BIT, tmp, op[0]); + emit(AND(tmp, src_reg(tmp), elk_imm_ud(0x80000000u))); /* Add 1.0 to each channel, predicated to skip the cases where the * channel's value was 0 */ - inst = emit(OR(tmp, src_reg(tmp), brw_imm_ud(0x3f800000u))); - inst->predicate = BRW_PREDICATE_NORMAL; + inst = emit(OR(tmp, src_reg(tmp), elk_imm_ud(0x3f800000u))); + inst->predicate = ELK_PREDICATE_NORMAL; /* Now convert the result from float to double */ emit_conversion_to_double(dst, retype(src_reg(tmp), - BRW_REGISTER_TYPE_F)); + ELK_REGISTER_TYPE_F)); } break; @@ -1767,49 +1767,49 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_b32csel: - enum brw_predicate predicate; + enum elk_predicate predicate; if (!optimize_predicate(instr, &predicate)) { - emit(CMP(dst_null_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ)); + emit(CMP(dst_null_d(), op[0], elk_imm_d(0), ELK_CONDITIONAL_NZ)); switch (dst.writemask) { case WRITEMASK_X: - predicate = BRW_PREDICATE_ALIGN16_REPLICATE_X; + predicate = ELK_PREDICATE_ALIGN16_REPLICATE_X; break; case WRITEMASK_Y: - predicate = BRW_PREDICATE_ALIGN16_REPLICATE_Y; + predicate = ELK_PREDICATE_ALIGN16_REPLICATE_Y; break; case WRITEMASK_Z: - predicate = BRW_PREDICATE_ALIGN16_REPLICATE_Z; + predicate = ELK_PREDICATE_ALIGN16_REPLICATE_Z; break; case WRITEMASK_W: - predicate = BRW_PREDICATE_ALIGN16_REPLICATE_W; + predicate = ELK_PREDICATE_ALIGN16_REPLICATE_W; break; default: - predicate = BRW_PREDICATE_NORMAL; + predicate = ELK_PREDICATE_NORMAL; break; } } - inst = emit(BRW_OPCODE_SEL, dst, op[1], op[2]); + inst = emit(ELK_OPCODE_SEL, dst, op[1], op[2]); inst->predicate = predicate; break; case nir_op_fdot2_replicated: try_immediate_source(instr, op, true); - inst = emit(BRW_OPCODE_DP2, dst, op[0], op[1]); + inst = emit(ELK_OPCODE_DP2, dst, op[0], op[1]); break; case nir_op_fdot3_replicated: try_immediate_source(instr, op, true); - inst = emit(BRW_OPCODE_DP3, dst, op[0], op[1]); + inst = emit(ELK_OPCODE_DP3, dst, op[0], op[1]); break; case nir_op_fdot4_replicated: try_immediate_source(instr, op, true); - inst = emit(BRW_OPCODE_DP4, dst, op[0], op[1]); + inst = emit(ELK_OPCODE_DP4, dst, op[0], op[1]); break; case nir_op_fdph_replicated: try_immediate_source(instr, op, false); - inst = emit(BRW_OPCODE_DPH, dst, op[0], op[1]); + inst = emit(ELK_OPCODE_DPH, dst, op[0], op[1]); break; case nir_op_fdiv: @@ -1830,14 +1830,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) * to sign extend the low bit to 0/~0 */ if (devinfo->ver <= 5 && - (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == - BRW_NIR_BOOLEAN_NEEDS_RESOLVE) { + (instr->instr.pass_flags & ELK_NIR_BOOLEAN_MASK) == + ELK_NIR_BOOLEAN_NEEDS_RESOLVE) { dst_reg masked = dst_reg(this, glsl_int_type()); masked.writemask = dst.writemask; - emit(AND(masked, src_reg(dst), brw_imm_d(1))); + emit(AND(masked, src_reg(dst), elk_imm_d(1))); src_reg masked_neg = src_reg(masked); masked_neg.negate = true; - emit(MOV(retype(dst, BRW_REGISTER_TYPE_D), masked_neg)); + emit(MOV(retype(dst, ELK_REGISTER_TYPE_D), masked_neg)); } } @@ -1846,11 +1846,11 @@ vec4_visitor::nir_emit_jump(nir_jump_instr *instr) { switch (instr->type) { case nir_jump_break: - emit(BRW_OPCODE_BREAK); + emit(ELK_OPCODE_BREAK); break; case nir_jump_continue: - emit(BRW_OPCODE_CONTINUE); + emit(ELK_OPCODE_CONTINUE); break; case nir_jump_return: @@ -1874,8 +1874,8 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) { unsigned texture = instr->texture_index; unsigned sampler = instr->sampler_index; - src_reg texture_reg = brw_imm_ud(texture); - src_reg sampler_reg = brw_imm_ud(sampler); + src_reg texture_reg = elk_imm_ud(texture); + src_reg sampler_reg = elk_imm_ud(sampler); src_reg coordinate; const glsl_type *coord_type = NULL; src_reg shadow_comparator; @@ -1888,7 +1888,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) /* The hardware requires a LOD for buffer textures */ if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) - lod = brw_imm_d(0); + lod = elk_imm_d(0); /* Load the texture operation sources */ uint32_t constant_offset = 0; @@ -1896,7 +1896,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) switch (instr->src[i].src_type) { case nir_tex_src_comparator: shadow_comparator = get_nir_src(instr->src[i].src, - BRW_REGISTER_TYPE_F, 1); + ELK_REGISTER_TYPE_F, 1); break; case nir_tex_src_coord: { @@ -1906,13 +1906,13 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) case nir_texop_txf: case nir_texop_txf_ms: case nir_texop_samples_identical: - coordinate = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, + coordinate = get_nir_src(instr->src[i].src, ELK_REGISTER_TYPE_D, src_size); coord_type = glsl_ivec_type(src_size); break; default: - coordinate = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_F, + coordinate = get_nir_src(instr->src[i].src, ELK_REGISTER_TYPE_F, src_size); coord_type = glsl_vec_type(src_size); break; @@ -1921,12 +1921,12 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) } case nir_tex_src_ddx: - lod = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_F, + lod = get_nir_src(instr->src[i].src, ELK_REGISTER_TYPE_F, nir_tex_instr_src_size(instr, i)); break; case nir_tex_src_ddy: - lod2 = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_F, + lod2 = get_nir_src(instr->src[i].src, ELK_REGISTER_TYPE_F, nir_tex_instr_src_size(instr, i)); break; @@ -1934,38 +1934,38 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) switch (instr->op) { case nir_texop_txs: case nir_texop_txf: - lod = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 1); + lod = get_nir_src(instr->src[i].src, ELK_REGISTER_TYPE_D, 1); break; default: - lod = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_F, 1); + lod = get_nir_src(instr->src[i].src, ELK_REGISTER_TYPE_F, 1); break; } break; case nir_tex_src_ms_index: { - sample_index = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 1); + sample_index = get_nir_src(instr->src[i].src, ELK_REGISTER_TYPE_D, 1); break; } case nir_tex_src_offset: - if (!brw_texture_offset(instr, i, &constant_offset)) { + if (!elk_texture_offset(instr, i, &constant_offset)) { offset_value = - get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2); + get_nir_src(instr->src[i].src, ELK_REGISTER_TYPE_D, 2); } break; case nir_tex_src_texture_offset: { assert(texture_reg.is_zero()); texture_reg = emit_uniformize(get_nir_src(instr->src[i].src, - BRW_REGISTER_TYPE_UD, 1)); + ELK_REGISTER_TYPE_UD, 1)); break; } case nir_tex_src_sampler_offset: { assert(sampler_reg.is_zero()); sampler_reg = emit_uniformize(get_nir_src(instr->src[i].src, - BRW_REGISTER_TYPE_UD, 1)); + ELK_REGISTER_TYPE_UD, 1)); break; } @@ -1986,7 +1986,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) if (devinfo->ver >= 7) { mcs = emit_mcs_fetch(coord_type, coordinate, texture_reg); } else { - mcs = brw_imm_ud(0u); + mcs = elk_imm_ud(0u); } } @@ -2003,25 +2003,25 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) } } - enum opcode opcode; + enum elk_opcode opcode; switch (instr->op) { - case nir_texop_tex: opcode = SHADER_OPCODE_TXL; break; - case nir_texop_txl: opcode = SHADER_OPCODE_TXL; break; - case nir_texop_txd: opcode = SHADER_OPCODE_TXD; break; - case nir_texop_txf: opcode = SHADER_OPCODE_TXF; break; - case nir_texop_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break; - case nir_texop_txs: opcode = SHADER_OPCODE_TXS; break; - case nir_texop_query_levels: opcode = SHADER_OPCODE_TXS; break; - case nir_texop_texture_samples: opcode = SHADER_OPCODE_SAMPLEINFO; break; + case nir_texop_tex: opcode = ELK_SHADER_OPCODE_TXL; break; + case nir_texop_txl: opcode = ELK_SHADER_OPCODE_TXL; break; + case nir_texop_txd: opcode = ELK_SHADER_OPCODE_TXD; break; + case nir_texop_txf: opcode = ELK_SHADER_OPCODE_TXF; break; + case nir_texop_txf_ms: opcode = ELK_SHADER_OPCODE_TXF_CMS; break; + case nir_texop_txs: opcode = ELK_SHADER_OPCODE_TXS; break; + case nir_texop_query_levels: opcode = ELK_SHADER_OPCODE_TXS; break; + case nir_texop_texture_samples: opcode = ELK_SHADER_OPCODE_SAMPLEINFO; break; case nir_texop_tg4: - opcode = offset_value.file != BAD_FILE ? SHADER_OPCODE_TG4_OFFSET - : SHADER_OPCODE_TG4; + opcode = offset_value.file != BAD_FILE ? ELK_SHADER_OPCODE_TG4_OFFSET + : ELK_SHADER_OPCODE_TG4; break; case nir_texop_samples_identical: { /* There are some challenges implementing this for vec4, and it seems * unlikely to be used anyway. For now, just return false ways. */ - emit(MOV(dest, brw_imm_ud(0u))); + emit(MOV(dest, elk_imm_ud(0u))); return; } case nir_texop_txb: @@ -2045,9 +2045,9 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) inst->header_size = (devinfo->ver < 5 || inst->offset != 0 || - opcode == SHADER_OPCODE_TG4 || - opcode == SHADER_OPCODE_TG4_OFFSET || - opcode == SHADER_OPCODE_SAMPLEINFO || + opcode == ELK_SHADER_OPCODE_TG4 || + opcode == ELK_SHADER_OPCODE_TG4_OFFSET || + opcode == ELK_SHADER_OPCODE_SAMPLEINFO || is_high_sampler(devinfo, sampler_reg)) ? 1 : 0; inst->base_mrf = 2; inst->mlen = inst->header_size; @@ -2060,11 +2060,11 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) /* MRF for the first parameter */ int param_base = inst->base_mrf + inst->header_size; - if (opcode == SHADER_OPCODE_TXS) { + if (opcode == ELK_SHADER_OPCODE_TXS) { int writemask = devinfo->ver == 4 ? WRITEMASK_W : WRITEMASK_X; emit(MOV(dst_reg(MRF, param_base, lod.type, writemask), lod)); inst->mlen++; - } else if (opcode == SHADER_OPCODE_SAMPLEINFO) { + } else if (opcode == ELK_SHADER_OPCODE_SAMPLEINFO) { inst->dst.writemask = WRITEMASK_X; } else { /* Load the coordinate */ @@ -2078,12 +2078,12 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) if (zero_mask != 0) { emit(MOV(dst_reg(MRF, param_base, coordinate.type, zero_mask), - brw_imm_d(0))); + elk_imm_d(0))); } /* Load the shadow comparator */ if (shadow_comparator.file != BAD_FILE && - opcode != SHADER_OPCODE_TXD && - opcode != SHADER_OPCODE_TG4_OFFSET) { + opcode != ELK_SHADER_OPCODE_TXD && + opcode != ELK_SHADER_OPCODE_TG4_OFFSET) { emit(MOV(dst_reg(MRF, param_base + 1, shadow_comparator.type, WRITEMASK_X), shadow_comparator)); @@ -2092,7 +2092,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) /* Load the LOD info */ switch (opcode) { - case SHADER_OPCODE_TXL: { + case ELK_SHADER_OPCODE_TXL: { int mrf, writemask; if (devinfo->ver >= 5) { mrf = param_base + 1; @@ -2111,11 +2111,11 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) break; } - case SHADER_OPCODE_TXF: + case ELK_SHADER_OPCODE_TXF: emit(MOV(dst_reg(MRF, param_base, lod.type, WRITEMASK_W), lod)); break; - case SHADER_OPCODE_TXF_CMS: + case ELK_SHADER_OPCODE_TXF_CMS: emit(MOV(dst_reg(MRF, param_base + 1, sample_index.type, WRITEMASK_X), sample_index)); if (devinfo->ver >= 7) { @@ -2123,27 +2123,27 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) * the .y channel of the second vec4 of params, so replicate .x across * the whole vec4 and then mask off everything except .y */ - mcs.swizzle = BRW_SWIZZLE_XXXX; + mcs.swizzle = ELK_SWIZZLE_XXXX; emit(MOV(dst_reg(MRF, param_base + 1, glsl_uint_type(), WRITEMASK_Y), mcs)); } inst->mlen++; break; - case SHADER_OPCODE_TXD: { - const brw_reg_type type = lod.type; + case ELK_SHADER_OPCODE_TXD: { + const elk_reg_type type = lod.type; if (devinfo->ver >= 5) { - lod.swizzle = BRW_SWIZZLE4(BRW_SWIZZLE_X,BRW_SWIZZLE_X,BRW_SWIZZLE_Y,BRW_SWIZZLE_Y); - lod2.swizzle = BRW_SWIZZLE4(BRW_SWIZZLE_X,BRW_SWIZZLE_X,BRW_SWIZZLE_Y,BRW_SWIZZLE_Y); + lod.swizzle = ELK_SWIZZLE4(ELK_SWIZZLE_X,ELK_SWIZZLE_X,ELK_SWIZZLE_Y,ELK_SWIZZLE_Y); + lod2.swizzle = ELK_SWIZZLE4(ELK_SWIZZLE_X,ELK_SWIZZLE_X,ELK_SWIZZLE_Y,ELK_SWIZZLE_Y); emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XZ), lod)); emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_YW), lod2)); inst->mlen++; if (nir_tex_instr_dest_size(instr) == 3 || shadow_comparator.file != BAD_FILE) { - lod.swizzle = BRW_SWIZZLE_ZZZZ; - lod2.swizzle = BRW_SWIZZLE_ZZZZ; + lod.swizzle = ELK_SWIZZLE_ZZZZ; + lod2.swizzle = ELK_SWIZZLE_ZZZZ; emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_X), lod)); emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_Y), lod2)); inst->mlen++; @@ -2162,7 +2162,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) break; } - case SHADER_OPCODE_TG4_OFFSET: + case ELK_SHADER_OPCODE_TG4_OFFSET: if (shadow_comparator.file != BAD_FILE) { emit(MOV(dst_reg(MRF, param_base, shadow_comparator.type, WRITEMASK_W), shadow_comparator)); @@ -2185,15 +2185,15 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) */ if (instr->op == nir_texop_txs && devinfo->ver < 7) { /* Gfx4-6 return 0 instead of 1 for single layer surfaces. */ - emit_minmax(BRW_CONDITIONAL_GE, writemask(inst->dst, WRITEMASK_Z), - src_reg(inst->dst), brw_imm_d(1)); + emit_minmax(ELK_CONDITIONAL_GE, writemask(inst->dst, WRITEMASK_Z), + src_reg(inst->dst), elk_imm_d(1)); } if (instr->op == nir_texop_query_levels) { /* # levels is in .w */ src_reg swizzled(dest); - swizzled.swizzle = BRW_SWIZZLE4(BRW_SWIZZLE_W, BRW_SWIZZLE_W, - BRW_SWIZZLE_W, BRW_SWIZZLE_W); + swizzled.swizzle = ELK_SWIZZLE4(ELK_SWIZZLE_W, ELK_SWIZZLE_W, + ELK_SWIZZLE_W, ELK_SWIZZLE_W); emit(MOV(dest, swizzled)); } } @@ -2203,11 +2203,11 @@ vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate, src_reg surface) { vec4_instruction *inst = - new(mem_ctx) vec4_instruction(SHADER_OPCODE_TXF_MCS, + new(mem_ctx) vec4_instruction(ELK_SHADER_OPCODE_TXF_MCS, dst_reg(this, glsl_uvec4_type())); inst->base_mrf = 2; inst->src[1] = surface; - inst->src[2] = brw_imm_ud(0); /* sampler */ + inst->src[2] = elk_imm_ud(0); /* sampler */ inst->mlen = 1; const int param_base = inst->base_mrf; @@ -2220,7 +2220,7 @@ vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type, coordinate)); emit(MOV(dst_reg(MRF, param_base, coordinate_type, zero_mask), - brw_imm_d(0))); + elk_imm_d(0))); emit(inst); return src_reg(inst->dst); @@ -2266,20 +2266,20 @@ vec4_visitor::nir_emit_undef(nir_undef_instr *instr) vec4_instruction * vec4_visitor::shuffle_64bit_data(dst_reg dst, src_reg src, bool for_write, bool for_scratch, - bblock_t *block, vec4_instruction *ref) + elk_bblock_t *block, vec4_instruction *ref) { assert(type_sz(src.type) == 8); assert(type_sz(dst.type) == 8); assert(!regions_overlap(dst, 2 * REG_SIZE, src, 2 * REG_SIZE)); assert(!ref == !block); - opcode mov_op = for_scratch ? VEC4_OPCODE_MOV_FOR_SCRATCH : BRW_OPCODE_MOV; + elk_opcode mov_op = for_scratch ? ELK_VEC4_OPCODE_MOV_FOR_SCRATCH : ELK_OPCODE_MOV; const vec4_builder bld = !ref ? vec4_builder(this).at_end() : vec4_builder(this).at(block, ref->next); /* Resolve swizzle in src */ - if (src.swizzle != BRW_SWIZZLE_XYZW) { + if (src.swizzle != ELK_SWIZZLE_XYZW) { dst_reg data = dst_reg(this, glsl_dvec4_type()); bld.emit(mov_op, data, src); src = src_reg(data); @@ -2291,12 +2291,12 @@ vec4_visitor::shuffle_64bit_data(dst_reg dst, src_reg src, bool for_write, /* dst+0.ZW = src+1.XY */ bld.group(4, for_write ? 1 : 0) .emit(mov_op, writemask(dst, WRITEMASK_ZW), - swizzle(byte_offset(src, REG_SIZE), BRW_SWIZZLE_XYXY)); + swizzle(byte_offset(src, REG_SIZE), ELK_SWIZZLE_XYXY)); /* dst+1.XY = src+0.ZW */ bld.group(4, for_write ? 0 : 1) .emit(mov_op, writemask(byte_offset(dst, REG_SIZE), WRITEMASK_XY), - swizzle(src, BRW_SWIZZLE_ZWZW)); + swizzle(src, ELK_SWIZZLE_ZWZW)); /* dst+1.ZW = src+1.ZW */ return bld.group(4, 1) diff --git a/src/intel/compiler/elk/elk_vec4_reg_allocate.cpp b/src/intel/compiler/elk/elk_vec4_reg_allocate.cpp index 9d6750183df..47cae724de9 100644 --- a/src/intel/compiler/elk/elk_vec4_reg_allocate.cpp +++ b/src/intel/compiler/elk/elk_vec4_reg_allocate.cpp @@ -32,7 +32,7 @@ using namespace elk; namespace elk { static void -assign(unsigned int *reg_hw_locations, backend_reg *reg) +assign(unsigned int *reg_hw_locations, elk_backend_reg *reg) { if (reg->file == VGRF) { reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; @@ -91,10 +91,10 @@ vec4_visitor::reg_allocate_trivial() } extern "C" void -brw_vec4_alloc_reg_set(struct brw_compiler *compiler) +elk_vec4_alloc_reg_set(struct elk_compiler *compiler) { int base_reg_count = - compiler->devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF; + compiler->devinfo->ver >= 7 ? GFX7_MRF_HACK_START : ELK_MAX_GRF; assert(compiler->devinfo->ver < 8); @@ -287,8 +287,8 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, * compatible with our read mask */ if (prev_inst->dst.file == VGRF && prev_inst->dst.nr == scratch_reg) { - return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) && - (brw_mask_for_swizzle(inst->src[i].swizzle) & + return (!prev_inst->predicate || prev_inst->opcode == ELK_OPCODE_SEL) && + (elk_mask_for_swizzle(inst->src[i].swizzle) & ~prev_inst->dst.writemask) == 0; } @@ -296,8 +296,8 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, * other registers (that won't read/write scratch_reg) do not stop us from * reusing scratch_reg for this instruction. */ - if (prev_inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE || - prev_inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_READ) + if (prev_inst->opcode == ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE || + prev_inst->opcode == ELK_SHADER_OPCODE_GFX4_SCRATCH_READ) continue; /* If the previous instruction does not write to scratch_reg, then check @@ -335,7 +335,7 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, } static inline float -spill_cost_for_type(enum brw_reg_type type) +spill_cost_for_type(enum elk_reg_type type) { /* Spilling of a 64-bit register involves emitting 2 32-bit scratch * messages plus the 64b/32b shuffling code. @@ -424,17 +424,17 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill) switch (inst->opcode) { - case BRW_OPCODE_DO: + case ELK_OPCODE_DO: loop_scale *= 10; break; - case BRW_OPCODE_WHILE: + case ELK_OPCODE_WHILE: loop_scale /= 10; break; - case SHADER_OPCODE_GFX4_SCRATCH_READ: - case SHADER_OPCODE_GFX4_SCRATCH_WRITE: - case VEC4_OPCODE_MOV_FOR_SCRATCH: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ: + case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE: + case ELK_VEC4_OPCODE_MOV_FOR_SCRATCH: for (int i = 0; i < 3; i++) { if (inst->src[i].file == VGRF) no_spill[inst->src[i].nr] = true; @@ -490,7 +490,7 @@ vec4_visitor::spill_reg(unsigned spill_reg_nr) src_reg temp = inst->src[i]; temp.nr = scratch_reg; temp.offset = 0; - temp.swizzle = BRW_SWIZZLE_XYZW; + temp.swizzle = ELK_SWIZZLE_XYZW; emit_scratch_read(block, inst, dst_reg(temp), inst->src[i], spill_offset); temp.offset = inst->src[i].offset; diff --git a/src/intel/compiler/elk/elk_vec4_surface_builder.cpp b/src/intel/compiler/elk/elk_vec4_surface_builder.cpp index e3c19ffad78..525ccdb83d0 100644 --- a/src/intel/compiler/elk/elk_vec4_surface_builder.cpp +++ b/src/intel/compiler/elk/elk_vec4_surface_builder.cpp @@ -45,7 +45,7 @@ namespace { bld.MOV(writemask(offset(dst, 8, i * dst_stride / 4), 1 << (i * dst_stride % 4)), swizzle(offset(src, 8, i * src_stride / 4), - brw_swizzle_for_mask(1 << (i * src_stride % 4)))); + elk_swizzle_for_mask(1 << (i * src_stride % 4)))); return src_reg(dst); } @@ -71,7 +71,7 @@ namespace { bld.MOV(writemask(tmp, mask), src); if (n < 4) - bld.MOV(writemask(tmp, ~mask), brw_imm_d(0)); + bld.MOV(writemask(tmp, ~mask), elk_imm_d(0)); return emit_stride(bld, src_reg(tmp), n, has_simd4x2 ? 1 : 4, 1); } @@ -89,33 +89,33 @@ namespace elk { * result. */ src_reg - emit_send(const vec4_builder &bld, enum opcode op, + emit_send(const vec4_builder &bld, enum elk_opcode op, const src_reg &header, const src_reg &addr, unsigned addr_sz, const src_reg &src, unsigned src_sz, const src_reg &surface, unsigned arg, unsigned ret_sz, - brw_predicate pred = BRW_PREDICATE_NONE) + elk_predicate pred = ELK_PREDICATE_NONE) { /* Calculate the total number of components of the payload. */ const unsigned header_sz = (header.file == BAD_FILE ? 0 : 1); const unsigned sz = header_sz + addr_sz + src_sz; /* Construct the payload. */ - const dst_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, sz); + const dst_reg payload = bld.vgrf(ELK_REGISTER_TYPE_UD, sz); unsigned n = 0; if (header_sz) bld.exec_all().MOV(offset(payload, 8, n++), - retype(header, BRW_REGISTER_TYPE_UD)); + retype(header, ELK_REGISTER_TYPE_UD)); for (unsigned i = 0; i < addr_sz; i++) bld.MOV(offset(payload, 8, n++), - offset(retype(addr, BRW_REGISTER_TYPE_UD), 8, i)); + offset(retype(addr, ELK_REGISTER_TYPE_UD), 8, i)); for (unsigned i = 0; i < src_sz; i++) bld.MOV(offset(payload, 8, n++), - offset(retype(src, BRW_REGISTER_TYPE_UD), 8, i)); + offset(retype(src, ELK_REGISTER_TYPE_UD), 8, i)); /* Reduce the dynamically uniform surface index to a single * scalar. @@ -123,9 +123,9 @@ namespace elk { const src_reg usurface = bld.emit_uniformize(surface); /* Emit the message send instruction. */ - const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, ret_sz); + const dst_reg dst = bld.vgrf(ELK_REGISTER_TYPE_UD, ret_sz); vec4_instruction *inst = - bld.emit(op, dst, src_reg(payload), usurface, brw_imm_ud(arg)); + bld.emit(op, dst, src_reg(payload), usurface, elk_imm_ud(arg)); inst->mlen = sz; inst->size_written = ret_sz * REG_SIZE; inst->header_size = header_sz; @@ -144,9 +144,9 @@ namespace elk { emit_untyped_read(const vec4_builder &bld, const src_reg &surface, const src_reg &addr, unsigned dims, unsigned size, - brw_predicate pred) + elk_predicate pred) { - return emit_send(bld, VEC4_OPCODE_UNTYPED_SURFACE_READ, src_reg(), + return emit_send(bld, ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ, src_reg(), emit_insert(bld, addr, dims, true), 1, src_reg(), 0, surface, size, 1, pred); @@ -161,10 +161,10 @@ namespace elk { emit_untyped_write(const vec4_builder &bld, const src_reg &surface, const src_reg &addr, const src_reg &src, unsigned dims, unsigned size, - brw_predicate pred) + elk_predicate pred) { const bool has_simd4x2 = bld.shader->devinfo->verx10 == 75; - emit_send(bld, VEC4_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(), + emit_send(bld, ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(), emit_insert(bld, addr, dims, has_simd4x2), has_simd4x2 ? 1 : dims, emit_insert(bld, src, size, has_simd4x2), @@ -182,7 +182,7 @@ namespace elk { const src_reg &surface, const src_reg &addr, const src_reg &src0, const src_reg &src1, unsigned dims, unsigned rsize, unsigned op, - brw_predicate pred) + elk_predicate pred) { const bool has_simd4x2 = bld.shader->devinfo->verx10 == 75; @@ -190,19 +190,19 @@ namespace elk { * and Y components of the same vector. */ const unsigned size = (src0.file != BAD_FILE) + (src1.file != BAD_FILE); - const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD); + const dst_reg srcs = bld.vgrf(ELK_REGISTER_TYPE_UD); if (size >= 1) { bld.MOV(writemask(srcs, WRITEMASK_X), - swizzle(src0, BRW_SWIZZLE_XXXX)); + swizzle(src0, ELK_SWIZZLE_XXXX)); } if (size >= 2) { bld.MOV(writemask(srcs, WRITEMASK_Y), - swizzle(src1, BRW_SWIZZLE_XXXX)); + swizzle(src1, ELK_SWIZZLE_XXXX)); } - return emit_send(bld, VEC4_OPCODE_UNTYPED_ATOMIC, src_reg(), + return emit_send(bld, ELK_VEC4_OPCODE_UNTYPED_ATOMIC, src_reg(), emit_insert(bld, addr, dims, has_simd4x2), has_simd4x2 ? 1 : dims, emit_insert(bld, src_reg(srcs), size, has_simd4x2), diff --git a/src/intel/compiler/elk/elk_vec4_surface_builder.h b/src/intel/compiler/elk/elk_vec4_surface_builder.h index 8e3dbeac3a3..cf507d5fca0 100644 --- a/src/intel/compiler/elk/elk_vec4_surface_builder.h +++ b/src/intel/compiler/elk/elk_vec4_surface_builder.h @@ -33,20 +33,20 @@ namespace elk { emit_untyped_read(const vec4_builder &bld, const src_reg &surface, const src_reg &addr, unsigned dims, unsigned size, - brw_predicate pred = BRW_PREDICATE_NONE); + elk_predicate pred = ELK_PREDICATE_NONE); void emit_untyped_write(const vec4_builder &bld, const src_reg &surface, const src_reg &addr, const src_reg &src, unsigned dims, unsigned size, - brw_predicate pred = BRW_PREDICATE_NONE); + elk_predicate pred = ELK_PREDICATE_NONE); src_reg emit_untyped_atomic(const vec4_builder &bld, const src_reg &surface, const src_reg &addr, const src_reg &src0, const src_reg &src1, unsigned dims, unsigned rsize, unsigned op, - brw_predicate pred = BRW_PREDICATE_NONE); + elk_predicate pred = ELK_PREDICATE_NONE); } } diff --git a/src/intel/compiler/elk/elk_vec4_tcs.cpp b/src/intel/compiler/elk/elk_vec4_tcs.cpp index a0838797b9a..919baab6516 100644 --- a/src/intel/compiler/elk/elk_vec4_tcs.cpp +++ b/src/intel/compiler/elk/elk_vec4_tcs.cpp @@ -36,10 +36,10 @@ namespace elk { -vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const struct brw_tcs_prog_key *key, - struct brw_tcs_prog_data *prog_data, +vec4_tcs_visitor::vec4_tcs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const struct elk_tcs_prog_key *key, + struct elk_tcs_prog_data *prog_data, const nir_shader *nir, bool debug_enabled) : vec4_visitor(compiler, params, &key->base.tex, &prog_data->base, @@ -76,7 +76,7 @@ void vec4_tcs_visitor::emit_prolog() { invocation_id = src_reg(this, glsl_uint_type()); - emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id)); + emit(ELK_TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id)); /* HS threads are dispatched with the dispatch mask set to 0xFF. * If there are an odd number of output vertices, then the final @@ -85,11 +85,11 @@ vec4_tcs_visitor::emit_prolog() */ if (nir->info.tess.tcs_vertices_out % 2) { emit(CMP(dst_null_d(), invocation_id, - brw_imm_ud(nir->info.tess.tcs_vertices_out), - BRW_CONDITIONAL_L)); + elk_imm_ud(nir->info.tess.tcs_vertices_out), + ELK_CONDITIONAL_L)); /* Matching ENDIF is in emit_thread_end() */ - emit(IF(BRW_PREDICATE_NORMAL)); + emit(IF(ELK_PREDICATE_NORMAL)); } } @@ -101,12 +101,12 @@ vec4_tcs_visitor::emit_thread_end() current_annotation = "thread end"; if (nir->info.tess.tcs_vertices_out % 2) { - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); } if (devinfo->ver == 7) { - struct brw_tcs_prog_data *tcs_prog_data = - (struct brw_tcs_prog_data *) prog_data; + struct elk_tcs_prog_data *tcs_prog_data = + (struct elk_tcs_prog_data *) prog_data; current_annotation = "release input vertices"; @@ -115,8 +115,8 @@ vec4_tcs_visitor::emit_thread_end() */ if (tcs_prog_data->instances > 1) { dst_reg header = dst_reg(this, glsl_uvec4_type()); - emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header); - emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header)); + emit(ELK_TCS_OPCODE_CREATE_BARRIER_HEADER, header); + emit(ELK_SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header)); } /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles. @@ -125,10 +125,10 @@ vec4_tcs_visitor::emit_thread_end() * we don't have stride in the vec4 world, nor UV immediates in * align16, so we need an opcode to get invocation_id<0,4,0>. */ - set_condmod(BRW_CONDITIONAL_Z, - emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(), + set_condmod(ELK_CONDITIONAL_Z, + emit(ELK_TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(), invocation_id)); - emit(IF(BRW_PREDICATE_NORMAL)); + emit(IF(ELK_PREDICATE_NORMAL)); for (unsigned i = 0; i < key->input_vertices; i += 2) { /* If we have an odd number of input vertices, the last will be * unpaired. We don't want to use an interleaved URB write in @@ -137,13 +137,13 @@ vec4_tcs_visitor::emit_thread_end() const bool is_unpaired = i == key->input_vertices - 1; dst_reg header(this, glsl_uvec4_type()); - emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i), - brw_imm_ud(is_unpaired)); + emit(ELK_TCS_OPCODE_RELEASE_INPUT, header, elk_imm_ud(i), + elk_imm_ud(is_unpaired)); } - emit(BRW_OPCODE_ENDIF); + emit(ELK_OPCODE_ENDIF); } - inst = emit(TCS_OPCODE_THREAD_END); + inst = emit(ELK_TCS_OPCODE_THREAD_END); inst->base_mrf = 14; inst->mlen = 2; } @@ -162,12 +162,12 @@ vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst, /* Set up the message header to reference the proper parts of the URB */ dst_reg header = dst_reg(this, glsl_uvec4_type()); - inst = emit(VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index, + inst = emit(ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index, indirect_offset); inst->force_writemask_all = true; /* Read into a temporary, ignoring writemasking. */ - inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header)); + inst = emit(ELK_VEC4_OPCODE_URB_READ, temp, src_reg(header)); inst->offset = base_offset; inst->mlen = 1; inst->base_mrf = -1; @@ -177,10 +177,10 @@ vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst, * Also attempt to deal with gl_PointSize being in the .w component. */ if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { - emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW))); + emit(MOV(dst, swizzle(src_reg(temp), ELK_SWIZZLE_WWWW))); } else { src_reg src = src_reg(temp); - src.swizzle = BRW_SWZ_COMP_INPUT(first_component); + src.swizzle = ELK_SWZ_COMP_INPUT(first_component); emit(MOV(dst, src)); } } @@ -195,11 +195,11 @@ vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst, /* Set up the message header to reference the proper parts of the URB */ dst_reg header = dst_reg(this, glsl_uvec4_type()); - inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header, - brw_imm_ud(dst.writemask << first_component), indirect_offset); + inst = emit(ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header, + elk_imm_ud(dst.writemask << first_component), indirect_offset); inst->force_writemask_all = true; - vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header)); + vec4_instruction *read = emit(ELK_VEC4_OPCODE_URB_READ, dst, src_reg(header)); read->offset = base_offset; read->mlen = 1; read->base_mrf = -1; @@ -208,7 +208,7 @@ vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst, /* Read into a temporary and copy with a swizzle and writemask. */ read->dst = retype(dst_reg(this, glsl_ivec4_type()), dst.type); emit(MOV(dst, swizzle(src_reg(read->dst), - BRW_SWZ_COMP_INPUT(first_component)))); + ELK_SWZ_COMP_INPUT(first_component)))); } } @@ -224,14 +224,14 @@ vec4_tcs_visitor::emit_urb_write(const src_reg &value, src_reg message(this, glsl_uvec4_type(), 2); vec4_instruction *inst; - inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message), - brw_imm_ud(writemask), indirect_offset); + inst = emit(ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message), + elk_imm_ud(writemask), indirect_offset); inst->force_writemask_all = true; inst = emit(MOV(byte_offset(dst_reg(retype(message, value.type)), REG_SIZE), value)); inst->force_writemask_all = true; - inst = emit(VEC4_TCS_OPCODE_URB_WRITE, dst_null_f(), message); + inst = emit(ELK_VEC4_TCS_OPCODE_URB_WRITE, dst_null_f(), message); inst->offset = base_offset; inst->mlen = 2; inst->base_mrf = -1; @@ -242,16 +242,16 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) { switch (instr->intrinsic) { case nir_intrinsic_load_invocation_id: - emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_UD), + emit(MOV(get_nir_def(instr->def, ELK_REGISTER_TYPE_UD), invocation_id)); break; case nir_intrinsic_load_primitive_id: - emit(TCS_OPCODE_GET_PRIMITIVE_ID, - get_nir_def(instr->def, BRW_REGISTER_TYPE_UD)); + emit(ELK_TCS_OPCODE_GET_PRIMITIVE_ID, + get_nir_def(instr->def, ELK_REGISTER_TYPE_UD)); break; case nir_intrinsic_load_patch_vertices_in: - emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_D), - brw_imm_d(key->input_vertices))); + emit(MOV(get_nir_def(instr->def, ELK_REGISTER_TYPE_D), + elk_imm_d(key->input_vertices))); break; case nir_intrinsic_load_per_vertex_input: { assert(instr->def.bit_size == 32); @@ -259,11 +259,11 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) unsigned imm_offset = nir_intrinsic_base(instr); src_reg vertex_index = retype(get_nir_src_imm(instr->src[0]), - BRW_REGISTER_TYPE_UD); + ELK_REGISTER_TYPE_UD); unsigned first_component = nir_intrinsic_component(instr); - dst_reg dst = get_nir_def(instr->def, BRW_REGISTER_TYPE_D); - dst.writemask = brw_writemask_for_size(instr->num_components); + dst_reg dst = get_nir_def(instr->def, ELK_REGISTER_TYPE_D); + dst.writemask = elk_writemask_for_size(instr->num_components); emit_input_urb_read(dst, vertex_index, imm_offset, first_component, indirect_offset); break; @@ -276,8 +276,8 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) src_reg indirect_offset = get_indirect_offset(instr); unsigned imm_offset = nir_intrinsic_base(instr); - dst_reg dst = get_nir_def(instr->def, BRW_REGISTER_TYPE_D); - dst.writemask = brw_writemask_for_size(instr->num_components); + dst_reg dst = get_nir_def(instr->def, ELK_REGISTER_TYPE_D); + dst.writemask = elk_writemask_for_size(instr->num_components); emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr), indirect_offset); @@ -288,15 +288,15 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) assert(nir_src_bit_size(instr->src[0]) == 32); src_reg value = get_nir_src(instr->src[0]); unsigned mask = nir_intrinsic_write_mask(instr); - unsigned swiz = BRW_SWIZZLE_XYZW; + unsigned swiz = ELK_SWIZZLE_XYZW; src_reg indirect_offset = get_indirect_offset(instr); unsigned imm_offset = nir_intrinsic_base(instr); unsigned first_component = nir_intrinsic_component(instr); if (first_component) { - assert(swiz == BRW_SWIZZLE_XYZW); - swiz = BRW_SWZ_COMP_OUTPUT(first_component); + assert(swiz == ELK_SWIZZLE_XYZW); + swiz = ELK_SWZ_COMP_OUTPUT(first_component); mask = mask << first_component; } @@ -310,8 +310,8 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) vec4_visitor::nir_emit_intrinsic(instr); if (nir_intrinsic_execution_scope(instr) == SCOPE_WORKGROUP) { dst_reg header = dst_reg(this, glsl_uvec4_type()); - emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header); - emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header)); + emit(ELK_TCS_OPCODE_CREATE_BARRIER_HEADER, header); + emit(ELK_SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header)); } break; @@ -352,17 +352,17 @@ get_patch_count_threshold(int input_control_points) } /* namespace elk */ extern "C" const unsigned * -brw_compile_tcs(const struct brw_compiler *compiler, - struct brw_compile_tcs_params *params) +elk_compile_tcs(const struct elk_compiler *compiler, + struct elk_compile_tcs_params *params) { const struct intel_device_info *devinfo = compiler->devinfo; nir_shader *nir = params->base.nir; - const struct brw_tcs_prog_key *key = params->key; - struct brw_tcs_prog_data *prog_data = params->prog_data; - struct brw_vue_prog_data *vue_prog_data = &prog_data->base; + const struct elk_tcs_prog_key *key = params->key; + struct elk_tcs_prog_data *prog_data = params->prog_data; + struct elk_vue_prog_data *vue_prog_data = &prog_data->base; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL]; - const bool debug_enabled = brw_should_print_shader(nir, DEBUG_TCS); + const bool debug_enabled = elk_should_print_shader(nir, DEBUG_TCS); const unsigned *assembly; vue_prog_data->base.stage = MESA_SHADER_TESS_CTRL; @@ -373,22 +373,22 @@ brw_compile_tcs(const struct brw_compiler *compiler, nir->info.patch_outputs_written = key->patch_outputs_written; struct intel_vue_map input_vue_map; - brw_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read, + elk_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read, nir->info.separate_shader, 1); - brw_compute_tess_vue_map(&vue_prog_data->vue_map, + elk_compute_tess_vue_map(&vue_prog_data->vue_map, nir->info.outputs_written, nir->info.patch_outputs_written); - brw_nir_apply_key(nir, compiler, &key->base, 8); - brw_nir_lower_vue_inputs(nir, &input_vue_map); - brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map, + elk_nir_apply_key(nir, compiler, &key->base, 8); + elk_nir_lower_vue_inputs(nir, &input_vue_map); + elk_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map, key->_tes_primitive_mode); if (key->quads_workaround) intel_nir_apply_tcs_quads_workaround(nir); if (key->input_vertices > 0) intel_nir_lower_patch_vertices_in(nir, key->input_vertices); - brw_postprocess_nir(nir, compiler, debug_enabled, + elk_postprocess_nir(nir, compiler, debug_enabled, key->base.robust_flags); bool has_primitive_id = @@ -442,14 +442,14 @@ brw_compile_tcs(const struct brw_compiler *compiler, if (unlikely(debug_enabled)) { fprintf(stderr, "TCS Input "); - brw_print_vue_map(stderr, &input_vue_map, MESA_SHADER_TESS_CTRL); + elk_print_vue_map(stderr, &input_vue_map, MESA_SHADER_TESS_CTRL); fprintf(stderr, "TCS Output "); - brw_print_vue_map(stderr, &vue_prog_data->vue_map, MESA_SHADER_TESS_CTRL); + elk_print_vue_map(stderr, &vue_prog_data->vue_map, MESA_SHADER_TESS_CTRL); } if (is_scalar) { const unsigned dispatch_width = devinfo->ver >= 20 ? 16 : 8; - fs_visitor v(compiler, ¶ms->base, &key->base, + elk_fs_visitor v(compiler, ¶ms->base, &key->base, &prog_data->base.base, nir, dispatch_width, params->base.stats != NULL, debug_enabled); if (!v.run_tcs()) { @@ -461,7 +461,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, assert(v.payload().num_regs % reg_unit(devinfo) == 0); prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo); - fs_generator g(compiler, ¶ms->base, + elk_fs_generator g(compiler, ¶ms->base, &prog_data->base.base, false, MESA_SHADER_TESS_CTRL); if (unlikely(debug_enabled)) { g.enable_debug(ralloc_asprintf(params->base.mem_ctx, @@ -490,7 +490,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, v.dump_instructions(); - assembly = brw_vec4_generate_assembly(compiler, ¶ms->base, nir, + assembly = elk_vec4_generate_assembly(compiler, ¶ms->base, nir, &prog_data->base, v.cfg, v.performance_analysis.require(), debug_enabled); diff --git a/src/intel/compiler/elk/elk_vec4_tcs.h b/src/intel/compiler/elk/elk_vec4_tcs.h index fdf75b331c6..a005d40d991 100644 --- a/src/intel/compiler/elk/elk_vec4_tcs.h +++ b/src/intel/compiler/elk/elk_vec4_tcs.h @@ -40,10 +40,10 @@ namespace elk { class vec4_tcs_visitor : public vec4_visitor { public: - vec4_tcs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const struct brw_tcs_prog_key *key, - struct brw_tcs_prog_data *prog_data, + vec4_tcs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const struct elk_tcs_prog_key *key, + struct elk_tcs_prog_data *prog_data, const nir_shader *nir, bool debug_enabled); @@ -73,7 +73,7 @@ protected: virtual void emit_urb_write_header(int /* mrf */) {} virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) { return NULL; } - const struct brw_tcs_prog_key *key; + const struct elk_tcs_prog_key *key; src_reg invocation_id; }; diff --git a/src/intel/compiler/elk/elk_vec4_tes.cpp b/src/intel/compiler/elk/elk_vec4_tes.cpp index 1d623c6480d..adc8154dea7 100644 --- a/src/intel/compiler/elk/elk_vec4_tes.cpp +++ b/src/intel/compiler/elk/elk_vec4_tes.cpp @@ -33,10 +33,10 @@ namespace elk { -vec4_tes_visitor::vec4_tes_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const struct brw_tes_prog_key *key, - struct brw_tes_prog_data *prog_data, +vec4_tes_visitor::vec4_tes_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const struct elk_tes_prog_key *key, + struct elk_tes_prog_data *prog_data, const nir_shader *shader, bool debug_enabled) : vec4_visitor(compiler, params, &key->base.tex, &prog_data->base, @@ -63,7 +63,7 @@ vec4_tes_visitor::setup_payload() continue; unsigned slot = inst->src[i].nr + inst->src[i].offset / 16; - struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2)); + struct elk_reg grf = elk_vec4_grf(reg + slot / 2, 4 * (slot % 2)); grf = stride(grf, 0, 4, 1); grf.swizzle = inst->src[i].swizzle; grf.type = inst->src[i].type; @@ -83,7 +83,7 @@ void vec4_tes_visitor::emit_prolog() { input_read_header = src_reg(this, glsl_uvec4_type()); - emit(TES_OPCODE_CREATE_INPUT_READ_HEADER, dst_reg(input_read_header)); + emit(ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER, dst_reg(input_read_header)); this->current_annotation = NULL; } @@ -93,7 +93,7 @@ void vec4_tes_visitor::emit_urb_write_header(int mrf) { /* No need to do anything for DS; an implied write to this MRF will be - * performed by VEC4_VS_OPCODE_URB_WRITE. + * performed by ELK_VEC4_VS_OPCODE_URB_WRITE. */ (void) mrf; } @@ -102,9 +102,9 @@ vec4_tes_visitor::emit_urb_write_header(int mrf) vec4_instruction * vec4_tes_visitor::emit_urb_write_opcode(bool complete) { - vec4_instruction *inst = emit(VEC4_VS_OPCODE_URB_WRITE); + vec4_instruction *inst = emit(ELK_VEC4_VS_OPCODE_URB_WRITE); inst->urb_write_flags = complete ? - BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS; + ELK_URB_WRITE_EOT_COMPLETE : ELK_URB_WRITE_NO_FLAGS; return inst; } @@ -112,39 +112,39 @@ vec4_tes_visitor::emit_urb_write_opcode(bool complete) void vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) { - const struct brw_tes_prog_data *tes_prog_data = - (const struct brw_tes_prog_data *) prog_data; + const struct elk_tes_prog_data *tes_prog_data = + (const struct elk_tes_prog_data *) prog_data; switch (instr->intrinsic) { case nir_intrinsic_load_tess_coord: /* gl_TessCoord is part of the payload in g1 channels 0-2 and 4-6. */ - emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F), - src_reg(brw_vec8_grf(1, 0)))); + emit(MOV(get_nir_def(instr->def, ELK_REGISTER_TYPE_F), + src_reg(elk_vec8_grf(1, 0)))); break; case nir_intrinsic_load_tess_level_outer: if (tes_prog_data->domain == INTEL_TESS_DOMAIN_ISOLINE) { - emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->def, ELK_REGISTER_TYPE_F), swizzle(src_reg(ATTR, 1, glsl_vec4_type()), - BRW_SWIZZLE_ZWZW))); + ELK_SWIZZLE_ZWZW))); } else { - emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->def, ELK_REGISTER_TYPE_F), swizzle(src_reg(ATTR, 1, glsl_vec4_type()), - BRW_SWIZZLE_WZYX))); + ELK_SWIZZLE_WZYX))); } break; case nir_intrinsic_load_tess_level_inner: if (tes_prog_data->domain == INTEL_TESS_DOMAIN_QUAD) { - emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->def, ELK_REGISTER_TYPE_F), swizzle(src_reg(ATTR, 0, glsl_vec4_type()), - BRW_SWIZZLE_WZYX))); + ELK_SWIZZLE_WZYX))); } else { - emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F), + emit(MOV(get_nir_def(instr->def, ELK_REGISTER_TYPE_F), src_reg(ATTR, 1, glsl_float_type()))); } break; case nir_intrinsic_load_primitive_id: - emit(TES_OPCODE_GET_PRIMITIVE_ID, - get_nir_def(instr->def, BRW_REGISTER_TYPE_UD)); + emit(ELK_TES_OPCODE_GET_PRIMITIVE_ID, + get_nir_def(instr->def, ELK_REGISTER_TYPE_UD)); break; case nir_intrinsic_load_input: @@ -161,13 +161,13 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) /* Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the * valid range of the offset is [0, 0FFFFFFFh]. */ - emit_minmax(BRW_CONDITIONAL_L, + emit_minmax(ELK_CONDITIONAL_L, dst_reg(clamped_indirect_offset), - retype(indirect_offset, BRW_REGISTER_TYPE_UD), - brw_imm_ud(0x0fffffffu)); + retype(indirect_offset, ELK_REGISTER_TYPE_UD), + elk_imm_ud(0x0fffffffu)); header = src_reg(this, glsl_uvec4_type()); - emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header), + emit(ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header), input_read_header, clamped_indirect_offset); } else { /* Arbitrarily only push up to 24 vec4 slots worth of data, @@ -176,9 +176,9 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) const unsigned max_push_slots = 24; if (imm_offset < max_push_slots) { src_reg src = src_reg(ATTR, imm_offset, glsl_ivec4_type()); - src.swizzle = BRW_SWZ_COMP_INPUT(first_component); + src.swizzle = ELK_SWZ_COMP_INPUT(first_component); - emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_D), src)); + emit(MOV(get_nir_def(instr->def, ELK_REGISTER_TYPE_D), src)); prog_data->urb_read_length = MAX2(prog_data->urb_read_length, @@ -189,18 +189,18 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) dst_reg temp(this, glsl_ivec4_type()); vec4_instruction *read = - emit(VEC4_OPCODE_URB_READ, temp, src_reg(header)); + emit(ELK_VEC4_OPCODE_URB_READ, temp, src_reg(header)); read->offset = imm_offset; - read->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET; + read->urb_write_flags = ELK_URB_WRITE_PER_SLOT_OFFSET; src_reg src = src_reg(temp); - src.swizzle = BRW_SWZ_COMP_INPUT(first_component); + src.swizzle = ELK_SWZ_COMP_INPUT(first_component); /* Copy to target. We might end up with some funky writemasks landing * in here, but we really don't want them in the above pseudo-ops. */ - dst_reg dst = get_nir_def(instr->def, BRW_REGISTER_TYPE_D); - dst.writemask = brw_writemask_for_size(instr->num_components); + dst_reg dst = get_nir_def(instr->def, ELK_REGISTER_TYPE_D); + dst.writemask = elk_writemask_for_size(instr->num_components); emit(MOV(dst, src)); break; } diff --git a/src/intel/compiler/elk/elk_vec4_tes.h b/src/intel/compiler/elk/elk_vec4_tes.h index bf8d005ac62..48dc75ded13 100644 --- a/src/intel/compiler/elk/elk_vec4_tes.h +++ b/src/intel/compiler/elk/elk_vec4_tes.h @@ -38,10 +38,10 @@ namespace elk { class vec4_tes_visitor : public vec4_visitor { public: - vec4_tes_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const struct brw_tes_prog_key *key, - struct brw_tes_prog_data *prog_data, + vec4_tes_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const struct elk_tes_prog_key *key, + struct elk_tes_prog_data *prog_data, const nir_shader *nir, bool debug_enabled); diff --git a/src/intel/compiler/elk/elk_vec4_visitor.cpp b/src/intel/compiler/elk/elk_vec4_visitor.cpp index cc4f9821486..c361c5de6fa 100644 --- a/src/intel/compiler/elk/elk_vec4_visitor.cpp +++ b/src/intel/compiler/elk/elk_vec4_visitor.cpp @@ -28,7 +28,7 @@ namespace elk { -vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst, +vec4_instruction::vec4_instruction(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) { @@ -42,14 +42,14 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst, this->no_dd_clear = false; this->no_dd_check = false; this->writes_accumulator = false; - this->conditional_mod = BRW_CONDITIONAL_NONE; - this->predicate = BRW_PREDICATE_NONE; + this->conditional_mod = ELK_CONDITIONAL_NONE; + this->predicate = ELK_PREDICATE_NONE; this->predicate_inverse = false; this->target = 0; this->shadow_compare = false; this->eot = false; this->ir = NULL; - this->urb_write_flags = BRW_URB_WRITE_NO_FLAGS; + this->urb_write_flags = ELK_URB_WRITE_NO_FLAGS; this->header_size = 0; this->flag_subreg = 0; this->mlen = 0; @@ -74,7 +74,7 @@ vec4_visitor::emit(vec4_instruction *inst) } vec4_instruction * -vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst, +vec4_visitor::emit_before(elk_bblock_t *block, vec4_instruction *inst, vec4_instruction *new_inst) { new_inst->ir = inst->ir; @@ -86,7 +86,7 @@ vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst, } vec4_instruction * -vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, +vec4_visitor::emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) { return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1, src2)); @@ -94,26 +94,26 @@ vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, vec4_instruction * -vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, +vec4_visitor::emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1) { return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1)); } vec4_instruction * -vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) +vec4_visitor::emit(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0) { return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0)); } vec4_instruction * -vec4_visitor::emit(enum opcode opcode, const dst_reg &dst) +vec4_visitor::emit(enum elk_opcode opcode, const dst_reg &dst) { return emit(new(mem_ctx) vec4_instruction(opcode, dst)); } vec4_instruction * -vec4_visitor::emit(enum opcode opcode) +vec4_visitor::emit(enum elk_opcode opcode) { return emit(new(mem_ctx) vec4_instruction(opcode, dst_reg())); } @@ -122,7 +122,7 @@ vec4_visitor::emit(enum opcode opcode) vec4_instruction * \ vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \ { \ - return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \ + return new(mem_ctx) vec4_instruction(ELK_OPCODE_##op, dst, src0); \ } #define ALU2(op) \ @@ -130,7 +130,7 @@ vec4_visitor::emit(enum opcode opcode) vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \ const src_reg &src1) \ { \ - return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \ + return new(mem_ctx) vec4_instruction(ELK_OPCODE_##op, dst, \ src0, src1); \ } @@ -140,7 +140,7 @@ vec4_visitor::emit(enum opcode opcode) const src_reg &src1) \ { \ vec4_instruction *inst = new(mem_ctx) vec4_instruction( \ - BRW_OPCODE_##op, dst, src0, src1); \ + ELK_OPCODE_##op, dst, src0, src1); \ inst->writes_accumulator = true; \ return inst; \ } @@ -151,7 +151,7 @@ vec4_visitor::emit(enum opcode opcode) const src_reg &src1, const src_reg &src2) \ { \ assert(devinfo->ver >= 6); \ - return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \ + return new(mem_ctx) vec4_instruction(ELK_OPCODE_##op, dst, \ src0, src1, src2); \ } @@ -192,11 +192,11 @@ ALU1(DIM) /** Gfx4 predicated IF. */ vec4_instruction * -vec4_visitor::IF(enum brw_predicate predicate) +vec4_visitor::IF(enum elk_predicate predicate) { vec4_instruction *inst; - inst = new(mem_ctx) vec4_instruction(BRW_OPCODE_IF); + inst = new(mem_ctx) vec4_instruction(ELK_OPCODE_IF); inst->predicate = predicate; return inst; @@ -205,7 +205,7 @@ vec4_visitor::IF(enum brw_predicate predicate) /** Gfx6 IF with embedded comparison. */ vec4_instruction * vec4_visitor::IF(src_reg src0, src_reg src1, - enum brw_conditional_mod condition) + enum elk_conditional_mod condition) { assert(devinfo->ver == 6); @@ -214,7 +214,7 @@ vec4_visitor::IF(src_reg src0, src_reg src1, resolve_ud_negate(&src0); resolve_ud_negate(&src1); - inst = new(mem_ctx) vec4_instruction(BRW_OPCODE_IF, dst_null_d(), + inst = new(mem_ctx) vec4_instruction(ELK_OPCODE_IF, dst_null_d(), src0, src1); inst->conditional_mod = condition; @@ -228,7 +228,7 @@ vec4_visitor::IF(src_reg src0, src_reg src1, */ vec4_instruction * vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, - enum brw_conditional_mod condition) + enum elk_conditional_mod condition) { vec4_instruction *inst; @@ -247,7 +247,7 @@ vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, resolve_ud_negate(&src0); resolve_ud_negate(&src1); - inst = new(mem_ctx) vec4_instruction(BRW_OPCODE_CMP, dst, src0, src1); + inst = new(mem_ctx) vec4_instruction(ELK_OPCODE_CMP, dst, src0, src1); inst->conditional_mod = condition; return inst; @@ -258,7 +258,7 @@ vec4_visitor::SCRATCH_READ(const dst_reg &dst, const src_reg &index) { vec4_instruction *inst; - inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GFX4_SCRATCH_READ, + inst = new(mem_ctx) vec4_instruction(ELK_SHADER_OPCODE_GFX4_SCRATCH_READ, dst, index); inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver) + 1; inst->mlen = 2; @@ -272,7 +272,7 @@ vec4_visitor::SCRATCH_WRITE(const dst_reg &dst, const src_reg &src, { vec4_instruction *inst; - inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GFX4_SCRATCH_WRITE, + inst = new(mem_ctx) vec4_instruction(ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE, dst, src, index); inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver); inst->mlen = 3; @@ -297,12 +297,12 @@ vec4_visitor::fix_3src_operand(const src_reg &src) if (src.file != UNIFORM && src.file != IMM) return src; - if (src.file == UNIFORM && brw_is_single_value_swizzle(src.swizzle)) + if (src.file == UNIFORM && elk_is_single_value_swizzle(src.swizzle)) return src; dst_reg expanded = dst_reg(this, glsl_vec4_type()); expanded.type = src.type; - emit(VEC4_OPCODE_UNPACK_UNIFORM, expanded, src); + emit(ELK_VEC4_OPCODE_UNPACK_UNIFORM, expanded, src); return src_reg(expanded); } @@ -333,7 +333,7 @@ vec4_visitor::fix_math_operand(const src_reg &src) } vec4_instruction * -vec4_visitor::emit_math(enum opcode opcode, +vec4_visitor::emit_math(enum elk_opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1) { @@ -360,8 +360,8 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0) unreachable("ir_unop_pack_half_2x16 should be lowered"); } - assert(dst.type == BRW_REGISTER_TYPE_UD); - assert(src0.type == BRW_REGISTER_TYPE_F); + assert(dst.type == ELK_REGISTER_TYPE_UD); + assert(src0.type == ELK_REGISTER_TYPE_F); /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16: * @@ -401,7 +401,7 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0) * You should inspect the disasm output in order to verify that the MOV is * not optimized away. */ - emit(MOV(tmp_dst, brw_imm_ud(0x12345678u))); + emit(MOV(tmp_dst, elk_imm_ud(0x12345678u))); #endif /* Give tmp the form below, where "." means untouched. @@ -419,14 +419,14 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0) /* Give the write-channels of dst the form: * 0xhhhh0000 */ - tmp_src.swizzle = BRW_SWIZZLE_YYYY; - emit(SHL(dst, tmp_src, brw_imm_ud(16u))); + tmp_src.swizzle = ELK_SWIZZLE_YYYY; + emit(SHL(dst, tmp_src, elk_imm_ud(16u))); /* Finally, give the write-channels of dst the form of packHalf2x16's * output: * 0xhhhhllll */ - tmp_src.swizzle = BRW_SWIZZLE_XXXX; + tmp_src.swizzle = ELK_SWIZZLE_XXXX; emit(OR(dst, src_reg(dst), tmp_src)); } @@ -437,8 +437,8 @@ vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0) unreachable("ir_unop_unpack_half_2x16 should be lowered"); } - assert(dst.type == BRW_REGISTER_TYPE_F); - assert(src0.type == BRW_REGISTER_TYPE_UD); + assert(dst.type == ELK_REGISTER_TYPE_F); + assert(src0.type == ELK_REGISTER_TYPE_UD); /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32: * @@ -459,10 +459,10 @@ vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0) src_reg tmp_src(tmp_dst); tmp_dst.writemask = WRITEMASK_X; - emit(AND(tmp_dst, src0, brw_imm_ud(0xffffu))); + emit(AND(tmp_dst, src0, elk_imm_ud(0xffffu))); tmp_dst.writemask = WRITEMASK_Y; - emit(SHR(tmp_dst, src0, brw_imm_ud(16u))); + emit(SHR(tmp_dst, src0, elk_imm_ud(16u))); dst.writemask = WRITEMASK_XY; emit(F16TO32(dst, tmp_src)); @@ -477,17 +477,17 @@ vec4_visitor::emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0) * vector float and a type-converting MOV. */ dst_reg shift(this, glsl_uvec4_type()); - emit(MOV(shift, brw_imm_vf4(0x00, 0x60, 0x70, 0x78))); + emit(MOV(shift, elk_imm_vf4(0x00, 0x60, 0x70, 0x78))); dst_reg shifted(this, glsl_uvec4_type()); - src0.swizzle = BRW_SWIZZLE_XXXX; + src0.swizzle = ELK_SWIZZLE_XXXX; emit(SHR(shifted, src0, src_reg(shift))); - shifted.type = BRW_REGISTER_TYPE_UB; + shifted.type = ELK_REGISTER_TYPE_UB; dst_reg f(this, glsl_vec4_type()); - emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted)); + emit(ELK_VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted)); - emit(MUL(dst, src_reg(f), brw_imm_f(1.0f / 255.0f))); + emit(MUL(dst, src_reg(f), elk_imm_f(1.0f / 255.0f))); } void @@ -499,22 +499,22 @@ vec4_visitor::emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0) * vector float and a type-converting MOV. */ dst_reg shift(this, glsl_uvec4_type()); - emit(MOV(shift, brw_imm_vf4(0x00, 0x60, 0x70, 0x78))); + emit(MOV(shift, elk_imm_vf4(0x00, 0x60, 0x70, 0x78))); dst_reg shifted(this, glsl_uvec4_type()); - src0.swizzle = BRW_SWIZZLE_XXXX; + src0.swizzle = ELK_SWIZZLE_XXXX; emit(SHR(shifted, src0, src_reg(shift))); - shifted.type = BRW_REGISTER_TYPE_B; + shifted.type = ELK_REGISTER_TYPE_B; dst_reg f(this, glsl_vec4_type()); - emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted)); + emit(ELK_VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted)); dst_reg scaled(this, glsl_vec4_type()); - emit(MUL(scaled, src_reg(f), brw_imm_f(1.0f / 127.0f))); + emit(MUL(scaled, src_reg(f), elk_imm_f(1.0f / 127.0f))); dst_reg max(this, glsl_vec4_type()); - emit_minmax(BRW_CONDITIONAL_GE, max, src_reg(scaled), brw_imm_f(-1.0f)); - emit_minmax(BRW_CONDITIONAL_L, dst, src_reg(max), brw_imm_f(1.0f)); + emit_minmax(ELK_CONDITIONAL_GE, max, src_reg(scaled), elk_imm_f(-1.0f)); + emit_minmax(ELK_CONDITIONAL_L, dst, src_reg(max), elk_imm_f(1.0f)); } void @@ -525,7 +525,7 @@ vec4_visitor::emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0) inst->saturate = true; dst_reg scaled(this, glsl_vec4_type()); - emit(MUL(scaled, src_reg(saturated), brw_imm_f(255.0f))); + emit(MUL(scaled, src_reg(saturated), elk_imm_f(255.0f))); dst_reg rounded(this, glsl_vec4_type()); emit(RNDE(rounded, src_reg(scaled))); @@ -534,20 +534,20 @@ vec4_visitor::emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0) emit(MOV(u, src_reg(rounded))); src_reg bytes(u); - emit(VEC4_OPCODE_PACK_BYTES, dst, bytes); + emit(ELK_VEC4_OPCODE_PACK_BYTES, dst, bytes); } void vec4_visitor::emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0) { dst_reg max(this, glsl_vec4_type()); - emit_minmax(BRW_CONDITIONAL_GE, max, src0, brw_imm_f(-1.0f)); + emit_minmax(ELK_CONDITIONAL_GE, max, src0, elk_imm_f(-1.0f)); dst_reg min(this, glsl_vec4_type()); - emit_minmax(BRW_CONDITIONAL_L, min, src_reg(max), brw_imm_f(1.0f)); + emit_minmax(ELK_CONDITIONAL_L, min, src_reg(max), elk_imm_f(1.0f)); dst_reg scaled(this, glsl_vec4_type()); - emit(MUL(scaled, src_reg(min), brw_imm_f(127.0f))); + emit(MUL(scaled, src_reg(min), elk_imm_f(127.0f))); dst_reg rounded(this, glsl_vec4_type()); emit(RNDE(rounded, src_reg(scaled))); @@ -556,7 +556,7 @@ vec4_visitor::emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0) emit(MOV(i, src_reg(rounded))); src_reg bytes(i); - emit(VEC4_OPCODE_PACK_BYTES, dst, bytes); + emit(ELK_VEC4_OPCODE_PACK_BYTES, dst, bytes); } /* @@ -564,7 +564,7 @@ vec4_visitor::emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0) * false) elements needed to pack a type. */ static int -type_size_xvec4(const struct glsl_type *type, bool as_vec4, bool bindless) +elk_type_size_xvec4(const struct glsl_type *type, bool as_vec4, bool bindless) { unsigned int i; int size; @@ -597,13 +597,13 @@ type_size_xvec4(const struct glsl_type *type, bool as_vec4, bool bindless) } case GLSL_TYPE_ARRAY: assert(type->length > 0); - return type_size_xvec4(type->fields.array, as_vec4, bindless) * + return elk_type_size_xvec4(type->fields.array, as_vec4, bindless) * type->length; case GLSL_TYPE_STRUCT: case GLSL_TYPE_INTERFACE: size = 0; for (i = 0; i < type->length; i++) { - size += type_size_xvec4(type->fields.structure[i].type, as_vec4, + size += elk_type_size_xvec4(type->fields.structure[i].type, as_vec4, bindless); } return size; @@ -640,9 +640,9 @@ type_size_xvec4(const struct glsl_type *type, bool as_vec4, bool bindless) * store a particular type. */ extern "C" int -type_size_vec4(const struct glsl_type *type, bool bindless) +elk_type_size_vec4(const struct glsl_type *type, bool bindless) { - return type_size_xvec4(type, true, bindless); + return elk_type_size_xvec4(type, true, bindless); } /** @@ -665,9 +665,9 @@ type_size_vec4(const struct glsl_type *type, bool bindless) * type fits in one or two vec4 slots. */ extern "C" int -type_size_dvec4(const struct glsl_type *type, bool bindless) +elk_type_size_dvec4(const struct glsl_type *type, bool bindless) { - return type_size_xvec4(type, false, bindless); + return elk_type_size_xvec4(type, false, bindless); } src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type) @@ -675,15 +675,15 @@ src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type) init(); this->file = VGRF; - this->nr = v->alloc.allocate(type_size_vec4(type, false)); + this->nr = v->alloc.allocate(elk_type_size_vec4(type, false)); if (glsl_type_is_array(type) || glsl_type_is_struct(type)) { - this->swizzle = BRW_SWIZZLE_NOOP; + this->swizzle = ELK_SWIZZLE_NOOP; } else { - this->swizzle = brw_swizzle_for_size(type->vector_elements); + this->swizzle = elk_swizzle_for_size(type->vector_elements); } - this->type = brw_type_for_base_type(type); + this->type = elk_type_for_base_type(type); } src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type, int size) @@ -693,11 +693,11 @@ src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type, int size) init(); this->file = VGRF; - this->nr = v->alloc.allocate(type_size_vec4(type, false) * size); + this->nr = v->alloc.allocate(elk_type_size_vec4(type, false) * size); - this->swizzle = BRW_SWIZZLE_NOOP; + this->swizzle = ELK_SWIZZLE_NOOP; - this->type = brw_type_for_base_type(type); + this->type = elk_type_for_base_type(type); } dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type) @@ -705,7 +705,7 @@ dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type) init(); this->file = VGRF; - this->nr = v->alloc.allocate(type_size_vec4(type, false)); + this->nr = v->alloc.allocate(elk_type_size_vec4(type, false)); if (glsl_type_is_array(type) || glsl_type_is_struct(type)) { this->writemask = WRITEMASK_XYZW; @@ -713,14 +713,14 @@ dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type) this->writemask = (1 << type->vector_elements) - 1; } - this->type = brw_type_for_base_type(type); + this->type = elk_type_for_base_type(type); } vec4_instruction * -vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst, +vec4_visitor::emit_minmax(enum elk_conditional_mod conditionalmod, dst_reg dst, src_reg src0, src_reg src1) { - vec4_instruction *inst = emit(BRW_OPCODE_SEL, dst, src0, src1); + vec4_instruction *inst = emit(ELK_OPCODE_SEL, dst, src0, src1); inst->conditional_mod = conditionalmod; return inst; } @@ -734,7 +734,7 @@ void vec4_visitor::emit_pull_constant_load_reg(dst_reg dst, src_reg surf_index, src_reg offset_reg, - bblock_t *before_block, + elk_bblock_t *before_block, vec4_instruction *before_inst) { assert((before_inst == NULL && before_block == NULL) || @@ -754,13 +754,13 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst, else emit(pull); - pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GFX7, + pull = new(mem_ctx) vec4_instruction(ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7, dst, surf_index, src_reg(grf_offset)); pull->mlen = 1; } else { - pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD, + pull = new(mem_ctx) vec4_instruction(ELK_VS_OPCODE_PULL_CONSTANT_LOAD, dst, surf_index, offset_reg); @@ -781,9 +781,9 @@ vec4_visitor::emit_uniformize(const src_reg &src) const dst_reg dst = retype(dst_reg(this, glsl_uint_type()), src.type); - emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, dst_reg(chan_index)) + emit(ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, dst_reg(chan_index)) ->force_writemask_all = true; - emit(SHADER_OPCODE_BROADCAST, dst, src, chan_index) + emit(ELK_SHADER_OPCODE_BROADCAST, dst, src, chan_index) ->force_writemask_all = true; return src_reg(dst); @@ -812,15 +812,15 @@ vec4_visitor::emit_ndc_computation() /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */ dst_reg ndc = dst_reg(this, glsl_vec4_type()); - output_reg[BRW_VARYING_SLOT_NDC][0] = ndc; - output_num_components[BRW_VARYING_SLOT_NDC][0] = 4; + output_reg[ELK_VARYING_SLOT_NDC][0] = ndc; + output_num_components[ELK_VARYING_SLOT_NDC][0] = 4; current_annotation = "NDC"; dst_reg ndc_w = ndc; ndc_w.writemask = WRITEMASK_W; src_reg pos_w = pos; - pos_w.swizzle = BRW_SWIZZLE4(BRW_SWIZZLE_W, BRW_SWIZZLE_W, BRW_SWIZZLE_W, BRW_SWIZZLE_W); - emit_math(SHADER_OPCODE_RCP, ndc_w, pos_w); + pos_w.swizzle = ELK_SWIZZLE4(ELK_SWIZZLE_W, ELK_SWIZZLE_W, ELK_SWIZZLE_W, ELK_SWIZZLE_W); + emit_math(ELK_SHADER_OPCODE_RCP, ndc_w, pos_w); dst_reg ndc_xyz = ndc; ndc_xyz.writemask = WRITEMASK_XYZ; @@ -839,30 +839,30 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg) dst_reg header1_w = header1; header1_w.writemask = WRITEMASK_W; - emit(MOV(header1, brw_imm_ud(0u))); + emit(MOV(header1, elk_imm_ud(0u))); if (prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) { src_reg psiz = src_reg(output_reg[VARYING_SLOT_PSIZ][0]); current_annotation = "Point size"; - emit(MUL(header1_w, psiz, brw_imm_f((float)(1 << 11)))); - emit(AND(header1_w, src_reg(header1_w), brw_imm_d(0x7ff << 8))); + emit(MUL(header1_w, psiz, elk_imm_f((float)(1 << 11)))); + emit(AND(header1_w, src_reg(header1_w), elk_imm_d(0x7ff << 8))); } if (output_reg[VARYING_SLOT_CLIP_DIST0][0].file != BAD_FILE) { current_annotation = "Clipping flags"; dst_reg flags0 = dst_reg(this, glsl_uint_type()); - emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST0][0]), brw_imm_f(0.0f), BRW_CONDITIONAL_L)); - emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags0, brw_imm_d(0)); + emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST0][0]), elk_imm_f(0.0f), ELK_CONDITIONAL_L)); + emit(ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags0, elk_imm_d(0)); emit(OR(header1_w, src_reg(header1_w), src_reg(flags0))); } if (output_reg[VARYING_SLOT_CLIP_DIST1][0].file != BAD_FILE) { dst_reg flags1 = dst_reg(this, glsl_uint_type()); - emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST1][0]), brw_imm_f(0.0f), BRW_CONDITIONAL_L)); - emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags1, brw_imm_d(0)); - emit(SHL(flags1, src_reg(flags1), brw_imm_d(4))); + emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST1][0]), elk_imm_f(0.0f), ELK_CONDITIONAL_L)); + emit(ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags1, elk_imm_d(0)); + emit(SHL(flags1, src_reg(flags1), elk_imm_d(4))); emit(OR(header1_w, src_reg(header1_w), src_reg(flags1))); } @@ -876,42 +876,42 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg) * clipped against all fixed planes. */ if (devinfo->has_negative_rhw_bug && - output_reg[BRW_VARYING_SLOT_NDC][0].file != BAD_FILE) { - src_reg ndc_w = src_reg(output_reg[BRW_VARYING_SLOT_NDC][0]); - ndc_w.swizzle = BRW_SWIZZLE_WWWW; - emit(CMP(dst_null_f(), ndc_w, brw_imm_f(0.0f), BRW_CONDITIONAL_L)); + output_reg[ELK_VARYING_SLOT_NDC][0].file != BAD_FILE) { + src_reg ndc_w = src_reg(output_reg[ELK_VARYING_SLOT_NDC][0]); + ndc_w.swizzle = ELK_SWIZZLE_WWWW; + emit(CMP(dst_null_f(), ndc_w, elk_imm_f(0.0f), ELK_CONDITIONAL_L)); vec4_instruction *inst; - inst = emit(OR(header1_w, src_reg(header1_w), brw_imm_ud(1u << 6))); - inst->predicate = BRW_PREDICATE_NORMAL; - output_reg[BRW_VARYING_SLOT_NDC][0].type = BRW_REGISTER_TYPE_F; - inst = emit(MOV(output_reg[BRW_VARYING_SLOT_NDC][0], brw_imm_f(0.0f))); - inst->predicate = BRW_PREDICATE_NORMAL; + inst = emit(OR(header1_w, src_reg(header1_w), elk_imm_ud(1u << 6))); + inst->predicate = ELK_PREDICATE_NORMAL; + output_reg[ELK_VARYING_SLOT_NDC][0].type = ELK_REGISTER_TYPE_F; + inst = emit(MOV(output_reg[ELK_VARYING_SLOT_NDC][0], elk_imm_f(0.0f))); + inst->predicate = ELK_PREDICATE_NORMAL; } - emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1))); + emit(MOV(retype(reg, ELK_REGISTER_TYPE_UD), src_reg(header1))); } else if (devinfo->ver < 6) { - emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u))); + emit(MOV(retype(reg, ELK_REGISTER_TYPE_UD), elk_imm_ud(0u))); } else { - emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), brw_imm_d(0))); + emit(MOV(retype(reg, ELK_REGISTER_TYPE_D), elk_imm_d(0))); if (output_reg[VARYING_SLOT_PSIZ][0].file != BAD_FILE) { dst_reg reg_w = reg; reg_w.writemask = WRITEMASK_W; src_reg reg_as_src = src_reg(output_reg[VARYING_SLOT_PSIZ][0]); reg_as_src.type = reg_w.type; - reg_as_src.swizzle = brw_swizzle_for_size(1); + reg_as_src.swizzle = elk_swizzle_for_size(1); emit(MOV(reg_w, reg_as_src)); } if (output_reg[VARYING_SLOT_LAYER][0].file != BAD_FILE) { dst_reg reg_y = reg; reg_y.writemask = WRITEMASK_Y; - reg_y.type = BRW_REGISTER_TYPE_D; + reg_y.type = ELK_REGISTER_TYPE_D; output_reg[VARYING_SLOT_LAYER][0].type = reg_y.type; emit(MOV(reg_y, src_reg(output_reg[VARYING_SLOT_LAYER][0]))); } if (output_reg[VARYING_SLOT_VIEWPORT][0].file != BAD_FILE) { dst_reg reg_z = reg; reg_z.writemask = WRITEMASK_Z; - reg_z.type = BRW_REGISTER_TYPE_D; + reg_z.type = ELK_REGISTER_TYPE_D; output_reg[VARYING_SLOT_VIEWPORT][0].type = reg_z.type; emit(MOV(reg_z, src_reg(output_reg[VARYING_SLOT_VIEWPORT][0]))); } @@ -931,9 +931,9 @@ vec4_visitor::emit_generic_urb_slot(dst_reg reg, int varying, int component) current_annotation = output_reg_annotation[varying]; if (output_reg[varying][component].file != BAD_FILE) { src_reg src = src_reg(output_reg[varying][component]); - src.swizzle = BRW_SWZ_COMP_OUTPUT(component); + src.swizzle = ELK_SWZ_COMP_OUTPUT(component); reg.writemask = - brw_writemask_for_component_packing(num_comps, component); + elk_writemask_for_component_packing(num_comps, component); return emit(MOV(reg, src)); } return NULL; @@ -942,7 +942,7 @@ vec4_visitor::emit_generic_urb_slot(dst_reg reg, int varying, int component) void vec4_visitor::emit_urb_slot(dst_reg reg, int varying) { - reg.type = BRW_REGISTER_TYPE_F; + reg.type = ELK_REGISTER_TYPE_F; output_reg[varying][0].type = reg.type; switch (varying) { @@ -953,17 +953,17 @@ vec4_visitor::emit_urb_slot(dst_reg reg, int varying) emit_psiz_and_flags(reg); break; } - case BRW_VARYING_SLOT_NDC: + case ELK_VARYING_SLOT_NDC: current_annotation = "NDC"; - if (output_reg[BRW_VARYING_SLOT_NDC][0].file != BAD_FILE) - emit(MOV(reg, src_reg(output_reg[BRW_VARYING_SLOT_NDC][0]))); + if (output_reg[ELK_VARYING_SLOT_NDC][0].file != BAD_FILE) + emit(MOV(reg, src_reg(output_reg[ELK_VARYING_SLOT_NDC][0]))); break; case VARYING_SLOT_POS: current_annotation = "gl_Position"; if (output_reg[VARYING_SLOT_POS][0].file != BAD_FILE) emit(MOV(reg, src_reg(output_reg[VARYING_SLOT_POS][0]))); break; - case BRW_VARYING_SLOT_PAD: + case ELK_VARYING_SLOT_PAD: /* No need to write to this slot */ break; default: @@ -1050,7 +1050,7 @@ vec4_visitor::emit_vertex() * URB WRITE. Same thing if we reached the maximum length available. */ if (mrf > max_usable_mrf || - align_interleaved_urb_mlen(devinfo, mrf - base_mrf + 1) > BRW_MAX_MSG_LENGTH) { + align_interleaved_urb_mlen(devinfo, mrf - base_mrf + 1) > ELK_MAX_MSG_LENGTH) { slot++; break; } @@ -1067,7 +1067,7 @@ vec4_visitor::emit_vertex() src_reg -vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst, +vec4_visitor::get_scratch_offset(elk_bblock_t *block, vec4_instruction *inst, src_reg *reladdr, int reg_offset) { /* Because we store the values to scratch interleaved like our @@ -1090,18 +1090,18 @@ vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst, src_reg index = src_reg(this, glsl_int_type()); if (type_sz(inst->dst.type) < 8) { emit_before(block, inst, ADD(dst_reg(index), *reladdr, - brw_imm_d(reg_offset))); + elk_imm_d(reg_offset))); emit_before(block, inst, MUL(dst_reg(index), index, - brw_imm_d(message_header_scale))); + elk_imm_d(message_header_scale))); } else { emit_before(block, inst, MUL(dst_reg(index), *reladdr, - brw_imm_d(message_header_scale * 2))); + elk_imm_d(message_header_scale * 2))); emit_before(block, inst, ADD(dst_reg(index), index, - brw_imm_d(reg_offset * message_header_scale))); + elk_imm_d(reg_offset * message_header_scale))); } return index; } else { - return brw_imm_d(reg_offset * message_header_scale); + return elk_imm_d(reg_offset * message_header_scale); } } @@ -1112,7 +1112,7 @@ vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst, * @base_offset is measured in 32-byte units (the size of a register). */ void -vec4_visitor::emit_scratch_read(bblock_t *block, vec4_instruction *inst, +vec4_visitor::emit_scratch_read(elk_bblock_t *block, vec4_instruction *inst, dst_reg temp, src_reg orig_src, int base_offset) { @@ -1125,7 +1125,7 @@ vec4_visitor::emit_scratch_read(bblock_t *block, vec4_instruction *inst, emit_before(block, inst, SCRATCH_READ(temp, index)); } else { dst_reg shuffled = dst_reg(this, glsl_dvec4_type()); - dst_reg shuffled_float = retype(shuffled, BRW_REGISTER_TYPE_F); + dst_reg shuffled_float = retype(shuffled, ELK_REGISTER_TYPE_F); emit_before(block, inst, SCRATCH_READ(shuffled_float, index)); index = get_scratch_offset(block, inst, orig_src.reladdr, reg_offset + 1); vec4_instruction *last_read = @@ -1142,7 +1142,7 @@ vec4_visitor::emit_scratch_read(bblock_t *block, vec4_instruction *inst, * @base_offset is measured in 32-byte units (the size of a register). */ void -vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst, +vec4_visitor::emit_scratch_write(elk_bblock_t *block, vec4_instruction *inst, int base_offset) { assert(inst->dst.offset % REG_SIZE == 0); @@ -1162,13 +1162,13 @@ vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst, is_64bit ? glsl_dvec4_type() : glsl_vec4_type(); const src_reg temp = swizzle(retype(src_reg(this, alloc_type), inst->dst.type), - brw_swizzle_for_mask(inst->dst.writemask)); + elk_swizzle_for_mask(inst->dst.writemask)); if (!is_64bit) { - dst_reg dst = dst_reg(brw_writemask(brw_vec8_grf(0, 0), + dst_reg dst = dst_reg(elk_writemask(elk_vec8_grf(0, 0), inst->dst.writemask)); vec4_instruction *write = SCRATCH_WRITE(dst, temp, index); - if (inst->opcode != BRW_OPCODE_SEL) + if (inst->opcode != ELK_OPCODE_SEL) write->predicate = inst->predicate; write->ir = inst->ir; write->annotation = inst->annotation; @@ -1177,7 +1177,7 @@ vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst, dst_reg shuffled = dst_reg(this, alloc_type); vec4_instruction *last = shuffle_64bit_data(shuffled, temp, true, true, block, inst); - src_reg shuffled_float = src_reg(retype(shuffled, BRW_REGISTER_TYPE_F)); + src_reg shuffled_float = src_reg(retype(shuffled, ELK_REGISTER_TYPE_F)); uint8_t mask = 0; if (inst->dst.writemask & WRITEMASK_X) @@ -1185,10 +1185,10 @@ vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst, if (inst->dst.writemask & WRITEMASK_Y) mask |= WRITEMASK_ZW; if (mask) { - dst_reg dst = dst_reg(brw_writemask(brw_vec8_grf(0, 0), mask)); + dst_reg dst = dst_reg(elk_writemask(elk_vec8_grf(0, 0), mask)); vec4_instruction *write = SCRATCH_WRITE(dst, shuffled_float, index); - if (inst->opcode != BRW_OPCODE_SEL) + if (inst->opcode != ELK_OPCODE_SEL) write->predicate = inst->predicate; write->ir = inst->ir; write->annotation = inst->annotation; @@ -1201,13 +1201,13 @@ vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst, if (inst->dst.writemask & WRITEMASK_W) mask |= WRITEMASK_ZW; if (mask) { - dst_reg dst = dst_reg(brw_writemask(brw_vec8_grf(0, 0), mask)); + dst_reg dst = dst_reg(elk_writemask(elk_vec8_grf(0, 0), mask)); src_reg index = get_scratch_offset(block, inst, inst->dst.reladdr, reg_offset + 1); vec4_instruction *write = SCRATCH_WRITE(dst, byte_offset(shuffled_float, REG_SIZE), index); - if (inst->opcode != BRW_OPCODE_SEL) + if (inst->opcode != ELK_OPCODE_SEL) write->predicate = inst->predicate; write->ir = inst->ir; write->annotation = inst->annotation; @@ -1232,7 +1232,7 @@ vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst, * use to rewrite src. */ src_reg -vec4_visitor::emit_resolve_reladdr(int scratch_loc[], bblock_t *block, +vec4_visitor::emit_resolve_reladdr(int scratch_loc[], elk_bblock_t *block, vec4_instruction *inst, src_reg src) { /* Resolve recursive reladdr scratch access by calling ourselves @@ -1338,23 +1338,23 @@ vec4_visitor::move_grf_array_access_to_scratch() void vec4_visitor::resolve_ud_negate(src_reg *reg) { - if (reg->type != BRW_REGISTER_TYPE_UD || + if (reg->type != ELK_REGISTER_TYPE_UD || !reg->negate) return; src_reg temp = src_reg(this, glsl_uvec4_type()); - emit(BRW_OPCODE_MOV, dst_reg(temp), *reg); + emit(ELK_OPCODE_MOV, dst_reg(temp), *reg); *reg = temp; } -static brw_rnd_mode -brw_rnd_mode_from_execution_mode(unsigned execution_mode) +static elk_rnd_mode +elk_rnd_mode_from_execution_mode(unsigned execution_mode) { if (nir_has_any_rounding_mode_rtne(execution_mode)) - return BRW_RND_MODE_RTNE; + return ELK_RND_MODE_RTNE; if (nir_has_any_rounding_mode_rtz(execution_mode)) - return BRW_RND_MODE_RTZ; - return BRW_RND_MODE_UNSPECIFIED; + return ELK_RND_MODE_RTZ; + return ELK_RND_MODE_UNSPECIFIED; } void @@ -1362,20 +1362,20 @@ vec4_visitor::emit_shader_float_controls_execution_mode() { unsigned execution_mode = this->nir->info.float_controls_execution_mode; if (nir_has_any_rounding_mode_enabled(execution_mode)) { - brw_rnd_mode rnd = brw_rnd_mode_from_execution_mode(execution_mode); + elk_rnd_mode rnd = elk_rnd_mode_from_execution_mode(execution_mode); const vec4_builder bld = vec4_builder(this).at_end(); - bld.exec_all().emit(SHADER_OPCODE_RND_MODE, dst_null_ud(), brw_imm_d(rnd)); + bld.exec_all().emit(ELK_SHADER_OPCODE_RND_MODE, dst_null_ud(), elk_imm_d(rnd)); } } -vec4_visitor::vec4_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const struct brw_sampler_prog_key_data *key_tex, - struct brw_vue_prog_data *prog_data, +vec4_visitor::vec4_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const struct elk_sampler_prog_key_data *key_tex, + struct elk_vue_prog_data *prog_data, const nir_shader *shader, bool no_spills, bool debug_enabled) - : backend_shader(compiler, params, shader, &prog_data->base, debug_enabled), + : elk_backend_shader(compiler, params, shader, &prog_data->base, debug_enabled), key_tex(key_tex), prog_data(prog_data), fail_msg(NULL), @@ -1394,7 +1394,7 @@ vec4_visitor::vec4_visitor(const struct brw_compiler *compiler, memset(this->output_num_components, 0, sizeof(this->output_num_components)); - this->max_grf = devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF; + this->max_grf = devinfo->ver >= 7 ? GFX7_MRF_HACK_START : ELK_MAX_GRF; this->uniforms = 0; diff --git a/src/intel/compiler/elk/elk_vec4_vs.h b/src/intel/compiler/elk/elk_vec4_vs.h index df93923cc03..f50ab9dabae 100644 --- a/src/intel/compiler/elk/elk_vec4_vs.h +++ b/src/intel/compiler/elk/elk_vec4_vs.h @@ -31,10 +31,10 @@ namespace elk { class vec4_vs_visitor : public vec4_visitor { public: - vec4_vs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const struct brw_vs_prog_key *key, - struct brw_vs_prog_data *vs_prog_data, + vec4_vs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const struct elk_vs_prog_key *key, + struct elk_vs_prog_data *vs_prog_data, const nir_shader *shader, bool debug_enabled); @@ -49,8 +49,8 @@ protected: private: int setup_attributes(int payload_reg); - const struct brw_vs_prog_key *const key; - struct brw_vs_prog_data * const vs_prog_data; + const struct elk_vs_prog_key *const key; + struct elk_vs_prog_data * const vs_prog_data; }; } /* namespace elk */ diff --git a/src/intel/compiler/elk/elk_vec4_vs_visitor.cpp b/src/intel/compiler/elk/elk_vec4_vs_visitor.cpp index fb34fb11433..90beef1fe0f 100644 --- a/src/intel/compiler/elk/elk_vec4_vs_visitor.cpp +++ b/src/intel/compiler/elk/elk_vec4_vs_visitor.cpp @@ -37,7 +37,7 @@ void vec4_vs_visitor::emit_urb_write_header(int mrf) { /* No need to do anything for VS; an implied write to this MRF will be - * performed by VEC4_VS_OPCODE_URB_WRITE. + * performed by ELK_VEC4_VS_OPCODE_URB_WRITE. */ (void) mrf; } @@ -46,9 +46,9 @@ vec4_vs_visitor::emit_urb_write_header(int mrf) vec4_instruction * vec4_vs_visitor::emit_urb_write_opcode(bool complete) { - vec4_instruction *inst = emit(VEC4_VS_OPCODE_URB_WRITE); + vec4_instruction *inst = emit(ELK_VEC4_VS_OPCODE_URB_WRITE); inst->urb_write_flags = complete ? - BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS; + ELK_URB_WRITE_EOT_COMPLETE : ELK_URB_WRITE_NO_FLAGS; return inst; } @@ -57,7 +57,7 @@ vec4_vs_visitor::emit_urb_write_opcode(bool complete) void vec4_vs_visitor::emit_urb_slot(dst_reg reg, int varying) { - reg.type = BRW_REGISTER_TYPE_F; + reg.type = ELK_REGISTER_TYPE_F; output_reg[varying][0].type = reg.type; switch (varying) { @@ -91,10 +91,10 @@ vec4_vs_visitor::emit_thread_end() } -vec4_vs_visitor::vec4_vs_visitor(const struct brw_compiler *compiler, - const struct brw_compile_params *params, - const struct brw_vs_prog_key *key, - struct brw_vs_prog_data *vs_prog_data, +vec4_vs_visitor::vec4_vs_visitor(const struct elk_compiler *compiler, + const struct elk_compile_params *params, + const struct elk_vs_prog_key *key, + struct elk_vs_prog_data *vs_prog_data, const nir_shader *shader, bool debug_enabled) : vec4_visitor(compiler, params, &key->base.tex, &vs_prog_data->base, diff --git a/src/intel/compiler/elk/elk_vue_map.c b/src/intel/compiler/elk/elk_vue_map.c index a9c8768cef0..bb8f751ce83 100644 --- a/src/intel/compiler/elk/elk_vue_map.c +++ b/src/intel/compiler/elk/elk_vue_map.c @@ -57,7 +57,7 @@ assign_vue_slot(struct intel_vue_map *vue_map, int varying, int slot) * Compute the VUE map for a shader stage. */ void -brw_compute_vue_map(const struct intel_device_info *devinfo, +elk_compute_vue_map(const struct intel_device_info *devinfo, struct intel_vue_map *vue_map, uint64_t slots_valid, bool separate, @@ -95,14 +95,14 @@ brw_compute_vue_map(const struct intel_device_info *devinfo, /* Make sure that the values we store in vue_map->varying_to_slot and * vue_map->slot_to_varying won't overflow the signed chars that are used * to store them. Note that since vue_map->slot_to_varying sometimes holds - * values equal to BRW_VARYING_SLOT_COUNT, we need to ensure that - * BRW_VARYING_SLOT_COUNT is <= 127, not 128. + * values equal to ELK_VARYING_SLOT_COUNT, we need to ensure that + * ELK_VARYING_SLOT_COUNT is <= 127, not 128. */ - STATIC_ASSERT(BRW_VARYING_SLOT_COUNT <= 127); + STATIC_ASSERT(ELK_VARYING_SLOT_COUNT <= 127); - for (int i = 0; i < BRW_VARYING_SLOT_COUNT; ++i) { + for (int i = 0; i < ELK_VARYING_SLOT_COUNT; ++i) { vue_map->varying_to_slot[i] = -1; - vue_map->slot_to_varying[i] = BRW_VARYING_SLOT_PAD; + vue_map->slot_to_varying[i] = ELK_VARYING_SLOT_PAD; } int slot = 0; @@ -123,7 +123,7 @@ brw_compute_vue_map(const struct intel_device_info *devinfo, * will accept the same header layout as Gfx4 [and should be a bit faster] */ assign_vue_slot(vue_map, VARYING_SLOT_PSIZ, slot++); - assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC, slot++); + assign_vue_slot(vue_map, ELK_VARYING_SLOT_NDC, slot++); assign_vue_slot(vue_map, VARYING_SLOT_POS, slot++); } else { /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge: @@ -216,7 +216,7 @@ brw_compute_vue_map(const struct intel_device_info *devinfo, * tessellation evaluation shader inputs. */ void -brw_compute_tess_vue_map(struct intel_vue_map *vue_map, +elk_compute_tess_vue_map(struct intel_vue_map *vue_map, uint64_t vertex_slots, uint32_t patch_slots) { @@ -239,7 +239,7 @@ brw_compute_tess_vue_map(struct intel_vue_map *vue_map, for (int i = 0; i < VARYING_SLOT_TESS_MAX ; ++i) { vue_map->varying_to_slot[i] = -1; - vue_map->slot_to_varying[i] = BRW_VARYING_SLOT_PAD; + vue_map->slot_to_varying[i] = ELK_VARYING_SLOT_PAD; } int slot = 0; @@ -281,24 +281,24 @@ brw_compute_tess_vue_map(struct intel_vue_map *vue_map, } static const char * -varying_name(brw_varying_slot slot, gl_shader_stage stage) +varying_name(elk_varying_slot slot, gl_shader_stage stage) { - assume(slot < BRW_VARYING_SLOT_COUNT); + assume(slot < ELK_VARYING_SLOT_COUNT); if (slot < VARYING_SLOT_MAX) return gl_varying_slot_name_for_stage((gl_varying_slot)slot, stage); - static const char *brw_names[] = { - [BRW_VARYING_SLOT_NDC - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_NDC", - [BRW_VARYING_SLOT_PAD - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_PAD", - [BRW_VARYING_SLOT_PNTC - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_PNTC", + static const char *elk_names[] = { + [ELK_VARYING_SLOT_NDC - VARYING_SLOT_MAX] = "ELK_VARYING_SLOT_NDC", + [ELK_VARYING_SLOT_PAD - VARYING_SLOT_MAX] = "ELK_VARYING_SLOT_PAD", + [ELK_VARYING_SLOT_PNTC - VARYING_SLOT_MAX] = "ELK_VARYING_SLOT_PNTC", }; - return brw_names[slot - VARYING_SLOT_MAX]; + return elk_names[slot - VARYING_SLOT_MAX]; } void -brw_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, +elk_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, gl_shader_stage stage) { if (vue_map->num_per_vertex_slots > 0 || vue_map->num_per_patch_slots > 0) {