radeonsi: Add radeon_bitstream and use it in radeon_vcn_enc
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32829>
This commit is contained in:
David Rosca
@@ -101,6 +101,8 @@ files_libradeonsi = files(
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'radeon_vcn_enc_5_0.c',
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'radeon_video.c',
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'radeon_video.h',
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'radeon_bitstream.h',
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'radeon_bitstream.c',
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)
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radeonsi_include_dirs = [inc_src, inc_include, inc_gallium, inc_gallium_aux, inc_amd_common,
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@@ -0,0 +1,349 @@
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "radeon_bitstream.h"
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static const uint32_t index_to_shifts[4] = {24, 16, 8, 0};
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static void radeon_bs_output_one_byte(struct radeon_bitstream *bs, uint8_t byte)
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{
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if (bs->buf) {
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*(bs->buf++) = byte;
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return;
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}
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if (bs->byte_index == 0)
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bs->cs->current.buf[bs->cs->current.cdw] = 0;
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bs->cs->current.buf[bs->cs->current.cdw] |=
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((uint32_t)(byte) << index_to_shifts[bs->byte_index]);
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bs->byte_index++;
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if (bs->byte_index >= 4) {
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bs->byte_index = 0;
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bs->cs->current.cdw++;
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}
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}
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static void radeon_bs_emulation_prevention(struct radeon_bitstream *bs, uint8_t byte)
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{
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if (bs->emulation_prevention) {
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if ((bs->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) ||
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(byte == 0x02) || (byte == 0x03))) {
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radeon_bs_output_one_byte(bs, 0x03);
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bs->bits_output += 8;
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bs->num_zeros = 0;
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}
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bs->num_zeros = (byte == 0 ? (bs->num_zeros + 1) : 0);
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}
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}
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void radeon_bs_reset(struct radeon_bitstream *bs, uint8_t *out, struct radeon_cmdbuf *cs)
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{
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memset(bs, 0, sizeof(*bs));
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bs->buf = out;
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bs->cs = cs;
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}
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void radeon_bs_set_emulation_prevention(struct radeon_bitstream *bs, bool set)
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{
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if (set != bs->emulation_prevention) {
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bs->emulation_prevention = set;
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bs->num_zeros = 0;
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}
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}
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void radeon_bs_byte_align(struct radeon_bitstream *bs)
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{
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uint32_t num_padding_zeros = (32 - bs->bits_in_shifter) % 8;
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if (num_padding_zeros > 0)
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radeon_bs_code_fixed_bits(bs, 0, num_padding_zeros);
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}
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void radeon_bs_flush_headers(struct radeon_bitstream *bs)
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{
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if (bs->bits_in_shifter != 0) {
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uint8_t output_byte = bs->shifter >> 24;
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radeon_bs_emulation_prevention(bs, output_byte);
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radeon_bs_output_one_byte(bs, output_byte);
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bs->bits_output += bs->bits_in_shifter;
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bs->shifter = 0;
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bs->bits_in_shifter = 0;
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bs->num_zeros = 0;
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}
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if (bs->byte_index > 0) {
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bs->cs->current.cdw++;
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bs->byte_index = 0;
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}
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}
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void radeon_bs_code_fixed_bits(struct radeon_bitstream *bs, uint32_t value, uint32_t num_bits)
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{
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uint32_t bits_to_pack = 0;
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bs->bits_size += num_bits;
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while (num_bits > 0) {
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uint32_t value_to_pack = value & (0xffffffff >> (32 - num_bits));
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bits_to_pack =
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num_bits > (32 - bs->bits_in_shifter) ? (32 - bs->bits_in_shifter) : num_bits;
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if (bits_to_pack < num_bits)
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value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
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bs->shifter |= value_to_pack << (32 - bs->bits_in_shifter - bits_to_pack);
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num_bits -= bits_to_pack;
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bs->bits_in_shifter += bits_to_pack;
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while (bs->bits_in_shifter >= 8) {
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uint8_t output_byte = bs->shifter >> 24;
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bs->shifter <<= 8;
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radeon_bs_emulation_prevention(bs, output_byte);
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radeon_bs_output_one_byte(bs, output_byte);
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bs->bits_in_shifter -= 8;
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bs->bits_output += 8;
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}
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}
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}
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void radeon_bs_code_ue(struct radeon_bitstream *bs, uint32_t value)
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{
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uint32_t x = 0;
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uint32_t ue_code = value + 1;
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value += 1;
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while (value) {
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value = value >> 1;
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x += 1;
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}
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if (x > 1)
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radeon_bs_code_fixed_bits(bs, 0, x - 1);
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radeon_bs_code_fixed_bits(bs, ue_code, x);
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}
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void radeon_bs_code_se(struct radeon_bitstream *bs, int32_t value)
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{
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uint32_t v = 0;
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if (value != 0)
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v = (value < 0 ? ((uint32_t)(0 - value) << 1) : (((uint32_t)(value) << 1) - 1));
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radeon_bs_code_ue(bs, v);
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}
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void radeon_bs_code_uvlc(struct radeon_bitstream *bs, uint32_t value)
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{
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uint32_t num_bits = 0;
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uint64_t value_plus1 = (uint64_t)value + 1;
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uint32_t num_leading_zeros = 0;
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while ((uint64_t)1 << num_bits <= value_plus1)
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num_bits++;
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num_leading_zeros = num_bits - 1;
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radeon_bs_code_fixed_bits(bs, 0, num_leading_zeros);
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radeon_bs_code_fixed_bits(bs, 1, 1);
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radeon_bs_code_fixed_bits(bs, (uint32_t)value_plus1, num_leading_zeros);
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}
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void radeon_bs_code_ns(struct radeon_bitstream *bs, uint32_t value, uint32_t max)
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{
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uint32_t w = 0;
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uint32_t m;
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uint32_t max_num = max;
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while ( max_num ) {
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max_num >>= 1;
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w++;
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}
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m = (1 << w) - max;
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assert(w > 1);
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if (value < m) {
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radeon_bs_code_fixed_bits(bs, value, (w - 1));
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} else {
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uint32_t diff = value - m;
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uint32_t out = (((diff >> 1) + m) << 1) | (diff & 0x1);
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radeon_bs_code_fixed_bits(bs, out, w);
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}
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}
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void radeon_bs_h264_hrd_parameters(struct radeon_bitstream *bs,
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struct pipe_h264_enc_hrd_params *hrd)
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{
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radeon_bs_code_ue(bs, hrd->cpb_cnt_minus1);
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radeon_bs_code_fixed_bits(bs, hrd->bit_rate_scale, 4);
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radeon_bs_code_fixed_bits(bs, hrd->cpb_size_scale, 4);
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for (uint32_t i = 0; i <= hrd->cpb_cnt_minus1; i++) {
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radeon_bs_code_ue(bs, hrd->bit_rate_value_minus1[i]);
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radeon_bs_code_ue(bs, hrd->cpb_size_value_minus1[i]);
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radeon_bs_code_fixed_bits(bs, hrd->cbr_flag[i], 1);
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}
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radeon_bs_code_fixed_bits(bs, hrd->initial_cpb_removal_delay_length_minus1, 5);
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radeon_bs_code_fixed_bits(bs, hrd->cpb_removal_delay_length_minus1, 5);
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radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_length_minus1, 5);
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radeon_bs_code_fixed_bits(bs, hrd->time_offset_length, 5);
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}
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static void radeon_bs_hevc_profile_tier(struct radeon_bitstream *bs,
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struct pipe_h265_profile_tier *pt)
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{
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radeon_bs_code_fixed_bits(bs, pt->general_profile_space, 2);
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radeon_bs_code_fixed_bits(bs, pt->general_tier_flag, 1);
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radeon_bs_code_fixed_bits(bs, pt->general_profile_idc, 5);
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radeon_bs_code_fixed_bits(bs, pt->general_profile_compatibility_flag, 32);
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radeon_bs_code_fixed_bits(bs, pt->general_progressive_source_flag, 1);
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radeon_bs_code_fixed_bits(bs, pt->general_interlaced_source_flag, 1);
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radeon_bs_code_fixed_bits(bs, pt->general_non_packed_constraint_flag, 1);
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radeon_bs_code_fixed_bits(bs, pt->general_frame_only_constraint_flag, 1);
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/* general_reserved_zero_44bits */
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radeon_bs_code_fixed_bits(bs, 0x0, 16);
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radeon_bs_code_fixed_bits(bs, 0x0, 16);
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radeon_bs_code_fixed_bits(bs, 0x0, 12);
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}
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void radeon_bs_hevc_profile_tier_level(struct radeon_bitstream *bs,
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uint32_t max_num_sub_layers_minus1,
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struct pipe_h265_profile_tier_level *ptl)
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{
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uint32_t i;
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radeon_bs_hevc_profile_tier(bs, &ptl->profile_tier);
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radeon_bs_code_fixed_bits(bs, ptl->general_level_idc, 8);
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for (i = 0; i < max_num_sub_layers_minus1; ++i) {
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radeon_bs_code_fixed_bits(bs, ptl->sub_layer_profile_present_flag[i], 1);
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radeon_bs_code_fixed_bits(bs, ptl->sub_layer_level_present_flag[i], 1);
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}
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if (max_num_sub_layers_minus1 > 0) {
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for (i = max_num_sub_layers_minus1; i < 8; ++i)
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radeon_bs_code_fixed_bits(bs, 0x0, 2); /* reserved_zero_2bits */
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}
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for (i = 0; i < max_num_sub_layers_minus1; ++i) {
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if (ptl->sub_layer_profile_present_flag[i])
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radeon_bs_hevc_profile_tier(bs, &ptl->sub_layer_profile_tier[i]);
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if (ptl->sub_layer_level_present_flag[i])
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radeon_bs_code_fixed_bits(bs, ptl->sub_layer_level_idc[i], 8);
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}
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}
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static void radeon_bs_hevc_sub_layer_hrd_parameters(struct radeon_bitstream *bs,
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uint32_t cpb_cnt,
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uint32_t sub_pic_hrd_params_present_flag,
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struct pipe_h265_enc_sublayer_hrd_params *hrd)
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{
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for (uint32_t i = 0; i < cpb_cnt; i++) {
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radeon_bs_code_ue(bs, hrd->bit_rate_value_minus1[i]);
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radeon_bs_code_ue(bs, hrd->cpb_size_value_minus1[i]);
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if (sub_pic_hrd_params_present_flag) {
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radeon_bs_code_ue(bs, hrd->cpb_size_du_value_minus1[i]);
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radeon_bs_code_ue(bs, hrd->bit_rate_du_value_minus1[i]);
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}
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radeon_bs_code_fixed_bits(bs, hrd->cbr_flag[i], 1);
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}
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}
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void radeon_bs_hevc_hrd_parameters(struct radeon_bitstream *bs,
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uint32_t common_inf_present_flag,
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uint32_t max_sub_layers_minus1,
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struct pipe_h265_enc_hrd_params *hrd)
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{
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if (common_inf_present_flag) {
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radeon_bs_code_fixed_bits(bs, hrd->nal_hrd_parameters_present_flag, 1);
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radeon_bs_code_fixed_bits(bs, hrd->vcl_hrd_parameters_present_flag, 1);
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if (hrd->nal_hrd_parameters_present_flag || hrd->vcl_hrd_parameters_present_flag) {
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radeon_bs_code_fixed_bits(bs, hrd->sub_pic_hrd_params_present_flag, 1);
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if (hrd->sub_pic_hrd_params_present_flag) {
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radeon_bs_code_fixed_bits(bs, hrd->tick_divisor_minus2, 8);
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radeon_bs_code_fixed_bits(bs, hrd->du_cpb_removal_delay_increment_length_minus1, 5);
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radeon_bs_code_fixed_bits(bs, hrd->sub_pic_hrd_params_present_flag, 1);
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radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_du_length_minus1, 5);
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}
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radeon_bs_code_fixed_bits(bs, hrd->bit_rate_scale, 4);
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radeon_bs_code_fixed_bits(bs, hrd->cpb_rate_scale, 4);
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if (hrd->sub_pic_hrd_params_present_flag)
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radeon_bs_code_fixed_bits(bs, hrd->cpb_size_du_scale, 4);
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radeon_bs_code_fixed_bits(bs, hrd->initial_cpb_removal_delay_length_minus1, 5);
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radeon_bs_code_fixed_bits(bs, hrd->au_cpb_removal_delay_length_minus1, 5);
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radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_length_minus1, 5);
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}
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}
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for (uint32_t i = 0; i <= max_sub_layers_minus1; i++) {
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radeon_bs_code_fixed_bits(bs, hrd->fixed_pic_rate_general_flag[i], 1);
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if (!hrd->fixed_pic_rate_general_flag[i])
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radeon_bs_code_fixed_bits(bs, hrd->fixed_pic_rate_within_cvs_flag[i], 1);
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if (hrd->fixed_pic_rate_within_cvs_flag[i])
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radeon_bs_code_ue(bs, hrd->elemental_duration_in_tc_minus1[i]);
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else
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radeon_bs_code_fixed_bits(bs, hrd->low_delay_hrd_flag[i], 1);
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if (!hrd->low_delay_hrd_flag[i])
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radeon_bs_code_ue(bs, hrd->cpb_cnt_minus1[i]);
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if (hrd->nal_hrd_parameters_present_flag) {
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radeon_bs_hevc_sub_layer_hrd_parameters(bs,
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hrd->cpb_cnt_minus1[i] + 1,
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hrd->sub_pic_hrd_params_present_flag,
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&hrd->nal_hrd_parameters[i]);
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}
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if (hrd->vcl_hrd_parameters_present_flag) {
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radeon_bs_hevc_sub_layer_hrd_parameters(bs,
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hrd->cpb_cnt_minus1[i] + 1,
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hrd->sub_pic_hrd_params_present_flag,
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&hrd->vlc_hrd_parameters[i]);
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}
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}
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}
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/* returns NumPicTotalCurr */
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uint32_t radeon_bs_hevc_st_ref_pic_set(struct radeon_bitstream *bs,
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uint32_t index,
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uint32_t num_short_term_ref_pic_sets,
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struct pipe_h265_st_ref_pic_set *st_rps)
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{
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struct pipe_h265_st_ref_pic_set *ref_rps = NULL;
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struct pipe_h265_st_ref_pic_set *rps = &st_rps[index];
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uint32_t i, num_pic_total_curr = 0;
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if (index)
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radeon_bs_code_fixed_bits(bs, rps->inter_ref_pic_set_prediction_flag, 1);
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if (rps->inter_ref_pic_set_prediction_flag) {
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if (index == num_short_term_ref_pic_sets)
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radeon_bs_code_ue(bs, rps->delta_idx_minus1);
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radeon_bs_code_fixed_bits(bs, rps->delta_rps_sign, 1);
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radeon_bs_code_ue(bs, rps->abs_delta_rps_minus1);
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ref_rps = st_rps + index +
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(1 - 2 * rps->delta_rps_sign) * (st_rps->delta_idx_minus1 + 1);
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for (i = 0; i <= (ref_rps->num_negative_pics + ref_rps->num_positive_pics); i++) {
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radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_flag[i], 1);
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if (!rps->used_by_curr_pic_flag[i])
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radeon_bs_code_fixed_bits(bs, rps->use_delta_flag[i], 1);
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}
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} else {
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radeon_bs_code_ue(bs, rps->num_negative_pics);
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radeon_bs_code_ue(bs, rps->num_positive_pics);
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for (i = 0; i < rps->num_negative_pics; i++) {
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radeon_bs_code_ue(bs, rps->delta_poc_s0_minus1[i]);
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radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_s0_flag[i], 1);
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if (rps->used_by_curr_pic_s0_flag[i])
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num_pic_total_curr++;
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}
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for (i = 0; i < st_rps->num_positive_pics; i++) {
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radeon_bs_code_ue(bs, rps->delta_poc_s1_minus1[i]);
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radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_s1_flag[i], 1);
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if (rps->used_by_curr_pic_s1_flag[i])
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num_pic_total_curr++;
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}
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}
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return num_pic_total_curr;
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}
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@@ -0,0 +1,53 @@
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADEON_BITSTREAM_H
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#define RADEON_BITSTREAM_H
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#include "pipe/p_video_state.h"
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#include "winsys/radeon_winsys.h"
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struct radeon_bitstream {
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bool emulation_prevention;
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uint32_t shifter;
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uint32_t bits_in_shifter;
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uint32_t num_zeros;
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uint32_t byte_index;
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uint32_t bits_output;
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uint32_t bits_size;
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uint8_t *buf;
|
||||
struct radeon_cmdbuf *cs;
|
||||
};
|
||||
|
||||
void radeon_bs_reset(struct radeon_bitstream *bs, uint8_t *out, struct radeon_cmdbuf *cs);
|
||||
void radeon_bs_set_emulation_prevention(struct radeon_bitstream *bs, bool set);
|
||||
void radeon_bs_byte_align(struct radeon_bitstream *bs);
|
||||
void radeon_bs_flush_headers(struct radeon_bitstream *bs);
|
||||
|
||||
void radeon_bs_code_fixed_bits(struct radeon_bitstream *bs, uint32_t value, uint32_t num_bits);
|
||||
void radeon_bs_code_ue(struct radeon_bitstream *bs, uint32_t value);
|
||||
void radeon_bs_code_se(struct radeon_bitstream *bs, int32_t value);
|
||||
void radeon_bs_code_uvlc(struct radeon_bitstream *bs, uint32_t value);
|
||||
void radeon_bs_code_ns(struct radeon_bitstream *bs, uint32_t value, uint32_t max);
|
||||
|
||||
void radeon_bs_h264_hrd_parameters(struct radeon_bitstream *bs,
|
||||
struct pipe_h264_enc_hrd_params *hrd);
|
||||
|
||||
void radeon_bs_hevc_profile_tier_level(struct radeon_bitstream *bs,
|
||||
uint32_t max_num_sub_layers_minus1,
|
||||
struct pipe_h265_profile_tier_level *ptl);
|
||||
|
||||
void radeon_bs_hevc_hrd_parameters(struct radeon_bitstream *bs,
|
||||
uint32_t common_inf_present_flag,
|
||||
uint32_t max_sub_layers_minus1,
|
||||
struct pipe_h265_enc_hrd_params *hrd);
|
||||
|
||||
uint32_t radeon_bs_hevc_st_ref_pic_set(struct radeon_bitstream *bs,
|
||||
uint32_t index,
|
||||
uint32_t num_short_term_ref_pic_sets,
|
||||
struct pipe_h265_st_ref_pic_set *st_rps);
|
||||
|
||||
#endif
|
||||
@@ -17,8 +17,6 @@
|
||||
#include "util/u_video.h"
|
||||
#include "vl/vl_video_buffer.h"
|
||||
|
||||
static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
|
||||
|
||||
/* set quality modes from the input */
|
||||
static void radeon_vcn_enc_quality_modes(struct radeon_encoder *enc,
|
||||
struct pipe_enc_quality_modes *in)
|
||||
@@ -1980,7 +1978,6 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
|
||||
enc->base.fence_wait = radeon_enc_fence_wait;
|
||||
enc->base.destroy_fence = radeon_enc_destroy_fence;
|
||||
enc->get_buffer = get_buffer;
|
||||
enc->bits_in_shifter = 0;
|
||||
enc->screen = context->screen;
|
||||
enc->ws = ws;
|
||||
|
||||
@@ -2048,96 +2045,6 @@ void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *bu
|
||||
RADEON_ENC_CS(addr);
|
||||
}
|
||||
|
||||
void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set)
|
||||
{
|
||||
if (set != enc->emulation_prevention) {
|
||||
enc->emulation_prevention = set;
|
||||
enc->num_zeros = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void radeon_enc_set_output_buffer(struct radeon_encoder *enc, uint8_t *buffer)
|
||||
{
|
||||
enc->bits_buf = buffer;
|
||||
enc->bits_buf_pos = 0;
|
||||
}
|
||||
|
||||
void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
|
||||
{
|
||||
if (enc->bits_buf) {
|
||||
enc->bits_buf[enc->bits_buf_pos++] = byte;
|
||||
return;
|
||||
}
|
||||
|
||||
if (enc->byte_index == 0)
|
||||
enc->cs.current.buf[enc->cs.current.cdw] = 0;
|
||||
enc->cs.current.buf[enc->cs.current.cdw] |=
|
||||
((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
|
||||
enc->byte_index++;
|
||||
|
||||
if (enc->byte_index >= 4) {
|
||||
enc->byte_index = 0;
|
||||
enc->cs.current.cdw++;
|
||||
}
|
||||
}
|
||||
|
||||
void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte)
|
||||
{
|
||||
if (enc->emulation_prevention) {
|
||||
if ((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) ||
|
||||
(byte == 0x02) || (byte == 0x03))) {
|
||||
radeon_enc_output_one_byte(enc, 0x03);
|
||||
enc->bits_output += 8;
|
||||
enc->num_zeros = 0;
|
||||
}
|
||||
enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
|
||||
}
|
||||
}
|
||||
|
||||
void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
|
||||
unsigned int num_bits)
|
||||
{
|
||||
unsigned int bits_to_pack = 0;
|
||||
enc->bits_size += num_bits;
|
||||
|
||||
while (num_bits > 0) {
|
||||
unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
|
||||
bits_to_pack =
|
||||
num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
|
||||
|
||||
if (bits_to_pack < num_bits)
|
||||
value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
|
||||
|
||||
enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
|
||||
num_bits -= bits_to_pack;
|
||||
enc->bits_in_shifter += bits_to_pack;
|
||||
|
||||
while (enc->bits_in_shifter >= 8) {
|
||||
unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
|
||||
enc->shifter <<= 8;
|
||||
radeon_enc_emulation_prevention(enc, output_byte);
|
||||
radeon_enc_output_one_byte(enc, output_byte);
|
||||
enc->bits_in_shifter -= 8;
|
||||
enc->bits_output += 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void radeon_enc_code_uvlc(struct radeon_encoder *enc, unsigned int value)
|
||||
{
|
||||
uint32_t num_bits = 0;
|
||||
uint64_t value_plus1 = (uint64_t)value + 1;
|
||||
uint32_t num_leading_zeros = 0;
|
||||
|
||||
while ((uint64_t)1 << num_bits <= value_plus1)
|
||||
num_bits++;
|
||||
|
||||
num_leading_zeros = num_bits - 1;
|
||||
radeon_enc_code_fixed_bits(enc, 0, num_leading_zeros);
|
||||
radeon_enc_code_fixed_bits(enc, 1, 1);
|
||||
radeon_enc_code_fixed_bits(enc, (uint32_t)value_plus1, num_leading_zeros);
|
||||
}
|
||||
|
||||
void radeon_enc_code_leb128(uint8_t *buf, uint32_t value,
|
||||
uint32_t num_bytes)
|
||||
{
|
||||
@@ -2156,71 +2063,6 @@ void radeon_enc_code_leb128(uint8_t *buf, uint32_t value,
|
||||
} while((leb128_byte & 0x80));
|
||||
}
|
||||
|
||||
void radeon_enc_reset(struct radeon_encoder *enc)
|
||||
{
|
||||
enc->emulation_prevention = false;
|
||||
enc->shifter = 0;
|
||||
enc->bits_in_shifter = 0;
|
||||
enc->bits_output = 0;
|
||||
enc->num_zeros = 0;
|
||||
enc->byte_index = 0;
|
||||
enc->bits_size = 0;
|
||||
enc->bits_buf = NULL;
|
||||
enc->bits_buf_pos = 0;
|
||||
}
|
||||
|
||||
void radeon_enc_byte_align(struct radeon_encoder *enc)
|
||||
{
|
||||
unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
|
||||
|
||||
if (num_padding_zeros > 0)
|
||||
radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros);
|
||||
}
|
||||
|
||||
void radeon_enc_flush_headers(struct radeon_encoder *enc)
|
||||
{
|
||||
if (enc->bits_in_shifter != 0) {
|
||||
unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
|
||||
radeon_enc_emulation_prevention(enc, output_byte);
|
||||
radeon_enc_output_one_byte(enc, output_byte);
|
||||
enc->bits_output += enc->bits_in_shifter;
|
||||
enc->shifter = 0;
|
||||
enc->bits_in_shifter = 0;
|
||||
enc->num_zeros = 0;
|
||||
}
|
||||
|
||||
if (enc->byte_index > 0) {
|
||||
enc->cs.current.cdw++;
|
||||
enc->byte_index = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value)
|
||||
{
|
||||
unsigned int x = 0;
|
||||
unsigned int ue_code = value + 1;
|
||||
value += 1;
|
||||
|
||||
while (value) {
|
||||
value = (value >> 1);
|
||||
x += 1;
|
||||
}
|
||||
|
||||
if (x > 1)
|
||||
radeon_enc_code_fixed_bits(enc, 0, x - 1);
|
||||
radeon_enc_code_fixed_bits(enc, ue_code, x);
|
||||
}
|
||||
|
||||
void radeon_enc_code_se(struct radeon_encoder *enc, int value)
|
||||
{
|
||||
unsigned int v = 0;
|
||||
|
||||
if (value != 0)
|
||||
v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
|
||||
|
||||
radeon_enc_code_ue(enc, v);
|
||||
}
|
||||
|
||||
unsigned int radeon_enc_av1_tile_log2(unsigned int blk_size, unsigned int max)
|
||||
{
|
||||
unsigned int k;
|
||||
@@ -2231,30 +2073,6 @@ unsigned int radeon_enc_av1_tile_log2(unsigned int blk_size, unsigned int max)
|
||||
return k;
|
||||
}
|
||||
|
||||
void radeon_enc_code_ns(struct radeon_encoder *enc, unsigned int value, unsigned int max)
|
||||
{
|
||||
unsigned w = 0;
|
||||
unsigned m;
|
||||
unsigned max_num = max;
|
||||
|
||||
while ( max_num ) {
|
||||
max_num >>= 1;
|
||||
w++;
|
||||
}
|
||||
|
||||
m = ( 1 << w ) - max;
|
||||
|
||||
assert(w > 1);
|
||||
|
||||
if ( value < m )
|
||||
radeon_enc_code_fixed_bits(enc, value, (w - 1));
|
||||
else {
|
||||
unsigned diff = value - m;
|
||||
unsigned out = (((diff >> 1) + m) << 1) | (diff & 0x1);
|
||||
radeon_enc_code_fixed_bits(enc, out, w);
|
||||
}
|
||||
}
|
||||
|
||||
/* dummy function for re-using the same pipeline */
|
||||
void radeon_enc_dummy(struct radeon_encoder *enc) {}
|
||||
|
||||
@@ -2269,13 +2087,14 @@ static void radeon_enc_av1_bs_copy_end(struct radeon_encoder *enc, uint32_t bits
|
||||
|
||||
/* av1 bitstream instruction type */
|
||||
void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc,
|
||||
struct radeon_bitstream *bs,
|
||||
uint32_t inst,
|
||||
uint32_t obu_type)
|
||||
{
|
||||
radeon_enc_flush_headers(enc);
|
||||
radeon_bs_flush_headers(bs);
|
||||
|
||||
if (enc->bits_output)
|
||||
radeon_enc_av1_bs_copy_end(enc, enc->bits_output);
|
||||
if (bs->bits_output)
|
||||
radeon_enc_av1_bs_copy_end(enc, bs->bits_output);
|
||||
|
||||
enc->enc_pic.copy_start = &enc->cs.current.buf[enc->cs.current.cdw++];
|
||||
RADEON_ENC_CS(inst);
|
||||
@@ -2289,7 +2108,7 @@ void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc,
|
||||
} else
|
||||
RADEON_ENC_CS(0); /* allocate a dword for number of bits */
|
||||
|
||||
radeon_enc_reset(enc);
|
||||
radeon_bs_reset(bs, NULL, &enc->cs);
|
||||
}
|
||||
|
||||
uint32_t radeon_enc_value_bits(uint32_t value)
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
|
||||
#include "radeon_vcn.h"
|
||||
#include "util/macros.h"
|
||||
#include "radeon_bitstream.h"
|
||||
|
||||
#include "ac_vcn_enc.h"
|
||||
|
||||
@@ -248,19 +249,10 @@ struct radeon_encoder {
|
||||
rvcn_enc_cmd_t cmd;
|
||||
|
||||
unsigned alignment;
|
||||
unsigned shifter;
|
||||
unsigned bits_in_shifter;
|
||||
unsigned num_zeros;
|
||||
unsigned byte_index;
|
||||
unsigned bits_output;
|
||||
unsigned bits_size;
|
||||
uint8_t *bits_buf;
|
||||
uint32_t bits_buf_pos;
|
||||
uint32_t total_task_size;
|
||||
uint32_t *p_task_size;
|
||||
struct rvcn_sq_var sq;
|
||||
|
||||
bool emulation_prevention;
|
||||
bool need_feedback;
|
||||
bool need_rate_control;
|
||||
bool need_rc_per_pic;
|
||||
@@ -312,35 +304,9 @@ void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *bu
|
||||
|
||||
void radeon_enc_dummy(struct radeon_encoder *enc);
|
||||
|
||||
void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set);
|
||||
|
||||
void radeon_enc_set_output_buffer(struct radeon_encoder *enc, uint8_t *buffer);
|
||||
|
||||
void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte);
|
||||
|
||||
void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte);
|
||||
|
||||
void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
|
||||
unsigned int num_bits);
|
||||
|
||||
void radeon_enc_reset(struct radeon_encoder *enc);
|
||||
|
||||
void radeon_enc_byte_align(struct radeon_encoder *enc);
|
||||
|
||||
void radeon_enc_flush_headers(struct radeon_encoder *enc);
|
||||
|
||||
void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value);
|
||||
|
||||
void radeon_enc_code_se(struct radeon_encoder *enc, int value);
|
||||
|
||||
void radeon_enc_code_uvlc(struct radeon_encoder *enc, unsigned int value);
|
||||
|
||||
void radeon_enc_code_leb128(unsigned char *buf, unsigned int value,
|
||||
unsigned int num_bytes);
|
||||
|
||||
void radeon_enc_code_ns(struct radeon_encoder *enc, unsigned int value,
|
||||
unsigned int max);
|
||||
|
||||
void radeon_enc_1_2_init(struct radeon_encoder *enc);
|
||||
|
||||
void radeon_enc_2_0_init(struct radeon_encoder *enc);
|
||||
@@ -363,33 +329,15 @@ unsigned int radeon_enc_write_pps_hevc(struct radeon_encoder *enc, uint8_t *out)
|
||||
|
||||
unsigned int radeon_enc_write_sequence_header(struct radeon_encoder *enc, uint8_t *obu_bytes, uint8_t *out);
|
||||
|
||||
void radeon_enc_hrd_parameters(struct radeon_encoder *enc,
|
||||
struct pipe_h264_enc_hrd_params *hrd);
|
||||
|
||||
void radeon_enc_hevc_profile_tier_level(struct radeon_encoder *enc,
|
||||
unsigned int max_num_sub_layers_minus1,
|
||||
struct pipe_h265_profile_tier_level *ptl);
|
||||
|
||||
void radeon_enc_hevc_hrd_parameters(struct radeon_encoder *enc,
|
||||
unsigned int common_inf_present_flag,
|
||||
unsigned int max_sub_layers_minus1,
|
||||
struct pipe_h265_enc_hrd_params *hrd);
|
||||
|
||||
unsigned int radeon_enc_hevc_st_ref_pic_set(struct radeon_encoder *enc,
|
||||
unsigned int index,
|
||||
unsigned int num_short_term_ref_pic_sets,
|
||||
struct pipe_h265_st_ref_pic_set *st_rps);
|
||||
|
||||
void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc,
|
||||
struct radeon_bitstream *bs,
|
||||
unsigned int inst, unsigned int obu_type);
|
||||
|
||||
void radeon_enc_av1_obu_header(struct radeon_encoder *enc, uint32_t obu_type);
|
||||
void radeon_enc_av1_obu_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, uint32_t obu_type);
|
||||
|
||||
void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_header);
|
||||
void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header);
|
||||
|
||||
void radeon_enc_av1_tile_group(struct radeon_encoder *enc);
|
||||
|
||||
unsigned char *radeon_enc_av1_header_size_offset(struct radeon_encoder *enc);
|
||||
void radeon_enc_av1_tile_group(struct radeon_encoder *enc, struct radeon_bitstream *bs);
|
||||
|
||||
unsigned int radeon_enc_value_bits(unsigned int value);
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -157,226 +157,226 @@ static void radeon_enc_cdf_default_table(struct radeon_encoder *enc)
|
||||
RADEON_ENC_END();
|
||||
}
|
||||
|
||||
void radeon_enc_av1_obu_header(struct radeon_encoder *enc, uint32_t obu_type)
|
||||
void radeon_enc_av1_obu_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, uint32_t obu_type)
|
||||
{
|
||||
/* obu header () */
|
||||
/* obu_forbidden_bit */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
/* obu_type */
|
||||
radeon_enc_code_fixed_bits(enc, obu_type, 4);
|
||||
radeon_bs_code_fixed_bits(bs, obu_type, 4);
|
||||
/* obu_extension_flag */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.desc->obu_extension_flag ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.desc->obu_extension_flag ? 1 : 0, 1);
|
||||
/* obu_has_size_field */
|
||||
radeon_enc_code_fixed_bits(enc, 1, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 1, 1);
|
||||
/* obu_reserved_1bit */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
|
||||
if (enc->enc_pic.av1.desc->obu_extension_flag) {
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.temporal_id, 3);
|
||||
radeon_enc_code_fixed_bits(enc, 0, 2); /* spatial_id should always be zero */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 3); /* reserved 3 bits */
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.temporal_id, 3);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 2); /* spatial_id should always be zero */
|
||||
radeon_bs_code_fixed_bits(bs, 0, 3); /* reserved 3 bits */
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int radeon_enc_write_sequence_header(struct radeon_encoder *enc, uint8_t *obu_bytes, uint8_t *out)
|
||||
{
|
||||
struct radeon_bitstream bs;
|
||||
uint8_t *size_offset;
|
||||
uint32_t obu_size;
|
||||
uint32_t width_bits;
|
||||
uint32_t height_bits;
|
||||
struct pipe_av1_enc_seq_param *seq = &enc->enc_pic.av1.desc->seq;
|
||||
|
||||
radeon_enc_reset(enc);
|
||||
radeon_enc_set_output_buffer(enc, out);
|
||||
radeon_enc_code_fixed_bits(enc, obu_bytes[0], 8);
|
||||
radeon_bs_reset(&bs, out, NULL);
|
||||
radeon_bs_code_fixed_bits(&bs, obu_bytes[0], 8);
|
||||
if (obu_bytes[0] & 0x4) /* obu_extension_flag */
|
||||
radeon_enc_code_fixed_bits(enc, obu_bytes[1], 8);
|
||||
radeon_bs_code_fixed_bits(&bs, obu_bytes[1], 8);
|
||||
|
||||
/* obu_size, use one byte for header, the size will be written in afterwards */
|
||||
size_offset = &enc->bits_buf[enc->bits_buf_pos];
|
||||
radeon_enc_code_fixed_bits(enc, 0, 8);
|
||||
size_offset = &out[bs.bits_output / 8];
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 8);
|
||||
|
||||
/* sequence_header_obu() */
|
||||
/* seq_profile */
|
||||
radeon_enc_code_fixed_bits(enc, seq->profile, 3);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->profile, 3);
|
||||
/* still_picture */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.still_picture, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.still_picture, 1);
|
||||
/* reduced_still_picture_header */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.reduced_still_picture_header, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.reduced_still_picture_header, 1);
|
||||
|
||||
if (seq->seq_bits.reduced_still_picture_header) {
|
||||
/* seq_level_idx[0] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_level_idx[0], 5);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_level_idx[0], 5);
|
||||
} else {
|
||||
/* timing_info_present_flag */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.timing_info_present_flag, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.timing_info_present_flag, 1);
|
||||
|
||||
if (seq->seq_bits.timing_info_present_flag) {
|
||||
/* num_units_in_display_tick */
|
||||
radeon_enc_code_fixed_bits(enc, seq->num_units_in_display_tick, 32);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->num_units_in_display_tick, 32);
|
||||
/* time_scale */
|
||||
radeon_enc_code_fixed_bits(enc, seq->time_scale, 32);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->time_scale, 32);
|
||||
/* equal_picture_interval */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.equal_picture_interval, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.equal_picture_interval, 1);
|
||||
/* num_ticks_per_picture_minus_1 */
|
||||
if (seq->seq_bits.equal_picture_interval)
|
||||
radeon_enc_code_uvlc(enc, seq->num_tick_per_picture_minus1);
|
||||
radeon_bs_code_uvlc(&bs, seq->num_tick_per_picture_minus1);
|
||||
/* decoder_model_info_present_flag */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.decoder_model_info_present_flag, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.decoder_model_info_present_flag, 1);
|
||||
if (seq->seq_bits.decoder_model_info_present_flag) {
|
||||
/* buffer_delay_length_minus1 */
|
||||
radeon_enc_code_fixed_bits(enc, seq->decoder_model_info.buffer_delay_length_minus1, 5);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.buffer_delay_length_minus1, 5);
|
||||
/* num_units_in_decoding_tick */
|
||||
radeon_enc_code_fixed_bits(enc, seq->decoder_model_info.num_units_in_decoding_tick, 32);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.num_units_in_decoding_tick, 32);
|
||||
/* buffer_removal_time_length_minus1 */
|
||||
radeon_enc_code_fixed_bits(enc, seq->decoder_model_info.buffer_removal_time_length_minus1, 5);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.buffer_removal_time_length_minus1, 5);
|
||||
/* frame_presentation_time_length_minus1 */
|
||||
radeon_enc_code_fixed_bits(enc, seq->decoder_model_info.frame_presentation_time_length_minus1, 5);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.frame_presentation_time_length_minus1, 5);
|
||||
}
|
||||
}
|
||||
|
||||
/* initial_display_delay_present_flag */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.initial_display_delay_present_flag, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.initial_display_delay_present_flag, 1);
|
||||
/* operating_points_cnt_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, seq->num_temporal_layers - 1, 5);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->num_temporal_layers - 1, 5);
|
||||
|
||||
for (uint32_t i = 0; i < seq->num_temporal_layers; i++) {
|
||||
/* operating_point_idc[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->operating_point_idc[i], 12);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->operating_point_idc[i], 12);
|
||||
/* seq_level_idx[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_level_idx[i], 5);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_level_idx[i], 5);
|
||||
if (seq->seq_level_idx[i] > 7)
|
||||
/* seq_tier[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_tier[i], 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_tier[i], 1);
|
||||
if (seq->seq_bits.decoder_model_info_present_flag) {
|
||||
/* decoder_model_present_for_this_op[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->decoder_model_present_for_this_op[i], 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->decoder_model_present_for_this_op[i], 1);
|
||||
if (seq->decoder_model_present_for_this_op[i]) {
|
||||
uint32_t length = seq->decoder_model_info.buffer_delay_length_minus1 + 1;
|
||||
/* decoder_buffer_delay[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->decoder_buffer_delay[i], length);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->decoder_buffer_delay[i], length);
|
||||
/* encoder_buffer_delay[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->encoder_buffer_delay[i], length);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->encoder_buffer_delay[i], length);
|
||||
/* low_delay_mode_flag[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->low_delay_mode_flag[i], 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->low_delay_mode_flag[i], 1);
|
||||
}
|
||||
}
|
||||
if (seq->seq_bits.initial_display_delay_present_flag) {
|
||||
/* initial_display_delay_present_for_this_op[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->initial_display_delay_present_for_this_op[i], 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->initial_display_delay_present_for_this_op[i], 1);
|
||||
if (seq->initial_display_delay_present_for_this_op[i])
|
||||
/* initial_display_delay_minus_1[i] */
|
||||
radeon_enc_code_fixed_bits(enc, seq->initial_display_delay_minus_1[i], 4);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->initial_display_delay_minus_1[i], 4);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* frame_width_bits_minus_1 */
|
||||
width_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_width);
|
||||
radeon_enc_code_fixed_bits(enc, width_bits - 1, 4);
|
||||
radeon_bs_code_fixed_bits(&bs, width_bits - 1, 4);
|
||||
/* frame_height_bits_minus_1 */
|
||||
height_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height);
|
||||
radeon_enc_code_fixed_bits(enc, height_bits - 1, 4);
|
||||
radeon_bs_code_fixed_bits(&bs, height_bits - 1, 4);
|
||||
/* max_frame_width_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_width - 1,
|
||||
radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1.coded_width - 1,
|
||||
width_bits);
|
||||
/* max_frame_height_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_height - 1,
|
||||
radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1.coded_height - 1,
|
||||
height_bits);
|
||||
|
||||
if (!seq->seq_bits.reduced_still_picture_header)
|
||||
/* frame_id_numbers_present_flag */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.frame_id_number_present_flag, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.frame_id_number_present_flag, 1);
|
||||
|
||||
if (seq->seq_bits.frame_id_number_present_flag) {
|
||||
/* delta_frame_id_length_minus_2 */
|
||||
radeon_enc_code_fixed_bits(enc, seq->delta_frame_id_length - 2, 4);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->delta_frame_id_length - 2, 4);
|
||||
/* additional_frame_id_length_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, seq->additional_frame_id_length - 1, 3);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->additional_frame_id_length - 1, 3);
|
||||
}
|
||||
|
||||
/* use_128x128_superblock */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* enable_filter_intra */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* enable_intra_edge_filter */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
|
||||
if (!seq->seq_bits.reduced_still_picture_header) {
|
||||
/* enable_interintra_compound */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* enable_masked_compound */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* enable_warped_motion */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* enable_dual_filter */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* enable_order_hint */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.enable_order_hint, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.enable_order_hint, 1);
|
||||
|
||||
if (seq->seq_bits.enable_order_hint) {
|
||||
/* enable_jnt_comp */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* enable_ref_frame_mvs */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
}
|
||||
|
||||
/* seq_choose_screen_content_tools */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.disable_screen_content_tools ? 0 : 1, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, enc->enc_pic.disable_screen_content_tools ? 0 : 1, 1);
|
||||
if (enc->enc_pic.disable_screen_content_tools)
|
||||
/* seq_force_screen_content_tools */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
else
|
||||
/* seq_choose_integer_mv */
|
||||
radeon_enc_code_fixed_bits(enc, 1, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 1, 1);
|
||||
|
||||
if (seq->seq_bits.enable_order_hint)
|
||||
/* order_hint_bits_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, seq->order_hint_bits - 1, 3);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->order_hint_bits - 1, 3);
|
||||
}
|
||||
|
||||
/* enable_superres */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* enable_cdef */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.cdef_mode ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1_spec_misc.cdef_mode ? 1 : 0, 1);
|
||||
/* enable_restoration */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* high_bitdepth */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.enc_output_format.output_color_bit_depth, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, enc->enc_pic.enc_output_format.output_color_bit_depth, 1);
|
||||
/* mono_chrome */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
/* color_description_present_flag */
|
||||
radeon_enc_code_fixed_bits(enc, seq->seq_bits.color_description_present_flag, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->seq_bits.color_description_present_flag, 1);
|
||||
|
||||
if (seq->seq_bits.color_description_present_flag) {
|
||||
/* color_primaries */
|
||||
radeon_enc_code_fixed_bits(enc, seq->color_config.color_primaries, 8);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->color_config.color_primaries, 8);
|
||||
/* transfer_characteristics */
|
||||
radeon_enc_code_fixed_bits(enc, seq->color_config.transfer_characteristics, 8);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->color_config.transfer_characteristics, 8);
|
||||
/* matrix_coefficients */
|
||||
radeon_enc_code_fixed_bits(enc, seq->color_config.matrix_coefficients, 8);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->color_config.matrix_coefficients, 8);
|
||||
}
|
||||
/* color_range */
|
||||
radeon_enc_code_fixed_bits(enc, seq->color_config.color_range, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->color_config.color_range, 1);
|
||||
/* chroma_sample_position */
|
||||
radeon_enc_code_fixed_bits(enc, seq->color_config.chroma_sample_position, 2);
|
||||
radeon_bs_code_fixed_bits(&bs, seq->color_config.chroma_sample_position, 2);
|
||||
/* separate_uv_delta_q */
|
||||
bool separate_delta_q = false;
|
||||
radeon_enc_code_fixed_bits(enc, !!(separate_delta_q), 1);
|
||||
radeon_bs_code_fixed_bits(&bs, !!(separate_delta_q), 1);
|
||||
/* film_grain_params_present */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(&bs, 0, 1);
|
||||
|
||||
/* trailing_one_bit */
|
||||
radeon_enc_code_fixed_bits(enc, 1, 1);
|
||||
radeon_enc_byte_align(enc);
|
||||
radeon_bs_code_fixed_bits(&bs, 1, 1);
|
||||
radeon_bs_byte_align(&bs);
|
||||
|
||||
obu_size = (uint32_t)(&enc->bits_buf[enc->bits_buf_pos] - size_offset - 1);
|
||||
obu_size = (uint32_t)(&out[bs.bits_output / 8] - size_offset - 1);
|
||||
radeon_enc_code_leb128(size_offset, obu_size, 1);
|
||||
|
||||
return enc->bits_buf_pos;
|
||||
return bs.bits_output / 8;
|
||||
}
|
||||
|
||||
void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_header)
|
||||
void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header)
|
||||
{
|
||||
uint32_t i;
|
||||
bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
|
||||
@@ -386,53 +386,53 @@ void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_h
|
||||
bool error_resilient_mode = false;
|
||||
struct pipe_av1_enc_picture_desc *av1 = enc->enc_pic.av1.desc;
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
|
||||
radeon_enc_av1_obu_header(enc, obu_type);
|
||||
radeon_enc_av1_obu_header(enc, bs, obu_type);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
|
||||
|
||||
/* uncompressed_header() */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
|
||||
if (!av1->seq.seq_bits.reduced_still_picture_header) {
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1); /* show_existing_frame */
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1); /* show_existing_frame */
|
||||
/* frame_type */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_type, 2);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.frame_type, 2);
|
||||
/* show_frame */
|
||||
radeon_enc_code_fixed_bits(enc, av1->show_frame, 1);
|
||||
radeon_bs_code_fixed_bits(bs, av1->show_frame, 1);
|
||||
if (!av1->show_frame)
|
||||
/* showable_frame */
|
||||
radeon_enc_code_fixed_bits(enc, av1->showable_frame, 1);
|
||||
radeon_bs_code_fixed_bits(bs, av1->showable_frame, 1);
|
||||
|
||||
if ((enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH) ||
|
||||
(enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY && av1->show_frame))
|
||||
error_resilient_mode = true;
|
||||
else {
|
||||
/* error_resilient_mode */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_error_resilient_mode ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.enable_error_resilient_mode ? 1 : 0, 1);
|
||||
error_resilient_mode = enc->enc_pic.enable_error_resilient_mode;
|
||||
}
|
||||
}
|
||||
|
||||
/* disable_cdf_update */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_cdf_update ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1_spec_misc.disable_cdf_update ? 1 : 0, 1);
|
||||
|
||||
bool allow_screen_content_tools = false;
|
||||
if (av1->seq.seq_bits.reduced_still_picture_header || !enc->enc_pic.disable_screen_content_tools) {
|
||||
/* allow_screen_content_tools */
|
||||
allow_screen_content_tools = enc->enc_pic.av1_spec_misc.palette_mode_enable ||
|
||||
enc->enc_pic.force_integer_mv;
|
||||
radeon_enc_code_fixed_bits(enc, allow_screen_content_tools ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, allow_screen_content_tools ? 1 : 0, 1);
|
||||
}
|
||||
|
||||
if (allow_screen_content_tools)
|
||||
/* force_integer_mv */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.force_integer_mv ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.force_integer_mv ? 1 : 0, 1);
|
||||
|
||||
if (av1->seq.seq_bits.frame_id_number_present_flag)
|
||||
/* current_frame_id */
|
||||
radeon_enc_code_fixed_bits(enc, av1->current_frame_id,
|
||||
radeon_bs_code_fixed_bits(bs, av1->current_frame_id,
|
||||
av1->seq.delta_frame_id_length + av1->seq.additional_frame_id_length);
|
||||
|
||||
bool frame_size_override = false;
|
||||
@@ -441,176 +441,179 @@ void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_h
|
||||
else if (!av1->seq.seq_bits.reduced_still_picture_header) {
|
||||
/* frame_size_override_flag */
|
||||
frame_size_override = false;
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
}
|
||||
|
||||
if (av1->seq.seq_bits.enable_order_hint)
|
||||
/* order_hint */
|
||||
radeon_enc_code_fixed_bits(enc, av1->order_hint, av1->seq.order_hint_bits);
|
||||
radeon_bs_code_fixed_bits(bs, av1->order_hint, av1->seq.order_hint_bits);
|
||||
|
||||
if (!frame_is_intra && !error_resilient_mode)
|
||||
/* primary_ref_frame */
|
||||
radeon_enc_code_fixed_bits(enc, av1->primary_ref_frame, 3);
|
||||
radeon_bs_code_fixed_bits(bs, av1->primary_ref_frame, 3);
|
||||
|
||||
if ((enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SWITCH) &&
|
||||
(enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_KEY || !av1->show_frame))
|
||||
/* refresh_frame_flags */
|
||||
radeon_enc_code_fixed_bits(enc, av1->refresh_frame_flags, 8);
|
||||
radeon_bs_code_fixed_bits(bs, av1->refresh_frame_flags, 8);
|
||||
|
||||
if ((!frame_is_intra || av1->refresh_frame_flags != 0xff) &&
|
||||
error_resilient_mode && av1->seq.seq_bits.enable_order_hint)
|
||||
for (i = 0; i < RENCODE_AV1_NUM_REF_FRAMES; i++)
|
||||
/* ref_order_hint */
|
||||
radeon_enc_code_fixed_bits(enc, av1->ref_order_hint[i], av1->seq.order_hint_bits);
|
||||
radeon_bs_code_fixed_bits(bs, av1->ref_order_hint[i], av1->seq.order_hint_bits);
|
||||
|
||||
if (frame_is_intra) {
|
||||
/* render_and_frame_size_different */
|
||||
radeon_enc_code_fixed_bits(enc, av1->enable_render_size ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, av1->enable_render_size ? 1 : 0, 1);
|
||||
if (av1->enable_render_size) {
|
||||
/* render_width_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, av1->render_width_minus_1, 16);
|
||||
radeon_bs_code_fixed_bits(bs, av1->render_width_minus_1, 16);
|
||||
/* render_height_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, av1->render_height_minus_1, 16);
|
||||
radeon_bs_code_fixed_bits(bs, av1->render_height_minus_1, 16);
|
||||
}
|
||||
if (!enc->enc_pic.disable_screen_content_tools &&
|
||||
(enc->enc_pic.av1_spec_misc.palette_mode_enable || enc->enc_pic.force_integer_mv))
|
||||
/* allow_intrabc */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
} else {
|
||||
if (av1->seq.seq_bits.enable_order_hint)
|
||||
/* frame_refs_short_signaling */
|
||||
radeon_enc_code_fixed_bits(enc, av1->frame_refs_short_signaling, 1);
|
||||
radeon_bs_code_fixed_bits(bs, av1->frame_refs_short_signaling, 1);
|
||||
if (av1->frame_refs_short_signaling) {
|
||||
radeon_enc_code_fixed_bits(enc, av1->last_frame_idx, 3);
|
||||
radeon_enc_code_fixed_bits(enc, av1->gold_frame_idx, 3);
|
||||
radeon_bs_code_fixed_bits(bs, av1->last_frame_idx, 3);
|
||||
radeon_bs_code_fixed_bits(bs, av1->gold_frame_idx, 3);
|
||||
}
|
||||
for (i = 0; i < RENCODE_AV1_REFS_PER_FRAME; i++) {
|
||||
/* ref_frame_idx[i] */
|
||||
radeon_enc_code_fixed_bits(enc, av1->ref_frame_idx[i], 3);
|
||||
radeon_bs_code_fixed_bits(bs, av1->ref_frame_idx[i], 3);
|
||||
if (av1->seq.seq_bits.frame_id_number_present_flag)
|
||||
/* delta_frame_id_minus_1[i] */
|
||||
radeon_enc_code_fixed_bits(enc, av1->delta_frame_id_minus_1[i], av1->seq.delta_frame_id_length);
|
||||
radeon_bs_code_fixed_bits(bs, av1->delta_frame_id_minus_1[i], av1->seq.delta_frame_id_length);
|
||||
}
|
||||
|
||||
if (frame_size_override && !error_resilient_mode)
|
||||
/* found_ref */
|
||||
radeon_enc_code_fixed_bits(enc, 1, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 1, 1);
|
||||
else {
|
||||
if(frame_size_override) {
|
||||
/* frame_width_minus_1 */
|
||||
uint32_t used_bits =
|
||||
radeon_enc_value_bits(enc->enc_pic.av1.coded_width - 1);
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_width - 1,
|
||||
used_bits);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.coded_width - 1,
|
||||
used_bits);
|
||||
/* frame_height_minus_1 */
|
||||
used_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height - 1);
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_height - 1,
|
||||
used_bits);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.coded_height - 1,
|
||||
used_bits);
|
||||
}
|
||||
/* render_and_frame_size_different */
|
||||
radeon_enc_code_fixed_bits(enc, av1->enable_render_size ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, av1->enable_render_size ? 1 : 0, 1);
|
||||
if (av1->enable_render_size) {
|
||||
/* render_width_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, av1->render_width_minus_1, 16);
|
||||
radeon_bs_code_fixed_bits(bs, av1->render_width_minus_1, 16);
|
||||
/* render_height_minus_1 */
|
||||
radeon_enc_code_fixed_bits(enc, av1->render_height_minus_1, 16);
|
||||
radeon_bs_code_fixed_bits(bs, av1->render_height_minus_1, 16);
|
||||
}
|
||||
}
|
||||
|
||||
if (enc->enc_pic.disable_screen_content_tools || !enc->enc_pic.force_integer_mv)
|
||||
/* allow_high_precision_mv */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV, 0);
|
||||
|
||||
/* read_interpolation_filter */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER, 0);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
/* is_motion_mode_switchable */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
}
|
||||
|
||||
if (!av1->seq.seq_bits.reduced_still_picture_header && !enc->enc_pic.av1_spec_misc.disable_cdf_update)
|
||||
/* disable_frame_end_update_cdf */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
|
||||
}
|
||||
|
||||
static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_header)
|
||||
static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header)
|
||||
{
|
||||
bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
|
||||
enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
|
||||
|
||||
radeon_enc_av1_frame_header_common(enc, frame_header);
|
||||
radeon_enc_av1_frame_header_common(enc, bs, frame_header);
|
||||
|
||||
/* tile_info */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
|
||||
/* quantization_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
|
||||
/* segmentation_enable */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
/* delta_q_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
|
||||
/* delta_lf_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
|
||||
/* loop_filter_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
|
||||
/* cdef_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
|
||||
/* lr_params */
|
||||
/* read_tx_mode */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
|
||||
if (!frame_is_intra)
|
||||
/* reference_select */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
|
||||
/* reduced_tx_set */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
|
||||
if (!frame_is_intra)
|
||||
for (uint32_t ref = 1 /*LAST_FRAME*/; ref <= 7 /*ALTREF_FRAME*/; ref++)
|
||||
/* is_global */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
/* film_grain_params() */
|
||||
}
|
||||
|
||||
void radeon_enc_av1_tile_group(struct radeon_encoder *enc)
|
||||
void radeon_enc_av1_tile_group(struct radeon_encoder *enc, struct radeon_bitstream *bs)
|
||||
{
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
|
||||
RENCODE_OBU_START_TYPE_TILE_GROUP);
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
|
||||
RENCODE_OBU_START_TYPE_TILE_GROUP);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
|
||||
radeon_enc_av1_obu_header(enc, RENCODE_OBU_TYPE_TILE_GROUP);
|
||||
radeon_enc_av1_obu_header(enc, bs, RENCODE_OBU_TYPE_TILE_GROUP);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
|
||||
}
|
||||
|
||||
static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
|
||||
{
|
||||
struct radeon_bitstream bs;
|
||||
bool frame_header = !enc->enc_pic.is_obu_frame;
|
||||
radeon_enc_reset(enc);
|
||||
|
||||
radeon_bs_reset(&bs, NULL, &enc->cs);
|
||||
|
||||
RADEON_ENC_BEGIN(enc->cmd.bitstream_instruction_av1);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc,
|
||||
radeon_enc_av1_bs_instruction_type(enc, &bs,
|
||||
RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
|
||||
frame_header ? RENCODE_OBU_START_TYPE_FRAME_HEADER
|
||||
: RENCODE_OBU_START_TYPE_FRAME);
|
||||
|
||||
radeon_enc_av1_frame_header(enc, frame_header);
|
||||
radeon_enc_av1_frame_header(enc, &bs, frame_header);
|
||||
|
||||
if (!frame_header)
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
|
||||
|
||||
if (frame_header)
|
||||
radeon_enc_av1_tile_group(enc);
|
||||
radeon_enc_av1_tile_group(enc, &bs);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
|
||||
RADEON_ENC_END();
|
||||
}
|
||||
|
||||
|
||||
@@ -722,7 +722,7 @@ static void radeon_enc_tile_config_av1(struct radeon_encoder *enc)
|
||||
RADEON_ENC_END();
|
||||
}
|
||||
|
||||
static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
|
||||
static void radeon_enc_av1_tile_info(struct radeon_encoder *enc, struct radeon_bitstream *bs)
|
||||
{
|
||||
rvcn_enc_av1_tile_config_t *p_config = &enc->enc_pic.av1_tile_config;
|
||||
uint32_t i = 0;
|
||||
@@ -738,17 +738,17 @@ static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
|
||||
TileColsLog2 = util_logbase2_ceil(p_config->num_tile_cols);
|
||||
TileRowsLog2 = util_logbase2_ceil(p_config->num_tile_rows);
|
||||
|
||||
radeon_enc_code_fixed_bits(enc, p_config->uniform_tile_spacing, 1);
|
||||
radeon_bs_code_fixed_bits(bs, p_config->uniform_tile_spacing, 1);
|
||||
if (p_config->uniform_tile_spacing) {
|
||||
for ( i = minLog2TileCols; i < TileColsLog2; i++)
|
||||
radeon_enc_code_fixed_bits(enc, 1, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 1, 1);
|
||||
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
|
||||
for ( i = minLog2Tiles - TileColsLog2; i < TileRowsLog2; i++)
|
||||
radeon_enc_code_fixed_bits(enc, 1, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 1, 1);
|
||||
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
} else {
|
||||
uint32_t widestTileSb = 0;
|
||||
uint32_t maxWidthInSb = 0;
|
||||
@@ -758,7 +758,7 @@ static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
|
||||
|
||||
for (i = 0; i < p_config->num_tile_cols; i++) {
|
||||
maxWidthInSb = MIN2(sbCols - startSb, maxTileWidthSb);
|
||||
radeon_enc_code_ns(enc, p_config->tile_widths[i] - 1, maxWidthInSb);
|
||||
radeon_bs_code_ns(bs, p_config->tile_widths[i] - 1, maxWidthInSb);
|
||||
startSb += p_config->tile_widths[i];
|
||||
widestTileSb = MAX2( p_config->tile_widths[i], widestTileSb);
|
||||
}
|
||||
@@ -773,52 +773,52 @@ static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
|
||||
|
||||
for (i = 0; i < p_config->num_tile_rows; i++) {
|
||||
maxHeightInSb = MIN2(sbRows - startSb, maxTileHeightSb);
|
||||
radeon_enc_code_ns(enc, p_config->tile_height[i] - 1, maxHeightInSb);
|
||||
radeon_bs_code_ns(bs, p_config->tile_height[i] - 1, maxHeightInSb);
|
||||
startSb += p_config->tile_height[i];
|
||||
}
|
||||
}
|
||||
|
||||
if (TileColsLog2 > 0 || TileRowsLog2 > 0) {
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID, 0);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
|
||||
radeon_enc_code_fixed_bits(enc, p_config->tile_size_bytes_minus_1, 2);
|
||||
radeon_bs_code_fixed_bits(bs, p_config->tile_size_bytes_minus_1, 2);
|
||||
}
|
||||
}
|
||||
|
||||
static void radeon_enc_av1_write_delta_q(struct radeon_encoder *enc, int32_t q)
|
||||
static void radeon_enc_av1_write_delta_q(struct radeon_bitstream *bs, int32_t q)
|
||||
{
|
||||
radeon_enc_code_fixed_bits(enc, !!(q), 1);
|
||||
radeon_bs_code_fixed_bits(bs, !!(q), 1);
|
||||
|
||||
if (q)
|
||||
radeon_enc_code_fixed_bits(enc, q, ( 1 + 6 ));
|
||||
radeon_bs_code_fixed_bits(bs, q, ( 1 + 6 ));
|
||||
}
|
||||
|
||||
static void radeon_enc_av1_quantization_params(struct radeon_encoder *enc)
|
||||
static void radeon_enc_av1_quantization_params(struct radeon_encoder *enc, struct radeon_bitstream *bs)
|
||||
{
|
||||
rvcn_enc_av1_spec_misc_t *p = &enc->enc_pic.av1_spec_misc;
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX, 0);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
|
||||
radeon_enc_av1_write_delta_q(enc, p->delta_q_y_dc);
|
||||
radeon_enc_av1_write_delta_q(bs, p->delta_q_y_dc);
|
||||
|
||||
/* only support multi-planes at the time */
|
||||
if (p->separate_delta_q)
|
||||
radeon_enc_code_fixed_bits(enc, 1, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 1, 1);
|
||||
|
||||
radeon_enc_av1_write_delta_q(enc, p->delta_q_u_dc);
|
||||
radeon_enc_av1_write_delta_q(enc, p->delta_q_u_ac);
|
||||
radeon_enc_av1_write_delta_q(bs, p->delta_q_u_dc);
|
||||
radeon_enc_av1_write_delta_q(bs, p->delta_q_u_ac);
|
||||
|
||||
if (p->separate_delta_q) {
|
||||
radeon_enc_av1_write_delta_q(enc, p->delta_q_v_dc);
|
||||
radeon_enc_av1_write_delta_q(enc, p->delta_q_v_ac);
|
||||
radeon_enc_av1_write_delta_q(bs, p->delta_q_v_dc);
|
||||
radeon_enc_av1_write_delta_q(bs, p->delta_q_v_ac);
|
||||
}
|
||||
|
||||
/* using qmatrix */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
}
|
||||
|
||||
static int32_t radeon_enc_av1_get_relative_dist(struct radeon_encoder *enc, uint32_t a, uint32_t b)
|
||||
@@ -886,74 +886,76 @@ bool radeon_enc_av1_skip_mode_allowed(struct radeon_encoder *enc, uint32_t frame
|
||||
return true;
|
||||
}
|
||||
|
||||
static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_header)
|
||||
static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header)
|
||||
{
|
||||
bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
|
||||
enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
|
||||
|
||||
radeon_enc_av1_frame_header_common(enc, frame_header);
|
||||
radeon_enc_av1_frame_header_common(enc, bs, frame_header);
|
||||
|
||||
/* tile_info */
|
||||
radeon_enc_av1_tile_info(enc);
|
||||
radeon_enc_av1_tile_info(enc, bs);
|
||||
/* quantization_params */
|
||||
radeon_enc_av1_quantization_params(enc);
|
||||
radeon_enc_av1_quantization_params(enc, bs);
|
||||
/* segmentation_enable */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
/* delta_q_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
|
||||
/* delta_lf_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
|
||||
/* loop_filter_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
|
||||
/* cdef_params */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
|
||||
/* lr_params */
|
||||
/* read_tx_mode */
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
|
||||
|
||||
if (!frame_is_intra)
|
||||
/* reference_select */
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.compound, 1);
|
||||
radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.compound, 1);
|
||||
|
||||
if (enc->enc_pic.av1.skip_mode_allowed)
|
||||
/* skip_mode_present */
|
||||
radeon_enc_code_fixed_bits(enc, !enc->enc_pic.av1_spec_misc.disallow_skip_mode, 1);
|
||||
radeon_bs_code_fixed_bits(bs, !enc->enc_pic.av1_spec_misc.disallow_skip_mode, 1);
|
||||
|
||||
/* reduced_tx_set */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
|
||||
if (!frame_is_intra)
|
||||
for (uint32_t ref = 1 /*LAST_FRAME*/; ref <= 7 /*ALTREF_FRAME*/; ref++)
|
||||
/* is_global */
|
||||
radeon_enc_code_fixed_bits(enc, 0, 1);
|
||||
radeon_bs_code_fixed_bits(bs, 0, 1);
|
||||
/* film_grain_params() */
|
||||
}
|
||||
|
||||
static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
|
||||
{
|
||||
bool frame_header = !enc->enc_pic.is_obu_frame;
|
||||
struct radeon_bitstream bs;
|
||||
|
||||
radeon_bs_reset(&bs, NULL, &enc->cs);
|
||||
|
||||
radeon_enc_reset(enc);
|
||||
RADEON_ENC_BEGIN(enc->cmd.bitstream_instruction_av1);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc,
|
||||
radeon_enc_av1_bs_instruction_type(enc, &bs,
|
||||
RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
|
||||
frame_header ? RENCODE_OBU_START_TYPE_FRAME_HEADER
|
||||
: RENCODE_OBU_START_TYPE_FRAME);
|
||||
|
||||
radeon_enc_av1_frame_header(enc, frame_header);
|
||||
radeon_enc_av1_frame_header(enc, &bs, frame_header);
|
||||
|
||||
if (!frame_header)
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
|
||||
|
||||
if (frame_header)
|
||||
radeon_enc_av1_tile_group(enc);
|
||||
radeon_enc_av1_tile_group(enc, &bs);
|
||||
|
||||
radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
|
||||
radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
|
||||
RADEON_ENC_END();
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user