diff --git a/src/gallium/drivers/radeonsi/meson.build b/src/gallium/drivers/radeonsi/meson.build
index 735c5d2ee07..7fad61992ed 100644
--- a/src/gallium/drivers/radeonsi/meson.build
+++ b/src/gallium/drivers/radeonsi/meson.build
@@ -101,6 +101,8 @@ files_libradeonsi = files(
   'radeon_vcn_enc_5_0.c',
   'radeon_video.c',
   'radeon_video.h',
+  'radeon_bitstream.h',
+  'radeon_bitstream.c',
 )
 
 radeonsi_include_dirs = [inc_src, inc_include, inc_gallium, inc_gallium_aux, inc_amd_common,
diff --git a/src/gallium/drivers/radeonsi/radeon_bitstream.c b/src/gallium/drivers/radeonsi/radeon_bitstream.c
new file mode 100644
index 00000000000..fbebe87ed97
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/radeon_bitstream.c
@@ -0,0 +1,349 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "radeon_bitstream.h"
+
+static const uint32_t index_to_shifts[4] = {24, 16, 8, 0};
+
+static void radeon_bs_output_one_byte(struct radeon_bitstream *bs, uint8_t byte)
+{
+   if (bs->buf) {
+      *(bs->buf++) = byte;
+      return;
+   }
+
+   if (bs->byte_index == 0)
+      bs->cs->current.buf[bs->cs->current.cdw] = 0;
+   bs->cs->current.buf[bs->cs->current.cdw] |=
+      ((uint32_t)(byte) << index_to_shifts[bs->byte_index]);
+   bs->byte_index++;
+
+   if (bs->byte_index >= 4) {
+      bs->byte_index = 0;
+      bs->cs->current.cdw++;
+   }
+}
+
+static void radeon_bs_emulation_prevention(struct radeon_bitstream *bs, uint8_t byte)
+{
+   if (bs->emulation_prevention) {
+      if ((bs->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) ||
+         (byte == 0x02) || (byte == 0x03))) {
+         radeon_bs_output_one_byte(bs, 0x03);
+         bs->bits_output += 8;
+         bs->num_zeros = 0;
+      }
+      bs->num_zeros = (byte == 0 ? (bs->num_zeros + 1) : 0);
+   }
+}
+
+void radeon_bs_reset(struct radeon_bitstream *bs, uint8_t *out, struct radeon_cmdbuf *cs)
+{
+   memset(bs, 0, sizeof(*bs));
+   bs->buf = out;
+   bs->cs = cs;
+}
+
+void radeon_bs_set_emulation_prevention(struct radeon_bitstream *bs, bool set)
+{
+   if (set != bs->emulation_prevention) {
+      bs->emulation_prevention = set;
+      bs->num_zeros = 0;
+   }
+}
+
+void radeon_bs_byte_align(struct radeon_bitstream *bs)
+{
+   uint32_t num_padding_zeros = (32 - bs->bits_in_shifter) % 8;
+
+   if (num_padding_zeros > 0)
+      radeon_bs_code_fixed_bits(bs, 0, num_padding_zeros);
+}
+
+void radeon_bs_flush_headers(struct radeon_bitstream *bs)
+{
+   if (bs->bits_in_shifter != 0) {
+      uint8_t output_byte = bs->shifter >> 24;
+      radeon_bs_emulation_prevention(bs, output_byte);
+      radeon_bs_output_one_byte(bs, output_byte);
+      bs->bits_output += bs->bits_in_shifter;
+      bs->shifter = 0;
+      bs->bits_in_shifter = 0;
+      bs->num_zeros = 0;
+   }
+
+   if (bs->byte_index > 0) {
+      bs->cs->current.cdw++;
+      bs->byte_index = 0;
+   }
+}
+
+void radeon_bs_code_fixed_bits(struct radeon_bitstream *bs, uint32_t value, uint32_t num_bits)
+{
+   uint32_t bits_to_pack = 0;
+   bs->bits_size += num_bits;
+
+   while (num_bits > 0) {
+      uint32_t value_to_pack = value & (0xffffffff >> (32 - num_bits));
+      bits_to_pack =
+         num_bits > (32 - bs->bits_in_shifter) ? (32 - bs->bits_in_shifter) : num_bits;
+
+      if (bits_to_pack < num_bits)
+         value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
+
+      bs->shifter |= value_to_pack << (32 - bs->bits_in_shifter - bits_to_pack);
+      num_bits -= bits_to_pack;
+      bs->bits_in_shifter += bits_to_pack;
+
+      while (bs->bits_in_shifter >= 8) {
+         uint8_t output_byte = bs->shifter >> 24;
+         bs->shifter <<= 8;
+         radeon_bs_emulation_prevention(bs, output_byte);
+         radeon_bs_output_one_byte(bs, output_byte);
+         bs->bits_in_shifter -= 8;
+         bs->bits_output += 8;
+      }
+   }
+}
+
+void radeon_bs_code_ue(struct radeon_bitstream *bs, uint32_t value)
+{
+   uint32_t x = 0;
+   uint32_t ue_code = value + 1;
+   value += 1;
+
+   while (value) {
+      value = value >> 1;
+      x += 1;
+   }
+
+   if (x > 1)
+     radeon_bs_code_fixed_bits(bs, 0, x - 1);
+   radeon_bs_code_fixed_bits(bs, ue_code, x);
+}
+
+void radeon_bs_code_se(struct radeon_bitstream *bs, int32_t value)
+{
+   uint32_t v = 0;
+
+   if (value != 0)
+      v = (value < 0 ? ((uint32_t)(0 - value) << 1) : (((uint32_t)(value) << 1) - 1));
+
+   radeon_bs_code_ue(bs, v);
+}
+
+void radeon_bs_code_uvlc(struct radeon_bitstream *bs, uint32_t value)
+{
+   uint32_t num_bits = 0;
+   uint64_t value_plus1 = (uint64_t)value + 1;
+   uint32_t num_leading_zeros = 0;
+
+   while ((uint64_t)1 << num_bits <= value_plus1)
+      num_bits++;
+
+   num_leading_zeros = num_bits - 1;
+   radeon_bs_code_fixed_bits(bs, 0, num_leading_zeros);
+   radeon_bs_code_fixed_bits(bs, 1, 1);
+   radeon_bs_code_fixed_bits(bs, (uint32_t)value_plus1, num_leading_zeros);
+}
+
+void radeon_bs_code_ns(struct radeon_bitstream *bs, uint32_t value, uint32_t max)
+{
+   uint32_t w = 0;
+   uint32_t m;
+   uint32_t max_num = max;
+
+   while ( max_num ) {
+      max_num >>= 1;
+      w++;
+   }
+
+   m = (1 << w) - max;
+
+   assert(w > 1);
+
+   if (value < m) {
+      radeon_bs_code_fixed_bits(bs, value, (w - 1));
+   } else {
+      uint32_t diff = value - m;
+      uint32_t out = (((diff >> 1) + m) << 1) | (diff & 0x1);
+      radeon_bs_code_fixed_bits(bs, out, w);
+   }
+}
+
+void radeon_bs_h264_hrd_parameters(struct radeon_bitstream *bs,
+                                   struct pipe_h264_enc_hrd_params *hrd)
+{
+   radeon_bs_code_ue(bs, hrd->cpb_cnt_minus1);
+   radeon_bs_code_fixed_bits(bs, hrd->bit_rate_scale, 4);
+   radeon_bs_code_fixed_bits(bs, hrd->cpb_size_scale, 4);
+   for (uint32_t i = 0; i <= hrd->cpb_cnt_minus1; i++) {
+      radeon_bs_code_ue(bs, hrd->bit_rate_value_minus1[i]);
+      radeon_bs_code_ue(bs, hrd->cpb_size_value_minus1[i]);
+      radeon_bs_code_fixed_bits(bs, hrd->cbr_flag[i], 1);
+   }
+   radeon_bs_code_fixed_bits(bs, hrd->initial_cpb_removal_delay_length_minus1, 5);
+   radeon_bs_code_fixed_bits(bs, hrd->cpb_removal_delay_length_minus1, 5);
+   radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_length_minus1, 5);
+   radeon_bs_code_fixed_bits(bs, hrd->time_offset_length, 5);
+}
+
+static void radeon_bs_hevc_profile_tier(struct radeon_bitstream *bs,
+                                        struct pipe_h265_profile_tier *pt)
+{
+   radeon_bs_code_fixed_bits(bs, pt->general_profile_space, 2);
+   radeon_bs_code_fixed_bits(bs, pt->general_tier_flag, 1);
+   radeon_bs_code_fixed_bits(bs, pt->general_profile_idc, 5);
+   radeon_bs_code_fixed_bits(bs, pt->general_profile_compatibility_flag, 32);
+   radeon_bs_code_fixed_bits(bs, pt->general_progressive_source_flag, 1);
+   radeon_bs_code_fixed_bits(bs, pt->general_interlaced_source_flag, 1);
+   radeon_bs_code_fixed_bits(bs, pt->general_non_packed_constraint_flag, 1);
+   radeon_bs_code_fixed_bits(bs, pt->general_frame_only_constraint_flag, 1);
+   /* general_reserved_zero_44bits */
+   radeon_bs_code_fixed_bits(bs, 0x0, 16);
+   radeon_bs_code_fixed_bits(bs, 0x0, 16);
+   radeon_bs_code_fixed_bits(bs, 0x0, 12);
+}
+
+void radeon_bs_hevc_profile_tier_level(struct radeon_bitstream *bs,
+                                       uint32_t max_num_sub_layers_minus1,
+                                       struct pipe_h265_profile_tier_level *ptl)
+{
+   uint32_t i;
+
+   radeon_bs_hevc_profile_tier(bs, &ptl->profile_tier);
+   radeon_bs_code_fixed_bits(bs, ptl->general_level_idc, 8);
+
+   for (i = 0; i < max_num_sub_layers_minus1; ++i) {
+      radeon_bs_code_fixed_bits(bs, ptl->sub_layer_profile_present_flag[i], 1);
+      radeon_bs_code_fixed_bits(bs, ptl->sub_layer_level_present_flag[i], 1);
+   }
+
+   if (max_num_sub_layers_minus1 > 0) {
+      for (i = max_num_sub_layers_minus1; i < 8; ++i)
+         radeon_bs_code_fixed_bits(bs, 0x0, 2); /* reserved_zero_2bits */
+   }
+
+   for (i = 0; i < max_num_sub_layers_minus1; ++i) {
+      if (ptl->sub_layer_profile_present_flag[i])
+         radeon_bs_hevc_profile_tier(bs, &ptl->sub_layer_profile_tier[i]);
+
+      if (ptl->sub_layer_level_present_flag[i])
+         radeon_bs_code_fixed_bits(bs, ptl->sub_layer_level_idc[i], 8);
+   }
+}
+
+static void radeon_bs_hevc_sub_layer_hrd_parameters(struct radeon_bitstream *bs,
+                                                    uint32_t cpb_cnt,
+                                                    uint32_t sub_pic_hrd_params_present_flag,
+                                                    struct pipe_h265_enc_sublayer_hrd_params *hrd)
+{
+   for (uint32_t i = 0; i < cpb_cnt; i++) {
+      radeon_bs_code_ue(bs, hrd->bit_rate_value_minus1[i]);
+      radeon_bs_code_ue(bs, hrd->cpb_size_value_minus1[i]);
+      if (sub_pic_hrd_params_present_flag) {
+         radeon_bs_code_ue(bs, hrd->cpb_size_du_value_minus1[i]);
+         radeon_bs_code_ue(bs, hrd->bit_rate_du_value_minus1[i]);
+      }
+      radeon_bs_code_fixed_bits(bs, hrd->cbr_flag[i], 1);
+   }
+}
+
+void radeon_bs_hevc_hrd_parameters(struct radeon_bitstream *bs,
+                                   uint32_t common_inf_present_flag,
+                                   uint32_t max_sub_layers_minus1,
+                                   struct pipe_h265_enc_hrd_params *hrd)
+{
+   if (common_inf_present_flag) {
+      radeon_bs_code_fixed_bits(bs, hrd->nal_hrd_parameters_present_flag, 1);
+      radeon_bs_code_fixed_bits(bs, hrd->vcl_hrd_parameters_present_flag, 1);
+      if (hrd->nal_hrd_parameters_present_flag || hrd->vcl_hrd_parameters_present_flag) {
+         radeon_bs_code_fixed_bits(bs, hrd->sub_pic_hrd_params_present_flag, 1);
+         if (hrd->sub_pic_hrd_params_present_flag) {
+            radeon_bs_code_fixed_bits(bs, hrd->tick_divisor_minus2, 8);
+            radeon_bs_code_fixed_bits(bs, hrd->du_cpb_removal_delay_increment_length_minus1, 5);
+            radeon_bs_code_fixed_bits(bs, hrd->sub_pic_hrd_params_present_flag, 1);
+            radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_du_length_minus1, 5);
+         }
+         radeon_bs_code_fixed_bits(bs, hrd->bit_rate_scale, 4);
+         radeon_bs_code_fixed_bits(bs, hrd->cpb_rate_scale, 4);
+         if (hrd->sub_pic_hrd_params_present_flag)
+            radeon_bs_code_fixed_bits(bs, hrd->cpb_size_du_scale, 4);
+         radeon_bs_code_fixed_bits(bs, hrd->initial_cpb_removal_delay_length_minus1, 5);
+         radeon_bs_code_fixed_bits(bs, hrd->au_cpb_removal_delay_length_minus1, 5);
+         radeon_bs_code_fixed_bits(bs, hrd->dpb_output_delay_length_minus1, 5);
+      }
+   }
+
+   for (uint32_t i = 0; i <= max_sub_layers_minus1; i++) {
+      radeon_bs_code_fixed_bits(bs, hrd->fixed_pic_rate_general_flag[i], 1);
+      if (!hrd->fixed_pic_rate_general_flag[i])
+         radeon_bs_code_fixed_bits(bs, hrd->fixed_pic_rate_within_cvs_flag[i], 1);
+      if (hrd->fixed_pic_rate_within_cvs_flag[i])
+         radeon_bs_code_ue(bs, hrd->elemental_duration_in_tc_minus1[i]);
+      else
+         radeon_bs_code_fixed_bits(bs, hrd->low_delay_hrd_flag[i], 1);
+      if (!hrd->low_delay_hrd_flag[i])
+         radeon_bs_code_ue(bs, hrd->cpb_cnt_minus1[i]);
+      if (hrd->nal_hrd_parameters_present_flag) {
+         radeon_bs_hevc_sub_layer_hrd_parameters(bs,
+                                                 hrd->cpb_cnt_minus1[i] + 1,
+                                                 hrd->sub_pic_hrd_params_present_flag,
+                                                 &hrd->nal_hrd_parameters[i]);
+      }
+      if (hrd->vcl_hrd_parameters_present_flag) {
+         radeon_bs_hevc_sub_layer_hrd_parameters(bs,
+                                                 hrd->cpb_cnt_minus1[i] + 1,
+                                                 hrd->sub_pic_hrd_params_present_flag,
+                                                 &hrd->vlc_hrd_parameters[i]);
+      }
+   }
+}
+
+/* returns NumPicTotalCurr */
+uint32_t radeon_bs_hevc_st_ref_pic_set(struct radeon_bitstream *bs,
+                                       uint32_t index,
+                                       uint32_t num_short_term_ref_pic_sets,
+                                       struct pipe_h265_st_ref_pic_set *st_rps)
+{
+   struct pipe_h265_st_ref_pic_set *ref_rps = NULL;
+   struct pipe_h265_st_ref_pic_set *rps = &st_rps[index];
+   uint32_t i, num_pic_total_curr = 0;
+
+   if (index)
+      radeon_bs_code_fixed_bits(bs, rps->inter_ref_pic_set_prediction_flag, 1);
+
+   if (rps->inter_ref_pic_set_prediction_flag) {
+      if (index == num_short_term_ref_pic_sets)
+         radeon_bs_code_ue(bs, rps->delta_idx_minus1);
+      radeon_bs_code_fixed_bits(bs, rps->delta_rps_sign, 1);
+      radeon_bs_code_ue(bs, rps->abs_delta_rps_minus1);
+      ref_rps = st_rps + index +
+         (1 - 2 * rps->delta_rps_sign) * (st_rps->delta_idx_minus1 + 1);
+      for (i = 0; i <= (ref_rps->num_negative_pics + ref_rps->num_positive_pics); i++) {
+         radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_flag[i], 1);
+         if (!rps->used_by_curr_pic_flag[i])
+            radeon_bs_code_fixed_bits(bs, rps->use_delta_flag[i], 1);
+      }
+   } else {
+      radeon_bs_code_ue(bs, rps->num_negative_pics);
+      radeon_bs_code_ue(bs, rps->num_positive_pics);
+      for (i = 0; i < rps->num_negative_pics; i++) {
+         radeon_bs_code_ue(bs, rps->delta_poc_s0_minus1[i]);
+         radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_s0_flag[i], 1);
+         if (rps->used_by_curr_pic_s0_flag[i])
+            num_pic_total_curr++;
+      }
+      for (i = 0; i < st_rps->num_positive_pics; i++) {
+         radeon_bs_code_ue(bs, rps->delta_poc_s1_minus1[i]);
+         radeon_bs_code_fixed_bits(bs, rps->used_by_curr_pic_s1_flag[i], 1);
+         if (rps->used_by_curr_pic_s1_flag[i])
+            num_pic_total_curr++;
+      }
+   }
+
+   return num_pic_total_curr;
+}
diff --git a/src/gallium/drivers/radeonsi/radeon_bitstream.h b/src/gallium/drivers/radeonsi/radeon_bitstream.h
new file mode 100644
index 00000000000..2713cdfae6b
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/radeon_bitstream.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef RADEON_BITSTREAM_H
+#define RADEON_BITSTREAM_H
+
+#include "pipe/p_video_state.h"
+#include "winsys/radeon_winsys.h"
+
+struct radeon_bitstream {
+   bool emulation_prevention;
+   uint32_t shifter;
+   uint32_t bits_in_shifter;
+   uint32_t num_zeros;
+   uint32_t byte_index;
+   uint32_t bits_output;
+   uint32_t bits_size;
+   uint8_t *buf;
+   struct radeon_cmdbuf *cs;
+};
+
+void radeon_bs_reset(struct radeon_bitstream *bs, uint8_t *out, struct radeon_cmdbuf *cs);
+void radeon_bs_set_emulation_prevention(struct radeon_bitstream *bs, bool set);
+void radeon_bs_byte_align(struct radeon_bitstream *bs);
+void radeon_bs_flush_headers(struct radeon_bitstream *bs);
+
+void radeon_bs_code_fixed_bits(struct radeon_bitstream *bs, uint32_t value, uint32_t num_bits);
+void radeon_bs_code_ue(struct radeon_bitstream *bs, uint32_t value);
+void radeon_bs_code_se(struct radeon_bitstream *bs, int32_t value);
+void radeon_bs_code_uvlc(struct radeon_bitstream *bs, uint32_t value);
+void radeon_bs_code_ns(struct radeon_bitstream *bs, uint32_t value, uint32_t max);
+
+void radeon_bs_h264_hrd_parameters(struct radeon_bitstream *bs,
+                                   struct pipe_h264_enc_hrd_params *hrd);
+
+void radeon_bs_hevc_profile_tier_level(struct radeon_bitstream *bs,
+                                       uint32_t max_num_sub_layers_minus1,
+                                       struct pipe_h265_profile_tier_level *ptl);
+
+void radeon_bs_hevc_hrd_parameters(struct radeon_bitstream *bs,
+                                   uint32_t common_inf_present_flag,
+                                   uint32_t max_sub_layers_minus1,
+                                   struct pipe_h265_enc_hrd_params *hrd);
+
+uint32_t radeon_bs_hevc_st_ref_pic_set(struct radeon_bitstream *bs,
+                                       uint32_t index,
+                                       uint32_t num_short_term_ref_pic_sets,
+                                       struct pipe_h265_st_ref_pic_set *st_rps);
+
+#endif
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
index e58ab6810a1..66ab0d47c79 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
@@ -17,8 +17,6 @@
 #include "util/u_video.h"
 #include "vl/vl_video_buffer.h"
 
-static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
-
 /* set quality modes from the input */
 static void radeon_vcn_enc_quality_modes(struct radeon_encoder *enc,
                                          struct pipe_enc_quality_modes *in)
@@ -1980,7 +1978,6 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
    enc->base.fence_wait = radeon_enc_fence_wait;
    enc->base.destroy_fence = radeon_enc_destroy_fence;
    enc->get_buffer = get_buffer;
-   enc->bits_in_shifter = 0;
    enc->screen = context->screen;
    enc->ws = ws;
 
@@ -2048,96 +2045,6 @@ void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *bu
    RADEON_ENC_CS(addr);
 }
 
-void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set)
-{
-   if (set != enc->emulation_prevention) {
-      enc->emulation_prevention = set;
-      enc->num_zeros = 0;
-   }
-}
-
-void radeon_enc_set_output_buffer(struct radeon_encoder *enc, uint8_t *buffer)
-{
-   enc->bits_buf = buffer;
-   enc->bits_buf_pos = 0;
-}
-
-void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
-{
-   if (enc->bits_buf) {
-      enc->bits_buf[enc->bits_buf_pos++] = byte;
-      return;
-   }
-
-   if (enc->byte_index == 0)
-      enc->cs.current.buf[enc->cs.current.cdw] = 0;
-   enc->cs.current.buf[enc->cs.current.cdw] |=
-      ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
-   enc->byte_index++;
-
-   if (enc->byte_index >= 4) {
-      enc->byte_index = 0;
-      enc->cs.current.cdw++;
-   }
-}
-
-void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte)
-{
-   if (enc->emulation_prevention) {
-      if ((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) ||
-         (byte == 0x02) || (byte == 0x03))) {
-         radeon_enc_output_one_byte(enc, 0x03);
-         enc->bits_output += 8;
-         enc->num_zeros = 0;
-      }
-      enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
-   }
-}
-
-void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
-                                unsigned int num_bits)
-{
-   unsigned int bits_to_pack = 0;
-   enc->bits_size += num_bits;
-
-   while (num_bits > 0) {
-      unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
-      bits_to_pack =
-         num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
-
-      if (bits_to_pack < num_bits)
-         value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
-
-      enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
-      num_bits -= bits_to_pack;
-      enc->bits_in_shifter += bits_to_pack;
-
-      while (enc->bits_in_shifter >= 8) {
-         unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
-         enc->shifter <<= 8;
-         radeon_enc_emulation_prevention(enc, output_byte);
-         radeon_enc_output_one_byte(enc, output_byte);
-         enc->bits_in_shifter -= 8;
-         enc->bits_output += 8;
-      }
-   }
-}
-
-void radeon_enc_code_uvlc(struct radeon_encoder *enc, unsigned int value)
-{
-   uint32_t num_bits = 0;
-   uint64_t value_plus1 = (uint64_t)value + 1;
-   uint32_t num_leading_zeros = 0;
-
-   while ((uint64_t)1 << num_bits <= value_plus1)
-      num_bits++;
-
-   num_leading_zeros = num_bits - 1;
-   radeon_enc_code_fixed_bits(enc, 0, num_leading_zeros);
-   radeon_enc_code_fixed_bits(enc, 1, 1);
-   radeon_enc_code_fixed_bits(enc, (uint32_t)value_plus1, num_leading_zeros);
-}
-
 void radeon_enc_code_leb128(uint8_t *buf, uint32_t value,
                             uint32_t num_bytes)
 {
@@ -2156,71 +2063,6 @@ void radeon_enc_code_leb128(uint8_t *buf, uint32_t value,
    } while((leb128_byte & 0x80));
 }
 
-void radeon_enc_reset(struct radeon_encoder *enc)
-{
-   enc->emulation_prevention = false;
-   enc->shifter = 0;
-   enc->bits_in_shifter = 0;
-   enc->bits_output = 0;
-   enc->num_zeros = 0;
-   enc->byte_index = 0;
-   enc->bits_size = 0;
-   enc->bits_buf = NULL;
-   enc->bits_buf_pos = 0;
-}
-
-void radeon_enc_byte_align(struct radeon_encoder *enc)
-{
-   unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
-
-   if (num_padding_zeros > 0)
-      radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros);
-}
-
-void radeon_enc_flush_headers(struct radeon_encoder *enc)
-{
-   if (enc->bits_in_shifter != 0) {
-      unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
-      radeon_enc_emulation_prevention(enc, output_byte);
-      radeon_enc_output_one_byte(enc, output_byte);
-      enc->bits_output += enc->bits_in_shifter;
-      enc->shifter = 0;
-      enc->bits_in_shifter = 0;
-      enc->num_zeros = 0;
-   }
-
-   if (enc->byte_index > 0) {
-      enc->cs.current.cdw++;
-      enc->byte_index = 0;
-   }
-}
-
-void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value)
-{
-   unsigned int x = 0;
-   unsigned int ue_code = value + 1;
-   value += 1;
-
-   while (value) {
-      value = (value >> 1);
-      x += 1;
-   }
-
-   if (x > 1)
-     radeon_enc_code_fixed_bits(enc, 0, x - 1);
-   radeon_enc_code_fixed_bits(enc, ue_code, x);
-}
-
-void radeon_enc_code_se(struct radeon_encoder *enc, int value)
-{
-   unsigned int v = 0;
-
-   if (value != 0)
-      v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
-
-   radeon_enc_code_ue(enc, v);
-}
-
 unsigned int radeon_enc_av1_tile_log2(unsigned int blk_size, unsigned int max)
 {
    unsigned int k;
@@ -2231,30 +2073,6 @@ unsigned int radeon_enc_av1_tile_log2(unsigned int blk_size, unsigned int max)
    return k;
 }
 
-void radeon_enc_code_ns(struct radeon_encoder *enc, unsigned int value, unsigned int max)
-{
-   unsigned w = 0;
-   unsigned m;
-   unsigned max_num = max;
-
-   while ( max_num ) {
-      max_num >>= 1;
-      w++;
-   }
-
-   m = ( 1 << w ) - max;
-
-   assert(w > 1);
-
-   if ( value < m )
-      radeon_enc_code_fixed_bits(enc, value, (w - 1));
-   else {
-      unsigned diff = value - m;
-      unsigned out = (((diff >> 1) + m) << 1) | (diff & 0x1);
-      radeon_enc_code_fixed_bits(enc, out, w);
-   }
-}
-
 /* dummy function for re-using the same pipeline */
 void radeon_enc_dummy(struct radeon_encoder *enc) {}
 
@@ -2269,13 +2087,14 @@ static void radeon_enc_av1_bs_copy_end(struct radeon_encoder *enc, uint32_t bits
 
 /* av1 bitstream instruction type */
 void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc,
+                                        struct radeon_bitstream *bs,
                                         uint32_t inst,
                                         uint32_t obu_type)
 {
-   radeon_enc_flush_headers(enc);
+   radeon_bs_flush_headers(bs);
 
-   if (enc->bits_output)
-      radeon_enc_av1_bs_copy_end(enc, enc->bits_output);
+   if (bs->bits_output)
+      radeon_enc_av1_bs_copy_end(enc, bs->bits_output);
 
    enc->enc_pic.copy_start = &enc->cs.current.buf[enc->cs.current.cdw++];
    RADEON_ENC_CS(inst);
@@ -2289,7 +2108,7 @@ void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc,
    } else
       RADEON_ENC_CS(0); /* allocate a dword for number of bits */
 
-   radeon_enc_reset(enc);
+   radeon_bs_reset(bs, NULL, &enc->cs);
 }
 
 uint32_t radeon_enc_value_bits(uint32_t value)
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.h b/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
index 763a80cfaf2..298004902b6 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
@@ -11,6 +11,7 @@
 
 #include "radeon_vcn.h"
 #include "util/macros.h"
+#include "radeon_bitstream.h"
 
 #include "ac_vcn_enc.h"
 
@@ -248,19 +249,10 @@ struct radeon_encoder {
    rvcn_enc_cmd_t cmd;
 
    unsigned alignment;
-   unsigned shifter;
-   unsigned bits_in_shifter;
-   unsigned num_zeros;
-   unsigned byte_index;
-   unsigned bits_output;
-   unsigned bits_size;
-   uint8_t *bits_buf;
-   uint32_t bits_buf_pos;
    uint32_t total_task_size;
    uint32_t *p_task_size;
    struct rvcn_sq_var sq;
 
-   bool emulation_prevention;
    bool need_feedback;
    bool need_rate_control;
    bool need_rc_per_pic;
@@ -312,35 +304,9 @@ void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *bu
 
 void radeon_enc_dummy(struct radeon_encoder *enc);
 
-void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set);
-
-void radeon_enc_set_output_buffer(struct radeon_encoder *enc, uint8_t *buffer);
-
-void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte);
-
-void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte);
-
-void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
-                                unsigned int num_bits);
-
-void radeon_enc_reset(struct radeon_encoder *enc);
-
-void radeon_enc_byte_align(struct radeon_encoder *enc);
-
-void radeon_enc_flush_headers(struct radeon_encoder *enc);
-
-void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value);
-
-void radeon_enc_code_se(struct radeon_encoder *enc, int value);
-
-void radeon_enc_code_uvlc(struct radeon_encoder *enc, unsigned int value);
-
 void radeon_enc_code_leb128(unsigned char *buf, unsigned int value,
                             unsigned int num_bytes);
 
-void radeon_enc_code_ns(struct radeon_encoder *enc, unsigned int value,
-                        unsigned int max);
-
 void radeon_enc_1_2_init(struct radeon_encoder *enc);
 
 void radeon_enc_2_0_init(struct radeon_encoder *enc);
@@ -363,33 +329,15 @@ unsigned int radeon_enc_write_pps_hevc(struct radeon_encoder *enc, uint8_t *out)
 
 unsigned int radeon_enc_write_sequence_header(struct radeon_encoder *enc, uint8_t *obu_bytes, uint8_t *out);
 
-void radeon_enc_hrd_parameters(struct radeon_encoder *enc,
-                               struct pipe_h264_enc_hrd_params *hrd);
-
-void radeon_enc_hevc_profile_tier_level(struct radeon_encoder *enc,
-                                        unsigned int max_num_sub_layers_minus1,
-                                        struct pipe_h265_profile_tier_level *ptl);
-
-void radeon_enc_hevc_hrd_parameters(struct radeon_encoder *enc,
-                                    unsigned int common_inf_present_flag,
-                                    unsigned int max_sub_layers_minus1,
-                                    struct pipe_h265_enc_hrd_params *hrd);
-
-unsigned int radeon_enc_hevc_st_ref_pic_set(struct radeon_encoder *enc,
-                                            unsigned int index,
-                                            unsigned int num_short_term_ref_pic_sets,
-                                            struct pipe_h265_st_ref_pic_set *st_rps);
-
 void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc,
+                                        struct radeon_bitstream *bs,
                                         unsigned int inst, unsigned int obu_type);
 
-void radeon_enc_av1_obu_header(struct radeon_encoder *enc, uint32_t obu_type);
+void radeon_enc_av1_obu_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, uint32_t obu_type);
 
-void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_header);
+void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header);
 
-void radeon_enc_av1_tile_group(struct radeon_encoder *enc);
-
-unsigned char *radeon_enc_av1_header_size_offset(struct radeon_encoder *enc);
+void radeon_enc_av1_tile_group(struct radeon_encoder *enc, struct radeon_bitstream *bs);
 
 unsigned int radeon_enc_value_bits(unsigned int value);
 
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
index 86653e6988c..cf7b20ea8eb 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
@@ -179,157 +179,153 @@ static void radeon_enc_quality_params(struct radeon_encoder *enc)
 
 unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out)
 {
+   struct radeon_bitstream bs;
    struct radeon_enc_pic *pic = &enc->enc_pic;
    struct pipe_h264_enc_seq_param *sps = &pic->h264.desc->seq;
 
-   radeon_enc_reset(enc);
-   radeon_enc_set_output_buffer(enc, out);
-   radeon_enc_set_emulation_prevention(enc, false);
-   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
-   radeon_enc_code_fixed_bits(enc, nal_byte, 8);
-   radeon_enc_byte_align(enc);
-   radeon_enc_set_emulation_prevention(enc, true);
-   radeon_enc_code_fixed_bits(enc, pic->spec_misc.profile_idc, 8);
-   radeon_enc_code_fixed_bits(enc, sps->enc_constraint_set_flags, 6);
-   radeon_enc_code_fixed_bits(enc, 0x0, 2); /* reserved_zero_2bits */
-   radeon_enc_code_fixed_bits(enc, pic->spec_misc.level_idc, 8);
-   radeon_enc_code_ue(enc, 0x0); /* seq_parameter_set_id */
+   radeon_bs_reset(&bs, out, NULL);
+   radeon_bs_set_emulation_prevention(&bs, false);
+   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
+   radeon_bs_code_fixed_bits(&bs, nal_byte, 8);
+   radeon_bs_set_emulation_prevention(&bs, true);
+   radeon_bs_code_fixed_bits(&bs, pic->spec_misc.profile_idc, 8);
+   radeon_bs_code_fixed_bits(&bs, sps->enc_constraint_set_flags, 6);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* reserved_zero_2bits */
+   radeon_bs_code_fixed_bits(&bs, pic->spec_misc.level_idc, 8);
+   radeon_bs_code_ue(&bs, 0x0); /* seq_parameter_set_id */
 
    if (pic->spec_misc.profile_idc == 100 || pic->spec_misc.profile_idc == 110 ||
        pic->spec_misc.profile_idc == 122 || pic->spec_misc.profile_idc == 244 ||
        pic->spec_misc.profile_idc == 44  || pic->spec_misc.profile_idc == 83 ||
        pic->spec_misc.profile_idc == 86  || pic->spec_misc.profile_idc == 118 ||
        pic->spec_misc.profile_idc == 128 || pic->spec_misc.profile_idc == 138) {
-      radeon_enc_code_ue(enc, 0x1); /* chroma_format_idc */
-      radeon_enc_code_ue(enc, 0x0); /* bit_depth_luma_minus8 */
-      radeon_enc_code_ue(enc, 0x0); /* bit_depth_chroma_minus8 */
-      radeon_enc_code_fixed_bits(enc, 0x0, 2); /* qpprime_y_zero_transform_bypass_flag + seq_scaling_matrix_present_flag */
+      radeon_bs_code_ue(&bs, 0x1); /* chroma_format_idc */
+      radeon_bs_code_ue(&bs, 0x0); /* bit_depth_luma_minus8 */
+      radeon_bs_code_ue(&bs, 0x0); /* bit_depth_chroma_minus8 */
+      radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* qpprime_y_zero_transform_bypass_flag + seq_scaling_matrix_present_flag */
    }
 
-   radeon_enc_code_ue(enc, sps->log2_max_frame_num_minus4);
-   radeon_enc_code_ue(enc, sps->pic_order_cnt_type);
+   radeon_bs_code_ue(&bs, sps->log2_max_frame_num_minus4);
+   radeon_bs_code_ue(&bs, sps->pic_order_cnt_type);
 
    if (sps->pic_order_cnt_type == 0)
-      radeon_enc_code_ue(enc, sps->log2_max_pic_order_cnt_lsb_minus4);
+      radeon_bs_code_ue(&bs, sps->log2_max_pic_order_cnt_lsb_minus4);
 
-   radeon_enc_code_ue(enc, sps->max_num_ref_frames);
-   radeon_enc_code_fixed_bits(enc, sps->gaps_in_frame_num_value_allowed_flag, 1);
-   radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_width / 16 - 1));
-   radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_height / 16 - 1));
-   radeon_enc_code_fixed_bits(enc, 0x1, 1); /* frame_mbs_only_flag */
-   radeon_enc_code_fixed_bits(enc, 0x1, 1); /* direct_8x8_inference_flag */
+   radeon_bs_code_ue(&bs, sps->max_num_ref_frames);
+   radeon_bs_code_fixed_bits(&bs, sps->gaps_in_frame_num_value_allowed_flag, 1);
+   radeon_bs_code_ue(&bs, (pic->session_init.aligned_picture_width / 16 - 1));
+   radeon_bs_code_ue(&bs, (pic->session_init.aligned_picture_height / 16 - 1));
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* frame_mbs_only_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* direct_8x8_inference_flag */
 
-   radeon_enc_code_fixed_bits(enc, sps->enc_frame_cropping_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, sps->enc_frame_cropping_flag, 1);
    if (sps->enc_frame_cropping_flag) {
-      radeon_enc_code_ue(enc, sps->enc_frame_crop_left_offset);
-      radeon_enc_code_ue(enc, sps->enc_frame_crop_right_offset);
-      radeon_enc_code_ue(enc, sps->enc_frame_crop_top_offset);
-      radeon_enc_code_ue(enc, sps->enc_frame_crop_bottom_offset);
+      radeon_bs_code_ue(&bs, sps->enc_frame_crop_left_offset);
+      radeon_bs_code_ue(&bs, sps->enc_frame_crop_right_offset);
+      radeon_bs_code_ue(&bs, sps->enc_frame_crop_top_offset);
+      radeon_bs_code_ue(&bs, sps->enc_frame_crop_bottom_offset);
    }
 
-   radeon_enc_code_fixed_bits(enc, sps->vui_parameters_present_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, sps->vui_parameters_present_flag, 1);
    if (sps->vui_parameters_present_flag) {
-      radeon_enc_code_fixed_bits(enc, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
+      radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
       if (sps->vui_flags.aspect_ratio_info_present_flag) {
-         radeon_enc_code_fixed_bits(enc, (sps->aspect_ratio_idc), 8);
+         radeon_bs_code_fixed_bits(&bs, (sps->aspect_ratio_idc), 8);
          if (sps->aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
-            radeon_enc_code_fixed_bits(enc, (sps->sar_width), 16);
-            radeon_enc_code_fixed_bits(enc, (sps->sar_height), 16);
+            radeon_bs_code_fixed_bits(&bs, (sps->sar_width), 16);
+            radeon_bs_code_fixed_bits(&bs, (sps->sar_height), 16);
          }
       }
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.overscan_info_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_info_present_flag, 1);
       if (sps->vui_flags.overscan_info_present_flag)
-         radeon_enc_code_fixed_bits(enc, sps->vui_flags.overscan_appropriate_flag, 1);
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.video_signal_type_present_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_appropriate_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.video_signal_type_present_flag, 1);
       if (sps->vui_flags.video_signal_type_present_flag) {
-         radeon_enc_code_fixed_bits(enc, sps->video_format, 3);
-         radeon_enc_code_fixed_bits(enc, sps->video_full_range_flag, 1);
-         radeon_enc_code_fixed_bits(enc, sps->vui_flags.colour_description_present_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, sps->video_format, 3);
+         radeon_bs_code_fixed_bits(&bs, sps->video_full_range_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.colour_description_present_flag, 1);
          if (sps->vui_flags.colour_description_present_flag) {
-            radeon_enc_code_fixed_bits(enc, sps->colour_primaries, 8);
-            radeon_enc_code_fixed_bits(enc, sps->transfer_characteristics, 8);
-            radeon_enc_code_fixed_bits(enc, sps->matrix_coefficients, 8);
+            radeon_bs_code_fixed_bits(&bs, sps->colour_primaries, 8);
+            radeon_bs_code_fixed_bits(&bs, sps->transfer_characteristics, 8);
+            radeon_bs_code_fixed_bits(&bs, sps->matrix_coefficients, 8);
          }
       }
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.chroma_loc_info_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.chroma_loc_info_present_flag, 1);
       if (sps->vui_flags.chroma_loc_info_present_flag) {
-         radeon_enc_code_ue(enc, sps->chroma_sample_loc_type_top_field);
-         radeon_enc_code_ue(enc, sps->chroma_sample_loc_type_bottom_field);
+         radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_top_field);
+         radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_bottom_field);
       }
-      radeon_enc_code_fixed_bits(enc, (sps->vui_flags.timing_info_present_flag), 1);
+      radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.timing_info_present_flag), 1);
       if (sps->vui_flags.timing_info_present_flag) {
-         radeon_enc_code_fixed_bits(enc, (sps->num_units_in_tick), 32);
-         radeon_enc_code_fixed_bits(enc, (sps->time_scale), 32);
-         radeon_enc_code_fixed_bits(enc, (sps->vui_flags.fixed_frame_rate_flag), 1);
+         radeon_bs_code_fixed_bits(&bs, (sps->num_units_in_tick), 32);
+         radeon_bs_code_fixed_bits(&bs, (sps->time_scale), 32);
+         radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.fixed_frame_rate_flag), 1);
       }
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.nal_hrd_parameters_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.nal_hrd_parameters_present_flag, 1);
       if (sps->vui_flags.nal_hrd_parameters_present_flag)
-         radeon_enc_hrd_parameters(enc, &sps->nal_hrd_parameters);
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.vcl_hrd_parameters_present_flag, 1);
+         radeon_bs_h264_hrd_parameters(&bs, &sps->nal_hrd_parameters);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.vcl_hrd_parameters_present_flag, 1);
       if (sps->vui_flags.vcl_hrd_parameters_present_flag)
-         radeon_enc_hrd_parameters(enc, &sps->vcl_hrd_parameters);
+         radeon_bs_h264_hrd_parameters(&bs, &sps->vcl_hrd_parameters);
       if (sps->vui_flags.nal_hrd_parameters_present_flag || sps->vui_flags.vcl_hrd_parameters_present_flag)
-         radeon_enc_code_fixed_bits(enc, sps->vui_flags.low_delay_hrd_flag, 1);
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.pic_struct_present_flag, 1);
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.bitstream_restriction_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.low_delay_hrd_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.pic_struct_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.bitstream_restriction_flag, 1);
       if (sps->vui_flags.bitstream_restriction_flag) {
-         radeon_enc_code_fixed_bits(enc, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
-         radeon_enc_code_ue(enc, 0x0); /* max_bytes_per_pic_denom */
-         radeon_enc_code_ue(enc, 0x0); /* max_bits_per_mb_denom */
-         radeon_enc_code_ue(enc, 16); /* log2_max_mv_length_horizontal */
-         radeon_enc_code_ue(enc, 16); /* log2_max_mv_length_vertical */
-         radeon_enc_code_ue(enc, sps->max_num_reorder_frames);
-         radeon_enc_code_ue(enc, sps->max_dec_frame_buffering);
+         radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
+         radeon_bs_code_ue(&bs, 0x0); /* max_bytes_per_pic_denom */
+         radeon_bs_code_ue(&bs, 0x0); /* max_bits_per_mb_denom */
+         radeon_bs_code_ue(&bs, 16); /* log2_max_mv_length_horizontal */
+         radeon_bs_code_ue(&bs, 16); /* log2_max_mv_length_vertical */
+         radeon_bs_code_ue(&bs, sps->max_num_reorder_frames);
+         radeon_bs_code_ue(&bs, sps->max_dec_frame_buffering);
       }
    }
 
-   radeon_enc_code_fixed_bits(enc, 0x1, 1);
-   radeon_enc_byte_align(enc);
-   radeon_enc_flush_headers(enc);
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
+   radeon_bs_byte_align(&bs);
 
-   return enc->bits_buf_pos;
+   return bs.bits_output / 8;
 }
 
 unsigned int radeon_enc_write_sps_hevc(struct radeon_encoder *enc, uint8_t *out)
 {
+   struct radeon_bitstream bs;
    struct radeon_enc_pic *pic = &enc->enc_pic;
    struct pipe_h265_enc_seq_param *sps = &pic->hevc.desc->seq;
    int i;
 
-   radeon_enc_reset(enc);
-   radeon_enc_set_output_buffer(enc, out);
-   radeon_enc_set_emulation_prevention(enc, false);
-   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
-   radeon_enc_code_fixed_bits(enc, 0x4201, 16);
-   radeon_enc_byte_align(enc);
-   radeon_enc_set_emulation_prevention(enc, true);
-   radeon_enc_code_fixed_bits(enc, 0x0, 4); /* sps_video_parameter_set_id */
-   radeon_enc_code_fixed_bits(enc, sps->sps_max_sub_layers_minus1, 3);
-   radeon_enc_code_fixed_bits(enc, sps->sps_temporal_id_nesting_flag, 1);
-   radeon_enc_hevc_profile_tier_level(enc, sps->sps_max_sub_layers_minus1, &sps->profile_tier_level);
-   radeon_enc_code_ue(enc, 0x0); /* sps_seq_parameter_set_id */
-   radeon_enc_code_ue(enc, sps->chroma_format_idc);
-   radeon_enc_code_ue(enc, pic->session_init.aligned_picture_width);
-   radeon_enc_code_ue(enc, pic->session_init.aligned_picture_height);
+   radeon_bs_reset(&bs, out, NULL);
+   radeon_bs_set_emulation_prevention(&bs, false);
+   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
+   radeon_bs_code_fixed_bits(&bs, 0x4201, 16);
+   radeon_bs_set_emulation_prevention(&bs, true);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 4); /* sps_video_parameter_set_id */
+   radeon_bs_code_fixed_bits(&bs, sps->sps_max_sub_layers_minus1, 3);
+   radeon_bs_code_fixed_bits(&bs, sps->sps_temporal_id_nesting_flag, 1);
+   radeon_bs_hevc_profile_tier_level(&bs, sps->sps_max_sub_layers_minus1, &sps->profile_tier_level);
+   radeon_bs_code_ue(&bs, 0x0); /* sps_seq_parameter_set_id */
+   radeon_bs_code_ue(&bs, sps->chroma_format_idc);
+   radeon_bs_code_ue(&bs, pic->session_init.aligned_picture_width);
+   radeon_bs_code_ue(&bs, pic->session_init.aligned_picture_height);
 
+   radeon_bs_code_fixed_bits(&bs, sps->conformance_window_flag, 1);
    if (sps->conformance_window_flag) {
-      radeon_enc_code_fixed_bits(enc, 0x1, 1);
-      radeon_enc_code_ue(enc, sps->conf_win_left_offset);
-      radeon_enc_code_ue(enc, sps->conf_win_right_offset);
-      radeon_enc_code_ue(enc, sps->conf_win_top_offset);
-      radeon_enc_code_ue(enc, sps->conf_win_bottom_offset);
-   } else
-      radeon_enc_code_fixed_bits(enc, 0x0, 1);
+      radeon_bs_code_ue(&bs, sps->conf_win_left_offset);
+      radeon_bs_code_ue(&bs, sps->conf_win_right_offset);
+      radeon_bs_code_ue(&bs, sps->conf_win_top_offset);
+      radeon_bs_code_ue(&bs, sps->conf_win_bottom_offset);
+   }
 
-   radeon_enc_code_ue(enc, sps->bit_depth_luma_minus8);
-   radeon_enc_code_ue(enc, sps->bit_depth_chroma_minus8);
-   radeon_enc_code_ue(enc, sps->log2_max_pic_order_cnt_lsb_minus4);
-   radeon_enc_code_fixed_bits(enc, sps->sps_sub_layer_ordering_info_present_flag, 1);
+   radeon_bs_code_ue(&bs, sps->bit_depth_luma_minus8);
+   radeon_bs_code_ue(&bs, sps->bit_depth_chroma_minus8);
+   radeon_bs_code_ue(&bs, sps->log2_max_pic_order_cnt_lsb_minus4);
+   radeon_bs_code_fixed_bits(&bs, sps->sps_sub_layer_ordering_info_present_flag, 1);
    i = sps->sps_sub_layer_ordering_info_present_flag ? 0 : sps->sps_max_sub_layers_minus1;
    for (; i <= sps->sps_max_sub_layers_minus1; i++) {
-      radeon_enc_code_ue(enc, sps->sps_max_dec_pic_buffering_minus1[i]);
-      radeon_enc_code_ue(enc, sps->sps_max_num_reorder_pics[i]);
-      radeon_enc_code_ue(enc, sps->sps_max_latency_increase_plus1[i]);
+      radeon_bs_code_ue(&bs, sps->sps_max_dec_pic_buffering_minus1[i]);
+      radeon_bs_code_ue(&bs, sps->sps_max_num_reorder_pics[i]);
+      radeon_bs_code_ue(&bs, sps->sps_max_latency_increase_plus1[i]);
    }
 
    unsigned log2_diff_max_min_luma_coding_block_size =
@@ -340,234 +336,228 @@ unsigned int radeon_enc_write_sps_hevc(struct radeon_encoder *enc, uint8_t *out)
    unsigned max_transform_hierarchy_depth_inter = log2_diff_max_min_luma_coding_block_size + 1;
    unsigned max_transform_hierarchy_depth_intra = max_transform_hierarchy_depth_inter;
 
-   radeon_enc_code_ue(enc, pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
-   radeon_enc_code_ue(enc, log2_diff_max_min_luma_coding_block_size);
-   radeon_enc_code_ue(enc, log2_min_transform_block_size_minus2);
-   radeon_enc_code_ue(enc, log2_diff_max_min_transform_block_size);
-   radeon_enc_code_ue(enc, max_transform_hierarchy_depth_inter);
-   radeon_enc_code_ue(enc, max_transform_hierarchy_depth_intra);
+   radeon_bs_code_ue(&bs, pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
+   radeon_bs_code_ue(&bs, log2_diff_max_min_luma_coding_block_size);
+   radeon_bs_code_ue(&bs, log2_min_transform_block_size_minus2);
+   radeon_bs_code_ue(&bs, log2_diff_max_min_transform_block_size);
+   radeon_bs_code_ue(&bs, max_transform_hierarchy_depth_inter);
+   radeon_bs_code_ue(&bs, max_transform_hierarchy_depth_intra);
 
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* scaling_list_enabled_flag */
-   radeon_enc_code_fixed_bits(enc, !pic->hevc_spec_misc.amp_disabled, 1);
-   radeon_enc_code_fixed_bits(enc, !pic->hevc_deblock.disable_sao, 1);
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pcm_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* scaling_list_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, !pic->hevc_spec_misc.amp_disabled, 1);
+   radeon_bs_code_fixed_bits(&bs, !pic->hevc_deblock.disable_sao, 1);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pcm_enabled_flag */
 
-   radeon_enc_code_ue(enc, sps->num_short_term_ref_pic_sets);
+   radeon_bs_code_ue(&bs, sps->num_short_term_ref_pic_sets);
    for (i = 0; i < sps->num_short_term_ref_pic_sets; i++)
-      radeon_enc_hevc_st_ref_pic_set(enc, i, sps->num_short_term_ref_pic_sets, sps->st_ref_pic_set);
+      radeon_bs_hevc_st_ref_pic_set(&bs, i, sps->num_short_term_ref_pic_sets, sps->st_ref_pic_set);
 
-   radeon_enc_code_fixed_bits(enc, sps->long_term_ref_pics_present_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, sps->long_term_ref_pics_present_flag, 1);
    if (sps->long_term_ref_pics_present_flag) {
-      radeon_enc_code_ue(enc, sps->num_long_term_ref_pics_sps);
+      radeon_bs_code_ue(&bs, sps->num_long_term_ref_pics_sps);
       for (i = 0; i < sps->num_long_term_ref_pics_sps; i++) {
-         radeon_enc_code_fixed_bits(enc, sps->lt_ref_pic_poc_lsb_sps[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
-         radeon_enc_code_fixed_bits(enc, sps->used_by_curr_pic_lt_sps_flag[i], 1);
+         radeon_bs_code_fixed_bits(&bs, sps->lt_ref_pic_poc_lsb_sps[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
+         radeon_bs_code_fixed_bits(&bs, sps->used_by_curr_pic_lt_sps_flag[i], 1);
       }
    }
 
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* sps_temporal_mvp_enabled_flag */
-   radeon_enc_code_fixed_bits(enc, pic->hevc_spec_misc.strong_intra_smoothing_enabled, 1);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* sps_temporal_mvp_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, pic->hevc_spec_misc.strong_intra_smoothing_enabled, 1);
 
    /* VUI parameters present flag */
-   radeon_enc_code_fixed_bits(enc, (sps->vui_parameters_present_flag), 1);
+   radeon_bs_code_fixed_bits(&bs, (sps->vui_parameters_present_flag), 1);
    if (sps->vui_parameters_present_flag) {
       /* aspect ratio present flag */
-      radeon_enc_code_fixed_bits(enc, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
+      radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
       if (sps->vui_flags.aspect_ratio_info_present_flag) {
-         radeon_enc_code_fixed_bits(enc, (sps->aspect_ratio_idc), 8);
+         radeon_bs_code_fixed_bits(&bs, (sps->aspect_ratio_idc), 8);
          if (sps->aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
-            radeon_enc_code_fixed_bits(enc, (sps->sar_width), 16);
-            radeon_enc_code_fixed_bits(enc, (sps->sar_height), 16);
+            radeon_bs_code_fixed_bits(&bs, (sps->sar_width), 16);
+            radeon_bs_code_fixed_bits(&bs, (sps->sar_height), 16);
          }
       }
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.overscan_info_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_info_present_flag, 1);
       if (sps->vui_flags.overscan_info_present_flag)
-         radeon_enc_code_fixed_bits(enc, sps->vui_flags.overscan_appropriate_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_appropriate_flag, 1);
       /* video signal type present flag  */
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.video_signal_type_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.video_signal_type_present_flag, 1);
       if (sps->vui_flags.video_signal_type_present_flag) {
-         radeon_enc_code_fixed_bits(enc, sps->video_format, 3);
-         radeon_enc_code_fixed_bits(enc, sps->video_full_range_flag, 1);
-         radeon_enc_code_fixed_bits(enc, sps->vui_flags.colour_description_present_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, sps->video_format, 3);
+         radeon_bs_code_fixed_bits(&bs, sps->video_full_range_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.colour_description_present_flag, 1);
          if (sps->vui_flags.colour_description_present_flag) {
-            radeon_enc_code_fixed_bits(enc, sps->colour_primaries, 8);
-            radeon_enc_code_fixed_bits(enc, sps->transfer_characteristics, 8);
-            radeon_enc_code_fixed_bits(enc, sps->matrix_coefficients, 8);
+            radeon_bs_code_fixed_bits(&bs, sps->colour_primaries, 8);
+            radeon_bs_code_fixed_bits(&bs, sps->transfer_characteristics, 8);
+            radeon_bs_code_fixed_bits(&bs, sps->matrix_coefficients, 8);
          }
       }
       /* chroma loc info present flag */
-      radeon_enc_code_fixed_bits(enc, sps->vui_flags.chroma_loc_info_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.chroma_loc_info_present_flag, 1);
       if (sps->vui_flags.chroma_loc_info_present_flag) {
-         radeon_enc_code_ue(enc, sps->chroma_sample_loc_type_top_field);
-         radeon_enc_code_ue(enc, sps->chroma_sample_loc_type_bottom_field);
+         radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_top_field);
+         radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_bottom_field);
       }
-      radeon_enc_code_fixed_bits(enc, 0x0, 1);  /* neutral chroma indication flag */
-      radeon_enc_code_fixed_bits(enc, 0x0, 1);  /* field seq flag */
-      radeon_enc_code_fixed_bits(enc, 0x0, 1);  /* frame field info present flag */
-      radeon_enc_code_fixed_bits(enc, 0x0, 1);  /* default display windows flag */
+      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* neutral chroma indication flag */
+      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* field seq flag */
+      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* frame field info present flag */
+      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* default display windows flag */
       /* vui timing info present flag */
-      radeon_enc_code_fixed_bits(enc, (sps->vui_flags.timing_info_present_flag), 1);
+      radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.timing_info_present_flag), 1);
       if (sps->vui_flags.timing_info_present_flag) {
-         radeon_enc_code_fixed_bits(enc, (sps->num_units_in_tick), 32);
-         radeon_enc_code_fixed_bits(enc, (sps->time_scale), 32);
-         radeon_enc_code_fixed_bits(enc, sps->vui_flags.poc_proportional_to_timing_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, (sps->num_units_in_tick), 32);
+         radeon_bs_code_fixed_bits(&bs, (sps->time_scale), 32);
+         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.poc_proportional_to_timing_flag, 1);
          if (sps->vui_flags.poc_proportional_to_timing_flag)
-            radeon_enc_code_ue(enc, sps->num_ticks_poc_diff_one_minus1);
-         radeon_enc_code_fixed_bits(enc, sps->vui_flags.hrd_parameters_present_flag, 1);
+            radeon_bs_code_ue(&bs, sps->num_ticks_poc_diff_one_minus1);
+         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.hrd_parameters_present_flag, 1);
          if (sps->vui_flags.hrd_parameters_present_flag)
-            radeon_enc_hevc_hrd_parameters(enc, 1, sps->sps_max_sub_layers_minus1, &sps->hrd_parameters);
+            radeon_bs_hevc_hrd_parameters(&bs, 1, sps->sps_max_sub_layers_minus1, &sps->hrd_parameters);
       }
-      radeon_enc_code_fixed_bits(enc, 0x0, 1);  /* bitstream restriction flag */
+      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* bitstream restriction flag */
    }
-   radeon_enc_code_fixed_bits(enc, 0x0, 1);  /* sps extension present flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* sps extension present flag */
 
-   radeon_enc_code_fixed_bits(enc, 0x1, 1);
-   radeon_enc_byte_align(enc);
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
+   radeon_bs_byte_align(&bs);
 
-   radeon_enc_flush_headers(enc);
-   return enc->bits_buf_pos;
+   return bs.bits_output / 8;
 }
 
 unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out)
 {
-   radeon_enc_reset(enc);
-   radeon_enc_set_output_buffer(enc, out);
-   radeon_enc_set_emulation_prevention(enc, false);
-   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
-   radeon_enc_code_fixed_bits(enc, nal_byte, 8);
-   radeon_enc_byte_align(enc);
-   radeon_enc_set_emulation_prevention(enc, true);
-   radeon_enc_code_ue(enc, 0x0); /* pic_parameter_set_id */
-   radeon_enc_code_ue(enc, 0x0); /* seq_parameter_set_id */
-   radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bottom_field_pic_order_in_frame_present_flag */
-   radeon_enc_code_ue(enc, 0x0); /* num_slice_groups_minus_1 */
-   radeon_enc_code_ue(enc, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l0_default_active_minus1);
-   radeon_enc_code_ue(enc, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l1_default_active_minus1);
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* weighted_pred_flag */
-   radeon_enc_code_fixed_bits(enc, 0x0, 2); /* weighted_bipred_idc */
-   radeon_enc_code_se(enc, 0x0); /* pic_init_qp_minus26 */
-   radeon_enc_code_se(enc, 0x0); /* pic_init_qs_minus26 */
-   radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cb_qp_offset); /* chroma_qp_index_offset */
-   radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag), 1);
-   radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.constrained_intra_pred_flag), 1);
-   radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag), 1);
-   radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.transform_8x8_mode), 1);
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_scaling_matrix_present_flag */
-   radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cr_qp_offset); /* second_chroma_qp_index_offset */
+   struct radeon_bitstream bs;
 
-   radeon_enc_code_fixed_bits(enc, 0x1, 1);
-   radeon_enc_byte_align(enc);
+   radeon_bs_reset(&bs, out, NULL);
+   radeon_bs_set_emulation_prevention(&bs, false);
+   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
+   radeon_bs_code_fixed_bits(&bs, nal_byte, 8);
+   radeon_bs_set_emulation_prevention(&bs, true);
+   radeon_bs_code_ue(&bs, 0x0); /* pic_parameter_set_id */
+   radeon_bs_code_ue(&bs, 0x0); /* seq_parameter_set_id */
+   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* bottom_field_pic_order_in_frame_present_flag */
+   radeon_bs_code_ue(&bs, 0x0); /* num_slice_groups_minus_1 */
+   radeon_bs_code_ue(&bs, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l0_default_active_minus1);
+   radeon_bs_code_ue(&bs, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l1_default_active_minus1);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* weighted_pred_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* weighted_bipred_idc */
+   radeon_bs_code_se(&bs, 0x0); /* pic_init_qp_minus26 */
+   radeon_bs_code_se(&bs, 0x0); /* pic_init_qs_minus26 */
+   radeon_bs_code_se(&bs, enc->enc_pic.h264_deblock.cb_qp_offset); /* chroma_qp_index_offset */
+   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag), 1);
+   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.constrained_intra_pred_flag), 1);
+   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag), 1);
+   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.transform_8x8_mode), 1);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pic_scaling_matrix_present_flag */
+   radeon_bs_code_se(&bs, enc->enc_pic.h264_deblock.cr_qp_offset); /* second_chroma_qp_index_offset */
 
-   radeon_enc_flush_headers(enc);
-   return enc->bits_buf_pos;
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
+   radeon_bs_byte_align(&bs);
+
+   return bs.bits_output / 8;
 }
 
 unsigned int radeon_enc_write_pps_hevc(struct radeon_encoder *enc, uint8_t *out)
 {
+   struct radeon_bitstream bs;
    struct pipe_h265_enc_pic_param *pps = &enc->enc_pic.hevc.desc->pic;
 
-   radeon_enc_reset(enc);
-   radeon_enc_set_output_buffer(enc, out);
-   radeon_enc_set_emulation_prevention(enc, false);
-   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
-   radeon_enc_code_fixed_bits(enc, 0x4401, 16);
-   radeon_enc_byte_align(enc);
-   radeon_enc_set_emulation_prevention(enc, true);
-   radeon_enc_code_ue(enc, 0x0); /* pps_pic_parameter_set_id */
-   radeon_enc_code_ue(enc, 0x0); /* pps_seq_parameter_set_id */
-   radeon_enc_code_fixed_bits(enc, 0x1, 1); /* dependent_slice_segments_enabled_flag */
-   radeon_enc_code_fixed_bits(enc, pps->output_flag_present_flag, 1);
-   radeon_enc_code_fixed_bits(enc, 0x0, 3); /* num_extra_slice_header_bits */
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* sign_data_hiding_enabled_flag */
-   radeon_enc_code_fixed_bits(enc, 0x1, 1); /* cabac_init_present_flag */
-   radeon_enc_code_ue(enc, pps->num_ref_idx_l0_default_active_minus1);
-   radeon_enc_code_ue(enc, pps->num_ref_idx_l1_default_active_minus1);
-   radeon_enc_code_se(enc, 0x0); /* init_qp_minus26 */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
-   radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.transform_skip_disabled, 1);
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag, 1);
+   radeon_bs_reset(&bs, out, NULL);
+   radeon_bs_set_emulation_prevention(&bs, false);
+   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
+   radeon_bs_code_fixed_bits(&bs, 0x4401, 16);
+   radeon_bs_set_emulation_prevention(&bs, true);
+   radeon_bs_code_ue(&bs, 0x0); /* pps_pic_parameter_set_id */
+   radeon_bs_code_ue(&bs, 0x0); /* pps_seq_parameter_set_id */
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* dependent_slice_segments_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, pps->output_flag_present_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 3); /* num_extra_slice_header_bits */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* sign_data_hiding_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* cabac_init_present_flag */
+   radeon_bs_code_ue(&bs, pps->num_ref_idx_l0_default_active_minus1);
+   radeon_bs_code_ue(&bs, pps->num_ref_idx_l1_default_active_minus1);
+   radeon_bs_code_se(&bs, 0x0); /* init_qp_minus26 */
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, !enc->enc_pic.hevc_spec_misc.transform_skip_disabled, 1);
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag, 1);
    if (enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag)
-      radeon_enc_code_ue(enc, 0); /* diff_cu_qp_delta_depth */
-   radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
-   radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pps_slice_chroma_qp_offsets_present_flag */
-   radeon_enc_code_fixed_bits(enc, 0x0, 2); /* weighted_pred_flag + weighted_bipred_flag */
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* transquant_bypass_enabled_flag */
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* tiles_enabled_flag */
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* entropy_coding_sync_enabled_flag */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
-   radeon_enc_code_fixed_bits(enc, 0x1, 1); /* deblocking_filter_control_present_flag */
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* deblocking_filter_override_enabled_flag */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
+      radeon_bs_code_ue(&bs, 0); /* diff_cu_qp_delta_depth */
+   radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.cb_qp_offset);
+   radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.cr_qp_offset);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pps_slice_chroma_qp_offsets_present_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* weighted_pred_flag + weighted_bipred_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* transquant_bypass_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* tiles_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* entropy_coding_sync_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* deblocking_filter_control_present_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* deblocking_filter_override_enabled_flag */
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
 
    if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
-      radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
-      radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
+      radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.beta_offset_div2);
+      radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.tc_offset_div2);
    }
 
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pps_scaling_list_data_present_flag */
-   radeon_enc_code_fixed_bits(enc, pps->lists_modification_present_flag, 1);
-   radeon_enc_code_ue(enc, pps->log2_parallel_merge_level_minus2);
-   radeon_enc_code_fixed_bits(enc, 0x0, 2);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pps_scaling_list_data_present_flag */
+   radeon_bs_code_fixed_bits(&bs, pps->lists_modification_present_flag, 1);
+   radeon_bs_code_ue(&bs, pps->log2_parallel_merge_level_minus2);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 2);
 
-   radeon_enc_code_fixed_bits(enc, 0x1, 1);
-   radeon_enc_byte_align(enc);
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
+   radeon_bs_byte_align(&bs);
 
-   radeon_enc_flush_headers(enc);
-   return enc->bits_buf_pos;
+   return bs.bits_output / 8;
 }
 
 unsigned int radeon_enc_write_vps(struct radeon_encoder *enc, uint8_t *out)
 {
+   struct radeon_bitstream bs;
    struct pipe_h265_enc_vid_param *vps = &enc->enc_pic.hevc.desc->vid;
    int i;
 
-   radeon_enc_reset(enc);
-   radeon_enc_set_output_buffer(enc, out);
-   radeon_enc_set_emulation_prevention(enc, false);
-   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
-   radeon_enc_code_fixed_bits(enc, 0x4001, 16);
-   radeon_enc_byte_align(enc);
-   radeon_enc_set_emulation_prevention(enc, true);
-
-   radeon_enc_code_fixed_bits(enc, 0x0, 4); /* vps_video_parameter_set_id*/
-   radeon_enc_code_fixed_bits(enc, vps->vps_base_layer_internal_flag, 1);
-   radeon_enc_code_fixed_bits(enc, vps->vps_base_layer_available_flag, 1);
-   radeon_enc_code_fixed_bits(enc, 0x0, 6); /* vps_max_layers_minus1 */
-   radeon_enc_code_fixed_bits(enc, vps->vps_max_sub_layers_minus1, 3);
-   radeon_enc_code_fixed_bits(enc, vps->vps_temporal_id_nesting_flag, 1);
-   radeon_enc_code_fixed_bits(enc, 0xffff, 16); /* vps_reserved_0xffff_16bits */
-   radeon_enc_hevc_profile_tier_level(enc, vps->vps_max_sub_layers_minus1, &vps->profile_tier_level);
-   radeon_enc_code_fixed_bits(enc, vps->vps_sub_layer_ordering_info_present_flag, 1);
+   radeon_bs_reset(&bs, out, NULL);
+   radeon_bs_set_emulation_prevention(&bs, false);
+   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
+   radeon_bs_code_fixed_bits(&bs, 0x4001, 16);
+   radeon_bs_set_emulation_prevention(&bs, true);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 4); /* vps_video_parameter_set_id*/
+   radeon_bs_code_fixed_bits(&bs, vps->vps_base_layer_internal_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, vps->vps_base_layer_available_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 6); /* vps_max_layers_minus1 */
+   radeon_bs_code_fixed_bits(&bs, vps->vps_max_sub_layers_minus1, 3);
+   radeon_bs_code_fixed_bits(&bs, vps->vps_temporal_id_nesting_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, 0xffff, 16); /* vps_reserved_0xffff_16bits */
+   radeon_bs_hevc_profile_tier_level(&bs, vps->vps_max_sub_layers_minus1, &vps->profile_tier_level);
+   radeon_bs_code_fixed_bits(&bs, vps->vps_sub_layer_ordering_info_present_flag, 1);
    i = vps->vps_sub_layer_ordering_info_present_flag ? 0 : vps->vps_max_sub_layers_minus1;
    for (; i <= vps->vps_max_sub_layers_minus1; i++) {
-      radeon_enc_code_ue(enc, vps->vps_max_dec_pic_buffering_minus1[i]);
-      radeon_enc_code_ue(enc, vps->vps_max_num_reorder_pics[i]);
-      radeon_enc_code_ue(enc, vps->vps_max_latency_increase_plus1[i]);
+      radeon_bs_code_ue(&bs, vps->vps_max_dec_pic_buffering_minus1[i]);
+      radeon_bs_code_ue(&bs, vps->vps_max_num_reorder_pics[i]);
+      radeon_bs_code_ue(&bs, vps->vps_max_latency_increase_plus1[i]);
    }
-   radeon_enc_code_fixed_bits(enc, 0x0, 6); /* vps_max_layer_id */
-   radeon_enc_code_ue(enc, 0x0); /* vps_num_layer_sets_minus1 */
-   radeon_enc_code_fixed_bits(enc, vps->vps_timing_info_present_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 6); /* vps_max_layer_id */
+   radeon_bs_code_ue(&bs, 0x0); /* vps_num_layer_sets_minus1 */
+   radeon_bs_code_fixed_bits(&bs, vps->vps_timing_info_present_flag, 1);
    if (vps->vps_timing_info_present_flag) {
-      radeon_enc_code_fixed_bits(enc, vps->vps_num_units_in_tick, 32);
-      radeon_enc_code_fixed_bits(enc, vps->vps_time_scale, 32);
-      radeon_enc_code_fixed_bits(enc, vps->vps_poc_proportional_to_timing_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, vps->vps_num_units_in_tick, 32);
+      radeon_bs_code_fixed_bits(&bs, vps->vps_time_scale, 32);
+      radeon_bs_code_fixed_bits(&bs, vps->vps_poc_proportional_to_timing_flag, 1);
       if (vps->vps_poc_proportional_to_timing_flag)
-         radeon_enc_code_ue(enc, vps->vps_num_ticks_poc_diff_one_minus1);
-      radeon_enc_code_ue(enc, 0x0); /* vps_num_hrd_parameters */
+         radeon_bs_code_ue(&bs, vps->vps_num_ticks_poc_diff_one_minus1);
+      radeon_bs_code_ue(&bs, 0x0); /* vps_num_hrd_parameters */
    }
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* vps_extension_flag */
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* vps_extension_flag */
 
-   radeon_enc_code_fixed_bits(enc, 0x1, 1);
-   radeon_enc_byte_align(enc);
+   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
+   radeon_bs_byte_align(&bs);
 
-   radeon_enc_flush_headers(enc);
-   return enc->bits_buf_pos;
+   return bs.bits_output / 8;
 }
 
 static void radeon_enc_slice_header(struct radeon_encoder *enc)
 {
+   struct radeon_bitstream bs;
    struct pipe_h264_enc_seq_param *sps = &enc->enc_pic.h264.desc->seq;
    struct pipe_h264_enc_pic_control *pps = &enc->enc_pic.h264.desc->pic_ctrl;
    struct pipe_h264_enc_slice_param *slice = &enc->enc_pic.h264.desc->slice;
@@ -577,19 +567,20 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
    unsigned int cdw_start = 0;
    unsigned int cdw_filled = 0;
    unsigned int bits_copied = 0;
+
    RADEON_ENC_BEGIN(enc->cmd.slice_header);
-   radeon_enc_reset(enc);
-   radeon_enc_set_emulation_prevention(enc, false);
+   radeon_bs_reset(&bs, NULL, &enc->cs);
+   radeon_bs_set_emulation_prevention(&bs, false);
 
    cdw_start = enc->cs.current.cdw;
-   radeon_enc_code_fixed_bits(enc, 0x0, 1); /* forbidden_zero_bit */
-   radeon_enc_code_fixed_bits(enc, pps->nal_ref_idc, 2);
-   radeon_enc_code_fixed_bits(enc, pps->nal_unit_type, 5);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* forbidden_zero_bit */
+   radeon_bs_code_fixed_bits(&bs, pps->nal_ref_idc, 2);
+   radeon_bs_code_fixed_bits(&bs, pps->nal_unit_type, 5);
 
-   radeon_enc_flush_headers(enc);
+   radeon_bs_flush_headers(&bs);
    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-   num_bits[inst_index] = enc->bits_output - bits_copied;
-   bits_copied = enc->bits_output;
+   num_bits[inst_index] = bs.bits_output - bits_copied;
+   bits_copied = bs.bits_output;
    inst_index++;
 
    instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
@@ -598,26 +589,26 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
    switch (enc->enc_pic.picture_type) {
    case PIPE_H2645_ENC_PICTURE_TYPE_I:
    case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
-      radeon_enc_code_fixed_bits(enc, 0x08, 7);
+      radeon_bs_code_fixed_bits(&bs, 0x08, 7);
       break;
    case PIPE_H2645_ENC_PICTURE_TYPE_P:
    case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
-      radeon_enc_code_fixed_bits(enc, 0x06, 5);
+      radeon_bs_code_fixed_bits(&bs, 0x06, 5);
       break;
    case PIPE_H2645_ENC_PICTURE_TYPE_B:
-      radeon_enc_code_fixed_bits(enc, 0x07, 5);
+      radeon_bs_code_fixed_bits(&bs, 0x07, 5);
       break;
    default:
-      radeon_enc_code_fixed_bits(enc, 0x08, 7);
+      radeon_bs_code_fixed_bits(&bs, 0x08, 7);
    }
 
-   radeon_enc_code_ue(enc, 0x0); /* pic_parameter_set_id */
-   radeon_enc_code_fixed_bits(enc, slice->frame_num, sps->log2_max_frame_num_minus4 + 4);
+   radeon_bs_code_ue(&bs, 0x0); /* pic_parameter_set_id */
+   radeon_bs_code_fixed_bits(&bs, slice->frame_num, sps->log2_max_frame_num_minus4 + 4);
 
    if (enc->enc_pic.h264_enc_params.input_picture_structure !=
        RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
-      radeon_enc_code_fixed_bits(enc, 0x1, 1);
-      radeon_enc_code_fixed_bits(enc,
+      radeon_bs_code_fixed_bits(&bs, 0x1, 1);
+      radeon_bs_code_fixed_bits(&bs,
                                  enc->enc_pic.h264_enc_params.input_picture_structure ==
                                        RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
                                     ? 1
@@ -626,80 +617,80 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
    }
 
    if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
-      radeon_enc_code_ue(enc, slice->idr_pic_id);
+      radeon_bs_code_ue(&bs, slice->idr_pic_id);
 
    if (sps->pic_order_cnt_type == 0)
-      radeon_enc_code_fixed_bits(enc, slice->pic_order_cnt_lsb, sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
+      radeon_bs_code_fixed_bits(&bs, slice->pic_order_cnt_lsb, sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
 
    if (pps->redundant_pic_cnt_present_flag)
-      radeon_enc_code_ue(enc, slice->redundant_pic_cnt);
+      radeon_bs_code_ue(&bs, slice->redundant_pic_cnt);
 
    if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
-      radeon_enc_code_fixed_bits(enc, 0x1, 1); /* direct_spatial_mv_pred_flag */
+      radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* direct_spatial_mv_pred_flag */
 
    if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P ||
        enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
-      radeon_enc_code_fixed_bits(enc, slice->num_ref_idx_active_override_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, slice->num_ref_idx_active_override_flag, 1);
       if (slice->num_ref_idx_active_override_flag) {
-         radeon_enc_code_ue(enc, slice->num_ref_idx_l0_active_minus1);
+         radeon_bs_code_ue(&bs, slice->num_ref_idx_l0_active_minus1);
          if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
-            radeon_enc_code_ue(enc, slice->num_ref_idx_l1_active_minus1);
+            radeon_bs_code_ue(&bs, slice->num_ref_idx_l1_active_minus1);
       }
-      radeon_enc_code_fixed_bits(enc, slice->ref_pic_list_modification_flag_l0, 1);
+      radeon_bs_code_fixed_bits(&bs, slice->ref_pic_list_modification_flag_l0, 1);
       if (slice->ref_pic_list_modification_flag_l0) {
          for (unsigned i = 0; i < slice->num_ref_list0_mod_operations; i++) {
             struct pipe_h264_ref_list_mod_entry *op =
                &slice->ref_list0_mod_operations[i];
-            radeon_enc_code_ue(enc, op->modification_of_pic_nums_idc);
+            radeon_bs_code_ue(&bs, op->modification_of_pic_nums_idc);
             if (op->modification_of_pic_nums_idc == 0 ||
                 op->modification_of_pic_nums_idc == 1)
-               radeon_enc_code_ue(enc, op->abs_diff_pic_num_minus1);
+               radeon_bs_code_ue(&bs, op->abs_diff_pic_num_minus1);
             else if (op->modification_of_pic_nums_idc == 2)
-               radeon_enc_code_ue(enc, op->long_term_pic_num);
+               radeon_bs_code_ue(&bs, op->long_term_pic_num);
          }
-         radeon_enc_code_ue(enc, 0x3); /* modification_of_pic_nums_idc */
+         radeon_bs_code_ue(&bs, 0x3); /* modification_of_pic_nums_idc */
       }
       if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
-         radeon_enc_code_fixed_bits(enc, slice->ref_pic_list_modification_flag_l1, 1);
+         radeon_bs_code_fixed_bits(&bs, slice->ref_pic_list_modification_flag_l1, 1);
          if (slice->ref_pic_list_modification_flag_l1) {
             for (unsigned i = 0; i < slice->num_ref_list1_mod_operations; i++) {
                struct pipe_h264_ref_list_mod_entry *op =
                   &slice->ref_list1_mod_operations[i];
-               radeon_enc_code_ue(enc, op->modification_of_pic_nums_idc);
+               radeon_bs_code_ue(&bs, op->modification_of_pic_nums_idc);
                if (op->modification_of_pic_nums_idc == 0 ||
                    op->modification_of_pic_nums_idc == 1)
-                  radeon_enc_code_ue(enc, op->abs_diff_pic_num_minus1);
+                  radeon_bs_code_ue(&bs, op->abs_diff_pic_num_minus1);
                else if (op->modification_of_pic_nums_idc == 2)
-                  radeon_enc_code_ue(enc, op->long_term_pic_num);
+                  radeon_bs_code_ue(&bs, op->long_term_pic_num);
             }
-            radeon_enc_code_ue(enc, 0x3); /* modification_of_pic_nums_idc */
+            radeon_bs_code_ue(&bs, 0x3); /* modification_of_pic_nums_idc */
          }
       }
    }
 
    if (!enc->enc_pic.not_referenced) {
       if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) {
-         radeon_enc_code_fixed_bits(enc, slice->no_output_of_prior_pics_flag, 1);
-         radeon_enc_code_fixed_bits(enc, slice->long_term_reference_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, slice->no_output_of_prior_pics_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, slice->long_term_reference_flag, 1);
       } else {
-         radeon_enc_code_fixed_bits(enc, slice->adaptive_ref_pic_marking_mode_flag, 1);
+         radeon_bs_code_fixed_bits(&bs, slice->adaptive_ref_pic_marking_mode_flag, 1);
          if (slice->adaptive_ref_pic_marking_mode_flag) {
             for (unsigned i = 0; i < slice->num_ref_pic_marking_operations; i++) {
                struct pipe_h264_ref_pic_marking_entry *op =
                   &slice->ref_pic_marking_operations[i];
-               radeon_enc_code_ue(enc, op->memory_management_control_operation);
+               radeon_bs_code_ue(&bs, op->memory_management_control_operation);
                if (op->memory_management_control_operation == 1 ||
                    op->memory_management_control_operation == 3)
-                  radeon_enc_code_ue(enc, op->difference_of_pic_nums_minus1);
+                  radeon_bs_code_ue(&bs, op->difference_of_pic_nums_minus1);
                if (op->memory_management_control_operation == 2)
-                  radeon_enc_code_ue(enc, op->long_term_pic_num);
+                  radeon_bs_code_ue(&bs, op->long_term_pic_num);
                if (op->memory_management_control_operation == 3 ||
                    op->memory_management_control_operation == 6)
-                  radeon_enc_code_ue(enc, op->long_term_frame_idx);
+                  radeon_bs_code_ue(&bs, op->long_term_frame_idx);
                if (op->memory_management_control_operation == 4)
-                  radeon_enc_code_ue(enc, op->max_long_term_frame_idx_plus1);
+                  radeon_bs_code_ue(&bs, op->max_long_term_frame_idx_plus1);
             }
-            radeon_enc_code_ue(enc, 0); /* memory_management_control_operation */
+            radeon_bs_code_ue(&bs, 0); /* memory_management_control_operation */
          }
       }
    }
@@ -707,29 +698,29 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
    if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) &&
        (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) &&
        (enc->enc_pic.spec_misc.cabac_enable))
-      radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
+      radeon_bs_code_ue(&bs, enc->enc_pic.spec_misc.cabac_init_idc);
 
-   radeon_enc_flush_headers(enc);
+   radeon_bs_flush_headers(&bs);
    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-   num_bits[inst_index] = enc->bits_output - bits_copied;
-   bits_copied = enc->bits_output;
+   num_bits[inst_index] = bs.bits_output - bits_copied;
+   bits_copied = bs.bits_output;
    inst_index++;
 
    instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
    inst_index++;
 
    if (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag) {
-      radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
+      radeon_bs_code_ue(&bs, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
       if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
-         radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
-         radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
+         radeon_bs_code_se(&bs, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
+         radeon_bs_code_se(&bs, enc->enc_pic.h264_deblock.beta_offset_div2);
       }
    }
 
-   radeon_enc_flush_headers(enc);
+   radeon_bs_flush_headers(&bs);
    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-   num_bits[inst_index] = enc->bits_output - bits_copied;
-   bits_copied = enc->bits_output;
+   num_bits[inst_index] = bs.bits_output - bits_copied;
+   bits_copied = bs.bits_output;
    inst_index++;
 
    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
@@ -748,6 +739,7 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
 
 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
 {
+   struct radeon_bitstream bs;
    struct pipe_h265_enc_seq_param *sps = &enc->enc_pic.hevc.desc->seq;
    struct pipe_h265_enc_pic_param *pps = &enc->enc_pic.hevc.desc->pic;
    struct pipe_h265_enc_slice_param *slice = &enc->enc_pic.hevc.desc->slice;
@@ -758,34 +750,35 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
    unsigned int cdw_filled = 0;
    unsigned int bits_copied = 0;
    unsigned int num_pic_total_curr = 0;
+
    RADEON_ENC_BEGIN(enc->cmd.slice_header);
-   radeon_enc_reset(enc);
-   radeon_enc_set_emulation_prevention(enc, false);
+   radeon_bs_reset(&bs, NULL, &enc->cs);
+   radeon_bs_set_emulation_prevention(&bs, false);
 
    cdw_start = enc->cs.current.cdw;
-   radeon_enc_code_fixed_bits(enc, 0x0, 1);
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
-   radeon_enc_code_fixed_bits(enc, 0x0, 6);
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.temporal_id + 1, 3);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 1);
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.nal_unit_type, 6);
+   radeon_bs_code_fixed_bits(&bs, 0x0, 6);
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.temporal_id + 1, 3);
 
-   radeon_enc_flush_headers(enc);
+   radeon_bs_flush_headers(&bs);
    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-   num_bits[inst_index] = enc->bits_output - bits_copied;
-   bits_copied = enc->bits_output;
+   num_bits[inst_index] = bs.bits_output - bits_copied;
+   bits_copied = bs.bits_output;
    inst_index++;
 
    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
    inst_index++;
 
    if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
-      radeon_enc_code_fixed_bits(enc, slice->no_output_of_prior_pics_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, slice->no_output_of_prior_pics_flag, 1);
 
-   radeon_enc_code_ue(enc, 0x0); /* slice_pic_parameter_set_id */
+   radeon_bs_code_ue(&bs, 0x0); /* slice_pic_parameter_set_id */
 
-   radeon_enc_flush_headers(enc);
+   radeon_bs_flush_headers(&bs);
    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-   num_bits[inst_index] = enc->bits_output - bits_copied;
-   bits_copied = enc->bits_output;
+   num_bits[inst_index] = bs.bits_output - bits_copied;
+   bits_copied = bs.bits_output;
    inst_index++;
 
    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
@@ -797,59 +790,59 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
    switch (enc->enc_pic.picture_type) {
    case PIPE_H2645_ENC_PICTURE_TYPE_I:
    case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
-      radeon_enc_code_ue(enc, 0x2);
+      radeon_bs_code_ue(&bs, 0x2);
       break;
    case PIPE_H2645_ENC_PICTURE_TYPE_P:
    case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
-      radeon_enc_code_ue(enc, 0x1);
+      radeon_bs_code_ue(&bs, 0x1);
       break;
    case PIPE_H2645_ENC_PICTURE_TYPE_B:
-      radeon_enc_code_ue(enc, 0x0);
+      radeon_bs_code_ue(&bs, 0x0);
       break;
    default:
-      radeon_enc_code_ue(enc, 0x1);
+      radeon_bs_code_ue(&bs, 0x1);
    }
 
    if (pps->output_flag_present_flag)
-      radeon_enc_code_fixed_bits(enc, slice->pic_output_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, slice->pic_output_flag, 1);
 
    if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
-      radeon_enc_code_fixed_bits(enc, slice->slice_pic_order_cnt_lsb, sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
-      radeon_enc_code_fixed_bits(enc, slice->short_term_ref_pic_set_sps_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, slice->slice_pic_order_cnt_lsb, sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
+      radeon_bs_code_fixed_bits(&bs, slice->short_term_ref_pic_set_sps_flag, 1);
       if (!slice->short_term_ref_pic_set_sps_flag) {
          num_pic_total_curr =
-            radeon_enc_hevc_st_ref_pic_set(enc, sps->num_short_term_ref_pic_sets,
-                                           sps->num_short_term_ref_pic_sets, sps->st_ref_pic_set);
+            radeon_bs_hevc_st_ref_pic_set(&bs, sps->num_short_term_ref_pic_sets,
+                                          sps->num_short_term_ref_pic_sets, sps->st_ref_pic_set);
       } else if (sps->num_short_term_ref_pic_sets > 1) {
-         radeon_enc_code_fixed_bits(enc, slice->short_term_ref_pic_set_idx,
+         radeon_bs_code_fixed_bits(&bs, slice->short_term_ref_pic_set_idx,
                                     util_logbase2_ceil(sps->num_short_term_ref_pic_sets));
       }
       if (sps->long_term_ref_pics_present_flag) {
          if (sps->num_long_term_ref_pics_sps > 0)
-            radeon_enc_code_ue(enc, slice->num_long_term_sps);
-         radeon_enc_code_ue(enc, slice->num_long_term_pics);
+            radeon_bs_code_ue(&bs, slice->num_long_term_sps);
+         radeon_bs_code_ue(&bs, slice->num_long_term_pics);
          for (unsigned i = 0; i < slice->num_long_term_sps + slice->num_long_term_pics; i++) {
             if (i < slice->num_long_term_sps) {
                if (sps->num_long_term_ref_pics_sps > 1)
-                  radeon_enc_code_fixed_bits(enc, slice->lt_idx_sps[i], util_logbase2_ceil(sps->num_long_term_ref_pics_sps));
+                  radeon_bs_code_fixed_bits(&bs, slice->lt_idx_sps[i], util_logbase2_ceil(sps->num_long_term_ref_pics_sps));
             } else {
-               radeon_enc_code_fixed_bits(enc, slice->poc_lsb_lt[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
-               radeon_enc_code_fixed_bits(enc, slice->used_by_curr_pic_lt_flag[i], 1);
+               radeon_bs_code_fixed_bits(&bs, slice->poc_lsb_lt[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
+               radeon_bs_code_fixed_bits(&bs, slice->used_by_curr_pic_lt_flag[i], 1);
                if (slice->used_by_curr_pic_lt_flag[i])
                   num_pic_total_curr++;
             }
-            radeon_enc_code_fixed_bits(enc, slice->delta_poc_msb_present_flag[i], 1);
+            radeon_bs_code_fixed_bits(&bs, slice->delta_poc_msb_present_flag[i], 1);
             if (slice->delta_poc_msb_present_flag[i])
-               radeon_enc_code_ue(enc, slice->delta_poc_msb_cycle_lt[i]);
+               radeon_bs_code_ue(&bs, slice->delta_poc_msb_cycle_lt[i]);
          }
       }
    }
 
    if (!enc->enc_pic.hevc_deblock.disable_sao) {
-      radeon_enc_flush_headers(enc);
+      radeon_bs_flush_headers(&bs);
       instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-      num_bits[inst_index] = enc->bits_output - bits_copied;
-      bits_copied = enc->bits_output;
+      num_bits[inst_index] = bs.bits_output - bits_copied;
+      bits_copied = bs.bits_output;
       inst_index++;
 
       instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
@@ -858,37 +851,37 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
 
    if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
        (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
-      radeon_enc_code_fixed_bits(enc, slice->num_ref_idx_active_override_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, slice->num_ref_idx_active_override_flag, 1);
       if (slice->num_ref_idx_active_override_flag) {
-         radeon_enc_code_ue(enc, slice->num_ref_idx_l0_active_minus1);
+         radeon_bs_code_ue(&bs, slice->num_ref_idx_l0_active_minus1);
          if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
-            radeon_enc_code_ue(enc, slice->num_ref_idx_l1_active_minus1);
+            radeon_bs_code_ue(&bs, slice->num_ref_idx_l1_active_minus1);
       }
       if (pps->lists_modification_present_flag && num_pic_total_curr > 1) {
          unsigned num_bits = util_logbase2_ceil(num_pic_total_curr);
          unsigned num_ref_l0_minus1 = slice->num_ref_idx_active_override_flag ?
             slice->num_ref_idx_l0_active_minus1 : pps->num_ref_idx_l0_default_active_minus1;
-         radeon_enc_code_fixed_bits(enc, slice->ref_pic_lists_modification.ref_pic_list_modification_flag_l0, 1);
+         radeon_bs_code_fixed_bits(&bs, slice->ref_pic_lists_modification.ref_pic_list_modification_flag_l0, 1);
          for (unsigned i = 0; i <= num_ref_l0_minus1; i++)
-            radeon_enc_code_fixed_bits(enc, slice->ref_pic_lists_modification.list_entry_l0[i], num_bits);
+            radeon_bs_code_fixed_bits(&bs, slice->ref_pic_lists_modification.list_entry_l0[i], num_bits);
          if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
             unsigned num_ref_l1_minus1 = slice->num_ref_idx_active_override_flag ?
                slice->num_ref_idx_l1_active_minus1 : pps->num_ref_idx_l1_default_active_minus1;
-            radeon_enc_code_fixed_bits(enc, slice->ref_pic_lists_modification.ref_pic_list_modification_flag_l1, 1);
+            radeon_bs_code_fixed_bits(&bs, slice->ref_pic_lists_modification.ref_pic_list_modification_flag_l1, 1);
             for (unsigned i = 0; i <= num_ref_l1_minus1; i++)
-               radeon_enc_code_fixed_bits(enc, slice->ref_pic_lists_modification.list_entry_l1[i], num_bits);
+               radeon_bs_code_fixed_bits(&bs, slice->ref_pic_lists_modification.list_entry_l1[i], num_bits);
          }
       }
       if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
-         radeon_enc_code_fixed_bits(enc, 0x0, 1); /* mvd_l1_zero_flag */
-      radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
-      radeon_enc_code_ue(enc, 5 - slice->max_num_merge_cand);
+         radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* mvd_l1_zero_flag */
+      radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
+      radeon_bs_code_ue(&bs, 5 - slice->max_num_merge_cand);
    }
 
-   radeon_enc_flush_headers(enc);
+   radeon_bs_flush_headers(&bs);
    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-   num_bits[inst_index] = enc->bits_output - bits_copied;
-   bits_copied = enc->bits_output;
+   num_bits[inst_index] = bs.bits_output - bits_copied;
+   bits_copied = bs.bits_output;
    inst_index++;
 
    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
@@ -898,20 +891,20 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
        (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
         !enc->enc_pic.hevc_deblock.disable_sao)) {
        if (!enc->enc_pic.hevc_deblock.disable_sao) {
-           radeon_enc_flush_headers(enc);
+           radeon_bs_flush_headers(&bs);
            instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-           num_bits[inst_index] = enc->bits_output - bits_copied;
-           bits_copied = enc->bits_output;
+           num_bits[inst_index] = bs.bits_output - bits_copied;
+           bits_copied = bs.bits_output;
            inst_index++;
 
            instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
            inst_index++;
        } else {
-           radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
-           radeon_enc_flush_headers(enc);
+           radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
+           radeon_bs_flush_headers(&bs);
            instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
-           num_bits[inst_index] = enc->bits_output - bits_copied;
-           bits_copied = enc->bits_output;
+           num_bits[inst_index] = bs.bits_output - bits_copied;
+           bits_copied = bs.bits_output;
            inst_index++;
        }
    }
@@ -930,180 +923,6 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
    RADEON_ENC_END();
 }
 
-void radeon_enc_hrd_parameters(struct radeon_encoder *enc,
-                               struct pipe_h264_enc_hrd_params *hrd)
-{
-   radeon_enc_code_ue(enc, hrd->cpb_cnt_minus1);
-   radeon_enc_code_fixed_bits(enc, hrd->bit_rate_scale, 4);
-   radeon_enc_code_fixed_bits(enc, hrd->cpb_size_scale, 4);
-   for (unsigned i = 0; i <= hrd->cpb_cnt_minus1; i++) {
-      radeon_enc_code_ue(enc, hrd->bit_rate_value_minus1[i]);
-      radeon_enc_code_ue(enc, hrd->cpb_size_value_minus1[i]);
-      radeon_enc_code_fixed_bits(enc, hrd->cbr_flag[i], 1);
-   }
-   radeon_enc_code_fixed_bits(enc, hrd->initial_cpb_removal_delay_length_minus1, 5);
-   radeon_enc_code_fixed_bits(enc, hrd->cpb_removal_delay_length_minus1, 5);
-   radeon_enc_code_fixed_bits(enc, hrd->dpb_output_delay_length_minus1, 5);
-   radeon_enc_code_fixed_bits(enc, hrd->time_offset_length, 5);
-}
-
-static void radeon_enc_hevc_profile_tier(struct radeon_encoder *enc,
-                                         struct pipe_h265_profile_tier *pt)
-{
-   radeon_enc_code_fixed_bits(enc, pt->general_profile_space, 2);
-   radeon_enc_code_fixed_bits(enc, pt->general_tier_flag, 1);
-   radeon_enc_code_fixed_bits(enc, pt->general_profile_idc, 5);
-   radeon_enc_code_fixed_bits(enc, pt->general_profile_compatibility_flag, 32);
-   radeon_enc_code_fixed_bits(enc, pt->general_progressive_source_flag, 1);
-   radeon_enc_code_fixed_bits(enc, pt->general_interlaced_source_flag, 1);
-   radeon_enc_code_fixed_bits(enc, pt->general_non_packed_constraint_flag, 1);
-   radeon_enc_code_fixed_bits(enc, pt->general_frame_only_constraint_flag, 1);
-   /* general_reserved_zero_44bits */
-   radeon_enc_code_fixed_bits(enc, 0x0, 16);
-   radeon_enc_code_fixed_bits(enc, 0x0, 16);
-   radeon_enc_code_fixed_bits(enc, 0x0, 12);
-}
-
-void radeon_enc_hevc_profile_tier_level(struct radeon_encoder *enc,
-                                        unsigned int max_num_sub_layers_minus1,
-                                        struct pipe_h265_profile_tier_level *ptl)
-{
-   unsigned i;
-
-   radeon_enc_hevc_profile_tier(enc, &ptl->profile_tier);
-   radeon_enc_code_fixed_bits(enc, ptl->general_level_idc, 8);
-
-   for (i = 0; i < max_num_sub_layers_minus1; ++i) {
-      radeon_enc_code_fixed_bits(enc, ptl->sub_layer_profile_present_flag[i], 1);
-      radeon_enc_code_fixed_bits(enc, ptl->sub_layer_level_present_flag[i], 1);
-   }
-
-   if (max_num_sub_layers_minus1 > 0) {
-      for (i = max_num_sub_layers_minus1; i < 8; ++i)
-         radeon_enc_code_fixed_bits(enc, 0x0, 2); /* reserved_zero_2bits */
-   }
-
-   for (i = 0; i < max_num_sub_layers_minus1; ++i) {
-      if (ptl->sub_layer_profile_present_flag[i])
-         radeon_enc_hevc_profile_tier(enc, &ptl->sub_layer_profile_tier[i]);
-
-      if (ptl->sub_layer_level_present_flag[i])
-         radeon_enc_code_fixed_bits(enc, ptl->sub_layer_level_idc[i], 8);
-   }
-}
-
-static void radeon_enc_hevc_sub_layer_hrd_parameters(struct radeon_encoder *enc,
-                                                     unsigned int cpb_cnt,
-                                                     unsigned int sub_pic_hrd_params_present_flag,
-                                                     struct pipe_h265_enc_sublayer_hrd_params *hrd)
-{
-   for (unsigned i = 0; i < cpb_cnt; i++) {
-      radeon_enc_code_ue(enc, hrd->bit_rate_value_minus1[i]);
-      radeon_enc_code_ue(enc, hrd->cpb_size_value_minus1[i]);
-      if (sub_pic_hrd_params_present_flag) {
-         radeon_enc_code_ue(enc, hrd->cpb_size_du_value_minus1[i]);
-         radeon_enc_code_ue(enc, hrd->bit_rate_du_value_minus1[i]);
-      }
-      radeon_enc_code_fixed_bits(enc, hrd->cbr_flag[i], 1);
-   }
-}
-
-void radeon_enc_hevc_hrd_parameters(struct radeon_encoder *enc,
-                                    unsigned int common_inf_present_flag,
-                                    unsigned int max_sub_layers_minus1,
-                                    struct pipe_h265_enc_hrd_params *hrd)
-{
-   if (common_inf_present_flag) {
-      radeon_enc_code_fixed_bits(enc, hrd->nal_hrd_parameters_present_flag, 1);
-      radeon_enc_code_fixed_bits(enc, hrd->vcl_hrd_parameters_present_flag, 1);
-      if (hrd->nal_hrd_parameters_present_flag || hrd->vcl_hrd_parameters_present_flag) {
-         radeon_enc_code_fixed_bits(enc, hrd->sub_pic_hrd_params_present_flag, 1);
-         if (hrd->sub_pic_hrd_params_present_flag) {
-            radeon_enc_code_fixed_bits(enc, hrd->tick_divisor_minus2, 8);
-            radeon_enc_code_fixed_bits(enc, hrd->du_cpb_removal_delay_increment_length_minus1, 5);
-            radeon_enc_code_fixed_bits(enc, hrd->sub_pic_hrd_params_present_flag, 1);
-            radeon_enc_code_fixed_bits(enc, hrd->dpb_output_delay_du_length_minus1, 5);
-         }
-         radeon_enc_code_fixed_bits(enc, hrd->bit_rate_scale, 4);
-         radeon_enc_code_fixed_bits(enc, hrd->cpb_rate_scale, 4);
-         if (hrd->sub_pic_hrd_params_present_flag)
-            radeon_enc_code_fixed_bits(enc, hrd->cpb_size_du_scale, 4);
-         radeon_enc_code_fixed_bits(enc, hrd->initial_cpb_removal_delay_length_minus1, 5);
-         radeon_enc_code_fixed_bits(enc, hrd->au_cpb_removal_delay_length_minus1, 5);
-         radeon_enc_code_fixed_bits(enc, hrd->dpb_output_delay_length_minus1, 5);
-      }
-   }
-
-   for (unsigned i = 0; i <= max_sub_layers_minus1; i++) {
-      radeon_enc_code_fixed_bits(enc, hrd->fixed_pic_rate_general_flag[i], 1);
-      if (!hrd->fixed_pic_rate_general_flag[i])
-         radeon_enc_code_fixed_bits(enc, hrd->fixed_pic_rate_within_cvs_flag[i], 1);
-      if (hrd->fixed_pic_rate_within_cvs_flag[i])
-         radeon_enc_code_ue(enc, hrd->elemental_duration_in_tc_minus1[i]);
-      else
-         radeon_enc_code_fixed_bits(enc, hrd->low_delay_hrd_flag[i], 1);
-      if (!hrd->low_delay_hrd_flag[i])
-         radeon_enc_code_ue(enc, hrd->cpb_cnt_minus1[i]);
-      if (hrd->nal_hrd_parameters_present_flag) {
-         radeon_enc_hevc_sub_layer_hrd_parameters(enc,
-                                                  hrd->cpb_cnt_minus1[i] + 1,
-                                                  hrd->sub_pic_hrd_params_present_flag,
-                                                  &hrd->nal_hrd_parameters[i]);
-      }
-      if (hrd->vcl_hrd_parameters_present_flag) {
-         radeon_enc_hevc_sub_layer_hrd_parameters(enc,
-                                                  hrd->cpb_cnt_minus1[i] + 1,
-                                                  hrd->sub_pic_hrd_params_present_flag,
-                                                  &hrd->vlc_hrd_parameters[i]);
-      }
-   }
-}
-
-/* returns NumPicTotalCurr */
-unsigned int radeon_enc_hevc_st_ref_pic_set(struct radeon_encoder *enc,
-                                            unsigned int index,
-                                            unsigned int num_short_term_ref_pic_sets,
-                                            struct pipe_h265_st_ref_pic_set *st_rps)
-{
-   struct pipe_h265_st_ref_pic_set *ref_rps = NULL;
-   struct pipe_h265_st_ref_pic_set *rps = &st_rps[index];
-   unsigned i, num_pic_total_curr = 0;
-
-   if (index)
-      radeon_enc_code_fixed_bits(enc, rps->inter_ref_pic_set_prediction_flag, 1);
-
-   if (rps->inter_ref_pic_set_prediction_flag) {
-      if (index == num_short_term_ref_pic_sets)
-         radeon_enc_code_ue(enc, rps->delta_idx_minus1);
-      radeon_enc_code_fixed_bits(enc, rps->delta_rps_sign, 1);
-      radeon_enc_code_ue(enc, rps->abs_delta_rps_minus1);
-      ref_rps = st_rps + index +
-         (1 - 2 * rps->delta_rps_sign) * (st_rps->delta_idx_minus1 + 1);
-      for (i = 0; i <= (ref_rps->num_negative_pics + ref_rps->num_positive_pics); i++) {
-         radeon_enc_code_fixed_bits(enc, rps->used_by_curr_pic_flag[i], 1);
-         if (!rps->used_by_curr_pic_flag[i])
-            radeon_enc_code_fixed_bits(enc, rps->use_delta_flag[i], 1);
-      }
-   } else {
-      radeon_enc_code_ue(enc, rps->num_negative_pics);
-      radeon_enc_code_ue(enc, rps->num_positive_pics);
-      for (i = 0; i < rps->num_negative_pics; i++) {
-         radeon_enc_code_ue(enc, rps->delta_poc_s0_minus1[i]);
-         radeon_enc_code_fixed_bits(enc, rps->used_by_curr_pic_s0_flag[i], 1);
-         if (rps->used_by_curr_pic_s0_flag[i])
-            num_pic_total_curr++;
-      }
-      for (i = 0; i < st_rps->num_positive_pics; i++) {
-         radeon_enc_code_ue(enc, rps->delta_poc_s1_minus1[i]);
-         radeon_enc_code_fixed_bits(enc, rps->used_by_curr_pic_s1_flag[i], 1);
-         if (rps->used_by_curr_pic_s1_flag[i])
-            num_pic_total_curr++;
-      }
-   }
-
-   return num_pic_total_curr;
-}
-
 static void radeon_enc_ctx(struct radeon_encoder *enc)
 {
    enc->enc_pic.ctx_buf.swizzle_mode = 0;
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
index 6fdd14b6a51..7f386ad036c 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
@@ -157,226 +157,226 @@ static void radeon_enc_cdf_default_table(struct radeon_encoder *enc)
    RADEON_ENC_END();
 }
 
-void radeon_enc_av1_obu_header(struct radeon_encoder *enc, uint32_t obu_type)
+void radeon_enc_av1_obu_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, uint32_t obu_type)
 {
    /* obu header () */
    /* obu_forbidden_bit */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(bs, 0, 1);
    /* obu_type */
-   radeon_enc_code_fixed_bits(enc, obu_type, 4);
+   radeon_bs_code_fixed_bits(bs, obu_type, 4);
    /* obu_extension_flag */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.desc->obu_extension_flag ? 1 : 0, 1);
+   radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.desc->obu_extension_flag ? 1 : 0, 1);
    /* obu_has_size_field */
-   radeon_enc_code_fixed_bits(enc, 1, 1);
+   radeon_bs_code_fixed_bits(bs, 1, 1);
    /* obu_reserved_1bit */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(bs, 0, 1);
 
    if (enc->enc_pic.av1.desc->obu_extension_flag) {
-      radeon_enc_code_fixed_bits(enc, enc->enc_pic.temporal_id, 3);
-      radeon_enc_code_fixed_bits(enc, 0, 2);  /* spatial_id should always be zero */
-      radeon_enc_code_fixed_bits(enc, 0, 3);  /* reserved 3 bits */
+      radeon_bs_code_fixed_bits(bs, enc->enc_pic.temporal_id, 3);
+      radeon_bs_code_fixed_bits(bs, 0, 2);  /* spatial_id should always be zero */
+      radeon_bs_code_fixed_bits(bs, 0, 3);  /* reserved 3 bits */
    }
 }
 
 unsigned int radeon_enc_write_sequence_header(struct radeon_encoder *enc, uint8_t *obu_bytes, uint8_t *out)
 {
+   struct radeon_bitstream bs;
    uint8_t *size_offset;
    uint32_t obu_size;
    uint32_t width_bits;
    uint32_t height_bits;
    struct pipe_av1_enc_seq_param *seq = &enc->enc_pic.av1.desc->seq;
 
-   radeon_enc_reset(enc);
-   radeon_enc_set_output_buffer(enc, out);
-   radeon_enc_code_fixed_bits(enc, obu_bytes[0], 8);
+   radeon_bs_reset(&bs, out, NULL);
+   radeon_bs_code_fixed_bits(&bs, obu_bytes[0], 8);
    if (obu_bytes[0] & 0x4) /* obu_extension_flag */
-      radeon_enc_code_fixed_bits(enc, obu_bytes[1], 8);
+      radeon_bs_code_fixed_bits(&bs, obu_bytes[1], 8);
 
    /* obu_size, use one byte for header, the size will be written in afterwards */
-   size_offset = &enc->bits_buf[enc->bits_buf_pos];
-   radeon_enc_code_fixed_bits(enc, 0, 8);
+   size_offset = &out[bs.bits_output / 8];
+   radeon_bs_code_fixed_bits(&bs, 0, 8);
 
    /* sequence_header_obu() */
    /*  seq_profile  */
-   radeon_enc_code_fixed_bits(enc, seq->profile, 3);
+   radeon_bs_code_fixed_bits(&bs, seq->profile, 3);
    /*  still_picture */
-   radeon_enc_code_fixed_bits(enc, seq->seq_bits.still_picture, 1);
+   radeon_bs_code_fixed_bits(&bs, seq->seq_bits.still_picture, 1);
    /*  reduced_still_picture_header */
-   radeon_enc_code_fixed_bits(enc, seq->seq_bits.reduced_still_picture_header, 1);
+   radeon_bs_code_fixed_bits(&bs, seq->seq_bits.reduced_still_picture_header, 1);
 
    if (seq->seq_bits.reduced_still_picture_header) {
       /*  seq_level_idx[0]  */
-      radeon_enc_code_fixed_bits(enc, seq->seq_level_idx[0], 5);
+      radeon_bs_code_fixed_bits(&bs, seq->seq_level_idx[0], 5);
    } else {
       /*  timing_info_present_flag  */
-      radeon_enc_code_fixed_bits(enc, seq->seq_bits.timing_info_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, seq->seq_bits.timing_info_present_flag, 1);
 
       if (seq->seq_bits.timing_info_present_flag) {
          /*  num_units_in_display_tick  */
-         radeon_enc_code_fixed_bits(enc, seq->num_units_in_display_tick, 32);
+         radeon_bs_code_fixed_bits(&bs, seq->num_units_in_display_tick, 32);
          /*  time_scale  */
-         radeon_enc_code_fixed_bits(enc, seq->time_scale, 32);
+         radeon_bs_code_fixed_bits(&bs, seq->time_scale, 32);
          /*  equal_picture_interval  */
-         radeon_enc_code_fixed_bits(enc, seq->seq_bits.equal_picture_interval, 1);
+         radeon_bs_code_fixed_bits(&bs, seq->seq_bits.equal_picture_interval, 1);
          /*  num_ticks_per_picture_minus_1  */
           if (seq->seq_bits.equal_picture_interval)
-              radeon_enc_code_uvlc(enc, seq->num_tick_per_picture_minus1);
+              radeon_bs_code_uvlc(&bs, seq->num_tick_per_picture_minus1);
           /*  decoder_model_info_present_flag  */
-          radeon_enc_code_fixed_bits(enc, seq->seq_bits.decoder_model_info_present_flag, 1);
+          radeon_bs_code_fixed_bits(&bs, seq->seq_bits.decoder_model_info_present_flag, 1);
           if (seq->seq_bits.decoder_model_info_present_flag) {
              /*  buffer_delay_length_minus1  */
-             radeon_enc_code_fixed_bits(enc, seq->decoder_model_info.buffer_delay_length_minus1, 5);
+             radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.buffer_delay_length_minus1, 5);
              /*  num_units_in_decoding_tick  */
-             radeon_enc_code_fixed_bits(enc, seq->decoder_model_info.num_units_in_decoding_tick, 32);
+             radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.num_units_in_decoding_tick, 32);
              /*  buffer_removal_time_length_minus1  */
-             radeon_enc_code_fixed_bits(enc, seq->decoder_model_info.buffer_removal_time_length_minus1, 5);
+             radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.buffer_removal_time_length_minus1, 5);
              /*  frame_presentation_time_length_minus1  */
-             radeon_enc_code_fixed_bits(enc, seq->decoder_model_info.frame_presentation_time_length_minus1, 5);
+             radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.frame_presentation_time_length_minus1, 5);
           }
       }
 
       /*  initial_display_delay_present_flag  */
-      radeon_enc_code_fixed_bits(enc, seq->seq_bits.initial_display_delay_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, seq->seq_bits.initial_display_delay_present_flag, 1);
       /*  operating_points_cnt_minus_1  */
-      radeon_enc_code_fixed_bits(enc, seq->num_temporal_layers - 1, 5);
+      radeon_bs_code_fixed_bits(&bs, seq->num_temporal_layers - 1, 5);
 
       for (uint32_t i = 0; i < seq->num_temporal_layers; i++) {
          /*  operating_point_idc[i]  */
-         radeon_enc_code_fixed_bits(enc, seq->operating_point_idc[i], 12);
+         radeon_bs_code_fixed_bits(&bs, seq->operating_point_idc[i], 12);
          /*  seq_level_idx[i]  */
-         radeon_enc_code_fixed_bits(enc, seq->seq_level_idx[i], 5);
+         radeon_bs_code_fixed_bits(&bs, seq->seq_level_idx[i], 5);
          if (seq->seq_level_idx[i] > 7)
             /*  seq_tier[i]  */
-            radeon_enc_code_fixed_bits(enc, seq->seq_tier[i], 1);
+            radeon_bs_code_fixed_bits(&bs, seq->seq_tier[i], 1);
          if (seq->seq_bits.decoder_model_info_present_flag) {
             /*  decoder_model_present_for_this_op[i]  */
-            radeon_enc_code_fixed_bits(enc, seq->decoder_model_present_for_this_op[i], 1);
+            radeon_bs_code_fixed_bits(&bs, seq->decoder_model_present_for_this_op[i], 1);
             if (seq->decoder_model_present_for_this_op[i]) {
                uint32_t length = seq->decoder_model_info.buffer_delay_length_minus1 + 1;
                /*  decoder_buffer_delay[i]  */
-               radeon_enc_code_fixed_bits(enc, seq->decoder_buffer_delay[i], length);
+               radeon_bs_code_fixed_bits(&bs, seq->decoder_buffer_delay[i], length);
                /*  encoder_buffer_delay[i]  */
-               radeon_enc_code_fixed_bits(enc, seq->encoder_buffer_delay[i], length);
+               radeon_bs_code_fixed_bits(&bs, seq->encoder_buffer_delay[i], length);
                /*  low_delay_mode_flag[i]  */
-               radeon_enc_code_fixed_bits(enc, seq->low_delay_mode_flag[i], 1);
+               radeon_bs_code_fixed_bits(&bs, seq->low_delay_mode_flag[i], 1);
             }
          }
          if (seq->seq_bits.initial_display_delay_present_flag) {
             /*  initial_display_delay_present_for_this_op[i]  */
-            radeon_enc_code_fixed_bits(enc, seq->initial_display_delay_present_for_this_op[i], 1);
+            radeon_bs_code_fixed_bits(&bs, seq->initial_display_delay_present_for_this_op[i], 1);
             if (seq->initial_display_delay_present_for_this_op[i])
                /*  initial_display_delay_minus_1[i]  */
-               radeon_enc_code_fixed_bits(enc, seq->initial_display_delay_minus_1[i], 4);
+               radeon_bs_code_fixed_bits(&bs, seq->initial_display_delay_minus_1[i], 4);
          }
       }
    }
 
    /*  frame_width_bits_minus_1  */
    width_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_width);
-   radeon_enc_code_fixed_bits(enc, width_bits - 1, 4);
+   radeon_bs_code_fixed_bits(&bs, width_bits - 1, 4);
    /*  frame_height_bits_minus_1  */
    height_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height);
-   radeon_enc_code_fixed_bits(enc, height_bits - 1, 4);
+   radeon_bs_code_fixed_bits(&bs, height_bits - 1, 4);
    /*  max_frame_width_minus_1  */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_width - 1,
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1.coded_width - 1,
                                    width_bits);
    /*  max_frame_height_minus_1  */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_height - 1,
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1.coded_height - 1,
                                    height_bits);
 
    if (!seq->seq_bits.reduced_still_picture_header)
       /*  frame_id_numbers_present_flag  */
-      radeon_enc_code_fixed_bits(enc, seq->seq_bits.frame_id_number_present_flag, 1);
+      radeon_bs_code_fixed_bits(&bs, seq->seq_bits.frame_id_number_present_flag, 1);
 
    if (seq->seq_bits.frame_id_number_present_flag) {
       /*  delta_frame_id_length_minus_2  */
-      radeon_enc_code_fixed_bits(enc, seq->delta_frame_id_length - 2, 4);
+      radeon_bs_code_fixed_bits(&bs, seq->delta_frame_id_length - 2, 4);
       /*  additional_frame_id_length_minus_1  */
-      radeon_enc_code_fixed_bits(enc, seq->additional_frame_id_length - 1, 3);
+      radeon_bs_code_fixed_bits(&bs, seq->additional_frame_id_length - 1, 3);
    }
 
    /*  use_128x128_superblock  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(&bs, 0, 1);
    /*  enable_filter_intra  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(&bs, 0, 1);
    /*  enable_intra_edge_filter  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(&bs, 0, 1);
 
    if (!seq->seq_bits.reduced_still_picture_header) {
       /*  enable_interintra_compound  */
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(&bs, 0, 1);
       /*  enable_masked_compound  */
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(&bs, 0, 1);
       /*  enable_warped_motion  */
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(&bs, 0, 1);
       /*  enable_dual_filter  */
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(&bs, 0, 1);
       /*  enable_order_hint  */
-      radeon_enc_code_fixed_bits(enc, seq->seq_bits.enable_order_hint, 1);
+      radeon_bs_code_fixed_bits(&bs, seq->seq_bits.enable_order_hint, 1);
 
       if (seq->seq_bits.enable_order_hint) {
          /*  enable_jnt_comp  */
-         radeon_enc_code_fixed_bits(enc, 0, 1);
+         radeon_bs_code_fixed_bits(&bs, 0, 1);
          /*  enable_ref_frame_mvs  */
-         radeon_enc_code_fixed_bits(enc, 0, 1);
+         radeon_bs_code_fixed_bits(&bs, 0, 1);
       }
 
       /*  seq_choose_screen_content_tools  */
-      radeon_enc_code_fixed_bits(enc, enc->enc_pic.disable_screen_content_tools ? 0 : 1, 1);
+      radeon_bs_code_fixed_bits(&bs, enc->enc_pic.disable_screen_content_tools ? 0 : 1, 1);
       if (enc->enc_pic.disable_screen_content_tools)
          /*  seq_force_screen_content_tools  */
-         radeon_enc_code_fixed_bits(enc, 0, 1);
+         radeon_bs_code_fixed_bits(&bs, 0, 1);
       else
          /*  seq_choose_integer_mv  */
-         radeon_enc_code_fixed_bits(enc, 1, 1);
+         radeon_bs_code_fixed_bits(&bs, 1, 1);
 
       if (seq->seq_bits.enable_order_hint)
          /*  order_hint_bits_minus_1  */
-         radeon_enc_code_fixed_bits(enc, seq->order_hint_bits - 1, 3);
+         radeon_bs_code_fixed_bits(&bs, seq->order_hint_bits - 1, 3);
    }
 
    /*  enable_superres  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(&bs, 0, 1);
    /*  enable_cdef  */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.cdef_mode ? 1 : 0, 1);
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1_spec_misc.cdef_mode ? 1 : 0, 1);
    /*  enable_restoration  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(&bs, 0, 1);
    /*  high_bitdepth  */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.enc_output_format.output_color_bit_depth, 1);
+   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.enc_output_format.output_color_bit_depth, 1);
    /*  mono_chrome  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(&bs, 0, 1);
    /*  color_description_present_flag  */
-   radeon_enc_code_fixed_bits(enc, seq->seq_bits.color_description_present_flag, 1);
+   radeon_bs_code_fixed_bits(&bs, seq->seq_bits.color_description_present_flag, 1);
 
    if (seq->seq_bits.color_description_present_flag) {
       /*  color_primaries  */
-      radeon_enc_code_fixed_bits(enc, seq->color_config.color_primaries, 8);
+      radeon_bs_code_fixed_bits(&bs, seq->color_config.color_primaries, 8);
       /*  transfer_characteristics  */
-      radeon_enc_code_fixed_bits(enc, seq->color_config.transfer_characteristics, 8);
+      radeon_bs_code_fixed_bits(&bs, seq->color_config.transfer_characteristics, 8);
       /*  matrix_coefficients  */
-      radeon_enc_code_fixed_bits(enc, seq->color_config.matrix_coefficients, 8);
+      radeon_bs_code_fixed_bits(&bs, seq->color_config.matrix_coefficients, 8);
    }
    /*  color_range  */
-   radeon_enc_code_fixed_bits(enc, seq->color_config.color_range, 1);
+   radeon_bs_code_fixed_bits(&bs, seq->color_config.color_range, 1);
    /*  chroma_sample_position  */
-   radeon_enc_code_fixed_bits(enc, seq->color_config.chroma_sample_position, 2);
+   radeon_bs_code_fixed_bits(&bs, seq->color_config.chroma_sample_position, 2);
    /*  separate_uv_delta_q  */
    bool separate_delta_q = false;
-   radeon_enc_code_fixed_bits(enc, !!(separate_delta_q), 1);
+   radeon_bs_code_fixed_bits(&bs, !!(separate_delta_q), 1);
    /*  film_grain_params_present  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(&bs, 0, 1);
 
    /*  trailing_one_bit  */
-   radeon_enc_code_fixed_bits(enc, 1, 1);
-   radeon_enc_byte_align(enc);
+   radeon_bs_code_fixed_bits(&bs, 1, 1);
+   radeon_bs_byte_align(&bs);
 
-   obu_size = (uint32_t)(&enc->bits_buf[enc->bits_buf_pos] - size_offset - 1);
+   obu_size = (uint32_t)(&out[bs.bits_output / 8] - size_offset - 1);
    radeon_enc_code_leb128(size_offset, obu_size, 1);
 
-   return enc->bits_buf_pos;
+   return bs.bits_output / 8;
 }
 
-void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_header)
+void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header)
 {
    uint32_t i;
    bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
@@ -386,53 +386,53 @@ void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_h
    bool error_resilient_mode = false;
    struct pipe_av1_enc_picture_desc *av1 = enc->enc_pic.av1.desc;
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
 
-   radeon_enc_av1_obu_header(enc, obu_type);
+   radeon_enc_av1_obu_header(enc, bs, obu_type);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
 
    /*  uncompressed_header() */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
 
    if (!av1->seq.seq_bits.reduced_still_picture_header) {
-      radeon_enc_code_fixed_bits(enc, 0, 1); /* show_existing_frame */
+      radeon_bs_code_fixed_bits(bs, 0, 1); /* show_existing_frame */
       /*  frame_type  */
-      radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_type, 2);
+      radeon_bs_code_fixed_bits(bs, enc->enc_pic.frame_type, 2);
       /*  show_frame  */
-      radeon_enc_code_fixed_bits(enc, av1->show_frame, 1);
+      radeon_bs_code_fixed_bits(bs, av1->show_frame, 1);
       if (!av1->show_frame)
          /*  showable_frame  */
-         radeon_enc_code_fixed_bits(enc, av1->showable_frame, 1);
+         radeon_bs_code_fixed_bits(bs, av1->showable_frame, 1);
 
       if ((enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH) ||
             (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY && av1->show_frame))
          error_resilient_mode = true;
       else {
          /*  error_resilient_mode  */
-         radeon_enc_code_fixed_bits(enc, enc->enc_pic.enable_error_resilient_mode ? 1 : 0, 1);
+         radeon_bs_code_fixed_bits(bs, enc->enc_pic.enable_error_resilient_mode ? 1 : 0, 1);
          error_resilient_mode = enc->enc_pic.enable_error_resilient_mode;
       }
    }
 
    /*  disable_cdf_update  */
-   radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_cdf_update ? 1 : 0, 1);
+   radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1_spec_misc.disable_cdf_update ? 1 : 0, 1);
 
    bool allow_screen_content_tools = false;
    if (av1->seq.seq_bits.reduced_still_picture_header || !enc->enc_pic.disable_screen_content_tools) {
       /*  allow_screen_content_tools  */
       allow_screen_content_tools = enc->enc_pic.av1_spec_misc.palette_mode_enable ||
                                    enc->enc_pic.force_integer_mv;
-      radeon_enc_code_fixed_bits(enc, allow_screen_content_tools ? 1 : 0, 1);
+      radeon_bs_code_fixed_bits(bs, allow_screen_content_tools ? 1 : 0, 1);
    }
 
    if (allow_screen_content_tools)
       /*  force_integer_mv  */
-      radeon_enc_code_fixed_bits(enc, enc->enc_pic.force_integer_mv ? 1 : 0, 1);
+      radeon_bs_code_fixed_bits(bs, enc->enc_pic.force_integer_mv ? 1 : 0, 1);
 
    if (av1->seq.seq_bits.frame_id_number_present_flag)
       /*  current_frame_id  */
-      radeon_enc_code_fixed_bits(enc, av1->current_frame_id,
+      radeon_bs_code_fixed_bits(bs, av1->current_frame_id,
                                  av1->seq.delta_frame_id_length + av1->seq.additional_frame_id_length);
 
    bool frame_size_override = false;
@@ -441,176 +441,179 @@ void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_h
    else if (!av1->seq.seq_bits.reduced_still_picture_header) {
       /*  frame_size_override_flag  */
       frame_size_override = false;
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(bs, 0, 1);
    }
 
    if (av1->seq.seq_bits.enable_order_hint)
       /*  order_hint  */
-      radeon_enc_code_fixed_bits(enc, av1->order_hint, av1->seq.order_hint_bits);
+      radeon_bs_code_fixed_bits(bs, av1->order_hint, av1->seq.order_hint_bits);
 
    if (!frame_is_intra && !error_resilient_mode)
       /*  primary_ref_frame  */
-      radeon_enc_code_fixed_bits(enc, av1->primary_ref_frame, 3);
+      radeon_bs_code_fixed_bits(bs, av1->primary_ref_frame, 3);
 
    if ((enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SWITCH) &&
        (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_KEY || !av1->show_frame))
       /*  refresh_frame_flags  */
-      radeon_enc_code_fixed_bits(enc, av1->refresh_frame_flags, 8);
+      radeon_bs_code_fixed_bits(bs, av1->refresh_frame_flags, 8);
 
    if ((!frame_is_intra || av1->refresh_frame_flags != 0xff) &&
                   error_resilient_mode && av1->seq.seq_bits.enable_order_hint)
       for (i = 0; i < RENCODE_AV1_NUM_REF_FRAMES; i++)
          /*  ref_order_hint  */
-         radeon_enc_code_fixed_bits(enc, av1->ref_order_hint[i], av1->seq.order_hint_bits);
+         radeon_bs_code_fixed_bits(bs, av1->ref_order_hint[i], av1->seq.order_hint_bits);
 
    if (frame_is_intra) {
       /*  render_and_frame_size_different  */
-      radeon_enc_code_fixed_bits(enc, av1->enable_render_size ? 1 : 0, 1);
+      radeon_bs_code_fixed_bits(bs, av1->enable_render_size ? 1 : 0, 1);
       if (av1->enable_render_size) {
          /*  render_width_minus_1  */
-         radeon_enc_code_fixed_bits(enc, av1->render_width_minus_1, 16);
+         radeon_bs_code_fixed_bits(bs, av1->render_width_minus_1, 16);
          /*  render_height_minus_1  */
-         radeon_enc_code_fixed_bits(enc, av1->render_height_minus_1, 16);
+         radeon_bs_code_fixed_bits(bs, av1->render_height_minus_1, 16);
       }
       if (!enc->enc_pic.disable_screen_content_tools &&
             (enc->enc_pic.av1_spec_misc.palette_mode_enable || enc->enc_pic.force_integer_mv))
          /*  allow_intrabc  */
-         radeon_enc_code_fixed_bits(enc, 0, 1);
+         radeon_bs_code_fixed_bits(bs, 0, 1);
    } else {
       if (av1->seq.seq_bits.enable_order_hint)
          /*  frame_refs_short_signaling  */
-         radeon_enc_code_fixed_bits(enc, av1->frame_refs_short_signaling, 1);
+         radeon_bs_code_fixed_bits(bs, av1->frame_refs_short_signaling, 1);
       if (av1->frame_refs_short_signaling) {
-         radeon_enc_code_fixed_bits(enc, av1->last_frame_idx, 3);
-         radeon_enc_code_fixed_bits(enc, av1->gold_frame_idx, 3);
+         radeon_bs_code_fixed_bits(bs, av1->last_frame_idx, 3);
+         radeon_bs_code_fixed_bits(bs, av1->gold_frame_idx, 3);
       }
       for (i = 0; i < RENCODE_AV1_REFS_PER_FRAME; i++) {
          /*  ref_frame_idx[i]  */
-         radeon_enc_code_fixed_bits(enc, av1->ref_frame_idx[i], 3);
+         radeon_bs_code_fixed_bits(bs, av1->ref_frame_idx[i], 3);
          if (av1->seq.seq_bits.frame_id_number_present_flag)
             /*  delta_frame_id_minus_1[i]  */
-            radeon_enc_code_fixed_bits(enc, av1->delta_frame_id_minus_1[i], av1->seq.delta_frame_id_length);
+            radeon_bs_code_fixed_bits(bs, av1->delta_frame_id_minus_1[i], av1->seq.delta_frame_id_length);
       }
 
       if (frame_size_override && !error_resilient_mode)
          /*  found_ref  */
-         radeon_enc_code_fixed_bits(enc, 1, 1);
+         radeon_bs_code_fixed_bits(bs, 1, 1);
       else {
          if(frame_size_override) {
             /*  frame_width_minus_1  */
             uint32_t used_bits =
                      radeon_enc_value_bits(enc->enc_pic.av1.coded_width - 1);
-            radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_width - 1,
-                                            used_bits);
+            radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.coded_width - 1,
+                                          used_bits);
             /*  frame_height_minus_1  */
             used_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height - 1);
-            radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_height - 1,
-                                            used_bits);
+            radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.coded_height - 1,
+                                          used_bits);
          }
          /*  render_and_frame_size_different  */
-         radeon_enc_code_fixed_bits(enc, av1->enable_render_size ? 1 : 0, 1);
+         radeon_bs_code_fixed_bits(bs, av1->enable_render_size ? 1 : 0, 1);
          if (av1->enable_render_size) {
             /*  render_width_minus_1  */
-            radeon_enc_code_fixed_bits(enc, av1->render_width_minus_1, 16);
+            radeon_bs_code_fixed_bits(bs, av1->render_width_minus_1, 16);
             /*  render_height_minus_1  */
-            radeon_enc_code_fixed_bits(enc, av1->render_height_minus_1, 16);
+            radeon_bs_code_fixed_bits(bs, av1->render_height_minus_1, 16);
          }
       }
 
       if (enc->enc_pic.disable_screen_content_tools || !enc->enc_pic.force_integer_mv)
          /*  allow_high_precision_mv  */
-         radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV, 0);
+         radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV, 0);
 
       /*  read_interpolation_filter  */
-      radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER, 0);
+      radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER, 0);
 
-      radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+      radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
       /*  is_motion_mode_switchable  */
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(bs, 0, 1);
    }
 
    if (!av1->seq.seq_bits.reduced_still_picture_header && !enc->enc_pic.av1_spec_misc.disable_cdf_update)
       /*  disable_frame_end_update_cdf  */
-      radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
+      radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
 }
 
-static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_header)
+static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header)
 {
    bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
                          enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
 
-   radeon_enc_av1_frame_header_common(enc, frame_header);
+   radeon_enc_av1_frame_header_common(enc, bs, frame_header);
 
    /*  tile_info  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
    /*  quantization_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
    /*  segmentation_enable  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+   radeon_bs_code_fixed_bits(bs, 0, 1);
    /*  delta_q_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
    /*  delta_lf_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
    /*  loop_filter_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
    /*  cdef_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
    /*  lr_params  */
    /*  read_tx_mode  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
 
    if (!frame_is_intra)
       /*  reference_select  */
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(bs, 0, 1);
 
    /*  reduced_tx_set  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(bs, 0, 1);
 
    if (!frame_is_intra)
       for (uint32_t ref = 1 /*LAST_FRAME*/; ref <= 7 /*ALTREF_FRAME*/; ref++)
          /*  is_global  */
-         radeon_enc_code_fixed_bits(enc, 0, 1);
+         radeon_bs_code_fixed_bits(bs, 0, 1);
    /*  film_grain_params() */
 }
 
-void radeon_enc_av1_tile_group(struct radeon_encoder *enc)
+void radeon_enc_av1_tile_group(struct radeon_encoder *enc, struct radeon_bitstream *bs)
 {
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
-                                           RENCODE_OBU_START_TYPE_TILE_GROUP);
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
+                                               RENCODE_OBU_START_TYPE_TILE_GROUP);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
 
-   radeon_enc_av1_obu_header(enc, RENCODE_OBU_TYPE_TILE_GROUP);
+   radeon_enc_av1_obu_header(enc, bs, RENCODE_OBU_TYPE_TILE_GROUP);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
 }
 
 static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
 {
+   struct radeon_bitstream bs;
    bool frame_header = !enc->enc_pic.is_obu_frame;
-   radeon_enc_reset(enc);
+
+   radeon_bs_reset(&bs, NULL, &enc->cs);
+
    RADEON_ENC_BEGIN(enc->cmd.bitstream_instruction_av1);
 
-   radeon_enc_av1_bs_instruction_type(enc,
+   radeon_enc_av1_bs_instruction_type(enc, &bs,
          RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
             frame_header ? RENCODE_OBU_START_TYPE_FRAME_HEADER
                          : RENCODE_OBU_START_TYPE_FRAME);
 
-   radeon_enc_av1_frame_header(enc, frame_header);
+   radeon_enc_av1_frame_header(enc, &bs, frame_header);
 
    if (!frame_header)
-      radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
+      radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
+   radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
 
    if (frame_header)
-      radeon_enc_av1_tile_group(enc);
+      radeon_enc_av1_tile_group(enc, &bs);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
+   radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
    RADEON_ENC_END();
 }
 
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c
index 58e334c49d8..9757fe30dbb 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c
@@ -722,7 +722,7 @@ static void radeon_enc_tile_config_av1(struct radeon_encoder *enc)
    RADEON_ENC_END();
 }
 
-static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
+static void radeon_enc_av1_tile_info(struct radeon_encoder *enc, struct radeon_bitstream *bs)
 {
    rvcn_enc_av1_tile_config_t *p_config = &enc->enc_pic.av1_tile_config;
    uint32_t i = 0;
@@ -738,17 +738,17 @@ static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
    TileColsLog2 = util_logbase2_ceil(p_config->num_tile_cols);
    TileRowsLog2 = util_logbase2_ceil(p_config->num_tile_rows);
 
-   radeon_enc_code_fixed_bits(enc, p_config->uniform_tile_spacing, 1);
+   radeon_bs_code_fixed_bits(bs, p_config->uniform_tile_spacing, 1);
    if (p_config->uniform_tile_spacing) {
       for ( i = minLog2TileCols; i < TileColsLog2; i++)
-         radeon_enc_code_fixed_bits(enc, 1, 1);
+         radeon_bs_code_fixed_bits(bs, 1, 1);
 
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(bs, 0, 1);
 
       for ( i = minLog2Tiles - TileColsLog2; i < TileRowsLog2; i++)
-         radeon_enc_code_fixed_bits(enc, 1, 1);
+         radeon_bs_code_fixed_bits(bs, 1, 1);
 
-      radeon_enc_code_fixed_bits(enc, 0, 1);
+      radeon_bs_code_fixed_bits(bs, 0, 1);
    } else {
       uint32_t widestTileSb = 0;
       uint32_t maxWidthInSb = 0;
@@ -758,7 +758,7 @@ static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
 
       for (i = 0; i < p_config->num_tile_cols; i++) {
          maxWidthInSb = MIN2(sbCols - startSb, maxTileWidthSb);
-         radeon_enc_code_ns(enc, p_config->tile_widths[i] - 1, maxWidthInSb);
+         radeon_bs_code_ns(bs, p_config->tile_widths[i] - 1, maxWidthInSb);
          startSb += p_config->tile_widths[i];
          widestTileSb = MAX2( p_config->tile_widths[i], widestTileSb);
       }
@@ -773,52 +773,52 @@ static void radeon_enc_av1_tile_info(struct radeon_encoder *enc)
 
       for (i = 0; i < p_config->num_tile_rows; i++) {
          maxHeightInSb = MIN2(sbRows - startSb, maxTileHeightSb);
-         radeon_enc_code_ns(enc, p_config->tile_height[i] - 1, maxHeightInSb);
+         radeon_bs_code_ns(bs, p_config->tile_height[i] - 1, maxHeightInSb);
          startSb += p_config->tile_height[i];
       }
    }
 
    if (TileColsLog2 > 0 || TileRowsLog2 > 0) {
-      radeon_enc_av1_bs_instruction_type(enc, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID, 0);
+      radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_CONTEXT_UPDATE_TILE_ID, 0);
 
-      radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+      radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
 
-      radeon_enc_code_fixed_bits(enc, p_config->tile_size_bytes_minus_1, 2);
+      radeon_bs_code_fixed_bits(bs, p_config->tile_size_bytes_minus_1, 2);
    }
 }
 
-static void radeon_enc_av1_write_delta_q(struct radeon_encoder *enc, int32_t q)
+static void radeon_enc_av1_write_delta_q(struct radeon_bitstream *bs, int32_t q)
 {
-   radeon_enc_code_fixed_bits(enc, !!(q), 1);
+   radeon_bs_code_fixed_bits(bs, !!(q), 1);
 
    if (q)
-      radeon_enc_code_fixed_bits(enc, q, ( 1 + 6 ));
+      radeon_bs_code_fixed_bits(bs, q, ( 1 + 6 ));
 }
 
-static void radeon_enc_av1_quantization_params(struct radeon_encoder *enc)
+static void radeon_enc_av1_quantization_params(struct radeon_encoder *enc, struct radeon_bitstream *bs)
 {
    rvcn_enc_av1_spec_misc_t *p = &enc->enc_pic.av1_spec_misc;
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V5_AV1_BITSTREAM_INSTRUCTION_BASE_Q_IDX, 0);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
 
-   radeon_enc_av1_write_delta_q(enc, p->delta_q_y_dc);
+   radeon_enc_av1_write_delta_q(bs, p->delta_q_y_dc);
 
    /* only support multi-planes at the time */
    if (p->separate_delta_q)
-      radeon_enc_code_fixed_bits(enc, 1, 1);
+      radeon_bs_code_fixed_bits(bs, 1, 1);
 
-   radeon_enc_av1_write_delta_q(enc, p->delta_q_u_dc);
-   radeon_enc_av1_write_delta_q(enc, p->delta_q_u_ac);
+   radeon_enc_av1_write_delta_q(bs, p->delta_q_u_dc);
+   radeon_enc_av1_write_delta_q(bs, p->delta_q_u_ac);
 
    if (p->separate_delta_q) {
-      radeon_enc_av1_write_delta_q(enc, p->delta_q_v_dc);
-      radeon_enc_av1_write_delta_q(enc, p->delta_q_v_ac);
+      radeon_enc_av1_write_delta_q(bs, p->delta_q_v_dc);
+      radeon_enc_av1_write_delta_q(bs, p->delta_q_v_ac);
    }
 
    /* using qmatrix */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(bs, 0, 1);
 }
 
 static int32_t radeon_enc_av1_get_relative_dist(struct radeon_encoder *enc, uint32_t a, uint32_t b)
@@ -886,74 +886,76 @@ bool radeon_enc_av1_skip_mode_allowed(struct radeon_encoder *enc, uint32_t frame
    return true;
 }
 
-static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_header)
+static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header)
 {
    bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
                          enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
 
-   radeon_enc_av1_frame_header_common(enc, frame_header);
+   radeon_enc_av1_frame_header_common(enc, bs, frame_header);
 
    /*  tile_info  */
-   radeon_enc_av1_tile_info(enc);
+   radeon_enc_av1_tile_info(enc, bs);
    /*  quantization_params  */
-   radeon_enc_av1_quantization_params(enc);
+   radeon_enc_av1_quantization_params(enc, bs);
    /*  segmentation_enable  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(bs, 0, 1);
    /*  delta_q_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
    /*  delta_lf_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
    /*  loop_filter_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
    /*  cdef_params  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
    /*  lr_params  */
    /*  read_tx_mode  */
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
+   radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
 
    if (!frame_is_intra)
       /*  reference_select  */
-      radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.compound, 1);
+      radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.compound, 1);
 
    if (enc->enc_pic.av1.skip_mode_allowed)
       /*  skip_mode_present  */
-      radeon_enc_code_fixed_bits(enc, !enc->enc_pic.av1_spec_misc.disallow_skip_mode, 1);
+      radeon_bs_code_fixed_bits(bs, !enc->enc_pic.av1_spec_misc.disallow_skip_mode, 1);
 
    /*  reduced_tx_set  */
-   radeon_enc_code_fixed_bits(enc, 0, 1);
+   radeon_bs_code_fixed_bits(bs, 0, 1);
 
    if (!frame_is_intra)
       for (uint32_t ref = 1 /*LAST_FRAME*/; ref <= 7 /*ALTREF_FRAME*/; ref++)
          /*  is_global  */
-         radeon_enc_code_fixed_bits(enc, 0, 1);
+         radeon_bs_code_fixed_bits(bs, 0, 1);
    /*  film_grain_params() */
 }
 
 static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
 {
    bool frame_header = !enc->enc_pic.is_obu_frame;
+   struct radeon_bitstream bs;
+
+   radeon_bs_reset(&bs, NULL, &enc->cs);
 
-   radeon_enc_reset(enc);
    RADEON_ENC_BEGIN(enc->cmd.bitstream_instruction_av1);
 
-   radeon_enc_av1_bs_instruction_type(enc,
+   radeon_enc_av1_bs_instruction_type(enc, &bs,
          RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
             frame_header ? RENCODE_OBU_START_TYPE_FRAME_HEADER
                          : RENCODE_OBU_START_TYPE_FRAME);
 
-   radeon_enc_av1_frame_header(enc, frame_header);
+   radeon_enc_av1_frame_header(enc, &bs, frame_header);
 
    if (!frame_header)
-      radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
+      radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
+   radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
 
    if (frame_header)
-      radeon_enc_av1_tile_group(enc);
+      radeon_enc_av1_tile_group(enc, &bs);
 
-   radeon_enc_av1_bs_instruction_type(enc, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
+   radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
    RADEON_ENC_END();
 }