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radeon/llvm: Remove SILowerShaderInstructions.cpp

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This commit is contained in:
Tom Stellard
2012-05-10 15:31:42 -04:00
parent f8e9c29020
commit 628e5b208a
4 changed files with 0 additions and 81 deletions
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src/gallium/drivers/radeon/AMDGPU.h
-1
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@@ -26,7 +26,6 @@ FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
// SI Passes
FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
FunctionPass *createSILowerShaderInstructionsPass(TargetMachine &tm);
FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm);
FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
-1
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@@ -130,7 +130,6 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
PM->add(createR600LowerInstructionsPass(*TM));
} else {
PM->add(createSILowerShaderInstructionsPass(*TM));
PM->add(createSIAssignInterpRegsPass(*TM));
}
PM->add(createAMDGPULowerInstructionsPass(*TM));
src/gallium/drivers/radeon/Makefile.sources
-1
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@@ -54,7 +54,6 @@ CPP_SOURCES := \
SICodeEmitter.cpp \
SIInstrInfo.cpp \
SIISelLowering.cpp \
SILowerShaderInstructions.cpp \
SIMachineFunctionInfo.cpp \
SIPropagateImmReads.cpp \
SIRegisterInfo.cpp \
src/gallium/drivers/radeon/SILowerShaderInstructions.cpp
-78
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@@ -1,78 +0,0 @@
//===-- SILowerShaderInstructions.cpp - Pass for lowering shader instructions -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
//
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
namespace {
class SILowerShaderInstructionsPass : public MachineFunctionPass {
private:
static char ID;
TargetMachine &TM;
MachineRegisterInfo * MRI;
public:
SILowerShaderInstructionsPass(TargetMachine &tm) :
MachineFunctionPass(ID), TM(tm) { }
bool runOnMachineFunction(MachineFunction &MF);
const char *getPassName() const { return "SI Lower Shader Instructions"; }
void lowerSET_M0(MachineInstr &MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I);
};
} /* End anonymous namespace */
char SILowerShaderInstructionsPass::ID = 0;
FunctionPass *llvm::createSILowerShaderInstructionsPass(TargetMachine &tm) {
return new SILowerShaderInstructionsPass(tm);
}
bool SILowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
{
MRI = &MF.getRegInfo();
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
I != MBB.end(); I = Next, Next = llvm::next(I) ) {
MachineInstr &MI = *I;
switch (MI.getOpcode()) {
case AMDIL::SET_M0:
lowerSET_M0(MI, MBB, I);
break;
default: continue;
}
MI.removeFromParent();
}
}
return false;
}
void SILowerShaderInstructionsPass::lowerSET_M0(MachineInstr &MI,
MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
{
const struct TargetInstrInfo * TII = TM.getInstrInfo();
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::S_MOV_IMM_I32))
.addReg(AMDIL::M0)
.addOperand(MI.getOperand(1));
}