radeonsi/llvm: Move lowering of RETURN to ConvertToISA pass
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@@ -107,6 +107,8 @@ unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
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{
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switch (AMDILopcode) {
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case AMDIL::MAD_f32: return AMDIL::V_MAD_LEGACY_F32;
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//XXX We need a better way of detecting end of program
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case AMDIL::RETURN: return AMDIL::S_ENDPGM;
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default: return AMDGPUInstrInfo::getISAOpcode(AMDILopcode);
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}
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}
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@@ -35,7 +35,6 @@ namespace {
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const char *getPassName() const { return "SI Lower Shader Instructions"; }
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void lowerRETURN(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
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void lowerSET_M0(MachineInstr &MI, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I);
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};
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@@ -57,9 +56,6 @@ bool SILowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
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I != MBB.end(); I = Next, Next = llvm::next(I) ) {
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MachineInstr &MI = *I;
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switch (MI.getOpcode()) {
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case AMDIL::RETURN:
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lowerRETURN(MBB, I);
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break;
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case AMDIL::SET_M0:
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lowerSET_M0(MI, MBB, I);
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break;
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@@ -72,13 +68,6 @@ bool SILowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
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return false;
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}
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void SILowerShaderInstructionsPass::lowerRETURN(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I)
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{
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const struct TargetInstrInfo * TII = TM.getInstrInfo();
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BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::S_ENDPGM));
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}
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void SILowerShaderInstructionsPass::lowerSET_M0(MachineInstr &MI,
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MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
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{
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