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intel/brw/xe2+: Use phys_nr and phys_subnr in DPAS encoding

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Suggested-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
This commit is contained in:
Ian Romanick
2024-03-26 19:46:02 -07:00
committed by Marge Bot
parent 6d85f7129a
commit 5e9c01dfe4
1 changed files with 8 additions and 8 deletions
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src/intel/compiler/brw_eu_emit.c
+8 -8
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@@ -787,8 +787,8 @@ brw_dpas_three_src(struct brw_codegen *p, enum gfx12_systolic_depth opcode,
assert(dest.file == BRW_GENERAL_REGISTER_FILE);
brw_inst_set_dpas_3src_dst_reg_file(devinfo, inst,
BRW_GENERAL_REGISTER_FILE);
brw_inst_set_dpas_3src_dst_reg_nr(devinfo, inst, dest.nr);
brw_inst_set_dpas_3src_dst_subreg_nr(devinfo, inst, dest.subnr);
brw_inst_set_dpas_3src_dst_reg_nr(devinfo, inst, phys_nr(devinfo, dest));
brw_inst_set_dpas_3src_dst_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest));
if (brw_reg_type_is_floating_point(dest.type)) {
brw_inst_set_dpas_3src_exec_type(devinfo, inst,
@@ -811,21 +811,21 @@ brw_dpas_three_src(struct brw_codegen *p, enum gfx12_systolic_depth opcode,
src0.nr == BRW_ARF_NULL));
brw_inst_set_dpas_3src_src0_reg_file(devinfo, inst, src0.file);
brw_inst_set_dpas_3src_src0_reg_nr(devinfo, inst, src0.nr);
brw_inst_set_dpas_3src_src0_subreg_nr(devinfo, inst, src0.subnr);
brw_inst_set_dpas_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0));
brw_inst_set_dpas_3src_src0_subreg_nr(devinfo, inst, phys_subnr(devinfo, src0));
assert(src1.file == BRW_GENERAL_REGISTER_FILE);
brw_inst_set_dpas_3src_src1_reg_file(devinfo, inst, src1.file);
brw_inst_set_dpas_3src_src1_reg_nr(devinfo, inst, src1.nr);
brw_inst_set_dpas_3src_src1_subreg_nr(devinfo, inst, src1.subnr);
brw_inst_set_dpas_3src_src1_reg_nr(devinfo, inst, phys_nr(devinfo, src1));
brw_inst_set_dpas_3src_src1_subreg_nr(devinfo, inst, phys_subnr(devinfo, src1));
brw_inst_set_dpas_3src_src1_subbyte(devinfo, inst, BRW_SUB_BYTE_PRECISION_NONE);
assert(src2.file == BRW_GENERAL_REGISTER_FILE);
brw_inst_set_dpas_3src_src2_reg_file(devinfo, inst, src2.file);
brw_inst_set_dpas_3src_src2_reg_nr(devinfo, inst, src2.nr);
brw_inst_set_dpas_3src_src2_subreg_nr(devinfo, inst, src2.subnr);
brw_inst_set_dpas_3src_src2_reg_nr(devinfo, inst, phys_nr(devinfo, src2));
brw_inst_set_dpas_3src_src2_subreg_nr(devinfo, inst, phys_subnr(devinfo, src2));
brw_inst_set_dpas_3src_src2_subbyte(devinfo, inst, BRW_SUB_BYTE_PRECISION_NONE);
return inst;