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intel/brw/xe2+: DPAS must be SIMD16 now

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Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
This commit is contained in:
Ian Romanick
2024-03-25 10:23:49 -07:00
committed by Marge Bot
parent a8115221e5
commit 6d85f7129a
3 changed files with 13 additions and 8 deletions
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src/intel/compiler/brw_eu_validate.c
+8 -3
View File
@@ -2161,10 +2161,15 @@ instruction_restrictions(const struct brw_isa_info *isa,
const unsigned ops_per_chan =
MAX2(1, 32 / MAX2(src1_bits_per_element, src2_bits_per_element));
ERROR_IF(brw_inst_exec_size(devinfo, inst) != BRW_EXECUTE_8,
"DPAS execution size must be 8.");
if (devinfo->ver < 20) {
ERROR_IF(brw_inst_exec_size(devinfo, inst) != BRW_EXECUTE_8,
"DPAS execution size must be 8.");
} else {
ERROR_IF(brw_inst_exec_size(devinfo, inst) != BRW_EXECUTE_16,
"DPAS execution size must be 16.");
}
const unsigned exec_size = 8;
const unsigned exec_size = devinfo->ver < 20 ? 8 : 16;
const unsigned dst_subnr = brw_inst_dpas_3src_dst_subreg_nr(devinfo, inst);
const unsigned src0_subnr = brw_inst_dpas_3src_src0_subreg_nr(devinfo, inst);
src/intel/compiler/brw_fs_builder.h
+1 -1
View File
@@ -771,7 +771,7 @@ namespace brw {
DPAS(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1, const fs_reg &src2,
unsigned sdepth, unsigned rcount) const
{
assert(_dispatch_width == 8);
assert(_dispatch_width == 8 * reg_unit(shader->devinfo));
assert(sdepth == 8);
assert(rcount == 1 || rcount == 2 || rcount == 4 || rcount == 8);
src/intel/compiler/brw_fs_nir.cpp
+4 -4
View File
@@ -4519,8 +4519,8 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
fs_reg src0 = retype(get_nir_src(ntb, instr->src[0]), dest_type);
const fs_reg dest_hf = dest;
fs_builder bld8 = bld.exec_all().group(8, 0);
fs_builder bld16 = bld.exec_all().group(16, 0);
fs_builder bldn = devinfo->ver >= 20 ? bld16 : bld.exec_all().group(8, 0);
/* DG2 cannot have the destination or source 0 of DPAS be float16. It is
* still advantageous to support these formats for memory and bandwidth
@@ -4530,12 +4530,12 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
*/
if (devinfo->verx10 == 125 && dest_type == BRW_REGISTER_TYPE_HF &&
!s.compiler->lower_dpas) {
dest = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount);
dest = bldn.vgrf(BRW_REGISTER_TYPE_F, rcount);
if (src0.file != ARF) {
const fs_reg src0_hf = src0;
src0 = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount);
src0 = bldn.vgrf(BRW_REGISTER_TYPE_F, rcount);
for (unsigned i = 0; i < 4; i++) {
bld16.MOV(byte_offset(src0, REG_SIZE * i * 2),
@@ -4546,7 +4546,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
}
}
bld8.DPAS(dest,
bldn.DPAS(dest,
src0,
retype(get_nir_src(ntb, instr->src[2]), src_type),
retype(get_nir_src(ntb, instr->src[1]), src_type),