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brw: fix invalid sparse bitfield offset computation

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dest_size is the number of outputs to be provided into the IR, but the
location of the sparse bitfield in the dst temporary SEND destination
might be different (shorter due to masking of unused components
computed above).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14094
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37876>
This commit is contained in:
Lionel Landwerlin
2025-10-14 23:13:13 +03:00
committed by Marge Bot
parent a7b7ebf08b
commit 49226692e5
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw/brw_from_nir.cpp
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@@ -7755,7 +7755,7 @@ brw_from_nir_emit_texture(nir_to_brw_state &ntb,
/* The residency bits are only in the first component. */
if (instr->is_sparse) {
nir_dest[dest_size - 1] =
component(offset(dst, bld, dest_size - 1), 0);
component(offset(dst, bld, dest_comp), 0);
}
bld.LOAD_PAYLOAD(nir_def_reg, nir_dest, dest_size, 0);