intel/brw: Add TGL_PIPE_SCALAR value

Add the enum value for the (in-order) scalar pipe.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32236>
This commit is contained in:
Caio Oliveira
2024-11-19 13:06:35 -08:00
committed by Marge Bot
parent 7acd84da51
commit 46e9fe6981
3 changed files with 9 additions and 2 deletions
+2 -1
View File
@@ -1879,7 +1879,8 @@ swsb(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
swsb.pipe == TGL_PIPE_INT ? "I" :
swsb.pipe == TGL_PIPE_LONG ? "L" :
swsb.pipe == TGL_PIPE_ALL ? "A" :
swsb.pipe == TGL_PIPE_MATH ? "M" : "" ),
swsb.pipe == TGL_PIPE_MATH ? "M" :
swsb.pipe == TGL_PIPE_SCALAR ? "S" : "" ),
swsb.regdist);
if (swsb.mode)
format(file, " $%d%s", swsb.sbid,
+5
View File
@@ -895,6 +895,9 @@ operator|=(tgl_sbid_mode &x, tgl_sbid_mode y)
* the hardware to infer the pipeline based on the source types of the
* instruction. TGL_PIPE_ALL can be used when synchronization with all ALU
* pipelines is intended.
*
* Xe3 adds TGL_PIPE_SCALAR for a very specific use case (writing immediates
* to scalar register).
*/
enum tgl_pipe {
TGL_PIPE_NONE = 0,
@@ -902,6 +905,7 @@ enum tgl_pipe {
TGL_PIPE_INT,
TGL_PIPE_LONG,
TGL_PIPE_MATH,
TGL_PIPE_SCALAR,
TGL_PIPE_ALL
};
@@ -989,6 +993,7 @@ tgl_swsb_encode(const struct intel_device_info *devinfo,
swsb.pipe == TGL_PIPE_INT ? 0x18 :
swsb.pipe == TGL_PIPE_LONG ? 0x20 :
swsb.pipe == TGL_PIPE_MATH ? 0x28 :
swsb.pipe == TGL_PIPE_SCALAR ? 0x30 :
swsb.pipe == TGL_PIPE_ALL ? 0x8 : 0;
return pipe | swsb.regdist;
+2 -1
View File
@@ -651,7 +651,8 @@ brw_print_swsb(FILE *f, const struct intel_device_info *devinfo, const tgl_swsb
swsb.pipe == TGL_PIPE_INT ? "I" :
swsb.pipe == TGL_PIPE_LONG ? "L" :
swsb.pipe == TGL_PIPE_ALL ? "A" :
swsb.pipe == TGL_PIPE_MATH ? "M" : "" ),
swsb.pipe == TGL_PIPE_MATH ? "M" :
swsb.pipe == TGL_PIPE_SCALAR ? "S" : "" ),
swsb.regdist);
}