AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: Handle GSVS ring intrinsic correctly with LLVM.

Browse Source 
If we don't set progress to false we get a mess as a replacement is
still attempted.

Fixes: 382831c986 ("radv,nir: add intrinsics for streamout and GS copy shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19404>
This commit is contained in:
Bas Nieuwenhuizen
2022-10-30 16:31:04 +01:00
committed by Marge Bot
parent ec9d71498e
commit 45ff58cfd1
1 changed files with 3 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/amd/vulkan/radv_nir_lower_abi.c
View File

@@ -125,8 +125,10 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
replacement = load_ring(b, stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS : RING_ESGS_VS, s);
break;
case nir_intrinsic_load_ring_gsvs_amd:
if (s->use_llvm)
if (s->use_llvm) {
progress = false;
break;
}
replacement = load_ring(b, RING_GSVS_VS, s);
break;